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ixgbe: DCB, fix TX hang occurring in stress condition with PFC
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
e8e9f696
JP		 134MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
e8e9f696
JP		 172
173 kfree(adapter->vfinfo);
1cdd1ec8
GR		 174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
c7689578 285 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 292 pr_err("%-15s", rname);
dcd79aeb 293 for (j = 0; j < 8; j++)
c7689578
JP		 294 pr_cont(" %08x", regs[i*8+j]);
295 pr_cont("\n");
dcd79aeb
TI		 296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 325 pr_info("Device Name state "
dcd79aeb 326 "trans_start last_rx\n");
c7689578
JP		 327 pr_info("%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
dcd79aeb
TI		 332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 336 pr_info(" Register Name Value\n");
dcd79aeb
TI		 337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 348 for (n = 0; n < adapter->num_tx_queues; n++) {
349 tx_ring = adapter->tx_ring[n];
350 tx_buffer_info =
351 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 353 n, tx_ring->next_to_use, tx_ring->next_to_clean,
354 (u64)tx_buffer_info->dma,
355 tx_buffer_info->length,
356 tx_buffer_info->next_to_watch,
357 (u64)tx_buffer_info->time_stamp);
358 }
359
360 /* Print TX Rings */
361 if (!netif_msg_tx_done(adapter))
362 goto rx_ring_summary;
363
364 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
365
366 /* Transmit Descriptor Formats
367 *
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
375 */
376
377 for (n = 0; n < adapter->num_tx_queues; n++) {
378 tx_ring = adapter->tx_ring[n];
c7689578
JP		 379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
385
386 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 387 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
389 u0 = (struct my_u0 *)tx_desc;
c7689578 390 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 391 " %04X %3X %016llX %p", i,
392 le64_to_cpu(u0->a),
393 le64_to_cpu(u0->b),
394 (u64)tx_buffer_info->dma,
395 tx_buffer_info->length,
396 tx_buffer_info->next_to_watch,
397 (u64)tx_buffer_info->time_stamp,
398 tx_buffer_info->skb);
399 if (i == tx_ring->next_to_use &&
400 i == tx_ring->next_to_clean)
c7689578 401 pr_cont(" NTC/U\n");
dcd79aeb 402 else if (i == tx_ring->next_to_use)
c7689578 403 pr_cont(" NTU\n");
dcd79aeb 404 else if (i == tx_ring->next_to_clean)
c7689578 405 pr_cont(" NTC\n");
dcd79aeb 406 else
c7689578 407 pr_cont("\n");
dcd79aeb
TI		 408
409 if (netif_msg_pktdata(adapter) &&
410 tx_buffer_info->dma != 0)
411 print_hex_dump(KERN_INFO, "",
412 DUMP_PREFIX_ADDRESS, 16, 1,
413 phys_to_virt(tx_buffer_info->dma),
414 tx_buffer_info->length, true);
415 }
416 }
417
418 /* Print RX Rings Summary */
419rx_ring_summary:
420 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 421 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 422 for (n = 0; n < adapter->num_rx_queues; n++) {
423 rx_ring = adapter->rx_ring[n];
c7689578
JP		 424 pr_info("%5d %5X %5X\n",
425 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 426 }
427
428 /* Print RX Rings */
429 if (!netif_msg_rx_status(adapter))
430 goto exit;
431
432 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
433
434 /* Advanced Receive Descriptor (Read) Format
435 * 63 1 0
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
441 *
442 *
443 * Advanced Receive Descriptor (Write-Back) Format
444 *
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
453 */
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
c7689578
JP		 456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
c7689578 462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
465
466 for (i = 0; i < rx_ring->count; i++) {
467 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 468 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 469 u0 = (struct my_u0 *)rx_desc;
470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
471 if (staterr & IXGBE_RXD_STAT_DD) {
472 /* Descriptor Done */
c7689578 473 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 474 "%016llX ---------------- %p", i,
475 le64_to_cpu(u0->a),
476 le64_to_cpu(u0->b),
477 rx_buffer_info->skb);
478 } else {
c7689578 479 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 480 "%016llX %016llX %p", i,
481 le64_to_cpu(u0->a),
482 le64_to_cpu(u0->b),
483 (u64)rx_buffer_info->dma,
484 rx_buffer_info->skb);
485
486 if (netif_msg_pktdata(adapter)) {
487 print_hex_dump(KERN_INFO, "",
488 DUMP_PREFIX_ADDRESS, 16, 1,
489 phys_to_virt(rx_buffer_info->dma),
490 rx_ring->rx_buf_len, true);
491
492 if (rx_ring->rx_buf_len
493 < IXGBE_RXBUFFER_2048)
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(
497 rx_buffer_info->page_dma +
498 rx_buffer_info->page_offset
499 ),
500 PAGE_SIZE/2, true);
501 }
502 }
503
504 if (i == rx_ring->next_to_use)
c7689578 505 pr_cont(" NTU\n");
dcd79aeb 506 else if (i == rx_ring->next_to_clean)
c7689578 507 pr_cont(" NTC\n");
dcd79aeb 508 else
c7689578 509 pr_cont("\n");
dcd79aeb
TI		 510
511 }
512 }
513
514exit:
515 return;
516}
517
5eba3699
AV		 518static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
519{
520 u32 ctrl_ext;
521
522 /* Let firmware take over control of h/w */
523 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 525 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 526}
527
528static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
529{
530 u32 ctrl_ext;
531
532 /* Let firmware know the driver has taken over */
533 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 535 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 536}
9a799d71 537
e8e26350
PW		 538/*
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
544 *
545 */
546static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 547 u8 queue, u8 msix_vector)
9a799d71
AK		 548{
549 u32 ivar, index;
e8e26350
PW		 550 struct ixgbe_hw *hw = &adapter->hw;
551 switch (hw->mac.type) {
552 case ixgbe_mac_82598EB:
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
554 if (direction == -1)
555 direction = 0;
556 index = (((direction * 64) + queue) >> 2) & 0x1F;
557 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
558 ivar &= ~(0xFF << (8 * (queue & 0x3)));
559 ivar |= (msix_vector << (8 * (queue & 0x3)));
560 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
561 break;
562 case ixgbe_mac_82599EB:
563 if (direction == -1) {
564 /* other causes */
565 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
566 index = ((queue & 1) * 8);
567 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
568 ivar &= ~(0xFF << index);
569 ivar |= (msix_vector << index);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
571 break;
572 } else {
573 /* tx or rx causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((16 * (queue & 1)) + (8 * direction));
576 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
580 break;
581 }
582 default:
583 break;
584 }
9a799d71
AK		 585}
586
fe49f04a 587static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 588 u64 qmask)
fe49f04a
AD		 589{
590 u32 mask;
591
592 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
593 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
595 } else {
596 mask = (qmask & 0xFFFFFFFF);
597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
598 mask = (qmask >> 32);
599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
600 }
601}
602
84418e3b 603void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
e8e9f696
JP		 604 struct ixgbe_tx_buffer
605 *tx_buffer_info)
9a799d71 606{
e5a43549
AD		 607 if (tx_buffer_info->dma) {
608 if (tx_buffer_info->mapped_as_page)
1b507730 609 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 610 tx_buffer_info->dma,
611 tx_buffer_info->length,
1b507730 612 DMA_TO_DEVICE);
e5a43549 613 else
1b507730 614 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 615 tx_buffer_info->dma,
616 tx_buffer_info->length,
1b507730 617 DMA_TO_DEVICE);
e5a43549
AD		 618 tx_buffer_info->dma = 0;
619 }
9a799d71
AK		 620 if (tx_buffer_info->skb) {
621 dev_kfree_skb_any(tx_buffer_info->skb);
622 tx_buffer_info->skb = NULL;
623 }
44df32c5 624 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 625 /* tx_buffer_info must be completely set up in the transmit path */
626}
627
26f23d82 628/**
7483d9dd 629 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 630 * @adapter: the ixgbe adapter
631 * @tx_ring: the corresponding tx_ring
632 *
633 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
634 * corresponding TC of this tx_ring when checking TFCS.
635 *
7483d9dd 636 * Returns : true if in xon state (currently not paused)
26f23d82 637 */
7483d9dd 638static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
e8e9f696 639 struct ixgbe_ring *tx_ring)
26f23d82 640{
26f23d82
YZ		 641 u32 txoff = IXGBE_TFCS_TXOFF;
642
643#ifdef CONFIG_IXGBE_DCB
ca739481 644 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 645 int tc;
26f23d82
YZ		 646 int reg_idx = tx_ring->reg_idx;
647 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
648
6837e895
PW		 649 switch (adapter->hw.mac.type) {
650 case ixgbe_mac_82598EB:
26f23d82
YZ		 651 tc = reg_idx >> 2;
652 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 653 break;
654 case ixgbe_mac_82599EB:
26f23d82
YZ		 655 tc = 0;
656 txoff = IXGBE_TFCS_TXOFF;
657 if (dcb_i == 8) {
658 /* TC0, TC1 */
659 tc = reg_idx >> 5;
660 if (tc == 2) /* TC2, TC3 */
661 tc += (reg_idx - 64) >> 4;
662 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
663 tc += 1 + ((reg_idx - 96) >> 3);
664 } else if (dcb_i == 4) {
665 /* TC0, TC1 */
666 tc = reg_idx >> 6;
667 if (tc == 1) {
668 tc += (reg_idx - 64) >> 5;
669 if (tc == 2) /* TC2, TC3 */
670 tc += (reg_idx - 96) >> 4;
671 }
672 }
6837e895
PW		 673 break;
674 default:
675 tc = 0;
26f23d82
YZ		 676 }
677 txoff <<= tc;
678 }
679#endif
680 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
681}
682
9a799d71 683static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
e8e9f696
JP		 684 struct ixgbe_ring *tx_ring,
685 unsigned int eop)
9a799d71 686{
e01c31a5 687 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 688
9a799d71 689 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 690 * check with the clearing of time_stamp and movement of eop */
9a799d71 691 adapter->detect_tx_hung = false;
44df32c5 692 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 693 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 694 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 695 /* detected Tx unit hang */
e01c31a5 696 union ixgbe_adv_tx_desc *tx_desc;
31f05a2d 697 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
396e799c 698 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 699 " Tx Queue <%d>\n"
700 " TDH, TDT <%x>, <%x>\n"
701 " next_to_use <%x>\n"
702 " next_to_clean <%x>\n"
703 "tx_buffer_info[next_to_clean]\n"
704 " time_stamp <%lx>\n"
705 " jiffies <%lx>\n",
706 tx_ring->queue_index,
707 IXGBE_READ_REG(hw, tx_ring->head),
708 IXGBE_READ_REG(hw, tx_ring->tail),
709 tx_ring->next_to_use, eop,
710 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 711 return true;
712 }
713
714 return false;
715}
716
b4617240
PW		 717#define IXGBE_MAX_TXD_PWR 14
718#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 719
720/* Tx Descriptors needed, worst case */
721#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
722 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
723#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 724 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 725
e01c31a5
JB		 726static void ixgbe_tx_timeout(struct net_device *netdev);
727
9a799d71
AK		 728/**
729 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 730 * @q_vector: structure containing interrupt and ring information
e01c31a5 731 * @tx_ring: tx ring to clean
9a799d71 732 **/
fe49f04a 733static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 734 struct ixgbe_ring *tx_ring)
9a799d71 735{
fe49f04a 736 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 737 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 738 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
739 struct ixgbe_tx_buffer *tx_buffer_info;
740 unsigned int i, eop, count = 0;
e01c31a5 741 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 742
743 i = tx_ring->next_to_clean;
12207e49 744 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 745 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 746
747 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 748 (count < tx_ring->work_limit)) {
12207e49 749 bool cleaned = false;
2d0bb1c1 750 rmb(); /* read buffer_info after eop_desc */
12207e49
PWJ		 751 for ( ; !cleaned; count++) {
752 struct sk_buff *skb;
31f05a2d 753 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 754 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 755 cleaned = (i == eop);
e01c31a5 756 skb = tx_buffer_info->skb;
9a799d71 757
12207e49 758 if (cleaned && skb) {
e092be60 759 unsigned int segs, bytecount;
3d8fd385 760 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 761
762 /* gso_segs is currently only valid for tcp */
e092be60 763 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 764#ifdef IXGBE_FCOE
765 /* adjust for FCoE Sequence Offload */
766 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
767 && (skb->protocol == htons(ETH_P_FCOE)) &&
768 skb_is_gso(skb)) {
769 hlen = skb_transport_offset(skb) +
770 sizeof(struct fc_frame_header) +
771 sizeof(struct fcoe_crc_eof);
772 segs = DIV_ROUND_UP(skb->len - hlen,
773 skb_shinfo(skb)->gso_size);
774 }
775#endif /* IXGBE_FCOE */
e092be60 776 /* multiply data chunks by size of headers */
3d8fd385 777 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 778 total_packets += segs;
779 total_bytes += bytecount;
e092be60 780 }
e01c31a5 781
9a799d71 782 ixgbe_unmap_and_free_tx_resource(adapter,
e8e9f696 783 tx_buffer_info);
9a799d71 784
12207e49
PWJ		 785 tx_desc->wb.status = 0;
786
9a799d71
AK		 787 i++;
788 if (i == tx_ring->count)
789 i = 0;
e01c31a5 790 }
12207e49
PWJ		 791
792 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 793 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 794 }
795
9a799d71
AK		 796 tx_ring->next_to_clean = i;
797
e092be60 798#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5 799 if (unlikely(count && netif_carrier_ok(netdev) &&
e8e9f696 800 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 801 /* Make sure that anybody stopping the queue after this
802 * sees the new next_to_clean.
803 */
804 smp_mb();
30eba97a
AV		 805 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
806 !test_bit(__IXGBE_DOWN, &adapter->state)) {
807 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 808 ++tx_ring->restart_queue;
30eba97a 809 }
e092be60 810 }
9a799d71 811
e01c31a5
JB		 812 if (adapter->detect_tx_hung) {
813 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
814 /* schedule immediate reset if we believe we hung */
396e799c
ET		 815 e_info(probe, "tx hang %d detected, resetting "
816 "adapter\n", adapter->tx_timeout_count + 1);
e01c31a5
JB		 817 ixgbe_tx_timeout(adapter->netdev);
818 }
819 }
9a799d71 820
e01c31a5 821 /* re-arm the interrupt */
fe49f04a
AD		 822 if (count >= tx_ring->work_limit)
823 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 824
e01c31a5
JB		 825 tx_ring->total_bytes += total_bytes;
826 tx_ring->total_packets += total_packets;
de1036b1 827 u64_stats_update_begin(&tx_ring->syncp);
e01c31a5 828 tx_ring->stats.packets += total_packets;
12207e49 829 tx_ring->stats.bytes += total_bytes;
de1036b1 830 u64_stats_update_end(&tx_ring->syncp);
807540ba 831 return count < tx_ring->work_limit;
9a799d71
AK		 832}
833
5dd2d332 834#ifdef CONFIG_IXGBE_DCA
bd0362dd 835static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
e8e9f696 836 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 837{
838 u32 rxctrl;
839 int cpu = get_cpu();
4a0b9ca0 840 int q = rx_ring->reg_idx;
bd0362dd 841
3a581073 842 if (rx_ring->cpu != cpu) {
bd0362dd 843 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 844 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
845 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
846 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
847 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
848 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
849 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 850 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
e8e26350 851 }
bd0362dd
JC		 852 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
853 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
855 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e9f696 856 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 857 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 858 rx_ring->cpu = cpu;
bd0362dd
JC		 859 }
860 put_cpu();
861}
862
863static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
e8e9f696 864 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 865{
866 u32 txctrl;
867 int cpu = get_cpu();
4a0b9ca0 868 int q = tx_ring->reg_idx;
ee5f784a 869 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 870
3a581073 871 if (tx_ring->cpu != cpu) {
e8e26350 872 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 873 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 874 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
875 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 876 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
877 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 878 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 879 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 880 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
881 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 882 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
ee5f784a
DS		 883 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
884 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 885 }
3a581073 886 tx_ring->cpu = cpu;
bd0362dd
JC		 887 }
888 put_cpu();
889}
890
891static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
892{
893 int i;
894
895 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
896 return;
897
e35ec126
AD		 898 /* always use CB2 mode, difference is masked in the CB driver */
899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
900
bd0362dd 901 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 902 adapter->tx_ring[i]->cpu = -1;
903 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 904 }
905 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 906 adapter->rx_ring[i]->cpu = -1;
907 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 908 }
909}
910
911static int __ixgbe_notify_dca(struct device *dev, void *data)
912{
913 struct net_device *netdev = dev_get_drvdata(dev);
914 struct ixgbe_adapter *adapter = netdev_priv(netdev);
915 unsigned long event = *(unsigned long *)data;
916
917 switch (event) {
918 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 919 /* if we're already enabled, don't do it again */
920 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
921 break;
652f093f 922 if (dca_add_requester(dev) == 0) {
96b0e0f6 923 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 924 ixgbe_setup_dca(adapter);
925 break;
926 }
927 /* Fall Through since DCA is disabled. */
928 case DCA_PROVIDER_REMOVE:
929 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
930 dca_remove_requester(dev);
931 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
932 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
933 }
934 break;
935 }
936
652f093f 937 return 0;
bd0362dd
JC		 938}
939
5dd2d332 940#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 941/**
942 * ixgbe_receive_skb - Send a completed packet up the stack
943 * @adapter: board private structure
944 * @skb: packet to send up
177db6ff
MC		 945 * @status: hardware indication of status of receive
946 * @rx_ring: rx descriptor ring (for a specific queue) to setup
947 * @rx_desc: rx descriptor
9a799d71 948 **/
78b6f4ce 949static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 950 struct sk_buff *skb, u8 status,
951 struct ixgbe_ring *ring,
952 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 953{
78b6f4ce
HX		 954 struct ixgbe_adapter *adapter = q_vector->adapter;
955 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 956 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
957 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 958
f62bbb5e
JG		 959 if (is_vlan && (tag & VLAN_VID_MASK))
960 __vlan_hwaccel_put_tag(skb, tag);
961
962 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
963 napi_gro_receive(napi, skb);
964 else
965 netif_rx(skb);
9a799d71
AK		 966}
967
e59bd25d
AV		 968/**
969 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
970 * @adapter: address of board private structure
971 * @status_err: hardware indication of status of receive
972 * @skb: skb currently being received and modified
973 **/
9a799d71 974static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 975 union ixgbe_adv_rx_desc *rx_desc,
976 struct sk_buff *skb)
9a799d71 977{
8bae1b2b
DS		 978 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
979
bc8acf2c 980 skb_checksum_none_assert(skb);
9a799d71 981
712744be
JB		 982 /* Rx csum disabled */
983 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 984 return;
e59bd25d
AV		 985
986 /* if IP and error */
987 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
988 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 989 adapter->hw_csum_rx_error++;
990 return;
991 }
e59bd25d
AV		 992
993 if (!(status_err & IXGBE_RXD_STAT_L4CS))
994 return;
995
996 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 997 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
998
999 /*
1000 * 82599 errata, UDP frames with a 0 checksum can be marked as
1001 * checksum errors.
1002 */
1003 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1004 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1005 return;
1006
e59bd25d
AV		 1007 adapter->hw_csum_rx_error++;
1008 return;
1009 }
1010
9a799d71 1011 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1012 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1013}
1014
e8e26350 1015static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
e8e9f696 1016 struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1017{
1018 /*
1019 * Force memory writes to complete before letting h/w
1020 * know there are new descriptors to fetch. (Only
1021 * applicable for weak-ordered memory model archs,
1022 * such as IA-64).
1023 */
1024 wmb();
1025 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1026}
1027
9a799d71
AK		 1028/**
1029 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1030 * @adapter: address of board private structure
1031 **/
84418e3b 1032void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1033 struct ixgbe_ring *rx_ring,
1034 int cleaned_count)
9a799d71 1035{
d716a7d8 1036 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1037 struct pci_dev *pdev = adapter->pdev;
1038 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1039 struct ixgbe_rx_buffer *bi;
9a799d71 1040 unsigned int i;
d716a7d8 1041 unsigned int bufsz = rx_ring->rx_buf_len;
9a799d71
AK		 1042
1043 i = rx_ring->next_to_use;
3a581073 1044 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1045
1046 while (cleaned_count--) {
31f05a2d 1047 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1048
762f4c57 1049 if (!bi->page_dma &&
6e455b89 1050 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1051 if (!bi->page) {
d716a7d8 1052 bi->page = netdev_alloc_page(netdev);
762f4c57
JB		 1053 if (!bi->page) {
1054 adapter->alloc_rx_page_failed++;
1055 goto no_buffers;
1056 }
1057 bi->page_offset = 0;
1058 } else {
1059 /* use a half page if we're re-using */
1060 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1061 }
762f4c57 1062
1b507730 1063 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
e8e9f696
JP		 1064 bi->page_offset,
1065 (PAGE_SIZE / 2),
1b507730 1066 DMA_FROM_DEVICE);
9a799d71
AK		 1067 }
1068
3a581073 1069 if (!bi->skb) {
d716a7d8
AD		 1070 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1071 bufsz);
1072 bi->skb = skb;
9a799d71
AK		 1073
1074 if (!skb) {
1075 adapter->alloc_rx_buff_failed++;
1076 goto no_buffers;
1077 }
d716a7d8
AD		 1078 /* initialize queue mapping */
1079 skb_record_rx_queue(skb, rx_ring->queue_index);
1080 }
9a799d71 1081
d716a7d8
AD		 1082 if (!bi->dma) {
1083 bi->dma = dma_map_single(&pdev->dev,
1084 bi->skb->data,
e8e9f696 1085 rx_ring->rx_buf_len,
1b507730 1086 DMA_FROM_DEVICE);
9a799d71
AK		 1087 }
1088 /* Refresh the desc even if buffer_addrs didn't change because
1089 * each write-back erases this info. */
6e455b89 1090 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1091 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1092 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1093 } else {
3a581073 1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1095 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1096 }
1097
1098 i++;
1099 if (i == rx_ring->count)
1100 i = 0;
3a581073 1101 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1102 }
7c6e0a43 1103
9a799d71
AK		 1104no_buffers:
1105 if (rx_ring->next_to_use != i) {
1106 rx_ring->next_to_use = i;
1107 if (i-- == 0)
1108 i = (rx_ring->count - 1);
1109
e8e26350 1110 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1111 }
1112}
1113
7c6e0a43
JB		 1114static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1115{
1116 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1117}
1118
1119static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1120{
1121 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122}
1123
f8212f97
AD		 1124static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1125{
1126 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
e8e9f696
JP		 1127 IXGBE_RXDADV_RSCCNT_MASK) >>
1128 IXGBE_RXDADV_RSCCNT_SHIFT;
f8212f97
AD		 1129}
1130
1131/**
1132 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1133 * @skb: pointer to the last skb in the rsc queue
94b982b2 1134 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1135 *
1136 * This function changes a queue full of hw rsc buffers into a completed
1137 * packet. It uses the ->prev pointers to find the first packet and then
1138 * turns it into the frag list owner.
1139 **/
94b982b2 1140static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
e8e9f696 1141 u64 *count)
f8212f97
AD		 1142{
1143 unsigned int frag_list_size = 0;
1144
1145 while (skb->prev) {
1146 struct sk_buff *prev = skb->prev;
1147 frag_list_size += skb->len;
1148 skb->prev = NULL;
1149 skb = prev;
94b982b2 1150 *count += 1;
f8212f97
AD		 1151 }
1152
1153 skb_shinfo(skb)->frag_list = skb->next;
1154 skb->next = NULL;
1155 skb->len += frag_list_size;
1156 skb->data_len += frag_list_size;
1157 skb->truesize += frag_list_size;
1158 return skb;
1159}
1160
43634e82
MC		 1161struct ixgbe_rsc_cb {
1162 dma_addr_t dma;
e8171aaa 1163 bool delay_unmap;
43634e82
MC		 1164};
1165
1166#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1167
78b6f4ce 1168static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1169 struct ixgbe_ring *rx_ring,
1170 int *work_done, int work_to_do)
9a799d71 1171{
78b6f4ce 1172 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1173 struct pci_dev *pdev = adapter->pdev;
1174 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1175 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1176 struct sk_buff *skb;
f8212f97 1177 unsigned int i, rsc_count = 0;
7c6e0a43 1178 u32 len, staterr;
177db6ff
MC		 1179 u16 hdr_info;
1180 bool cleaned = false;
9a799d71 1181 int cleaned_count = 0;
d2f4fbe2 1182 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1183#ifdef IXGBE_FCOE
1184 int ddp_bytes = 0;
1185#endif /* IXGBE_FCOE */
9a799d71
AK		 1186
1187 i = rx_ring->next_to_clean;
31f05a2d 1188 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71
AK		 1189 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1190 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1191
1192 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1193 u32 upper_len = 0;
9a799d71
AK		 1194 if (*work_done >= work_to_do)
1195 break;
1196 (*work_done)++;
1197
3c945e5b 1198 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1199 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1200 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1201 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1202 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1203 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1204 if ((len > IXGBE_RX_HDR_SIZE) ||
1205 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1206 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1207 } else {
9a799d71 1208 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1209 }
9a799d71
AK		 1210
1211 cleaned = true;
1212 skb = rx_buffer_info->skb;
7ca3bc58 1213 prefetch(skb->data);
9a799d71
AK		 1214 rx_buffer_info->skb = NULL;
1215
21fa4e66 1216 if (rx_buffer_info->dma) {
43634e82
MC		 1217 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1218 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1219 (!(skb->prev))) {
43634e82
MC		 1220 /*
1221 * When HWRSC is enabled, delay unmapping
1222 * of the first packet. It carries the
1223 * header information, HW may still
1224 * access the header after the writeback.
1225 * Only unmap it when EOP is reached
1226 */
e8171aaa 1227 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1228 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1229 } else {
1b507730 1230 dma_unmap_single(&pdev->dev,
e8e9f696
JP		 1231 rx_buffer_info->dma,
1232 rx_ring->rx_buf_len,
1233 DMA_FROM_DEVICE);
e8171aaa 1234 }
4f57ca6e 1235 rx_buffer_info->dma = 0;
9a799d71
AK		 1236 skb_put(skb, len);
1237 }
1238
1239 if (upper_len) {
1b507730
NN		 1240 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1241 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1242 rx_buffer_info->page_dma = 0;
1243 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1244 rx_buffer_info->page,
1245 rx_buffer_info->page_offset,
1246 upper_len);
762f4c57
JB		 1247
1248 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1249 (page_count(rx_buffer_info->page) != 1))
1250 rx_buffer_info->page = NULL;
1251 else
1252 get_page(rx_buffer_info->page);
9a799d71
AK		 1253
1254 skb->len += upper_len;
1255 skb->data_len += upper_len;
1256 skb->truesize += upper_len;
1257 }
1258
1259 i++;
1260 if (i == rx_ring->count)
1261 i = 0;
9a799d71 1262
31f05a2d 1263 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1264 prefetch(next_rxd);
9a799d71 1265 cleaned_count++;
f8212f97 1266
0c19d6af 1267 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1268 rsc_count = ixgbe_get_rsc_count(rx_desc);
1269
1270 if (rsc_count) {
1271 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1272 IXGBE_RXDADV_NEXTP_SHIFT;
1273 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1274 } else {
1275 next_buffer = &rx_ring->rx_buffer_info[i];
1276 }
1277
9a799d71 1278 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1279 if (skb->prev)
e8e9f696
JP		 1280 skb = ixgbe_transform_rsc_queue(skb,
1281 &(rx_ring->rsc_count));
94b982b2 1282 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1283 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1284 dma_unmap_single(&pdev->dev,
1285 IXGBE_RSC_CB(skb)->dma,
e8e9f696 1286 rx_ring->rx_buf_len,
1b507730 1287 DMA_FROM_DEVICE);
fd3686a8 1288 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1289 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1290 }
94b982b2 1291 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
e8e9f696
JP		 1292 rx_ring->rsc_count +=
1293 skb_shinfo(skb)->nr_frags;
94b982b2
MC		 1294 else
1295 rx_ring->rsc_count++;
1296 rx_ring->rsc_flush++;
1297 }
de1036b1 1298 u64_stats_update_begin(&rx_ring->syncp);
9a799d71
AK		 1299 rx_ring->stats.packets++;
1300 rx_ring->stats.bytes += skb->len;
de1036b1 1301 u64_stats_update_end(&rx_ring->syncp);
9a799d71 1302 } else {
6e455b89 1303 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1304 rx_buffer_info->skb = next_buffer->skb;
1305 rx_buffer_info->dma = next_buffer->dma;
1306 next_buffer->skb = skb;
1307 next_buffer->dma = 0;
1308 } else {
1309 skb->next = next_buffer->skb;
1310 skb->next->prev = skb;
1311 }
7ca3bc58 1312 rx_ring->non_eop_descs++;
9a799d71
AK		 1313 goto next_desc;
1314 }
1315
1316 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1317 dev_kfree_skb_irq(skb);
1318 goto next_desc;
1319 }
1320
8bae1b2b 1321 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1322
1323 /* probably a little skewed due to removing CRC */
1324 total_rx_bytes += skb->len;
1325 total_rx_packets++;
1326
74ce8dd2 1327 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1328#ifdef IXGBE_FCOE
1329 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1330 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1331 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1332 if (!ddp_bytes)
332d4a7d 1333 goto next_desc;
3d8fd385 1334 }
332d4a7d 1335#endif /* IXGBE_FCOE */
fdaff1ce 1336 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1337
1338next_desc:
1339 rx_desc->wb.upper.status_error = 0;
1340
1341 /* return some buffers to hardware, one at a time is too slow */
1342 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1343 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1344 cleaned_count = 0;
1345 }
1346
1347 /* use prefetched values */
1348 rx_desc = next_rxd;
f8212f97 1349 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1350
1351 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1352 }
1353
9a799d71
AK		 1354 rx_ring->next_to_clean = i;
1355 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1356
1357 if (cleaned_count)
1358 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1359
3d8fd385
YZ		 1360#ifdef IXGBE_FCOE
1361 /* include DDPed FCoE data */
1362 if (ddp_bytes > 0) {
1363 unsigned int mss;
1364
1365 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1366 sizeof(struct fc_frame_header) -
1367 sizeof(struct fcoe_crc_eof);
1368 if (mss > 512)
1369 mss &= ~511;
1370 total_rx_bytes += ddp_bytes;
1371 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1372 }
1373#endif /* IXGBE_FCOE */
1374
f494e8fa
AV		 1375 rx_ring->total_packets += total_rx_packets;
1376 rx_ring->total_bytes += total_rx_bytes;
f494e8fa 1377
9a799d71
AK		 1378 return cleaned;
1379}
1380
021230d4 1381static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1382/**
1383 * ixgbe_configure_msix - Configure MSI-X hardware
1384 * @adapter: board private structure
1385 *
1386 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1387 * interrupts.
1388 **/
1389static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1390{
021230d4
AV		 1391 struct ixgbe_q_vector *q_vector;
1392 int i, j, q_vectors, v_idx, r_idx;
1393 u32 mask;
9a799d71 1394
021230d4 1395 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1396
4df10466
JB		 1397 /*
1398 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1399 * corresponding register.
1400 */
1401 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1402 q_vector = adapter->q_vector[v_idx];
984b3f57 1403 /* XXX for_each_set_bit(...) */
021230d4 1404 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1405 adapter->num_rx_queues);
021230d4
AV		 1406
1407 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1408 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1409 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1410 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1411 adapter->num_rx_queues,
1412 r_idx + 1);
021230d4
AV		 1413 }
1414 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1415 adapter->num_tx_queues);
021230d4
AV		 1416
1417 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1418 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1419 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1420 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1421 adapter->num_tx_queues,
1422 r_idx + 1);
021230d4
AV		 1423 }
1424
021230d4 1425 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1426 /* tx only */
1427 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1428 else if (q_vector->rxr_count)
f7554a2b
NS		 1429 /* rx or mixed */
1430 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1431
fe49f04a 1432 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1433 /* If Flow Director is enabled, set interrupt affinity */
1434 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1435 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1436 /*
1437 * Allocate the affinity_hint cpumask, assign the mask
1438 * for this vector, and set our affinity_hint for
1439 * this irq.
1440 */
1441 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1442 GFP_KERNEL))
1443 return;
1444 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1445 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1446 q_vector->affinity_mask);
1447 }
9a799d71
AK		 1448 }
1449
e8e26350
PW		 1450 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1451 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1452 v_idx);
e8e26350
PW		 1453 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1454 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1455 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1456
41fb9248 1457 /* set up to autoclear timer, and the vectors */
021230d4 1458 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1459 if (adapter->num_vfs)
1460 mask &= ~(IXGBE_EIMS_OTHER |
1461 IXGBE_EIMS_MAILBOX |
1462 IXGBE_EIMS_LSC);
1463 else
1464 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1465 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1466}
1467
f494e8fa
AV		 1468enum latency_range {
1469 lowest_latency = 0,
1470 low_latency = 1,
1471 bulk_latency = 2,
1472 latency_invalid = 255
1473};
1474
1475/**
1476 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1477 * @adapter: pointer to adapter
1478 * @eitr: eitr setting (ints per sec) to give last timeslice
1479 * @itr_setting: current throttle rate in ints/second
1480 * @packets: the number of packets during this measurement interval
1481 * @bytes: the number of bytes during this measurement interval
1482 *
1483 * Stores a new ITR value based on packets and byte
1484 * counts during the last interrupt. The advantage of per interrupt
1485 * computation is faster updates and more accurate ITR for the current
1486 * traffic pattern. Constants in this function were computed
1487 * based on theoretical maximum wire speed and thresholds were set based
1488 * on testing data as well as attempting to minimize response time
1489 * while increasing bulk throughput.
1490 * this functionality is controlled by the InterruptThrottleRate module
1491 * parameter (see ixgbe_param.c)
1492 **/
1493static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1494 u32 eitr, u8 itr_setting,
1495 int packets, int bytes)
f494e8fa
AV		 1496{
1497 unsigned int retval = itr_setting;
1498 u32 timepassed_us;
1499 u64 bytes_perint;
1500
1501 if (packets == 0)
1502 goto update_itr_done;
1503
1504
1505 /* simple throttlerate management
1506 * 0-20MB/s lowest (100000 ints/s)
1507 * 20-100MB/s low (20000 ints/s)
1508 * 100-1249MB/s bulk (8000 ints/s)
1509 */
1510 /* what was last interrupt timeslice? */
1511 timepassed_us = 1000000/eitr;
1512 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1513
1514 switch (itr_setting) {
1515 case lowest_latency:
1516 if (bytes_perint > adapter->eitr_low)
1517 retval = low_latency;
1518 break;
1519 case low_latency:
1520 if (bytes_perint > adapter->eitr_high)
1521 retval = bulk_latency;
1522 else if (bytes_perint <= adapter->eitr_low)
1523 retval = lowest_latency;
1524 break;
1525 case bulk_latency:
1526 if (bytes_perint <= adapter->eitr_high)
1527 retval = low_latency;
1528 break;
1529 }
1530
1531update_itr_done:
1532 return retval;
1533}
1534
509ee935
JB		 1535/**
1536 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1537 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1538 *
1539 * This function is made to be called by ethtool and by the driver
1540 * when it needs to update EITR registers at runtime. Hardware
1541 * specific quirks/differences are taken care of here.
1542 */
fe49f04a 1543void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1544{
fe49f04a 1545 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1546 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1547 int v_idx = q_vector->v_idx;
1548 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1549
509ee935
JB		 1550 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1551 /* must write high and low 16 bits to reset counter */
1552 itr_reg |= (itr_reg << 16);
1553 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1554 /*
1555 * 82599 can support a value of zero, so allow it for
1556 * max interrupt rate, but there is an errata where it can
1557 * not be zero with RSC
1558 */
1559 if (itr_reg == 8 &&
1560 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1561 itr_reg = 0;
1562
509ee935
JB		 1563 /*
1564 * set the WDIS bit to not clear the timer bits and cause an
1565 * immediate assertion of the interrupt
1566 */
1567 itr_reg |= IXGBE_EITR_CNT_WDIS;
1568 }
1569 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1570}
1571
f494e8fa
AV		 1572static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1573{
1574 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1575 u32 new_itr;
1576 u8 current_itr, ret_itr;
fe49f04a 1577 int i, r_idx;
f494e8fa
AV		 1578 struct ixgbe_ring *rx_ring, *tx_ring;
1579
1580 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1581 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1582 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1583 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1584 q_vector->tx_itr,
1585 tx_ring->total_packets,
1586 tx_ring->total_bytes);
f494e8fa
AV		 1587 /* if the result for this queue would decrease interrupt
1588 * rate for this vector then use that result */
30efa5a3 1589 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1590 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1591 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1592 r_idx + 1);
f494e8fa
AV		 1593 }
1594
1595 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1596 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1597 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1598 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1599 q_vector->rx_itr,
1600 rx_ring->total_packets,
1601 rx_ring->total_bytes);
f494e8fa
AV		 1602 /* if the result for this queue would decrease interrupt
1603 * rate for this vector then use that result */
30efa5a3 1604 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1605 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1606 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1607 r_idx + 1);
f494e8fa
AV		 1608 }
1609
30efa5a3 1610 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1611
1612 switch (current_itr) {
1613 /* counts and packets in update_itr are dependent on these numbers */
1614 case lowest_latency:
1615 new_itr = 100000;
1616 break;
1617 case low_latency:
1618 new_itr = 20000; /* aka hwitr = ~200 */
1619 break;
1620 case bulk_latency:
1621 default:
1622 new_itr = 8000;
1623 break;
1624 }
1625
1626 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1627 /* do an exponential smoothing */
1628 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1629
1630 /* save the algorithm value here, not the smoothed one */
1631 q_vector->eitr = new_itr;
fe49f04a
AD		 1632
1633 ixgbe_write_eitr(q_vector);
f494e8fa 1634 }
f494e8fa
AV		 1635}
1636
119fc60a
MC		 1637/**
1638 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1639 * @work: pointer to work_struct containing our data
1640 **/
1641static void ixgbe_check_overtemp_task(struct work_struct *work)
1642{
1643 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1644 struct ixgbe_adapter,
1645 check_overtemp_task);
119fc60a
MC		 1646 struct ixgbe_hw *hw = &adapter->hw;
1647 u32 eicr = adapter->interrupt_event;
1648
7ca647bd
JP		 1649 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1650 return;
1651
1652 switch (hw->device_id) {
1653 case IXGBE_DEV_ID_82599_T3_LOM: {
1654 u32 autoneg;
1655 bool link_up = false;
1656
1657 if (hw->mac.ops.check_link)
1658 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1659
1660 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1661 (eicr & IXGBE_EICR_LSC))
1662 /* Check if this is due to overtemp */
1663 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1664 break;
1665 return;
1666 }
1667 default:
1668 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1669 return;
7ca647bd 1670 break;
119fc60a 1671 }
7ca647bd
JP		 1672 e_crit(drv,
1673 "Network adapter has been stopped because it has over heated. "
1674 "Restart the computer. If the problem persists, "
1675 "power off the system and replace the adapter\n");
1676 /* write to clear the interrupt */
1677 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1678}
1679
0befdb3e
JB		 1680static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1681{
1682 struct ixgbe_hw *hw = &adapter->hw;
1683
1684 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1685 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1686 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1687 /* write to clear the interrupt */
1688 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1689 }
1690}
cf8280ee 1691
e8e26350
PW		 1692static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1693{
1694 struct ixgbe_hw *hw = &adapter->hw;
1695
1696 if (eicr & IXGBE_EICR_GPI_SDP1) {
1697 /* Clear the interrupt */
1698 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1699 schedule_work(&adapter->multispeed_fiber_task);
1700 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1701 /* Clear the interrupt */
1702 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1703 schedule_work(&adapter->sfp_config_module_task);
1704 } else {
1705 /* Interrupt isn't for us... */
1706 return;
1707 }
1708}
1709
cf8280ee
JB		 1710static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1711{
1712 struct ixgbe_hw *hw = &adapter->hw;
1713
1714 adapter->lsc_int++;
1715 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1716 adapter->link_check_timeout = jiffies;
1717 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1718 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1719 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1720 schedule_work(&adapter->watchdog_task);
1721 }
1722}
1723
9a799d71
AK		 1724static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1725{
1726 struct net_device *netdev = data;
1727 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1728 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1729 u32 eicr;
1730
1731 /*
1732 * Workaround for Silicon errata. Use clear-by-write instead
1733 * of clear-by-read. Reading with EICS will return the
1734 * interrupt causes without clearing, which later be done
1735 * with the write to EICR.
1736 */
1737 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1738 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1739
cf8280ee
JB		 1740 if (eicr & IXGBE_EICR_LSC)
1741 ixgbe_check_lsc(adapter);
d4f80882 1742
1cdd1ec8
GR		 1743 if (eicr & IXGBE_EICR_MAILBOX)
1744 ixgbe_msg_task(adapter);
1745
e8e26350
PW		 1746 if (hw->mac.type == ixgbe_mac_82598EB)
1747 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1748
c4cf55e5 1749 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1750 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1751 adapter->interrupt_event = eicr;
1752 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1753 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1754 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1755
1756 /* Handle Flow Director Full threshold interrupt */
1757 if (eicr & IXGBE_EICR_FLOW_DIR) {
1758 int i;
1759 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1760 /* Disable transmits before FDIR Re-initialization */
1761 netif_tx_stop_all_queues(netdev);
1762 for (i = 0; i < adapter->num_tx_queues; i++) {
1763 struct ixgbe_ring *tx_ring =
e8e9f696 1764 adapter->tx_ring[i];
c4cf55e5 1765 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 1766 &tx_ring->reinit_state))
c4cf55e5
PWJ		 1767 schedule_work(&adapter->fdir_reinit_task);
1768 }
1769 }
1770 }
d4f80882
AV		 1771 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1772 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1773
1774 return IRQ_HANDLED;
1775}
1776
fe49f04a
AD		 1777static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1778 u64 qmask)
1779{
1780 u32 mask;
1781
1782 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1783 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1784 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1785 } else {
1786 mask = (qmask & 0xFFFFFFFF);
1787 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1788 mask = (qmask >> 32);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1790 }
1791 /* skip the flush */
1792}
1793
1794static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1795 u64 qmask)
fe49f04a
AD		 1796{
1797 u32 mask;
1798
1799 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1800 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1801 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1802 } else {
1803 mask = (qmask & 0xFFFFFFFF);
1804 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1805 mask = (qmask >> 32);
1806 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1807 }
1808 /* skip the flush */
1809}
1810
9a799d71
AK		 1811static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1812{
021230d4
AV		 1813 struct ixgbe_q_vector *q_vector = data;
1814 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1815 struct ixgbe_ring *tx_ring;
021230d4
AV		 1816 int i, r_idx;
1817
1818 if (!q_vector->txr_count)
1819 return IRQ_HANDLED;
1820
1821 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1822 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1823 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1824 tx_ring->total_bytes = 0;
1825 tx_ring->total_packets = 0;
021230d4 1826 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1827 r_idx + 1);
021230d4 1828 }
9a799d71 1829
9b471446 1830 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1831 napi_schedule(&q_vector->napi);
1832
9a799d71
AK		 1833 return IRQ_HANDLED;
1834}
1835
021230d4
AV		 1836/**
1837 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1838 * @irq: unused
1839 * @data: pointer to our q_vector struct for this interrupt vector
1840 **/
9a799d71
AK		 1841static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1842{
021230d4
AV		 1843 struct ixgbe_q_vector *q_vector = data;
1844 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1845 struct ixgbe_ring *rx_ring;
021230d4 1846 int r_idx;
30efa5a3 1847 int i;
021230d4
AV		 1848
1849 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1850 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1851 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1852 rx_ring->total_bytes = 0;
1853 rx_ring->total_packets = 0;
1854 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1855 r_idx + 1);
30efa5a3
JB		 1856 }
1857
021230d4
AV		 1858 if (!q_vector->rxr_count)
1859 return IRQ_HANDLED;
1860
021230d4 1861 /* disable interrupts on this vector only */
9b471446 1862 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1863 napi_schedule(&q_vector->napi);
021230d4
AV		 1864
1865 return IRQ_HANDLED;
1866}
1867
1868static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1869{
91281fd3
AD		 1870 struct ixgbe_q_vector *q_vector = data;
1871 struct ixgbe_adapter *adapter = q_vector->adapter;
1872 struct ixgbe_ring *ring;
1873 int r_idx;
1874 int i;
1875
1876 if (!q_vector->txr_count && !q_vector->rxr_count)
1877 return IRQ_HANDLED;
1878
1879 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1880 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1881 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1882 ring->total_bytes = 0;
1883 ring->total_packets = 0;
1884 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1885 r_idx + 1);
91281fd3
AD		 1886 }
1887
1888 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1889 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1890 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1891 ring->total_bytes = 0;
1892 ring->total_packets = 0;
1893 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1894 r_idx + 1);
91281fd3
AD		 1895 }
1896
9b471446 1897 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1898 napi_schedule(&q_vector->napi);
9a799d71 1899
9a799d71
AK		 1900 return IRQ_HANDLED;
1901}
1902
021230d4
AV		 1903/**
1904 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1905 * @napi: napi struct with our devices info in it
1906 * @budget: amount of work driver is allowed to do this pass, in packets
1907 *
f0848276
JB		 1908 * This function is optimized for cleaning one queue only on a single
1909 * q_vector!!!
021230d4 1910 **/
9a799d71
AK		 1911static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1912{
021230d4 1913 struct ixgbe_q_vector *q_vector =
e8e9f696 1914 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1915 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1916 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1917 int work_done = 0;
021230d4 1918 long r_idx;
9a799d71 1919
021230d4 1920 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1921 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1922#ifdef CONFIG_IXGBE_DCA
bd0362dd 1923 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1924 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1925#endif
9a799d71 1926
78b6f4ce 1927 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1928
021230d4
AV		 1929 /* If all Rx work done, exit the polling mode */
1930 if (work_done < budget) {
288379f0 1931 napi_complete(napi);
f7554a2b 1932 if (adapter->rx_itr_setting & 1)
f494e8fa 1933 ixgbe_set_itr_msix(q_vector);
9a799d71 1934 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1935 ixgbe_irq_enable_queues(adapter,
e8e9f696 1936 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1937 }
1938
1939 return work_done;
1940}
1941
f0848276 1942/**
91281fd3 1943 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1944 * @napi: napi struct with our devices info in it
1945 * @budget: amount of work driver is allowed to do this pass, in packets
1946 *
1947 * This function will clean more than one rx queue associated with a
1948 * q_vector.
1949 **/
91281fd3 1950static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1951{
1952 struct ixgbe_q_vector *q_vector =
e8e9f696 1953 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 1954 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1955 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1956 int work_done = 0, i;
1957 long r_idx;
91281fd3
AD		 1958 bool tx_clean_complete = true;
1959
1960 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1961 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1962 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1963#ifdef CONFIG_IXGBE_DCA
1964 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1965 ixgbe_update_tx_dca(adapter, ring);
1966#endif
1967 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1968 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1969 r_idx + 1);
91281fd3 1970 }
f0848276
JB		 1971
1972 /* attempt to distribute budget to each queue fairly, but don't allow
1973 * the budget to go below 1 because we'll exit polling */
1974 budget /= (q_vector->rxr_count ?: 1);
1975 budget = max(budget, 1);
1976 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1977 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1978 ring = adapter->rx_ring[r_idx];
5dd2d332 1979#ifdef CONFIG_IXGBE_DCA
f0848276 1980 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1981 ixgbe_update_rx_dca(adapter, ring);
f0848276 1982#endif
91281fd3 1983 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 1984 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1985 r_idx + 1);
f0848276
JB		 1986 }
1987
1988 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1989 ring = adapter->rx_ring[r_idx];
f0848276 1990 /* If all Rx work done, exit the polling mode */
7f821875 1991 if (work_done < budget) {
288379f0 1992 napi_complete(napi);
f7554a2b 1993 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1994 ixgbe_set_itr_msix(q_vector);
1995 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1996 ixgbe_irq_enable_queues(adapter,
e8e9f696 1997 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1998 return 0;
1999 }
2000
2001 return work_done;
2002}
91281fd3
AD		 2003
2004/**
2005 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2006 * @napi: napi struct with our devices info in it
2007 * @budget: amount of work driver is allowed to do this pass, in packets
2008 *
2009 * This function is optimized for cleaning one queue only on a single
2010 * q_vector!!!
2011 **/
2012static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2013{
2014 struct ixgbe_q_vector *q_vector =
e8e9f696 2015 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2016 struct ixgbe_adapter *adapter = q_vector->adapter;
2017 struct ixgbe_ring *tx_ring = NULL;
2018 int work_done = 0;
2019 long r_idx;
2020
2021 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 2022 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2023#ifdef CONFIG_IXGBE_DCA
2024 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2025 ixgbe_update_tx_dca(adapter, tx_ring);
2026#endif
2027
2028 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2029 work_done = budget;
2030
f7554a2b 2031 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2032 if (work_done < budget) {
2033 napi_complete(napi);
f7554a2b 2034 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2035 ixgbe_set_itr_msix(q_vector);
2036 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2037 ixgbe_irq_enable_queues(adapter,
2038 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2039 }
2040
2041 return work_done;
2042}
2043
021230d4 2044static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2045 int r_idx)
021230d4 2046{
7a921c93
AD		 2047 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2048
2049 set_bit(r_idx, q_vector->rxr_idx);
2050 q_vector->rxr_count++;
021230d4
AV		 2051}
2052
2053static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2054 int t_idx)
021230d4 2055{
7a921c93
AD		 2056 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2057
2058 set_bit(t_idx, q_vector->txr_idx);
2059 q_vector->txr_count++;
021230d4
AV		 2060}
2061
9a799d71 2062/**
021230d4
AV		 2063 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2064 * @adapter: board private structure to initialize
2065 * @vectors: allotted vector count for descriptor rings
9a799d71 2066 *
021230d4
AV		 2067 * This function maps descriptor rings to the queue-specific vectors
2068 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2069 * one vector per ring/queue, but on a constrained vector budget, we
2070 * group the rings as "efficiently" as possible. You would add new
2071 * mapping configurations in here.
9a799d71 2072 **/
021230d4 2073static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
e8e9f696 2074 int vectors)
021230d4
AV		 2075{
2076 int v_start = 0;
2077 int rxr_idx = 0, txr_idx = 0;
2078 int rxr_remaining = adapter->num_rx_queues;
2079 int txr_remaining = adapter->num_tx_queues;
2080 int i, j;
2081 int rqpv, tqpv;
2082 int err = 0;
2083
2084 /* No mapping required if MSI-X is disabled. */
2085 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2086 goto out;
9a799d71 2087
021230d4
AV		 2088 /*
2089 * The ideal configuration...
2090 * We have enough vectors to map one per queue.
2091 */
2092 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2093 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2094 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2095
021230d4
AV		 2096 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2097 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2098
9a799d71 2099 goto out;
021230d4 2100 }
9a799d71 2101
021230d4
AV		 2102 /*
2103 * If we don't have enough vectors for a 1-to-1
2104 * mapping, we'll have to group them so there are
2105 * multiple queues per vector.
2106 */
2107 /* Re-adjusting *qpv takes care of the remainder. */
2108 for (i = v_start; i < vectors; i++) {
2109 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2110 for (j = 0; j < rqpv; j++) {
2111 map_vector_to_rxq(adapter, i, rxr_idx);
2112 rxr_idx++;
2113 rxr_remaining--;
2114 }
2115 }
2116 for (i = v_start; i < vectors; i++) {
2117 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2118 for (j = 0; j < tqpv; j++) {
2119 map_vector_to_txq(adapter, i, txr_idx);
2120 txr_idx++;
2121 txr_remaining--;
9a799d71 2122 }
9a799d71
AK		 2123 }
2124
021230d4
AV		 2125out:
2126 return err;
2127}
2128
2129/**
2130 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2131 * @adapter: board private structure
2132 *
2133 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2134 * interrupts from the kernel.
2135 **/
2136static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2137{
2138 struct net_device *netdev = adapter->netdev;
2139 irqreturn_t (*handler)(int, void *);
2140 int i, vector, q_vectors, err;
e8e9f696 2141 int ri = 0, ti = 0;
021230d4
AV		 2142
2143 /* Decrement for Other and TCP Timer vectors */
2144 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2145
2146 /* Map the Tx/Rx rings to the vectors we were allotted. */
2147 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2148 if (err)
2149 goto out;
2150
2151#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
e8e9f696
JP		 2152 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2153 &ixgbe_msix_clean_many)
021230d4 2154 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2155 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20 2156
e8e9f696 2157 if (handler == &ixgbe_msix_clean_rx) {
cb13fc20
RO		 2158 sprintf(adapter->name[vector], "%s-%s-%d",
2159 netdev->name, "rx", ri++);
e8e9f696 2160 } else if (handler == &ixgbe_msix_clean_tx) {
cb13fc20
RO		 2161 sprintf(adapter->name[vector], "%s-%s-%d",
2162 netdev->name, "tx", ti++);
e8e9f696 2163 } else
cb13fc20
RO		 2164 sprintf(adapter->name[vector], "%s-%s-%d",
2165 netdev->name, "TxRx", vector);
2166
021230d4 2167 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696
JP		 2168 handler, 0, adapter->name[vector],
2169 adapter->q_vector[vector]);
9a799d71 2170 if (err) {
396e799c 2171 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2172 "Error: %d\n", err);
021230d4 2173 goto free_queue_irqs;
9a799d71 2174 }
9a799d71
AK		 2175 }
2176
021230d4
AV		 2177 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2178 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696 2179 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2180 if (err) {
396e799c 2181 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2182 goto free_queue_irqs;
9a799d71
AK		 2183 }
2184
9a799d71
AK		 2185 return 0;
2186
021230d4
AV		 2187free_queue_irqs:
2188 for (i = vector - 1; i >= 0; i--)
2189 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2190 adapter->q_vector[i]);
021230d4
AV		 2191 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2192 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2193 kfree(adapter->msix_entries);
2194 adapter->msix_entries = NULL;
021230d4 2195out:
9a799d71
AK		 2196 return err;
2197}
2198
f494e8fa
AV		 2199static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2200{
7a921c93 2201 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2202 u8 current_itr;
2203 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2204 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2205 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2206
30efa5a3 2207 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2208 q_vector->tx_itr,
2209 tx_ring->total_packets,
2210 tx_ring->total_bytes);
30efa5a3 2211 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2212 q_vector->rx_itr,
2213 rx_ring->total_packets,
2214 rx_ring->total_bytes);
f494e8fa 2215
30efa5a3 2216 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2217
2218 switch (current_itr) {
2219 /* counts and packets in update_itr are dependent on these numbers */
2220 case lowest_latency:
2221 new_itr = 100000;
2222 break;
2223 case low_latency:
2224 new_itr = 20000; /* aka hwitr = ~200 */
2225 break;
2226 case bulk_latency:
2227 new_itr = 8000;
2228 break;
2229 default:
2230 break;
2231 }
2232
2233 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2234 /* do an exponential smoothing */
2235 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2236
2237 /* save the algorithm value here, not the smoothed one */
2238 q_vector->eitr = new_itr;
fe49f04a
AD		 2239
2240 ixgbe_write_eitr(q_vector);
f494e8fa 2241 }
f494e8fa
AV		 2242}
2243
79aefa45
AD		 2244/**
2245 * ixgbe_irq_enable - Enable default interrupt generation settings
2246 * @adapter: board private structure
2247 **/
6af3b9eb
ET		 2248static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2249 bool flush)
79aefa45
AD		 2250{
2251 u32 mask;
835462fc
NS		 2252
2253 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2254 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2255 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2256 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2257 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2258 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2259 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2260 mask |= IXGBE_EIMS_GPI_SDP1;
2261 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2262 if (adapter->num_vfs)
2263 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2264 }
c4cf55e5
PWJ		 2265 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2266 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2267 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2268
79aefa45 2269 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2270 if (queues)
2271 ixgbe_irq_enable_queues(adapter, ~0);
2272 if (flush)
2273 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2274
2275 if (adapter->num_vfs > 32) {
2276 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2277 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2278 }
79aefa45 2279}
021230d4 2280
9a799d71 2281/**
021230d4 2282 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2283 * @irq: interrupt number
2284 * @data: pointer to a network interface device structure
9a799d71
AK		 2285 **/
2286static irqreturn_t ixgbe_intr(int irq, void *data)
2287{
2288 struct net_device *netdev = data;
2289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2290 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2291 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2292 u32 eicr;
2293
54037505 2294 /*
6af3b9eb 2295 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2296 * before the read of EICR.
2297 */
2298 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2299
021230d4
AV		 2300 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2301 * therefore no explict interrupt disable is necessary */
2302 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2303 if (!eicr) {
6af3b9eb
ET		 2304 /*
2305 * shared interrupt alert!
f47cf66e 2306 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2307 * have disabled interrupts due to EIAM
2308 * finish the workaround of silicon errata on 82598. Unmask
2309 * the interrupt that we masked before the EICR read.
2310 */
2311 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2312 ixgbe_irq_enable(adapter, true, true);
9a799d71 2313 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2314 }
9a799d71 2315
cf8280ee
JB		 2316 if (eicr & IXGBE_EICR_LSC)
2317 ixgbe_check_lsc(adapter);
021230d4 2318
e8e26350
PW		 2319 if (hw->mac.type == ixgbe_mac_82599EB)
2320 ixgbe_check_sfp_event(adapter, eicr);
2321
0befdb3e 2322 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2323 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2324 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2325 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2326
7a921c93 2327 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2328 adapter->tx_ring[0]->total_packets = 0;
2329 adapter->tx_ring[0]->total_bytes = 0;
2330 adapter->rx_ring[0]->total_packets = 0;
2331 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2332 /* would disable interrupts here but EIAM disabled it */
7a921c93 2333 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2334 }
2335
6af3b9eb
ET		 2336 /*
2337 * re-enable link(maybe) and non-queue interrupts, no flush.
2338 * ixgbe_poll will re-enable the queue interrupts
2339 */
2340
2341 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2342 ixgbe_irq_enable(adapter, false, false);
2343
9a799d71
AK		 2344 return IRQ_HANDLED;
2345}
2346
021230d4
AV		 2347static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2348{
2349 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2350
2351 for (i = 0; i < q_vectors; i++) {
7a921c93 2352 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2353 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2354 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2355 q_vector->rxr_count = 0;
2356 q_vector->txr_count = 0;
2357 }
2358}
2359
9a799d71
AK		 2360/**
2361 * ixgbe_request_irq - initialize interrupts
2362 * @adapter: board private structure
2363 *
2364 * Attempts to configure interrupts using the best available
2365 * capabilities of the hardware and kernel.
2366 **/
021230d4 2367static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2368{
2369 struct net_device *netdev = adapter->netdev;
021230d4 2370 int err;
9a799d71 2371
021230d4
AV		 2372 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2373 err = ixgbe_request_msix_irqs(adapter);
2374 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2375 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2376 netdev->name, netdev);
021230d4 2377 } else {
a0607fd3 2378 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2379 netdev->name, netdev);
9a799d71
AK		 2380 }
2381
9a799d71 2382 if (err)
396e799c 2383 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2384
9a799d71
AK		 2385 return err;
2386}
2387
2388static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2389{
2390 struct net_device *netdev = adapter->netdev;
2391
2392 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2393 int i, q_vectors;
9a799d71 2394
021230d4
AV		 2395 q_vectors = adapter->num_msix_vectors;
2396
2397 i = q_vectors - 1;
9a799d71 2398 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2399
021230d4
AV		 2400 i--;
2401 for (; i >= 0; i--) {
2402 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2403 adapter->q_vector[i]);
021230d4
AV		 2404 }
2405
2406 ixgbe_reset_q_vectors(adapter);
2407 } else {
2408 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2409 }
2410}
2411
22d5a71b
JB		 2412/**
2413 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2414 * @adapter: board private structure
2415 **/
2416static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2417{
835462fc
NS		 2418 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2419 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2420 } else {
2421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2422 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2424 if (adapter->num_vfs > 32)
2425 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2426 }
2427 IXGBE_WRITE_FLUSH(&adapter->hw);
2428 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2429 int i;
2430 for (i = 0; i < adapter->num_msix_vectors; i++)
2431 synchronize_irq(adapter->msix_entries[i].vector);
2432 } else {
2433 synchronize_irq(adapter->pdev->irq);
2434 }
2435}
2436
9a799d71
AK		 2437/**
2438 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2439 *
2440 **/
2441static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2442{
9a799d71
AK		 2443 struct ixgbe_hw *hw = &adapter->hw;
2444
021230d4 2445 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2446 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2447
e8e26350
PW		 2448 ixgbe_set_ivar(adapter, 0, 0, 0);
2449 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2450
2451 map_vector_to_rxq(adapter, 0, 0);
2452 map_vector_to_txq(adapter, 0, 0);
2453
396e799c 2454 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2455}
2456
43e69bf0
AD		 2457/**
2458 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2459 * @adapter: board private structure
2460 * @ring: structure containing ring specific data
2461 *
2462 * Configure the Tx descriptor ring after a reset.
2463 **/
84418e3b
AD		 2464void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2465 struct ixgbe_ring *ring)
43e69bf0
AD		 2466{
2467 struct ixgbe_hw *hw = &adapter->hw;
2468 u64 tdba = ring->dma;
2f1860b8
AD		 2469 int wait_loop = 10;
2470 u32 txdctl;
43e69bf0
AD		 2471 u16 reg_idx = ring->reg_idx;
2472
2f1860b8
AD		 2473 /* disable queue to avoid issues while updating state */
2474 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2475 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2476 txdctl & ~IXGBE_TXDCTL_ENABLE);
2477 IXGBE_WRITE_FLUSH(hw);
2478
43e69bf0 2479 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2480 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2481 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2482 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2483 ring->count * sizeof(union ixgbe_adv_tx_desc));
2484 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2485 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2486 ring->head = IXGBE_TDH(reg_idx);
2487 ring->tail = IXGBE_TDT(reg_idx);
2488
2f1860b8
AD		 2489 /* configure fetching thresholds */
2490 if (adapter->rx_itr_setting == 0) {
2491 /* cannot set wthresh when itr==0 */
2492 txdctl &= ~0x007F0000;
2493 } else {
2494 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2495 txdctl |= (8 << 16);
2496 }
2497 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2498 /* PThresh workaround for Tx hang with DFP enabled. */
2499 txdctl |= 32;
2500 }
2501
2502 /* reinitialize flowdirector state */
2503 set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2504
2505 /* enable queue */
2506 txdctl |= IXGBE_TXDCTL_ENABLE;
2507 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2508
2509 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2510 if (hw->mac.type == ixgbe_mac_82598EB &&
2511 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2512 return;
2513
2514 /* poll to verify queue is enabled */
2515 do {
2516 msleep(1);
2517 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2518 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2519 if (!wait_loop)
2520 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2521}
2522
120ff942
AD		 2523static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2524{
2525 struct ixgbe_hw *hw = &adapter->hw;
2526 u32 rttdcs;
2527 u32 mask;
2528
2529 if (hw->mac.type == ixgbe_mac_82598EB)
2530 return;
2531
2532 /* disable the arbiter while setting MTQC */
2533 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2534 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2535 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2536
2537 /* set transmit pool layout */
2538 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2539 switch (adapter->flags & mask) {
2540
2541 case (IXGBE_FLAG_SRIOV_ENABLED):
2542 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2543 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2544 break;
2545
2546 case (IXGBE_FLAG_DCB_ENABLED):
2547 /* We enable 8 traffic classes, DCB only */
2548 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2549 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2550 break;
2551
2552 default:
2553 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2554 break;
2555 }
2556
2557 /* re-enable the arbiter */
2558 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2559 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2560}
2561
9a799d71 2562/**
3a581073 2563 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2564 * @adapter: board private structure
2565 *
2566 * Configure the Tx unit of the MAC after a reset.
2567 **/
2568static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2569{
2f1860b8
AD		 2570 struct ixgbe_hw *hw = &adapter->hw;
2571 u32 dmatxctl;
43e69bf0 2572 u32 i;
9a799d71 2573
2f1860b8
AD		 2574 ixgbe_setup_mtqc(adapter);
2575
2576 if (hw->mac.type != ixgbe_mac_82598EB) {
2577 /* DMATXCTL.EN must be before Tx queues are enabled */
2578 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2579 dmatxctl |= IXGBE_DMATXCTL_TE;
2580 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2581 }
2582
9a799d71 2583 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2584 for (i = 0; i < adapter->num_tx_queues; i++)
2585 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2586}
2587
e8e26350 2588#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2589
a6616b42 2590static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2591 struct ixgbe_ring *rx_ring)
cc41ac7c 2592{
cc41ac7c 2593 u32 srrctl;
a6616b42 2594 int index;
0cefafad 2595 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2596
a6616b42
YZ		 2597 index = rx_ring->reg_idx;
2598 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2599 unsigned long mask;
0cefafad 2600 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2601 index = index & mask;
cc41ac7c 2602 }
cc41ac7c
JB		 2603 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2604
2605 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2606 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2607 if (adapter->num_vfs)
2608 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2609
afafd5b0
AD		 2610 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2611 IXGBE_SRRCTL_BSIZEHDR_MASK;
2612
6e455b89 2613 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2614#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2615 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2616#else
2617 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2618#endif
cc41ac7c 2619 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2620 } else {
afafd5b0
AD		 2621 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2622 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2623 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2624 }
e8e26350 2625
cc41ac7c
JB		 2626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2627}
9a799d71 2628
05abb126 2629static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2630{
05abb126
AD		 2631 struct ixgbe_hw *hw = &adapter->hw;
2632 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2633 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2634 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2635 u32 mrqc = 0, reta = 0;
2636 u32 rxcsum;
2637 int i, j;
0cefafad
JB		 2638 int mask;
2639
05abb126
AD		 2640 /* Fill out hash function seeds */
2641 for (i = 0; i < 10; i++)
2642 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2643
2644 /* Fill out redirection table */
2645 for (i = 0, j = 0; i < 128; i++, j++) {
2646 if (j == adapter->ring_feature[RING_F_RSS].indices)
2647 j = 0;
2648 /* reta = 4-byte sliding window of
2649 * 0x00..(indices-1)(indices-1)00..etc. */
2650 reta = (reta << 8) | (j * 0x11);
2651 if ((i & 3) == 3)
2652 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2653 }
0cefafad 2654
05abb126
AD		 2655 /* Disable indicating checksum in descriptor, enables RSS hash */
2656 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2657 rxcsum |= IXGBE_RXCSUM_PCSD;
2658 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2659
2660 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2661 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2662 else
2663 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2664#ifdef CONFIG_IXGBE_DCB
05abb126 2665 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2666#endif
05abb126
AD		 2667 | IXGBE_FLAG_SRIOV_ENABLED
2668 );
0cefafad
JB		 2669
2670 switch (mask) {
2671 case (IXGBE_FLAG_RSS_ENABLED):
2672 mrqc = IXGBE_MRQC_RSSEN;
2673 break;
1cdd1ec8
GR		 2674 case (IXGBE_FLAG_SRIOV_ENABLED):
2675 mrqc = IXGBE_MRQC_VMDQEN;
2676 break;
0cefafad
JB		 2677#ifdef CONFIG_IXGBE_DCB
2678 case (IXGBE_FLAG_DCB_ENABLED):
2679 mrqc = IXGBE_MRQC_RT8TCEN;
2680 break;
2681#endif /* CONFIG_IXGBE_DCB */
2682 default:
2683 break;
2684 }
2685
05abb126
AD		 2686 /* Perform hash on these packet types */
2687 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2688 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2689 | IXGBE_MRQC_RSS_FIELD_IPV6
2690 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2691
2692 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2693}
2694
bb5a9ad2
NS		 2695/**
2696 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2697 * @adapter: address of board private structure
2698 * @index: index of ring to set
bb5a9ad2 2699 **/
7367096a
AD		 2700static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2701 struct ixgbe_ring *ring)
bb5a9ad2 2702{
bb5a9ad2 2703 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2704 u32 rscctrl;
edd2ea55 2705 int rx_buf_len;
7367096a
AD		 2706 u16 reg_idx = ring->reg_idx;
2707
2708 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2709 return;
bb5a9ad2 2710
7367096a
AD		 2711 rx_buf_len = ring->rx_buf_len;
2712 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2713 rscctrl |= IXGBE_RSCCTL_RSCEN;
2714 /*
2715 * we must limit the number of descriptors so that the
2716 * total size of max desc * buf_len is not greater
2717 * than 65535
2718 */
7367096a 2719 if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
bb5a9ad2
NS		 2720#if (MAX_SKB_FRAGS > 16)
2721 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2722#elif (MAX_SKB_FRAGS > 8)
2723 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2724#elif (MAX_SKB_FRAGS > 4)
2725 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2726#else
2727 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2728#endif
2729 } else {
2730 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2731 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2732 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2733 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2734 else
2735 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2736 }
7367096a 2737 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2738}
2739
9e10e045
AD		 2740/**
2741 * ixgbe_set_uta - Set unicast filter table address
2742 * @adapter: board private structure
2743 *
2744 * The unicast table address is a register array of 32-bit registers.
2745 * The table is meant to be used in a way similar to how the MTA is used
2746 * however due to certain limitations in the hardware it is necessary to
2747 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2748 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2749 **/
2750static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2751{
2752 struct ixgbe_hw *hw = &adapter->hw;
2753 int i;
2754
2755 /* The UTA table only exists on 82599 hardware and newer */
2756 if (hw->mac.type < ixgbe_mac_82599EB)
2757 return;
2758
2759 /* we only need to do this if VMDq is enabled */
2760 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2761 return;
2762
2763 for (i = 0; i < 128; i++)
2764 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2765}
2766
2767#define IXGBE_MAX_RX_DESC_POLL 10
2768static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2769 struct ixgbe_ring *ring)
2770{
2771 struct ixgbe_hw *hw = &adapter->hw;
2772 int reg_idx = ring->reg_idx;
2773 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2774 u32 rxdctl;
2775
2776 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2777 if (hw->mac.type == ixgbe_mac_82598EB &&
2778 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2779 return;
2780
2781 do {
2782 msleep(1);
2783 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2784 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2785
2786 if (!wait_loop) {
2787 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2788 "the polling period\n", reg_idx);
2789 }
2790}
2791
84418e3b
AD		 2792void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2793 struct ixgbe_ring *ring)
acd37177
AD		 2794{
2795 struct ixgbe_hw *hw = &adapter->hw;
2796 u64 rdba = ring->dma;
9e10e045 2797 u32 rxdctl;
acd37177
AD		 2798 u16 reg_idx = ring->reg_idx;
2799
9e10e045
AD		 2800 /* disable queue to avoid issues while updating state */
2801 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2802 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2803 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2804 IXGBE_WRITE_FLUSH(hw);
2805
acd37177
AD		 2806 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2807 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2808 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2809 ring->count * sizeof(union ixgbe_adv_rx_desc));
2810 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2811 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2812 ring->head = IXGBE_RDH(reg_idx);
2813 ring->tail = IXGBE_RDT(reg_idx);
9e10e045
AD		 2814
2815 ixgbe_configure_srrctl(adapter, ring);
2816 ixgbe_configure_rscctl(adapter, ring);
2817
2818 if (hw->mac.type == ixgbe_mac_82598EB) {
2819 /*
2820 * enable cache line friendly hardware writes:
2821 * PTHRESH=32 descriptors (half the internal cache),
2822 * this also removes ugly rx_no_buffer_count increment
2823 * HTHRESH=4 descriptors (to minimize latency on fetch)
2824 * WTHRESH=8 burst writeback up to two cache lines
2825 */
2826 rxdctl &= ~0x3FFFFF;
2827 rxdctl |= 0x080420;
2828 }
2829
2830 /* enable receive descriptor ring */
2831 rxdctl |= IXGBE_RXDCTL_ENABLE;
2832 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2833
2834 ixgbe_rx_desc_queue_enable(adapter, ring);
2835 ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 2836}
2837
48654521
AD		 2838static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2839{
2840 struct ixgbe_hw *hw = &adapter->hw;
2841 int p;
2842
2843 /* PSRTYPE must be initialized in non 82598 adapters */
2844 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2845 IXGBE_PSRTYPE_UDPHDR |
2846 IXGBE_PSRTYPE_IPV4HDR |
48654521 2847 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2848 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2849
2850 if (hw->mac.type == ixgbe_mac_82598EB)
2851 return;
2852
2853 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2854 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2855
2856 for (p = 0; p < adapter->num_rx_pools; p++)
2857 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2858 psrtype);
2859}
2860
f5b4a52e
AD		 2861static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2862{
2863 struct ixgbe_hw *hw = &adapter->hw;
2864 u32 gcr_ext;
2865 u32 vt_reg_bits;
2866 u32 reg_offset, vf_shift;
2867 u32 vmdctl;
2868
2869 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2870 return;
2871
2872 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2873 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2874 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2875 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2876
2877 vf_shift = adapter->num_vfs % 32;
2878 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2879
2880 /* Enable only the PF's pool for Tx/Rx */
2881 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2882 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2883 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2884 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2885 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2886
2887 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2888 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2889
2890 /*
2891 * Set up VF register offsets for selected VT Mode,
2892 * i.e. 32 or 64 VFs for SR-IOV
2893 */
2894 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2895 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2896 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2897 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2898
2899 /* enable Tx loopback for VF/PF communication */
2900 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2901}
2902
477de6ed 2903static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2904{
9a799d71
AK		 2905 struct ixgbe_hw *hw = &adapter->hw;
2906 struct net_device *netdev = adapter->netdev;
2907 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2908 int rx_buf_len;
477de6ed
AD		 2909 struct ixgbe_ring *rx_ring;
2910 int i;
2911 u32 mhadd, hlreg0;
48654521 2912
9a799d71 2913 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2914 /* Do not use packet split if we're in SR-IOV Mode */
2915 if (!adapter->num_vfs)
2916 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2917
2918 /* Set the RX buffer length according to the mode */
2919 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2920 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2921 } else {
0c19d6af 2922 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2923 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2924 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2925 else
477de6ed 2926 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 2927 }
2928
63f39bd1 2929#ifdef IXGBE_FCOE
477de6ed
AD		 2930 /* adjust max frame to be able to do baby jumbo for FCoE */
2931 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2932 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2933 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2934
477de6ed
AD		 2935#endif /* IXGBE_FCOE */
2936 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2937 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2938 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2939 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2940
2941 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2942 }
2943
2944 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2945 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2946 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2947 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2948
0cefafad
JB		 2949 /*
2950 * Setup the HW Rx Head and Tail Descriptor Pointers and
2951 * the Base and Length of the Rx Descriptor Ring
2952 */
9a799d71 2953 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2954 rx_ring = adapter->rx_ring[i];
a6616b42 2955 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2956
6e455b89
YZ		 2957 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2958 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2959 else
2960 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2961
63f39bd1 2962#ifdef IXGBE_FCOE
e8e9f696 2963 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2964 struct ixgbe_ring_feature *f;
2965 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2966 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2967 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2968 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2969 rx_ring->rx_buf_len =
e8e9f696 2970 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2971 }
63f39bd1 2972 }
63f39bd1 2973#endif /* IXGBE_FCOE */
477de6ed
AD		 2974 }
2975
2976}
2977
7367096a
AD		 2978static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2979{
2980 struct ixgbe_hw *hw = &adapter->hw;
2981 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2982
2983 switch (hw->mac.type) {
2984 case ixgbe_mac_82598EB:
2985 /*
2986 * For VMDq support of different descriptor types or
2987 * buffer sizes through the use of multiple SRRCTL
2988 * registers, RDRXCTL.MVMEN must be set to 1
2989 *
2990 * also, the manual doesn't mention it clearly but DCA hints
2991 * will only use queue 0's tags unless this bit is set. Side
2992 * effects of setting this bit are only that SRRCTL must be
2993 * fully programmed [0..15]
2994 */
2995 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2996 break;
2997 case ixgbe_mac_82599EB:
2998 /* Disable RSC for ACK packets */
2999 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3000 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3001 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3002 /* hardware requires some bits to be set by default */
3003 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3004 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3005 break;
3006 default:
3007 /* We should do nothing since we don't know this hardware */
3008 return;
3009 }
3010
3011 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3012}
3013
477de6ed
AD		 3014/**
3015 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3016 * @adapter: board private structure
3017 *
3018 * Configure the Rx unit of the MAC after a reset.
3019 **/
3020static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3021{
3022 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3023 int i;
3024 u32 rxctrl;
477de6ed
AD		 3025
3026 /* disable receives while setting up the descriptors */
3027 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3028 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3029
3030 ixgbe_setup_psrtype(adapter);
7367096a 3031 ixgbe_setup_rdrxctl(adapter);
477de6ed 3032
9e10e045 3033 /* Program registers for the distribution of queues */
f5b4a52e 3034 ixgbe_setup_mrqc(adapter);
f5b4a52e 3035
9e10e045
AD		 3036 ixgbe_set_uta(adapter);
3037
477de6ed
AD		 3038 /* set_rx_buffer_len must be called before ring initialization */
3039 ixgbe_set_rx_buffer_len(adapter);
3040
3041 /*
3042 * Setup the HW Rx Head and Tail Descriptor Pointers and
3043 * the Base and Length of the Rx Descriptor Ring
3044 */
9e10e045
AD		 3045 for (i = 0; i < adapter->num_rx_queues; i++)
3046 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3047
9e10e045
AD		 3048 /* disable drop enable for 82598 parts */
3049 if (hw->mac.type == ixgbe_mac_82598EB)
3050 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3051
3052 /* enable all receives */
3053 rxctrl |= IXGBE_RXCTRL_RXEN;
3054 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3055}
3056
068c89b0
DS		 3057static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3058{
3059 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3060 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3061 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3062
3063 /* add VID to filter table */
1ada1b1b 3064 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3065 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3066}
3067
3068static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3069{
3070 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3071 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3072 int pool_ndx = adapter->num_vfs;
068c89b0 3073
068c89b0 3074 /* remove VID from filter table */
1ada1b1b 3075 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3076 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3077}
3078
5f6c0181
JB		 3079/**
3080 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3081 * @adapter: driver data
3082 */
3083static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3084{
3085 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3086 u32 vlnctrl;
3087
3088 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3089 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3090 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3091}
3092
3093/**
3094 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3095 * @adapter: driver data
3096 */
3097static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3098{
3099 struct ixgbe_hw *hw = &adapter->hw;
3100 u32 vlnctrl;
3101
3102 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3103 vlnctrl |= IXGBE_VLNCTRL_VFE;
3104 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3105 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3106}
3107
3108/**
3109 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3110 * @adapter: driver data
3111 */
3112static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3113{
3114 struct ixgbe_hw *hw = &adapter->hw;
3115 u32 vlnctrl;
5f6c0181
JB		 3116 int i, j;
3117
3118 switch (hw->mac.type) {
3119 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3120 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3121 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3122 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3123 break;
3124 case ixgbe_mac_82599EB:
5f6c0181
JB		 3125 for (i = 0; i < adapter->num_rx_queues; i++) {
3126 j = adapter->rx_ring[i]->reg_idx;
3127 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3128 vlnctrl &= ~IXGBE_RXDCTL_VME;
3129 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3130 }
3131 break;
3132 default:
3133 break;
3134 }
3135}
3136
3137/**
f62bbb5e 3138 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3139 * @adapter: driver data
3140 */
f62bbb5e 3141static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3142{
3143 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3144 u32 vlnctrl;
5f6c0181
JB		 3145 int i, j;
3146
3147 switch (hw->mac.type) {
3148 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3149 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3150 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3151 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3152 break;
3153 case ixgbe_mac_82599EB:
5f6c0181
JB		 3154 for (i = 0; i < adapter->num_rx_queues; i++) {
3155 j = adapter->rx_ring[i]->reg_idx;
3156 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3157 vlnctrl |= IXGBE_RXDCTL_VME;
3158 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3159 }
3160 break;
3161 default:
3162 break;
3163 }
3164}
3165
9a799d71
AK		 3166static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3167{
f62bbb5e 3168 u16 vid;
9a799d71 3169
f62bbb5e
JG		 3170 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3171
3172 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3173 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3174}
3175
2850062a
AD		 3176/**
3177 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3178 * @netdev: network interface device structure
3179 *
3180 * Writes unicast address list to the RAR table.
3181 * Returns: -ENOMEM on failure/insufficient address space
3182 * 0 on no addresses written
3183 * X on writing X addresses to the RAR table
3184 **/
3185static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3186{
3187 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3188 struct ixgbe_hw *hw = &adapter->hw;
3189 unsigned int vfn = adapter->num_vfs;
3190 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3191 int count = 0;
3192
3193 /* return ENOMEM indicating insufficient memory for addresses */
3194 if (netdev_uc_count(netdev) > rar_entries)
3195 return -ENOMEM;
3196
3197 if (!netdev_uc_empty(netdev) && rar_entries) {
3198 struct netdev_hw_addr *ha;
3199 /* return error if we do not support writing to RAR table */
3200 if (!hw->mac.ops.set_rar)
3201 return -ENOMEM;
3202
3203 netdev_for_each_uc_addr(ha, netdev) {
3204 if (!rar_entries)
3205 break;
3206 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3207 vfn, IXGBE_RAH_AV);
3208 count++;
3209 }
3210 }
3211 /* write the addresses in reverse order to avoid write combining */
3212 for (; rar_entries > 0 ; rar_entries--)
3213 hw->mac.ops.clear_rar(hw, rar_entries);
3214
3215 return count;
3216}
3217
9a799d71 3218/**
2c5645cf 3219 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3220 * @netdev: network interface device structure
3221 *
2c5645cf
CL		 3222 * The set_rx_method entry point is called whenever the unicast/multicast
3223 * address list or the network interface flags are updated. This routine is
3224 * responsible for configuring the hardware for proper unicast, multicast and
3225 * promiscuous mode.
9a799d71 3226 **/
7f870475 3227void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3228{
3229 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3230 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3231 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3232 int count;
9a799d71
AK		 3233
3234 /* Check for Promiscuous and All Multicast modes */
3235
3236 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3237
f5dc442b
AD		 3238 /* set all bits that we expect to always be set */
3239 fctrl |= IXGBE_FCTRL_BAM;
3240 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3241 fctrl |= IXGBE_FCTRL_PMCF;
3242
2850062a
AD		 3243 /* clear the bits we are changing the status of */
3244 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3245
9a799d71 3246 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3247 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3248 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3249 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3250 /* don't hardware filter vlans in promisc mode */
3251 ixgbe_vlan_filter_disable(adapter);
9a799d71 3252 } else {
746b9f02
PM		 3253 if (netdev->flags & IFF_ALLMULTI) {
3254 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3255 vmolr |= IXGBE_VMOLR_MPE;
3256 } else {
3257 /*
3258 * Write addresses to the MTA, if the attempt fails
3259 * then we should just turn on promiscous mode so
3260 * that we can at least receive multicast traffic
3261 */
3262 hw->mac.ops.update_mc_addr_list(hw, netdev);
3263 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3264 }
5f6c0181 3265 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3266 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3267 /*
3268 * Write addresses to available RAR registers, if there is not
3269 * sufficient space to store all the addresses then enable
3270 * unicast promiscous mode
3271 */
3272 count = ixgbe_write_uc_addr_list(netdev);
3273 if (count < 0) {
3274 fctrl |= IXGBE_FCTRL_UPE;
3275 vmolr |= IXGBE_VMOLR_ROPE;
3276 }
9a799d71
AK		 3277 }
3278
2850062a 3279 if (adapter->num_vfs) {
1cdd1ec8 3280 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3281 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3282 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3283 IXGBE_VMOLR_ROPE);
3284 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3285 }
3286
3287 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3288
3289 if (netdev->features & NETIF_F_HW_VLAN_RX)
3290 ixgbe_vlan_strip_enable(adapter);
3291 else
3292 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3293}
3294
021230d4
AV		 3295static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3296{
3297 int q_idx;
3298 struct ixgbe_q_vector *q_vector;
3299 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3300
3301 /* legacy and MSI only use one vector */
3302 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3303 q_vectors = 1;
3304
3305 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3306 struct napi_struct *napi;
7a921c93 3307 q_vector = adapter->q_vector[q_idx];
f0848276 3308 napi = &q_vector->napi;
91281fd3
AD		 3309 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3310 if (!q_vector->rxr_count || !q_vector->txr_count) {
3311 if (q_vector->txr_count == 1)
3312 napi->poll = &ixgbe_clean_txonly;
3313 else if (q_vector->rxr_count == 1)
3314 napi->poll = &ixgbe_clean_rxonly;
3315 }
3316 }
f0848276
JB		 3317
3318 napi_enable(napi);
021230d4
AV		 3319 }
3320}
3321
3322static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3323{
3324 int q_idx;
3325 struct ixgbe_q_vector *q_vector;
3326 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3327
3328 /* legacy and MSI only use one vector */
3329 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3330 q_vectors = 1;
3331
3332 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3333 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3334 napi_disable(&q_vector->napi);
3335 }
3336}
3337
7a6b6f51 3338#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3339/*
3340 * ixgbe_configure_dcb - Configure DCB hardware
3341 * @adapter: ixgbe adapter struct
3342 *
3343 * This is called by the driver on open to configure the DCB hardware.
3344 * This is also called by the gennetlink interface when reconfiguring
3345 * the DCB state.
3346 */
3347static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3348{
3349 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3350 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
5f6c0181 3351 u32 txdctl;
2f90b865
AD		 3352 int i, j;
3353
67ebd791
AD		 3354 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3355 if (hw->mac.type == ixgbe_mac_82598EB)
3356 netif_set_gso_max_size(adapter->netdev, 65536);
3357 return;
3358 }
3359
3360 if (hw->mac.type == ixgbe_mac_82598EB)
3361 netif_set_gso_max_size(adapter->netdev, 32768);
3362
9806307a
JF		 3363#ifdef CONFIG_FCOE
3364 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3365 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3366#endif
3367
3368 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, max_frame,
3369 DCB_TX_CONFIG);
3370 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, max_frame,
3371 DCB_RX_CONFIG);
2f90b865
AD		 3372
3373 /* reconfigure the hardware */
3374 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3375
3376 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3377 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3378 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3379 /* PThresh workaround for Tx hang with DFP enabled. */
3380 txdctl |= 32;
3381 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3382 }
3383 /* Enable VLAN tag insert/strip */
f62bbb5e 3384 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3385
2f90b865
AD		 3386 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3387}
3388
3389#endif
9a799d71
AK		 3390static void ixgbe_configure(struct ixgbe_adapter *adapter)
3391{
3392 struct net_device *netdev = adapter->netdev;
c4cf55e5 3393 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3394 int i;
3395
7a6b6f51 3396#ifdef CONFIG_IXGBE_DCB
67ebd791 3397 ixgbe_configure_dcb(adapter);
2f90b865 3398#endif
9a799d71 3399
f62bbb5e
JG		 3400 ixgbe_set_rx_mode(netdev);
3401 ixgbe_restore_vlan(adapter);
3402
eacd73f7
YZ		 3403#ifdef IXGBE_FCOE
3404 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3405 ixgbe_configure_fcoe(adapter);
3406
3407#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3408 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3409 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3410 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3411 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3412 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3413 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3414 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3415 }
933d41f1 3416 ixgbe_configure_virtualization(adapter);
c4cf55e5 3417
9a799d71
AK		 3418 ixgbe_configure_tx(adapter);
3419 ixgbe_configure_rx(adapter);
9a799d71
AK		 3420}
3421
e8e26350
PW		 3422static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3423{
3424 switch (hw->phy.type) {
3425 case ixgbe_phy_sfp_avago:
3426 case ixgbe_phy_sfp_ftl:
3427 case ixgbe_phy_sfp_intel:
3428 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3429 case ixgbe_phy_sfp_passive_tyco:
3430 case ixgbe_phy_sfp_passive_unknown:
3431 case ixgbe_phy_sfp_active_unknown:
3432 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3433 return true;
3434 default:
3435 return false;
3436 }
3437}
3438
0ecc061d 3439/**
e8e26350
PW		 3440 * ixgbe_sfp_link_config - set up SFP+ link
3441 * @adapter: pointer to private adapter struct
3442 **/
3443static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3444{
3445 struct ixgbe_hw *hw = &adapter->hw;
3446
3447 if (hw->phy.multispeed_fiber) {
3448 /*
3449 * In multispeed fiber setups, the device may not have
3450 * had a physical connection when the driver loaded.
3451 * If that's the case, the initial link configuration
3452 * couldn't get the MAC into 10G or 1G mode, so we'll
3453 * never have a link status change interrupt fire.
3454 * We need to try and force an autonegotiation
3455 * session, then bring up link.
3456 */
3457 hw->mac.ops.setup_sfp(hw);
3458 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3459 schedule_work(&adapter->multispeed_fiber_task);
3460 } else {
3461 /*
3462 * Direct Attach Cu and non-multispeed fiber modules
3463 * still need to be configured properly prior to
3464 * attempting link.
3465 */
3466 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3467 schedule_work(&adapter->sfp_config_module_task);
3468 }
3469}
3470
3471/**
3472 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3473 * @hw: pointer to private hardware struct
3474 *
3475 * Returns 0 on success, negative on failure
3476 **/
e8e26350 3477static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3478{
3479 u32 autoneg;
8620a103 3480 bool negotiation, link_up = false;
0ecc061d
PWJ		 3481 u32 ret = IXGBE_ERR_LINK_SETUP;
3482
3483 if (hw->mac.ops.check_link)
3484 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3485
3486 if (ret)
3487 goto link_cfg_out;
3488
3489 if (hw->mac.ops.get_link_capabilities)
e8e9f696
JP		 3490 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3491 &negotiation);
0ecc061d
PWJ		 3492 if (ret)
3493 goto link_cfg_out;
3494
8620a103
MC		 3495 if (hw->mac.ops.setup_link)
3496 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3497link_cfg_out:
3498 return ret;
3499}
3500
a34bcfff 3501static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3502{
9a799d71 3503 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3504 u32 gpie = 0;
9a799d71 3505
9b471446 3506 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3507 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3508 IXGBE_GPIE_OCD;
3509 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3510 /*
3511 * use EIAM to auto-mask when MSI-X interrupt is asserted
3512 * this saves a register write for every interrupt
3513 */
3514 switch (hw->mac.type) {
3515 case ixgbe_mac_82598EB:
3516 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3517 break;
3518 default:
3519 case ixgbe_mac_82599EB:
3520 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3521 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3522 break;
3523 }
3524 } else {
021230d4
AV		 3525 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3526 * specifically only auto mask tx and rx interrupts */
3527 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3528 }
9a799d71 3529
a34bcfff
AD		 3530 /* XXX: to interrupt immediately for EICS writes, enable this */
3531 /* gpie |= IXGBE_GPIE_EIMEN; */
3532
3533 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3534 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3535 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3536 }
3537
a34bcfff
AD		 3538 /* Enable fan failure interrupt */
3539 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3540 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3541
a34bcfff 3542 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3543 gpie |= IXGBE_SDP1_GPIEN;
3544 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3545
3546 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3547}
3548
3549static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3550{
3551 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3552 int err;
a34bcfff
AD		 3553 u32 ctrl_ext;
3554
3555 ixgbe_get_hw_control(adapter);
3556 ixgbe_setup_gpie(adapter);
e8e26350 3557
9a799d71
AK		 3558 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3559 ixgbe_configure_msix(adapter);
3560 else
3561 ixgbe_configure_msi_and_legacy(adapter);
3562
61fac744
PW		 3563 /* enable the optics */
3564 if (hw->phy.multispeed_fiber)
3565 hw->mac.ops.enable_tx_laser(hw);
3566
9a799d71 3567 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3568 ixgbe_napi_enable_all(adapter);
3569
3570 /* clear any pending interrupts, may auto mask */
3571 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3572 ixgbe_irq_enable(adapter, true, true);
9a799d71 3573
bf069c97
DS		 3574 /*
3575 * If this adapter has a fan, check to see if we had a failure
3576 * before we enabled the interrupt.
3577 */
3578 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3579 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3580 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3581 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3582 }
3583
e8e26350
PW		 3584 /*
3585 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3586 * arrived before interrupts were enabled but after probe. Such
3587 * devices wouldn't have their type identified yet. We need to
3588 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3589 * If we're not hot-pluggable SFP+, we just need to configure link
3590 * and bring it up.
3591 */
19343de2
DS		 3592 if (hw->phy.type == ixgbe_phy_unknown) {
3593 err = hw->phy.ops.identify(hw);
3594 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3595 /*
3596 * Take the device down and schedule the sfp tasklet
3597 * which will unregister_netdev and log it.
3598 */
19343de2 3599 ixgbe_down(adapter);
5da43c1a 3600 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3601 return err;
3602 }
e8e26350
PW		 3603 }
3604
3605 if (ixgbe_is_sfp(hw)) {
3606 ixgbe_sfp_link_config(adapter);
3607 } else {
3608 err = ixgbe_non_sfp_link_config(hw);
3609 if (err)
396e799c 3610 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3611 }
0ecc061d 3612
1da100bb 3613 /* enable transmits */
477de6ed 3614 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3615
9a799d71
AK		 3616 /* bring the link up in the watchdog, this could race with our first
3617 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3618 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3619 adapter->link_check_timeout = jiffies;
9a799d71 3620 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3621
3622 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3623 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3624 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3625 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3626
9a799d71
AK		 3627 return 0;
3628}
3629
d4f80882
AV		 3630void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3631{
3632 WARN_ON(in_interrupt());
3633 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3634 msleep(1);
3635 ixgbe_down(adapter);
5809a1ae
GR		 3636 /*
3637 * If SR-IOV enabled then wait a bit before bringing the adapter
3638 * back up to give the VFs time to respond to the reset. The
3639 * two second wait is based upon the watchdog timer cycle in
3640 * the VF driver.
3641 */
3642 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3643 msleep(2000);
d4f80882
AV		 3644 ixgbe_up(adapter);
3645 clear_bit(__IXGBE_RESETTING, &adapter->state);
3646}
3647
9a799d71
AK		 3648int ixgbe_up(struct ixgbe_adapter *adapter)
3649{
3650 /* hardware has been reset, we need to reload some things */
3651 ixgbe_configure(adapter);
3652
3653 return ixgbe_up_complete(adapter);
3654}
3655
3656void ixgbe_reset(struct ixgbe_adapter *adapter)
3657{
c44ade9e 3658 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3659 int err;
3660
3661 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3662 switch (err) {
3663 case 0:
3664 case IXGBE_ERR_SFP_NOT_PRESENT:
3665 break;
3666 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3667 e_dev_err("master disable timed out\n");
da4dd0f7 3668 break;
794caeb2
PWJ		 3669 case IXGBE_ERR_EEPROM_VERSION:
3670 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3671 e_dev_warn("This device is a pre-production adapter/LOM. "
3672 "Please be aware there may be issuesassociated with "
3673 "your hardware. If you are experiencing problems "
3674 "please contact your Intel or hardware "
3675 "representative who provided you with this "
3676 "hardware.\n");
794caeb2 3677 break;
da4dd0f7 3678 default:
849c4542 3679 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3680 }
9a799d71
AK		 3681
3682 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3683 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3684 IXGBE_RAH_AV);
9a799d71
AK		 3685}
3686
9a799d71
AK		 3687/**
3688 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3689 * @adapter: board private structure
3690 * @rx_ring: ring to free buffers from
3691 **/
3692static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
e8e9f696 3693 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3694{
3695 struct pci_dev *pdev = adapter->pdev;
3696 unsigned long size;
3697 unsigned int i;
3698
84418e3b
AD		 3699 /* ring already cleared, nothing to do */
3700 if (!rx_ring->rx_buffer_info)
3701 return;
9a799d71 3702
84418e3b 3703 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3704 for (i = 0; i < rx_ring->count; i++) {
3705 struct ixgbe_rx_buffer *rx_buffer_info;
3706
3707 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3708 if (rx_buffer_info->dma) {
1b507730 3709 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
e8e9f696 3710 rx_ring->rx_buf_len,
1b507730 3711 DMA_FROM_DEVICE);
9a799d71
AK		 3712 rx_buffer_info->dma = 0;
3713 }
3714 if (rx_buffer_info->skb) {
f8212f97 3715 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3716 rx_buffer_info->skb = NULL;
f8212f97
AD		 3717 do {
3718 struct sk_buff *this = skb;
e8171aaa 3719 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3720 dma_unmap_single(&pdev->dev,
3721 IXGBE_RSC_CB(this)->dma,
e8e9f696 3722 rx_ring->rx_buf_len,
1b507730 3723 DMA_FROM_DEVICE);
fd3686a8 3724 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3725 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3726 }
f8212f97
AD		 3727 skb = skb->prev;
3728 dev_kfree_skb(this);
3729 } while (skb);
9a799d71
AK		 3730 }
3731 if (!rx_buffer_info->page)
3732 continue;
4f57ca6e 3733 if (rx_buffer_info->page_dma) {
1b507730
NN		 3734 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3735 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3736 rx_buffer_info->page_dma = 0;
3737 }
9a799d71
AK		 3738 put_page(rx_buffer_info->page);
3739 rx_buffer_info->page = NULL;
762f4c57 3740 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3741 }
3742
3743 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3744 memset(rx_ring->rx_buffer_info, 0, size);
3745
3746 /* Zero out the descriptor ring */
3747 memset(rx_ring->desc, 0, rx_ring->size);
3748
3749 rx_ring->next_to_clean = 0;
3750 rx_ring->next_to_use = 0;
3751
9891ca7c
JB		 3752 if (rx_ring->head)
3753 writel(0, adapter->hw.hw_addr + rx_ring->head);
3754 if (rx_ring->tail)
3755 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3756}
3757
3758/**
3759 * ixgbe_clean_tx_ring - Free Tx Buffers
3760 * @adapter: board private structure
3761 * @tx_ring: ring to be cleaned
3762 **/
3763static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
e8e9f696 3764 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3765{
3766 struct ixgbe_tx_buffer *tx_buffer_info;
3767 unsigned long size;
3768 unsigned int i;
3769
84418e3b
AD		 3770 /* ring already cleared, nothing to do */
3771 if (!tx_ring->tx_buffer_info)
3772 return;
9a799d71 3773
84418e3b 3774 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3775 for (i = 0; i < tx_ring->count; i++) {
3776 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3777 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3778 }
3779
3780 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3781 memset(tx_ring->tx_buffer_info, 0, size);
3782
3783 /* Zero out the descriptor ring */
3784 memset(tx_ring->desc, 0, tx_ring->size);
3785
3786 tx_ring->next_to_use = 0;
3787 tx_ring->next_to_clean = 0;
3788
9891ca7c
JB		 3789 if (tx_ring->head)
3790 writel(0, adapter->hw.hw_addr + tx_ring->head);
3791 if (tx_ring->tail)
3792 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3793}
3794
3795/**
021230d4 3796 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3797 * @adapter: board private structure
3798 **/
021230d4 3799static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3800{
3801 int i;
3802
021230d4 3803 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3804 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3805}
3806
3807/**
021230d4 3808 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3809 * @adapter: board private structure
3810 **/
021230d4 3811static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3812{
3813 int i;
3814
021230d4 3815 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3816 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3817}
3818
3819void ixgbe_down(struct ixgbe_adapter *adapter)
3820{
3821 struct net_device *netdev = adapter->netdev;
7f821875 3822 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3823 u32 rxctrl;
7f821875
JB		 3824 u32 txdctl;
3825 int i, j;
b25ebfd2 3826 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 3827
3828 /* signal that we are down to the interrupt handler */
3829 set_bit(__IXGBE_DOWN, &adapter->state);
3830
767081ad
GR		 3831 /* disable receive for all VFs and wait one second */
3832 if (adapter->num_vfs) {
767081ad
GR		 3833 /* ping all the active vfs to let them know we are going down */
3834 ixgbe_ping_all_vfs(adapter);
581d1aa7 3835
767081ad
GR		 3836 /* Disable all VFTE/VFRE TX/RX */
3837 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3838
3839 /* Mark all the VFs as inactive */
3840 for (i = 0 ; i < adapter->num_vfs; i++)
3841 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3842 }
3843
9a799d71 3844 /* disable receives */
7f821875
JB		 3845 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3846 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3847
7f821875 3848 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3849 msleep(10);
3850
7f821875
JB		 3851 netif_tx_stop_all_queues(netdev);
3852
0a1f87cb
DS		 3853 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3854 del_timer_sync(&adapter->sfp_timer);
9a799d71 3855 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3856 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3857
c0dfb90e
JF		 3858 netif_carrier_off(netdev);
3859 netif_tx_disable(netdev);
3860
3861 ixgbe_irq_disable(adapter);
3862
3863 ixgbe_napi_disable_all(adapter);
3864
b25ebfd2
PW		 3865 /* Cleanup the affinity_hint CPU mask memory and callback */
3866 for (i = 0; i < num_q_vectors; i++) {
3867 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3868 /* clear the affinity_mask in the IRQ descriptor */
3869 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3870 /* release the CPU mask memory */
3871 free_cpumask_var(q_vector->affinity_mask);
3872 }
3873
c4cf55e5
PWJ		 3874 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3875 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3876 cancel_work_sync(&adapter->fdir_reinit_task);
3877
119fc60a
MC		 3878 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3879 cancel_work_sync(&adapter->check_overtemp_task);
3880
7f821875
JB		 3881 /* disable transmits in the hardware now that interrupts are off */
3882 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3883 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3884 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3885 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
e8e9f696 3886 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 3887 }
88512539
PW		 3888 /* Disable the Tx DMA engine on 82599 */
3889 if (hw->mac.type == ixgbe_mac_82599EB)
3890 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 3891 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3892 ~IXGBE_DMATXCTL_TE));
7f821875 3893
9f756f01
JF		 3894 /* power down the optics */
3895 if (hw->phy.multispeed_fiber)
3896 hw->mac.ops.disable_tx_laser(hw);
3897
9a713e7c
PW		 3898 /* clear n-tuple filters that are cached */
3899 ethtool_ntuple_flush(netdev);
3900
6f4a0e45
PL		 3901 if (!pci_channel_offline(adapter->pdev))
3902 ixgbe_reset(adapter);
9a799d71
AK		 3903 ixgbe_clean_all_tx_rings(adapter);
3904 ixgbe_clean_all_rx_rings(adapter);
3905
5dd2d332 3906#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3907 /* since we reset the hardware DCA settings were cleared */
e35ec126 3908 ixgbe_setup_dca(adapter);
96b0e0f6 3909#endif
9a799d71
AK		 3910}
3911
9a799d71 3912/**
021230d4
AV		 3913 * ixgbe_poll - NAPI Rx polling callback
3914 * @napi: structure for representing this polling device
3915 * @budget: how many packets driver is allowed to clean
3916 *
3917 * This function is used for legacy and MSI, NAPI mode
9a799d71 3918 **/
021230d4 3919static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3920{
9a1a69ad 3921 struct ixgbe_q_vector *q_vector =
e8e9f696 3922 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3923 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3924 int tx_clean_complete, work_done = 0;
9a799d71 3925
5dd2d332 3926#ifdef CONFIG_IXGBE_DCA
bd0362dd 3927 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3928 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3929 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3930 }
3931#endif
3932
4a0b9ca0
PW		 3933 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3934 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3935
9a1a69ad 3936 if (!tx_clean_complete)
d2c7ddd6
DM		 3937 work_done = budget;
3938
53e52c72
DM		 3939 /* If budget not fully consumed, exit the polling mode */
3940 if (work_done < budget) {
288379f0 3941 napi_complete(napi);
f7554a2b 3942 if (adapter->rx_itr_setting & 1)
f494e8fa 3943 ixgbe_set_itr(adapter);
d4f80882 3944 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3945 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3946 }
9a799d71
AK		 3947 return work_done;
3948}
3949
3950/**
3951 * ixgbe_tx_timeout - Respond to a Tx Hang
3952 * @netdev: network interface device structure
3953 **/
3954static void ixgbe_tx_timeout(struct net_device *netdev)
3955{
3956 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3957
3958 /* Do the reset outside of interrupt context */
3959 schedule_work(&adapter->reset_task);
3960}
3961
3962static void ixgbe_reset_task(struct work_struct *work)
3963{
3964 struct ixgbe_adapter *adapter;
3965 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3966
2f90b865
AD		 3967 /* If we're already down or resetting, just bail */
3968 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3969 test_bit(__IXGBE_RESETTING, &adapter->state))
3970 return;
3971
9a799d71
AK		 3972 adapter->tx_timeout_count++;
3973
dcd79aeb
TI		 3974 ixgbe_dump(adapter);
3975 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3976 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3977}
3978
bc97114d
PWJ		 3979#ifdef CONFIG_IXGBE_DCB
3980static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3981{
bc97114d 3982 bool ret = false;
0cefafad 3983 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3984
0cefafad
JB		 3985 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3986 return ret;
3987
3988 f->mask = 0x7 << 3;
3989 adapter->num_rx_queues = f->indices;
3990 adapter->num_tx_queues = f->indices;
3991 ret = true;
2f90b865 3992
bc97114d
PWJ		 3993 return ret;
3994}
3995#endif
3996
4df10466
JB		 3997/**
3998 * ixgbe_set_rss_queues: Allocate queues for RSS
3999 * @adapter: board private structure to initialize
4000 *
4001 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4002 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4003 *
4004 **/
bc97114d
PWJ		 4005static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4006{
4007 bool ret = false;
0cefafad 4008 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4009
4010 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4011 f->mask = 0xF;
4012 adapter->num_rx_queues = f->indices;
4013 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4014 ret = true;
4015 } else {
bc97114d 4016 ret = false;
b9804972
JB		 4017 }
4018
bc97114d
PWJ		 4019 return ret;
4020}
4021
c4cf55e5
PWJ		 4022/**
4023 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4024 * @adapter: board private structure to initialize
4025 *
4026 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4027 * to the original CPU that initiated the Tx session. This runs in addition
4028 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4029 * Rx load across CPUs using RSS.
4030 *
4031 **/
e8e9f696 4032static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4033{
4034 bool ret = false;
4035 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4036
4037 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4038 f_fdir->mask = 0;
4039
4040 /* Flow Director must have RSS enabled */
4041 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4042 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4043 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4044 adapter->num_tx_queues = f_fdir->indices;
4045 adapter->num_rx_queues = f_fdir->indices;
4046 ret = true;
4047 } else {
4048 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4049 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4050 }
4051 return ret;
4052}
4053
0331a832
YZ		 4054#ifdef IXGBE_FCOE
4055/**
4056 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4057 * @adapter: board private structure to initialize
4058 *
4059 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4060 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4061 * rx queues out of the max number of rx queues, instead, it is used as the
4062 * index of the first rx queue used by FCoE.
4063 *
4064 **/
4065static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4066{
4067 bool ret = false;
4068 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4069
4070 f->indices = min((int)num_online_cpus(), f->indices);
4071 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 4072 adapter->num_rx_queues = 1;
4073 adapter->num_tx_queues = 1;
0331a832
YZ		 4074#ifdef CONFIG_IXGBE_DCB
4075 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 4076 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 4077 ixgbe_set_dcb_queues(adapter);
4078 }
4079#endif
4080 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4081 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4082 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4083 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4084 ixgbe_set_fdir_queues(adapter);
4085 else
4086 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4087 }
4088 /* adding FCoE rx rings to the end */
4089 f->mask = adapter->num_rx_queues;
4090 adapter->num_rx_queues += f->indices;
8de8b2e6 4091 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4092
4093 ret = true;
4094 }
4095
4096 return ret;
4097}
4098
4099#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4100/**
4101 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4102 * @adapter: board private structure to initialize
4103 *
4104 * IOV doesn't actually use anything, so just NAK the
4105 * request for now and let the other queue routines
4106 * figure out what to do.
4107 */
4108static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4109{
4110 return false;
4111}
4112
4df10466
JB		 4113/*
4114 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4115 * @adapter: board private structure to initialize
4116 *
4117 * This is the top level queue allocation routine. The order here is very
4118 * important, starting with the "most" number of features turned on at once,
4119 * and ending with the smallest set of features. This way large combinations
4120 * can be allocated if they're turned on, and smaller combinations are the
4121 * fallthrough conditions.
4122 *
4123 **/
847f53ff 4124static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4125{
1cdd1ec8
GR		 4126 /* Start with base case */
4127 adapter->num_rx_queues = 1;
4128 adapter->num_tx_queues = 1;
4129 adapter->num_rx_pools = adapter->num_rx_queues;
4130 adapter->num_rx_queues_per_pool = 1;
4131
4132 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4133 goto done;
1cdd1ec8 4134
0331a832
YZ		 4135#ifdef IXGBE_FCOE
4136 if (ixgbe_set_fcoe_queues(adapter))
4137 goto done;
4138
4139#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4140#ifdef CONFIG_IXGBE_DCB
4141 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4142 goto done;
bc97114d
PWJ		 4143
4144#endif
c4cf55e5
PWJ		 4145 if (ixgbe_set_fdir_queues(adapter))
4146 goto done;
4147
bc97114d 4148 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4149 goto done;
4150
4151 /* fallback to base case */
4152 adapter->num_rx_queues = 1;
4153 adapter->num_tx_queues = 1;
4154
4155done:
847f53ff 4156 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4157 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4158 return netif_set_real_num_rx_queues(adapter->netdev,
4159 adapter->num_rx_queues);
b9804972
JB		 4160}
4161
021230d4 4162static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4163 int vectors)
021230d4
AV		 4164{
4165 int err, vector_threshold;
4166
4167 /* We'll want at least 3 (vector_threshold):
4168 * 1) TxQ[0] Cleanup
4169 * 2) RxQ[0] Cleanup
4170 * 3) Other (Link Status Change, etc.)
4171 * 4) TCP Timer (optional)
4172 */
4173 vector_threshold = MIN_MSIX_COUNT;
4174
4175 /* The more we get, the more we will assign to Tx/Rx Cleanup
4176 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4177 * Right now, we simply care about how many we'll get; we'll
4178 * set them up later while requesting irq's.
4179 */
4180 while (vectors >= vector_threshold) {
4181 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4182 vectors);
021230d4
AV		 4183 if (!err) /* Success in acquiring all requested vectors. */
4184 break;
4185 else if (err < 0)
4186 vectors = 0; /* Nasty failure, quit now */
4187 else /* err == number of vectors we should try again with */
4188 vectors = err;
4189 }
4190
4191 if (vectors < vector_threshold) {
4192 /* Can't allocate enough MSI-X interrupts? Oh well.
4193 * This just means we'll go with either a single MSI
4194 * vector or fall back to legacy interrupts.
4195 */
849c4542
ET		 4196 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4197 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4198 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4199 kfree(adapter->msix_entries);
4200 adapter->msix_entries = NULL;
021230d4
AV		 4201 } else {
4202 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4203 /*
4204 * Adjust for only the vectors we'll use, which is minimum
4205 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4206 * vectors we were allocated.
4207 */
4208 adapter->num_msix_vectors = min(vectors,
e8e9f696 4209 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4210 }
4211}
4212
021230d4 4213/**
bc97114d 4214 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4215 * @adapter: board private structure to initialize
4216 *
bc97114d
PWJ		 4217 * Cache the descriptor ring offsets for RSS to the assigned rings.
4218 *
021230d4 4219 **/
bc97114d 4220static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4221{
bc97114d
PWJ		 4222 int i;
4223 bool ret = false;
4224
4225 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4226 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4227 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4228 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4229 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4230 ret = true;
4231 } else {
4232 ret = false;
4233 }
4234
4235 return ret;
4236}
4237
4238#ifdef CONFIG_IXGBE_DCB
4239/**
4240 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4241 * @adapter: board private structure to initialize
4242 *
4243 * Cache the descriptor ring offsets for DCB to the assigned rings.
4244 *
4245 **/
4246static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4247{
4248 int i;
4249 bool ret = false;
4250 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4251
4252 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4253 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4254 /* the number of queues is assumed to be symmetric */
4255 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4256 adapter->rx_ring[i]->reg_idx = i << 3;
4257 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4258 }
bc97114d 4259 ret = true;
e8e26350 4260 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4261 if (dcb_i == 8) {
4262 /*
4263 * Tx TC0 starts at: descriptor queue 0
4264 * Tx TC1 starts at: descriptor queue 32
4265 * Tx TC2 starts at: descriptor queue 64
4266 * Tx TC3 starts at: descriptor queue 80
4267 * Tx TC4 starts at: descriptor queue 96
4268 * Tx TC5 starts at: descriptor queue 104
4269 * Tx TC6 starts at: descriptor queue 112
4270 * Tx TC7 starts at: descriptor queue 120
4271 *
4272 * Rx TC0-TC7 are offset by 16 queues each
4273 */
4274 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4275 adapter->tx_ring[i]->reg_idx = i << 5;
4276 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4277 }
4278 for ( ; i < 5; i++) {
4a0b9ca0 4279 adapter->tx_ring[i]->reg_idx =
e8e9f696 4280 ((i + 2) << 4);
4a0b9ca0 4281 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4282 }
4283 for ( ; i < dcb_i; i++) {
4a0b9ca0 4284 adapter->tx_ring[i]->reg_idx =
e8e9f696 4285 ((i + 8) << 3);
4a0b9ca0 4286 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4287 }
4288
4289 ret = true;
4290 } else if (dcb_i == 4) {
4291 /*
4292 * Tx TC0 starts at: descriptor queue 0
4293 * Tx TC1 starts at: descriptor queue 64
4294 * Tx TC2 starts at: descriptor queue 96
4295 * Tx TC3 starts at: descriptor queue 112
4296 *
4297 * Rx TC0-TC3 are offset by 32 queues each
4298 */
4a0b9ca0
PW		 4299 adapter->tx_ring[0]->reg_idx = 0;
4300 adapter->tx_ring[1]->reg_idx = 64;
4301 adapter->tx_ring[2]->reg_idx = 96;
4302 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4303 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4304 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4305
4306 ret = true;
4307 } else {
4308 ret = false;
e8e26350 4309 }
bc97114d
PWJ		 4310 } else {
4311 ret = false;
021230d4 4312 }
bc97114d
PWJ		 4313 } else {
4314 ret = false;
021230d4 4315 }
bc97114d
PWJ		 4316
4317 return ret;
4318}
4319#endif
4320
c4cf55e5
PWJ		 4321/**
4322 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4323 * @adapter: board private structure to initialize
4324 *
4325 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4326 *
4327 **/
e8e9f696 4328static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4329{
4330 int i;
4331 bool ret = false;
4332
4333 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4334 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4335 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4336 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4337 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4338 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4339 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4340 ret = true;
4341 }
4342
4343 return ret;
4344}
4345
0331a832
YZ		 4346#ifdef IXGBE_FCOE
4347/**
4348 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4349 * @adapter: board private structure to initialize
4350 *
4351 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4352 *
4353 */
4354static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4355{
8de8b2e6 4356 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4357 bool ret = false;
4358 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4359
4360 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4361#ifdef CONFIG_IXGBE_DCB
4362 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4363 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4364
0331a832 4365 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4366 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4367 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4368 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4369 /*
4370 * In 82599, the number of Tx queues for each traffic
4371 * class for both 8-TC and 4-TC modes are:
4372 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4373 * 8 TCs: 32 32 16 16 8 8 8 8
4374 * 4 TCs: 64 64 32 32
4375 * We have max 8 queues for FCoE, where 8 the is
4376 * FCoE redirection table size. If TC for FCoE is
4377 * less than or equal to TC3, we have enough queues
4378 * to add max of 8 queues for FCoE, so we start FCoE
4379 * tx descriptor from the next one, i.e., reg_idx + 1.
4380 * If TC for FCoE is above TC3, implying 8 TC mode,
4381 * and we need 8 for FCoE, we have to take all queues
4382 * in that traffic class for FCoE.
4383 */
4384 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4385 fcoe_tx_i--;
0331a832
YZ		 4386 }
4387#endif /* CONFIG_IXGBE_DCB */
4388 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4389 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4390 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4391 ixgbe_cache_ring_fdir(adapter);
4392 else
4393 ixgbe_cache_ring_rss(adapter);
4394
8de8b2e6
YZ		 4395 fcoe_rx_i = f->mask;
4396 fcoe_tx_i = f->mask;
4397 }
4398 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4399 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4400 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4401 }
0331a832
YZ		 4402 ret = true;
4403 }
4404 return ret;
4405}
4406
4407#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4408/**
4409 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4410 * @adapter: board private structure to initialize
4411 *
4412 * SR-IOV doesn't use any descriptor rings but changes the default if
4413 * no other mapping is used.
4414 *
4415 */
4416static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4417{
4a0b9ca0
PW		 4418 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4419 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4420 if (adapter->num_vfs)
4421 return true;
4422 else
4423 return false;
4424}
4425
bc97114d
PWJ		 4426/**
4427 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4428 * @adapter: board private structure to initialize
4429 *
4430 * Once we know the feature-set enabled for the device, we'll cache
4431 * the register offset the descriptor ring is assigned to.
4432 *
4433 * Note, the order the various feature calls is important. It must start with
4434 * the "most" features enabled at the same time, then trickle down to the
4435 * least amount of features turned on at once.
4436 **/
4437static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4438{
4439 /* start with default case */
4a0b9ca0
PW		 4440 adapter->rx_ring[0]->reg_idx = 0;
4441 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4442
1cdd1ec8
GR		 4443 if (ixgbe_cache_ring_sriov(adapter))
4444 return;
4445
0331a832
YZ		 4446#ifdef IXGBE_FCOE
4447 if (ixgbe_cache_ring_fcoe(adapter))
4448 return;
4449
4450#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4451#ifdef CONFIG_IXGBE_DCB
4452 if (ixgbe_cache_ring_dcb(adapter))
4453 return;
4454
4455#endif
c4cf55e5
PWJ		 4456 if (ixgbe_cache_ring_fdir(adapter))
4457 return;
4458
bc97114d
PWJ		 4459 if (ixgbe_cache_ring_rss(adapter))
4460 return;
021230d4
AV		 4461}
4462
9a799d71
AK		 4463/**
4464 * ixgbe_alloc_queues - Allocate memory for all rings
4465 * @adapter: board private structure to initialize
4466 *
4467 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4468 * number of queues at compile-time. The polling_netdev array is
4469 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4470 **/
2f90b865 4471static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4472{
4473 int i;
4a0b9ca0 4474 int orig_node = adapter->node;
9a799d71 4475
021230d4 4476 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4477 struct ixgbe_ring *ring = adapter->tx_ring[i];
4478 if (orig_node == -1) {
4479 int cur_node = next_online_node(adapter->node);
4480 if (cur_node == MAX_NUMNODES)
4481 cur_node = first_online_node;
4482 adapter->node = cur_node;
4483 }
4484 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4485 adapter->node);
4a0b9ca0
PW		 4486 if (!ring)
4487 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4488 if (!ring)
4489 goto err_tx_ring_allocation;
4490 ring->count = adapter->tx_ring_count;
4491 ring->queue_index = i;
4492 ring->numa_node = adapter->node;
4493
4494 adapter->tx_ring[i] = ring;
021230d4 4495 }
b9804972 4496
4a0b9ca0
PW		 4497 /* Restore the adapter's original node */
4498 adapter->node = orig_node;
4499
9a799d71 4500 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4501 struct ixgbe_ring *ring = adapter->rx_ring[i];
4502 if (orig_node == -1) {
4503 int cur_node = next_online_node(adapter->node);
4504 if (cur_node == MAX_NUMNODES)
4505 cur_node = first_online_node;
4506 adapter->node = cur_node;
4507 }
4508 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4509 adapter->node);
4a0b9ca0
PW		 4510 if (!ring)
4511 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4512 if (!ring)
4513 goto err_rx_ring_allocation;
4514 ring->count = adapter->rx_ring_count;
4515 ring->queue_index = i;
4516 ring->numa_node = adapter->node;
4517
4518 adapter->rx_ring[i] = ring;
021230d4
AV		 4519 }
4520
4a0b9ca0
PW		 4521 /* Restore the adapter's original node */
4522 adapter->node = orig_node;
4523
021230d4
AV		 4524 ixgbe_cache_ring_register(adapter);
4525
4526 return 0;
4527
4528err_rx_ring_allocation:
4a0b9ca0
PW		 4529 for (i = 0; i < adapter->num_tx_queues; i++)
4530 kfree(adapter->tx_ring[i]);
021230d4
AV		 4531err_tx_ring_allocation:
4532 return -ENOMEM;
4533}
4534
4535/**
4536 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4537 * @adapter: board private structure to initialize
4538 *
4539 * Attempt to configure the interrupts using the best available
4540 * capabilities of the hardware and the kernel.
4541 **/
feea6a57 4542static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4543{
8be0e467 4544 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4545 int err = 0;
4546 int vector, v_budget;
4547
4548 /*
4549 * It's easy to be greedy for MSI-X vectors, but it really
4550 * doesn't do us much good if we have a lot more vectors
4551 * than CPU's. So let's be conservative and only ask for
342bde1b 4552 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4553 */
4554 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4555 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4556
4557 /*
4558 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4559 * hw.mac->max_msix_vectors vectors. With features
4560 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4561 * descriptor queues supported by our device. Thus, we cap it off in
4562 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4563 */
8be0e467 4564 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4565
4566 /* A failure in MSI-X entry allocation isn't fatal, but it does
4567 * mean we disable MSI-X capabilities of the adapter. */
4568 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4569 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4570 if (adapter->msix_entries) {
4571 for (vector = 0; vector < v_budget; vector++)
4572 adapter->msix_entries[vector].entry = vector;
021230d4 4573
7a921c93 4574 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4575
7a921c93
AD		 4576 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4577 goto out;
4578 }
26d27844 4579
7a921c93
AD		 4580 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4581 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4582 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4583 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4584 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4585 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4586 ixgbe_disable_sriov(adapter);
4587
847f53ff
BH		 4588 err = ixgbe_set_num_queues(adapter);
4589 if (err)
4590 return err;
021230d4 4591
021230d4
AV		 4592 err = pci_enable_msi(adapter->pdev);
4593 if (!err) {
4594 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4595 } else {
849c4542
ET		 4596 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4597 "Unable to allocate MSI interrupt, "
4598 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4599 /* reset err */
4600 err = 0;
4601 }
4602
4603out:
021230d4
AV		 4604 return err;
4605}
4606
7a921c93
AD		 4607/**
4608 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4609 * @adapter: board private structure to initialize
4610 *
4611 * We allocate one q_vector per queue interrupt. If allocation fails we
4612 * return -ENOMEM.
4613 **/
4614static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4615{
4616 int q_idx, num_q_vectors;
4617 struct ixgbe_q_vector *q_vector;
4618 int napi_vectors;
4619 int (*poll)(struct napi_struct *, int);
4620
4621 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4622 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4623 napi_vectors = adapter->num_rx_queues;
91281fd3 4624 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4625 } else {
4626 num_q_vectors = 1;
4627 napi_vectors = 1;
4628 poll = &ixgbe_poll;
4629 }
4630
4631 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4632 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4633 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4634 if (!q_vector)
4635 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4636 GFP_KERNEL);
7a921c93
AD		 4637 if (!q_vector)
4638 goto err_out;
4639 q_vector->adapter = adapter;
f7554a2b
NS		 4640 if (q_vector->txr_count && !q_vector->rxr_count)
4641 q_vector->eitr = adapter->tx_eitr_param;
4642 else
4643 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4644 q_vector->v_idx = q_idx;
91281fd3 4645 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4646 adapter->q_vector[q_idx] = q_vector;
4647 }
4648
4649 return 0;
4650
4651err_out:
4652 while (q_idx) {
4653 q_idx--;
4654 q_vector = adapter->q_vector[q_idx];
4655 netif_napi_del(&q_vector->napi);
4656 kfree(q_vector);
4657 adapter->q_vector[q_idx] = NULL;
4658 }
4659 return -ENOMEM;
4660}
4661
4662/**
4663 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4664 * @adapter: board private structure to initialize
4665 *
4666 * This function frees the memory allocated to the q_vectors. In addition if
4667 * NAPI is enabled it will delete any references to the NAPI struct prior
4668 * to freeing the q_vector.
4669 **/
4670static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4671{
4672 int q_idx, num_q_vectors;
7a921c93 4673
91281fd3 4674 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4675 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4676 else
7a921c93 4677 num_q_vectors = 1;
7a921c93
AD		 4678
4679 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4680 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4681 adapter->q_vector[q_idx] = NULL;
91281fd3 4682 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4683 kfree(q_vector);
4684 }
4685}
4686
7b25cdba 4687static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4688{
4689 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4690 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4691 pci_disable_msix(adapter->pdev);
4692 kfree(adapter->msix_entries);
4693 adapter->msix_entries = NULL;
4694 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4695 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4696 pci_disable_msi(adapter->pdev);
4697 }
021230d4
AV		 4698}
4699
4700/**
4701 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4702 * @adapter: board private structure to initialize
4703 *
4704 * We determine which interrupt scheme to use based on...
4705 * - Kernel support (MSI, MSI-X)
4706 * - which can be user-defined (via MODULE_PARAM)
4707 * - Hardware queue count (num_*_queues)
4708 * - defined by miscellaneous hardware support/features (RSS, etc.)
4709 **/
2f90b865 4710int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4711{
4712 int err;
4713
4714 /* Number of supported queues */
847f53ff
BH		 4715 err = ixgbe_set_num_queues(adapter);
4716 if (err)
4717 return err;
021230d4 4718
021230d4
AV		 4719 err = ixgbe_set_interrupt_capability(adapter);
4720 if (err) {
849c4542 4721 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4722 goto err_set_interrupt;
9a799d71
AK		 4723 }
4724
7a921c93
AD		 4725 err = ixgbe_alloc_q_vectors(adapter);
4726 if (err) {
849c4542 4727 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4728 goto err_alloc_q_vectors;
4729 }
4730
4731 err = ixgbe_alloc_queues(adapter);
4732 if (err) {
849c4542 4733 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4734 goto err_alloc_queues;
4735 }
4736
849c4542 4737 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4738 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4739 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4740
4741 set_bit(__IXGBE_DOWN, &adapter->state);
4742
9a799d71 4743 return 0;
021230d4 4744
7a921c93
AD		 4745err_alloc_queues:
4746 ixgbe_free_q_vectors(adapter);
4747err_alloc_q_vectors:
4748 ixgbe_reset_interrupt_capability(adapter);
021230d4 4749err_set_interrupt:
7a921c93
AD		 4750 return err;
4751}
4752
4753/**
4754 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4755 * @adapter: board private structure to clear interrupt scheme on
4756 *
4757 * We go through and clear interrupt specific resources and reset the structure
4758 * to pre-load conditions
4759 **/
4760void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4761{
4a0b9ca0
PW		 4762 int i;
4763
4764 for (i = 0; i < adapter->num_tx_queues; i++) {
4765 kfree(adapter->tx_ring[i]);
4766 adapter->tx_ring[i] = NULL;
4767 }
4768 for (i = 0; i < adapter->num_rx_queues; i++) {
4769 kfree(adapter->rx_ring[i]);
4770 adapter->rx_ring[i] = NULL;
4771 }
7a921c93
AD		 4772
4773 ixgbe_free_q_vectors(adapter);
4774 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4775}
4776
c4900be0
DS		 4777/**
4778 * ixgbe_sfp_timer - worker thread to find a missing module
4779 * @data: pointer to our adapter struct
4780 **/
4781static void ixgbe_sfp_timer(unsigned long data)
4782{
4783 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4784
4df10466
JB		 4785 /*
4786 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4787 * delays that sfp+ detection requires
4788 */
4789 schedule_work(&adapter->sfp_task);
4790}
4791
4792/**
4793 * ixgbe_sfp_task - worker thread to find a missing module
4794 * @work: pointer to work_struct containing our data
4795 **/
4796static void ixgbe_sfp_task(struct work_struct *work)
4797{
4798 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 4799 struct ixgbe_adapter,
4800 sfp_task);
c4900be0
DS		 4801 struct ixgbe_hw *hw = &adapter->hw;
4802
4803 if ((hw->phy.type == ixgbe_phy_nl) &&
4804 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4805 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4806 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4807 goto reschedule;
4808 ret = hw->phy.ops.reset(hw);
4809 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4810 e_dev_err("failed to initialize because an unsupported "
4811 "SFP+ module type was detected.\n");
4812 e_dev_err("Reload the driver after installing a "
4813 "supported module.\n");
c4900be0
DS		 4814 unregister_netdev(adapter->netdev);
4815 } else {
396e799c 4816 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4817 }
4818 /* don't need this routine any more */
4819 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4820 }
4821 return;
4822reschedule:
4823 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4824 mod_timer(&adapter->sfp_timer,
e8e9f696 4825 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 4826}
4827
9a799d71
AK		 4828/**
4829 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4830 * @adapter: board private structure to initialize
4831 *
4832 * ixgbe_sw_init initializes the Adapter private data structure.
4833 * Fields are initialized based on PCI device information and
4834 * OS network device settings (MTU size).
4835 **/
4836static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4837{
4838 struct ixgbe_hw *hw = &adapter->hw;
4839 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4840 struct net_device *dev = adapter->netdev;
021230d4 4841 unsigned int rss;
7a6b6f51 4842#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4843 int j;
4844 struct tc_configuration *tc;
4845#endif
021230d4 4846
c44ade9e
JB		 4847 /* PCI config space info */
4848
4849 hw->vendor_id = pdev->vendor;
4850 hw->device_id = pdev->device;
4851 hw->revision_id = pdev->revision;
4852 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4853 hw->subsystem_device_id = pdev->subsystem_device;
4854
021230d4
AV		 4855 /* Set capability flags */
4856 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4857 adapter->ring_feature[RING_F_RSS].indices = rss;
4858 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4859 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4860 if (hw->mac.type == ixgbe_mac_82598EB) {
4861 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4862 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4863 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4864 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4865 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4866 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4867 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4868 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4869 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4870 if (dev->features & NETIF_F_NTUPLE) {
4871 /* Flow Director perfect filter enabled */
4872 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4873 adapter->atr_sample_rate = 0;
4874 spin_lock_init(&adapter->fdir_perfect_lock);
4875 } else {
4876 /* Flow Director hash filters enabled */
4877 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4878 adapter->atr_sample_rate = 20;
4879 }
c4cf55e5 4880 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4881 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4882 adapter->fdir_pballoc = 0;
eacd73f7 4883#ifdef IXGBE_FCOE
0d551589
YZ		 4884 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4885 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4886 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4887#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4888 /* Default traffic class to use for FCoE */
4889 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4890 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4891#endif
eacd73f7 4892#endif /* IXGBE_FCOE */
f8212f97 4893 }
2f90b865 4894
7a6b6f51 4895#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4896 /* Configure DCB traffic classes */
4897 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4898 tc = &adapter->dcb_cfg.tc_config[j];
4899 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4900 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4901 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4902 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4903 tc->dcb_pfc = pfc_disabled;
4904 }
4905 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4906 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4907 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4908 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4909 adapter->dcb_cfg.round_robin_enable = false;
4910 adapter->dcb_set_bitmap = 0x00;
4911 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e8e9f696 4912 adapter->ring_feature[RING_F_DCB].indices);
2f90b865
AD		 4913
4914#endif
9a799d71
AK		 4915
4916 /* default flow control settings */
cd7664f6 4917 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4918 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4919#ifdef CONFIG_DCB
4920 adapter->last_lfc_mode = hw->fc.current_mode;
4921#endif
2b9ade93
JB		 4922 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4923 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4924 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4925 hw->fc.send_xon = true;
71fd570b 4926 hw->fc.disable_fc_autoneg = false;
9a799d71 4927
30efa5a3 4928 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4929 adapter->rx_itr_setting = 1;
4930 adapter->rx_eitr_param = 20000;
4931 adapter->tx_itr_setting = 1;
4932 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4933
4934 /* set defaults for eitr in MegaBytes */
4935 adapter->eitr_low = 10;
4936 adapter->eitr_high = 20;
4937
4938 /* set default ring sizes */
4939 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4940 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4941
9a799d71 4942 /* initialize eeprom parameters */
c44ade9e 4943 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4944 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4945 return -EIO;
4946 }
4947
021230d4 4948 /* enable rx csum by default */
9a799d71
AK		 4949 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4950
1a6c14a2
JB		 4951 /* get assigned NUMA node */
4952 adapter->node = dev_to_node(&pdev->dev);
4953
9a799d71
AK		 4954 set_bit(__IXGBE_DOWN, &adapter->state);
4955
4956 return 0;
4957}
4958
4959/**
4960 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4961 * @adapter: board private structure
3a581073 4962 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4963 *
4964 * Return 0 on success, negative on failure
4965 **/
4966int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e8e9f696 4967 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4968{
4969 struct pci_dev *pdev = adapter->pdev;
4970 int size;
4971
3a581073 4972 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4973 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4974 if (!tx_ring->tx_buffer_info)
4975 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4976 if (!tx_ring->tx_buffer_info)
4977 goto err;
3a581073 4978 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4979
4980 /* round up to nearest 4K */
12207e49 4981 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4982 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4983
1b507730
NN		 4984 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4985 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4986 if (!tx_ring->desc)
4987 goto err;
9a799d71 4988
3a581073
JB		 4989 tx_ring->next_to_use = 0;
4990 tx_ring->next_to_clean = 0;
4991 tx_ring->work_limit = tx_ring->count;
9a799d71 4992 return 0;
e01c31a5
JB		 4993
4994err:
4995 vfree(tx_ring->tx_buffer_info);
4996 tx_ring->tx_buffer_info = NULL;
396e799c 4997 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4998 return -ENOMEM;
9a799d71
AK		 4999}
5000
69888674
AD		 5001/**
5002 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5003 * @adapter: board private structure
5004 *
5005 * If this function returns with an error, then it's possible one or
5006 * more of the rings is populated (while the rest are not). It is the
5007 * callers duty to clean those orphaned rings.
5008 *
5009 * Return 0 on success, negative on failure
5010 **/
5011static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5012{
5013 int i, err = 0;
5014
5015 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5016 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 5017 if (!err)
5018 continue;
396e799c 5019 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5020 break;
5021 }
5022
5023 return err;
5024}
5025
9a799d71
AK		 5026/**
5027 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5028 * @adapter: board private structure
3a581073 5029 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5030 *
5031 * Returns 0 on success, negative on failure
5032 **/
5033int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5034 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5035{
5036 struct pci_dev *pdev = adapter->pdev;
021230d4 5037 int size;
9a799d71 5038
3a581073 5039 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 5040 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
5041 if (!rx_ring->rx_buffer_info)
5042 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 5043 if (!rx_ring->rx_buffer_info) {
396e799c
ET		 5044 e_err(probe, "vmalloc allocation failed for the Rx "
5045 "descriptor ring\n");
177db6ff 5046 goto alloc_failed;
9a799d71 5047 }
3a581073 5048 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 5049
9a799d71 5050 /* Round up to nearest 4K */
3a581073
JB		 5051 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5052 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5053
1b507730
NN		 5054 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
5055 &rx_ring->dma, GFP_KERNEL);
9a799d71 5056
3a581073 5057 if (!rx_ring->desc) {
396e799c
ET		 5058 e_err(probe, "Memory allocation failed for the Rx "
5059 "descriptor ring\n");
3a581073 5060 vfree(rx_ring->rx_buffer_info);
177db6ff 5061 goto alloc_failed;
9a799d71
AK		 5062 }
5063
3a581073
JB		 5064 rx_ring->next_to_clean = 0;
5065 rx_ring->next_to_use = 0;
9a799d71
AK		 5066
5067 return 0;
177db6ff
MC		 5068
5069alloc_failed:
177db6ff 5070 return -ENOMEM;
9a799d71
AK		 5071}
5072
69888674
AD		 5073/**
5074 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5075 * @adapter: board private structure
5076 *
5077 * If this function returns with an error, then it's possible one or
5078 * more of the rings is populated (while the rest are not). It is the
5079 * callers duty to clean those orphaned rings.
5080 *
5081 * Return 0 on success, negative on failure
5082 **/
5083
5084static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5085{
5086 int i, err = 0;
5087
5088 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 5089 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 5090 if (!err)
5091 continue;
396e799c 5092 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5093 break;
5094 }
5095
5096 return err;
5097}
5098
9a799d71
AK		 5099/**
5100 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5101 * @adapter: board private structure
5102 * @tx_ring: Tx descriptor ring for a specific queue
5103 *
5104 * Free all transmit software resources
5105 **/
c431f97e 5106void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5107 struct ixgbe_ring *tx_ring)
9a799d71
AK		 5108{
5109 struct pci_dev *pdev = adapter->pdev;
5110
5111 ixgbe_clean_tx_ring(adapter, tx_ring);
5112
5113 vfree(tx_ring->tx_buffer_info);
5114 tx_ring->tx_buffer_info = NULL;
5115
1b507730
NN		 5116 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5117 tx_ring->dma);
9a799d71
AK		 5118
5119 tx_ring->desc = NULL;
5120}
5121
5122/**
5123 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5124 * @adapter: board private structure
5125 *
5126 * Free all transmit software resources
5127 **/
5128static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5129{
5130 int i;
5131
5132 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 5133 if (adapter->tx_ring[i]->desc)
5134 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 5135}
5136
5137/**
b4617240 5138 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5139 * @adapter: board private structure
5140 * @rx_ring: ring to clean the resources from
5141 *
5142 * Free all receive software resources
5143 **/
c431f97e 5144void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5145 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5146{
5147 struct pci_dev *pdev = adapter->pdev;
5148
5149 ixgbe_clean_rx_ring(adapter, rx_ring);
5150
5151 vfree(rx_ring->rx_buffer_info);
5152 rx_ring->rx_buffer_info = NULL;
5153
1b507730
NN		 5154 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5155 rx_ring->dma);
9a799d71
AK		 5156
5157 rx_ring->desc = NULL;
5158}
5159
5160/**
5161 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5162 * @adapter: board private structure
5163 *
5164 * Free all receive software resources
5165 **/
5166static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5167{
5168 int i;
5169
5170 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 5171 if (adapter->rx_ring[i]->desc)
5172 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 5173}
5174
9a799d71
AK		 5175/**
5176 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5177 * @netdev: network interface device structure
5178 * @new_mtu: new value for maximum frame size
5179 *
5180 * Returns 0 on success, negative on failure
5181 **/
5182static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5183{
5184 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5185 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5186
42c783c5
JB		 5187 /* MTU < 68 is an error and causes problems on some kernels */
5188 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5189 return -EINVAL;
5190
396e799c 5191 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5192 /* must set new MTU before calling down or up */
9a799d71
AK		 5193 netdev->mtu = new_mtu;
5194
d4f80882
AV		 5195 if (netif_running(netdev))
5196 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5197
5198 return 0;
5199}
5200
5201/**
5202 * ixgbe_open - Called when a network interface is made active
5203 * @netdev: network interface device structure
5204 *
5205 * Returns 0 on success, negative value on failure
5206 *
5207 * The open entry point is called when a network interface is made
5208 * active by the system (IFF_UP). At this point all resources needed
5209 * for transmit and receive operations are allocated, the interrupt
5210 * handler is registered with the OS, the watchdog timer is started,
5211 * and the stack is notified that the interface is ready.
5212 **/
5213static int ixgbe_open(struct net_device *netdev)
5214{
5215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5216 int err;
4bebfaa5
AK		 5217
5218 /* disallow open during test */
5219 if (test_bit(__IXGBE_TESTING, &adapter->state))
5220 return -EBUSY;
9a799d71 5221
54386467
JB		 5222 netif_carrier_off(netdev);
5223
9a799d71
AK		 5224 /* allocate transmit descriptors */
5225 err = ixgbe_setup_all_tx_resources(adapter);
5226 if (err)
5227 goto err_setup_tx;
5228
9a799d71
AK		 5229 /* allocate receive descriptors */
5230 err = ixgbe_setup_all_rx_resources(adapter);
5231 if (err)
5232 goto err_setup_rx;
5233
5234 ixgbe_configure(adapter);
5235
021230d4 5236 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5237 if (err)
5238 goto err_req_irq;
5239
9a799d71
AK		 5240 err = ixgbe_up_complete(adapter);
5241 if (err)
5242 goto err_up;
5243
d55b53ff
JK		 5244 netif_tx_start_all_queues(netdev);
5245
9a799d71
AK		 5246 return 0;
5247
5248err_up:
5eba3699 5249 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5250 ixgbe_free_irq(adapter);
5251err_req_irq:
9a799d71 5252err_setup_rx:
a20a1199 5253 ixgbe_free_all_rx_resources(adapter);
9a799d71 5254err_setup_tx:
a20a1199 5255 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5256 ixgbe_reset(adapter);
5257
5258 return err;
5259}
5260
5261/**
5262 * ixgbe_close - Disables a network interface
5263 * @netdev: network interface device structure
5264 *
5265 * Returns 0, this is not allowed to fail
5266 *
5267 * The close entry point is called when an interface is de-activated
5268 * by the OS. The hardware is still under the drivers control, but
5269 * needs to be disabled. A global MAC reset is issued to stop the
5270 * hardware, and all transmit and receive resources are freed.
5271 **/
5272static int ixgbe_close(struct net_device *netdev)
5273{
5274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5275
5276 ixgbe_down(adapter);
5277 ixgbe_free_irq(adapter);
5278
5279 ixgbe_free_all_tx_resources(adapter);
5280 ixgbe_free_all_rx_resources(adapter);
5281
5eba3699 5282 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5283
5284 return 0;
5285}
5286
b3c8b4ba
AD		 5287#ifdef CONFIG_PM
5288static int ixgbe_resume(struct pci_dev *pdev)
5289{
5290 struct net_device *netdev = pci_get_drvdata(pdev);
5291 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5292 u32 err;
5293
5294 pci_set_power_state(pdev, PCI_D0);
5295 pci_restore_state(pdev);
656ab817
DS		 5296 /*
5297 * pci_restore_state clears dev->state_saved so call
5298 * pci_save_state to restore it.
5299 */
5300 pci_save_state(pdev);
9ce77666 5301
5302 err = pci_enable_device_mem(pdev);
b3c8b4ba 5303 if (err) {
849c4542 5304 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5305 return err;
5306 }
5307 pci_set_master(pdev);
5308
dd4d8ca6 5309 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5310
5311 err = ixgbe_init_interrupt_scheme(adapter);
5312 if (err) {
849c4542 5313 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5314 return err;
5315 }
5316
b3c8b4ba
AD		 5317 ixgbe_reset(adapter);
5318
495dce12
WJP		 5319 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5320
b3c8b4ba
AD		 5321 if (netif_running(netdev)) {
5322 err = ixgbe_open(adapter->netdev);
5323 if (err)
5324 return err;
5325 }
5326
5327 netif_device_attach(netdev);
5328
5329 return 0;
5330}
b3c8b4ba 5331#endif /* CONFIG_PM */
9d8d05ae
RW		 5332
5333static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5334{
5335 struct net_device *netdev = pci_get_drvdata(pdev);
5336 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5337 struct ixgbe_hw *hw = &adapter->hw;
5338 u32 ctrl, fctrl;
5339 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5340#ifdef CONFIG_PM
5341 int retval = 0;
5342#endif
5343
5344 netif_device_detach(netdev);
5345
5346 if (netif_running(netdev)) {
5347 ixgbe_down(adapter);
5348 ixgbe_free_irq(adapter);
5349 ixgbe_free_all_tx_resources(adapter);
5350 ixgbe_free_all_rx_resources(adapter);
5351 }
b3c8b4ba
AD		 5352
5353#ifdef CONFIG_PM
5354 retval = pci_save_state(pdev);
5355 if (retval)
5356 return retval;
4df10466 5357
b3c8b4ba 5358#endif
e8e26350
PW		 5359 if (wufc) {
5360 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5361
e8e26350
PW		 5362 /* turn on all-multi mode if wake on multicast is enabled */
5363 if (wufc & IXGBE_WUFC_MC) {
5364 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5365 fctrl |= IXGBE_FCTRL_MPE;
5366 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5367 }
5368
5369 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5370 ctrl |= IXGBE_CTRL_GIO_DIS;
5371 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5372
5373 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5374 } else {
5375 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5376 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5377 }
5378
dd4d8ca6
DS		 5379 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5380 pci_wake_from_d3(pdev, true);
5381 else
5382 pci_wake_from_d3(pdev, false);
b3c8b4ba 5383
9d8d05ae
RW		 5384 *enable_wake = !!wufc;
5385
fa378134
AG		 5386 ixgbe_clear_interrupt_scheme(adapter);
5387
b3c8b4ba
AD		 5388 ixgbe_release_hw_control(adapter);
5389
5390 pci_disable_device(pdev);
5391
9d8d05ae
RW		 5392 return 0;
5393}
5394
5395#ifdef CONFIG_PM
5396static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5397{
5398 int retval;
5399 bool wake;
5400
5401 retval = __ixgbe_shutdown(pdev, &wake);
5402 if (retval)
5403 return retval;
5404
5405 if (wake) {
5406 pci_prepare_to_sleep(pdev);
5407 } else {
5408 pci_wake_from_d3(pdev, false);
5409 pci_set_power_state(pdev, PCI_D3hot);
5410 }
b3c8b4ba
AD		 5411
5412 return 0;
5413}
9d8d05ae 5414#endif /* CONFIG_PM */
b3c8b4ba
AD		 5415
5416static void ixgbe_shutdown(struct pci_dev *pdev)
5417{
9d8d05ae
RW		 5418 bool wake;
5419
5420 __ixgbe_shutdown(pdev, &wake);
5421
5422 if (system_state == SYSTEM_POWER_OFF) {
5423 pci_wake_from_d3(pdev, wake);
5424 pci_set_power_state(pdev, PCI_D3hot);
5425 }
b3c8b4ba
AD		 5426}
5427
9a799d71
AK		 5428/**
5429 * ixgbe_update_stats - Update the board statistics counters.
5430 * @adapter: board private structure
5431 **/
5432void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5433{
2d86f139 5434 struct net_device *netdev = adapter->netdev;
9a799d71 5435 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5436 u64 total_mpc = 0;
5437 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5438 u64 non_eop_descs = 0, restart_queue = 0;
7ca647bd 5439 struct ixgbe_hw_stats *hwstats = &adapter->stats;
9a799d71 5440
d08935c2
DS		 5441 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5442 test_bit(__IXGBE_RESETTING, &adapter->state))
5443 return;
5444
94b982b2 5445 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5446 u64 rsc_count = 0;
94b982b2 5447 u64 rsc_flush = 0;
d51019a4
PW		 5448 for (i = 0; i < 16; i++)
5449 adapter->hw_rx_no_dma_resources +=
7ca647bd 5450 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5451 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5452 rsc_count += adapter->rx_ring[i]->rsc_count;
5453 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5454 }
5455 adapter->rsc_total_count = rsc_count;
5456 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5457 }
5458
7ca3bc58
JB		 5459 /* gather some stats to the adapter struct that are per queue */
5460 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5461 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5462 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5463
5464 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5465 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5466 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5467
7ca647bd 5468 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5469 for (i = 0; i < 8; i++) {
5470 /* for packet buffers not used, the register should read 0 */
5471 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5472 missed_rx += mpc;
7ca647bd
JP		 5473 hwstats->mpc[i] += mpc;
5474 total_mpc += hwstats->mpc[i];
e8e26350 5475 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5476 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5477 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5478 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5479 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5480 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350 5481 if (hw->mac.type == ixgbe_mac_82599EB) {
7ca647bd
JP		 5482 hwstats->pxonrxc[i] +=
5483 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5484 hwstats->pxoffrxc[i] +=
5485 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5486 hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350 5487 } else {
7ca647bd
JP		 5488 hwstats->pxonrxc[i] +=
5489 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5490 hwstats->pxoffrxc[i] +=
5491 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
e8e26350 5492 }
7ca647bd
JP		 5493 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5494 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5495 }
7ca647bd 5496 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5497 /* work around hardware counting issue */
7ca647bd 5498 hwstats->gprc -= missed_rx;
6f11eef7
AV		 5499
5500 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5501 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5502 u64 tmp;
7ca647bd 5503 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
e8e9f696
JP		 5504 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5505 /* 4 high bits of GORC */
7ca647bd
JP		 5506 hwstats->gorc += (tmp << 32);
5507 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
e8e9f696
JP		 5508 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5509 /* 4 high bits of GOTC */
7ca647bd
JP		 5510 hwstats->gotc += (tmp << 32);
5511 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
e8e9f696 5512 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd
JP		 5513 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5514 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5515 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5516 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5517#ifdef IXGBE_FCOE
7ca647bd
JP		 5518 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5519 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5520 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5521 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5522 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5523 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5524#endif /* IXGBE_FCOE */
e8e26350 5525 } else {
7ca647bd
JP		 5526 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5527 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5528 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5529 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5530 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
e8e26350 5531 }
9a799d71 5532 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5533 hwstats->bprc += bprc;
5534 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5535 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5536 hwstats->mprc -= bprc;
5537 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5538 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5539 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5540 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5541 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5542 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5543 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5544 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5545 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5546 hwstats->lxontxc += lxon;
6f11eef7 5547 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5548 hwstats->lxofftxc += lxoff;
5549 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5550 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5551 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5552 /*
5553 * 82598 errata - tx of flow control packets is included in tx counters
5554 */
5555 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5556 hwstats->gptc -= xon_off_tot;
5557 hwstats->mptc -= xon_off_tot;
5558 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5559 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5560 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5561 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5562 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5563 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5564 hwstats->ptc64 -= xon_off_tot;
5565 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5566 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5567 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5568 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5569 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5570 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5571
5572 /* Fill out the OS statistics structure */
7ca647bd 5573 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5574
5575 /* Rx Errors */
7ca647bd 5576 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5577 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5578 netdev->stats.rx_length_errors = hwstats->rlec;
5579 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5580 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5581}
5582
5583/**
5584 * ixgbe_watchdog - Timer Call-back
5585 * @data: pointer to adapter cast into an unsigned long
5586 **/
5587static void ixgbe_watchdog(unsigned long data)
5588{
5589 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5590 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5591 u64 eics = 0;
5592 int i;
cf8280ee 5593
fe49f04a
AD		 5594 /*
5595 * Do the watchdog outside of interrupt context due to the lovely
5596 * delays that some of the newer hardware requires
5597 */
22d5a71b 5598
fe49f04a
AD		 5599 if (test_bit(__IXGBE_DOWN, &adapter->state))
5600 goto watchdog_short_circuit;
22d5a71b 5601
fe49f04a
AD		 5602 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5603 /*
5604 * for legacy and MSI interrupts don't set any bits
5605 * that are enabled for EIAM, because this operation
5606 * would set *both* EIMS and EICS for any bit in EIAM
5607 */
5608 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5609 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5610 goto watchdog_reschedule;
5611 }
5612
5613 /* get one bit for every active tx/rx interrupt vector */
5614 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5615 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5616 if (qv->rxr_count || qv->txr_count)
5617 eics |= ((u64)1 << i);
cf8280ee 5618 }
9a799d71 5619
fe49f04a
AD		 5620 /* Cause software interrupt to ensure rx rings are cleaned */
5621 ixgbe_irq_rearm_queues(adapter, eics);
5622
5623watchdog_reschedule:
5624 /* Reset the timer */
5625 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5626
5627watchdog_short_circuit:
cf8280ee
JB		 5628 schedule_work(&adapter->watchdog_task);
5629}
5630
e8e26350
PW		 5631/**
5632 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5633 * @work: pointer to work_struct containing our data
5634 **/
5635static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5636{
5637 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5638 struct ixgbe_adapter,
5639 multispeed_fiber_task);
e8e26350
PW		 5640 struct ixgbe_hw *hw = &adapter->hw;
5641 u32 autoneg;
8620a103 5642 bool negotiation;
e8e26350
PW		 5643
5644 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5645 autoneg = hw->phy.autoneg_advertised;
5646 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5647 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5648 hw->mac.autotry_restart = false;
8620a103
MC		 5649 if (hw->mac.ops.setup_link)
5650 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5651 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5652 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5653}
5654
5655/**
5656 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5657 * @work: pointer to work_struct containing our data
5658 **/
5659static void ixgbe_sfp_config_module_task(struct work_struct *work)
5660{
5661 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5662 struct ixgbe_adapter,
5663 sfp_config_module_task);
e8e26350
PW		 5664 struct ixgbe_hw *hw = &adapter->hw;
5665 u32 err;
5666
5667 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5668
5669 /* Time for electrical oscillations to settle down */
5670 msleep(100);
e8e26350 5671 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5672
e8e26350 5673 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5674 e_dev_err("failed to initialize because an unsupported SFP+ "
5675 "module type was detected.\n");
5676 e_dev_err("Reload the driver after installing a supported "
5677 "module.\n");
63d6e1d8 5678 unregister_netdev(adapter->netdev);
e8e26350
PW		 5679 return;
5680 }
5681 hw->mac.ops.setup_sfp(hw);
5682
8d1c3c07 5683 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5684 /* This will also work for DA Twinax connections */
5685 schedule_work(&adapter->multispeed_fiber_task);
5686 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5687}
5688
c4cf55e5
PWJ		 5689/**
5690 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5691 * @work: pointer to work_struct containing our data
5692 **/
5693static void ixgbe_fdir_reinit_task(struct work_struct *work)
5694{
5695 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5696 struct ixgbe_adapter,
5697 fdir_reinit_task);
c4cf55e5
PWJ		 5698 struct ixgbe_hw *hw = &adapter->hw;
5699 int i;
5700
5701 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5702 for (i = 0; i < adapter->num_tx_queues; i++)
5703 set_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 5704 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 5705 } else {
396e799c 5706 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5707 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5708 }
5709 /* Done FDIR Re-initialization, enable transmits */
5710 netif_tx_start_all_queues(adapter->netdev);
5711}
5712
10eec955
JF		 5713static DEFINE_MUTEX(ixgbe_watchdog_lock);
5714
cf8280ee 5715/**
69888674
AD		 5716 * ixgbe_watchdog_task - worker thread to bring link up
5717 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5718 **/
5719static void ixgbe_watchdog_task(struct work_struct *work)
5720{
5721 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5722 struct ixgbe_adapter,
5723 watchdog_task);
cf8280ee
JB		 5724 struct net_device *netdev = adapter->netdev;
5725 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5726 u32 link_speed;
5727 bool link_up;
bc59fcda
NS		 5728 int i;
5729 struct ixgbe_ring *tx_ring;
5730 int some_tx_pending = 0;
cf8280ee 5731
10eec955
JF		 5732 mutex_lock(&ixgbe_watchdog_lock);
5733
5734 link_up = adapter->link_up;
5735 link_speed = adapter->link_speed;
cf8280ee
JB		 5736
5737 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5738 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5739 if (link_up) {
5740#ifdef CONFIG_DCB
5741 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5742 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5743 hw->mac.ops.fc_enable(hw, i);
264857b8 5744 } else {
620fa036 5745 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5746 }
5747#else
620fa036 5748 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5749#endif
5750 }
5751
cf8280ee
JB		 5752 if (link_up ||
5753 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 5754 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5755 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5756 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5757 }
5758 adapter->link_up = link_up;
5759 adapter->link_speed = link_speed;
5760 }
9a799d71
AK		 5761
5762 if (link_up) {
5763 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5764 bool flow_rx, flow_tx;
5765
5766 if (hw->mac.type == ixgbe_mac_82599EB) {
5767 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5768 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5769 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5770 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5771 } else {
5772 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5773 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5774 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5775 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5776 }
5777
396e799c 5778 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5779 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5780 "10 Gbps" :
5781 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5782 "1 Gbps" : "unknown speed")),
e8e26350 5783 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5784 (flow_rx ? "RX" :
5785 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5786
5787 netif_carrier_on(netdev);
9a799d71
AK		 5788 } else {
5789 /* Force detection of hung controller */
5790 adapter->detect_tx_hung = true;
5791 }
5792 } else {
cf8280ee
JB		 5793 adapter->link_up = false;
5794 adapter->link_speed = 0;
9a799d71 5795 if (netif_carrier_ok(netdev)) {
396e799c 5796 e_info(drv, "NIC Link is Down\n");
9a799d71 5797 netif_carrier_off(netdev);
9a799d71
AK		 5798 }
5799 }
5800
bc59fcda
NS		 5801 if (!netif_carrier_ok(netdev)) {
5802 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5803 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5804 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5805 some_tx_pending = 1;
5806 break;
5807 }
5808 }
5809
5810 if (some_tx_pending) {
5811 /* We've lost link, so the controller stops DMA,
5812 * but we've got queued Tx work that's never going
5813 * to get done, so reset controller to flush Tx.
5814 * (Do the reset outside of interrupt context).
5815 */
5816 schedule_work(&adapter->reset_task);
5817 }
5818 }
5819
9a799d71 5820 ixgbe_update_stats(adapter);
10eec955 5821 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5822}
5823
9a799d71 5824static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696
JP		 5825 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5826 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5827{
5828 struct ixgbe_adv_tx_context_desc *context_desc;
5829 unsigned int i;
5830 int err;
5831 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5832 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5833 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5834
5835 if (skb_is_gso(skb)) {
5836 if (skb_header_cloned(skb)) {
5837 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5838 if (err)
5839 return err;
5840 }
5841 l4len = tcp_hdrlen(skb);
5842 *hdr_len += l4len;
5843
8327d000 5844 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5845 struct iphdr *iph = ip_hdr(skb);
5846 iph->tot_len = 0;
5847 iph->check = 0;
5848 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 5849 iph->daddr, 0,
5850 IPPROTO_TCP,
5851 0);
8e1e8a47 5852 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5853 ipv6_hdr(skb)->payload_len = 0;
5854 tcp_hdr(skb)->check =
5855 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 5856 &ipv6_hdr(skb)->daddr,
5857 0, IPPROTO_TCP, 0);
9a799d71
AK		 5858 }
5859
5860 i = tx_ring->next_to_use;
5861
5862 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5863 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5864
5865 /* VLAN MACLEN IPLEN */
5866 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5867 vlan_macip_lens |=
5868 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5869 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 5870 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5871 *hdr_len += skb_network_offset(skb);
5872 vlan_macip_lens |=
5873 (skb_transport_header(skb) - skb_network_header(skb));
5874 *hdr_len +=
5875 (skb_transport_header(skb) - skb_network_header(skb));
5876 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5877 context_desc->seqnum_seed = 0;
5878
5879 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5880 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 5881 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5882
8327d000 5883 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5884 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5885 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5886 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5887
5888 /* MSS L4LEN IDX */
9f8cdf4f 5889 mss_l4len_idx =
9a799d71
AK		 5890 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5891 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5892 /* use index 1 for TSO */
5893 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5894 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5895
5896 tx_buffer_info->time_stamp = jiffies;
5897 tx_buffer_info->next_to_watch = i;
5898
5899 i++;
5900 if (i == tx_ring->count)
5901 i = 0;
5902 tx_ring->next_to_use = i;
5903
5904 return true;
5905 }
5906 return false;
5907}
5908
7ca647bd
JP		 5909static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb)
5910{
5911 u32 rtn = 0;
5912 __be16 protocol;
5913
5914 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5915 protocol = ((const struct vlan_ethhdr *)skb->data)->
5916 h_vlan_encapsulated_proto;
5917 else
5918 protocol = skb->protocol;
5919
5920 switch (protocol) {
5921 case cpu_to_be16(ETH_P_IP):
5922 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5923 switch (ip_hdr(skb)->protocol) {
5924 case IPPROTO_TCP:
5925 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5926 break;
5927 case IPPROTO_SCTP:
5928 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5929 break;
5930 }
5931 break;
5932 case cpu_to_be16(ETH_P_IPV6):
5933 /* XXX what about other V6 headers?? */
5934 switch (ipv6_hdr(skb)->nexthdr) {
5935 case IPPROTO_TCP:
5936 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5937 break;
5938 case IPPROTO_SCTP:
5939 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5940 break;
5941 }
5942 break;
5943 default:
5944 if (unlikely(net_ratelimit()))
5945 e_warn(probe, "partial checksum but proto=%x!\n",
5946 skb->protocol);
5947 break;
5948 }
5949
5950 return rtn;
5951}
5952
9a799d71 5953static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696
JP		 5954 struct ixgbe_ring *tx_ring,
5955 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5956{
5957 struct ixgbe_adv_tx_context_desc *context_desc;
5958 unsigned int i;
5959 struct ixgbe_tx_buffer *tx_buffer_info;
5960 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5961
5962 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5963 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5964 i = tx_ring->next_to_use;
5965 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5966 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5967
5968 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5969 vlan_macip_lens |=
5970 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5971 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 5972 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5973 if (skb->ip_summed == CHECKSUM_PARTIAL)
5974 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 5975 skb_network_header(skb));
9a799d71
AK		 5976
5977 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5978 context_desc->seqnum_seed = 0;
5979
5980 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 5981 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5982
7ca647bd
JP		 5983 if (skb->ip_summed == CHECKSUM_PARTIAL)
5984 type_tucmd_mlhl |= ixgbe_psum(adapter, skb);
9a799d71
AK		 5985
5986 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5987 /* use index zero for tx checksum offload */
9a799d71
AK		 5988 context_desc->mss_l4len_idx = 0;
5989
5990 tx_buffer_info->time_stamp = jiffies;
5991 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5992
9a799d71
AK		 5993 i++;
5994 if (i == tx_ring->count)
5995 i = 0;
5996 tx_ring->next_to_use = i;
5997
5998 return true;
5999 }
9f8cdf4f 6000
9a799d71
AK		 6001 return false;
6002}
6003
6004static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6005 struct ixgbe_ring *tx_ring,
6006 struct sk_buff *skb, u32 tx_flags,
6007 unsigned int first)
9a799d71 6008{
e5a43549 6009 struct pci_dev *pdev = adapter->pdev;
9a799d71 6010 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6011 unsigned int len;
6012 unsigned int total = skb->len;
9a799d71
AK		 6013 unsigned int offset = 0, size, count = 0, i;
6014 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6015 unsigned int f;
9a799d71
AK		 6016
6017 i = tx_ring->next_to_use;
6018
eacd73f7
YZ		 6019 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6020 /* excluding fcoe_crc_eof for FCoE */
6021 total -= sizeof(struct fcoe_crc_eof);
6022
6023 len = min(skb_headlen(skb), total);
9a799d71
AK		 6024 while (len) {
6025 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6026 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6027
6028 tx_buffer_info->length = size;
e5a43549 6029 tx_buffer_info->mapped_as_page = false;
1b507730 6030 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 6031 skb->data + offset,
1b507730
NN		 6032 size, DMA_TO_DEVICE);
6033 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 6034 goto dma_error;
9a799d71
AK		 6035 tx_buffer_info->time_stamp = jiffies;
6036 tx_buffer_info->next_to_watch = i;
6037
6038 len -= size;
eacd73f7 6039 total -= size;
9a799d71
AK		 6040 offset += size;
6041 count++;
44df32c5
AD		 6042
6043 if (len) {
6044 i++;
6045 if (i == tx_ring->count)
6046 i = 0;
6047 }
9a799d71
AK		 6048 }
6049
6050 for (f = 0; f < nr_frags; f++) {
6051 struct skb_frag_struct *frag;
6052
6053 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6054 len = min((unsigned int)frag->size, total);
e5a43549 6055 offset = frag->page_offset;
9a799d71
AK		 6056
6057 while (len) {
44df32c5
AD		 6058 i++;
6059 if (i == tx_ring->count)
6060 i = 0;
6061
9a799d71
AK		 6062 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6063 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6064
6065 tx_buffer_info->length = size;
1b507730 6066 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 6067 frag->page,
6068 offset, size,
1b507730 6069 DMA_TO_DEVICE);
e5a43549 6070 tx_buffer_info->mapped_as_page = true;
1b507730 6071 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 6072 goto dma_error;
9a799d71
AK		 6073 tx_buffer_info->time_stamp = jiffies;
6074 tx_buffer_info->next_to_watch = i;
6075
6076 len -= size;
eacd73f7 6077 total -= size;
9a799d71
AK		 6078 offset += size;
6079 count++;
9a799d71 6080 }
eacd73f7
YZ		 6081 if (total == 0)
6082 break;
9a799d71 6083 }
44df32c5 6084
9a799d71
AK		 6085 tx_ring->tx_buffer_info[i].skb = skb;
6086 tx_ring->tx_buffer_info[first].next_to_watch = i;
6087
e5a43549
AD		 6088 return count;
6089
6090dma_error:
849c4542 6091 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6092
6093 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6094 tx_buffer_info->dma = 0;
6095 tx_buffer_info->time_stamp = 0;
6096 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6097 if (count)
6098 count--;
e5a43549
AD		 6099
6100 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6101 while (count--) {
e8e9f696 6102 if (i == 0)
e5a43549 6103 i += tx_ring->count;
c1fa347f 6104 i--;
e5a43549
AD		 6105 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6106 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6107 }
6108
e44d38e1 6109 return 0;
9a799d71
AK		 6110}
6111
6112static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6113 struct ixgbe_ring *tx_ring,
6114 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6115{
6116 union ixgbe_adv_tx_desc *tx_desc = NULL;
6117 struct ixgbe_tx_buffer *tx_buffer_info;
6118 u32 olinfo_status = 0, cmd_type_len = 0;
6119 unsigned int i;
6120 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6121
6122 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6123
6124 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6125
6126 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6127 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6128
6129 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6130 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6131
6132 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6133 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6134
4eeae6fd
PW		 6135 /* use index 1 context for tso */
6136 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6137 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6138 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6139 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6140
6141 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6142 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6143 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6144
eacd73f7
YZ		 6145 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6146 olinfo_status |= IXGBE_ADVTXD_CC;
6147 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6148 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6149 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6150 }
6151
9a799d71
AK		 6152 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6153
6154 i = tx_ring->next_to_use;
6155 while (count--) {
6156 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6157 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6158 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6159 tx_desc->read.cmd_type_len =
e8e9f696 6160 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6161 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6162 i++;
6163 if (i == tx_ring->count)
6164 i = 0;
6165 }
6166
6167 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6168
6169 /*
6170 * Force memory writes to complete before letting h/w
6171 * know there are new descriptors to fetch. (Only
6172 * applicable for weak-ordered memory model archs,
6173 * such as IA-64).
6174 */
6175 wmb();
6176
6177 tx_ring->next_to_use = i;
6178 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6179}
6180
c4cf55e5 6181static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
e8e9f696 6182 int queue, u32 tx_flags)
c4cf55e5 6183{
c4cf55e5
PWJ		 6184 struct ixgbe_atr_input atr_input;
6185 struct tcphdr *th;
c4cf55e5
PWJ		 6186 struct iphdr *iph = ip_hdr(skb);
6187 struct ethhdr *eth = (struct ethhdr *)skb->data;
6188 u16 vlan_id, src_port, dst_port, flex_bytes;
6189 u32 src_ipv4_addr, dst_ipv4_addr;
6190 u8 l4type = 0;
6191
d3ead241
GG		 6192 /* Right now, we support IPv4 only */
6193 if (skb->protocol != htons(ETH_P_IP))
6194 return;
c4cf55e5
PWJ		 6195 /* check if we're UDP or TCP */
6196 if (iph->protocol == IPPROTO_TCP) {
6197 th = tcp_hdr(skb);
6198 src_port = th->source;
6199 dst_port = th->dest;
6200 l4type |= IXGBE_ATR_L4TYPE_TCP;
6201 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6202 } else {
6203 /* Unsupported L4 header, just bail here */
6204 return;
6205 }
6206
6207 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6208
6209 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
e8e9f696 6210 IXGBE_TX_FLAGS_VLAN_SHIFT;
c4cf55e5
PWJ		 6211 src_ipv4_addr = iph->saddr;
6212 dst_ipv4_addr = iph->daddr;
6213 flex_bytes = eth->h_proto;
6214
6215 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6216 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6217 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6218 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6219 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6220 /* src and dst are inverted, think how the receiver sees them */
6221 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6222 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6223
6224 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6225 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6226}
6227
e092be60 6228static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6229 struct ixgbe_ring *tx_ring, int size)
e092be60 6230{
30eba97a 6231 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6232 /* Herbert's original patch had:
6233 * smp_mb__after_netif_stop_queue();
6234 * but since that doesn't exist yet, just open code it. */
6235 smp_mb();
6236
6237 /* We need to check again in a case another CPU has just
6238 * made room available. */
6239 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6240 return -EBUSY;
6241
6242 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6243 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6244 ++tx_ring->restart_queue;
e092be60
AV		 6245 return 0;
6246}
6247
6248static int ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6249 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6250{
6251 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6252 return 0;
6253 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6254}
6255
09a3b1f8
SH		 6256static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6257{
6258 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6259 int txq = smp_processor_id();
09a3b1f8 6260
56075a98
JF		 6261#ifdef IXGBE_FCOE
6262 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6263 (skb->protocol == htons(ETH_P_FIP))) {
6264 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6265 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6266 txq += adapter->ring_feature[RING_F_FCOE].mask;
6267 return txq;
4bc091d8 6268#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6269 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6270 txq = adapter->fcoe.up;
6271 return txq;
4bc091d8 6272#endif
56075a98
JF		 6273 }
6274 }
6275#endif
6276
fdd3d631
KK		 6277 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6278 while (unlikely(txq >= dev->real_num_tx_queues))
6279 txq -= dev->real_num_tx_queues;
5f715823 6280 return txq;
fdd3d631 6281 }
c4cf55e5 6282
2ea186ae
JF		 6283 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6284 if (skb->priority == TC_PRIO_CONTROL)
6285 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6286 else
6287 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6288 >> 13;
6289 return txq;
6290 }
09a3b1f8
SH		 6291
6292 return skb_tx_hash(dev, skb);
6293}
6294
84418e3b
AD		 6295netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
6296 struct ixgbe_adapter *adapter,
6297 struct ixgbe_ring *tx_ring)
9a799d71 6298{
60d51134 6299 struct netdev_queue *txq;
9a799d71
AK		 6300 unsigned int first;
6301 unsigned int tx_flags = 0;
30eba97a 6302 u8 hdr_len = 0;
5f715823 6303 int tso;
9a799d71
AK		 6304 int count = 0;
6305 unsigned int f;
9f8cdf4f 6306
eab6d18d 6307 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6308 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6309 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6310 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6311 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6312 }
6313 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6314 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6315 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6316 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6317 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6318 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6319 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6320 }
eacd73f7 6321
09ad1cc0 6322#ifdef IXGBE_FCOE
56075a98
JF		 6323 /* for FCoE with DCB, we force the priority to what
6324 * was specified by the switch */
6325 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6326 (skb->protocol == htons(ETH_P_FCOE) ||
6327 skb->protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6328#ifdef CONFIG_IXGBE_DCB
6329 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6330 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6331 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6332 tx_flags |= ((adapter->fcoe.up << 13)
6333 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6334 }
6335#endif
ca77cd59
RL		 6336 /* flag for FCoE offloads */
6337 if (skb->protocol == htons(ETH_P_FCOE))
6338 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6339 }
ca77cd59
RL		 6340#endif
6341
eacd73f7 6342 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6343 if (skb_is_gso(skb) ||
6344 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6345 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6346 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6347 count++;
6348
9f8cdf4f
JB		 6349 count += TXD_USE_COUNT(skb_headlen(skb));
6350 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6351 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6352
e092be60 6353 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6354 adapter->tx_busy++;
9a799d71
AK		 6355 return NETDEV_TX_BUSY;
6356 }
9a799d71 6357
9a799d71 6358 first = tx_ring->next_to_use;
eacd73f7
YZ		 6359 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6360#ifdef IXGBE_FCOE
6361 /* setup tx offload for FCoE */
6362 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6363 if (tso < 0) {
6364 dev_kfree_skb_any(skb);
6365 return NETDEV_TX_OK;
6366 }
6367 if (tso)
6368 tx_flags |= IXGBE_TX_FLAGS_FSO;
6369#endif /* IXGBE_FCOE */
6370 } else {
6371 if (skb->protocol == htons(ETH_P_IP))
6372 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6373 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6374 if (tso < 0) {
6375 dev_kfree_skb_any(skb);
6376 return NETDEV_TX_OK;
6377 }
9a799d71 6378
eacd73f7
YZ		 6379 if (tso)
6380 tx_flags |= IXGBE_TX_FLAGS_TSO;
6381 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6382 (skb->ip_summed == CHECKSUM_PARTIAL))
6383 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6384 }
9a799d71 6385
eacd73f7 6386 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 6387 if (count) {
c4cf55e5
PWJ		 6388 /* add the ATR filter if ATR is on */
6389 if (tx_ring->atr_sample_rate) {
6390 ++tx_ring->atr_count;
6391 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
e8e9f696
JP		 6392 test_bit(__IXGBE_FDIR_INIT_DONE,
6393 &tx_ring->reinit_state)) {
c4cf55e5 6394 ixgbe_atr(adapter, skb, tx_ring->queue_index,
e8e9f696 6395 tx_flags);
c4cf55e5
PWJ		 6396 tx_ring->atr_count = 0;
6397 }
6398 }
60d51134
ED		 6399 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6400 txq->tx_bytes += skb->len;
6401 txq->tx_packets++;
44df32c5 6402 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
e8e9f696 6403 hdr_len);
44df32c5 6404 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6405
44df32c5
AD		 6406 } else {
6407 dev_kfree_skb_any(skb);
6408 tx_ring->tx_buffer_info[first].time_stamp = 0;
6409 tx_ring->next_to_use = first;
6410 }
9a799d71
AK		 6411
6412 return NETDEV_TX_OK;
6413}
6414
84418e3b
AD		 6415static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6416{
6417 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6418 struct ixgbe_ring *tx_ring;
6419
6420 tx_ring = adapter->tx_ring[skb->queue_mapping];
6421 return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
6422}
6423
9a799d71
AK		 6424/**
6425 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6426 * @netdev: network interface device structure
6427 * @p: pointer to an address structure
6428 *
6429 * Returns 0 on success, negative on failure
6430 **/
6431static int ixgbe_set_mac(struct net_device *netdev, void *p)
6432{
6433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6434 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6435 struct sockaddr *addr = p;
6436
6437 if (!is_valid_ether_addr(addr->sa_data))
6438 return -EADDRNOTAVAIL;
6439
6440 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6441 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6442
1cdd1ec8
GR		 6443 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6444 IXGBE_RAH_AV);
9a799d71
AK		 6445
6446 return 0;
6447}
6448
6b73e10d
BH		 6449static int
6450ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6451{
6452 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6453 struct ixgbe_hw *hw = &adapter->hw;
6454 u16 value;
6455 int rc;
6456
6457 if (prtad != hw->phy.mdio.prtad)
6458 return -EINVAL;
6459 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6460 if (!rc)
6461 rc = value;
6462 return rc;
6463}
6464
6465static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6466 u16 addr, u16 value)
6467{
6468 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6469 struct ixgbe_hw *hw = &adapter->hw;
6470
6471 if (prtad != hw->phy.mdio.prtad)
6472 return -EINVAL;
6473 return hw->phy.ops.write_reg(hw, addr, devad, value);
6474}
6475
6476static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6477{
6478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6479
6480 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6481}
6482
0365e6e4
PW		 6483/**
6484 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6485 * netdev->dev_addrs
0365e6e4
PW		 6486 * @netdev: network interface device structure
6487 *
6488 * Returns non-zero on failure
6489 **/
6490static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6491{
6492 int err = 0;
6493 struct ixgbe_adapter *adapter = netdev_priv(dev);
6494 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6495
6496 if (is_valid_ether_addr(mac->san_addr)) {
6497 rtnl_lock();
6498 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6499 rtnl_unlock();
6500 }
6501 return err;
6502}
6503
6504/**
6505 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6506 * netdev->dev_addrs
0365e6e4
PW		 6507 * @netdev: network interface device structure
6508 *
6509 * Returns non-zero on failure
6510 **/
6511static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6512{
6513 int err = 0;
6514 struct ixgbe_adapter *adapter = netdev_priv(dev);
6515 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6516
6517 if (is_valid_ether_addr(mac->san_addr)) {
6518 rtnl_lock();
6519 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6520 rtnl_unlock();
6521 }
6522 return err;
6523}
6524
9a799d71
AK		 6525#ifdef CONFIG_NET_POLL_CONTROLLER
6526/*
6527 * Polling 'interrupt' - used by things like netconsole to send skbs
6528 * without having to re-enable interrupts. It's not called while
6529 * the interrupt routine is executing.
6530 */
6531static void ixgbe_netpoll(struct net_device *netdev)
6532{
6533 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6534 int i;
9a799d71 6535
1a647bd2
AD		 6536 /* if interface is down do nothing */
6537 if (test_bit(__IXGBE_DOWN, &adapter->state))
6538 return;
6539
9a799d71 6540 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6541 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6542 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6543 for (i = 0; i < num_q_vectors; i++) {
6544 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6545 ixgbe_msix_clean_many(0, q_vector);
6546 }
6547 } else {
6548 ixgbe_intr(adapter->pdev->irq, netdev);
6549 }
9a799d71 6550 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6551}
6552#endif
6553
de1036b1
ED		 6554static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6555 struct rtnl_link_stats64 *stats)
6556{
6557 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6558 int i;
6559
6560 /* accurate rx/tx bytes/packets stats */
6561 dev_txq_stats_fold(netdev, stats);
6562 for (i = 0; i < adapter->num_rx_queues; i++) {
6563 struct ixgbe_ring *ring = adapter->rx_ring[i];
6564 u64 bytes, packets;
6565 unsigned int start;
6566
6567 do {
6568 start = u64_stats_fetch_begin_bh(&ring->syncp);
6569 packets = ring->stats.packets;
6570 bytes = ring->stats.bytes;
6571 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6572 stats->rx_packets += packets;
6573 stats->rx_bytes += bytes;
6574 }
6575
6576 /* following stats updated by ixgbe_watchdog_task() */
6577 stats->multicast = netdev->stats.multicast;
6578 stats->rx_errors = netdev->stats.rx_errors;
6579 stats->rx_length_errors = netdev->stats.rx_length_errors;
6580 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6581 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6582 return stats;
6583}
6584
6585
0edc3527 6586static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6587 .ndo_open = ixgbe_open,
0edc3527 6588 .ndo_stop = ixgbe_close,
00829823 6589 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6590 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6591 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6592 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6593 .ndo_validate_addr = eth_validate_addr,
6594 .ndo_set_mac_address = ixgbe_set_mac,
6595 .ndo_change_mtu = ixgbe_change_mtu,
6596 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6597 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6598 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6599 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6600 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6601 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6602 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6603 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6604 .ndo_get_stats64 = ixgbe_get_stats64,
0edc3527
SH		 6605#ifdef CONFIG_NET_POLL_CONTROLLER
6606 .ndo_poll_controller = ixgbe_netpoll,
6607#endif
332d4a7d
YZ		 6608#ifdef IXGBE_FCOE
6609 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6610 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6611 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6612 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6613 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6614#endif /* IXGBE_FCOE */
0edc3527
SH		 6615};
6616
1cdd1ec8
GR		 6617static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6618 const struct ixgbe_info *ii)
6619{
6620#ifdef CONFIG_PCI_IOV
6621 struct ixgbe_hw *hw = &adapter->hw;
6622 int err;
6623
6624 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6625 return;
6626
6627 /* The 82599 supports up to 64 VFs per physical function
6628 * but this implementation limits allocation to 63 so that
6629 * basic networking resources are still available to the
6630 * physical function
6631 */
6632 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6633 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6634 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6635 if (err) {
396e799c 6636 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6637 goto err_novfs;
6638 }
6639 /* If call to enable VFs succeeded then allocate memory
6640 * for per VF control structures.
6641 */
6642 adapter->vfinfo =
6643 kcalloc(adapter->num_vfs,
6644 sizeof(struct vf_data_storage), GFP_KERNEL);
6645 if (adapter->vfinfo) {
6646 /* Now that we're sure SR-IOV is enabled
6647 * and memory allocated set up the mailbox parameters
6648 */
6649 ixgbe_init_mbx_params_pf(hw);
6650 memcpy(&hw->mbx.ops, ii->mbx_ops,
6651 sizeof(hw->mbx.ops));
6652
6653 /* Disable RSC when in SR-IOV mode */
6654 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6655 IXGBE_FLAG2_RSC_ENABLED);
6656 return;
6657 }
6658
6659 /* Oh oh */
396e799c
ET		 6660 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6661 "SRIOV disabled\n");
1cdd1ec8
GR		 6662 pci_disable_sriov(adapter->pdev);
6663
6664err_novfs:
6665 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6666 adapter->num_vfs = 0;
6667#endif /* CONFIG_PCI_IOV */
6668}
6669
9a799d71
AK		 6670/**
6671 * ixgbe_probe - Device Initialization Routine
6672 * @pdev: PCI device information struct
6673 * @ent: entry in ixgbe_pci_tbl
6674 *
6675 * Returns 0 on success, negative on failure
6676 *
6677 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6678 * The OS initialization, configuring of the adapter private structure,
6679 * and a hardware reset occur.
6680 **/
6681static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6682 const struct pci_device_id *ent)
9a799d71
AK		 6683{
6684 struct net_device *netdev;
6685 struct ixgbe_adapter *adapter = NULL;
6686 struct ixgbe_hw *hw;
6687 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6688 static int cards_found;
6689 int i, err, pci_using_dac;
c85a2618 6690 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6691#ifdef IXGBE_FCOE
6692 u16 device_caps;
6693#endif
c44ade9e 6694 u32 part_num, eec;
9a799d71 6695
bded64a7
AG		 6696 /* Catch broken hardware that put the wrong VF device ID in
6697 * the PCIe SR-IOV capability.
6698 */
6699 if (pdev->is_virtfn) {
6700 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6701 pci_name(pdev), pdev->vendor, pdev->device);
6702 return -EINVAL;
6703 }
6704
9ce77666 6705 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6706 if (err)
6707 return err;
6708
1b507730
NN		 6709 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6710 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6711 pci_using_dac = 1;
6712 } else {
1b507730 6713 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6714 if (err) {
1b507730
NN		 6715 err = dma_set_coherent_mask(&pdev->dev,
6716 DMA_BIT_MASK(32));
9a799d71 6717 if (err) {
b8bc0421
DC		 6718 dev_err(&pdev->dev,
6719 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6720 goto err_dma;
6721 }
6722 }
6723 pci_using_dac = 0;
6724 }
6725
9ce77666 6726 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 6727 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6728 if (err) {
b8bc0421
DC		 6729 dev_err(&pdev->dev,
6730 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6731 goto err_pci_reg;
6732 }
6733
19d5afd4 6734 pci_enable_pcie_error_reporting(pdev);
6fabd715 6735
9a799d71 6736 pci_set_master(pdev);
fb3b27bc 6737 pci_save_state(pdev);
9a799d71 6738
c85a2618
JF		 6739 if (ii->mac == ixgbe_mac_82598EB)
6740 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6741 else
6742 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6743
6744 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6745#ifdef IXGBE_FCOE
6746 indices += min_t(unsigned int, num_possible_cpus(),
6747 IXGBE_MAX_FCOE_INDICES);
6748#endif
c85a2618 6749 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6750 if (!netdev) {
6751 err = -ENOMEM;
6752 goto err_alloc_etherdev;
6753 }
6754
9a799d71
AK		 6755 SET_NETDEV_DEV(netdev, &pdev->dev);
6756
6757 pci_set_drvdata(pdev, netdev);
6758 adapter = netdev_priv(netdev);
6759
6760 adapter->netdev = netdev;
6761 adapter->pdev = pdev;
6762 hw = &adapter->hw;
6763 hw->back = adapter;
6764 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6765
05857980 6766 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 6767 pci_resource_len(pdev, 0));
9a799d71
AK		 6768 if (!hw->hw_addr) {
6769 err = -EIO;
6770 goto err_ioremap;
6771 }
6772
6773 for (i = 1; i <= 5; i++) {
6774 if (pci_resource_len(pdev, i) == 0)
6775 continue;
6776 }
6777
0edc3527 6778 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6779 ixgbe_set_ethtool_ops(netdev);
9a799d71 6780 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6781 strcpy(netdev->name, pci_name(pdev));
6782
9a799d71
AK		 6783 adapter->bd_number = cards_found;
6784
9a799d71
AK		 6785 /* Setup hw api */
6786 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6787 hw->mac.type = ii->mac;
9a799d71 6788
c44ade9e
JB		 6789 /* EEPROM */
6790 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6791 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6792 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6793 if (!(eec & (1 << 8)))
6794 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6795
6796 /* PHY */
6797 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6798 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6799 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6800 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6801 hw->phy.mdio.mmds = 0;
6802 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6803 hw->phy.mdio.dev = netdev;
6804 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6805 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6806
6807 /* set up this timer and work struct before calling get_invariants
6808 * which might start the timer
6809 */
6810 init_timer(&adapter->sfp_timer);
c061b18d 6811 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 6812 adapter->sfp_timer.data = (unsigned long) adapter;
6813
6814 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6815
e8e26350
PW		 6816 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6817 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6818
6819 /* a new SFP+ module arrival, called from GPI SDP2 context */
6820 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 6821 ixgbe_sfp_config_module_task);
e8e26350 6822
8ca783ab 6823 ii->get_invariants(hw);
9a799d71
AK		 6824
6825 /* setup the private structure */
6826 err = ixgbe_sw_init(adapter);
6827 if (err)
6828 goto err_sw_init;
6829
e86bff0e
DS		 6830 /* Make it possible the adapter to be woken up via WOL */
6831 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6832 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6833
bf069c97
DS		 6834 /*
6835 * If there is a fan on this device and it has failed log the
6836 * failure.
6837 */
6838 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6839 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6840 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6841 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6842 }
6843
c44ade9e 6844 /* reset_hw fills in the perm_addr as well */
119fc60a 6845 hw->phy.reset_if_overtemp = true;
c44ade9e 6846 err = hw->mac.ops.reset_hw(hw);
119fc60a 6847 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6848 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6849 hw->mac.type == ixgbe_mac_82598EB) {
6850 /*
6851 * Start a kernel thread to watch for a module to arrive.
6852 * Only do this for 82598, since 82599 will generate
6853 * interrupts on module arrival.
6854 */
6855 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6856 mod_timer(&adapter->sfp_timer,
6857 round_jiffies(jiffies + (2 * HZ)));
6858 err = 0;
6859 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6860 e_dev_err("failed to initialize because an unsupported SFP+ "
6861 "module type was detected.\n");
6862 e_dev_err("Reload the driver after installing a supported "
6863 "module.\n");
04f165ef
PW		 6864 goto err_sw_init;
6865 } else if (err) {
849c4542 6866 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6867 goto err_sw_init;
6868 }
6869
1cdd1ec8
GR		 6870 ixgbe_probe_vf(adapter, ii);
6871
396e799c 6872 netdev->features = NETIF_F_SG |
e8e9f696
JP		 6873 NETIF_F_IP_CSUM |
6874 NETIF_F_HW_VLAN_TX |
6875 NETIF_F_HW_VLAN_RX |
6876 NETIF_F_HW_VLAN_FILTER;
9a799d71 6877
e9990a9c 6878 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6879 netdev->features |= NETIF_F_TSO;
9a799d71 6880 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6881 netdev->features |= NETIF_F_GRO;
ad31c402 6882
45a5ead0
JB		 6883 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6884 netdev->features |= NETIF_F_SCTP_CSUM;
6885
ad31c402
JK		 6886 netdev->vlan_features |= NETIF_F_TSO;
6887 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6888 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6889 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6890 netdev->vlan_features |= NETIF_F_SG;
6891
1cdd1ec8
GR		 6892 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6893 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6894 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6895 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6896 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6897
7a6b6f51 6898#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6899 netdev->dcbnl_ops = &dcbnl_ops;
6900#endif
6901
eacd73f7 6902#ifdef IXGBE_FCOE
0d551589 6903 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6904 if (hw->mac.ops.get_device_caps) {
6905 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6906 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6907 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6908 }
6909 }
5e09d7f6
YZ		 6910 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6911 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6912 netdev->vlan_features |= NETIF_F_FSO;
6913 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6914 }
eacd73f7 6915#endif /* IXGBE_FCOE */
7b872a55 6916 if (pci_using_dac) {
9a799d71 6917 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6918 netdev->vlan_features |= NETIF_F_HIGHDMA;
6919 }
9a799d71 6920
0c19d6af 6921 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6922 netdev->features |= NETIF_F_LRO;
6923
9a799d71 6924 /* make sure the EEPROM is good */
c44ade9e 6925 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6926 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6927 err = -EIO;
6928 goto err_eeprom;
6929 }
6930
6931 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6932 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6933
c44ade9e 6934 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6935 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6936 err = -EIO;
6937 goto err_eeprom;
6938 }
6939
61fac744
PW		 6940 /* power down the optics */
6941 if (hw->phy.multispeed_fiber)
6942 hw->mac.ops.disable_tx_laser(hw);
6943
9a799d71 6944 init_timer(&adapter->watchdog_timer);
c061b18d 6945 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 6946 adapter->watchdog_timer.data = (unsigned long)adapter;
6947
6948 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6949 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6950
021230d4
AV		 6951 err = ixgbe_init_interrupt_scheme(adapter);
6952 if (err)
6953 goto err_sw_init;
9a799d71 6954
e8e26350
PW		 6955 switch (pdev->device) {
6956 case IXGBE_DEV_ID_82599_KX4:
495dce12 6957 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 6958 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6959 break;
6960 default:
6961 adapter->wol = 0;
6962 break;
6963 }
e8e26350
PW		 6964 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6965
04f165ef
PW		 6966 /* pick up the PCI bus settings for reporting later */
6967 hw->mac.ops.get_bus_info(hw);
6968
9a799d71 6969 /* print bus type/speed/width info */
849c4542 6970 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 6971 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6972 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6973 "Unknown"),
6974 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6975 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6976 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6977 "Unknown"),
6978 netdev->dev_addr);
c44ade9e 6979 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 6980 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 6981 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6982 "PBA No: %06x-%03x\n",
6983 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6984 (part_num >> 8), (part_num & 0xff));
e8e26350 6985 else
849c4542
ET		 6986 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6987 hw->mac.type, hw->phy.type,
6988 (part_num >> 8), (part_num & 0xff));
9a799d71 6989
e8e26350 6990 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 6991 e_dev_warn("PCI-Express bandwidth available for this card is "
6992 "not sufficient for optimal performance.\n");
6993 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6994 "is required.\n");
0c254d86
AK		 6995 }
6996
34b0368c
PWJ		 6997 /* save off EEPROM version number */
6998 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6999
9a799d71 7000 /* reset the hardware with the new settings */
794caeb2 7001 err = hw->mac.ops.start_hw(hw);
c44ade9e 7002
794caeb2
PWJ		 7003 if (err == IXGBE_ERR_EEPROM_VERSION) {
7004 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7005 e_dev_warn("This device is a pre-production adapter/LOM. "
7006 "Please be aware there may be issues associated "
7007 "with your hardware. If you are experiencing "
7008 "problems please contact your Intel or hardware "
7009 "representative who provided you with this "
7010 "hardware.\n");
794caeb2 7011 }
9a799d71
AK		 7012 strcpy(netdev->name, "eth%d");
7013 err = register_netdev(netdev);
7014 if (err)
7015 goto err_register;
7016
54386467
JB		 7017 /* carrier off reporting is important to ethtool even BEFORE open */
7018 netif_carrier_off(netdev);
7019
c4cf55e5
PWJ		 7020 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7021 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7022 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7023
119fc60a 7024 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7025 INIT_WORK(&adapter->check_overtemp_task,
7026 ixgbe_check_overtemp_task);
5dd2d332 7027#ifdef CONFIG_IXGBE_DCA
652f093f 7028 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7029 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7030 ixgbe_setup_dca(adapter);
7031 }
7032#endif
1cdd1ec8 7033 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7034 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7035 for (i = 0; i < adapter->num_vfs; i++)
7036 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7037 }
7038
0365e6e4
PW		 7039 /* add san mac addr to netdev */
7040 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7041
849c4542 7042 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7043 cards_found++;
7044 return 0;
7045
7046err_register:
5eba3699 7047 ixgbe_release_hw_control(adapter);
7a921c93 7048 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7049err_sw_init:
7050err_eeprom:
1cdd1ec8
GR		 7051 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7052 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7053 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7054 del_timer_sync(&adapter->sfp_timer);
7055 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7056 cancel_work_sync(&adapter->multispeed_fiber_task);
7057 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7058 iounmap(hw->hw_addr);
7059err_ioremap:
7060 free_netdev(netdev);
7061err_alloc_etherdev:
e8e9f696
JP		 7062 pci_release_selected_regions(pdev,
7063 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7064err_pci_reg:
7065err_dma:
7066 pci_disable_device(pdev);
7067 return err;
7068}
7069
7070/**
7071 * ixgbe_remove - Device Removal Routine
7072 * @pdev: PCI device information struct
7073 *
7074 * ixgbe_remove is called by the PCI subsystem to alert the driver
7075 * that it should release a PCI device. The could be caused by a
7076 * Hot-Plug event, or because the driver is going to be removed from
7077 * memory.
7078 **/
7079static void __devexit ixgbe_remove(struct pci_dev *pdev)
7080{
7081 struct net_device *netdev = pci_get_drvdata(pdev);
7082 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7083
7084 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 7085 /* clear the module not found bit to make sure the worker won't
7086 * reschedule
7087 */
7088 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 7089 del_timer_sync(&adapter->watchdog_timer);
7090
c4900be0
DS		 7091 del_timer_sync(&adapter->sfp_timer);
7092 cancel_work_sync(&adapter->watchdog_task);
7093 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7094 cancel_work_sync(&adapter->multispeed_fiber_task);
7095 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7096 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7097 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7098 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 7099 flush_scheduled_work();
7100
5dd2d332 7101#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7102 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7103 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7104 dca_remove_requester(&pdev->dev);
7105 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7106 }
7107
7108#endif
332d4a7d
YZ		 7109#ifdef IXGBE_FCOE
7110 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7111 ixgbe_cleanup_fcoe(adapter);
7112
7113#endif /* IXGBE_FCOE */
0365e6e4
PW		 7114
7115 /* remove the added san mac */
7116 ixgbe_del_sanmac_netdev(netdev);
7117
c4900be0
DS		 7118 if (netdev->reg_state == NETREG_REGISTERED)
7119 unregister_netdev(netdev);
9a799d71 7120
1cdd1ec8
GR		 7121 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7122 ixgbe_disable_sriov(adapter);
7123
7a921c93 7124 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7125
021230d4 7126 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7127
7128 iounmap(adapter->hw.hw_addr);
9ce77666 7129 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7130 IORESOURCE_MEM));
9a799d71 7131
849c4542 7132 e_dev_info("complete\n");
021230d4 7133
9a799d71
AK		 7134 free_netdev(netdev);
7135
19d5afd4 7136 pci_disable_pcie_error_reporting(pdev);
6fabd715 7137
9a799d71
AK		 7138 pci_disable_device(pdev);
7139}
7140
7141/**
7142 * ixgbe_io_error_detected - called when PCI error is detected
7143 * @pdev: Pointer to PCI device
7144 * @state: The current pci connection state
7145 *
7146 * This function is called after a PCI bus error affecting
7147 * this device has been detected.
7148 */
7149static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7150 pci_channel_state_t state)
9a799d71
AK		 7151{
7152 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7153 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7154
7155 netif_device_detach(netdev);
7156
3044b8d1
BL		 7157 if (state == pci_channel_io_perm_failure)
7158 return PCI_ERS_RESULT_DISCONNECT;
7159
9a799d71
AK		 7160 if (netif_running(netdev))
7161 ixgbe_down(adapter);
7162 pci_disable_device(pdev);
7163
b4617240 7164 /* Request a slot reset. */
9a799d71
AK		 7165 return PCI_ERS_RESULT_NEED_RESET;
7166}
7167
7168/**
7169 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7170 * @pdev: Pointer to PCI device
7171 *
7172 * Restart the card from scratch, as if from a cold-boot.
7173 */
7174static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7175{
7176 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7177 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 7178 pci_ers_result_t result;
7179 int err;
9a799d71 7180
9ce77666 7181 if (pci_enable_device_mem(pdev)) {
396e799c 7182 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7183 result = PCI_ERS_RESULT_DISCONNECT;
7184 } else {
7185 pci_set_master(pdev);
7186 pci_restore_state(pdev);
c0e1f68b 7187 pci_save_state(pdev);
9a799d71 7188
dd4d8ca6 7189 pci_wake_from_d3(pdev, false);
9a799d71 7190
6fabd715 7191 ixgbe_reset(adapter);
88512539 7192 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7193 result = PCI_ERS_RESULT_RECOVERED;
7194 }
7195
7196 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7197 if (err) {
849c4542
ET		 7198 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7199 "failed 0x%0x\n", err);
6fabd715
PWJ		 7200 /* non-fatal, continue */
7201 }
9a799d71 7202
6fabd715 7203 return result;
9a799d71
AK		 7204}
7205
7206/**
7207 * ixgbe_io_resume - called when traffic can start flowing again.
7208 * @pdev: Pointer to PCI device
7209 *
7210 * This callback is called when the error recovery driver tells us that
7211 * its OK to resume normal operation.
7212 */
7213static void ixgbe_io_resume(struct pci_dev *pdev)
7214{
7215 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7217
7218 if (netif_running(netdev)) {
7219 if (ixgbe_up(adapter)) {
396e799c 7220 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7221 return;
7222 }
7223 }
7224
7225 netif_device_attach(netdev);
9a799d71
AK		 7226}
7227
7228static struct pci_error_handlers ixgbe_err_handler = {
7229 .error_detected = ixgbe_io_error_detected,
7230 .slot_reset = ixgbe_io_slot_reset,
7231 .resume = ixgbe_io_resume,
7232};
7233
7234static struct pci_driver ixgbe_driver = {
7235 .name = ixgbe_driver_name,
7236 .id_table = ixgbe_pci_tbl,
7237 .probe = ixgbe_probe,
7238 .remove = __devexit_p(ixgbe_remove),
7239#ifdef CONFIG_PM
7240 .suspend = ixgbe_suspend,
7241 .resume = ixgbe_resume,
7242#endif
7243 .shutdown = ixgbe_shutdown,
7244 .err_handler = &ixgbe_err_handler
7245};
7246
7247/**
7248 * ixgbe_init_module - Driver Registration Routine
7249 *
7250 * ixgbe_init_module is the first routine called when the driver is
7251 * loaded. All it does is register with the PCI subsystem.
7252 **/
7253static int __init ixgbe_init_module(void)
7254{
7255 int ret;
c7689578 7256 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7257 pr_info("%s\n", ixgbe_copyright);
9a799d71 7258
5dd2d332 7259#ifdef CONFIG_IXGBE_DCA
bd0362dd 7260 dca_register_notify(&dca_notifier);
bd0362dd 7261#endif
5dd2d332 7262
9a799d71
AK		 7263 ret = pci_register_driver(&ixgbe_driver);
7264 return ret;
7265}
b4617240 7266
9a799d71
AK		 7267module_init(ixgbe_init_module);
7268
7269/**
7270 * ixgbe_exit_module - Driver Exit Cleanup Routine
7271 *
7272 * ixgbe_exit_module is called just before the driver is removed
7273 * from memory.
7274 **/
7275static void __exit ixgbe_exit_module(void)
7276{
5dd2d332 7277#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7278 dca_unregister_notify(&dca_notifier);
7279#endif
9a799d71
AK		 7280 pci_unregister_driver(&ixgbe_driver);
7281}
bd0362dd 7282
5dd2d332 7283#ifdef CONFIG_IXGBE_DCA
bd0362dd 7284static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7285 void *p)
bd0362dd
JC		 7286{
7287 int ret_val;
7288
7289 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7290 __ixgbe_notify_dca);
bd0362dd
JC		 7291
7292 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7293}
b453368d 7294
5dd2d332 7295#endif /* CONFIG_IXGBE_DCA */
849c4542 7296
b453368d 7297/**
849c4542 7298 * ixgbe_get_hw_dev return device
b453368d
AD		 7299 * used by hardware layer to print debugging information
7300 **/
849c4542 7301struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7302{
7303 struct ixgbe_adapter *adapter = hw->back;
849c4542 7304 return adapter->netdev;
b453368d 7305}
bd0362dd 7306
9a799d71
AK		 7307module_exit(ixgbe_exit_module);
7308
7309/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree