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[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
e8e9f696
JP		 134MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
e8e9f696
JP		 172
173 kfree(adapter->vfinfo);
1cdd1ec8
GR		 174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
c7689578 285 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 292 pr_err("%-15s", rname);
dcd79aeb 293 for (j = 0; j < 8; j++)
c7689578
JP		 294 pr_cont(" %08x", regs[i*8+j]);
295 pr_cont("\n");
dcd79aeb
TI		 296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 325 pr_info("Device Name state "
dcd79aeb 326 "trans_start last_rx\n");
c7689578
JP		 327 pr_info("%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
dcd79aeb
TI		 332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 336 pr_info(" Register Name Value\n");
dcd79aeb
TI		 337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 348 for (n = 0; n < adapter->num_tx_queues; n++) {
349 tx_ring = adapter->tx_ring[n];
350 tx_buffer_info =
351 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 353 n, tx_ring->next_to_use, tx_ring->next_to_clean,
354 (u64)tx_buffer_info->dma,
355 tx_buffer_info->length,
356 tx_buffer_info->next_to_watch,
357 (u64)tx_buffer_info->time_stamp);
358 }
359
360 /* Print TX Rings */
361 if (!netif_msg_tx_done(adapter))
362 goto rx_ring_summary;
363
364 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
365
366 /* Transmit Descriptor Formats
367 *
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
375 */
376
377 for (n = 0; n < adapter->num_tx_queues; n++) {
378 tx_ring = adapter->tx_ring[n];
c7689578
JP		 379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
385
386 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 387 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
389 u0 = (struct my_u0 *)tx_desc;
c7689578 390 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 391 " %04X %3X %016llX %p", i,
392 le64_to_cpu(u0->a),
393 le64_to_cpu(u0->b),
394 (u64)tx_buffer_info->dma,
395 tx_buffer_info->length,
396 tx_buffer_info->next_to_watch,
397 (u64)tx_buffer_info->time_stamp,
398 tx_buffer_info->skb);
399 if (i == tx_ring->next_to_use &&
400 i == tx_ring->next_to_clean)
c7689578 401 pr_cont(" NTC/U\n");
dcd79aeb 402 else if (i == tx_ring->next_to_use)
c7689578 403 pr_cont(" NTU\n");
dcd79aeb 404 else if (i == tx_ring->next_to_clean)
c7689578 405 pr_cont(" NTC\n");
dcd79aeb 406 else
c7689578 407 pr_cont("\n");
dcd79aeb
TI		 408
409 if (netif_msg_pktdata(adapter) &&
410 tx_buffer_info->dma != 0)
411 print_hex_dump(KERN_INFO, "",
412 DUMP_PREFIX_ADDRESS, 16, 1,
413 phys_to_virt(tx_buffer_info->dma),
414 tx_buffer_info->length, true);
415 }
416 }
417
418 /* Print RX Rings Summary */
419rx_ring_summary:
420 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 421 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 422 for (n = 0; n < adapter->num_rx_queues; n++) {
423 rx_ring = adapter->rx_ring[n];
c7689578
JP		 424 pr_info("%5d %5X %5X\n",
425 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 426 }
427
428 /* Print RX Rings */
429 if (!netif_msg_rx_status(adapter))
430 goto exit;
431
432 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
433
434 /* Advanced Receive Descriptor (Read) Format
435 * 63 1 0
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
441 *
442 *
443 * Advanced Receive Descriptor (Write-Back) Format
444 *
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
453 */
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
c7689578
JP		 456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
c7689578 462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
465
466 for (i = 0; i < rx_ring->count; i++) {
467 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 468 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 469 u0 = (struct my_u0 *)rx_desc;
470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
471 if (staterr & IXGBE_RXD_STAT_DD) {
472 /* Descriptor Done */
c7689578 473 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 474 "%016llX ---------------- %p", i,
475 le64_to_cpu(u0->a),
476 le64_to_cpu(u0->b),
477 rx_buffer_info->skb);
478 } else {
c7689578 479 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 480 "%016llX %016llX %p", i,
481 le64_to_cpu(u0->a),
482 le64_to_cpu(u0->b),
483 (u64)rx_buffer_info->dma,
484 rx_buffer_info->skb);
485
486 if (netif_msg_pktdata(adapter)) {
487 print_hex_dump(KERN_INFO, "",
488 DUMP_PREFIX_ADDRESS, 16, 1,
489 phys_to_virt(rx_buffer_info->dma),
490 rx_ring->rx_buf_len, true);
491
492 if (rx_ring->rx_buf_len
493 < IXGBE_RXBUFFER_2048)
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(
497 rx_buffer_info->page_dma +
498 rx_buffer_info->page_offset
499 ),
500 PAGE_SIZE/2, true);
501 }
502 }
503
504 if (i == rx_ring->next_to_use)
c7689578 505 pr_cont(" NTU\n");
dcd79aeb 506 else if (i == rx_ring->next_to_clean)
c7689578 507 pr_cont(" NTC\n");
dcd79aeb 508 else
c7689578 509 pr_cont("\n");
dcd79aeb
TI		 510
511 }
512 }
513
514exit:
515 return;
516}
517
5eba3699
AV		 518static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
519{
520 u32 ctrl_ext;
521
522 /* Let firmware take over control of h/w */
523 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 525 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 526}
527
528static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
529{
530 u32 ctrl_ext;
531
532 /* Let firmware know the driver has taken over */
533 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 535 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 536}
9a799d71 537
e8e26350
PW		 538/*
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
544 *
545 */
546static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 547 u8 queue, u8 msix_vector)
9a799d71
AK		 548{
549 u32 ivar, index;
e8e26350
PW		 550 struct ixgbe_hw *hw = &adapter->hw;
551 switch (hw->mac.type) {
552 case ixgbe_mac_82598EB:
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
554 if (direction == -1)
555 direction = 0;
556 index = (((direction * 64) + queue) >> 2) & 0x1F;
557 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
558 ivar &= ~(0xFF << (8 * (queue & 0x3)));
559 ivar |= (msix_vector << (8 * (queue & 0x3)));
560 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
561 break;
562 case ixgbe_mac_82599EB:
563 if (direction == -1) {
564 /* other causes */
565 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
566 index = ((queue & 1) * 8);
567 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
568 ivar &= ~(0xFF << index);
569 ivar |= (msix_vector << index);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
571 break;
572 } else {
573 /* tx or rx causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((16 * (queue & 1)) + (8 * direction));
576 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
580 break;
581 }
582 default:
583 break;
584 }
9a799d71
AK		 585}
586
fe49f04a 587static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 588 u64 qmask)
fe49f04a
AD		 589{
590 u32 mask;
591
592 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
593 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
595 } else {
596 mask = (qmask & 0xFFFFFFFF);
597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
598 mask = (qmask >> 32);
599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
600 }
601}
602
84418e3b 603void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
e8e9f696
JP		 604 struct ixgbe_tx_buffer
605 *tx_buffer_info)
9a799d71 606{
e5a43549
AD		 607 if (tx_buffer_info->dma) {
608 if (tx_buffer_info->mapped_as_page)
1b507730 609 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 610 tx_buffer_info->dma,
611 tx_buffer_info->length,
1b507730 612 DMA_TO_DEVICE);
e5a43549 613 else
1b507730 614 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 615 tx_buffer_info->dma,
616 tx_buffer_info->length,
1b507730 617 DMA_TO_DEVICE);
e5a43549
AD		 618 tx_buffer_info->dma = 0;
619 }
9a799d71
AK		 620 if (tx_buffer_info->skb) {
621 dev_kfree_skb_any(tx_buffer_info->skb);
622 tx_buffer_info->skb = NULL;
623 }
44df32c5 624 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 625 /* tx_buffer_info must be completely set up in the transmit path */
626}
627
26f23d82 628/**
7483d9dd 629 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 630 * @adapter: the ixgbe adapter
631 * @tx_ring: the corresponding tx_ring
632 *
633 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
634 * corresponding TC of this tx_ring when checking TFCS.
635 *
7483d9dd 636 * Returns : true if in xon state (currently not paused)
26f23d82 637 */
7483d9dd 638static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
e8e9f696 639 struct ixgbe_ring *tx_ring)
26f23d82 640{
26f23d82
YZ		 641 u32 txoff = IXGBE_TFCS_TXOFF;
642
643#ifdef CONFIG_IXGBE_DCB
ca739481 644 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 645 int tc;
26f23d82
YZ		 646 int reg_idx = tx_ring->reg_idx;
647 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
648
6837e895
PW		 649 switch (adapter->hw.mac.type) {
650 case ixgbe_mac_82598EB:
26f23d82
YZ		 651 tc = reg_idx >> 2;
652 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 653 break;
654 case ixgbe_mac_82599EB:
26f23d82
YZ		 655 tc = 0;
656 txoff = IXGBE_TFCS_TXOFF;
657 if (dcb_i == 8) {
658 /* TC0, TC1 */
659 tc = reg_idx >> 5;
660 if (tc == 2) /* TC2, TC3 */
661 tc += (reg_idx - 64) >> 4;
662 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
663 tc += 1 + ((reg_idx - 96) >> 3);
664 } else if (dcb_i == 4) {
665 /* TC0, TC1 */
666 tc = reg_idx >> 6;
667 if (tc == 1) {
668 tc += (reg_idx - 64) >> 5;
669 if (tc == 2) /* TC2, TC3 */
670 tc += (reg_idx - 96) >> 4;
671 }
672 }
6837e895
PW		 673 break;
674 default:
675 tc = 0;
26f23d82
YZ		 676 }
677 txoff <<= tc;
678 }
679#endif
680 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
681}
682
9a799d71 683static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
e8e9f696
JP		 684 struct ixgbe_ring *tx_ring,
685 unsigned int eop)
9a799d71 686{
e01c31a5 687 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 688
9a799d71 689 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 690 * check with the clearing of time_stamp and movement of eop */
9a799d71 691 adapter->detect_tx_hung = false;
44df32c5 692 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 693 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 694 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 695 /* detected Tx unit hang */
e01c31a5 696 union ixgbe_adv_tx_desc *tx_desc;
31f05a2d 697 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
396e799c 698 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 699 " Tx Queue <%d>\n"
700 " TDH, TDT <%x>, <%x>\n"
701 " next_to_use <%x>\n"
702 " next_to_clean <%x>\n"
703 "tx_buffer_info[next_to_clean]\n"
704 " time_stamp <%lx>\n"
705 " jiffies <%lx>\n",
706 tx_ring->queue_index,
707 IXGBE_READ_REG(hw, tx_ring->head),
708 IXGBE_READ_REG(hw, tx_ring->tail),
709 tx_ring->next_to_use, eop,
710 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 711 return true;
712 }
713
714 return false;
715}
716
b4617240
PW		 717#define IXGBE_MAX_TXD_PWR 14
718#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 719
720/* Tx Descriptors needed, worst case */
721#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
722 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
723#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 724 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 725
e01c31a5
JB		 726static void ixgbe_tx_timeout(struct net_device *netdev);
727
9a799d71
AK		 728/**
729 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 730 * @q_vector: structure containing interrupt and ring information
e01c31a5 731 * @tx_ring: tx ring to clean
9a799d71 732 **/
fe49f04a 733static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 734 struct ixgbe_ring *tx_ring)
9a799d71 735{
fe49f04a 736 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 737 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 738 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
739 struct ixgbe_tx_buffer *tx_buffer_info;
740 unsigned int i, eop, count = 0;
e01c31a5 741 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 742
743 i = tx_ring->next_to_clean;
12207e49 744 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 745 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 746
747 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 748 (count < tx_ring->work_limit)) {
12207e49 749 bool cleaned = false;
2d0bb1c1 750 rmb(); /* read buffer_info after eop_desc */
12207e49
PWJ		 751 for ( ; !cleaned; count++) {
752 struct sk_buff *skb;
31f05a2d 753 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 754 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 755 cleaned = (i == eop);
e01c31a5 756 skb = tx_buffer_info->skb;
9a799d71 757
12207e49 758 if (cleaned && skb) {
e092be60 759 unsigned int segs, bytecount;
3d8fd385 760 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 761
762 /* gso_segs is currently only valid for tcp */
e092be60 763 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 764#ifdef IXGBE_FCOE
765 /* adjust for FCoE Sequence Offload */
766 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5e09a105
HZ		 767 && skb_is_gso(skb)
768 && vlan_get_protocol(skb) ==
769 htons(ETH_P_FCOE)) {
3d8fd385
YZ		 770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
775 }
776#endif /* IXGBE_FCOE */
e092be60 777 /* multiply data chunks by size of headers */
3d8fd385 778 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 779 total_packets += segs;
780 total_bytes += bytecount;
e092be60 781 }
e01c31a5 782
9a799d71 783 ixgbe_unmap_and_free_tx_resource(adapter,
e8e9f696 784 tx_buffer_info);
9a799d71 785
12207e49
PWJ		 786 tx_desc->wb.status = 0;
787
9a799d71
AK		 788 i++;
789 if (i == tx_ring->count)
790 i = 0;
e01c31a5 791 }
12207e49
PWJ		 792
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 794 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 795 }
796
9a799d71
AK		 797 tx_ring->next_to_clean = i;
798
e092be60 799#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5 800 if (unlikely(count && netif_carrier_ok(netdev) &&
e8e9f696 801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
804 */
805 smp_mb();
30eba97a
AV		 806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 809 ++tx_ring->restart_queue;
30eba97a 810 }
e092be60 811 }
9a799d71 812
e01c31a5
JB		 813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
396e799c
ET		 816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
e01c31a5
JB		 818 ixgbe_tx_timeout(adapter->netdev);
819 }
820 }
9a799d71 821
e01c31a5 822 /* re-arm the interrupt */
fe49f04a
AD		 823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 825
e01c31a5
JB		 826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
de1036b1 828 u64_stats_update_begin(&tx_ring->syncp);
e01c31a5 829 tx_ring->stats.packets += total_packets;
12207e49 830 tx_ring->stats.bytes += total_bytes;
de1036b1 831 u64_stats_update_end(&tx_ring->syncp);
807540ba 832 return count < tx_ring->work_limit;
9a799d71
AK		 833}
834
5dd2d332 835#ifdef CONFIG_IXGBE_DCA
bd0362dd 836static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
e8e9f696 837 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 838{
839 u32 rxctrl;
840 int cpu = get_cpu();
4a0b9ca0 841 int q = rx_ring->reg_idx;
bd0362dd 842
3a581073 843 if (rx_ring->cpu != cpu) {
bd0362dd 844 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 845 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
846 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
847 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
848 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
849 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
850 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 851 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
e8e26350 852 }
bd0362dd
JC		 853 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
854 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 855 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
856 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e9f696 857 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 858 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 859 rx_ring->cpu = cpu;
bd0362dd
JC		 860 }
861 put_cpu();
862}
863
864static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
e8e9f696 865 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 866{
867 u32 txctrl;
868 int cpu = get_cpu();
4a0b9ca0 869 int q = tx_ring->reg_idx;
ee5f784a 870 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 871
3a581073 872 if (tx_ring->cpu != cpu) {
e8e26350 873 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 874 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 875 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
876 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 877 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
878 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 879 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 880 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 881 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
882 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 883 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
ee5f784a
DS		 884 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
885 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 886 }
3a581073 887 tx_ring->cpu = cpu;
bd0362dd
JC		 888 }
889 put_cpu();
890}
891
892static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
893{
894 int i;
895
896 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
897 return;
898
e35ec126
AD		 899 /* always use CB2 mode, difference is masked in the CB driver */
900 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
901
bd0362dd 902 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 903 adapter->tx_ring[i]->cpu = -1;
904 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 905 }
906 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 907 adapter->rx_ring[i]->cpu = -1;
908 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 909 }
910}
911
912static int __ixgbe_notify_dca(struct device *dev, void *data)
913{
914 struct net_device *netdev = dev_get_drvdata(dev);
915 struct ixgbe_adapter *adapter = netdev_priv(netdev);
916 unsigned long event = *(unsigned long *)data;
917
918 switch (event) {
919 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 920 /* if we're already enabled, don't do it again */
921 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
922 break;
652f093f 923 if (dca_add_requester(dev) == 0) {
96b0e0f6 924 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 925 ixgbe_setup_dca(adapter);
926 break;
927 }
928 /* Fall Through since DCA is disabled. */
929 case DCA_PROVIDER_REMOVE:
930 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
931 dca_remove_requester(dev);
932 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
934 }
935 break;
936 }
937
652f093f 938 return 0;
bd0362dd
JC		 939}
940
5dd2d332 941#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 942/**
943 * ixgbe_receive_skb - Send a completed packet up the stack
944 * @adapter: board private structure
945 * @skb: packet to send up
177db6ff
MC		 946 * @status: hardware indication of status of receive
947 * @rx_ring: rx descriptor ring (for a specific queue) to setup
948 * @rx_desc: rx descriptor
9a799d71 949 **/
78b6f4ce 950static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 951 struct sk_buff *skb, u8 status,
952 struct ixgbe_ring *ring,
953 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 954{
78b6f4ce
HX		 955 struct ixgbe_adapter *adapter = q_vector->adapter;
956 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 957 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
958 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 959
f62bbb5e
JG		 960 if (is_vlan && (tag & VLAN_VID_MASK))
961 __vlan_hwaccel_put_tag(skb, tag);
962
963 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
964 napi_gro_receive(napi, skb);
965 else
966 netif_rx(skb);
9a799d71
AK		 967}
968
e59bd25d
AV		 969/**
970 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
971 * @adapter: address of board private structure
972 * @status_err: hardware indication of status of receive
973 * @skb: skb currently being received and modified
974 **/
9a799d71 975static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 976 union ixgbe_adv_rx_desc *rx_desc,
977 struct sk_buff *skb)
9a799d71 978{
8bae1b2b
DS		 979 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
980
bc8acf2c 981 skb_checksum_none_assert(skb);
9a799d71 982
712744be
JB		 983 /* Rx csum disabled */
984 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 985 return;
e59bd25d
AV		 986
987 /* if IP and error */
988 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
989 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 990 adapter->hw_csum_rx_error++;
991 return;
992 }
e59bd25d
AV		 993
994 if (!(status_err & IXGBE_RXD_STAT_L4CS))
995 return;
996
997 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 998 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
999
1000 /*
1001 * 82599 errata, UDP frames with a 0 checksum can be marked as
1002 * checksum errors.
1003 */
1004 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1005 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1006 return;
1007
e59bd25d
AV		 1008 adapter->hw_csum_rx_error++;
1009 return;
1010 }
1011
9a799d71 1012 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1013 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1014}
1015
e8e26350 1016static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
e8e9f696 1017 struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1018{
1019 /*
1020 * Force memory writes to complete before letting h/w
1021 * know there are new descriptors to fetch. (Only
1022 * applicable for weak-ordered memory model archs,
1023 * such as IA-64).
1024 */
1025 wmb();
1026 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1027}
1028
9a799d71
AK		 1029/**
1030 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1031 * @adapter: address of board private structure
1032 **/
84418e3b 1033void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1034 struct ixgbe_ring *rx_ring,
1035 int cleaned_count)
9a799d71 1036{
d716a7d8 1037 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1038 struct pci_dev *pdev = adapter->pdev;
1039 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1040 struct ixgbe_rx_buffer *bi;
9a799d71 1041 unsigned int i;
d716a7d8 1042 unsigned int bufsz = rx_ring->rx_buf_len;
9a799d71
AK		 1043
1044 i = rx_ring->next_to_use;
3a581073 1045 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1046
1047 while (cleaned_count--) {
31f05a2d 1048 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1049
762f4c57 1050 if (!bi->page_dma &&
6e455b89 1051 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1052 if (!bi->page) {
d716a7d8 1053 bi->page = netdev_alloc_page(netdev);
762f4c57
JB		 1054 if (!bi->page) {
1055 adapter->alloc_rx_page_failed++;
1056 goto no_buffers;
1057 }
1058 bi->page_offset = 0;
1059 } else {
1060 /* use a half page if we're re-using */
1061 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1062 }
762f4c57 1063
1b507730 1064 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
e8e9f696
JP		 1065 bi->page_offset,
1066 (PAGE_SIZE / 2),
1b507730 1067 DMA_FROM_DEVICE);
9a799d71
AK		 1068 }
1069
3a581073 1070 if (!bi->skb) {
d716a7d8
AD		 1071 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1072 bufsz);
1073 bi->skb = skb;
9a799d71
AK		 1074
1075 if (!skb) {
1076 adapter->alloc_rx_buff_failed++;
1077 goto no_buffers;
1078 }
d716a7d8
AD		 1079 /* initialize queue mapping */
1080 skb_record_rx_queue(skb, rx_ring->queue_index);
1081 }
9a799d71 1082
d716a7d8
AD		 1083 if (!bi->dma) {
1084 bi->dma = dma_map_single(&pdev->dev,
1085 bi->skb->data,
e8e9f696 1086 rx_ring->rx_buf_len,
1b507730 1087 DMA_FROM_DEVICE);
9a799d71
AK		 1088 }
1089 /* Refresh the desc even if buffer_addrs didn't change because
1090 * each write-back erases this info. */
6e455b89 1091 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1092 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1093 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1094 } else {
3a581073 1095 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1096 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1097 }
1098
1099 i++;
1100 if (i == rx_ring->count)
1101 i = 0;
3a581073 1102 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1103 }
7c6e0a43 1104
9a799d71
AK		 1105no_buffers:
1106 if (rx_ring->next_to_use != i) {
1107 rx_ring->next_to_use = i;
1108 if (i-- == 0)
1109 i = (rx_ring->count - 1);
1110
e8e26350 1111 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1112 }
1113}
1114
7c6e0a43
JB		 1115static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1116{
1117 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1118}
1119
1120static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1121{
1122 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1123}
1124
f8212f97
AD		 1125static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1126{
1127 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
e8e9f696
JP		 1128 IXGBE_RXDADV_RSCCNT_MASK) >>
1129 IXGBE_RXDADV_RSCCNT_SHIFT;
f8212f97
AD		 1130}
1131
1132/**
1133 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1134 * @skb: pointer to the last skb in the rsc queue
94b982b2 1135 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1136 *
1137 * This function changes a queue full of hw rsc buffers into a completed
1138 * packet. It uses the ->prev pointers to find the first packet and then
1139 * turns it into the frag list owner.
1140 **/
94b982b2 1141static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
e8e9f696 1142 u64 *count)
f8212f97
AD		 1143{
1144 unsigned int frag_list_size = 0;
1145
1146 while (skb->prev) {
1147 struct sk_buff *prev = skb->prev;
1148 frag_list_size += skb->len;
1149 skb->prev = NULL;
1150 skb = prev;
94b982b2 1151 *count += 1;
f8212f97
AD		 1152 }
1153
1154 skb_shinfo(skb)->frag_list = skb->next;
1155 skb->next = NULL;
1156 skb->len += frag_list_size;
1157 skb->data_len += frag_list_size;
1158 skb->truesize += frag_list_size;
1159 return skb;
1160}
1161
43634e82
MC		 1162struct ixgbe_rsc_cb {
1163 dma_addr_t dma;
e8171aaa 1164 bool delay_unmap;
43634e82
MC		 1165};
1166
1167#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1168
78b6f4ce 1169static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1170 struct ixgbe_ring *rx_ring,
1171 int *work_done, int work_to_do)
9a799d71 1172{
78b6f4ce 1173 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1174 struct pci_dev *pdev = adapter->pdev;
1175 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1176 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1177 struct sk_buff *skb;
f8212f97 1178 unsigned int i, rsc_count = 0;
7c6e0a43 1179 u32 len, staterr;
177db6ff
MC		 1180 u16 hdr_info;
1181 bool cleaned = false;
9a799d71 1182 int cleaned_count = 0;
d2f4fbe2 1183 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1184#ifdef IXGBE_FCOE
1185 int ddp_bytes = 0;
1186#endif /* IXGBE_FCOE */
9a799d71
AK		 1187
1188 i = rx_ring->next_to_clean;
31f05a2d 1189 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71
AK		 1190 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1191 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1192
1193 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1194 u32 upper_len = 0;
9a799d71
AK		 1195 if (*work_done >= work_to_do)
1196 break;
1197 (*work_done)++;
1198
3c945e5b 1199 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1200 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1201 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1202 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1203 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1204 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1205 if ((len > IXGBE_RX_HDR_SIZE) ||
1206 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1207 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1208 } else {
9a799d71 1209 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1210 }
9a799d71
AK		 1211
1212 cleaned = true;
1213 skb = rx_buffer_info->skb;
7ca3bc58 1214 prefetch(skb->data);
9a799d71
AK		 1215 rx_buffer_info->skb = NULL;
1216
21fa4e66 1217 if (rx_buffer_info->dma) {
43634e82
MC		 1218 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1219 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1220 (!(skb->prev))) {
43634e82
MC		 1221 /*
1222 * When HWRSC is enabled, delay unmapping
1223 * of the first packet. It carries the
1224 * header information, HW may still
1225 * access the header after the writeback.
1226 * Only unmap it when EOP is reached
1227 */
e8171aaa 1228 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1229 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1230 } else {
1b507730 1231 dma_unmap_single(&pdev->dev,
e8e9f696
JP		 1232 rx_buffer_info->dma,
1233 rx_ring->rx_buf_len,
1234 DMA_FROM_DEVICE);
e8171aaa 1235 }
4f57ca6e 1236 rx_buffer_info->dma = 0;
9a799d71
AK		 1237 skb_put(skb, len);
1238 }
1239
1240 if (upper_len) {
1b507730
NN		 1241 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1242 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1243 rx_buffer_info->page_dma = 0;
1244 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1245 rx_buffer_info->page,
1246 rx_buffer_info->page_offset,
1247 upper_len);
762f4c57
JB		 1248
1249 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1250 (page_count(rx_buffer_info->page) != 1))
1251 rx_buffer_info->page = NULL;
1252 else
1253 get_page(rx_buffer_info->page);
9a799d71
AK		 1254
1255 skb->len += upper_len;
1256 skb->data_len += upper_len;
1257 skb->truesize += upper_len;
1258 }
1259
1260 i++;
1261 if (i == rx_ring->count)
1262 i = 0;
9a799d71 1263
31f05a2d 1264 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1265 prefetch(next_rxd);
9a799d71 1266 cleaned_count++;
f8212f97 1267
0c19d6af 1268 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1269 rsc_count = ixgbe_get_rsc_count(rx_desc);
1270
1271 if (rsc_count) {
1272 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1273 IXGBE_RXDADV_NEXTP_SHIFT;
1274 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1275 } else {
1276 next_buffer = &rx_ring->rx_buffer_info[i];
1277 }
1278
9a799d71 1279 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1280 if (skb->prev)
e8e9f696
JP		 1281 skb = ixgbe_transform_rsc_queue(skb,
1282 &(rx_ring->rsc_count));
94b982b2 1283 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1284 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1285 dma_unmap_single(&pdev->dev,
1286 IXGBE_RSC_CB(skb)->dma,
e8e9f696 1287 rx_ring->rx_buf_len,
1b507730 1288 DMA_FROM_DEVICE);
fd3686a8 1289 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1290 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1291 }
94b982b2 1292 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
e8e9f696
JP		 1293 rx_ring->rsc_count +=
1294 skb_shinfo(skb)->nr_frags;
94b982b2
MC		 1295 else
1296 rx_ring->rsc_count++;
1297 rx_ring->rsc_flush++;
1298 }
de1036b1 1299 u64_stats_update_begin(&rx_ring->syncp);
9a799d71
AK		 1300 rx_ring->stats.packets++;
1301 rx_ring->stats.bytes += skb->len;
de1036b1 1302 u64_stats_update_end(&rx_ring->syncp);
9a799d71 1303 } else {
6e455b89 1304 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1305 rx_buffer_info->skb = next_buffer->skb;
1306 rx_buffer_info->dma = next_buffer->dma;
1307 next_buffer->skb = skb;
1308 next_buffer->dma = 0;
1309 } else {
1310 skb->next = next_buffer->skb;
1311 skb->next->prev = skb;
1312 }
7ca3bc58 1313 rx_ring->non_eop_descs++;
9a799d71
AK		 1314 goto next_desc;
1315 }
1316
1317 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1318 dev_kfree_skb_irq(skb);
1319 goto next_desc;
1320 }
1321
8bae1b2b 1322 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1323
1324 /* probably a little skewed due to removing CRC */
1325 total_rx_bytes += skb->len;
1326 total_rx_packets++;
1327
74ce8dd2 1328 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1329#ifdef IXGBE_FCOE
1330 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1331 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1332 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1333 if (!ddp_bytes)
332d4a7d 1334 goto next_desc;
3d8fd385 1335 }
332d4a7d 1336#endif /* IXGBE_FCOE */
fdaff1ce 1337 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1338
1339next_desc:
1340 rx_desc->wb.upper.status_error = 0;
1341
1342 /* return some buffers to hardware, one at a time is too slow */
1343 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1344 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1345 cleaned_count = 0;
1346 }
1347
1348 /* use prefetched values */
1349 rx_desc = next_rxd;
f8212f97 1350 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1351
1352 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1353 }
1354
9a799d71
AK		 1355 rx_ring->next_to_clean = i;
1356 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1357
1358 if (cleaned_count)
1359 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1360
3d8fd385
YZ		 1361#ifdef IXGBE_FCOE
1362 /* include DDPed FCoE data */
1363 if (ddp_bytes > 0) {
1364 unsigned int mss;
1365
1366 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1367 sizeof(struct fc_frame_header) -
1368 sizeof(struct fcoe_crc_eof);
1369 if (mss > 512)
1370 mss &= ~511;
1371 total_rx_bytes += ddp_bytes;
1372 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1373 }
1374#endif /* IXGBE_FCOE */
1375
f494e8fa
AV		 1376 rx_ring->total_packets += total_rx_packets;
1377 rx_ring->total_bytes += total_rx_bytes;
f494e8fa 1378
9a799d71
AK		 1379 return cleaned;
1380}
1381
021230d4 1382static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1383/**
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1386 *
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388 * interrupts.
1389 **/
1390static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391{
021230d4
AV		 1392 struct ixgbe_q_vector *q_vector;
1393 int i, j, q_vectors, v_idx, r_idx;
1394 u32 mask;
9a799d71 1395
021230d4 1396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1397
4df10466
JB		 1398 /*
1399 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1400 * corresponding register.
1401 */
1402 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1403 q_vector = adapter->q_vector[v_idx];
984b3f57 1404 /* XXX for_each_set_bit(...) */
021230d4 1405 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1406 adapter->num_rx_queues);
021230d4
AV		 1407
1408 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1409 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1410 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1411 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1412 adapter->num_rx_queues,
1413 r_idx + 1);
021230d4
AV		 1414 }
1415 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1416 adapter->num_tx_queues);
021230d4
AV		 1417
1418 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1419 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1420 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1421 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1422 adapter->num_tx_queues,
1423 r_idx + 1);
021230d4
AV		 1424 }
1425
021230d4 1426 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1427 /* tx only */
1428 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1429 else if (q_vector->rxr_count)
f7554a2b
NS		 1430 /* rx or mixed */
1431 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1432
fe49f04a 1433 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1434 /* If Flow Director is enabled, set interrupt affinity */
1435 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1436 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1437 /*
1438 * Allocate the affinity_hint cpumask, assign the mask
1439 * for this vector, and set our affinity_hint for
1440 * this irq.
1441 */
1442 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1443 GFP_KERNEL))
1444 return;
1445 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1446 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1447 q_vector->affinity_mask);
1448 }
9a799d71
AK		 1449 }
1450
e8e26350
PW		 1451 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1452 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1453 v_idx);
e8e26350
PW		 1454 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1455 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1456 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1457
41fb9248 1458 /* set up to autoclear timer, and the vectors */
021230d4 1459 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1460 if (adapter->num_vfs)
1461 mask &= ~(IXGBE_EIMS_OTHER |
1462 IXGBE_EIMS_MAILBOX |
1463 IXGBE_EIMS_LSC);
1464 else
1465 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1467}
1468
f494e8fa
AV		 1469enum latency_range {
1470 lowest_latency = 0,
1471 low_latency = 1,
1472 bulk_latency = 2,
1473 latency_invalid = 255
1474};
1475
1476/**
1477 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1478 * @adapter: pointer to adapter
1479 * @eitr: eitr setting (ints per sec) to give last timeslice
1480 * @itr_setting: current throttle rate in ints/second
1481 * @packets: the number of packets during this measurement interval
1482 * @bytes: the number of bytes during this measurement interval
1483 *
1484 * Stores a new ITR value based on packets and byte
1485 * counts during the last interrupt. The advantage of per interrupt
1486 * computation is faster updates and more accurate ITR for the current
1487 * traffic pattern. Constants in this function were computed
1488 * based on theoretical maximum wire speed and thresholds were set based
1489 * on testing data as well as attempting to minimize response time
1490 * while increasing bulk throughput.
1491 * this functionality is controlled by the InterruptThrottleRate module
1492 * parameter (see ixgbe_param.c)
1493 **/
1494static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1495 u32 eitr, u8 itr_setting,
1496 int packets, int bytes)
f494e8fa
AV		 1497{
1498 unsigned int retval = itr_setting;
1499 u32 timepassed_us;
1500 u64 bytes_perint;
1501
1502 if (packets == 0)
1503 goto update_itr_done;
1504
1505
1506 /* simple throttlerate management
1507 * 0-20MB/s lowest (100000 ints/s)
1508 * 20-100MB/s low (20000 ints/s)
1509 * 100-1249MB/s bulk (8000 ints/s)
1510 */
1511 /* what was last interrupt timeslice? */
1512 timepassed_us = 1000000/eitr;
1513 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1514
1515 switch (itr_setting) {
1516 case lowest_latency:
1517 if (bytes_perint > adapter->eitr_low)
1518 retval = low_latency;
1519 break;
1520 case low_latency:
1521 if (bytes_perint > adapter->eitr_high)
1522 retval = bulk_latency;
1523 else if (bytes_perint <= adapter->eitr_low)
1524 retval = lowest_latency;
1525 break;
1526 case bulk_latency:
1527 if (bytes_perint <= adapter->eitr_high)
1528 retval = low_latency;
1529 break;
1530 }
1531
1532update_itr_done:
1533 return retval;
1534}
1535
509ee935
JB		 1536/**
1537 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1538 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1539 *
1540 * This function is made to be called by ethtool and by the driver
1541 * when it needs to update EITR registers at runtime. Hardware
1542 * specific quirks/differences are taken care of here.
1543 */
fe49f04a 1544void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1545{
fe49f04a 1546 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1547 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1548 int v_idx = q_vector->v_idx;
1549 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1550
509ee935
JB		 1551 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1552 /* must write high and low 16 bits to reset counter */
1553 itr_reg |= (itr_reg << 16);
1554 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1555 /*
1556 * 82599 can support a value of zero, so allow it for
1557 * max interrupt rate, but there is an errata where it can
1558 * not be zero with RSC
1559 */
1560 if (itr_reg == 8 &&
1561 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1562 itr_reg = 0;
1563
509ee935
JB		 1564 /*
1565 * set the WDIS bit to not clear the timer bits and cause an
1566 * immediate assertion of the interrupt
1567 */
1568 itr_reg |= IXGBE_EITR_CNT_WDIS;
1569 }
1570 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1571}
1572
f494e8fa
AV		 1573static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1574{
1575 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1576 u32 new_itr;
1577 u8 current_itr, ret_itr;
fe49f04a 1578 int i, r_idx;
f494e8fa
AV		 1579 struct ixgbe_ring *rx_ring, *tx_ring;
1580
1581 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1582 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1583 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1584 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1585 q_vector->tx_itr,
1586 tx_ring->total_packets,
1587 tx_ring->total_bytes);
f494e8fa
AV		 1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
30efa5a3 1590 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1591 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1592 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1593 r_idx + 1);
f494e8fa
AV		 1594 }
1595
1596 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1597 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1598 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1599 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1600 q_vector->rx_itr,
1601 rx_ring->total_packets,
1602 rx_ring->total_bytes);
f494e8fa
AV		 1603 /* if the result for this queue would decrease interrupt
1604 * rate for this vector then use that result */
30efa5a3 1605 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1606 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1607 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1608 r_idx + 1);
f494e8fa
AV		 1609 }
1610
30efa5a3 1611 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1612
1613 switch (current_itr) {
1614 /* counts and packets in update_itr are dependent on these numbers */
1615 case lowest_latency:
1616 new_itr = 100000;
1617 break;
1618 case low_latency:
1619 new_itr = 20000; /* aka hwitr = ~200 */
1620 break;
1621 case bulk_latency:
1622 default:
1623 new_itr = 8000;
1624 break;
1625 }
1626
1627 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1628 /* do an exponential smoothing */
1629 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1630
1631 /* save the algorithm value here, not the smoothed one */
1632 q_vector->eitr = new_itr;
fe49f04a
AD		 1633
1634 ixgbe_write_eitr(q_vector);
f494e8fa 1635 }
f494e8fa
AV		 1636}
1637
119fc60a
MC		 1638/**
1639 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1640 * @work: pointer to work_struct containing our data
1641 **/
1642static void ixgbe_check_overtemp_task(struct work_struct *work)
1643{
1644 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1645 struct ixgbe_adapter,
1646 check_overtemp_task);
119fc60a
MC		 1647 struct ixgbe_hw *hw = &adapter->hw;
1648 u32 eicr = adapter->interrupt_event;
1649
7ca647bd
JP		 1650 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1651 return;
1652
1653 switch (hw->device_id) {
1654 case IXGBE_DEV_ID_82599_T3_LOM: {
1655 u32 autoneg;
1656 bool link_up = false;
1657
1658 if (hw->mac.ops.check_link)
1659 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1660
1661 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1662 (eicr & IXGBE_EICR_LSC))
1663 /* Check if this is due to overtemp */
1664 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1665 break;
1666 return;
1667 }
1668 default:
1669 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1670 return;
7ca647bd 1671 break;
119fc60a 1672 }
7ca647bd
JP		 1673 e_crit(drv,
1674 "Network adapter has been stopped because it has over heated. "
1675 "Restart the computer. If the problem persists, "
1676 "power off the system and replace the adapter\n");
1677 /* write to clear the interrupt */
1678 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1679}
1680
0befdb3e
JB		 1681static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1682{
1683 struct ixgbe_hw *hw = &adapter->hw;
1684
1685 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1686 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1687 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1688 /* write to clear the interrupt */
1689 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1690 }
1691}
cf8280ee 1692
e8e26350
PW		 1693static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1694{
1695 struct ixgbe_hw *hw = &adapter->hw;
1696
1697 if (eicr & IXGBE_EICR_GPI_SDP1) {
1698 /* Clear the interrupt */
1699 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1700 schedule_work(&adapter->multispeed_fiber_task);
1701 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1702 /* Clear the interrupt */
1703 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1704 schedule_work(&adapter->sfp_config_module_task);
1705 } else {
1706 /* Interrupt isn't for us... */
1707 return;
1708 }
1709}
1710
cf8280ee
JB		 1711static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1712{
1713 struct ixgbe_hw *hw = &adapter->hw;
1714
1715 adapter->lsc_int++;
1716 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1717 adapter->link_check_timeout = jiffies;
1718 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1719 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1720 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1721 schedule_work(&adapter->watchdog_task);
1722 }
1723}
1724
9a799d71
AK		 1725static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1726{
1727 struct net_device *netdev = data;
1728 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1729 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1730 u32 eicr;
1731
1732 /*
1733 * Workaround for Silicon errata. Use clear-by-write instead
1734 * of clear-by-read. Reading with EICS will return the
1735 * interrupt causes without clearing, which later be done
1736 * with the write to EICR.
1737 */
1738 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1739 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1740
cf8280ee
JB		 1741 if (eicr & IXGBE_EICR_LSC)
1742 ixgbe_check_lsc(adapter);
d4f80882 1743
1cdd1ec8
GR		 1744 if (eicr & IXGBE_EICR_MAILBOX)
1745 ixgbe_msg_task(adapter);
1746
e8e26350
PW		 1747 if (hw->mac.type == ixgbe_mac_82598EB)
1748 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1749
c4cf55e5 1750 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1751 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1752 adapter->interrupt_event = eicr;
1753 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1754 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1755 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1756
1757 /* Handle Flow Director Full threshold interrupt */
1758 if (eicr & IXGBE_EICR_FLOW_DIR) {
1759 int i;
1760 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1761 /* Disable transmits before FDIR Re-initialization */
1762 netif_tx_stop_all_queues(netdev);
1763 for (i = 0; i < adapter->num_tx_queues; i++) {
1764 struct ixgbe_ring *tx_ring =
e8e9f696 1765 adapter->tx_ring[i];
c4cf55e5 1766 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 1767 &tx_ring->reinit_state))
c4cf55e5
PWJ		 1768 schedule_work(&adapter->fdir_reinit_task);
1769 }
1770 }
1771 }
d4f80882
AV		 1772 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1773 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1774
1775 return IRQ_HANDLED;
1776}
1777
fe49f04a
AD		 1778static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1779 u64 qmask)
1780{
1781 u32 mask;
1782
1783 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1784 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1785 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1786 } else {
1787 mask = (qmask & 0xFFFFFFFF);
1788 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1789 mask = (qmask >> 32);
1790 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1791 }
1792 /* skip the flush */
1793}
1794
1795static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1796 u64 qmask)
fe49f04a
AD		 1797{
1798 u32 mask;
1799
1800 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1801 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1802 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1803 } else {
1804 mask = (qmask & 0xFFFFFFFF);
1805 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1806 mask = (qmask >> 32);
1807 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1808 }
1809 /* skip the flush */
1810}
1811
9a799d71
AK		 1812static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1813{
021230d4
AV		 1814 struct ixgbe_q_vector *q_vector = data;
1815 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1816 struct ixgbe_ring *tx_ring;
021230d4
AV		 1817 int i, r_idx;
1818
1819 if (!q_vector->txr_count)
1820 return IRQ_HANDLED;
1821
1822 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1823 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1824 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1825 tx_ring->total_bytes = 0;
1826 tx_ring->total_packets = 0;
021230d4 1827 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1828 r_idx + 1);
021230d4 1829 }
9a799d71 1830
9b471446 1831 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1832 napi_schedule(&q_vector->napi);
1833
9a799d71
AK		 1834 return IRQ_HANDLED;
1835}
1836
021230d4
AV		 1837/**
1838 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1839 * @irq: unused
1840 * @data: pointer to our q_vector struct for this interrupt vector
1841 **/
9a799d71
AK		 1842static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1843{
021230d4
AV		 1844 struct ixgbe_q_vector *q_vector = data;
1845 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1846 struct ixgbe_ring *rx_ring;
021230d4 1847 int r_idx;
30efa5a3 1848 int i;
021230d4
AV		 1849
1850 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1851 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1852 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1853 rx_ring->total_bytes = 0;
1854 rx_ring->total_packets = 0;
1855 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1856 r_idx + 1);
30efa5a3
JB		 1857 }
1858
021230d4
AV		 1859 if (!q_vector->rxr_count)
1860 return IRQ_HANDLED;
1861
021230d4 1862 /* disable interrupts on this vector only */
9b471446 1863 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1864 napi_schedule(&q_vector->napi);
021230d4
AV		 1865
1866 return IRQ_HANDLED;
1867}
1868
1869static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1870{
91281fd3
AD		 1871 struct ixgbe_q_vector *q_vector = data;
1872 struct ixgbe_adapter *adapter = q_vector->adapter;
1873 struct ixgbe_ring *ring;
1874 int r_idx;
1875 int i;
1876
1877 if (!q_vector->txr_count && !q_vector->rxr_count)
1878 return IRQ_HANDLED;
1879
1880 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1881 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1882 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1883 ring->total_bytes = 0;
1884 ring->total_packets = 0;
1885 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1886 r_idx + 1);
91281fd3
AD		 1887 }
1888
1889 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1890 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1891 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1892 ring->total_bytes = 0;
1893 ring->total_packets = 0;
1894 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1895 r_idx + 1);
91281fd3
AD		 1896 }
1897
9b471446 1898 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1899 napi_schedule(&q_vector->napi);
9a799d71 1900
9a799d71
AK		 1901 return IRQ_HANDLED;
1902}
1903
021230d4
AV		 1904/**
1905 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1906 * @napi: napi struct with our devices info in it
1907 * @budget: amount of work driver is allowed to do this pass, in packets
1908 *
f0848276
JB		 1909 * This function is optimized for cleaning one queue only on a single
1910 * q_vector!!!
021230d4 1911 **/
9a799d71
AK		 1912static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1913{
021230d4 1914 struct ixgbe_q_vector *q_vector =
e8e9f696 1915 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1916 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1917 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1918 int work_done = 0;
021230d4 1919 long r_idx;
9a799d71 1920
021230d4 1921 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1922 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1923#ifdef CONFIG_IXGBE_DCA
bd0362dd 1924 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1925 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1926#endif
9a799d71 1927
78b6f4ce 1928 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1929
021230d4
AV		 1930 /* If all Rx work done, exit the polling mode */
1931 if (work_done < budget) {
288379f0 1932 napi_complete(napi);
f7554a2b 1933 if (adapter->rx_itr_setting & 1)
f494e8fa 1934 ixgbe_set_itr_msix(q_vector);
9a799d71 1935 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1936 ixgbe_irq_enable_queues(adapter,
e8e9f696 1937 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1938 }
1939
1940 return work_done;
1941}
1942
f0848276 1943/**
91281fd3 1944 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1945 * @napi: napi struct with our devices info in it
1946 * @budget: amount of work driver is allowed to do this pass, in packets
1947 *
1948 * This function will clean more than one rx queue associated with a
1949 * q_vector.
1950 **/
91281fd3 1951static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1952{
1953 struct ixgbe_q_vector *q_vector =
e8e9f696 1954 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 1955 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1956 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1957 int work_done = 0, i;
1958 long r_idx;
91281fd3
AD		 1959 bool tx_clean_complete = true;
1960
1961 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1962 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1963 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1964#ifdef CONFIG_IXGBE_DCA
1965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966 ixgbe_update_tx_dca(adapter, ring);
1967#endif
1968 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1969 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1970 r_idx + 1);
91281fd3 1971 }
f0848276
JB		 1972
1973 /* attempt to distribute budget to each queue fairly, but don't allow
1974 * the budget to go below 1 because we'll exit polling */
1975 budget /= (q_vector->rxr_count ?: 1);
1976 budget = max(budget, 1);
1977 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1978 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1979 ring = adapter->rx_ring[r_idx];
5dd2d332 1980#ifdef CONFIG_IXGBE_DCA
f0848276 1981 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1982 ixgbe_update_rx_dca(adapter, ring);
f0848276 1983#endif
91281fd3 1984 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 1985 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1986 r_idx + 1);
f0848276
JB		 1987 }
1988
1989 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1990 ring = adapter->rx_ring[r_idx];
f0848276 1991 /* If all Rx work done, exit the polling mode */
7f821875 1992 if (work_done < budget) {
288379f0 1993 napi_complete(napi);
f7554a2b 1994 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1995 ixgbe_set_itr_msix(q_vector);
1996 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1997 ixgbe_irq_enable_queues(adapter,
e8e9f696 1998 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1999 return 0;
2000 }
2001
2002 return work_done;
2003}
91281fd3
AD		 2004
2005/**
2006 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2007 * @napi: napi struct with our devices info in it
2008 * @budget: amount of work driver is allowed to do this pass, in packets
2009 *
2010 * This function is optimized for cleaning one queue only on a single
2011 * q_vector!!!
2012 **/
2013static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2014{
2015 struct ixgbe_q_vector *q_vector =
e8e9f696 2016 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2017 struct ixgbe_adapter *adapter = q_vector->adapter;
2018 struct ixgbe_ring *tx_ring = NULL;
2019 int work_done = 0;
2020 long r_idx;
2021
2022 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 2023 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2024#ifdef CONFIG_IXGBE_DCA
2025 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2026 ixgbe_update_tx_dca(adapter, tx_ring);
2027#endif
2028
2029 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2030 work_done = budget;
2031
f7554a2b 2032 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2033 if (work_done < budget) {
2034 napi_complete(napi);
f7554a2b 2035 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2036 ixgbe_set_itr_msix(q_vector);
2037 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2038 ixgbe_irq_enable_queues(adapter,
2039 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2040 }
2041
2042 return work_done;
2043}
2044
021230d4 2045static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2046 int r_idx)
021230d4 2047{
7a921c93
AD		 2048 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2049
2050 set_bit(r_idx, q_vector->rxr_idx);
2051 q_vector->rxr_count++;
021230d4
AV		 2052}
2053
2054static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2055 int t_idx)
021230d4 2056{
7a921c93
AD		 2057 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2058
2059 set_bit(t_idx, q_vector->txr_idx);
2060 q_vector->txr_count++;
021230d4
AV		 2061}
2062
9a799d71 2063/**
021230d4
AV		 2064 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2065 * @adapter: board private structure to initialize
2066 * @vectors: allotted vector count for descriptor rings
9a799d71 2067 *
021230d4
AV		 2068 * This function maps descriptor rings to the queue-specific vectors
2069 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2070 * one vector per ring/queue, but on a constrained vector budget, we
2071 * group the rings as "efficiently" as possible. You would add new
2072 * mapping configurations in here.
9a799d71 2073 **/
021230d4 2074static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
e8e9f696 2075 int vectors)
021230d4
AV		 2076{
2077 int v_start = 0;
2078 int rxr_idx = 0, txr_idx = 0;
2079 int rxr_remaining = adapter->num_rx_queues;
2080 int txr_remaining = adapter->num_tx_queues;
2081 int i, j;
2082 int rqpv, tqpv;
2083 int err = 0;
2084
2085 /* No mapping required if MSI-X is disabled. */
2086 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2087 goto out;
9a799d71 2088
021230d4
AV		 2089 /*
2090 * The ideal configuration...
2091 * We have enough vectors to map one per queue.
2092 */
2093 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2094 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2095 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2096
021230d4
AV		 2097 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2098 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2099
9a799d71 2100 goto out;
021230d4 2101 }
9a799d71 2102
021230d4
AV		 2103 /*
2104 * If we don't have enough vectors for a 1-to-1
2105 * mapping, we'll have to group them so there are
2106 * multiple queues per vector.
2107 */
2108 /* Re-adjusting *qpv takes care of the remainder. */
2109 for (i = v_start; i < vectors; i++) {
2110 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2111 for (j = 0; j < rqpv; j++) {
2112 map_vector_to_rxq(adapter, i, rxr_idx);
2113 rxr_idx++;
2114 rxr_remaining--;
2115 }
2116 }
2117 for (i = v_start; i < vectors; i++) {
2118 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2119 for (j = 0; j < tqpv; j++) {
2120 map_vector_to_txq(adapter, i, txr_idx);
2121 txr_idx++;
2122 txr_remaining--;
9a799d71 2123 }
9a799d71
AK		 2124 }
2125
021230d4
AV		 2126out:
2127 return err;
2128}
2129
2130/**
2131 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2132 * @adapter: board private structure
2133 *
2134 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2135 * interrupts from the kernel.
2136 **/
2137static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2138{
2139 struct net_device *netdev = adapter->netdev;
2140 irqreturn_t (*handler)(int, void *);
2141 int i, vector, q_vectors, err;
e8e9f696 2142 int ri = 0, ti = 0;
021230d4
AV		 2143
2144 /* Decrement for Other and TCP Timer vectors */
2145 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2146
2147 /* Map the Tx/Rx rings to the vectors we were allotted. */
2148 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2149 if (err)
2150 goto out;
2151
2152#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
e8e9f696
JP		 2153 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2154 &ixgbe_msix_clean_many)
021230d4 2155 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2156 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20 2157
e8e9f696 2158 if (handler == &ixgbe_msix_clean_rx) {
cb13fc20
RO		 2159 sprintf(adapter->name[vector], "%s-%s-%d",
2160 netdev->name, "rx", ri++);
e8e9f696 2161 } else if (handler == &ixgbe_msix_clean_tx) {
cb13fc20
RO		 2162 sprintf(adapter->name[vector], "%s-%s-%d",
2163 netdev->name, "tx", ti++);
e8e9f696 2164 } else
cb13fc20
RO		 2165 sprintf(adapter->name[vector], "%s-%s-%d",
2166 netdev->name, "TxRx", vector);
2167
021230d4 2168 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696
JP		 2169 handler, 0, adapter->name[vector],
2170 adapter->q_vector[vector]);
9a799d71 2171 if (err) {
396e799c 2172 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2173 "Error: %d\n", err);
021230d4 2174 goto free_queue_irqs;
9a799d71 2175 }
9a799d71
AK		 2176 }
2177
021230d4
AV		 2178 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2179 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696 2180 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2181 if (err) {
396e799c 2182 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2183 goto free_queue_irqs;
9a799d71
AK		 2184 }
2185
9a799d71
AK		 2186 return 0;
2187
021230d4
AV		 2188free_queue_irqs:
2189 for (i = vector - 1; i >= 0; i--)
2190 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2191 adapter->q_vector[i]);
021230d4
AV		 2192 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2193 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2194 kfree(adapter->msix_entries);
2195 adapter->msix_entries = NULL;
021230d4 2196out:
9a799d71
AK		 2197 return err;
2198}
2199
f494e8fa
AV		 2200static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2201{
7a921c93 2202 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2203 u8 current_itr;
2204 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2205 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2206 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2207
30efa5a3 2208 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2209 q_vector->tx_itr,
2210 tx_ring->total_packets,
2211 tx_ring->total_bytes);
30efa5a3 2212 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2213 q_vector->rx_itr,
2214 rx_ring->total_packets,
2215 rx_ring->total_bytes);
f494e8fa 2216
30efa5a3 2217 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2218
2219 switch (current_itr) {
2220 /* counts and packets in update_itr are dependent on these numbers */
2221 case lowest_latency:
2222 new_itr = 100000;
2223 break;
2224 case low_latency:
2225 new_itr = 20000; /* aka hwitr = ~200 */
2226 break;
2227 case bulk_latency:
2228 new_itr = 8000;
2229 break;
2230 default:
2231 break;
2232 }
2233
2234 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2235 /* do an exponential smoothing */
2236 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2237
2238 /* save the algorithm value here, not the smoothed one */
2239 q_vector->eitr = new_itr;
fe49f04a
AD		 2240
2241 ixgbe_write_eitr(q_vector);
f494e8fa 2242 }
f494e8fa
AV		 2243}
2244
79aefa45
AD		 2245/**
2246 * ixgbe_irq_enable - Enable default interrupt generation settings
2247 * @adapter: board private structure
2248 **/
6af3b9eb
ET		 2249static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2250 bool flush)
79aefa45
AD		 2251{
2252 u32 mask;
835462fc
NS		 2253
2254 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2255 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2256 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2257 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2258 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2259 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2260 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2261 mask |= IXGBE_EIMS_GPI_SDP1;
2262 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2263 if (adapter->num_vfs)
2264 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2265 }
c4cf55e5
PWJ		 2266 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2267 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2268 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2269
79aefa45 2270 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2271 if (queues)
2272 ixgbe_irq_enable_queues(adapter, ~0);
2273 if (flush)
2274 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2275
2276 if (adapter->num_vfs > 32) {
2277 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2278 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2279 }
79aefa45 2280}
021230d4 2281
9a799d71 2282/**
021230d4 2283 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2284 * @irq: interrupt number
2285 * @data: pointer to a network interface device structure
9a799d71
AK		 2286 **/
2287static irqreturn_t ixgbe_intr(int irq, void *data)
2288{
2289 struct net_device *netdev = data;
2290 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2291 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2292 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2293 u32 eicr;
2294
54037505 2295 /*
6af3b9eb 2296 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2297 * before the read of EICR.
2298 */
2299 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2300
021230d4
AV		 2301 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2302 * therefore no explict interrupt disable is necessary */
2303 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2304 if (!eicr) {
6af3b9eb
ET		 2305 /*
2306 * shared interrupt alert!
f47cf66e 2307 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2308 * have disabled interrupts due to EIAM
2309 * finish the workaround of silicon errata on 82598. Unmask
2310 * the interrupt that we masked before the EICR read.
2311 */
2312 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2313 ixgbe_irq_enable(adapter, true, true);
9a799d71 2314 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2315 }
9a799d71 2316
cf8280ee
JB		 2317 if (eicr & IXGBE_EICR_LSC)
2318 ixgbe_check_lsc(adapter);
021230d4 2319
e8e26350
PW		 2320 if (hw->mac.type == ixgbe_mac_82599EB)
2321 ixgbe_check_sfp_event(adapter, eicr);
2322
0befdb3e 2323 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2324 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2325 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2326 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2327
7a921c93 2328 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2329 adapter->tx_ring[0]->total_packets = 0;
2330 adapter->tx_ring[0]->total_bytes = 0;
2331 adapter->rx_ring[0]->total_packets = 0;
2332 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2333 /* would disable interrupts here but EIAM disabled it */
7a921c93 2334 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2335 }
2336
6af3b9eb
ET		 2337 /*
2338 * re-enable link(maybe) and non-queue interrupts, no flush.
2339 * ixgbe_poll will re-enable the queue interrupts
2340 */
2341
2342 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2343 ixgbe_irq_enable(adapter, false, false);
2344
9a799d71
AK		 2345 return IRQ_HANDLED;
2346}
2347
021230d4
AV		 2348static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2349{
2350 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2351
2352 for (i = 0; i < q_vectors; i++) {
7a921c93 2353 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2354 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2355 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2356 q_vector->rxr_count = 0;
2357 q_vector->txr_count = 0;
2358 }
2359}
2360
9a799d71
AK		 2361/**
2362 * ixgbe_request_irq - initialize interrupts
2363 * @adapter: board private structure
2364 *
2365 * Attempts to configure interrupts using the best available
2366 * capabilities of the hardware and kernel.
2367 **/
021230d4 2368static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2369{
2370 struct net_device *netdev = adapter->netdev;
021230d4 2371 int err;
9a799d71 2372
021230d4
AV		 2373 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2374 err = ixgbe_request_msix_irqs(adapter);
2375 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2376 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2377 netdev->name, netdev);
021230d4 2378 } else {
a0607fd3 2379 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2380 netdev->name, netdev);
9a799d71
AK		 2381 }
2382
9a799d71 2383 if (err)
396e799c 2384 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2385
9a799d71
AK		 2386 return err;
2387}
2388
2389static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2390{
2391 struct net_device *netdev = adapter->netdev;
2392
2393 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2394 int i, q_vectors;
9a799d71 2395
021230d4
AV		 2396 q_vectors = adapter->num_msix_vectors;
2397
2398 i = q_vectors - 1;
9a799d71 2399 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2400
021230d4
AV		 2401 i--;
2402 for (; i >= 0; i--) {
2403 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2404 adapter->q_vector[i]);
021230d4
AV		 2405 }
2406
2407 ixgbe_reset_q_vectors(adapter);
2408 } else {
2409 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2410 }
2411}
2412
22d5a71b
JB		 2413/**
2414 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2415 * @adapter: board private structure
2416 **/
2417static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2418{
835462fc
NS		 2419 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2420 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2421 } else {
2422 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2425 if (adapter->num_vfs > 32)
2426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2427 }
2428 IXGBE_WRITE_FLUSH(&adapter->hw);
2429 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2430 int i;
2431 for (i = 0; i < adapter->num_msix_vectors; i++)
2432 synchronize_irq(adapter->msix_entries[i].vector);
2433 } else {
2434 synchronize_irq(adapter->pdev->irq);
2435 }
2436}
2437
9a799d71
AK		 2438/**
2439 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2440 *
2441 **/
2442static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2443{
9a799d71
AK		 2444 struct ixgbe_hw *hw = &adapter->hw;
2445
021230d4 2446 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2447 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2448
e8e26350
PW		 2449 ixgbe_set_ivar(adapter, 0, 0, 0);
2450 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2451
2452 map_vector_to_rxq(adapter, 0, 0);
2453 map_vector_to_txq(adapter, 0, 0);
2454
396e799c 2455 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2456}
2457
43e69bf0
AD		 2458/**
2459 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2460 * @adapter: board private structure
2461 * @ring: structure containing ring specific data
2462 *
2463 * Configure the Tx descriptor ring after a reset.
2464 **/
84418e3b
AD		 2465void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2466 struct ixgbe_ring *ring)
43e69bf0
AD		 2467{
2468 struct ixgbe_hw *hw = &adapter->hw;
2469 u64 tdba = ring->dma;
2f1860b8
AD		 2470 int wait_loop = 10;
2471 u32 txdctl;
43e69bf0
AD		 2472 u16 reg_idx = ring->reg_idx;
2473
2f1860b8
AD		 2474 /* disable queue to avoid issues while updating state */
2475 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2476 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2477 txdctl & ~IXGBE_TXDCTL_ENABLE);
2478 IXGBE_WRITE_FLUSH(hw);
2479
43e69bf0 2480 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2481 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2482 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2483 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2484 ring->count * sizeof(union ixgbe_adv_tx_desc));
2485 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2486 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2487 ring->head = IXGBE_TDH(reg_idx);
2488 ring->tail = IXGBE_TDT(reg_idx);
2489
2f1860b8
AD		 2490 /* configure fetching thresholds */
2491 if (adapter->rx_itr_setting == 0) {
2492 /* cannot set wthresh when itr==0 */
2493 txdctl &= ~0x007F0000;
2494 } else {
2495 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2496 txdctl |= (8 << 16);
2497 }
2498 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2499 /* PThresh workaround for Tx hang with DFP enabled. */
2500 txdctl |= 32;
2501 }
2502
2503 /* reinitialize flowdirector state */
2504 set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2505
2506 /* enable queue */
2507 txdctl |= IXGBE_TXDCTL_ENABLE;
2508 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2509
2510 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2511 if (hw->mac.type == ixgbe_mac_82598EB &&
2512 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2513 return;
2514
2515 /* poll to verify queue is enabled */
2516 do {
2517 msleep(1);
2518 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2519 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2520 if (!wait_loop)
2521 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2522}
2523
120ff942
AD		 2524static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2525{
2526 struct ixgbe_hw *hw = &adapter->hw;
2527 u32 rttdcs;
2528 u32 mask;
2529
2530 if (hw->mac.type == ixgbe_mac_82598EB)
2531 return;
2532
2533 /* disable the arbiter while setting MTQC */
2534 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2535 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2536 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2537
2538 /* set transmit pool layout */
2539 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2540 switch (adapter->flags & mask) {
2541
2542 case (IXGBE_FLAG_SRIOV_ENABLED):
2543 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2544 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2545 break;
2546
2547 case (IXGBE_FLAG_DCB_ENABLED):
2548 /* We enable 8 traffic classes, DCB only */
2549 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2550 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2551 break;
2552
2553 default:
2554 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2555 break;
2556 }
2557
2558 /* re-enable the arbiter */
2559 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2560 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2561}
2562
9a799d71 2563/**
3a581073 2564 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2565 * @adapter: board private structure
2566 *
2567 * Configure the Tx unit of the MAC after a reset.
2568 **/
2569static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2570{
2f1860b8
AD		 2571 struct ixgbe_hw *hw = &adapter->hw;
2572 u32 dmatxctl;
43e69bf0 2573 u32 i;
9a799d71 2574
2f1860b8
AD		 2575 ixgbe_setup_mtqc(adapter);
2576
2577 if (hw->mac.type != ixgbe_mac_82598EB) {
2578 /* DMATXCTL.EN must be before Tx queues are enabled */
2579 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2580 dmatxctl |= IXGBE_DMATXCTL_TE;
2581 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2582 }
2583
9a799d71 2584 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2585 for (i = 0; i < adapter->num_tx_queues; i++)
2586 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2587}
2588
e8e26350 2589#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2590
a6616b42 2591static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2592 struct ixgbe_ring *rx_ring)
cc41ac7c 2593{
cc41ac7c 2594 u32 srrctl;
a6616b42 2595 int index;
0cefafad 2596 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2597
a6616b42
YZ		 2598 index = rx_ring->reg_idx;
2599 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2600 unsigned long mask;
0cefafad 2601 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2602 index = index & mask;
cc41ac7c 2603 }
cc41ac7c
JB		 2604 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2605
2606 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2607 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2608 if (adapter->num_vfs)
2609 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2610
afafd5b0
AD		 2611 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2612 IXGBE_SRRCTL_BSIZEHDR_MASK;
2613
6e455b89 2614 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2615#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2616 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2617#else
2618 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2619#endif
cc41ac7c 2620 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2621 } else {
afafd5b0
AD		 2622 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2623 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2624 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2625 }
e8e26350 2626
cc41ac7c
JB		 2627 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2628}
9a799d71 2629
05abb126 2630static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2631{
05abb126
AD		 2632 struct ixgbe_hw *hw = &adapter->hw;
2633 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2634 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2635 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2636 u32 mrqc = 0, reta = 0;
2637 u32 rxcsum;
2638 int i, j;
0cefafad
JB		 2639 int mask;
2640
05abb126
AD		 2641 /* Fill out hash function seeds */
2642 for (i = 0; i < 10; i++)
2643 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2644
2645 /* Fill out redirection table */
2646 for (i = 0, j = 0; i < 128; i++, j++) {
2647 if (j == adapter->ring_feature[RING_F_RSS].indices)
2648 j = 0;
2649 /* reta = 4-byte sliding window of
2650 * 0x00..(indices-1)(indices-1)00..etc. */
2651 reta = (reta << 8) | (j * 0x11);
2652 if ((i & 3) == 3)
2653 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2654 }
0cefafad 2655
05abb126
AD		 2656 /* Disable indicating checksum in descriptor, enables RSS hash */
2657 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2658 rxcsum |= IXGBE_RXCSUM_PCSD;
2659 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2660
2661 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2662 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2663 else
2664 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2665#ifdef CONFIG_IXGBE_DCB
05abb126 2666 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2667#endif
05abb126
AD		 2668 | IXGBE_FLAG_SRIOV_ENABLED
2669 );
0cefafad
JB		 2670
2671 switch (mask) {
2672 case (IXGBE_FLAG_RSS_ENABLED):
2673 mrqc = IXGBE_MRQC_RSSEN;
2674 break;
1cdd1ec8
GR		 2675 case (IXGBE_FLAG_SRIOV_ENABLED):
2676 mrqc = IXGBE_MRQC_VMDQEN;
2677 break;
0cefafad
JB		 2678#ifdef CONFIG_IXGBE_DCB
2679 case (IXGBE_FLAG_DCB_ENABLED):
2680 mrqc = IXGBE_MRQC_RT8TCEN;
2681 break;
2682#endif /* CONFIG_IXGBE_DCB */
2683 default:
2684 break;
2685 }
2686
05abb126
AD		 2687 /* Perform hash on these packet types */
2688 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2689 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2690 | IXGBE_MRQC_RSS_FIELD_IPV6
2691 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2692
2693 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2694}
2695
bb5a9ad2
NS		 2696/**
2697 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2698 * @adapter: address of board private structure
2699 * @index: index of ring to set
bb5a9ad2 2700 **/
7367096a
AD		 2701static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2702 struct ixgbe_ring *ring)
bb5a9ad2 2703{
bb5a9ad2 2704 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2705 u32 rscctrl;
edd2ea55 2706 int rx_buf_len;
7367096a
AD		 2707 u16 reg_idx = ring->reg_idx;
2708
2709 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2710 return;
bb5a9ad2 2711
7367096a
AD		 2712 rx_buf_len = ring->rx_buf_len;
2713 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2714 rscctrl |= IXGBE_RSCCTL_RSCEN;
2715 /*
2716 * we must limit the number of descriptors so that the
2717 * total size of max desc * buf_len is not greater
2718 * than 65535
2719 */
7367096a 2720 if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
bb5a9ad2
NS		 2721#if (MAX_SKB_FRAGS > 16)
2722 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2723#elif (MAX_SKB_FRAGS > 8)
2724 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2725#elif (MAX_SKB_FRAGS > 4)
2726 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2727#else
2728 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2729#endif
2730 } else {
2731 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2732 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2733 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2734 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2735 else
2736 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2737 }
7367096a 2738 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2739}
2740
9e10e045
AD		 2741/**
2742 * ixgbe_set_uta - Set unicast filter table address
2743 * @adapter: board private structure
2744 *
2745 * The unicast table address is a register array of 32-bit registers.
2746 * The table is meant to be used in a way similar to how the MTA is used
2747 * however due to certain limitations in the hardware it is necessary to
2748 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2749 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2750 **/
2751static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2752{
2753 struct ixgbe_hw *hw = &adapter->hw;
2754 int i;
2755
2756 /* The UTA table only exists on 82599 hardware and newer */
2757 if (hw->mac.type < ixgbe_mac_82599EB)
2758 return;
2759
2760 /* we only need to do this if VMDq is enabled */
2761 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2762 return;
2763
2764 for (i = 0; i < 128; i++)
2765 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2766}
2767
2768#define IXGBE_MAX_RX_DESC_POLL 10
2769static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2770 struct ixgbe_ring *ring)
2771{
2772 struct ixgbe_hw *hw = &adapter->hw;
2773 int reg_idx = ring->reg_idx;
2774 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2775 u32 rxdctl;
2776
2777 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2778 if (hw->mac.type == ixgbe_mac_82598EB &&
2779 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2780 return;
2781
2782 do {
2783 msleep(1);
2784 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2785 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2786
2787 if (!wait_loop) {
2788 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2789 "the polling period\n", reg_idx);
2790 }
2791}
2792
84418e3b
AD		 2793void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2794 struct ixgbe_ring *ring)
acd37177
AD		 2795{
2796 struct ixgbe_hw *hw = &adapter->hw;
2797 u64 rdba = ring->dma;
9e10e045 2798 u32 rxdctl;
acd37177
AD		 2799 u16 reg_idx = ring->reg_idx;
2800
9e10e045
AD		 2801 /* disable queue to avoid issues while updating state */
2802 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2803 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2804 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2805 IXGBE_WRITE_FLUSH(hw);
2806
acd37177
AD		 2807 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2808 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2809 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2810 ring->count * sizeof(union ixgbe_adv_rx_desc));
2811 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2812 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2813 ring->head = IXGBE_RDH(reg_idx);
2814 ring->tail = IXGBE_RDT(reg_idx);
9e10e045
AD		 2815
2816 ixgbe_configure_srrctl(adapter, ring);
2817 ixgbe_configure_rscctl(adapter, ring);
2818
2819 if (hw->mac.type == ixgbe_mac_82598EB) {
2820 /*
2821 * enable cache line friendly hardware writes:
2822 * PTHRESH=32 descriptors (half the internal cache),
2823 * this also removes ugly rx_no_buffer_count increment
2824 * HTHRESH=4 descriptors (to minimize latency on fetch)
2825 * WTHRESH=8 burst writeback up to two cache lines
2826 */
2827 rxdctl &= ~0x3FFFFF;
2828 rxdctl |= 0x080420;
2829 }
2830
2831 /* enable receive descriptor ring */
2832 rxdctl |= IXGBE_RXDCTL_ENABLE;
2833 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2834
2835 ixgbe_rx_desc_queue_enable(adapter, ring);
2836 ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 2837}
2838
48654521
AD		 2839static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2840{
2841 struct ixgbe_hw *hw = &adapter->hw;
2842 int p;
2843
2844 /* PSRTYPE must be initialized in non 82598 adapters */
2845 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2846 IXGBE_PSRTYPE_UDPHDR |
2847 IXGBE_PSRTYPE_IPV4HDR |
48654521 2848 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2849 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2850
2851 if (hw->mac.type == ixgbe_mac_82598EB)
2852 return;
2853
2854 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2855 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2856
2857 for (p = 0; p < adapter->num_rx_pools; p++)
2858 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2859 psrtype);
2860}
2861
f5b4a52e
AD		 2862static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2863{
2864 struct ixgbe_hw *hw = &adapter->hw;
2865 u32 gcr_ext;
2866 u32 vt_reg_bits;
2867 u32 reg_offset, vf_shift;
2868 u32 vmdctl;
2869
2870 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2871 return;
2872
2873 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2874 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2875 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2876 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2877
2878 vf_shift = adapter->num_vfs % 32;
2879 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2880
2881 /* Enable only the PF's pool for Tx/Rx */
2882 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2883 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2884 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2885 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2886 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2887
2888 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2889 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2890
2891 /*
2892 * Set up VF register offsets for selected VT Mode,
2893 * i.e. 32 or 64 VFs for SR-IOV
2894 */
2895 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2896 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2897 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2898 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2899
2900 /* enable Tx loopback for VF/PF communication */
2901 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2902}
2903
477de6ed 2904static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2905{
9a799d71
AK		 2906 struct ixgbe_hw *hw = &adapter->hw;
2907 struct net_device *netdev = adapter->netdev;
2908 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2909 int rx_buf_len;
477de6ed
AD		 2910 struct ixgbe_ring *rx_ring;
2911 int i;
2912 u32 mhadd, hlreg0;
48654521 2913
9a799d71 2914 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2915 /* Do not use packet split if we're in SR-IOV Mode */
2916 if (!adapter->num_vfs)
2917 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2918
2919 /* Set the RX buffer length according to the mode */
2920 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2921 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2922 } else {
0c19d6af 2923 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2924 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2925 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2926 else
477de6ed 2927 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 2928 }
2929
63f39bd1 2930#ifdef IXGBE_FCOE
477de6ed
AD		 2931 /* adjust max frame to be able to do baby jumbo for FCoE */
2932 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2933 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2934 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2935
477de6ed
AD		 2936#endif /* IXGBE_FCOE */
2937 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2938 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2939 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2940 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2941
2942 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2943 }
2944
2945 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2946 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2947 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2948 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2949
0cefafad
JB		 2950 /*
2951 * Setup the HW Rx Head and Tail Descriptor Pointers and
2952 * the Base and Length of the Rx Descriptor Ring
2953 */
9a799d71 2954 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2955 rx_ring = adapter->rx_ring[i];
a6616b42 2956 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2957
6e455b89
YZ		 2958 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2959 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2960 else
2961 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2962
63f39bd1 2963#ifdef IXGBE_FCOE
e8e9f696 2964 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2965 struct ixgbe_ring_feature *f;
2966 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2967 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2968 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2969 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2970 rx_ring->rx_buf_len =
e8e9f696 2971 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2972 }
63f39bd1 2973 }
63f39bd1 2974#endif /* IXGBE_FCOE */
477de6ed
AD		 2975 }
2976
2977}
2978
7367096a
AD		 2979static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2980{
2981 struct ixgbe_hw *hw = &adapter->hw;
2982 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2983
2984 switch (hw->mac.type) {
2985 case ixgbe_mac_82598EB:
2986 /*
2987 * For VMDq support of different descriptor types or
2988 * buffer sizes through the use of multiple SRRCTL
2989 * registers, RDRXCTL.MVMEN must be set to 1
2990 *
2991 * also, the manual doesn't mention it clearly but DCA hints
2992 * will only use queue 0's tags unless this bit is set. Side
2993 * effects of setting this bit are only that SRRCTL must be
2994 * fully programmed [0..15]
2995 */
2996 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2997 break;
2998 case ixgbe_mac_82599EB:
2999 /* Disable RSC for ACK packets */
3000 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3001 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3002 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3003 /* hardware requires some bits to be set by default */
3004 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3005 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3006 break;
3007 default:
3008 /* We should do nothing since we don't know this hardware */
3009 return;
3010 }
3011
3012 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3013}
3014
477de6ed
AD		 3015/**
3016 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3017 * @adapter: board private structure
3018 *
3019 * Configure the Rx unit of the MAC after a reset.
3020 **/
3021static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3022{
3023 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3024 int i;
3025 u32 rxctrl;
477de6ed
AD		 3026
3027 /* disable receives while setting up the descriptors */
3028 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3029 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3030
3031 ixgbe_setup_psrtype(adapter);
7367096a 3032 ixgbe_setup_rdrxctl(adapter);
477de6ed 3033
9e10e045 3034 /* Program registers for the distribution of queues */
f5b4a52e 3035 ixgbe_setup_mrqc(adapter);
f5b4a52e 3036
9e10e045
AD		 3037 ixgbe_set_uta(adapter);
3038
477de6ed
AD		 3039 /* set_rx_buffer_len must be called before ring initialization */
3040 ixgbe_set_rx_buffer_len(adapter);
3041
3042 /*
3043 * Setup the HW Rx Head and Tail Descriptor Pointers and
3044 * the Base and Length of the Rx Descriptor Ring
3045 */
9e10e045
AD		 3046 for (i = 0; i < adapter->num_rx_queues; i++)
3047 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3048
9e10e045
AD		 3049 /* disable drop enable for 82598 parts */
3050 if (hw->mac.type == ixgbe_mac_82598EB)
3051 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3052
3053 /* enable all receives */
3054 rxctrl |= IXGBE_RXCTRL_RXEN;
3055 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3056}
3057
068c89b0
DS		 3058static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3059{
3060 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3061 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3062 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3063
3064 /* add VID to filter table */
1ada1b1b 3065 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3066 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3067}
3068
3069static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3070{
3071 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3072 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3073 int pool_ndx = adapter->num_vfs;
068c89b0 3074
068c89b0 3075 /* remove VID from filter table */
1ada1b1b 3076 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3077 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3078}
3079
5f6c0181
JB		 3080/**
3081 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3082 * @adapter: driver data
3083 */
3084static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3085{
3086 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3087 u32 vlnctrl;
3088
3089 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3090 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3091 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3092}
3093
3094/**
3095 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3096 * @adapter: driver data
3097 */
3098static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3099{
3100 struct ixgbe_hw *hw = &adapter->hw;
3101 u32 vlnctrl;
3102
3103 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3104 vlnctrl |= IXGBE_VLNCTRL_VFE;
3105 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3106 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3107}
3108
3109/**
3110 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3111 * @adapter: driver data
3112 */
3113static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3114{
3115 struct ixgbe_hw *hw = &adapter->hw;
3116 u32 vlnctrl;
5f6c0181
JB		 3117 int i, j;
3118
3119 switch (hw->mac.type) {
3120 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3121 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3122 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3123 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3124 break;
3125 case ixgbe_mac_82599EB:
5f6c0181
JB		 3126 for (i = 0; i < adapter->num_rx_queues; i++) {
3127 j = adapter->rx_ring[i]->reg_idx;
3128 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3129 vlnctrl &= ~IXGBE_RXDCTL_VME;
3130 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3131 }
3132 break;
3133 default:
3134 break;
3135 }
3136}
3137
3138/**
f62bbb5e 3139 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3140 * @adapter: driver data
3141 */
f62bbb5e 3142static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3143{
3144 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3145 u32 vlnctrl;
5f6c0181
JB		 3146 int i, j;
3147
3148 switch (hw->mac.type) {
3149 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3150 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3151 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3152 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3153 break;
3154 case ixgbe_mac_82599EB:
5f6c0181
JB		 3155 for (i = 0; i < adapter->num_rx_queues; i++) {
3156 j = adapter->rx_ring[i]->reg_idx;
3157 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3158 vlnctrl |= IXGBE_RXDCTL_VME;
3159 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3160 }
3161 break;
3162 default:
3163 break;
3164 }
3165}
3166
9a799d71
AK		 3167static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3168{
f62bbb5e 3169 u16 vid;
9a799d71 3170
f62bbb5e
JG		 3171 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3172
3173 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3174 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3175}
3176
2850062a
AD		 3177/**
3178 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3179 * @netdev: network interface device structure
3180 *
3181 * Writes unicast address list to the RAR table.
3182 * Returns: -ENOMEM on failure/insufficient address space
3183 * 0 on no addresses written
3184 * X on writing X addresses to the RAR table
3185 **/
3186static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3187{
3188 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3189 struct ixgbe_hw *hw = &adapter->hw;
3190 unsigned int vfn = adapter->num_vfs;
3191 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3192 int count = 0;
3193
3194 /* return ENOMEM indicating insufficient memory for addresses */
3195 if (netdev_uc_count(netdev) > rar_entries)
3196 return -ENOMEM;
3197
3198 if (!netdev_uc_empty(netdev) && rar_entries) {
3199 struct netdev_hw_addr *ha;
3200 /* return error if we do not support writing to RAR table */
3201 if (!hw->mac.ops.set_rar)
3202 return -ENOMEM;
3203
3204 netdev_for_each_uc_addr(ha, netdev) {
3205 if (!rar_entries)
3206 break;
3207 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3208 vfn, IXGBE_RAH_AV);
3209 count++;
3210 }
3211 }
3212 /* write the addresses in reverse order to avoid write combining */
3213 for (; rar_entries > 0 ; rar_entries--)
3214 hw->mac.ops.clear_rar(hw, rar_entries);
3215
3216 return count;
3217}
3218
9a799d71 3219/**
2c5645cf 3220 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3221 * @netdev: network interface device structure
3222 *
2c5645cf
CL		 3223 * The set_rx_method entry point is called whenever the unicast/multicast
3224 * address list or the network interface flags are updated. This routine is
3225 * responsible for configuring the hardware for proper unicast, multicast and
3226 * promiscuous mode.
9a799d71 3227 **/
7f870475 3228void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3229{
3230 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3231 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3232 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3233 int count;
9a799d71
AK		 3234
3235 /* Check for Promiscuous and All Multicast modes */
3236
3237 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3238
f5dc442b
AD		 3239 /* set all bits that we expect to always be set */
3240 fctrl |= IXGBE_FCTRL_BAM;
3241 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3242 fctrl |= IXGBE_FCTRL_PMCF;
3243
2850062a
AD		 3244 /* clear the bits we are changing the status of */
3245 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3246
9a799d71 3247 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3248 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3249 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3250 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3251 /* don't hardware filter vlans in promisc mode */
3252 ixgbe_vlan_filter_disable(adapter);
9a799d71 3253 } else {
746b9f02
PM		 3254 if (netdev->flags & IFF_ALLMULTI) {
3255 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3256 vmolr |= IXGBE_VMOLR_MPE;
3257 } else {
3258 /*
3259 * Write addresses to the MTA, if the attempt fails
3260 * then we should just turn on promiscous mode so
3261 * that we can at least receive multicast traffic
3262 */
3263 hw->mac.ops.update_mc_addr_list(hw, netdev);
3264 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3265 }
5f6c0181 3266 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3267 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3268 /*
3269 * Write addresses to available RAR registers, if there is not
3270 * sufficient space to store all the addresses then enable
3271 * unicast promiscous mode
3272 */
3273 count = ixgbe_write_uc_addr_list(netdev);
3274 if (count < 0) {
3275 fctrl |= IXGBE_FCTRL_UPE;
3276 vmolr |= IXGBE_VMOLR_ROPE;
3277 }
9a799d71
AK		 3278 }
3279
2850062a 3280 if (adapter->num_vfs) {
1cdd1ec8 3281 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3282 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3283 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3284 IXGBE_VMOLR_ROPE);
3285 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3286 }
3287
3288 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3289
3290 if (netdev->features & NETIF_F_HW_VLAN_RX)
3291 ixgbe_vlan_strip_enable(adapter);
3292 else
3293 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3294}
3295
021230d4
AV		 3296static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3297{
3298 int q_idx;
3299 struct ixgbe_q_vector *q_vector;
3300 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3301
3302 /* legacy and MSI only use one vector */
3303 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3304 q_vectors = 1;
3305
3306 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3307 struct napi_struct *napi;
7a921c93 3308 q_vector = adapter->q_vector[q_idx];
f0848276 3309 napi = &q_vector->napi;
91281fd3
AD		 3310 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3311 if (!q_vector->rxr_count || !q_vector->txr_count) {
3312 if (q_vector->txr_count == 1)
3313 napi->poll = &ixgbe_clean_txonly;
3314 else if (q_vector->rxr_count == 1)
3315 napi->poll = &ixgbe_clean_rxonly;
3316 }
3317 }
f0848276
JB		 3318
3319 napi_enable(napi);
021230d4
AV		 3320 }
3321}
3322
3323static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3324{
3325 int q_idx;
3326 struct ixgbe_q_vector *q_vector;
3327 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3328
3329 /* legacy and MSI only use one vector */
3330 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3331 q_vectors = 1;
3332
3333 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3334 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3335 napi_disable(&q_vector->napi);
3336 }
3337}
3338
7a6b6f51 3339#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3340/*
3341 * ixgbe_configure_dcb - Configure DCB hardware
3342 * @adapter: ixgbe adapter struct
3343 *
3344 * This is called by the driver on open to configure the DCB hardware.
3345 * This is also called by the gennetlink interface when reconfiguring
3346 * the DCB state.
3347 */
3348static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3349{
3350 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3351 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
5f6c0181 3352 u32 txdctl;
2f90b865
AD		 3353 int i, j;
3354
67ebd791
AD		 3355 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3356 if (hw->mac.type == ixgbe_mac_82598EB)
3357 netif_set_gso_max_size(adapter->netdev, 65536);
3358 return;
3359 }
3360
3361 if (hw->mac.type == ixgbe_mac_82598EB)
3362 netif_set_gso_max_size(adapter->netdev, 32768);
3363
9806307a
JF		 3364#ifdef CONFIG_FCOE
3365 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3366 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3367#endif
3368
80ab193d 3369 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3370 DCB_TX_CONFIG);
80ab193d 3371 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
9806307a 3372 DCB_RX_CONFIG);
2f90b865
AD		 3373
3374 /* reconfigure the hardware */
3375 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3376
3377 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3378 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3379 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3380 /* PThresh workaround for Tx hang with DFP enabled. */
3381 txdctl |= 32;
3382 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3383 }
3384 /* Enable VLAN tag insert/strip */
f62bbb5e 3385 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3386
2f90b865
AD		 3387 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3388}
3389
3390#endif
9a799d71
AK		 3391static void ixgbe_configure(struct ixgbe_adapter *adapter)
3392{
3393 struct net_device *netdev = adapter->netdev;
c4cf55e5 3394 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3395 int i;
3396
7a6b6f51 3397#ifdef CONFIG_IXGBE_DCB
67ebd791 3398 ixgbe_configure_dcb(adapter);
2f90b865 3399#endif
9a799d71 3400
f62bbb5e
JG		 3401 ixgbe_set_rx_mode(netdev);
3402 ixgbe_restore_vlan(adapter);
3403
eacd73f7
YZ		 3404#ifdef IXGBE_FCOE
3405 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3406 ixgbe_configure_fcoe(adapter);
3407
3408#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3409 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3410 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3411 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3412 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3413 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3414 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3415 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3416 }
933d41f1 3417 ixgbe_configure_virtualization(adapter);
c4cf55e5 3418
9a799d71
AK		 3419 ixgbe_configure_tx(adapter);
3420 ixgbe_configure_rx(adapter);
9a799d71
AK		 3421}
3422
e8e26350
PW		 3423static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3424{
3425 switch (hw->phy.type) {
3426 case ixgbe_phy_sfp_avago:
3427 case ixgbe_phy_sfp_ftl:
3428 case ixgbe_phy_sfp_intel:
3429 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3430 case ixgbe_phy_sfp_passive_tyco:
3431 case ixgbe_phy_sfp_passive_unknown:
3432 case ixgbe_phy_sfp_active_unknown:
3433 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3434 return true;
3435 default:
3436 return false;
3437 }
3438}
3439
0ecc061d 3440/**
e8e26350
PW		 3441 * ixgbe_sfp_link_config - set up SFP+ link
3442 * @adapter: pointer to private adapter struct
3443 **/
3444static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3445{
3446 struct ixgbe_hw *hw = &adapter->hw;
3447
3448 if (hw->phy.multispeed_fiber) {
3449 /*
3450 * In multispeed fiber setups, the device may not have
3451 * had a physical connection when the driver loaded.
3452 * If that's the case, the initial link configuration
3453 * couldn't get the MAC into 10G or 1G mode, so we'll
3454 * never have a link status change interrupt fire.
3455 * We need to try and force an autonegotiation
3456 * session, then bring up link.
3457 */
3458 hw->mac.ops.setup_sfp(hw);
3459 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3460 schedule_work(&adapter->multispeed_fiber_task);
3461 } else {
3462 /*
3463 * Direct Attach Cu and non-multispeed fiber modules
3464 * still need to be configured properly prior to
3465 * attempting link.
3466 */
3467 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3468 schedule_work(&adapter->sfp_config_module_task);
3469 }
3470}
3471
3472/**
3473 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3474 * @hw: pointer to private hardware struct
3475 *
3476 * Returns 0 on success, negative on failure
3477 **/
e8e26350 3478static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3479{
3480 u32 autoneg;
8620a103 3481 bool negotiation, link_up = false;
0ecc061d
PWJ		 3482 u32 ret = IXGBE_ERR_LINK_SETUP;
3483
3484 if (hw->mac.ops.check_link)
3485 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3486
3487 if (ret)
3488 goto link_cfg_out;
3489
3490 if (hw->mac.ops.get_link_capabilities)
e8e9f696
JP		 3491 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3492 &negotiation);
0ecc061d
PWJ		 3493 if (ret)
3494 goto link_cfg_out;
3495
8620a103
MC		 3496 if (hw->mac.ops.setup_link)
3497 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3498link_cfg_out:
3499 return ret;
3500}
3501
a34bcfff 3502static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3503{
9a799d71 3504 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3505 u32 gpie = 0;
9a799d71 3506
9b471446 3507 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3508 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3509 IXGBE_GPIE_OCD;
3510 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3511 /*
3512 * use EIAM to auto-mask when MSI-X interrupt is asserted
3513 * this saves a register write for every interrupt
3514 */
3515 switch (hw->mac.type) {
3516 case ixgbe_mac_82598EB:
3517 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3518 break;
3519 default:
3520 case ixgbe_mac_82599EB:
3521 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3522 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3523 break;
3524 }
3525 } else {
021230d4
AV		 3526 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3527 * specifically only auto mask tx and rx interrupts */
3528 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3529 }
9a799d71 3530
a34bcfff
AD		 3531 /* XXX: to interrupt immediately for EICS writes, enable this */
3532 /* gpie |= IXGBE_GPIE_EIMEN; */
3533
3534 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3535 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3536 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3537 }
3538
a34bcfff
AD		 3539 /* Enable fan failure interrupt */
3540 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3541 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3542
a34bcfff 3543 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3544 gpie |= IXGBE_SDP1_GPIEN;
3545 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3546
3547 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3548}
3549
3550static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3551{
3552 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3553 int err;
a34bcfff
AD		 3554 u32 ctrl_ext;
3555
3556 ixgbe_get_hw_control(adapter);
3557 ixgbe_setup_gpie(adapter);
e8e26350 3558
9a799d71
AK		 3559 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3560 ixgbe_configure_msix(adapter);
3561 else
3562 ixgbe_configure_msi_and_legacy(adapter);
3563
61fac744
PW		 3564 /* enable the optics */
3565 if (hw->phy.multispeed_fiber)
3566 hw->mac.ops.enable_tx_laser(hw);
3567
9a799d71 3568 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3569 ixgbe_napi_enable_all(adapter);
3570
3571 /* clear any pending interrupts, may auto mask */
3572 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3573 ixgbe_irq_enable(adapter, true, true);
9a799d71 3574
bf069c97
DS		 3575 /*
3576 * If this adapter has a fan, check to see if we had a failure
3577 * before we enabled the interrupt.
3578 */
3579 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3580 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3581 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3582 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3583 }
3584
e8e26350
PW		 3585 /*
3586 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3587 * arrived before interrupts were enabled but after probe. Such
3588 * devices wouldn't have their type identified yet. We need to
3589 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3590 * If we're not hot-pluggable SFP+, we just need to configure link
3591 * and bring it up.
3592 */
19343de2
DS		 3593 if (hw->phy.type == ixgbe_phy_unknown) {
3594 err = hw->phy.ops.identify(hw);
3595 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3596 /*
3597 * Take the device down and schedule the sfp tasklet
3598 * which will unregister_netdev and log it.
3599 */
19343de2 3600 ixgbe_down(adapter);
5da43c1a 3601 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3602 return err;
3603 }
e8e26350
PW		 3604 }
3605
3606 if (ixgbe_is_sfp(hw)) {
3607 ixgbe_sfp_link_config(adapter);
3608 } else {
3609 err = ixgbe_non_sfp_link_config(hw);
3610 if (err)
396e799c 3611 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3612 }
0ecc061d 3613
1da100bb 3614 /* enable transmits */
477de6ed 3615 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3616
9a799d71
AK		 3617 /* bring the link up in the watchdog, this could race with our first
3618 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3619 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3620 adapter->link_check_timeout = jiffies;
9a799d71 3621 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3622
3623 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3624 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3625 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3626 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3627
9a799d71
AK		 3628 return 0;
3629}
3630
d4f80882
AV		 3631void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3632{
3633 WARN_ON(in_interrupt());
3634 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3635 msleep(1);
3636 ixgbe_down(adapter);
5809a1ae
GR		 3637 /*
3638 * If SR-IOV enabled then wait a bit before bringing the adapter
3639 * back up to give the VFs time to respond to the reset. The
3640 * two second wait is based upon the watchdog timer cycle in
3641 * the VF driver.
3642 */
3643 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3644 msleep(2000);
d4f80882
AV		 3645 ixgbe_up(adapter);
3646 clear_bit(__IXGBE_RESETTING, &adapter->state);
3647}
3648
9a799d71
AK		 3649int ixgbe_up(struct ixgbe_adapter *adapter)
3650{
3651 /* hardware has been reset, we need to reload some things */
3652 ixgbe_configure(adapter);
3653
3654 return ixgbe_up_complete(adapter);
3655}
3656
3657void ixgbe_reset(struct ixgbe_adapter *adapter)
3658{
c44ade9e 3659 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3660 int err;
3661
3662 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3663 switch (err) {
3664 case 0:
3665 case IXGBE_ERR_SFP_NOT_PRESENT:
3666 break;
3667 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3668 e_dev_err("master disable timed out\n");
da4dd0f7 3669 break;
794caeb2
PWJ		 3670 case IXGBE_ERR_EEPROM_VERSION:
3671 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3672 e_dev_warn("This device is a pre-production adapter/LOM. "
3673 "Please be aware there may be issuesassociated with "
3674 "your hardware. If you are experiencing problems "
3675 "please contact your Intel or hardware "
3676 "representative who provided you with this "
3677 "hardware.\n");
794caeb2 3678 break;
da4dd0f7 3679 default:
849c4542 3680 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3681 }
9a799d71
AK		 3682
3683 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3684 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3685 IXGBE_RAH_AV);
9a799d71
AK		 3686}
3687
9a799d71
AK		 3688/**
3689 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3690 * @adapter: board private structure
3691 * @rx_ring: ring to free buffers from
3692 **/
3693static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
e8e9f696 3694 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3695{
3696 struct pci_dev *pdev = adapter->pdev;
3697 unsigned long size;
3698 unsigned int i;
3699
84418e3b
AD		 3700 /* ring already cleared, nothing to do */
3701 if (!rx_ring->rx_buffer_info)
3702 return;
9a799d71 3703
84418e3b 3704 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3705 for (i = 0; i < rx_ring->count; i++) {
3706 struct ixgbe_rx_buffer *rx_buffer_info;
3707
3708 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3709 if (rx_buffer_info->dma) {
1b507730 3710 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
e8e9f696 3711 rx_ring->rx_buf_len,
1b507730 3712 DMA_FROM_DEVICE);
9a799d71
AK		 3713 rx_buffer_info->dma = 0;
3714 }
3715 if (rx_buffer_info->skb) {
f8212f97 3716 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3717 rx_buffer_info->skb = NULL;
f8212f97
AD		 3718 do {
3719 struct sk_buff *this = skb;
e8171aaa 3720 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3721 dma_unmap_single(&pdev->dev,
3722 IXGBE_RSC_CB(this)->dma,
e8e9f696 3723 rx_ring->rx_buf_len,
1b507730 3724 DMA_FROM_DEVICE);
fd3686a8 3725 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3726 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3727 }
f8212f97
AD		 3728 skb = skb->prev;
3729 dev_kfree_skb(this);
3730 } while (skb);
9a799d71
AK		 3731 }
3732 if (!rx_buffer_info->page)
3733 continue;
4f57ca6e 3734 if (rx_buffer_info->page_dma) {
1b507730
NN		 3735 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3736 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3737 rx_buffer_info->page_dma = 0;
3738 }
9a799d71
AK		 3739 put_page(rx_buffer_info->page);
3740 rx_buffer_info->page = NULL;
762f4c57 3741 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3742 }
3743
3744 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3745 memset(rx_ring->rx_buffer_info, 0, size);
3746
3747 /* Zero out the descriptor ring */
3748 memset(rx_ring->desc, 0, rx_ring->size);
3749
3750 rx_ring->next_to_clean = 0;
3751 rx_ring->next_to_use = 0;
3752
9891ca7c
JB		 3753 if (rx_ring->head)
3754 writel(0, adapter->hw.hw_addr + rx_ring->head);
3755 if (rx_ring->tail)
3756 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3757}
3758
3759/**
3760 * ixgbe_clean_tx_ring - Free Tx Buffers
3761 * @adapter: board private structure
3762 * @tx_ring: ring to be cleaned
3763 **/
3764static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
e8e9f696 3765 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3766{
3767 struct ixgbe_tx_buffer *tx_buffer_info;
3768 unsigned long size;
3769 unsigned int i;
3770
84418e3b
AD		 3771 /* ring already cleared, nothing to do */
3772 if (!tx_ring->tx_buffer_info)
3773 return;
9a799d71 3774
84418e3b 3775 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3776 for (i = 0; i < tx_ring->count; i++) {
3777 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3778 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3779 }
3780
3781 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3782 memset(tx_ring->tx_buffer_info, 0, size);
3783
3784 /* Zero out the descriptor ring */
3785 memset(tx_ring->desc, 0, tx_ring->size);
3786
3787 tx_ring->next_to_use = 0;
3788 tx_ring->next_to_clean = 0;
3789
9891ca7c
JB		 3790 if (tx_ring->head)
3791 writel(0, adapter->hw.hw_addr + tx_ring->head);
3792 if (tx_ring->tail)
3793 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3794}
3795
3796/**
021230d4 3797 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3798 * @adapter: board private structure
3799 **/
021230d4 3800static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3801{
3802 int i;
3803
021230d4 3804 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3805 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3806}
3807
3808/**
021230d4 3809 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3810 * @adapter: board private structure
3811 **/
021230d4 3812static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3813{
3814 int i;
3815
021230d4 3816 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3817 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3818}
3819
3820void ixgbe_down(struct ixgbe_adapter *adapter)
3821{
3822 struct net_device *netdev = adapter->netdev;
7f821875 3823 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3824 u32 rxctrl;
7f821875
JB		 3825 u32 txdctl;
3826 int i, j;
b25ebfd2 3827 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 3828
3829 /* signal that we are down to the interrupt handler */
3830 set_bit(__IXGBE_DOWN, &adapter->state);
3831
767081ad
GR		 3832 /* disable receive for all VFs and wait one second */
3833 if (adapter->num_vfs) {
767081ad
GR		 3834 /* ping all the active vfs to let them know we are going down */
3835 ixgbe_ping_all_vfs(adapter);
581d1aa7 3836
767081ad
GR		 3837 /* Disable all VFTE/VFRE TX/RX */
3838 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3839
3840 /* Mark all the VFs as inactive */
3841 for (i = 0 ; i < adapter->num_vfs; i++)
3842 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3843 }
3844
9a799d71 3845 /* disable receives */
7f821875
JB		 3846 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3847 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3848
7f821875 3849 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3850 msleep(10);
3851
7f821875
JB		 3852 netif_tx_stop_all_queues(netdev);
3853
0a1f87cb
DS		 3854 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3855 del_timer_sync(&adapter->sfp_timer);
9a799d71 3856 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3857 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3858
c0dfb90e
JF		 3859 netif_carrier_off(netdev);
3860 netif_tx_disable(netdev);
3861
3862 ixgbe_irq_disable(adapter);
3863
3864 ixgbe_napi_disable_all(adapter);
3865
b25ebfd2
PW		 3866 /* Cleanup the affinity_hint CPU mask memory and callback */
3867 for (i = 0; i < num_q_vectors; i++) {
3868 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3869 /* clear the affinity_mask in the IRQ descriptor */
3870 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3871 /* release the CPU mask memory */
3872 free_cpumask_var(q_vector->affinity_mask);
3873 }
3874
c4cf55e5
PWJ		 3875 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3876 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3877 cancel_work_sync(&adapter->fdir_reinit_task);
3878
119fc60a
MC		 3879 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3880 cancel_work_sync(&adapter->check_overtemp_task);
3881
7f821875
JB		 3882 /* disable transmits in the hardware now that interrupts are off */
3883 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3884 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3885 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3886 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
e8e9f696 3887 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 3888 }
88512539
PW		 3889 /* Disable the Tx DMA engine on 82599 */
3890 if (hw->mac.type == ixgbe_mac_82599EB)
3891 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 3892 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3893 ~IXGBE_DMATXCTL_TE));
7f821875 3894
9f756f01
JF		 3895 /* power down the optics */
3896 if (hw->phy.multispeed_fiber)
3897 hw->mac.ops.disable_tx_laser(hw);
3898
9a713e7c
PW		 3899 /* clear n-tuple filters that are cached */
3900 ethtool_ntuple_flush(netdev);
3901
6f4a0e45
PL		 3902 if (!pci_channel_offline(adapter->pdev))
3903 ixgbe_reset(adapter);
9a799d71
AK		 3904 ixgbe_clean_all_tx_rings(adapter);
3905 ixgbe_clean_all_rx_rings(adapter);
3906
5dd2d332 3907#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3908 /* since we reset the hardware DCA settings were cleared */
e35ec126 3909 ixgbe_setup_dca(adapter);
96b0e0f6 3910#endif
9a799d71
AK		 3911}
3912
9a799d71 3913/**
021230d4
AV		 3914 * ixgbe_poll - NAPI Rx polling callback
3915 * @napi: structure for representing this polling device
3916 * @budget: how many packets driver is allowed to clean
3917 *
3918 * This function is used for legacy and MSI, NAPI mode
9a799d71 3919 **/
021230d4 3920static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3921{
9a1a69ad 3922 struct ixgbe_q_vector *q_vector =
e8e9f696 3923 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3924 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3925 int tx_clean_complete, work_done = 0;
9a799d71 3926
5dd2d332 3927#ifdef CONFIG_IXGBE_DCA
bd0362dd 3928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3929 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3930 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3931 }
3932#endif
3933
4a0b9ca0
PW		 3934 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3935 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3936
9a1a69ad 3937 if (!tx_clean_complete)
d2c7ddd6
DM		 3938 work_done = budget;
3939
53e52c72
DM		 3940 /* If budget not fully consumed, exit the polling mode */
3941 if (work_done < budget) {
288379f0 3942 napi_complete(napi);
f7554a2b 3943 if (adapter->rx_itr_setting & 1)
f494e8fa 3944 ixgbe_set_itr(adapter);
d4f80882 3945 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3946 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3947 }
9a799d71
AK		 3948 return work_done;
3949}
3950
3951/**
3952 * ixgbe_tx_timeout - Respond to a Tx Hang
3953 * @netdev: network interface device structure
3954 **/
3955static void ixgbe_tx_timeout(struct net_device *netdev)
3956{
3957 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3958
3959 /* Do the reset outside of interrupt context */
3960 schedule_work(&adapter->reset_task);
3961}
3962
3963static void ixgbe_reset_task(struct work_struct *work)
3964{
3965 struct ixgbe_adapter *adapter;
3966 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3967
2f90b865
AD		 3968 /* If we're already down or resetting, just bail */
3969 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3970 test_bit(__IXGBE_RESETTING, &adapter->state))
3971 return;
3972
9a799d71
AK		 3973 adapter->tx_timeout_count++;
3974
dcd79aeb
TI		 3975 ixgbe_dump(adapter);
3976 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3977 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3978}
3979
bc97114d
PWJ		 3980#ifdef CONFIG_IXGBE_DCB
3981static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3982{
bc97114d 3983 bool ret = false;
0cefafad 3984 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3985
0cefafad
JB		 3986 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3987 return ret;
3988
3989 f->mask = 0x7 << 3;
3990 adapter->num_rx_queues = f->indices;
3991 adapter->num_tx_queues = f->indices;
3992 ret = true;
2f90b865 3993
bc97114d
PWJ		 3994 return ret;
3995}
3996#endif
3997
4df10466
JB		 3998/**
3999 * ixgbe_set_rss_queues: Allocate queues for RSS
4000 * @adapter: board private structure to initialize
4001 *
4002 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4003 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4004 *
4005 **/
bc97114d
PWJ		 4006static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4007{
4008 bool ret = false;
0cefafad 4009 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4010
4011 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4012 f->mask = 0xF;
4013 adapter->num_rx_queues = f->indices;
4014 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4015 ret = true;
4016 } else {
bc97114d 4017 ret = false;
b9804972
JB		 4018 }
4019
bc97114d
PWJ		 4020 return ret;
4021}
4022
c4cf55e5
PWJ		 4023/**
4024 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4025 * @adapter: board private structure to initialize
4026 *
4027 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4028 * to the original CPU that initiated the Tx session. This runs in addition
4029 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4030 * Rx load across CPUs using RSS.
4031 *
4032 **/
e8e9f696 4033static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4034{
4035 bool ret = false;
4036 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4037
4038 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4039 f_fdir->mask = 0;
4040
4041 /* Flow Director must have RSS enabled */
4042 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4043 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4044 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4045 adapter->num_tx_queues = f_fdir->indices;
4046 adapter->num_rx_queues = f_fdir->indices;
4047 ret = true;
4048 } else {
4049 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4050 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4051 }
4052 return ret;
4053}
4054
0331a832
YZ		 4055#ifdef IXGBE_FCOE
4056/**
4057 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4058 * @adapter: board private structure to initialize
4059 *
4060 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4061 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4062 * rx queues out of the max number of rx queues, instead, it is used as the
4063 * index of the first rx queue used by FCoE.
4064 *
4065 **/
4066static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4067{
4068 bool ret = false;
4069 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4070
4071 f->indices = min((int)num_online_cpus(), f->indices);
4072 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 4073 adapter->num_rx_queues = 1;
4074 adapter->num_tx_queues = 1;
0331a832
YZ		 4075#ifdef CONFIG_IXGBE_DCB
4076 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 4077 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 4078 ixgbe_set_dcb_queues(adapter);
4079 }
4080#endif
4081 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4082 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4083 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4084 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4085 ixgbe_set_fdir_queues(adapter);
4086 else
4087 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4088 }
4089 /* adding FCoE rx rings to the end */
4090 f->mask = adapter->num_rx_queues;
4091 adapter->num_rx_queues += f->indices;
8de8b2e6 4092 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4093
4094 ret = true;
4095 }
4096
4097 return ret;
4098}
4099
4100#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4101/**
4102 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4103 * @adapter: board private structure to initialize
4104 *
4105 * IOV doesn't actually use anything, so just NAK the
4106 * request for now and let the other queue routines
4107 * figure out what to do.
4108 */
4109static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4110{
4111 return false;
4112}
4113
4df10466
JB		 4114/*
4115 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4116 * @adapter: board private structure to initialize
4117 *
4118 * This is the top level queue allocation routine. The order here is very
4119 * important, starting with the "most" number of features turned on at once,
4120 * and ending with the smallest set of features. This way large combinations
4121 * can be allocated if they're turned on, and smaller combinations are the
4122 * fallthrough conditions.
4123 *
4124 **/
847f53ff 4125static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4126{
1cdd1ec8
GR		 4127 /* Start with base case */
4128 adapter->num_rx_queues = 1;
4129 adapter->num_tx_queues = 1;
4130 adapter->num_rx_pools = adapter->num_rx_queues;
4131 adapter->num_rx_queues_per_pool = 1;
4132
4133 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4134 goto done;
1cdd1ec8 4135
0331a832
YZ		 4136#ifdef IXGBE_FCOE
4137 if (ixgbe_set_fcoe_queues(adapter))
4138 goto done;
4139
4140#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4141#ifdef CONFIG_IXGBE_DCB
4142 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4143 goto done;
bc97114d
PWJ		 4144
4145#endif
c4cf55e5
PWJ		 4146 if (ixgbe_set_fdir_queues(adapter))
4147 goto done;
4148
bc97114d 4149 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4150 goto done;
4151
4152 /* fallback to base case */
4153 adapter->num_rx_queues = 1;
4154 adapter->num_tx_queues = 1;
4155
4156done:
847f53ff 4157 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4158 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4159 return netif_set_real_num_rx_queues(adapter->netdev,
4160 adapter->num_rx_queues);
b9804972
JB		 4161}
4162
021230d4 4163static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4164 int vectors)
021230d4
AV		 4165{
4166 int err, vector_threshold;
4167
4168 /* We'll want at least 3 (vector_threshold):
4169 * 1) TxQ[0] Cleanup
4170 * 2) RxQ[0] Cleanup
4171 * 3) Other (Link Status Change, etc.)
4172 * 4) TCP Timer (optional)
4173 */
4174 vector_threshold = MIN_MSIX_COUNT;
4175
4176 /* The more we get, the more we will assign to Tx/Rx Cleanup
4177 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4178 * Right now, we simply care about how many we'll get; we'll
4179 * set them up later while requesting irq's.
4180 */
4181 while (vectors >= vector_threshold) {
4182 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4183 vectors);
021230d4
AV		 4184 if (!err) /* Success in acquiring all requested vectors. */
4185 break;
4186 else if (err < 0)
4187 vectors = 0; /* Nasty failure, quit now */
4188 else /* err == number of vectors we should try again with */
4189 vectors = err;
4190 }
4191
4192 if (vectors < vector_threshold) {
4193 /* Can't allocate enough MSI-X interrupts? Oh well.
4194 * This just means we'll go with either a single MSI
4195 * vector or fall back to legacy interrupts.
4196 */
849c4542
ET		 4197 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4198 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4199 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4200 kfree(adapter->msix_entries);
4201 adapter->msix_entries = NULL;
021230d4
AV		 4202 } else {
4203 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4204 /*
4205 * Adjust for only the vectors we'll use, which is minimum
4206 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4207 * vectors we were allocated.
4208 */
4209 adapter->num_msix_vectors = min(vectors,
e8e9f696 4210 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4211 }
4212}
4213
021230d4 4214/**
bc97114d 4215 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4216 * @adapter: board private structure to initialize
4217 *
bc97114d
PWJ		 4218 * Cache the descriptor ring offsets for RSS to the assigned rings.
4219 *
021230d4 4220 **/
bc97114d 4221static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4222{
bc97114d
PWJ		 4223 int i;
4224 bool ret = false;
4225
4226 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4227 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4228 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4229 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4230 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4231 ret = true;
4232 } else {
4233 ret = false;
4234 }
4235
4236 return ret;
4237}
4238
4239#ifdef CONFIG_IXGBE_DCB
4240/**
4241 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4242 * @adapter: board private structure to initialize
4243 *
4244 * Cache the descriptor ring offsets for DCB to the assigned rings.
4245 *
4246 **/
4247static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4248{
4249 int i;
4250 bool ret = false;
4251 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4252
4253 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4254 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4255 /* the number of queues is assumed to be symmetric */
4256 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4257 adapter->rx_ring[i]->reg_idx = i << 3;
4258 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4259 }
bc97114d 4260 ret = true;
e8e26350 4261 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4262 if (dcb_i == 8) {
4263 /*
4264 * Tx TC0 starts at: descriptor queue 0
4265 * Tx TC1 starts at: descriptor queue 32
4266 * Tx TC2 starts at: descriptor queue 64
4267 * Tx TC3 starts at: descriptor queue 80
4268 * Tx TC4 starts at: descriptor queue 96
4269 * Tx TC5 starts at: descriptor queue 104
4270 * Tx TC6 starts at: descriptor queue 112
4271 * Tx TC7 starts at: descriptor queue 120
4272 *
4273 * Rx TC0-TC7 are offset by 16 queues each
4274 */
4275 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4276 adapter->tx_ring[i]->reg_idx = i << 5;
4277 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4278 }
4279 for ( ; i < 5; i++) {
4a0b9ca0 4280 adapter->tx_ring[i]->reg_idx =
e8e9f696 4281 ((i + 2) << 4);
4a0b9ca0 4282 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4283 }
4284 for ( ; i < dcb_i; i++) {
4a0b9ca0 4285 adapter->tx_ring[i]->reg_idx =
e8e9f696 4286 ((i + 8) << 3);
4a0b9ca0 4287 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4288 }
4289
4290 ret = true;
4291 } else if (dcb_i == 4) {
4292 /*
4293 * Tx TC0 starts at: descriptor queue 0
4294 * Tx TC1 starts at: descriptor queue 64
4295 * Tx TC2 starts at: descriptor queue 96
4296 * Tx TC3 starts at: descriptor queue 112
4297 *
4298 * Rx TC0-TC3 are offset by 32 queues each
4299 */
4a0b9ca0
PW		 4300 adapter->tx_ring[0]->reg_idx = 0;
4301 adapter->tx_ring[1]->reg_idx = 64;
4302 adapter->tx_ring[2]->reg_idx = 96;
4303 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4304 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4305 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4306
4307 ret = true;
4308 } else {
4309 ret = false;
e8e26350 4310 }
bc97114d
PWJ		 4311 } else {
4312 ret = false;
021230d4 4313 }
bc97114d
PWJ		 4314 } else {
4315 ret = false;
021230d4 4316 }
bc97114d
PWJ		 4317
4318 return ret;
4319}
4320#endif
4321
c4cf55e5
PWJ		 4322/**
4323 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4324 * @adapter: board private structure to initialize
4325 *
4326 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4327 *
4328 **/
e8e9f696 4329static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4330{
4331 int i;
4332 bool ret = false;
4333
4334 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4335 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4336 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4337 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4338 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4339 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4340 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4341 ret = true;
4342 }
4343
4344 return ret;
4345}
4346
0331a832
YZ		 4347#ifdef IXGBE_FCOE
4348/**
4349 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4350 * @adapter: board private structure to initialize
4351 *
4352 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4353 *
4354 */
4355static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4356{
8de8b2e6 4357 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4358 bool ret = false;
4359 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4360
4361 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4362#ifdef CONFIG_IXGBE_DCB
4363 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4364 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4365
0331a832 4366 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4367 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4368 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4369 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4370 /*
4371 * In 82599, the number of Tx queues for each traffic
4372 * class for both 8-TC and 4-TC modes are:
4373 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4374 * 8 TCs: 32 32 16 16 8 8 8 8
4375 * 4 TCs: 64 64 32 32
4376 * We have max 8 queues for FCoE, where 8 the is
4377 * FCoE redirection table size. If TC for FCoE is
4378 * less than or equal to TC3, we have enough queues
4379 * to add max of 8 queues for FCoE, so we start FCoE
4380 * tx descriptor from the next one, i.e., reg_idx + 1.
4381 * If TC for FCoE is above TC3, implying 8 TC mode,
4382 * and we need 8 for FCoE, we have to take all queues
4383 * in that traffic class for FCoE.
4384 */
4385 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4386 fcoe_tx_i--;
0331a832
YZ		 4387 }
4388#endif /* CONFIG_IXGBE_DCB */
4389 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4390 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4391 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4392 ixgbe_cache_ring_fdir(adapter);
4393 else
4394 ixgbe_cache_ring_rss(adapter);
4395
8de8b2e6
YZ		 4396 fcoe_rx_i = f->mask;
4397 fcoe_tx_i = f->mask;
4398 }
4399 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4400 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4401 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4402 }
0331a832
YZ		 4403 ret = true;
4404 }
4405 return ret;
4406}
4407
4408#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4409/**
4410 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4411 * @adapter: board private structure to initialize
4412 *
4413 * SR-IOV doesn't use any descriptor rings but changes the default if
4414 * no other mapping is used.
4415 *
4416 */
4417static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4418{
4a0b9ca0
PW		 4419 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4420 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4421 if (adapter->num_vfs)
4422 return true;
4423 else
4424 return false;
4425}
4426
bc97114d
PWJ		 4427/**
4428 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4429 * @adapter: board private structure to initialize
4430 *
4431 * Once we know the feature-set enabled for the device, we'll cache
4432 * the register offset the descriptor ring is assigned to.
4433 *
4434 * Note, the order the various feature calls is important. It must start with
4435 * the "most" features enabled at the same time, then trickle down to the
4436 * least amount of features turned on at once.
4437 **/
4438static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4439{
4440 /* start with default case */
4a0b9ca0
PW		 4441 adapter->rx_ring[0]->reg_idx = 0;
4442 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4443
1cdd1ec8
GR		 4444 if (ixgbe_cache_ring_sriov(adapter))
4445 return;
4446
0331a832
YZ		 4447#ifdef IXGBE_FCOE
4448 if (ixgbe_cache_ring_fcoe(adapter))
4449 return;
4450
4451#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4452#ifdef CONFIG_IXGBE_DCB
4453 if (ixgbe_cache_ring_dcb(adapter))
4454 return;
4455
4456#endif
c4cf55e5
PWJ		 4457 if (ixgbe_cache_ring_fdir(adapter))
4458 return;
4459
bc97114d
PWJ		 4460 if (ixgbe_cache_ring_rss(adapter))
4461 return;
021230d4
AV		 4462}
4463
9a799d71
AK		 4464/**
4465 * ixgbe_alloc_queues - Allocate memory for all rings
4466 * @adapter: board private structure to initialize
4467 *
4468 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4469 * number of queues at compile-time. The polling_netdev array is
4470 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4471 **/
2f90b865 4472static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4473{
4474 int i;
4a0b9ca0 4475 int orig_node = adapter->node;
9a799d71 4476
021230d4 4477 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4478 struct ixgbe_ring *ring = adapter->tx_ring[i];
4479 if (orig_node == -1) {
4480 int cur_node = next_online_node(adapter->node);
4481 if (cur_node == MAX_NUMNODES)
4482 cur_node = first_online_node;
4483 adapter->node = cur_node;
4484 }
4485 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4486 adapter->node);
4a0b9ca0
PW		 4487 if (!ring)
4488 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4489 if (!ring)
4490 goto err_tx_ring_allocation;
4491 ring->count = adapter->tx_ring_count;
4492 ring->queue_index = i;
4493 ring->numa_node = adapter->node;
4494
4495 adapter->tx_ring[i] = ring;
021230d4 4496 }
b9804972 4497
4a0b9ca0
PW		 4498 /* Restore the adapter's original node */
4499 adapter->node = orig_node;
4500
9a799d71 4501 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4502 struct ixgbe_ring *ring = adapter->rx_ring[i];
4503 if (orig_node == -1) {
4504 int cur_node = next_online_node(adapter->node);
4505 if (cur_node == MAX_NUMNODES)
4506 cur_node = first_online_node;
4507 adapter->node = cur_node;
4508 }
4509 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4510 adapter->node);
4a0b9ca0
PW		 4511 if (!ring)
4512 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4513 if (!ring)
4514 goto err_rx_ring_allocation;
4515 ring->count = adapter->rx_ring_count;
4516 ring->queue_index = i;
4517 ring->numa_node = adapter->node;
4518
4519 adapter->rx_ring[i] = ring;
021230d4
AV		 4520 }
4521
4a0b9ca0
PW		 4522 /* Restore the adapter's original node */
4523 adapter->node = orig_node;
4524
021230d4
AV		 4525 ixgbe_cache_ring_register(adapter);
4526
4527 return 0;
4528
4529err_rx_ring_allocation:
4a0b9ca0
PW		 4530 for (i = 0; i < adapter->num_tx_queues; i++)
4531 kfree(adapter->tx_ring[i]);
021230d4
AV		 4532err_tx_ring_allocation:
4533 return -ENOMEM;
4534}
4535
4536/**
4537 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4538 * @adapter: board private structure to initialize
4539 *
4540 * Attempt to configure the interrupts using the best available
4541 * capabilities of the hardware and the kernel.
4542 **/
feea6a57 4543static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4544{
8be0e467 4545 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4546 int err = 0;
4547 int vector, v_budget;
4548
4549 /*
4550 * It's easy to be greedy for MSI-X vectors, but it really
4551 * doesn't do us much good if we have a lot more vectors
4552 * than CPU's. So let's be conservative and only ask for
342bde1b 4553 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4554 */
4555 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4556 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4557
4558 /*
4559 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4560 * hw.mac->max_msix_vectors vectors. With features
4561 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4562 * descriptor queues supported by our device. Thus, we cap it off in
4563 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4564 */
8be0e467 4565 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4566
4567 /* A failure in MSI-X entry allocation isn't fatal, but it does
4568 * mean we disable MSI-X capabilities of the adapter. */
4569 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4570 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4571 if (adapter->msix_entries) {
4572 for (vector = 0; vector < v_budget; vector++)
4573 adapter->msix_entries[vector].entry = vector;
021230d4 4574
7a921c93 4575 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4576
7a921c93
AD		 4577 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4578 goto out;
4579 }
26d27844 4580
7a921c93
AD		 4581 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4582 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4583 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4584 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4585 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4586 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4587 ixgbe_disable_sriov(adapter);
4588
847f53ff
BH		 4589 err = ixgbe_set_num_queues(adapter);
4590 if (err)
4591 return err;
021230d4 4592
021230d4
AV		 4593 err = pci_enable_msi(adapter->pdev);
4594 if (!err) {
4595 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4596 } else {
849c4542
ET		 4597 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4598 "Unable to allocate MSI interrupt, "
4599 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4600 /* reset err */
4601 err = 0;
4602 }
4603
4604out:
021230d4
AV		 4605 return err;
4606}
4607
7a921c93
AD		 4608/**
4609 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4610 * @adapter: board private structure to initialize
4611 *
4612 * We allocate one q_vector per queue interrupt. If allocation fails we
4613 * return -ENOMEM.
4614 **/
4615static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4616{
4617 int q_idx, num_q_vectors;
4618 struct ixgbe_q_vector *q_vector;
4619 int napi_vectors;
4620 int (*poll)(struct napi_struct *, int);
4621
4622 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4623 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4624 napi_vectors = adapter->num_rx_queues;
91281fd3 4625 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4626 } else {
4627 num_q_vectors = 1;
4628 napi_vectors = 1;
4629 poll = &ixgbe_poll;
4630 }
4631
4632 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4633 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4634 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4635 if (!q_vector)
4636 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4637 GFP_KERNEL);
7a921c93
AD		 4638 if (!q_vector)
4639 goto err_out;
4640 q_vector->adapter = adapter;
f7554a2b
NS		 4641 if (q_vector->txr_count && !q_vector->rxr_count)
4642 q_vector->eitr = adapter->tx_eitr_param;
4643 else
4644 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4645 q_vector->v_idx = q_idx;
91281fd3 4646 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4647 adapter->q_vector[q_idx] = q_vector;
4648 }
4649
4650 return 0;
4651
4652err_out:
4653 while (q_idx) {
4654 q_idx--;
4655 q_vector = adapter->q_vector[q_idx];
4656 netif_napi_del(&q_vector->napi);
4657 kfree(q_vector);
4658 adapter->q_vector[q_idx] = NULL;
4659 }
4660 return -ENOMEM;
4661}
4662
4663/**
4664 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4665 * @adapter: board private structure to initialize
4666 *
4667 * This function frees the memory allocated to the q_vectors. In addition if
4668 * NAPI is enabled it will delete any references to the NAPI struct prior
4669 * to freeing the q_vector.
4670 **/
4671static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4672{
4673 int q_idx, num_q_vectors;
7a921c93 4674
91281fd3 4675 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4676 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4677 else
7a921c93 4678 num_q_vectors = 1;
7a921c93
AD		 4679
4680 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4681 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4682 adapter->q_vector[q_idx] = NULL;
91281fd3 4683 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4684 kfree(q_vector);
4685 }
4686}
4687
7b25cdba 4688static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4689{
4690 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4691 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4692 pci_disable_msix(adapter->pdev);
4693 kfree(adapter->msix_entries);
4694 adapter->msix_entries = NULL;
4695 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4696 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4697 pci_disable_msi(adapter->pdev);
4698 }
021230d4
AV		 4699}
4700
4701/**
4702 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4703 * @adapter: board private structure to initialize
4704 *
4705 * We determine which interrupt scheme to use based on...
4706 * - Kernel support (MSI, MSI-X)
4707 * - which can be user-defined (via MODULE_PARAM)
4708 * - Hardware queue count (num_*_queues)
4709 * - defined by miscellaneous hardware support/features (RSS, etc.)
4710 **/
2f90b865 4711int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4712{
4713 int err;
4714
4715 /* Number of supported queues */
847f53ff
BH		 4716 err = ixgbe_set_num_queues(adapter);
4717 if (err)
4718 return err;
021230d4 4719
021230d4
AV		 4720 err = ixgbe_set_interrupt_capability(adapter);
4721 if (err) {
849c4542 4722 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4723 goto err_set_interrupt;
9a799d71
AK		 4724 }
4725
7a921c93
AD		 4726 err = ixgbe_alloc_q_vectors(adapter);
4727 if (err) {
849c4542 4728 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4729 goto err_alloc_q_vectors;
4730 }
4731
4732 err = ixgbe_alloc_queues(adapter);
4733 if (err) {
849c4542 4734 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4735 goto err_alloc_queues;
4736 }
4737
849c4542 4738 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4739 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4740 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4741
4742 set_bit(__IXGBE_DOWN, &adapter->state);
4743
9a799d71 4744 return 0;
021230d4 4745
7a921c93
AD		 4746err_alloc_queues:
4747 ixgbe_free_q_vectors(adapter);
4748err_alloc_q_vectors:
4749 ixgbe_reset_interrupt_capability(adapter);
021230d4 4750err_set_interrupt:
7a921c93
AD		 4751 return err;
4752}
4753
1a51502b
ED		 4754static void ring_free_rcu(struct rcu_head *head)
4755{
4756 kfree(container_of(head, struct ixgbe_ring, rcu));
4757}
4758
7a921c93
AD		 4759/**
4760 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4761 * @adapter: board private structure to clear interrupt scheme on
4762 *
4763 * We go through and clear interrupt specific resources and reset the structure
4764 * to pre-load conditions
4765 **/
4766void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4767{
4a0b9ca0
PW		 4768 int i;
4769
4770 for (i = 0; i < adapter->num_tx_queues; i++) {
4771 kfree(adapter->tx_ring[i]);
4772 adapter->tx_ring[i] = NULL;
4773 }
4774 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4775 struct ixgbe_ring *ring = adapter->rx_ring[i];
4776
4777 /* ixgbe_get_stats64() might access this ring, we must wait
4778 * a grace period before freeing it.
4779 */
4780 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 4781 adapter->rx_ring[i] = NULL;
4782 }
7a921c93
AD		 4783
4784 ixgbe_free_q_vectors(adapter);
4785 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4786}
4787
c4900be0
DS		 4788/**
4789 * ixgbe_sfp_timer - worker thread to find a missing module
4790 * @data: pointer to our adapter struct
4791 **/
4792static void ixgbe_sfp_timer(unsigned long data)
4793{
4794 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4795
4df10466
JB		 4796 /*
4797 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4798 * delays that sfp+ detection requires
4799 */
4800 schedule_work(&adapter->sfp_task);
4801}
4802
4803/**
4804 * ixgbe_sfp_task - worker thread to find a missing module
4805 * @work: pointer to work_struct containing our data
4806 **/
4807static void ixgbe_sfp_task(struct work_struct *work)
4808{
4809 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 4810 struct ixgbe_adapter,
4811 sfp_task);
c4900be0
DS		 4812 struct ixgbe_hw *hw = &adapter->hw;
4813
4814 if ((hw->phy.type == ixgbe_phy_nl) &&
4815 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4816 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4817 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4818 goto reschedule;
4819 ret = hw->phy.ops.reset(hw);
4820 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4821 e_dev_err("failed to initialize because an unsupported "
4822 "SFP+ module type was detected.\n");
4823 e_dev_err("Reload the driver after installing a "
4824 "supported module.\n");
c4900be0
DS		 4825 unregister_netdev(adapter->netdev);
4826 } else {
396e799c 4827 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4828 }
4829 /* don't need this routine any more */
4830 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4831 }
4832 return;
4833reschedule:
4834 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4835 mod_timer(&adapter->sfp_timer,
e8e9f696 4836 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 4837}
4838
9a799d71
AK		 4839/**
4840 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4841 * @adapter: board private structure to initialize
4842 *
4843 * ixgbe_sw_init initializes the Adapter private data structure.
4844 * Fields are initialized based on PCI device information and
4845 * OS network device settings (MTU size).
4846 **/
4847static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4848{
4849 struct ixgbe_hw *hw = &adapter->hw;
4850 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4851 struct net_device *dev = adapter->netdev;
021230d4 4852 unsigned int rss;
7a6b6f51 4853#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4854 int j;
4855 struct tc_configuration *tc;
4856#endif
16b61beb 4857 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 4858
c44ade9e
JB		 4859 /* PCI config space info */
4860
4861 hw->vendor_id = pdev->vendor;
4862 hw->device_id = pdev->device;
4863 hw->revision_id = pdev->revision;
4864 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4865 hw->subsystem_device_id = pdev->subsystem_device;
4866
021230d4
AV		 4867 /* Set capability flags */
4868 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4869 adapter->ring_feature[RING_F_RSS].indices = rss;
4870 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4871 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4872 if (hw->mac.type == ixgbe_mac_82598EB) {
4873 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4874 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4875 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4876 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4877 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4878 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4879 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4880 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4881 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4882 if (dev->features & NETIF_F_NTUPLE) {
4883 /* Flow Director perfect filter enabled */
4884 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4885 adapter->atr_sample_rate = 0;
4886 spin_lock_init(&adapter->fdir_perfect_lock);
4887 } else {
4888 /* Flow Director hash filters enabled */
4889 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4890 adapter->atr_sample_rate = 20;
4891 }
c4cf55e5 4892 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4893 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4894 adapter->fdir_pballoc = 0;
eacd73f7 4895#ifdef IXGBE_FCOE
0d551589
YZ		 4896 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4897 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4898 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4899#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4900 /* Default traffic class to use for FCoE */
4901 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4902 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4903#endif
eacd73f7 4904#endif /* IXGBE_FCOE */
f8212f97 4905 }
2f90b865 4906
7a6b6f51 4907#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4908 /* Configure DCB traffic classes */
4909 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4910 tc = &adapter->dcb_cfg.tc_config[j];
4911 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4912 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4913 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4914 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4915 tc->dcb_pfc = pfc_disabled;
4916 }
4917 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4918 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4919 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4920 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4921 adapter->dcb_cfg.round_robin_enable = false;
4922 adapter->dcb_set_bitmap = 0x00;
4923 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e8e9f696 4924 adapter->ring_feature[RING_F_DCB].indices);
2f90b865
AD		 4925
4926#endif
9a799d71
AK		 4927
4928 /* default flow control settings */
cd7664f6 4929 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4930 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4931#ifdef CONFIG_DCB
4932 adapter->last_lfc_mode = hw->fc.current_mode;
4933#endif
16b61beb
JF		 4934 hw->fc.high_water = FC_HIGH_WATER(max_frame);
4935 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 4936 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4937 hw->fc.send_xon = true;
71fd570b 4938 hw->fc.disable_fc_autoneg = false;
9a799d71 4939
30efa5a3 4940 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4941 adapter->rx_itr_setting = 1;
4942 adapter->rx_eitr_param = 20000;
4943 adapter->tx_itr_setting = 1;
4944 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4945
4946 /* set defaults for eitr in MegaBytes */
4947 adapter->eitr_low = 10;
4948 adapter->eitr_high = 20;
4949
4950 /* set default ring sizes */
4951 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4952 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4953
9a799d71 4954 /* initialize eeprom parameters */
c44ade9e 4955 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4956 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4957 return -EIO;
4958 }
4959
021230d4 4960 /* enable rx csum by default */
9a799d71
AK		 4961 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4962
1a6c14a2
JB		 4963 /* get assigned NUMA node */
4964 adapter->node = dev_to_node(&pdev->dev);
4965
9a799d71
AK		 4966 set_bit(__IXGBE_DOWN, &adapter->state);
4967
4968 return 0;
4969}
4970
4971/**
4972 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4973 * @adapter: board private structure
3a581073 4974 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4975 *
4976 * Return 0 on success, negative on failure
4977 **/
4978int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e8e9f696 4979 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4980{
4981 struct pci_dev *pdev = adapter->pdev;
4982 int size;
4983
3a581073 4984 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4985 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4986 if (!tx_ring->tx_buffer_info)
4987 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4988 if (!tx_ring->tx_buffer_info)
4989 goto err;
3a581073 4990 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4991
4992 /* round up to nearest 4K */
12207e49 4993 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4994 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4995
1b507730
NN		 4996 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4997 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4998 if (!tx_ring->desc)
4999 goto err;
9a799d71 5000
3a581073
JB		 5001 tx_ring->next_to_use = 0;
5002 tx_ring->next_to_clean = 0;
5003 tx_ring->work_limit = tx_ring->count;
9a799d71 5004 return 0;
e01c31a5
JB		 5005
5006err:
5007 vfree(tx_ring->tx_buffer_info);
5008 tx_ring->tx_buffer_info = NULL;
396e799c 5009 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5010 return -ENOMEM;
9a799d71
AK		 5011}
5012
69888674
AD		 5013/**
5014 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5015 * @adapter: board private structure
5016 *
5017 * If this function returns with an error, then it's possible one or
5018 * more of the rings is populated (while the rest are not). It is the
5019 * callers duty to clean those orphaned rings.
5020 *
5021 * Return 0 on success, negative on failure
5022 **/
5023static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5024{
5025 int i, err = 0;
5026
5027 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5028 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 5029 if (!err)
5030 continue;
396e799c 5031 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5032 break;
5033 }
5034
5035 return err;
5036}
5037
9a799d71
AK		 5038/**
5039 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5040 * @adapter: board private structure
3a581073 5041 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5042 *
5043 * Returns 0 on success, negative on failure
5044 **/
5045int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5046 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5047{
5048 struct pci_dev *pdev = adapter->pdev;
021230d4 5049 int size;
9a799d71 5050
3a581073 5051 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 5052 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
5053 if (!rx_ring->rx_buffer_info)
5054 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 5055 if (!rx_ring->rx_buffer_info) {
396e799c
ET		 5056 e_err(probe, "vmalloc allocation failed for the Rx "
5057 "descriptor ring\n");
177db6ff 5058 goto alloc_failed;
9a799d71 5059 }
3a581073 5060 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 5061
9a799d71 5062 /* Round up to nearest 4K */
3a581073
JB		 5063 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5064 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5065
1b507730
NN		 5066 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
5067 &rx_ring->dma, GFP_KERNEL);
9a799d71 5068
3a581073 5069 if (!rx_ring->desc) {
396e799c
ET		 5070 e_err(probe, "Memory allocation failed for the Rx "
5071 "descriptor ring\n");
3a581073 5072 vfree(rx_ring->rx_buffer_info);
177db6ff 5073 goto alloc_failed;
9a799d71
AK		 5074 }
5075
3a581073
JB		 5076 rx_ring->next_to_clean = 0;
5077 rx_ring->next_to_use = 0;
9a799d71
AK		 5078
5079 return 0;
177db6ff
MC		 5080
5081alloc_failed:
177db6ff 5082 return -ENOMEM;
9a799d71
AK		 5083}
5084
69888674
AD		 5085/**
5086 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5087 * @adapter: board private structure
5088 *
5089 * If this function returns with an error, then it's possible one or
5090 * more of the rings is populated (while the rest are not). It is the
5091 * callers duty to clean those orphaned rings.
5092 *
5093 * Return 0 on success, negative on failure
5094 **/
5095
5096static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5097{
5098 int i, err = 0;
5099
5100 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 5101 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 5102 if (!err)
5103 continue;
396e799c 5104 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5105 break;
5106 }
5107
5108 return err;
5109}
5110
9a799d71
AK		 5111/**
5112 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5113 * @adapter: board private structure
5114 * @tx_ring: Tx descriptor ring for a specific queue
5115 *
5116 * Free all transmit software resources
5117 **/
c431f97e 5118void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5119 struct ixgbe_ring *tx_ring)
9a799d71
AK		 5120{
5121 struct pci_dev *pdev = adapter->pdev;
5122
5123 ixgbe_clean_tx_ring(adapter, tx_ring);
5124
5125 vfree(tx_ring->tx_buffer_info);
5126 tx_ring->tx_buffer_info = NULL;
5127
1b507730
NN		 5128 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5129 tx_ring->dma);
9a799d71
AK		 5130
5131 tx_ring->desc = NULL;
5132}
5133
5134/**
5135 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5136 * @adapter: board private structure
5137 *
5138 * Free all transmit software resources
5139 **/
5140static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5141{
5142 int i;
5143
5144 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 5145 if (adapter->tx_ring[i]->desc)
5146 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 5147}
5148
5149/**
b4617240 5150 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5151 * @adapter: board private structure
5152 * @rx_ring: ring to clean the resources from
5153 *
5154 * Free all receive software resources
5155 **/
c431f97e 5156void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5157 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5158{
5159 struct pci_dev *pdev = adapter->pdev;
5160
5161 ixgbe_clean_rx_ring(adapter, rx_ring);
5162
5163 vfree(rx_ring->rx_buffer_info);
5164 rx_ring->rx_buffer_info = NULL;
5165
1b507730
NN		 5166 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5167 rx_ring->dma);
9a799d71
AK		 5168
5169 rx_ring->desc = NULL;
5170}
5171
5172/**
5173 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5174 * @adapter: board private structure
5175 *
5176 * Free all receive software resources
5177 **/
5178static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5179{
5180 int i;
5181
5182 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 5183 if (adapter->rx_ring[i]->desc)
5184 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 5185}
5186
9a799d71
AK		 5187/**
5188 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5189 * @netdev: network interface device structure
5190 * @new_mtu: new value for maximum frame size
5191 *
5192 * Returns 0 on success, negative on failure
5193 **/
5194static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5195{
5196 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5197 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5198 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5199
42c783c5
JB		 5200 /* MTU < 68 is an error and causes problems on some kernels */
5201 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5202 return -EINVAL;
5203
396e799c 5204 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5205 /* must set new MTU before calling down or up */
9a799d71
AK		 5206 netdev->mtu = new_mtu;
5207
16b61beb
JF		 5208 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5209 hw->fc.low_water = FC_LOW_WATER(max_frame);
5210
d4f80882
AV		 5211 if (netif_running(netdev))
5212 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5213
5214 return 0;
5215}
5216
5217/**
5218 * ixgbe_open - Called when a network interface is made active
5219 * @netdev: network interface device structure
5220 *
5221 * Returns 0 on success, negative value on failure
5222 *
5223 * The open entry point is called when a network interface is made
5224 * active by the system (IFF_UP). At this point all resources needed
5225 * for transmit and receive operations are allocated, the interrupt
5226 * handler is registered with the OS, the watchdog timer is started,
5227 * and the stack is notified that the interface is ready.
5228 **/
5229static int ixgbe_open(struct net_device *netdev)
5230{
5231 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5232 int err;
4bebfaa5
AK		 5233
5234 /* disallow open during test */
5235 if (test_bit(__IXGBE_TESTING, &adapter->state))
5236 return -EBUSY;
9a799d71 5237
54386467
JB		 5238 netif_carrier_off(netdev);
5239
9a799d71
AK		 5240 /* allocate transmit descriptors */
5241 err = ixgbe_setup_all_tx_resources(adapter);
5242 if (err)
5243 goto err_setup_tx;
5244
9a799d71
AK		 5245 /* allocate receive descriptors */
5246 err = ixgbe_setup_all_rx_resources(adapter);
5247 if (err)
5248 goto err_setup_rx;
5249
5250 ixgbe_configure(adapter);
5251
021230d4 5252 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5253 if (err)
5254 goto err_req_irq;
5255
9a799d71
AK		 5256 err = ixgbe_up_complete(adapter);
5257 if (err)
5258 goto err_up;
5259
d55b53ff
JK		 5260 netif_tx_start_all_queues(netdev);
5261
9a799d71
AK		 5262 return 0;
5263
5264err_up:
5eba3699 5265 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5266 ixgbe_free_irq(adapter);
5267err_req_irq:
9a799d71 5268err_setup_rx:
a20a1199 5269 ixgbe_free_all_rx_resources(adapter);
9a799d71 5270err_setup_tx:
a20a1199 5271 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5272 ixgbe_reset(adapter);
5273
5274 return err;
5275}
5276
5277/**
5278 * ixgbe_close - Disables a network interface
5279 * @netdev: network interface device structure
5280 *
5281 * Returns 0, this is not allowed to fail
5282 *
5283 * The close entry point is called when an interface is de-activated
5284 * by the OS. The hardware is still under the drivers control, but
5285 * needs to be disabled. A global MAC reset is issued to stop the
5286 * hardware, and all transmit and receive resources are freed.
5287 **/
5288static int ixgbe_close(struct net_device *netdev)
5289{
5290 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5291
5292 ixgbe_down(adapter);
5293 ixgbe_free_irq(adapter);
5294
5295 ixgbe_free_all_tx_resources(adapter);
5296 ixgbe_free_all_rx_resources(adapter);
5297
5eba3699 5298 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5299
5300 return 0;
5301}
5302
b3c8b4ba
AD		 5303#ifdef CONFIG_PM
5304static int ixgbe_resume(struct pci_dev *pdev)
5305{
5306 struct net_device *netdev = pci_get_drvdata(pdev);
5307 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5308 u32 err;
5309
5310 pci_set_power_state(pdev, PCI_D0);
5311 pci_restore_state(pdev);
656ab817
DS		 5312 /*
5313 * pci_restore_state clears dev->state_saved so call
5314 * pci_save_state to restore it.
5315 */
5316 pci_save_state(pdev);
9ce77666 5317
5318 err = pci_enable_device_mem(pdev);
b3c8b4ba 5319 if (err) {
849c4542 5320 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5321 return err;
5322 }
5323 pci_set_master(pdev);
5324
dd4d8ca6 5325 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5326
5327 err = ixgbe_init_interrupt_scheme(adapter);
5328 if (err) {
849c4542 5329 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5330 return err;
5331 }
5332
b3c8b4ba
AD		 5333 ixgbe_reset(adapter);
5334
495dce12
WJP		 5335 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5336
b3c8b4ba
AD		 5337 if (netif_running(netdev)) {
5338 err = ixgbe_open(adapter->netdev);
5339 if (err)
5340 return err;
5341 }
5342
5343 netif_device_attach(netdev);
5344
5345 return 0;
5346}
b3c8b4ba 5347#endif /* CONFIG_PM */
9d8d05ae
RW		 5348
5349static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5350{
5351 struct net_device *netdev = pci_get_drvdata(pdev);
5352 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5353 struct ixgbe_hw *hw = &adapter->hw;
5354 u32 ctrl, fctrl;
5355 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5356#ifdef CONFIG_PM
5357 int retval = 0;
5358#endif
5359
5360 netif_device_detach(netdev);
5361
5362 if (netif_running(netdev)) {
5363 ixgbe_down(adapter);
5364 ixgbe_free_irq(adapter);
5365 ixgbe_free_all_tx_resources(adapter);
5366 ixgbe_free_all_rx_resources(adapter);
5367 }
b3c8b4ba
AD		 5368
5369#ifdef CONFIG_PM
5370 retval = pci_save_state(pdev);
5371 if (retval)
5372 return retval;
4df10466 5373
b3c8b4ba 5374#endif
e8e26350
PW		 5375 if (wufc) {
5376 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5377
e8e26350
PW		 5378 /* turn on all-multi mode if wake on multicast is enabled */
5379 if (wufc & IXGBE_WUFC_MC) {
5380 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5381 fctrl |= IXGBE_FCTRL_MPE;
5382 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5383 }
5384
5385 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5386 ctrl |= IXGBE_CTRL_GIO_DIS;
5387 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5388
5389 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5390 } else {
5391 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5392 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5393 }
5394
dd4d8ca6
DS		 5395 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5396 pci_wake_from_d3(pdev, true);
5397 else
5398 pci_wake_from_d3(pdev, false);
b3c8b4ba 5399
9d8d05ae
RW		 5400 *enable_wake = !!wufc;
5401
fa378134
AG		 5402 ixgbe_clear_interrupt_scheme(adapter);
5403
b3c8b4ba
AD		 5404 ixgbe_release_hw_control(adapter);
5405
5406 pci_disable_device(pdev);
5407
9d8d05ae
RW		 5408 return 0;
5409}
5410
5411#ifdef CONFIG_PM
5412static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5413{
5414 int retval;
5415 bool wake;
5416
5417 retval = __ixgbe_shutdown(pdev, &wake);
5418 if (retval)
5419 return retval;
5420
5421 if (wake) {
5422 pci_prepare_to_sleep(pdev);
5423 } else {
5424 pci_wake_from_d3(pdev, false);
5425 pci_set_power_state(pdev, PCI_D3hot);
5426 }
b3c8b4ba
AD		 5427
5428 return 0;
5429}
9d8d05ae 5430#endif /* CONFIG_PM */
b3c8b4ba
AD		 5431
5432static void ixgbe_shutdown(struct pci_dev *pdev)
5433{
9d8d05ae
RW		 5434 bool wake;
5435
5436 __ixgbe_shutdown(pdev, &wake);
5437
5438 if (system_state == SYSTEM_POWER_OFF) {
5439 pci_wake_from_d3(pdev, wake);
5440 pci_set_power_state(pdev, PCI_D3hot);
5441 }
b3c8b4ba
AD		 5442}
5443
9a799d71
AK		 5444/**
5445 * ixgbe_update_stats - Update the board statistics counters.
5446 * @adapter: board private structure
5447 **/
5448void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5449{
2d86f139 5450 struct net_device *netdev = adapter->netdev;
9a799d71 5451 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5452 u64 total_mpc = 0;
5453 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5454 u64 non_eop_descs = 0, restart_queue = 0;
7ca647bd 5455 struct ixgbe_hw_stats *hwstats = &adapter->stats;
9a799d71 5456
d08935c2
DS		 5457 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5458 test_bit(__IXGBE_RESETTING, &adapter->state))
5459 return;
5460
94b982b2 5461 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5462 u64 rsc_count = 0;
94b982b2 5463 u64 rsc_flush = 0;
d51019a4
PW		 5464 for (i = 0; i < 16; i++)
5465 adapter->hw_rx_no_dma_resources +=
7ca647bd 5466 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5467 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5468 rsc_count += adapter->rx_ring[i]->rsc_count;
5469 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5470 }
5471 adapter->rsc_total_count = rsc_count;
5472 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5473 }
5474
7ca3bc58
JB		 5475 /* gather some stats to the adapter struct that are per queue */
5476 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5477 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5478 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5479
5480 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5481 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5482 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5483
7ca647bd 5484 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5485 for (i = 0; i < 8; i++) {
5486 /* for packet buffers not used, the register should read 0 */
5487 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5488 missed_rx += mpc;
7ca647bd
JP		 5489 hwstats->mpc[i] += mpc;
5490 total_mpc += hwstats->mpc[i];
e8e26350 5491 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5492 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5493 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5494 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5495 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5496 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350 5497 if (hw->mac.type == ixgbe_mac_82599EB) {
7ca647bd
JP		 5498 hwstats->pxonrxc[i] +=
5499 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5500 hwstats->pxoffrxc[i] +=
5501 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5502 hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350 5503 } else {
7ca647bd
JP		 5504 hwstats->pxonrxc[i] +=
5505 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5506 hwstats->pxoffrxc[i] +=
5507 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
e8e26350 5508 }
7ca647bd
JP		 5509 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5510 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5511 }
7ca647bd 5512 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5513 /* work around hardware counting issue */
7ca647bd 5514 hwstats->gprc -= missed_rx;
6f11eef7
AV		 5515
5516 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5517 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5518 u64 tmp;
7ca647bd 5519 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
e8e9f696
JP		 5520 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5521 /* 4 high bits of GORC */
7ca647bd
JP		 5522 hwstats->gorc += (tmp << 32);
5523 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
e8e9f696
JP		 5524 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5525 /* 4 high bits of GOTC */
7ca647bd
JP		 5526 hwstats->gotc += (tmp << 32);
5527 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
e8e9f696 5528 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd
JP		 5529 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5530 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5531 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5532 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5533#ifdef IXGBE_FCOE
7ca647bd
JP		 5534 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5535 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5536 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5537 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5538 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5539 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5540#endif /* IXGBE_FCOE */
e8e26350 5541 } else {
7ca647bd
JP		 5542 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5543 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5544 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5545 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5546 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
e8e26350 5547 }
9a799d71 5548 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5549 hwstats->bprc += bprc;
5550 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5551 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5552 hwstats->mprc -= bprc;
5553 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5554 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5555 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5556 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5557 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5558 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5559 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5560 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5561 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5562 hwstats->lxontxc += lxon;
6f11eef7 5563 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5564 hwstats->lxofftxc += lxoff;
5565 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5566 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5567 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5568 /*
5569 * 82598 errata - tx of flow control packets is included in tx counters
5570 */
5571 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5572 hwstats->gptc -= xon_off_tot;
5573 hwstats->mptc -= xon_off_tot;
5574 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5575 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5576 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5577 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5578 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5579 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5580 hwstats->ptc64 -= xon_off_tot;
5581 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5582 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5583 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5584 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5585 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5586 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5587
5588 /* Fill out the OS statistics structure */
7ca647bd 5589 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5590
5591 /* Rx Errors */
7ca647bd 5592 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5593 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5594 netdev->stats.rx_length_errors = hwstats->rlec;
5595 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5596 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5597}
5598
5599/**
5600 * ixgbe_watchdog - Timer Call-back
5601 * @data: pointer to adapter cast into an unsigned long
5602 **/
5603static void ixgbe_watchdog(unsigned long data)
5604{
5605 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5606 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5607 u64 eics = 0;
5608 int i;
cf8280ee 5609
fe49f04a
AD		 5610 /*
5611 * Do the watchdog outside of interrupt context due to the lovely
5612 * delays that some of the newer hardware requires
5613 */
22d5a71b 5614
fe49f04a
AD		 5615 if (test_bit(__IXGBE_DOWN, &adapter->state))
5616 goto watchdog_short_circuit;
22d5a71b 5617
fe49f04a
AD		 5618 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5619 /*
5620 * for legacy and MSI interrupts don't set any bits
5621 * that are enabled for EIAM, because this operation
5622 * would set *both* EIMS and EICS for any bit in EIAM
5623 */
5624 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5625 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5626 goto watchdog_reschedule;
5627 }
5628
5629 /* get one bit for every active tx/rx interrupt vector */
5630 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5631 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5632 if (qv->rxr_count || qv->txr_count)
5633 eics |= ((u64)1 << i);
cf8280ee 5634 }
9a799d71 5635
fe49f04a
AD		 5636 /* Cause software interrupt to ensure rx rings are cleaned */
5637 ixgbe_irq_rearm_queues(adapter, eics);
5638
5639watchdog_reschedule:
5640 /* Reset the timer */
5641 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5642
5643watchdog_short_circuit:
cf8280ee
JB		 5644 schedule_work(&adapter->watchdog_task);
5645}
5646
e8e26350
PW		 5647/**
5648 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5649 * @work: pointer to work_struct containing our data
5650 **/
5651static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5652{
5653 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5654 struct ixgbe_adapter,
5655 multispeed_fiber_task);
e8e26350
PW		 5656 struct ixgbe_hw *hw = &adapter->hw;
5657 u32 autoneg;
8620a103 5658 bool negotiation;
e8e26350
PW		 5659
5660 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5661 autoneg = hw->phy.autoneg_advertised;
5662 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5663 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5664 hw->mac.autotry_restart = false;
8620a103
MC		 5665 if (hw->mac.ops.setup_link)
5666 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5667 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5668 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5669}
5670
5671/**
5672 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5673 * @work: pointer to work_struct containing our data
5674 **/
5675static void ixgbe_sfp_config_module_task(struct work_struct *work)
5676{
5677 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5678 struct ixgbe_adapter,
5679 sfp_config_module_task);
e8e26350
PW		 5680 struct ixgbe_hw *hw = &adapter->hw;
5681 u32 err;
5682
5683 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5684
5685 /* Time for electrical oscillations to settle down */
5686 msleep(100);
e8e26350 5687 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5688
e8e26350 5689 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5690 e_dev_err("failed to initialize because an unsupported SFP+ "
5691 "module type was detected.\n");
5692 e_dev_err("Reload the driver after installing a supported "
5693 "module.\n");
63d6e1d8 5694 unregister_netdev(adapter->netdev);
e8e26350
PW		 5695 return;
5696 }
5697 hw->mac.ops.setup_sfp(hw);
5698
8d1c3c07 5699 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5700 /* This will also work for DA Twinax connections */
5701 schedule_work(&adapter->multispeed_fiber_task);
5702 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5703}
5704
c4cf55e5
PWJ		 5705/**
5706 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5707 * @work: pointer to work_struct containing our data
5708 **/
5709static void ixgbe_fdir_reinit_task(struct work_struct *work)
5710{
5711 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5712 struct ixgbe_adapter,
5713 fdir_reinit_task);
c4cf55e5
PWJ		 5714 struct ixgbe_hw *hw = &adapter->hw;
5715 int i;
5716
5717 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5718 for (i = 0; i < adapter->num_tx_queues; i++)
5719 set_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 5720 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 5721 } else {
396e799c 5722 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5723 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5724 }
5725 /* Done FDIR Re-initialization, enable transmits */
5726 netif_tx_start_all_queues(adapter->netdev);
5727}
5728
10eec955
JF		 5729static DEFINE_MUTEX(ixgbe_watchdog_lock);
5730
cf8280ee 5731/**
69888674
AD		 5732 * ixgbe_watchdog_task - worker thread to bring link up
5733 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5734 **/
5735static void ixgbe_watchdog_task(struct work_struct *work)
5736{
5737 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5738 struct ixgbe_adapter,
5739 watchdog_task);
cf8280ee
JB		 5740 struct net_device *netdev = adapter->netdev;
5741 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5742 u32 link_speed;
5743 bool link_up;
bc59fcda
NS		 5744 int i;
5745 struct ixgbe_ring *tx_ring;
5746 int some_tx_pending = 0;
cf8280ee 5747
10eec955
JF		 5748 mutex_lock(&ixgbe_watchdog_lock);
5749
5750 link_up = adapter->link_up;
5751 link_speed = adapter->link_speed;
cf8280ee
JB		 5752
5753 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5754 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5755 if (link_up) {
5756#ifdef CONFIG_DCB
5757 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5758 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5759 hw->mac.ops.fc_enable(hw, i);
264857b8 5760 } else {
620fa036 5761 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5762 }
5763#else
620fa036 5764 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5765#endif
5766 }
5767
cf8280ee
JB		 5768 if (link_up ||
5769 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 5770 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5771 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5772 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5773 }
5774 adapter->link_up = link_up;
5775 adapter->link_speed = link_speed;
5776 }
9a799d71
AK		 5777
5778 if (link_up) {
5779 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5780 bool flow_rx, flow_tx;
5781
5782 if (hw->mac.type == ixgbe_mac_82599EB) {
5783 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5784 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5785 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5786 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5787 } else {
5788 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5789 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5790 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5791 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5792 }
5793
396e799c 5794 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5795 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5796 "10 Gbps" :
5797 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5798 "1 Gbps" : "unknown speed")),
e8e26350 5799 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5800 (flow_rx ? "RX" :
5801 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5802
5803 netif_carrier_on(netdev);
9a799d71
AK		 5804 } else {
5805 /* Force detection of hung controller */
5806 adapter->detect_tx_hung = true;
5807 }
5808 } else {
cf8280ee
JB		 5809 adapter->link_up = false;
5810 adapter->link_speed = 0;
9a799d71 5811 if (netif_carrier_ok(netdev)) {
396e799c 5812 e_info(drv, "NIC Link is Down\n");
9a799d71 5813 netif_carrier_off(netdev);
9a799d71
AK		 5814 }
5815 }
5816
bc59fcda
NS		 5817 if (!netif_carrier_ok(netdev)) {
5818 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5819 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5820 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5821 some_tx_pending = 1;
5822 break;
5823 }
5824 }
5825
5826 if (some_tx_pending) {
5827 /* We've lost link, so the controller stops DMA,
5828 * but we've got queued Tx work that's never going
5829 * to get done, so reset controller to flush Tx.
5830 * (Do the reset outside of interrupt context).
5831 */
5832 schedule_work(&adapter->reset_task);
5833 }
5834 }
5835
9a799d71 5836 ixgbe_update_stats(adapter);
10eec955 5837 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5838}
5839
9a799d71 5840static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 5841 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 5842 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 5843{
5844 struct ixgbe_adv_tx_context_desc *context_desc;
5845 unsigned int i;
5846 int err;
5847 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5848 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5849 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5850
5851 if (skb_is_gso(skb)) {
5852 if (skb_header_cloned(skb)) {
5853 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5854 if (err)
5855 return err;
5856 }
5857 l4len = tcp_hdrlen(skb);
5858 *hdr_len += l4len;
5859
5e09a105 5860 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5861 struct iphdr *iph = ip_hdr(skb);
5862 iph->tot_len = 0;
5863 iph->check = 0;
5864 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 5865 iph->daddr, 0,
5866 IPPROTO_TCP,
5867 0);
8e1e8a47 5868 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5869 ipv6_hdr(skb)->payload_len = 0;
5870 tcp_hdr(skb)->check =
5871 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 5872 &ipv6_hdr(skb)->daddr,
5873 0, IPPROTO_TCP, 0);
9a799d71
AK		 5874 }
5875
5876 i = tx_ring->next_to_use;
5877
5878 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5879 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5880
5881 /* VLAN MACLEN IPLEN */
5882 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5883 vlan_macip_lens |=
5884 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5885 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 5886 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5887 *hdr_len += skb_network_offset(skb);
5888 vlan_macip_lens |=
5889 (skb_transport_header(skb) - skb_network_header(skb));
5890 *hdr_len +=
5891 (skb_transport_header(skb) - skb_network_header(skb));
5892 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5893 context_desc->seqnum_seed = 0;
5894
5895 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5896 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 5897 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5898
5e09a105 5899 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 5900 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5901 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5902 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5903
5904 /* MSS L4LEN IDX */
9f8cdf4f 5905 mss_l4len_idx =
9a799d71
AK		 5906 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5907 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5908 /* use index 1 for TSO */
5909 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5910 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5911
5912 tx_buffer_info->time_stamp = jiffies;
5913 tx_buffer_info->next_to_watch = i;
5914
5915 i++;
5916 if (i == tx_ring->count)
5917 i = 0;
5918 tx_ring->next_to_use = i;
5919
5920 return true;
5921 }
5922 return false;
5923}
5924
5e09a105
HZ		 5925static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5926 __be16 protocol)
7ca647bd
JP		 5927{
5928 u32 rtn = 0;
7ca647bd
JP		 5929
5930 switch (protocol) {
5931 case cpu_to_be16(ETH_P_IP):
5932 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5933 switch (ip_hdr(skb)->protocol) {
5934 case IPPROTO_TCP:
5935 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5936 break;
5937 case IPPROTO_SCTP:
5938 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5939 break;
5940 }
5941 break;
5942 case cpu_to_be16(ETH_P_IPV6):
5943 /* XXX what about other V6 headers?? */
5944 switch (ipv6_hdr(skb)->nexthdr) {
5945 case IPPROTO_TCP:
5946 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5947 break;
5948 case IPPROTO_SCTP:
5949 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5950 break;
5951 }
5952 break;
5953 default:
5954 if (unlikely(net_ratelimit()))
5955 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 5956 protocol);
7ca647bd
JP		 5957 break;
5958 }
5959
5960 return rtn;
5961}
5962
9a799d71 5963static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 5964 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 5965 struct sk_buff *skb, u32 tx_flags,
5966 __be16 protocol)
9a799d71
AK		 5967{
5968 struct ixgbe_adv_tx_context_desc *context_desc;
5969 unsigned int i;
5970 struct ixgbe_tx_buffer *tx_buffer_info;
5971 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5972
5973 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5974 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5975 i = tx_ring->next_to_use;
5976 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5977 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5978
5979 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5980 vlan_macip_lens |=
5981 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5982 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 5983 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5984 if (skb->ip_summed == CHECKSUM_PARTIAL)
5985 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 5986 skb_network_header(skb));
9a799d71
AK		 5987
5988 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5989 context_desc->seqnum_seed = 0;
5990
5991 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 5992 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5993
7ca647bd 5994 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 5995 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 5996
5997 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5998 /* use index zero for tx checksum offload */
9a799d71
AK		 5999 context_desc->mss_l4len_idx = 0;
6000
6001 tx_buffer_info->time_stamp = jiffies;
6002 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6003
9a799d71
AK		 6004 i++;
6005 if (i == tx_ring->count)
6006 i = 0;
6007 tx_ring->next_to_use = i;
6008
6009 return true;
6010 }
9f8cdf4f 6011
9a799d71
AK		 6012 return false;
6013}
6014
6015static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6016 struct ixgbe_ring *tx_ring,
6017 struct sk_buff *skb, u32 tx_flags,
6018 unsigned int first)
9a799d71 6019{
e5a43549 6020 struct pci_dev *pdev = adapter->pdev;
9a799d71 6021 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6022 unsigned int len;
6023 unsigned int total = skb->len;
9a799d71
AK		 6024 unsigned int offset = 0, size, count = 0, i;
6025 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6026 unsigned int f;
9a799d71
AK		 6027
6028 i = tx_ring->next_to_use;
6029
eacd73f7
YZ		 6030 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6031 /* excluding fcoe_crc_eof for FCoE */
6032 total -= sizeof(struct fcoe_crc_eof);
6033
6034 len = min(skb_headlen(skb), total);
9a799d71
AK		 6035 while (len) {
6036 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6037 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6038
6039 tx_buffer_info->length = size;
e5a43549 6040 tx_buffer_info->mapped_as_page = false;
1b507730 6041 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 6042 skb->data + offset,
1b507730
NN		 6043 size, DMA_TO_DEVICE);
6044 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 6045 goto dma_error;
9a799d71
AK		 6046 tx_buffer_info->time_stamp = jiffies;
6047 tx_buffer_info->next_to_watch = i;
6048
6049 len -= size;
eacd73f7 6050 total -= size;
9a799d71
AK		 6051 offset += size;
6052 count++;
44df32c5
AD		 6053
6054 if (len) {
6055 i++;
6056 if (i == tx_ring->count)
6057 i = 0;
6058 }
9a799d71
AK		 6059 }
6060
6061 for (f = 0; f < nr_frags; f++) {
6062 struct skb_frag_struct *frag;
6063
6064 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6065 len = min((unsigned int)frag->size, total);
e5a43549 6066 offset = frag->page_offset;
9a799d71
AK		 6067
6068 while (len) {
44df32c5
AD		 6069 i++;
6070 if (i == tx_ring->count)
6071 i = 0;
6072
9a799d71
AK		 6073 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6074 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6075
6076 tx_buffer_info->length = size;
1b507730 6077 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 6078 frag->page,
6079 offset, size,
1b507730 6080 DMA_TO_DEVICE);
e5a43549 6081 tx_buffer_info->mapped_as_page = true;
1b507730 6082 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 6083 goto dma_error;
9a799d71
AK		 6084 tx_buffer_info->time_stamp = jiffies;
6085 tx_buffer_info->next_to_watch = i;
6086
6087 len -= size;
eacd73f7 6088 total -= size;
9a799d71
AK		 6089 offset += size;
6090 count++;
9a799d71 6091 }
eacd73f7
YZ		 6092 if (total == 0)
6093 break;
9a799d71 6094 }
44df32c5 6095
9a799d71
AK		 6096 tx_ring->tx_buffer_info[i].skb = skb;
6097 tx_ring->tx_buffer_info[first].next_to_watch = i;
6098
e5a43549
AD		 6099 return count;
6100
6101dma_error:
849c4542 6102 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6103
6104 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6105 tx_buffer_info->dma = 0;
6106 tx_buffer_info->time_stamp = 0;
6107 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6108 if (count)
6109 count--;
e5a43549
AD		 6110
6111 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6112 while (count--) {
e8e9f696 6113 if (i == 0)
e5a43549 6114 i += tx_ring->count;
c1fa347f 6115 i--;
e5a43549
AD		 6116 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6117 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6118 }
6119
e44d38e1 6120 return 0;
9a799d71
AK		 6121}
6122
6123static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6124 struct ixgbe_ring *tx_ring,
6125 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6126{
6127 union ixgbe_adv_tx_desc *tx_desc = NULL;
6128 struct ixgbe_tx_buffer *tx_buffer_info;
6129 u32 olinfo_status = 0, cmd_type_len = 0;
6130 unsigned int i;
6131 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6132
6133 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6134
6135 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6136
6137 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6138 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6139
6140 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6141 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6142
6143 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6144 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6145
4eeae6fd
PW		 6146 /* use index 1 context for tso */
6147 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6148 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6149 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6150 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6151
6152 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6153 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6154 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6155
eacd73f7
YZ		 6156 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6157 olinfo_status |= IXGBE_ADVTXD_CC;
6158 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6159 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6160 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6161 }
6162
9a799d71
AK		 6163 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6164
6165 i = tx_ring->next_to_use;
6166 while (count--) {
6167 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6168 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6169 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6170 tx_desc->read.cmd_type_len =
e8e9f696 6171 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6172 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6173 i++;
6174 if (i == tx_ring->count)
6175 i = 0;
6176 }
6177
6178 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6179
6180 /*
6181 * Force memory writes to complete before letting h/w
6182 * know there are new descriptors to fetch. (Only
6183 * applicable for weak-ordered memory model archs,
6184 * such as IA-64).
6185 */
6186 wmb();
6187
6188 tx_ring->next_to_use = i;
6189 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6190}
6191
c4cf55e5 6192static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5e09a105 6193 int queue, u32 tx_flags, __be16 protocol)
c4cf55e5 6194{
c4cf55e5
PWJ		 6195 struct ixgbe_atr_input atr_input;
6196 struct tcphdr *th;
c4cf55e5
PWJ		 6197 struct iphdr *iph = ip_hdr(skb);
6198 struct ethhdr *eth = (struct ethhdr *)skb->data;
6199 u16 vlan_id, src_port, dst_port, flex_bytes;
6200 u32 src_ipv4_addr, dst_ipv4_addr;
6201 u8 l4type = 0;
6202
d3ead241 6203 /* Right now, we support IPv4 only */
5e09a105 6204 if (protocol != htons(ETH_P_IP))
d3ead241 6205 return;
c4cf55e5
PWJ		 6206 /* check if we're UDP or TCP */
6207 if (iph->protocol == IPPROTO_TCP) {
6208 th = tcp_hdr(skb);
6209 src_port = th->source;
6210 dst_port = th->dest;
6211 l4type |= IXGBE_ATR_L4TYPE_TCP;
6212 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6213 } else {
6214 /* Unsupported L4 header, just bail here */
6215 return;
6216 }
6217
6218 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6219
6220 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
e8e9f696 6221 IXGBE_TX_FLAGS_VLAN_SHIFT;
c4cf55e5
PWJ		 6222 src_ipv4_addr = iph->saddr;
6223 dst_ipv4_addr = iph->daddr;
6224 flex_bytes = eth->h_proto;
6225
6226 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6227 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6228 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6229 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6230 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6231 /* src and dst are inverted, think how the receiver sees them */
6232 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6233 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6234
6235 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6236 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6237}
6238
e092be60 6239static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6240 struct ixgbe_ring *tx_ring, int size)
e092be60 6241{
30eba97a 6242 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6243 /* Herbert's original patch had:
6244 * smp_mb__after_netif_stop_queue();
6245 * but since that doesn't exist yet, just open code it. */
6246 smp_mb();
6247
6248 /* We need to check again in a case another CPU has just
6249 * made room available. */
6250 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6251 return -EBUSY;
6252
6253 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6254 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6255 ++tx_ring->restart_queue;
e092be60
AV		 6256 return 0;
6257}
6258
6259static int ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6260 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6261{
6262 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6263 return 0;
6264 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6265}
6266
09a3b1f8
SH		 6267static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6268{
6269 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6270 int txq = smp_processor_id();
56075a98 6271#ifdef IXGBE_FCOE
5e09a105
HZ		 6272 __be16 protocol;
6273
6274 protocol = vlan_get_protocol(skb);
6275
6276 if ((protocol == htons(ETH_P_FCOE)) ||
6277 (protocol == htons(ETH_P_FIP))) {
56075a98
JF		 6278 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6279 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6280 txq += adapter->ring_feature[RING_F_FCOE].mask;
6281 return txq;
4bc091d8 6282#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6283 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6284 txq = adapter->fcoe.up;
6285 return txq;
4bc091d8 6286#endif
56075a98
JF		 6287 }
6288 }
6289#endif
6290
fdd3d631
KK		 6291 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6292 while (unlikely(txq >= dev->real_num_tx_queues))
6293 txq -= dev->real_num_tx_queues;
5f715823 6294 return txq;
fdd3d631 6295 }
c4cf55e5 6296
2ea186ae
JF		 6297 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6298 if (skb->priority == TC_PRIO_CONTROL)
6299 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6300 else
6301 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6302 >> 13;
6303 return txq;
6304 }
09a3b1f8
SH		 6305
6306 return skb_tx_hash(dev, skb);
6307}
6308
84418e3b
AD		 6309netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
6310 struct ixgbe_adapter *adapter,
6311 struct ixgbe_ring *tx_ring)
9a799d71 6312{
60d51134 6313 struct netdev_queue *txq;
9a799d71
AK		 6314 unsigned int first;
6315 unsigned int tx_flags = 0;
30eba97a 6316 u8 hdr_len = 0;
5f715823 6317 int tso;
9a799d71
AK		 6318 int count = 0;
6319 unsigned int f;
5e09a105
HZ		 6320 __be16 protocol;
6321
6322 protocol = vlan_get_protocol(skb);
9f8cdf4f 6323
eab6d18d 6324 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6325 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6326 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6327 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6328 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6329 }
6330 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6331 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6332 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6333 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6334 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6335 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6336 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6337 }
eacd73f7 6338
09ad1cc0 6339#ifdef IXGBE_FCOE
56075a98
JF		 6340 /* for FCoE with DCB, we force the priority to what
6341 * was specified by the switch */
6342 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
5e09a105
HZ		 6343 (protocol == htons(ETH_P_FCOE) ||
6344 protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6345#ifdef CONFIG_IXGBE_DCB
6346 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6347 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6348 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6349 tx_flags |= ((adapter->fcoe.up << 13)
6350 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6351 }
6352#endif
ca77cd59 6353 /* flag for FCoE offloads */
5e09a105 6354 if (protocol == htons(ETH_P_FCOE))
ca77cd59 6355 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6356 }
ca77cd59
RL		 6357#endif
6358
eacd73f7 6359 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6360 if (skb_is_gso(skb) ||
6361 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6362 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6363 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6364 count++;
6365
9f8cdf4f
JB		 6366 count += TXD_USE_COUNT(skb_headlen(skb));
6367 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6368 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6369
e092be60 6370 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6371 adapter->tx_busy++;
9a799d71
AK		 6372 return NETDEV_TX_BUSY;
6373 }
9a799d71 6374
9a799d71 6375 first = tx_ring->next_to_use;
eacd73f7
YZ		 6376 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6377#ifdef IXGBE_FCOE
6378 /* setup tx offload for FCoE */
6379 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6380 if (tso < 0) {
6381 dev_kfree_skb_any(skb);
6382 return NETDEV_TX_OK;
6383 }
6384 if (tso)
6385 tx_flags |= IXGBE_TX_FLAGS_FSO;
6386#endif /* IXGBE_FCOE */
6387 } else {
5e09a105 6388 if (protocol == htons(ETH_P_IP))
eacd73f7 6389 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6390 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6391 protocol);
eacd73f7
YZ		 6392 if (tso < 0) {
6393 dev_kfree_skb_any(skb);
6394 return NETDEV_TX_OK;
6395 }
9a799d71 6396
eacd73f7
YZ		 6397 if (tso)
6398 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6399 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6400 protocol) &&
eacd73f7
YZ		 6401 (skb->ip_summed == CHECKSUM_PARTIAL))
6402 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6403 }
9a799d71 6404
eacd73f7 6405 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 6406 if (count) {
c4cf55e5
PWJ		 6407 /* add the ATR filter if ATR is on */
6408 if (tx_ring->atr_sample_rate) {
6409 ++tx_ring->atr_count;
6410 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
e8e9f696
JP		 6411 test_bit(__IXGBE_FDIR_INIT_DONE,
6412 &tx_ring->reinit_state)) {
c4cf55e5 6413 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5e09a105 6414 tx_flags, protocol);
c4cf55e5
PWJ		 6415 tx_ring->atr_count = 0;
6416 }
6417 }
60d51134
ED		 6418 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6419 txq->tx_bytes += skb->len;
6420 txq->tx_packets++;
44df32c5 6421 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
e8e9f696 6422 hdr_len);
44df32c5 6423 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6424
44df32c5
AD		 6425 } else {
6426 dev_kfree_skb_any(skb);
6427 tx_ring->tx_buffer_info[first].time_stamp = 0;
6428 tx_ring->next_to_use = first;
6429 }
9a799d71
AK		 6430
6431 return NETDEV_TX_OK;
6432}
6433
84418e3b
AD		 6434static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6435{
6436 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6437 struct ixgbe_ring *tx_ring;
6438
6439 tx_ring = adapter->tx_ring[skb->queue_mapping];
6440 return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
6441}
6442
9a799d71
AK		 6443/**
6444 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6445 * @netdev: network interface device structure
6446 * @p: pointer to an address structure
6447 *
6448 * Returns 0 on success, negative on failure
6449 **/
6450static int ixgbe_set_mac(struct net_device *netdev, void *p)
6451{
6452 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6453 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6454 struct sockaddr *addr = p;
6455
6456 if (!is_valid_ether_addr(addr->sa_data))
6457 return -EADDRNOTAVAIL;
6458
6459 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6460 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6461
1cdd1ec8
GR		 6462 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6463 IXGBE_RAH_AV);
9a799d71
AK		 6464
6465 return 0;
6466}
6467
6b73e10d
BH		 6468static int
6469ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6470{
6471 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6472 struct ixgbe_hw *hw = &adapter->hw;
6473 u16 value;
6474 int rc;
6475
6476 if (prtad != hw->phy.mdio.prtad)
6477 return -EINVAL;
6478 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6479 if (!rc)
6480 rc = value;
6481 return rc;
6482}
6483
6484static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6485 u16 addr, u16 value)
6486{
6487 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6488 struct ixgbe_hw *hw = &adapter->hw;
6489
6490 if (prtad != hw->phy.mdio.prtad)
6491 return -EINVAL;
6492 return hw->phy.ops.write_reg(hw, addr, devad, value);
6493}
6494
6495static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6496{
6497 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6498
6499 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6500}
6501
0365e6e4
PW		 6502/**
6503 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6504 * netdev->dev_addrs
0365e6e4
PW		 6505 * @netdev: network interface device structure
6506 *
6507 * Returns non-zero on failure
6508 **/
6509static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6510{
6511 int err = 0;
6512 struct ixgbe_adapter *adapter = netdev_priv(dev);
6513 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6514
6515 if (is_valid_ether_addr(mac->san_addr)) {
6516 rtnl_lock();
6517 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6518 rtnl_unlock();
6519 }
6520 return err;
6521}
6522
6523/**
6524 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6525 * netdev->dev_addrs
0365e6e4
PW		 6526 * @netdev: network interface device structure
6527 *
6528 * Returns non-zero on failure
6529 **/
6530static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6531{
6532 int err = 0;
6533 struct ixgbe_adapter *adapter = netdev_priv(dev);
6534 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6535
6536 if (is_valid_ether_addr(mac->san_addr)) {
6537 rtnl_lock();
6538 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6539 rtnl_unlock();
6540 }
6541 return err;
6542}
6543
9a799d71
AK		 6544#ifdef CONFIG_NET_POLL_CONTROLLER
6545/*
6546 * Polling 'interrupt' - used by things like netconsole to send skbs
6547 * without having to re-enable interrupts. It's not called while
6548 * the interrupt routine is executing.
6549 */
6550static void ixgbe_netpoll(struct net_device *netdev)
6551{
6552 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6553 int i;
9a799d71 6554
1a647bd2
AD		 6555 /* if interface is down do nothing */
6556 if (test_bit(__IXGBE_DOWN, &adapter->state))
6557 return;
6558
9a799d71 6559 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6560 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6561 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6562 for (i = 0; i < num_q_vectors; i++) {
6563 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6564 ixgbe_msix_clean_many(0, q_vector);
6565 }
6566 } else {
6567 ixgbe_intr(adapter->pdev->irq, netdev);
6568 }
9a799d71 6569 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6570}
6571#endif
6572
de1036b1
ED		 6573static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6574 struct rtnl_link_stats64 *stats)
6575{
6576 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6577 int i;
6578
6579 /* accurate rx/tx bytes/packets stats */
6580 dev_txq_stats_fold(netdev, stats);
1a51502b 6581 rcu_read_lock();
de1036b1 6582 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6583 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6584 u64 bytes, packets;
6585 unsigned int start;
6586
1a51502b
ED		 6587 if (ring) {
6588 do {
6589 start = u64_stats_fetch_begin_bh(&ring->syncp);
6590 packets = ring->stats.packets;
6591 bytes = ring->stats.bytes;
6592 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6593 stats->rx_packets += packets;
6594 stats->rx_bytes += bytes;
6595 }
de1036b1 6596 }
1a51502b 6597 rcu_read_unlock();
de1036b1
ED		 6598 /* following stats updated by ixgbe_watchdog_task() */
6599 stats->multicast = netdev->stats.multicast;
6600 stats->rx_errors = netdev->stats.rx_errors;
6601 stats->rx_length_errors = netdev->stats.rx_length_errors;
6602 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6603 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6604 return stats;
6605}
6606
6607
0edc3527 6608static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6609 .ndo_open = ixgbe_open,
0edc3527 6610 .ndo_stop = ixgbe_close,
00829823 6611 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6612 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6613 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6614 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6615 .ndo_validate_addr = eth_validate_addr,
6616 .ndo_set_mac_address = ixgbe_set_mac,
6617 .ndo_change_mtu = ixgbe_change_mtu,
6618 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6619 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6620 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6621 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6622 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6623 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6624 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6625 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6626 .ndo_get_stats64 = ixgbe_get_stats64,
0edc3527
SH		 6627#ifdef CONFIG_NET_POLL_CONTROLLER
6628 .ndo_poll_controller = ixgbe_netpoll,
6629#endif
332d4a7d
YZ		 6630#ifdef IXGBE_FCOE
6631 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6632 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6633 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6634 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6635 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6636#endif /* IXGBE_FCOE */
0edc3527
SH		 6637};
6638
1cdd1ec8
GR		 6639static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6640 const struct ixgbe_info *ii)
6641{
6642#ifdef CONFIG_PCI_IOV
6643 struct ixgbe_hw *hw = &adapter->hw;
6644 int err;
6645
6646 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6647 return;
6648
6649 /* The 82599 supports up to 64 VFs per physical function
6650 * but this implementation limits allocation to 63 so that
6651 * basic networking resources are still available to the
6652 * physical function
6653 */
6654 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6655 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6656 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6657 if (err) {
396e799c 6658 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6659 goto err_novfs;
6660 }
6661 /* If call to enable VFs succeeded then allocate memory
6662 * for per VF control structures.
6663 */
6664 adapter->vfinfo =
6665 kcalloc(adapter->num_vfs,
6666 sizeof(struct vf_data_storage), GFP_KERNEL);
6667 if (adapter->vfinfo) {
6668 /* Now that we're sure SR-IOV is enabled
6669 * and memory allocated set up the mailbox parameters
6670 */
6671 ixgbe_init_mbx_params_pf(hw);
6672 memcpy(&hw->mbx.ops, ii->mbx_ops,
6673 sizeof(hw->mbx.ops));
6674
6675 /* Disable RSC when in SR-IOV mode */
6676 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6677 IXGBE_FLAG2_RSC_ENABLED);
6678 return;
6679 }
6680
6681 /* Oh oh */
396e799c
ET		 6682 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6683 "SRIOV disabled\n");
1cdd1ec8
GR		 6684 pci_disable_sriov(adapter->pdev);
6685
6686err_novfs:
6687 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6688 adapter->num_vfs = 0;
6689#endif /* CONFIG_PCI_IOV */
6690}
6691
9a799d71
AK		 6692/**
6693 * ixgbe_probe - Device Initialization Routine
6694 * @pdev: PCI device information struct
6695 * @ent: entry in ixgbe_pci_tbl
6696 *
6697 * Returns 0 on success, negative on failure
6698 *
6699 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6700 * The OS initialization, configuring of the adapter private structure,
6701 * and a hardware reset occur.
6702 **/
6703static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6704 const struct pci_device_id *ent)
9a799d71
AK		 6705{
6706 struct net_device *netdev;
6707 struct ixgbe_adapter *adapter = NULL;
6708 struct ixgbe_hw *hw;
6709 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6710 static int cards_found;
6711 int i, err, pci_using_dac;
c85a2618 6712 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6713#ifdef IXGBE_FCOE
6714 u16 device_caps;
6715#endif
c44ade9e 6716 u32 part_num, eec;
9a799d71 6717
bded64a7
AG		 6718 /* Catch broken hardware that put the wrong VF device ID in
6719 * the PCIe SR-IOV capability.
6720 */
6721 if (pdev->is_virtfn) {
6722 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6723 pci_name(pdev), pdev->vendor, pdev->device);
6724 return -EINVAL;
6725 }
6726
9ce77666 6727 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6728 if (err)
6729 return err;
6730
1b507730
NN		 6731 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6732 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6733 pci_using_dac = 1;
6734 } else {
1b507730 6735 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6736 if (err) {
1b507730
NN		 6737 err = dma_set_coherent_mask(&pdev->dev,
6738 DMA_BIT_MASK(32));
9a799d71 6739 if (err) {
b8bc0421
DC		 6740 dev_err(&pdev->dev,
6741 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6742 goto err_dma;
6743 }
6744 }
6745 pci_using_dac = 0;
6746 }
6747
9ce77666 6748 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 6749 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6750 if (err) {
b8bc0421
DC		 6751 dev_err(&pdev->dev,
6752 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6753 goto err_pci_reg;
6754 }
6755
19d5afd4 6756 pci_enable_pcie_error_reporting(pdev);
6fabd715 6757
9a799d71 6758 pci_set_master(pdev);
fb3b27bc 6759 pci_save_state(pdev);
9a799d71 6760
c85a2618
JF		 6761 if (ii->mac == ixgbe_mac_82598EB)
6762 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6763 else
6764 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6765
6766 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6767#ifdef IXGBE_FCOE
6768 indices += min_t(unsigned int, num_possible_cpus(),
6769 IXGBE_MAX_FCOE_INDICES);
6770#endif
c85a2618 6771 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6772 if (!netdev) {
6773 err = -ENOMEM;
6774 goto err_alloc_etherdev;
6775 }
6776
9a799d71
AK		 6777 SET_NETDEV_DEV(netdev, &pdev->dev);
6778
6779 pci_set_drvdata(pdev, netdev);
6780 adapter = netdev_priv(netdev);
6781
6782 adapter->netdev = netdev;
6783 adapter->pdev = pdev;
6784 hw = &adapter->hw;
6785 hw->back = adapter;
6786 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6787
05857980 6788 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 6789 pci_resource_len(pdev, 0));
9a799d71
AK		 6790 if (!hw->hw_addr) {
6791 err = -EIO;
6792 goto err_ioremap;
6793 }
6794
6795 for (i = 1; i <= 5; i++) {
6796 if (pci_resource_len(pdev, i) == 0)
6797 continue;
6798 }
6799
0edc3527 6800 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6801 ixgbe_set_ethtool_ops(netdev);
9a799d71 6802 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6803 strcpy(netdev->name, pci_name(pdev));
6804
9a799d71
AK		 6805 adapter->bd_number = cards_found;
6806
9a799d71
AK		 6807 /* Setup hw api */
6808 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6809 hw->mac.type = ii->mac;
9a799d71 6810
c44ade9e
JB		 6811 /* EEPROM */
6812 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6813 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6814 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6815 if (!(eec & (1 << 8)))
6816 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6817
6818 /* PHY */
6819 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6820 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6821 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6822 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6823 hw->phy.mdio.mmds = 0;
6824 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6825 hw->phy.mdio.dev = netdev;
6826 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6827 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6828
6829 /* set up this timer and work struct before calling get_invariants
6830 * which might start the timer
6831 */
6832 init_timer(&adapter->sfp_timer);
c061b18d 6833 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 6834 adapter->sfp_timer.data = (unsigned long) adapter;
6835
6836 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6837
e8e26350
PW		 6838 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6839 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6840
6841 /* a new SFP+ module arrival, called from GPI SDP2 context */
6842 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 6843 ixgbe_sfp_config_module_task);
e8e26350 6844
8ca783ab 6845 ii->get_invariants(hw);
9a799d71
AK		 6846
6847 /* setup the private structure */
6848 err = ixgbe_sw_init(adapter);
6849 if (err)
6850 goto err_sw_init;
6851
e86bff0e
DS		 6852 /* Make it possible the adapter to be woken up via WOL */
6853 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6854 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6855
bf069c97
DS		 6856 /*
6857 * If there is a fan on this device and it has failed log the
6858 * failure.
6859 */
6860 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6861 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6862 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6863 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6864 }
6865
c44ade9e 6866 /* reset_hw fills in the perm_addr as well */
119fc60a 6867 hw->phy.reset_if_overtemp = true;
c44ade9e 6868 err = hw->mac.ops.reset_hw(hw);
119fc60a 6869 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6870 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6871 hw->mac.type == ixgbe_mac_82598EB) {
6872 /*
6873 * Start a kernel thread to watch for a module to arrive.
6874 * Only do this for 82598, since 82599 will generate
6875 * interrupts on module arrival.
6876 */
6877 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6878 mod_timer(&adapter->sfp_timer,
6879 round_jiffies(jiffies + (2 * HZ)));
6880 err = 0;
6881 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6882 e_dev_err("failed to initialize because an unsupported SFP+ "
6883 "module type was detected.\n");
6884 e_dev_err("Reload the driver after installing a supported "
6885 "module.\n");
04f165ef
PW		 6886 goto err_sw_init;
6887 } else if (err) {
849c4542 6888 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6889 goto err_sw_init;
6890 }
6891
1cdd1ec8
GR		 6892 ixgbe_probe_vf(adapter, ii);
6893
396e799c 6894 netdev->features = NETIF_F_SG |
e8e9f696
JP		 6895 NETIF_F_IP_CSUM |
6896 NETIF_F_HW_VLAN_TX |
6897 NETIF_F_HW_VLAN_RX |
6898 NETIF_F_HW_VLAN_FILTER;
9a799d71 6899
e9990a9c 6900 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6901 netdev->features |= NETIF_F_TSO;
9a799d71 6902 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6903 netdev->features |= NETIF_F_GRO;
ad31c402 6904
45a5ead0
JB		 6905 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6906 netdev->features |= NETIF_F_SCTP_CSUM;
6907
ad31c402
JK		 6908 netdev->vlan_features |= NETIF_F_TSO;
6909 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6910 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6911 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6912 netdev->vlan_features |= NETIF_F_SG;
6913
1cdd1ec8
GR		 6914 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6915 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6916 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6917 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6918 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6919
7a6b6f51 6920#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6921 netdev->dcbnl_ops = &dcbnl_ops;
6922#endif
6923
eacd73f7 6924#ifdef IXGBE_FCOE
0d551589 6925 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6926 if (hw->mac.ops.get_device_caps) {
6927 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6928 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6929 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6930 }
6931 }
5e09d7f6
YZ		 6932 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6933 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6934 netdev->vlan_features |= NETIF_F_FSO;
6935 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6936 }
eacd73f7 6937#endif /* IXGBE_FCOE */
7b872a55 6938 if (pci_using_dac) {
9a799d71 6939 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6940 netdev->vlan_features |= NETIF_F_HIGHDMA;
6941 }
9a799d71 6942
0c19d6af 6943 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6944 netdev->features |= NETIF_F_LRO;
6945
9a799d71 6946 /* make sure the EEPROM is good */
c44ade9e 6947 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6948 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6949 err = -EIO;
6950 goto err_eeprom;
6951 }
6952
6953 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6954 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6955
c44ade9e 6956 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6957 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6958 err = -EIO;
6959 goto err_eeprom;
6960 }
6961
61fac744
PW		 6962 /* power down the optics */
6963 if (hw->phy.multispeed_fiber)
6964 hw->mac.ops.disable_tx_laser(hw);
6965
9a799d71 6966 init_timer(&adapter->watchdog_timer);
c061b18d 6967 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 6968 adapter->watchdog_timer.data = (unsigned long)adapter;
6969
6970 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6971 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6972
021230d4
AV		 6973 err = ixgbe_init_interrupt_scheme(adapter);
6974 if (err)
6975 goto err_sw_init;
9a799d71 6976
e8e26350
PW		 6977 switch (pdev->device) {
6978 case IXGBE_DEV_ID_82599_KX4:
495dce12 6979 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 6980 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6981 break;
6982 default:
6983 adapter->wol = 0;
6984 break;
6985 }
e8e26350
PW		 6986 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6987
04f165ef
PW		 6988 /* pick up the PCI bus settings for reporting later */
6989 hw->mac.ops.get_bus_info(hw);
6990
9a799d71 6991 /* print bus type/speed/width info */
849c4542 6992 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 6993 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6994 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6995 "Unknown"),
6996 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6997 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6998 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6999 "Unknown"),
7000 netdev->dev_addr);
c44ade9e 7001 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 7002 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 7003 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7004 "PBA No: %06x-%03x\n",
7005 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7006 (part_num >> 8), (part_num & 0xff));
e8e26350 7007 else
849c4542
ET		 7008 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7009 hw->mac.type, hw->phy.type,
7010 (part_num >> 8), (part_num & 0xff));
9a799d71 7011
e8e26350 7012 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7013 e_dev_warn("PCI-Express bandwidth available for this card is "
7014 "not sufficient for optimal performance.\n");
7015 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7016 "is required.\n");
0c254d86
AK		 7017 }
7018
34b0368c
PWJ		 7019 /* save off EEPROM version number */
7020 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7021
9a799d71 7022 /* reset the hardware with the new settings */
794caeb2 7023 err = hw->mac.ops.start_hw(hw);
c44ade9e 7024
794caeb2
PWJ		 7025 if (err == IXGBE_ERR_EEPROM_VERSION) {
7026 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7027 e_dev_warn("This device is a pre-production adapter/LOM. "
7028 "Please be aware there may be issues associated "
7029 "with your hardware. If you are experiencing "
7030 "problems please contact your Intel or hardware "
7031 "representative who provided you with this "
7032 "hardware.\n");
794caeb2 7033 }
9a799d71
AK		 7034 strcpy(netdev->name, "eth%d");
7035 err = register_netdev(netdev);
7036 if (err)
7037 goto err_register;
7038
54386467
JB		 7039 /* carrier off reporting is important to ethtool even BEFORE open */
7040 netif_carrier_off(netdev);
7041
c4cf55e5
PWJ		 7042 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7043 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7044 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7045
119fc60a 7046 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7047 INIT_WORK(&adapter->check_overtemp_task,
7048 ixgbe_check_overtemp_task);
5dd2d332 7049#ifdef CONFIG_IXGBE_DCA
652f093f 7050 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7051 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7052 ixgbe_setup_dca(adapter);
7053 }
7054#endif
1cdd1ec8 7055 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7056 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7057 for (i = 0; i < adapter->num_vfs; i++)
7058 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7059 }
7060
0365e6e4
PW		 7061 /* add san mac addr to netdev */
7062 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7063
849c4542 7064 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7065 cards_found++;
7066 return 0;
7067
7068err_register:
5eba3699 7069 ixgbe_release_hw_control(adapter);
7a921c93 7070 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7071err_sw_init:
7072err_eeprom:
1cdd1ec8
GR		 7073 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7074 ixgbe_disable_sriov(adapter);
c4900be0
DS		 7075 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7076 del_timer_sync(&adapter->sfp_timer);
7077 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7078 cancel_work_sync(&adapter->multispeed_fiber_task);
7079 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 7080 iounmap(hw->hw_addr);
7081err_ioremap:
7082 free_netdev(netdev);
7083err_alloc_etherdev:
e8e9f696
JP		 7084 pci_release_selected_regions(pdev,
7085 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7086err_pci_reg:
7087err_dma:
7088 pci_disable_device(pdev);
7089 return err;
7090}
7091
7092/**
7093 * ixgbe_remove - Device Removal Routine
7094 * @pdev: PCI device information struct
7095 *
7096 * ixgbe_remove is called by the PCI subsystem to alert the driver
7097 * that it should release a PCI device. The could be caused by a
7098 * Hot-Plug event, or because the driver is going to be removed from
7099 * memory.
7100 **/
7101static void __devexit ixgbe_remove(struct pci_dev *pdev)
7102{
7103 struct net_device *netdev = pci_get_drvdata(pdev);
7104 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7105
7106 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 7107 /* clear the module not found bit to make sure the worker won't
7108 * reschedule
7109 */
7110 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 7111 del_timer_sync(&adapter->watchdog_timer);
7112
c4900be0
DS		 7113 del_timer_sync(&adapter->sfp_timer);
7114 cancel_work_sync(&adapter->watchdog_task);
7115 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7116 cancel_work_sync(&adapter->multispeed_fiber_task);
7117 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7118 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7119 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7120 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 7121 flush_scheduled_work();
7122
5dd2d332 7123#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7124 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7125 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7126 dca_remove_requester(&pdev->dev);
7127 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7128 }
7129
7130#endif
332d4a7d
YZ		 7131#ifdef IXGBE_FCOE
7132 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7133 ixgbe_cleanup_fcoe(adapter);
7134
7135#endif /* IXGBE_FCOE */
0365e6e4
PW		 7136
7137 /* remove the added san mac */
7138 ixgbe_del_sanmac_netdev(netdev);
7139
c4900be0
DS		 7140 if (netdev->reg_state == NETREG_REGISTERED)
7141 unregister_netdev(netdev);
9a799d71 7142
1cdd1ec8
GR		 7143 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7144 ixgbe_disable_sriov(adapter);
7145
7a921c93 7146 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7147
021230d4 7148 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7149
7150 iounmap(adapter->hw.hw_addr);
9ce77666 7151 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7152 IORESOURCE_MEM));
9a799d71 7153
849c4542 7154 e_dev_info("complete\n");
021230d4 7155
9a799d71
AK		 7156 free_netdev(netdev);
7157
19d5afd4 7158 pci_disable_pcie_error_reporting(pdev);
6fabd715 7159
9a799d71
AK		 7160 pci_disable_device(pdev);
7161}
7162
7163/**
7164 * ixgbe_io_error_detected - called when PCI error is detected
7165 * @pdev: Pointer to PCI device
7166 * @state: The current pci connection state
7167 *
7168 * This function is called after a PCI bus error affecting
7169 * this device has been detected.
7170 */
7171static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7172 pci_channel_state_t state)
9a799d71
AK		 7173{
7174 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7175 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7176
7177 netif_device_detach(netdev);
7178
3044b8d1
BL		 7179 if (state == pci_channel_io_perm_failure)
7180 return PCI_ERS_RESULT_DISCONNECT;
7181
9a799d71
AK		 7182 if (netif_running(netdev))
7183 ixgbe_down(adapter);
7184 pci_disable_device(pdev);
7185
b4617240 7186 /* Request a slot reset. */
9a799d71
AK		 7187 return PCI_ERS_RESULT_NEED_RESET;
7188}
7189
7190/**
7191 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7192 * @pdev: Pointer to PCI device
7193 *
7194 * Restart the card from scratch, as if from a cold-boot.
7195 */
7196static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7197{
7198 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7199 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 7200 pci_ers_result_t result;
7201 int err;
9a799d71 7202
9ce77666 7203 if (pci_enable_device_mem(pdev)) {
396e799c 7204 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7205 result = PCI_ERS_RESULT_DISCONNECT;
7206 } else {
7207 pci_set_master(pdev);
7208 pci_restore_state(pdev);
c0e1f68b 7209 pci_save_state(pdev);
9a799d71 7210
dd4d8ca6 7211 pci_wake_from_d3(pdev, false);
9a799d71 7212
6fabd715 7213 ixgbe_reset(adapter);
88512539 7214 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7215 result = PCI_ERS_RESULT_RECOVERED;
7216 }
7217
7218 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7219 if (err) {
849c4542
ET		 7220 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7221 "failed 0x%0x\n", err);
6fabd715
PWJ		 7222 /* non-fatal, continue */
7223 }
9a799d71 7224
6fabd715 7225 return result;
9a799d71
AK		 7226}
7227
7228/**
7229 * ixgbe_io_resume - called when traffic can start flowing again.
7230 * @pdev: Pointer to PCI device
7231 *
7232 * This callback is called when the error recovery driver tells us that
7233 * its OK to resume normal operation.
7234 */
7235static void ixgbe_io_resume(struct pci_dev *pdev)
7236{
7237 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7238 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7239
7240 if (netif_running(netdev)) {
7241 if (ixgbe_up(adapter)) {
396e799c 7242 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7243 return;
7244 }
7245 }
7246
7247 netif_device_attach(netdev);
9a799d71
AK		 7248}
7249
7250static struct pci_error_handlers ixgbe_err_handler = {
7251 .error_detected = ixgbe_io_error_detected,
7252 .slot_reset = ixgbe_io_slot_reset,
7253 .resume = ixgbe_io_resume,
7254};
7255
7256static struct pci_driver ixgbe_driver = {
7257 .name = ixgbe_driver_name,
7258 .id_table = ixgbe_pci_tbl,
7259 .probe = ixgbe_probe,
7260 .remove = __devexit_p(ixgbe_remove),
7261#ifdef CONFIG_PM
7262 .suspend = ixgbe_suspend,
7263 .resume = ixgbe_resume,
7264#endif
7265 .shutdown = ixgbe_shutdown,
7266 .err_handler = &ixgbe_err_handler
7267};
7268
7269/**
7270 * ixgbe_init_module - Driver Registration Routine
7271 *
7272 * ixgbe_init_module is the first routine called when the driver is
7273 * loaded. All it does is register with the PCI subsystem.
7274 **/
7275static int __init ixgbe_init_module(void)
7276{
7277 int ret;
c7689578 7278 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7279 pr_info("%s\n", ixgbe_copyright);
9a799d71 7280
5dd2d332 7281#ifdef CONFIG_IXGBE_DCA
bd0362dd 7282 dca_register_notify(&dca_notifier);
bd0362dd 7283#endif
5dd2d332 7284
9a799d71
AK		 7285 ret = pci_register_driver(&ixgbe_driver);
7286 return ret;
7287}
b4617240 7288
9a799d71
AK		 7289module_init(ixgbe_init_module);
7290
7291/**
7292 * ixgbe_exit_module - Driver Exit Cleanup Routine
7293 *
7294 * ixgbe_exit_module is called just before the driver is removed
7295 * from memory.
7296 **/
7297static void __exit ixgbe_exit_module(void)
7298{
5dd2d332 7299#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7300 dca_unregister_notify(&dca_notifier);
7301#endif
9a799d71 7302 pci_unregister_driver(&ixgbe_driver);
1a51502b 7303 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7304}
bd0362dd 7305
5dd2d332 7306#ifdef CONFIG_IXGBE_DCA
bd0362dd 7307static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7308 void *p)
bd0362dd
JC		 7309{
7310 int ret_val;
7311
7312 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7313 __ixgbe_notify_dca);
bd0362dd
JC		 7314
7315 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7316}
b453368d 7317
5dd2d332 7318#endif /* CONFIG_IXGBE_DCA */
849c4542 7319
b453368d 7320/**
849c4542 7321 * ixgbe_get_hw_dev return device
b453368d
AD		 7322 * used by hardware layer to print debugging information
7323 **/
849c4542 7324struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7325{
7326 struct ixgbe_adapter *adapter = hw->back;
849c4542 7327 return adapter->netdev;
b453368d 7328}
bd0362dd 7329
9a799d71
AK		 7330module_exit(ixgbe_exit_module);
7331
7332/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree