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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
1da177e4
LT		 80#include <linux/interrupt.h>
81#include <linux/pci.h>
82#include <linux/mii.h>
83#include <linux/init.h>
84#include <linux/netdevice.h>
85#include <linux/etherdevice.h>
86#include <linux/skbuff.h>
87#include <linux/ethtool.h>
88#include <linux/highmem.h>
89#include <linux/eisa.h>
90#include <linux/bitops.h>
ff5688ae 91#include <linux/jiffies.h>
5a0e3ad6 92#include <linux/gfp.h>
60e4ad7a 93#include <asm/irq.h> /* For nr_irqs only. */
1da177e4
LT		 94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
86de79b6
SH		 105static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
b4adbb4d 238 CH_3C905B_TX,
1da177e4
LT		 239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271/* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
1f1bd5fc 282 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 284 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 286 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 287 {"3c595 Vortex 100baseTx",
1f1bd5fc 288 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 289 {"3c595 Vortex 100baseT4",
1f1bd5fc 290 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 291
292 {"3c595 Vortex 100base-MII",
1f1bd5fc 293 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 294 {"3c900 Boomerang 10baseT",
1f1bd5fc 295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 296 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 300 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 305 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 307 {"3c905 Boomerang 100baseTx",
1f1bd5fc 308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 309 {"3c905 Boomerang 100baseT4",
1f1bd5fc 310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
b4adbb4d
PT		 311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 313 {"3c905B Cyclone 100baseTx",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 315
316 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 318 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 320 {"3c905C Tornado",
1f1bd5fc 321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 324 {"3c980 Cyclone",
aa807f79 325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 326
327 {"3c980C Python-T",
1f1bd5fc 328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 329 {"3cSOHO100-TX Hurricane",
b8a1fcee 330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 331 {"3c555 Laptop Hurricane",
1f1bd5fc 332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 333 {"3c556 Laptop Tornado",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
1f1bd5fc 337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 342 {"3c575 Boomerang CardBus",
1f1bd5fc 343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 344 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 362 {"3c920 Tornado",
1f1bd5fc 363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 364 {"3c982 Hydra Dual Port A",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 366
367 {"3c982 Hydra Dual Port B",
1f1bd5fc 368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 369 {"3c905B-T4",
1f1bd5fc 370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 371 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 373
374 {NULL,}, /* NULL terminated list. */
375};
376
377
a3aa1884 378static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
1da177e4
LT		 379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
b4adbb4d 395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
1da177e4
LT		 396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431/* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
1da177e4
LT		 438#define EL3_CMD 0x0e
439#define EL3_STATUS 0x0e
440
441/* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
446
447enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459/* The SetRxFilter command accepts the following classes: */
460enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463/* Bits in the general status register. */
464enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
471};
472
473/* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
475enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
479};
480enum Window0 {
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
484};
485enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
489};
490/* EEPROM locations. */
491enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497enum Window2 { /* Window 2. */
498 Wn2_ResetOptions=12,
499};
500enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502};
503
504#define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507#define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511#define RAM_SIZE(v) BFEXT(v, 0, 3)
512#define RAM_WIDTH(v) BFEXT(v, 3, 1)
513#define RAM_SPEED(v) BFEXT(v, 4, 2)
514#define ROM_SIZE(v) BFEXT(v, 6, 2)
515#define RAM_SPLIT(v) BFEXT(v, 16, 2)
516#define XCVR(v) BFEXT(v, 20, 4)
517#define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521};
522enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
527};
528enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531};
532/* Boomerang bus master control registers. */
533enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536};
537
538/* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543struct boom_rx_desc {
cc2d6596
AV		 544 __le32 next; /* Last entry points to 0. */
545 __le32 status;
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
1da177e4
LT		 548};
549/* Values for the Rx status entry. */
550enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555};
556
557#ifdef MAX_SKB_FRAGS
558#define DO_ZEROCOPY 1
559#else
560#define DO_ZEROCOPY 0
561#endif
562
563struct boom_tx_desc {
cc2d6596
AV		 564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
1da177e4
LT		 566#if DO_ZEROCOPY
567 struct {
cc2d6596
AV		 568 __le32 addr;
569 __le32 length;
1da177e4
LT		 570 } frag[1+MAX_SKB_FRAGS];
571#else
cc2d6596
AV		 572 __le32 addr;
573 __le32 length;
1da177e4
LT		 574#endif
575};
576
577/* Values for the Tx status entry. */
578enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
582};
583
584/* Chip features we care about in vp->capabilities, read from the EEPROM. */
585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587struct vortex_extra_stats {
8d1d0340
SK		 588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
1da177e4
LT		 593};
594
595struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
1da177e4
LT		 606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
609
610 /* PCI configuration space information. */
611 struct device *gendev;
62afe595
JL		 612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 614
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 625 full_duplex:1, autoselect:1,
1da177e4
LT		 626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
630 has_nway:1,
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 open:1,
634 medialock:1,
635 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
636 large_frames:1; /* accept large frames */
637 int drv_flags;
638 u16 status_enable;
639 u16 intr_enable;
640 u16 available_media; /* From Wn3_Options. */
641 u16 capabilities, info1, info2; /* Various, from EEPROM. */
642 u16 advertising; /* NWay media advertisement */
643 unsigned char phys[2]; /* MII device addresses. */
644 u16 deferred; /* Resend these interrupts when we
645 * bale from the ISR */
646 u16 io_size; /* Size of PCI region (for release_region) */
de847272
BH		 647
648 /* Serialises access to hardware other than MII and variables below.
649 * The lock hierarchy is rtnl_lock > lock > mii_lock > window_lock. */
650 spinlock_t lock;
651
652 spinlock_t mii_lock; /* Serialises access to MII */
653 struct mii_if_info mii; /* MII lib hooks/info */
654 spinlock_t window_lock; /* Serialises access to windowed regs */
655 int window; /* Register window */
1da177e4
LT		 656};
657
a095cfc4
BH		 658static void window_set(struct vortex_private *vp, int window)
659{
660 if (window != vp->window) {
661 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
662 vp->window = window;
663 }
664}
665
666#define DEFINE_WINDOW_IO(size) \
667static u ## size \
668window_read ## size(struct vortex_private *vp, int window, int addr) \
669{ \
de847272
BH		 670 unsigned long flags; \
671 u ## size ret; \
672 spin_lock_irqsave(&vp->window_lock, flags); \
a095cfc4 673 window_set(vp, window); \
de847272
BH		 674 ret = ioread ## size(vp->ioaddr + addr); \
675 spin_unlock_irqrestore(&vp->window_lock, flags); \
676 return ret; \
a095cfc4
BH		 677} \
678static void \
679window_write ## size(struct vortex_private *vp, u ## size value, \
680 int window, int addr) \
681{ \
de847272
BH		 682 unsigned long flags; \
683 spin_lock_irqsave(&vp->window_lock, flags); \
a095cfc4
BH		 684 window_set(vp, window); \
685 iowrite ## size(value, vp->ioaddr + addr); \
de847272 686 spin_unlock_irqrestore(&vp->window_lock, flags); \
a095cfc4
BH		 687}
688DEFINE_WINDOW_IO(8)
689DEFINE_WINDOW_IO(16)
690DEFINE_WINDOW_IO(32)
691
1da177e4
LT		 692#ifdef CONFIG_PCI
693#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
694#else
695#define DEVICE_PCI(dev) NULL
696#endif
697
698#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
699
700#ifdef CONFIG_EISA
701#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
702#else
703#define DEVICE_EISA(dev) NULL
704#endif
705
706#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
707
708/* The action to take with a media selection timer tick.
709 Note that we deviate from the 3Com order by checking 10base2 before AUI.
710 */
711enum xcvr_types {
712 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
713 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
714};
715
f71e1309 716static const struct media_table {
1da177e4
LT		 717 char *name;
718 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
719 mask:8, /* The transceiver-present bit in Wn3_Config.*/
720 next:8; /* The media type to try next. */
721 int wait; /* Time before we check media status. */
722} media_tbl[] = {
723 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
724 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
725 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
726 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
727 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
728 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
729 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
730 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
731 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
732 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
733 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
734};
735
736static struct {
737 const char str[ETH_GSTRING_LEN];
738} ethtool_stats_keys[] = {
739 { "tx_deferred" },
8d1d0340 740 { "tx_max_collisions" },
1da177e4 741 { "tx_multiple_collisions" },
8d1d0340 742 { "tx_single_collisions" },
1da177e4
LT		 743 { "rx_bad_ssd" },
744};
745
746/* number of ETHTOOL_GSTATS u64's */
8d1d0340 747#define VORTEX_NUM_STATS 5
1da177e4 748
62afe595 749static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4 750 int chip_idx, int card_idx);
c8303d10 751static int vortex_up(struct net_device *dev);
1da177e4
LT		 752static void vortex_down(struct net_device *dev, int final);
753static int vortex_open(struct net_device *dev);
a095cfc4 754static void mdio_sync(struct vortex_private *vp, int bits);
1da177e4
LT		 755static int mdio_read(struct net_device *dev, int phy_id, int location);
756static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
757static void vortex_timer(unsigned long arg);
758static void rx_oom_timer(unsigned long arg);
27a1de95
SH		 759static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
760 struct net_device *dev);
761static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
762 struct net_device *dev);
1da177e4
LT		 763static int vortex_rx(struct net_device *dev);
764static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 765static irqreturn_t vortex_interrupt(int irq, void *dev_id);
766static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 767static int vortex_close(struct net_device *dev);
768static void dump_tx_ring(struct net_device *dev);
62afe595 769static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 770static struct net_device_stats *vortex_get_stats(struct net_device *dev);
771static void set_rx_mode(struct net_device *dev);
772#ifdef CONFIG_PCI
773static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
774#endif
775static void vortex_tx_timeout(struct net_device *dev);
776static void acpi_set_WOL(struct net_device *dev);
7282d491 777static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 778static void set_8021q_mode(struct net_device *dev, int enable);
779
1da177e4
LT		 780/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
781/* Option count limit only -- unlimited interfaces are supported. */
782#define MAX_UNITS 8
9954ab7f
JL		 783static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
784static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
785static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
786static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
787static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 788static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 789static int global_options = -1;
790static int global_full_duplex = -1;
791static int global_enable_wol = -1;
900fd17d 792static int global_use_mmio = -1;
1da177e4 793
1da177e4
LT		 794/* Variables to work-around the Compaq PCI BIOS32 problem. */
795static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
796static struct net_device *compaq_net_device;
797
798static int vortex_cards_found;
799
800module_param(debug, int, 0);
801module_param(global_options, int, 0);
802module_param_array(options, int, NULL, 0);
803module_param(global_full_duplex, int, 0);
804module_param_array(full_duplex, int, NULL, 0);
805module_param_array(hw_checksums, int, NULL, 0);
806module_param_array(flow_ctrl, int, NULL, 0);
807module_param(global_enable_wol, int, 0);
808module_param_array(enable_wol, int, NULL, 0);
809module_param(rx_copybreak, int, 0);
810module_param(max_interrupt_work, int, 0);
811module_param(compaq_ioaddr, int, 0);
812module_param(compaq_irq, int, 0);
813module_param(compaq_device_id, int, 0);
814module_param(watchdog, int, 0);
900fd17d
JL		 815module_param(global_use_mmio, int, 0);
816module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 817MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
818MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
819MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
820MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 821MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 822MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
823MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
824MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 825MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 826MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
827MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
828MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
829MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
830MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
831MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 832MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
833MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 834
835#ifdef CONFIG_NET_POLL_CONTROLLER
836static void poll_vortex(struct net_device *dev)
837{
838 struct vortex_private *vp = netdev_priv(dev);
839 unsigned long flags;
0d38ff1d 840 local_irq_save(flags);
7d12e780 841 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 842 local_irq_restore(flags);
6aa20a22 843}
1da177e4
LT		 844#endif
845
846#ifdef CONFIG_PM
847
7bfc4ab5 848static int vortex_suspend(struct device *dev)
1da177e4 849{
7bfc4ab5
AV		 850 struct pci_dev *pdev = to_pci_dev(dev);
851 struct net_device *ndev = pci_get_drvdata(pdev);
852
853 if (!ndev || !netif_running(ndev))
854 return 0;
855
856 netif_device_detach(ndev);
857 vortex_down(ndev, 1);
1da177e4 858
1da177e4
LT		 859 return 0;
860}
861
7bfc4ab5 862static int vortex_resume(struct device *dev)
1da177e4 863{
7bfc4ab5
AV		 864 struct pci_dev *pdev = to_pci_dev(dev);
865 struct net_device *ndev = pci_get_drvdata(pdev);
e1265153 866 int err;
1da177e4 867
7bfc4ab5
AV		 868 if (!ndev || !netif_running(ndev))
869 return 0;
870
871 err = vortex_up(ndev);
872 if (err)
873 return err;
874
875 netif_device_attach(ndev);
876
1da177e4
LT		 877 return 0;
878}
879
47145210 880static const struct dev_pm_ops vortex_pm_ops = {
7bfc4ab5
AV		 881 .suspend = vortex_suspend,
882 .resume = vortex_resume,
883 .freeze = vortex_suspend,
884 .thaw = vortex_resume,
885 .poweroff = vortex_suspend,
886 .restore = vortex_resume,
887};
888
889#define VORTEX_PM_OPS (&vortex_pm_ops)
890
891#else /* !CONFIG_PM */
892
893#define VORTEX_PM_OPS NULL
894
895#endif /* !CONFIG_PM */
1da177e4
LT		 896
897#ifdef CONFIG_EISA
898static struct eisa_device_id vortex_eisa_ids[] = {
899 { "TCM5920", CH_3C592 },
900 { "TCM5970", CH_3C597 },
901 { "" }
902};
07563c71 903MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 904
95c408a9 905static int __init vortex_eisa_probe(struct device *device)
1da177e4 906{
62afe595 907 void __iomem *ioaddr;
1da177e4
LT		 908 struct eisa_device *edev;
909
a880c4cd 910 edev = to_eisa_device(device);
1da177e4 911
62afe595 912 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 913 return -EBUSY;
914
62afe595
JL		 915 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
916
917 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 918 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 919 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 920 return -ENODEV;
921 }
922
923 vortex_cards_found++;
924
925 return 0;
926}
927
95c408a9 928static int __devexit vortex_eisa_remove(struct device *device)
1da177e4
LT		 929{
930 struct eisa_device *edev;
931 struct net_device *dev;
932 struct vortex_private *vp;
62afe595 933 void __iomem *ioaddr;
1da177e4 934
a880c4cd
SK		 935 edev = to_eisa_device(device);
936 dev = eisa_get_drvdata(edev);
1da177e4
LT		 937
938 if (!dev) {
39738e16 939 pr_err("vortex_eisa_remove called for Compaq device!\n");
1da177e4
LT		 940 BUG();
941 }
942
943 vp = netdev_priv(dev);
62afe595 944 ioaddr = vp->ioaddr;
6aa20a22 945
a880c4cd
SK		 946 unregister_netdev(dev);
947 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
948 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 949
a880c4cd 950 free_netdev(dev);
1da177e4
LT		 951 return 0;
952}
95c408a9
RB		 953
954static struct eisa_driver vortex_eisa_driver = {
955 .id_table = vortex_eisa_ids,
956 .driver = {
957 .name = "3c59x",
958 .probe = vortex_eisa_probe,
959 .remove = __devexit_p(vortex_eisa_remove)
960 }
961};
962
963#endif /* CONFIG_EISA */
1da177e4
LT		 964
965/* returns count found (>= 0), or negative on error */
a880c4cd 966static int __init vortex_eisa_init(void)
1da177e4
LT		 967{
968 int eisa_found = 0;
969 int orig_cards_found = vortex_cards_found;
970
971#ifdef CONFIG_EISA
c2f6fabb
BH		 972 int err;
973
974 err = eisa_driver_register (&vortex_eisa_driver);
975 if (!err) {
976 /*
977 * Because of the way EISA bus is probed, we cannot assume
978 * any device have been found when we exit from
979 * eisa_driver_register (the bus root driver may not be
980 * initialized yet). So we blindly assume something was
981 * found, and let the sysfs magic happend...
982 */
983 eisa_found = 1;
1da177e4
LT		 984 }
985#endif
6aa20a22 986
1da177e4
LT		 987 /* Special code to work-around the Compaq PCI BIOS32 problem. */
988 if (compaq_ioaddr) {
62afe595
JL		 989 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
990 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 991 }
992
993 return vortex_cards_found - orig_cards_found + eisa_found;
994}
995
996/* returns count (>= 0), or negative on error */
a880c4cd 997static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 998 const struct pci_device_id *ent)
999{
900fd17d
JL		 1000 int rc, unit, pci_bar;
1001 struct vortex_chip_info *vci;
1002 void __iomem *ioaddr;
1da177e4 1003
6aa20a22 1004 /* wake up and enable device */
a880c4cd 1005 rc = pci_enable_device(pdev);
1da177e4
LT		 1006 if (rc < 0)
1007 goto out;
1008
900fd17d
JL		 1009 unit = vortex_cards_found;
1010
1011 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1012 /* Determine the default if the user didn't override us */
1013 vci = &vortex_info_tbl[ent->driver_data];
1014 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1015 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1016 pci_bar = use_mmio[unit] ? 1 : 0;
1017 else
1018 pci_bar = global_use_mmio ? 1 : 0;
1019
1020 ioaddr = pci_iomap(pdev, pci_bar, 0);
1021 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1022 ioaddr = pci_iomap(pdev, 0, 0);
1023
1024 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1025 ent->driver_data, unit);
1da177e4 1026 if (rc < 0) {
a880c4cd 1027 pci_disable_device(pdev);
1da177e4
LT		 1028 goto out;
1029 }
1030
1031 vortex_cards_found++;
1032
1033out:
1034 return rc;
1035}
1036
48b47a5e
SH		 1037static const struct net_device_ops boomrang_netdev_ops = {
1038 .ndo_open = vortex_open,
1039 .ndo_stop = vortex_close,
1040 .ndo_start_xmit = boomerang_start_xmit,
1041 .ndo_tx_timeout = vortex_tx_timeout,
1042 .ndo_get_stats = vortex_get_stats,
1043#ifdef CONFIG_PCI
1044 .ndo_do_ioctl = vortex_ioctl,
1045#endif
1046 .ndo_set_multicast_list = set_rx_mode,
1047 .ndo_change_mtu = eth_change_mtu,
1048 .ndo_set_mac_address = eth_mac_addr,
1049 .ndo_validate_addr = eth_validate_addr,
1050#ifdef CONFIG_NET_POLL_CONTROLLER
1051 .ndo_poll_controller = poll_vortex,
1052#endif
1053};
1054
1055static const struct net_device_ops vortex_netdev_ops = {
1056 .ndo_open = vortex_open,
1057 .ndo_stop = vortex_close,
1058 .ndo_start_xmit = vortex_start_xmit,
1059 .ndo_tx_timeout = vortex_tx_timeout,
1060 .ndo_get_stats = vortex_get_stats,
1061#ifdef CONFIG_PCI
1062 .ndo_do_ioctl = vortex_ioctl,
1063#endif
1064 .ndo_set_multicast_list = set_rx_mode,
1065 .ndo_change_mtu = eth_change_mtu,
1066 .ndo_set_mac_address = eth_mac_addr,
1067 .ndo_validate_addr = eth_validate_addr,
1068#ifdef CONFIG_NET_POLL_CONTROLLER
1069 .ndo_poll_controller = poll_vortex,
1070#endif
1071};
1072
1da177e4
LT		 1073/*
1074 * Start up the PCI/EISA device which is described by *gendev.
1075 * Return 0 on success.
1076 *
1077 * NOTE: pdev can be NULL, for the case of a Compaq device
1078 */
1079static int __devinit vortex_probe1(struct device *gendev,
62afe595 1080 void __iomem *ioaddr, int irq,
1da177e4
LT		 1081 int chip_idx, int card_idx)
1082{
1083 struct vortex_private *vp;
1084 int option;
1085 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1086 int i, step;
1087 struct net_device *dev;
1088 static int printed_version;
1089 int retval, print_info;
1090 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
361d5ee3 1091 const char *print_name = "3c59x";
1da177e4
LT		 1092 struct pci_dev *pdev = NULL;
1093 struct eisa_device *edev = NULL;
1094
1095 if (!printed_version) {
39738e16 1096 pr_info("%s", version);
1da177e4
LT		 1097 printed_version = 1;
1098 }
1099
1100 if (gendev) {
1101 if ((pdev = DEVICE_PCI(gendev))) {
1102 print_name = pci_name(pdev);
1103 }
1104
1105 if ((edev = DEVICE_EISA(gendev))) {
fb28ad35 1106 print_name = dev_name(&edev->dev);
1da177e4
LT		 1107 }
1108 }
1109
1110 dev = alloc_etherdev(sizeof(*vp));
1111 retval = -ENOMEM;
1112 if (!dev) {
39738e16 1113 pr_err(PFX "unable to allocate etherdev, aborting\n");
1da177e4
LT		 1114 goto out;
1115 }
1da177e4
LT		 1116 SET_NETDEV_DEV(dev, gendev);
1117 vp = netdev_priv(dev);
1118
1119 option = global_options;
1120
1121 /* The lower four bits are the media type. */
1122 if (dev->mem_start) {
1123 /*
1124 * The 'options' param is passed in as the third arg to the
1125 * LILO 'ether=' argument for non-modular use
1126 */
1127 option = dev->mem_start;
1128 }
1129 else if (card_idx < MAX_UNITS) {
1130 if (options[card_idx] >= 0)
1131 option = options[card_idx];
1132 }
1133
1134 if (option > 0) {
1135 if (option & 0x8000)
1136 vortex_debug = 7;
1137 if (option & 0x4000)
1138 vortex_debug = 2;
1139 if (option & 0x0400)
1140 vp->enable_wol = 1;
1141 }
1142
1143 print_info = (vortex_debug > 1);
1144 if (print_info)
39738e16 1145 pr_info("See Documentation/networking/vortex.txt\n");
1da177e4 1146
39738e16 1147 pr_info("%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1148 print_name,
1149 pdev ? "PCI" : "EISA",
1150 vci->name,
1151 ioaddr);
1152
62afe595 1153 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1154 dev->irq = irq;
1155 dev->mtu = mtu;
62afe595 1156 vp->ioaddr = ioaddr;
1da177e4
LT		 1157 vp->large_frames = mtu > 1500;
1158 vp->drv_flags = vci->drv_flags;
1159 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1160 vp->io_size = vci->io_size;
1161 vp->card_idx = card_idx;
a095cfc4 1162 vp->window = -1;
1da177e4
LT		 1163
1164 /* module list only for Compaq device */
1165 if (gendev == NULL) {
1166 compaq_net_device = dev;
1167 }
1168
1169 /* PCI-only startup logic */
1170 if (pdev) {
1171 /* EISA resources already marked, so only PCI needs to do this here */
1172 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1173 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1174 vp->must_free_region = 1;
1175
6aa20a22 1176 /* enable bus-mastering if necessary */
1da177e4 1177 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1178 pci_set_master(pdev);
1da177e4
LT		 1179
1180 if (vci->drv_flags & IS_VORTEX) {
1181 u8 pci_latency;
1182 u8 new_latency = 248;
1183
1184 /* Check the PCI latency value. On the 3c590 series the latency timer
1185 must be set to the maximum value to avoid data corruption that occurs
1186 when the timer expires during a transfer. This bug exists the Vortex
1187 chip only. */
1188 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1189 if (pci_latency < new_latency) {
39738e16 1190 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1da177e4 1191 print_name, pci_latency, new_latency);
39738e16 1192 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1da177e4
LT		 1193 }
1194 }
1195 }
1196
1197 spin_lock_init(&vp->lock);
de847272
BH		 1198 spin_lock_init(&vp->mii_lock);
1199 spin_lock_init(&vp->window_lock);
1da177e4
LT		 1200 vp->gendev = gendev;
1201 vp->mii.dev = dev;
1202 vp->mii.mdio_read = mdio_read;
1203 vp->mii.mdio_write = mdio_write;
1204 vp->mii.phy_id_mask = 0x1f;
1205 vp->mii.reg_num_mask = 0x1f;
1206
1207 /* Makes sure rings are at least 16 byte aligned. */
1208 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1209 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1210 &vp->rx_ring_dma);
1211 retval = -ENOMEM;
cc2d6596 1212 if (!vp->rx_ring)
1da177e4
LT		 1213 goto free_region;
1214
1215 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1216 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1217
1218 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1219 * instead of a module list */
1da177e4
LT		 1220 if (pdev)
1221 pci_set_drvdata(pdev, dev);
1222 if (edev)
a880c4cd 1223 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1224
1225 vp->media_override = 7;
1226 if (option >= 0) {
1227 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1228 if (vp->media_override != 7)
1229 vp->medialock = 1;
1230 vp->full_duplex = (option & 0x200) ? 1 : 0;
1231 vp->bus_master = (option & 16) ? 1 : 0;
1232 }
1233
1234 if (global_full_duplex > 0)
1235 vp->full_duplex = 1;
1236 if (global_enable_wol > 0)
1237 vp->enable_wol = 1;
1238
1239 if (card_idx < MAX_UNITS) {
1240 if (full_duplex[card_idx] > 0)
1241 vp->full_duplex = 1;
1242 if (flow_ctrl[card_idx] > 0)
1243 vp->flow_ctrl = 1;
1244 if (enable_wol[card_idx] > 0)
1245 vp->enable_wol = 1;
1246 }
1247
125d5ce8 1248 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1249 vp->options = option;
1250 /* Read the station address from the EEPROM. */
1da177e4
LT		 1251 {
1252 int base;
1253
1254 if (vci->drv_flags & EEPROM_8BIT)
1255 base = 0x230;
1256 else if (vci->drv_flags & EEPROM_OFFSET)
1257 base = EEPROM_Read + 0x30;
1258 else
1259 base = EEPROM_Read;
1260
1261 for (i = 0; i < 0x40; i++) {
1262 int timer;
a095cfc4 1263 window_write16(vp, base + i, 0, Wn0EepromCmd);
1da177e4
LT		 1264 /* Pause for at least 162 us. for the read to take place. */
1265 for (timer = 10; timer >= 0; timer--) {
1266 udelay(162);
a095cfc4
BH		 1267 if ((window_read16(vp, 0, Wn0EepromCmd) &
1268 0x8000) == 0)
1da177e4
LT		 1269 break;
1270 }
a095cfc4 1271 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1da177e4
LT		 1272 }
1273 }
1274 for (i = 0; i < 0x18; i++)
1275 checksum ^= eeprom[i];
1276 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1277 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1278 while (i < 0x21)
1279 checksum ^= eeprom[i++];
1280 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1281 }
1282 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
39738e16 1283 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1da177e4 1284 for (i = 0; i < 3; i++)
cc2d6596 1285 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1286 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
0795af57 1287 if (print_info)
39738e16 1288 pr_cont(" %pM", dev->dev_addr);
1da177e4
LT		 1289 /* Unfortunately an all zero eeprom passes the checksum and this
1290 gets found in the wild in failure cases. Crypto is hard 8) */
1291 if (!is_valid_ether_addr(dev->dev_addr)) {
1292 retval = -EINVAL;
39738e16 1293 pr_err("*** EEPROM MAC address is invalid.\n");
1da177e4
LT		 1294 goto free_ring; /* With every pack */
1295 }
1da177e4 1296 for (i = 0; i < 6; i++)
a095cfc4 1297 window_write8(vp, dev->dev_addr[i], 2, i);
1da177e4 1298
1da177e4 1299 if (print_info)
39738e16 1300 pr_cont(", IRQ %d\n", dev->irq);
1da177e4 1301 /* Tell them about an invalid IRQ. */
60e4ad7a 1302 if (dev->irq <= 0 || dev->irq >= nr_irqs)
39738e16 1303 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1da177e4 1304 dev->irq);
1da177e4 1305
a095cfc4 1306 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1da177e4 1307 if (print_info) {
39738e16
AB		 1308 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1309 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1da177e4
LT		 1310 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1311 }
1312
1313
1314 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1315 unsigned short n;
1316
62afe595
JL		 1317 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1318 if (!vp->cb_fn_base) {
1da177e4 1319 retval = -ENOMEM;
62afe595 1320 goto free_ring;
1da177e4 1321 }
62afe595 1322
1da177e4 1323 if (print_info) {
39738e16 1324 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
7c7459d1
GKH		 1325 print_name,
1326 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1327 vp->cb_fn_base);
1da177e4 1328 }
1da177e4 1329
a095cfc4 1330 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1331 if (vp->drv_flags & INVERT_LED_PWR)
1332 n |= 0x10;
1333 if (vp->drv_flags & INVERT_MII_PWR)
1334 n |= 0x4000;
a095cfc4 1335 window_write16(vp, n, 2, Wn2_ResetOptions);
1da177e4 1336 if (vp->drv_flags & WNO_XCVR_PWR) {
a095cfc4 1337 window_write16(vp, 0x0800, 0, 0);
1da177e4
LT		 1338 }
1339 }
1340
1341 /* Extract our information from the EEPROM data. */
1342 vp->info1 = eeprom[13];
1343 vp->info2 = eeprom[15];
1344 vp->capabilities = eeprom[16];
1345
1346 if (vp->info1 & 0x8000) {
1347 vp->full_duplex = 1;
1348 if (print_info)
39738e16 1349 pr_info("Full duplex capable\n");
1da177e4
LT		 1350 }
1351
1352 {
f71e1309 1353 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4 1354 unsigned int config;
a095cfc4 1355 vp->available_media = window_read16(vp, 3, Wn3_Options);
1da177e4
LT		 1356 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1357 vp->available_media = 0x40;
a095cfc4 1358 config = window_read32(vp, 3, Wn3_Config);
1da177e4 1359 if (print_info) {
39738e16 1360 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
a095cfc4 1361 config, window_read16(vp, 3, Wn3_Options));
39738e16 1362 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1da177e4
LT		 1363 8 << RAM_SIZE(config),
1364 RAM_WIDTH(config) ? "word" : "byte",
1365 ram_split[RAM_SPLIT(config)],
1366 AUTOSELECT(config) ? "autoselect/" : "",
1367 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1368 media_tbl[XCVR(config)].name);
1369 }
1370 vp->default_media = XCVR(config);
1371 if (vp->default_media == XCVR_NWAY)
1372 vp->has_nway = 1;
1373 vp->autoselect = AUTOSELECT(config);
1374 }
1375
1376 if (vp->media_override != 7) {
39738e16 1377 pr_info("%s: Media override to transceiver type %d (%s).\n",
1da177e4
LT		 1378 print_name, vp->media_override,
1379 media_tbl[vp->media_override].name);
1380 dev->if_port = vp->media_override;
1381 } else
1382 dev->if_port = vp->default_media;
1383
1384 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1385 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1386 int phy, phy_idx = 0;
1da177e4
LT		 1387 mii_preamble_required++;
1388 if (vp->drv_flags & EXTRA_PREAMBLE)
1389 mii_preamble_required++;
1390 mdio_sync(ioaddr, 32);
106427e6 1391 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1392 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1393 int mii_status, phyx;
1394
1395 /*
1396 * For the 3c905CX we look at index 24 first, because it bogusly
1397 * reports an external PHY at all indices
1398 */
1399 if (phy == 0)
1400 phyx = 24;
1401 else if (phy <= 24)
1402 phyx = phy - 1;
1403 else
1404 phyx = phy;
106427e6 1405 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1406 if (mii_status && mii_status != 0xffff) {
1407 vp->phys[phy_idx++] = phyx;
1408 if (print_info) {
39738e16
AB		 1409 pr_info(" MII transceiver found at address %d, status %4x.\n",
1410 phyx, mii_status);
1da177e4
LT		 1411 }
1412 if ((mii_status & 0x0040) == 0)
1413 mii_preamble_required++;
1414 }
1415 }
1416 mii_preamble_required--;
1417 if (phy_idx == 0) {
39738e16 1418 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1da177e4
LT		 1419 vp->phys[0] = 24;
1420 } else {
106427e6 1421 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1422 if (vp->full_duplex) {
1423 /* Only advertise the FD media types. */
1424 vp->advertising &= ~0x02A0;
1425 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1426 }
1427 }
1428 vp->mii.phy_id = vp->phys[0];
1429 }
1430
1431 if (vp->capabilities & CapBusMaster) {
1432 vp->full_bus_master_tx = 1;
1433 if (print_info) {
39738e16 1434 pr_info(" Enabling bus-master transmits and %s receives.\n",
1da177e4
LT		 1435 (vp->info2 & 1) ? "early" : "whole-frame" );
1436 }
1437 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1438 vp->bus_master = 0; /* AKPM: vortex only */
1439 }
1440
1441 /* The 3c59x-specific entries in the device structure. */
1da177e4 1442 if (vp->full_bus_master_tx) {
48b47a5e 1443 dev->netdev_ops = &boomrang_netdev_ops;
1da177e4 1444 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1445 if (card_idx < MAX_UNITS &&
1446 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1447 hw_checksums[card_idx] == 1)) {
d311b0d3 1448 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4 1449 }
48b47a5e
SH		 1450 } else
1451 dev->netdev_ops = &vortex_netdev_ops;
1da177e4
LT		 1452
1453 if (print_info) {
39738e16 1454 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1da177e4
LT		 1455 print_name,
1456 (dev->features & NETIF_F_SG) ? "en":"dis",
1457 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1458 }
1459
1da177e4 1460 dev->ethtool_ops = &vortex_ethtool_ops;
1da177e4 1461 dev->watchdog_timeo = (watchdog * HZ) / 1000;
48b47a5e 1462
1da177e4
LT		 1463 if (pdev) {
1464 vp->pm_state_valid = 1;
1465 pci_save_state(VORTEX_PCI(vp));
1466 acpi_set_WOL(dev);
1467 }
1468 retval = register_netdev(dev);
1469 if (retval == 0)
1470 return 0;
1471
1472free_ring:
1473 pci_free_consistent(pdev,
1474 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1475 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1476 vp->rx_ring,
1477 vp->rx_ring_dma);
1478free_region:
1479 if (vp->must_free_region)
62afe595 1480 release_region(dev->base_addr, vci->io_size);
1da177e4 1481 free_netdev(dev);
39738e16 1482 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1da177e4
LT		 1483out:
1484 return retval;
1485}
1486
1487static void
1488issue_and_wait(struct net_device *dev, int cmd)
1489{
62afe595
JL		 1490 struct vortex_private *vp = netdev_priv(dev);
1491 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1492 int i;
1493
62afe595 1494 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1495 for (i = 0; i < 2000; i++) {
62afe595 1496 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1497 return;
1498 }
1499
1500 /* OK, that didn't work. Do it the slow way. One second */
1501 for (i = 0; i < 100000; i++) {
62afe595 1502 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4 1503 if (vortex_debug > 1)
39738e16 1504 pr_info("%s: command 0x%04x took %d usecs\n",
1da177e4
LT		 1505 dev->name, cmd, i * 10);
1506 return;
1507 }
1508 udelay(10);
1509 }
39738e16 1510 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1511 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1512}
1513
125d5ce8
SK		 1514static void
1515vortex_set_duplex(struct net_device *dev)
1516{
1517 struct vortex_private *vp = netdev_priv(dev);
125d5ce8 1518
39738e16 1519 pr_info("%s: setting %s-duplex.\n",
125d5ce8
SK		 1520 dev->name, (vp->full_duplex) ? "full" : "half");
1521
125d5ce8 1522 /* Set the full-duplex bit. */
a095cfc4
BH		 1523 window_write16(vp,
1524 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1525 (vp->large_frames ? 0x40 : 0) |
1526 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1527 0x100 : 0),
1528 3, Wn3_MAC_Ctrl);
125d5ce8
SK		 1529}
1530
1531static void vortex_check_media(struct net_device *dev, unsigned int init)
1532{
1533 struct vortex_private *vp = netdev_priv(dev);
1534 unsigned int ok_to_print = 0;
1535
1536 if (vortex_debug > 3)
1537 ok_to_print = 1;
1538
1539 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1540 vp->full_duplex = vp->mii.full_duplex;
1541 vortex_set_duplex(dev);
1542 } else if (init) {
1543 vortex_set_duplex(dev);
1544 }
1545}
1546
c8303d10 1547static int
1da177e4
LT		 1548vortex_up(struct net_device *dev)
1549{
1da177e4 1550 struct vortex_private *vp = netdev_priv(dev);
62afe595 1551 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1552 unsigned int config;
0280f9f9 1553 int i, mii_reg1, mii_reg5, err = 0;
1da177e4
LT		 1554
1555 if (VORTEX_PCI(vp)) {
1556 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1557 if (vp->pm_state_valid)
1558 pci_restore_state(VORTEX_PCI(vp));
c8303d10
MH		 1559 err = pci_enable_device(VORTEX_PCI(vp));
1560 if (err) {
39738e16 1561 pr_warning("%s: Could not enable device\n",
c8303d10
MH		 1562 dev->name);
1563 goto err_out;
1564 }
1da177e4
LT		 1565 }
1566
1567 /* Before initializing select the active media port. */
a095cfc4 1568 config = window_read32(vp, 3, Wn3_Config);
1da177e4
LT		 1569
1570 if (vp->media_override != 7) {
39738e16 1571 pr_info("%s: Media override to transceiver %d (%s).\n",
1da177e4
LT		 1572 dev->name, vp->media_override,
1573 media_tbl[vp->media_override].name);
1574 dev->if_port = vp->media_override;
1575 } else if (vp->autoselect) {
1576 if (vp->has_nway) {
1577 if (vortex_debug > 1)
39738e16 1578 pr_info("%s: using NWAY device table, not %d\n",
1da177e4
LT		 1579 dev->name, dev->if_port);
1580 dev->if_port = XCVR_NWAY;
1581 } else {
1582 /* Find first available media type, starting with 100baseTx. */
1583 dev->if_port = XCVR_100baseTx;
1584 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1585 dev->if_port = media_tbl[dev->if_port].next;
1586 if (vortex_debug > 1)
39738e16 1587 pr_info("%s: first available media type: %s\n",
1da177e4
LT		 1588 dev->name, media_tbl[dev->if_port].name);
1589 }
1590 } else {
1591 dev->if_port = vp->default_media;
1592 if (vortex_debug > 1)
39738e16 1593 pr_info("%s: using default media %s\n",
1da177e4
LT		 1594 dev->name, media_tbl[dev->if_port].name);
1595 }
1596
1597 init_timer(&vp->timer);
1598 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1599 vp->timer.data = (unsigned long)dev;
1600 vp->timer.function = vortex_timer; /* timer handler */
1601 add_timer(&vp->timer);
1602
1603 init_timer(&vp->rx_oom_timer);
1604 vp->rx_oom_timer.data = (unsigned long)dev;
1605 vp->rx_oom_timer.function = rx_oom_timer;
1606
1607 if (vortex_debug > 1)
39738e16 1608 pr_debug("%s: Initial media type %s.\n",
1da177e4
LT		 1609 dev->name, media_tbl[dev->if_port].name);
1610
125d5ce8 1611 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1612 config = BFINS(config, dev->if_port, 20, 4);
1613 if (vortex_debug > 6)
39738e16 1614 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
a095cfc4 1615 window_write32(vp, config, 3, Wn3_Config);
1da177e4
LT		 1616
1617 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
09ce3512
SK		 1618 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1619 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1620 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
373492d0 1621 vp->mii.full_duplex = vp->full_duplex;
09ce3512 1622
125d5ce8 1623 vortex_check_media(dev, 1);
1da177e4 1624 }
125d5ce8
SK		 1625 else
1626 vortex_set_duplex(dev);
1da177e4 1627
09ce3512
SK		 1628 issue_and_wait(dev, TxReset);
1629 /*
1630 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1631 */
1632 issue_and_wait(dev, RxReset|0x04);
1633
1da177e4 1634
62afe595 1635 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1636
1637 if (vortex_debug > 1) {
39738e16 1638 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
a095cfc4 1639 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1da177e4
LT		 1640 }
1641
1642 /* Set the station address and mask in window 2 each time opened. */
1da177e4 1643 for (i = 0; i < 6; i++)
a095cfc4 1644 window_write8(vp, dev->dev_addr[i], 2, i);
1da177e4 1645 for (; i < 12; i+=2)
a095cfc4 1646 window_write16(vp, 0, 2, i);
1da177e4
LT		 1647
1648 if (vp->cb_fn_base) {
a095cfc4 1649 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1650 if (vp->drv_flags & INVERT_LED_PWR)
1651 n |= 0x10;
1652 if (vp->drv_flags & INVERT_MII_PWR)
1653 n |= 0x4000;
a095cfc4 1654 window_write16(vp, n, 2, Wn2_ResetOptions);
1da177e4
LT		 1655 }
1656
1657 if (dev->if_port == XCVR_10base2)
1658 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1659 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4 1660 if (dev->if_port != XCVR_NWAY) {
a095cfc4
BH		 1661 window_write16(vp,
1662 (window_read16(vp, 4, Wn4_Media) &
1663 ~(Media_10TP|Media_SQE)) |
1664 media_tbl[dev->if_port].media_bits,
1665 4, Wn4_Media);
1da177e4
LT		 1666 }
1667
1668 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1669 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4 1670 for (i = 0; i < 10; i++)
a095cfc4
BH		 1671 window_read8(vp, 6, i);
1672 window_read16(vp, 6, 10);
1673 window_read16(vp, 6, 12);
1da177e4 1674 /* New: On the Vortex we must also clear the BadSSD counter. */
a095cfc4 1675 window_read8(vp, 4, 12);
1da177e4 1676 /* ..and on the Boomerang we enable the extra statistics bits. */
a095cfc4 1677 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1da177e4
LT		 1678
1679 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1680 vp->cur_rx = vp->dirty_rx = 0;
1681 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1682 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1683 iowrite32(0x0020, ioaddr + PktStatus);
1684 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1685 }
1686 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1687 vp->cur_tx = vp->dirty_tx = 0;
1688 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1689 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1690 /* Clear the Rx, Tx rings. */
1691 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1692 vp->rx_ring[i].status = 0;
1693 for (i = 0; i < TX_RING_SIZE; i++)
1694 vp->tx_skbuff[i] = NULL;
62afe595 1695 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1696 }
1697 /* Set receiver mode: presumably accept b-case and phys addr only. */
1698 set_rx_mode(dev);
1699 /* enable 802.1q tagged frames */
1700 set_8021q_mode(dev, 1);
62afe595 1701 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1702
62afe595
JL		 1703 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1704 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1705 /* Allow status bits to be seen. */
1706 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1707 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1708 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1709 (vp->bus_master ? DMADone : 0);
1710 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1711 (vp->full_bus_master_rx ? 0 : RxComplete) |
1712 StatsFull | HostError | TxComplete | IntReq
1713 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1714 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1715 /* Ack all pending events, and set active indicator mask. */
62afe595 1716 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1717 ioaddr + EL3_CMD);
62afe595 1718 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1719 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1720 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 1721 netif_start_queue (dev);
c8303d10
MH		 1722err_out:
1723 return err;
1da177e4
LT		 1724}
1725
1726static int
1727vortex_open(struct net_device *dev)
1728{
1729 struct vortex_private *vp = netdev_priv(dev);
1730 int i;
1731 int retval;
1732
1733 /* Use the now-standard shared IRQ implementation. */
1734 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1735 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
39738e16 1736 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
c8303d10 1737 goto err;
1da177e4
LT		 1738 }
1739
1740 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1741 if (vortex_debug > 2)
39738e16 1742 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1da177e4
LT		 1743 for (i = 0; i < RX_RING_SIZE; i++) {
1744 struct sk_buff *skb;
1745 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1746 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1747 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
9a5d3414
SH		 1748
1749 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1750 GFP_KERNEL);
1da177e4
LT		 1751 vp->rx_skbuff[i] = skb;
1752 if (skb == NULL)
1753 break; /* Bad news! */
9a5d3414
SH		 1754
1755 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
689be439 1756 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1757 }
1758 if (i != RX_RING_SIZE) {
1759 int j;
39738e16 1760 pr_emerg("%s: no memory for rx ring\n", dev->name);
1da177e4
LT		 1761 for (j = 0; j < i; j++) {
1762 if (vp->rx_skbuff[j]) {
1763 dev_kfree_skb(vp->rx_skbuff[j]);
1764 vp->rx_skbuff[j] = NULL;
1765 }
1766 }
1767 retval = -ENOMEM;
c8303d10 1768 goto err_free_irq;
1da177e4
LT		 1769 }
1770 /* Wrap the ring. */
1771 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1772 }
1773
c8303d10
MH		 1774 retval = vortex_up(dev);
1775 if (!retval)
1776 goto out;
1da177e4 1777
c8303d10 1778err_free_irq:
1da177e4 1779 free_irq(dev->irq, dev);
c8303d10 1780err:
1da177e4 1781 if (vortex_debug > 1)
39738e16 1782 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
c8303d10 1783out:
1da177e4
LT		 1784 return retval;
1785}
1786
1787static void
1788vortex_timer(unsigned long data)
1789{
1790 struct net_device *dev = (struct net_device *)data;
1791 struct vortex_private *vp = netdev_priv(dev);
62afe595 1792 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1793 int next_tick = 60*HZ;
1794 int ok = 0;
a095cfc4 1795 int media_status;
1da177e4
LT		 1796
1797 if (vortex_debug > 2) {
39738e16 1798 pr_debug("%s: Media selection timer tick happened, %s.\n",
1da177e4 1799 dev->name, media_tbl[dev->if_port].name);
39738e16 1800 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1da177e4
LT		 1801 }
1802
a095cfc4 1803 media_status = window_read16(vp, 4, Wn4_Media);
1da177e4
LT		 1804 switch (dev->if_port) {
1805 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1806 if (media_status & Media_LnkBeat) {
1807 netif_carrier_on(dev);
1808 ok = 1;
1809 if (vortex_debug > 1)
39738e16 1810 pr_debug("%s: Media %s has link beat, %x.\n",
1da177e4
LT		 1811 dev->name, media_tbl[dev->if_port].name, media_status);
1812 } else {
1813 netif_carrier_off(dev);
1814 if (vortex_debug > 1) {
39738e16 1815 pr_debug("%s: Media %s has no link beat, %x.\n",
1da177e4
LT		 1816 dev->name, media_tbl[dev->if_port].name, media_status);
1817 }
1818 }
1819 break;
1820 case XCVR_MII: case XCVR_NWAY:
1821 {
1da177e4 1822 ok = 1;
125d5ce8 1823 vortex_check_media(dev, 0);
1da177e4
LT		 1824 }
1825 break;
1826 default: /* Other media types handled by Tx timeouts. */
1827 if (vortex_debug > 1)
39738e16 1828 pr_debug("%s: Media %s has no indication, %x.\n",
1da177e4
LT		 1829 dev->name, media_tbl[dev->if_port].name, media_status);
1830 ok = 1;
1831 }
b4ff6450
SK		 1832
1833 if (!netif_carrier_ok(dev))
1834 next_tick = 5*HZ;
1835
e94d10eb
SK		 1836 if (vp->medialock)
1837 goto leave_media_alone;
1838
a880c4cd 1839 if (!ok) {
1da177e4
LT		 1840 unsigned int config;
1841
de847272
BH		 1842 spin_lock_irq(&vp->lock);
1843
1da177e4
LT		 1844 do {
1845 dev->if_port = media_tbl[dev->if_port].next;
1846 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1847 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1848 dev->if_port = vp->default_media;
1849 if (vortex_debug > 1)
39738e16 1850 pr_debug("%s: Media selection failing, using default %s port.\n",
1da177e4
LT		 1851 dev->name, media_tbl[dev->if_port].name);
1852 } else {
1853 if (vortex_debug > 1)
39738e16 1854 pr_debug("%s: Media selection failed, now trying %s port.\n",
1da177e4
LT		 1855 dev->name, media_tbl[dev->if_port].name);
1856 next_tick = media_tbl[dev->if_port].wait;
1857 }
a095cfc4
BH		 1858 window_write16(vp,
1859 (media_status & ~(Media_10TP|Media_SQE)) |
1860 media_tbl[dev->if_port].media_bits,
1861 4, Wn4_Media);
1da177e4 1862
a095cfc4 1863 config = window_read32(vp, 3, Wn3_Config);
1da177e4 1864 config = BFINS(config, dev->if_port, 20, 4);
a095cfc4 1865 window_write32(vp, config, 3, Wn3_Config);
1da177e4 1866
62afe595 1867 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1868 ioaddr + EL3_CMD);
1869 if (vortex_debug > 1)
39738e16 1870 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1da177e4 1871 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
de847272
BH		 1872
1873 spin_unlock_irq(&vp->lock);
1da177e4 1874 }
1da177e4
LT		 1875
1876leave_media_alone:
1877 if (vortex_debug > 2)
39738e16 1878 pr_debug("%s: Media selection timer finished, %s.\n",
1da177e4
LT		 1879 dev->name, media_tbl[dev->if_port].name);
1880
1881 mod_timer(&vp->timer, RUN_AT(next_tick));
1882 if (vp->deferred)
62afe595 1883 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1884}
1885
1886static void vortex_tx_timeout(struct net_device *dev)
1887{
1888 struct vortex_private *vp = netdev_priv(dev);
62afe595 1889 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1890
39738e16 1891 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1892 dev->name, ioread8(ioaddr + TxStatus),
1893 ioread16(ioaddr + EL3_STATUS));
39738e16 1894 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
a095cfc4
BH		 1895 window_read16(vp, 4, Wn4_NetDiag),
1896 window_read16(vp, 4, Wn4_Media),
62afe595 1897 ioread32(ioaddr + PktStatus),
a095cfc4 1898 window_read16(vp, 4, Wn4_FIFODiag));
1da177e4 1899 /* Slight code bloat to be user friendly. */
62afe595 1900 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
39738e16 1901 pr_err("%s: Transmitter encountered 16 collisions --"
1da177e4 1902 " network cable problem?\n", dev->name);
62afe595 1903 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
39738e16 1904 pr_err("%s: Interrupt posted but not delivered --"
1da177e4
LT		 1905 " IRQ blocked by another device?\n", dev->name);
1906 /* Bad idea here.. but we might as well handle a few events. */
1907 {
1908 /*
1909 * Block interrupts because vortex_interrupt does a bare spin_lock()
1910 */
1911 unsigned long flags;
1912 local_irq_save(flags);
1913 if (vp->full_bus_master_tx)
7d12e780 1914 boomerang_interrupt(dev->irq, dev);
1da177e4 1915 else
7d12e780 1916 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1917 local_irq_restore(flags);
1918 }
1919 }
1920
1921 if (vortex_debug > 0)
1922 dump_tx_ring(dev);
1923
1924 issue_and_wait(dev, TxReset);
1925
1daad055 1926 dev->stats.tx_errors++;
1da177e4 1927 if (vp->full_bus_master_tx) {
39738e16 1928 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1929 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1930 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1931 ioaddr + DownListPtr);
1932 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1933 netif_wake_queue (dev);
1934 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1935 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1936 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 1937 } else {
1daad055 1938 dev->stats.tx_dropped++;
1da177e4
LT		 1939 netif_wake_queue(dev);
1940 }
6aa20a22 1941
1da177e4 1942 /* Issue Tx Enable */
62afe595 1943 iowrite16(TxEnable, ioaddr + EL3_CMD);
1ae5dc34 1944 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 1945}
1946
1947/*
1948 * Handle uncommon interrupt sources. This is a separate routine to minimize
1949 * the cache impact.
1950 */
1951static void
1952vortex_error(struct net_device *dev, int status)
1953{
1954 struct vortex_private *vp = netdev_priv(dev);
62afe595 1955 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1956 int do_tx_reset = 0, reset_mask = 0;
1957 unsigned char tx_status = 0;
1958
1959 if (vortex_debug > 2) {
39738e16 1960 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1da177e4
LT		 1961 }
1962
1963 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1964 tx_status = ioread8(ioaddr + TxStatus);
1da177e4 1965 /* Presumably a tx-timeout. We must merely re-enable. */
8e95a202
JP		 1966 if (vortex_debug > 2 ||
1967 (tx_status != 0x88 && vortex_debug > 0)) {
39738e16 1968 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1da177e4
LT		 1969 dev->name, tx_status);
1970 if (tx_status == 0x82) {
39738e16 1971 pr_err("Probably a duplex mismatch. See "
1da177e4
LT		 1972 "Documentation/networking/vortex.txt\n");
1973 }
1974 dump_tx_ring(dev);
1975 }
1daad055
PZ		 1976 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1977 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
0000754c 1978 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1979 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1980 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1981 do_tx_reset = 1;
0000754c
AM		 1982 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1983 do_tx_reset = 1;
1984 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1985 } else { /* Merely re-enable the transmitter. */
62afe595 1986 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1987 }
1988 }
1989
1990 if (status & RxEarly) { /* Rx early is unused. */
1991 vortex_rx(dev);
62afe595 1992 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1993 }
1994 if (status & StatsFull) { /* Empty statistics. */
1995 static int DoneDidThat;
1996 if (vortex_debug > 4)
39738e16 1997 pr_debug("%s: Updating stats.\n", dev->name);
1da177e4
LT		 1998 update_stats(ioaddr, dev);
1999 /* HACK: Disable statistics as an interrupt source. */
2000 /* This occurs when we have the wrong media type! */
2001 if (DoneDidThat == 0 &&
62afe595 2002 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
39738e16 2003 pr_warning("%s: Updating statistics failed, disabling "
1da177e4 2004 "stats as an interrupt source.\n", dev->name);
a095cfc4
BH		 2005 iowrite16(SetIntrEnb |
2006 (window_read16(vp, 5, 10) & ~StatsFull),
2007 ioaddr + EL3_CMD);
1da177e4 2008 vp->intr_enable &= ~StatsFull;
1da177e4
LT		 2009 DoneDidThat++;
2010 }
2011 }
2012 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 2013 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2014 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 2015 }
2016 if (status & HostError) {
2017 u16 fifo_diag;
a095cfc4 2018 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
39738e16 2019 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
1da177e4
LT		 2020 dev->name, fifo_diag);
2021 /* Adapter failure requires Tx/Rx reset and reinit. */
2022 if (vp->full_bus_master_tx) {
62afe595 2023 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2024 /* 0x80000000 PCI master abort. */
2025 /* 0x40000000 PCI target abort. */
2026 if (vortex_debug)
39738e16 2027 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1da177e4
LT		 2028
2029 /* In this case, blow the card away */
2030 /* Must not enter D3 or we can't legally issue the reset! */
2031 vortex_down(dev, 0);
2032 issue_and_wait(dev, TotalReset | 0xff);
2033 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2034 } else if (fifo_diag & 0x0400)
2035 do_tx_reset = 1;
2036 if (fifo_diag & 0x3000) {
2037 /* Reset Rx fifo and upload logic */
2038 issue_and_wait(dev, RxReset|0x07);
2039 /* Set the Rx filter to the current state. */
2040 set_rx_mode(dev);
2041 /* enable 802.1q VLAN tagged frames */
2042 set_8021q_mode(dev, 1);
62afe595
JL		 2043 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2044 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2045 }
2046 }
2047
2048 if (do_tx_reset) {
2049 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2050 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2051 if (!vp->full_bus_master_tx)
2052 netif_wake_queue(dev);
2053 }
2054}
2055
27a1de95 2056static netdev_tx_t
1da177e4
LT		 2057vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2058{
2059 struct vortex_private *vp = netdev_priv(dev);
62afe595 2060 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2061
2062 /* Put out the doubleword header... */
62afe595 2063 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2064 if (vp->bus_master) {
2065 /* Set the bus-master controller to transfer the packet. */
2066 int len = (skb->len + 3) & ~3;
a095cfc4
BH		 2067 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2068 PCI_DMA_TODEVICE);
de847272 2069 spin_lock_irq(&vp->window_lock);
a095cfc4
BH		 2070 window_set(vp, 7);
2071 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
62afe595 2072 iowrite16(len, ioaddr + Wn7_MasterLen);
de847272 2073 spin_unlock_irq(&vp->window_lock);
1da177e4 2074 vp->tx_skb = skb;
62afe595 2075 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2076 /* netif_wake_queue() will be called at the DMADone interrupt. */
2077 } else {
2078 /* ... and the packet rounded to a doubleword. */
62afe595 2079 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2080 dev_kfree_skb (skb);
62afe595 2081 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2082 netif_start_queue (dev); /* AKPM: redundant? */
2083 } else {
2084 /* Interrupt us when the FIFO has room for max-sized packet. */
2085 netif_stop_queue(dev);
62afe595 2086 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2087 }
2088 }
2089
1da177e4
LT		 2090
2091 /* Clear the Tx status stack. */
2092 {
2093 int tx_status;
2094 int i = 32;
2095
62afe595 2096 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2097 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2098 if (vortex_debug > 2)
39738e16 2099 pr_debug("%s: Tx error, status %2.2x.\n",
1da177e4 2100 dev->name, tx_status);
1daad055
PZ		 2101 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2102 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1da177e4
LT		 2103 if (tx_status & 0x30) {
2104 issue_and_wait(dev, TxReset);
2105 }
62afe595 2106 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2107 }
62afe595 2108 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2109 }
2110 }
6ed10654 2111 return NETDEV_TX_OK;
1da177e4
LT		 2112}
2113
27a1de95 2114static netdev_tx_t
1da177e4
LT		 2115boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2116{
2117 struct vortex_private *vp = netdev_priv(dev);
62afe595 2118 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2119 /* Calculate the next Tx descriptor entry. */
2120 int entry = vp->cur_tx % TX_RING_SIZE;
2121 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2122 unsigned long flags;
2123
2124 if (vortex_debug > 6) {
39738e16
AB		 2125 pr_debug("boomerang_start_xmit()\n");
2126 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
0f667ff5 2127 dev->name, vp->cur_tx);
1da177e4
LT		 2128 }
2129
2130 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2131 if (vortex_debug > 0)
39738e16 2132 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
1da177e4
LT		 2133 dev->name);
2134 netif_stop_queue(dev);
5b548140 2135 return NETDEV_TX_BUSY;
1da177e4
LT		 2136 }
2137
2138 vp->tx_skbuff[entry] = skb;
2139
2140 vp->tx_ring[entry].next = 0;
2141#if DO_ZEROCOPY
84fa7933 2142 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2143 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2144 else
2145 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2146
2147 if (!skb_shinfo(skb)->nr_frags) {
2148 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2149 skb->len, PCI_DMA_TODEVICE));
2150 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2151 } else {
2152 int i;
2153
2154 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
e743d313
ED		 2155 skb_headlen(skb), PCI_DMA_TODEVICE));
2156 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
1da177e4
LT		 2157
2158 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2159 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2160
2161 vp->tx_ring[entry].frag[i+1].addr =
2162 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2163 (void*)page_address(frag->page) + frag->page_offset,
2164 frag->size, PCI_DMA_TODEVICE));
2165
2166 if (i == skb_shinfo(skb)->nr_frags-1)
2167 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2168 else
2169 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2170 }
2171 }
2172#else
2173 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2174 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2175 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2176#endif
2177
2178 spin_lock_irqsave(&vp->lock, flags);
2179 /* Wait for the stall to complete. */
2180 issue_and_wait(dev, DownStall);
2181 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2182 if (ioread32(ioaddr + DownListPtr) == 0) {
2183 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2184 vp->queued_packet++;
2185 }
2186
2187 vp->cur_tx++;
2188 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2189 netif_stop_queue (dev);
2190 } else { /* Clear previous interrupt enable. */
2191#if defined(tx_interrupt_mitigation)
2192 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2193 * were selected, this would corrupt DN_COMPLETE. No?
2194 */
2195 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2196#endif
2197 }
62afe595 2198 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 2199 spin_unlock_irqrestore(&vp->lock, flags);
6ed10654 2200 return NETDEV_TX_OK;
1da177e4
LT		 2201}
2202
2203/* The interrupt handler does all of the Rx thread work and cleans up
2204 after the Tx thread. */
2205
2206/*
2207 * This is the ISR for the vortex series chips.
2208 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2209 */
2210
2211static irqreturn_t
7d12e780 2212vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2213{
2214 struct net_device *dev = dev_id;
2215 struct vortex_private *vp = netdev_priv(dev);
62afe595 2216 void __iomem *ioaddr;
1da177e4
LT		 2217 int status;
2218 int work_done = max_interrupt_work;
2219 int handled = 0;
2220
62afe595 2221 ioaddr = vp->ioaddr;
1da177e4
LT		 2222 spin_lock(&vp->lock);
2223
62afe595 2224 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2225
2226 if (vortex_debug > 6)
39738e16 2227 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
1da177e4
LT		 2228
2229 if ((status & IntLatch) == 0)
2230 goto handler_exit; /* No interrupt: shared IRQs cause this */
2231 handled = 1;
2232
2233 if (status & IntReq) {
2234 status |= vp->deferred;
2235 vp->deferred = 0;
2236 }
2237
2238 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2239 goto handler_exit;
2240
2241 if (vortex_debug > 4)
39738e16 2242 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2243 dev->name, status, ioread8(ioaddr + Timer));
1da177e4 2244
de847272 2245 spin_lock(&vp->window_lock);
a095cfc4
BH		 2246 window_set(vp, 7);
2247
1da177e4
LT		 2248 do {
2249 if (vortex_debug > 5)
39738e16 2250 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2251 dev->name, status);
2252 if (status & RxComplete)
2253 vortex_rx(dev);
2254
2255 if (status & TxAvailable) {
2256 if (vortex_debug > 5)
39738e16 2257 pr_debug(" TX room bit was handled.\n");
1da177e4 2258 /* There's room in the FIFO for a full-sized packet. */
62afe595 2259 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2260 netif_wake_queue (dev);
2261 }
2262
2263 if (status & DMADone) {
62afe595
JL		 2264 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2265 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2266 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2267 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2268 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2269 /*
2270 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2271 * insufficient FIFO room, the TxAvailable test will succeed and call
2272 * netif_wake_queue()
2273 */
2274 netif_wake_queue(dev);
2275 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2276 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2277 netif_stop_queue(dev);
2278 }
2279 }
2280 }
2281 /* Check for all uncommon interrupts at once. */
2282 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2283 if (status == 0xffff)
2284 break;
2285 vortex_error(dev, status);
2286 }
2287
2288 if (--work_done < 0) {
39738e16
AB		 2289 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2290 dev->name, status);
1da177e4
LT		 2291 /* Disable all pending interrupts. */
2292 do {
2293 vp->deferred |= status;
62afe595 2294 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2295 ioaddr + EL3_CMD);
62afe595
JL		 2296 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2297 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2298 /* The timer will reenable interrupts. */
2299 mod_timer(&vp->timer, jiffies + 1*HZ);
2300 break;
2301 }
2302 /* Acknowledge the IRQ. */
62afe595
JL		 2303 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2304 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4 2305
de847272
BH		 2306 spin_unlock(&vp->window_lock);
2307
1da177e4 2308 if (vortex_debug > 4)
39738e16 2309 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2310 dev->name, status);
2311handler_exit:
2312 spin_unlock(&vp->lock);
2313 return IRQ_RETVAL(handled);
2314}
2315
2316/*
2317 * This is the ISR for the boomerang series chips.
2318 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2319 */
2320
2321static irqreturn_t
7d12e780 2322boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2323{
2324 struct net_device *dev = dev_id;
2325 struct vortex_private *vp = netdev_priv(dev);
62afe595 2326 void __iomem *ioaddr;
1da177e4
LT		 2327 int status;
2328 int work_done = max_interrupt_work;
2329
62afe595 2330 ioaddr = vp->ioaddr;
1da177e4
LT		 2331
2332 /*
2333 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2334 * and boomerang_start_xmit
2335 */
2336 spin_lock(&vp->lock);
2337
62afe595 2338 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2339
2340 if (vortex_debug > 6)
39738e16 2341 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
1da177e4
LT		 2342
2343 if ((status & IntLatch) == 0)
2344 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2345
2346 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2347 if (vortex_debug > 1)
39738e16 2348 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
1da177e4
LT		 2349 goto handler_exit;
2350 }
2351
2352 if (status & IntReq) {
2353 status |= vp->deferred;
2354 vp->deferred = 0;
2355 }
2356
2357 if (vortex_debug > 4)
39738e16 2358 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2359 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2360 do {
2361 if (vortex_debug > 5)
39738e16 2362 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2363 dev->name, status);
2364 if (status & UpComplete) {
62afe595 2365 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4 2366 if (vortex_debug > 5)
39738e16 2367 pr_debug("boomerang_interrupt->boomerang_rx\n");
1da177e4
LT		 2368 boomerang_rx(dev);
2369 }
2370
2371 if (status & DownComplete) {
2372 unsigned int dirty_tx = vp->dirty_tx;
2373
62afe595 2374 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2375 while (vp->cur_tx - dirty_tx > 0) {
2376 int entry = dirty_tx % TX_RING_SIZE;
2377#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2378 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2379 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2380 break; /* It still hasn't been processed. */
2381#else
2382 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2383 break; /* It still hasn't been processed. */
2384#endif
6aa20a22 2385
1da177e4
LT		 2386 if (vp->tx_skbuff[entry]) {
2387 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2388#if DO_ZEROCOPY
1da177e4
LT		 2389 int i;
2390 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2391 pci_unmap_single(VORTEX_PCI(vp),
2392 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2393 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2394 PCI_DMA_TODEVICE);
2395#else
2396 pci_unmap_single(VORTEX_PCI(vp),
2397 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2398#endif
2399 dev_kfree_skb_irq(skb);
2400 vp->tx_skbuff[entry] = NULL;
2401 } else {
39738e16 2402 pr_debug("boomerang_interrupt: no skb!\n");
1da177e4 2403 }
1daad055 2404 /* dev->stats.tx_packets++; Counted below. */
1da177e4
LT		 2405 dirty_tx++;
2406 }
2407 vp->dirty_tx = dirty_tx;
2408 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2409 if (vortex_debug > 6)
39738e16 2410 pr_debug("boomerang_interrupt: wake queue\n");
1da177e4
LT		 2411 netif_wake_queue (dev);
2412 }
2413 }
2414
2415 /* Check for all uncommon interrupts at once. */
2416 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2417 vortex_error(dev, status);
2418
2419 if (--work_done < 0) {
39738e16
AB		 2420 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2421 dev->name, status);
1da177e4
LT		 2422 /* Disable all pending interrupts. */
2423 do {
2424 vp->deferred |= status;
62afe595 2425 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2426 ioaddr + EL3_CMD);
62afe595
JL		 2427 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2428 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2429 /* The timer will reenable interrupts. */
2430 mod_timer(&vp->timer, jiffies + 1*HZ);
2431 break;
2432 }
2433 /* Acknowledge the IRQ. */
62afe595 2434 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2435 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2436 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2437
62afe595 2438 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2439
2440 if (vortex_debug > 4)
39738e16 2441 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2442 dev->name, status);
2443handler_exit:
2444 spin_unlock(&vp->lock);
2445 return IRQ_HANDLED;
2446}
2447
2448static int vortex_rx(struct net_device *dev)
2449{
2450 struct vortex_private *vp = netdev_priv(dev);
62afe595 2451 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2452 int i;
2453 short rx_status;
2454
2455 if (vortex_debug > 5)
39738e16 2456 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2457 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2458 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2459 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2460 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4 2461 if (vortex_debug > 2)
39738e16 2462 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2463 dev->stats.rx_errors++;
2464 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2465 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2466 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2467 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2468 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2469 } else {
2470 /* The packet length: up to 4.5K!. */
2471 int pkt_len = rx_status & 0x1fff;
2472 struct sk_buff *skb;
2473
2474 skb = dev_alloc_skb(pkt_len + 5);
2475 if (vortex_debug > 4)
39738e16 2476 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2477 pkt_len, rx_status);
2478 if (skb != NULL) {
1da177e4
LT		 2479 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2480 /* 'skb_put()' points to the start of sk_buff data area. */
2481 if (vp->bus_master &&
62afe595 2482 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2483 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2484 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2485 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2486 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2487 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2488 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2489 ;
2490 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2491 } else {
62afe595
JL		 2492 ioread32_rep(ioaddr + RX_FIFO,
2493 skb_put(skb, pkt_len),
2494 (pkt_len + 3) >> 2);
1da177e4 2495 }
62afe595 2496 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2497 skb->protocol = eth_type_trans(skb, dev);
2498 netif_rx(skb);
1daad055 2499 dev->stats.rx_packets++;
1da177e4
LT		 2500 /* Wait a limited time to go to next packet. */
2501 for (i = 200; i >= 0; i--)
62afe595 2502 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2503 break;
2504 continue;
2505 } else if (vortex_debug > 0)
39738e16
AB		 2506 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2507 dev->name, pkt_len);
1daad055 2508 dev->stats.rx_dropped++;
1da177e4 2509 }
1da177e4
LT		 2510 issue_and_wait(dev, RxDiscard);
2511 }
2512
2513 return 0;
2514}
2515
2516static int
2517boomerang_rx(struct net_device *dev)
2518{
2519 struct vortex_private *vp = netdev_priv(dev);
2520 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2521 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2522 int rx_status;
2523 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2524
2525 if (vortex_debug > 5)
39738e16 2526 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2527
2528 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2529 if (--rx_work_limit < 0)
2530 break;
2531 if (rx_status & RxDError) { /* Error, update stats. */
2532 unsigned char rx_error = rx_status >> 16;
2533 if (vortex_debug > 2)
39738e16 2534 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2535 dev->stats.rx_errors++;
2536 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2537 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2538 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2539 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2540 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2541 } else {
2542 /* The packet length: up to 4.5K!. */
2543 int pkt_len = rx_status & 0x1fff;
2544 struct sk_buff *skb;
2545 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2546
2547 if (vortex_debug > 4)
39738e16 2548 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2549 pkt_len, rx_status);
2550
2551 /* Check if the packet is long enough to just accept without
2552 copying to a properly sized skbuff. */
cc2d6596 2553 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 2554 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2555 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2556 /* 'skb_put()' points to the start of sk_buff data area. */
2557 memcpy(skb_put(skb, pkt_len),
689be439 2558 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2559 pkt_len);
2560 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2561 vp->rx_copy++;
2562 } else {
2563 /* Pass up the skbuff already on the Rx ring. */
2564 skb = vp->rx_skbuff[entry];
2565 vp->rx_skbuff[entry] = NULL;
2566 skb_put(skb, pkt_len);
2567 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2568 vp->rx_nocopy++;
2569 }
2570 skb->protocol = eth_type_trans(skb, dev);
2571 { /* Use hardware checksum info. */
2572 int csum_bits = rx_status & 0xee000000;
2573 if (csum_bits &&
2574 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2575 csum_bits == (IPChksumValid | UDPChksumValid))) {
2576 skb->ip_summed = CHECKSUM_UNNECESSARY;
2577 vp->rx_csumhits++;
2578 }
2579 }
2580 netif_rx(skb);
1daad055 2581 dev->stats.rx_packets++;
1da177e4
LT		 2582 }
2583 entry = (++vp->cur_rx) % RX_RING_SIZE;
2584 }
2585 /* Refill the Rx ring buffers. */
2586 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2587 struct sk_buff *skb;
2588 entry = vp->dirty_rx % RX_RING_SIZE;
2589 if (vp->rx_skbuff[entry] == NULL) {
89d71a66 2590 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
1da177e4
LT		 2591 if (skb == NULL) {
2592 static unsigned long last_jif;
ff5688ae 2593 if (time_after(jiffies, last_jif + 10 * HZ)) {
39738e16 2594 pr_warning("%s: memory shortage\n", dev->name);
1da177e4
LT		 2595 last_jif = jiffies;
2596 }
2597 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2598 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2599 break; /* Bad news! */
2600 }
9a5d3414 2601
689be439 2602 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2603 vp->rx_skbuff[entry] = skb;
2604 }
2605 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2606 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2607 }
2608 return 0;
2609}
2610
2611/*
2612 * If we've hit a total OOM refilling the Rx ring we poll once a second
2613 * for some memory. Otherwise there is no way to restart the rx process.
2614 */
2615static void
2616rx_oom_timer(unsigned long arg)
2617{
2618 struct net_device *dev = (struct net_device *)arg;
2619 struct vortex_private *vp = netdev_priv(dev);
2620
2621 spin_lock_irq(&vp->lock);
2622 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2623 boomerang_rx(dev);
2624 if (vortex_debug > 1) {
39738e16 2625 pr_debug("%s: rx_oom_timer %s\n", dev->name,
1da177e4
LT		 2626 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2627 }
2628 spin_unlock_irq(&vp->lock);
2629}
2630
2631static void
2632vortex_down(struct net_device *dev, int final_down)
2633{
2634 struct vortex_private *vp = netdev_priv(dev);
62afe595 2635 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2636
2637 netif_stop_queue (dev);
2638
2639 del_timer_sync(&vp->rx_oom_timer);
2640 del_timer_sync(&vp->timer);
2641
1daad055 2642 /* Turn off statistics ASAP. We update dev->stats below. */
62afe595 2643 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2644
2645 /* Disable the receiver and transmitter. */
62afe595
JL		 2646 iowrite16(RxDisable, ioaddr + EL3_CMD);
2647 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2648
2649 /* Disable receiving 802.1q tagged frames */
2650 set_8021q_mode(dev, 0);
2651
2652 if (dev->if_port == XCVR_10base2)
2653 /* Turn off thinnet power. Green! */
62afe595 2654 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2655
62afe595 2656 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2657
2658 update_stats(ioaddr, dev);
2659 if (vp->full_bus_master_rx)
62afe595 2660 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2661 if (vp->full_bus_master_tx)
62afe595 2662 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2663
2664 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2665 vp->pm_state_valid = 1;
1da177e4
LT		 2666 pci_save_state(VORTEX_PCI(vp));
2667 acpi_set_WOL(dev);
2668 }
2669}
2670
2671static int
2672vortex_close(struct net_device *dev)
2673{
2674 struct vortex_private *vp = netdev_priv(dev);
62afe595 2675 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2676 int i;
2677
2678 if (netif_device_present(dev))
2679 vortex_down(dev, 1);
2680
2681 if (vortex_debug > 1) {
39738e16 2682 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2683 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
39738e16 2684 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
1da177e4
LT		 2685 " tx_queued %d Rx pre-checksummed %d.\n",
2686 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2687 }
2688
2689#if DO_ZEROCOPY
32fb5f06
JL		 2690 if (vp->rx_csumhits &&
2691 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2692 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
39738e16 2693 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
1da177e4
LT		 2694 }
2695#endif
6aa20a22 2696
1da177e4
LT		 2697 free_irq(dev->irq, dev);
2698
2699 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2700 for (i = 0; i < RX_RING_SIZE; i++)
2701 if (vp->rx_skbuff[i]) {
2702 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2703 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2704 dev_kfree_skb(vp->rx_skbuff[i]);
2705 vp->rx_skbuff[i] = NULL;
2706 }
2707 }
2708 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2709 for (i = 0; i < TX_RING_SIZE; i++) {
2710 if (vp->tx_skbuff[i]) {
2711 struct sk_buff *skb = vp->tx_skbuff[i];
2712#if DO_ZEROCOPY
2713 int k;
2714
2715 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2716 pci_unmap_single(VORTEX_PCI(vp),
2717 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2718 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2719 PCI_DMA_TODEVICE);
2720#else
2721 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2722#endif
2723 dev_kfree_skb(skb);
2724 vp->tx_skbuff[i] = NULL;
2725 }
2726 }
2727 }
2728
2729 return 0;
2730}
2731
2732static void
2733dump_tx_ring(struct net_device *dev)
2734{
2735 if (vortex_debug > 0) {
2736 struct vortex_private *vp = netdev_priv(dev);
62afe595 2737 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2738
1da177e4
LT		 2739 if (vp->full_bus_master_tx) {
2740 int i;
62afe595 2741 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4 2742
39738e16 2743 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
1da177e4
LT		 2744 vp->full_bus_master_tx,
2745 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2746 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
39738e16 2747 pr_err(" Transmit list %8.8x vs. %p.\n",
62afe595 2748 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2749 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2750 issue_and_wait(dev, DownStall);
2751 for (i = 0; i < TX_RING_SIZE; i++) {
0cb13536
JD		 2752 unsigned int length;
2753
1da177e4 2754#if DO_ZEROCOPY
0cb13536 2755 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
1da177e4 2756#else
0cb13536 2757 length = le32_to_cpu(vp->tx_ring[i].length);
1da177e4 2758#endif
0cb13536
JD		 2759 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2760 i, &vp->tx_ring[i], length,
1da177e4
LT		 2761 le32_to_cpu(vp->tx_ring[i].status));
2762 }
2763 if (!stalled)
62afe595 2764 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2765 }
2766 }
2767}
2768
2769static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2770{
2771 struct vortex_private *vp = netdev_priv(dev);
62afe595 2772 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2773 unsigned long flags;
2774
2775 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2776 spin_lock_irqsave (&vp->lock, flags);
62afe595 2777 update_stats(ioaddr, dev);
1da177e4
LT		 2778 spin_unlock_irqrestore (&vp->lock, flags);
2779 }
1daad055 2780 return &dev->stats;
1da177e4
LT		 2781}
2782
2783/* Update statistics.
2784 Unlike with the EL3 we need not worry about interrupts changing
2785 the window setting from underneath us, but we must still guard
2786 against a race condition with a StatsUpdate interrupt updating the
2787 table. This is done by checking that the ASM (!) code generated uses
2788 atomic updates with '+='.
2789 */
62afe595 2790static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2791{
2792 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2793
1da177e4
LT		 2794 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2795 /* Switch to the stats window, and read everything. */
a095cfc4
BH		 2796 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2797 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2798 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2799 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2800 dev->stats.tx_packets += window_read8(vp, 6, 6);
2801 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2802 0x30) << 4;
2803 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
1da177e4
LT		 2804 /* Don't bother with register 9, an extension of registers 6&7.
2805 If we do use the 6&7 values the atomic update assumption above
2806 is invalid. */
a095cfc4
BH		 2807 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2808 dev->stats.tx_bytes += window_read16(vp, 6, 12);
1da177e4 2809 /* Extra stats for get_ethtool_stats() */
a095cfc4
BH		 2810 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2811 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2812 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2813 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
1da177e4 2814
1daad055 2815 dev->stats.collisions = vp->xstats.tx_multiple_collisions
8d1d0340
SK		 2816 + vp->xstats.tx_single_collisions
2817 + vp->xstats.tx_max_collisions;
2818
1da177e4 2819 {
a095cfc4 2820 u8 up = window_read8(vp, 4, 13);
1daad055
PZ		 2821 dev->stats.rx_bytes += (up & 0x0f) << 16;
2822 dev->stats.tx_bytes += (up & 0xf0) << 12;
1da177e4 2823 }
1da177e4
LT		 2824}
2825
2826static int vortex_nway_reset(struct net_device *dev)
2827{
2828 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2829
de847272 2830 return mii_nway_restart(&vp->mii);
1da177e4
LT		 2831}
2832
1da177e4
LT		 2833static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2834{
2835 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2836
de847272 2837 return mii_ethtool_gset(&vp->mii, cmd);
1da177e4
LT		 2838}
2839
2840static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2841{
2842 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2843
de847272 2844 return mii_ethtool_sset(&vp->mii, cmd);
1da177e4
LT		 2845}
2846
2847static u32 vortex_get_msglevel(struct net_device *dev)
2848{
2849 return vortex_debug;
2850}
2851
2852static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2853{
2854 vortex_debug = dbg;
2855}
2856
b9f2c044 2857static int vortex_get_sset_count(struct net_device *dev, int sset)
1da177e4 2858{
b9f2c044
JG		 2859 switch (sset) {
2860 case ETH_SS_STATS:
2861 return VORTEX_NUM_STATS;
2862 default:
2863 return -EOPNOTSUPP;
2864 }
1da177e4
LT		 2865}
2866
2867static void vortex_get_ethtool_stats(struct net_device *dev,
2868 struct ethtool_stats *stats, u64 *data)
2869{
2870 struct vortex_private *vp = netdev_priv(dev);
62afe595 2871 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2872 unsigned long flags;
2873
2874 spin_lock_irqsave(&vp->lock, flags);
62afe595 2875 update_stats(ioaddr, dev);
1da177e4
LT		 2876 spin_unlock_irqrestore(&vp->lock, flags);
2877
2878 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2879 data[1] = vp->xstats.tx_max_collisions;
2880 data[2] = vp->xstats.tx_multiple_collisions;
2881 data[3] = vp->xstats.tx_single_collisions;
2882 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2883}
2884
2885
2886static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2887{
2888 switch (stringset) {
2889 case ETH_SS_STATS:
2890 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2891 break;
2892 default:
2893 WARN_ON(1);
2894 break;
2895 }
2896}
2897
2898static void vortex_get_drvinfo(struct net_device *dev,
2899 struct ethtool_drvinfo *info)
2900{
2901 struct vortex_private *vp = netdev_priv(dev);
2902
2903 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2904 if (VORTEX_PCI(vp)) {
2905 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2906 } else {
2907 if (VORTEX_EISA(vp))
86de79b6 2908 strcpy(info->bus_info, dev_name(vp->gendev));
1da177e4
LT		 2909 else
2910 sprintf(info->bus_info, "EISA 0x%lx %d",
2911 dev->base_addr, dev->irq);
2912 }
2913}
2914
7282d491 2915static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2916 .get_drvinfo = vortex_get_drvinfo,
2917 .get_strings = vortex_get_strings,
2918 .get_msglevel = vortex_get_msglevel,
2919 .set_msglevel = vortex_set_msglevel,
2920 .get_ethtool_stats = vortex_get_ethtool_stats,
b9f2c044 2921 .get_sset_count = vortex_get_sset_count,
1da177e4
LT		 2922 .get_settings = vortex_get_settings,
2923 .set_settings = vortex_set_settings,
373a6887 2924 .get_link = ethtool_op_get_link,
1da177e4
LT		 2925 .nway_reset = vortex_nway_reset,
2926};
2927
2928#ifdef CONFIG_PCI
2929/*
2930 * Must power the device up to do MDIO operations
2931 */
2932static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2933{
2934 int err;
2935 struct vortex_private *vp = netdev_priv(dev);
1da177e4 2936 unsigned long flags;
cc2d6596 2937 pci_power_t state = 0;
1da177e4
LT		 2938
2939 if(VORTEX_PCI(vp))
2940 state = VORTEX_PCI(vp)->current_state;
2941
2942 /* The kernel core really should have pci_get_power_state() */
2943
2944 if(state != 0)
2945 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2946 spin_lock_irqsave(&vp->lock, flags);
1da177e4
LT		 2947 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2948 spin_unlock_irqrestore(&vp->lock, flags);
2949 if(state != 0)
2950 pci_set_power_state(VORTEX_PCI(vp), state);
2951
2952 return err;
2953}
2954#endif
2955
2956
2957/* Pre-Cyclone chips have no documented multicast filter, so the only
2958 multicast setting is to receive all multicast frames. At least
2959 the chip has a very clean way to set the mode, unlike many others. */
2960static void set_rx_mode(struct net_device *dev)
2961{
62afe595
JL		 2962 struct vortex_private *vp = netdev_priv(dev);
2963 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2964 int new_mode;
2965
2966 if (dev->flags & IFF_PROMISC) {
d5b20697 2967 if (vortex_debug > 3)
39738e16 2968 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
1da177e4 2969 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
59ce25d9 2970 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2971 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2972 } else
2973 new_mode = SetRxFilter | RxStation | RxBroadcast;
2974
62afe595 2975 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2976}
2977
2978#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2979/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2980 Note that this must be done after each RxReset due to some backwards
2981 compatibility logic in the Cyclone and Tornado ASICs */
2982
2983/* The Ethernet Type used for 802.1q tagged frames */
2984#define VLAN_ETHER_TYPE 0x8100
2985
2986static void set_8021q_mode(struct net_device *dev, int enable)
2987{
2988 struct vortex_private *vp = netdev_priv(dev);
1da177e4
LT		 2989 int mac_ctrl;
2990
2991 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2992 /* cyclone and tornado chipsets can recognize 802.1q
2993 * tagged frames and treat them correctly */
2994
2995 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2996 if (enable)
2997 max_pkt_size += 4; /* 802.1Q VLAN tag */
2998
a095cfc4 2999 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
1da177e4
LT		 3000
3001 /* set VlanEtherType to let the hardware checksumming
3002 treat tagged frames correctly */
a095cfc4 3003 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
1da177e4
LT		 3004 } else {
3005 /* on older cards we have to enable large frames */
3006
3007 vp->large_frames = dev->mtu > 1500 || enable;
3008
a095cfc4 3009 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
1da177e4
LT		 3010 if (vp->large_frames)
3011 mac_ctrl |= 0x40;
3012 else
3013 mac_ctrl &= ~0x40;
a095cfc4 3014 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
1da177e4 3015 }
1da177e4
LT		 3016}
3017#else
3018
3019static void set_8021q_mode(struct net_device *dev, int enable)
3020{
3021}
3022
3023
3024#endif
3025
3026/* MII transceiver control section.
3027 Read and write the MII registers using software-generated serial
3028 MDIO protocol. See the MII specifications or DP83840A data sheet
3029 for details. */
3030
3031/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3032 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3033 "overclocking" issues. */
a095cfc4
BH		 3034static void mdio_delay(struct vortex_private *vp)
3035{
3036 window_read32(vp, 4, Wn4_PhysicalMgmt);
3037}
1da177e4
LT		 3038
3039#define MDIO_SHIFT_CLK 0x01
3040#define MDIO_DIR_WRITE 0x04
3041#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3042#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3043#define MDIO_DATA_READ 0x02
3044#define MDIO_ENB_IN 0x00
3045
3046/* Generate the preamble required for initial synchronization and
3047 a few older transceivers. */
a095cfc4 3048static void mdio_sync(struct vortex_private *vp, int bits)
1da177e4 3049{
1da177e4
LT		 3050 /* Establish sync by sending at least 32 logic ones. */
3051 while (-- bits >= 0) {
a095cfc4
BH		 3052 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3053 mdio_delay(vp);
3054 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3055 4, Wn4_PhysicalMgmt);
3056 mdio_delay(vp);
1da177e4
LT		 3057 }
3058}
3059
3060static int mdio_read(struct net_device *dev, int phy_id, int location)
3061{
3062 int i;
62afe595 3063 struct vortex_private *vp = netdev_priv(dev);
1da177e4
LT		 3064 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3065 unsigned int retval = 0;
1da177e4 3066
de847272
BH		 3067 spin_lock_bh(&vp->mii_lock);
3068
1da177e4 3069 if (mii_preamble_required)
a095cfc4 3070 mdio_sync(vp, 32);
1da177e4
LT		 3071
3072 /* Shift the read command bits out. */
3073 for (i = 14; i >= 0; i--) {
3074 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
a095cfc4
BH		 3075 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3076 mdio_delay(vp);
3077 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3078 4, Wn4_PhysicalMgmt);
3079 mdio_delay(vp);
1da177e4
LT		 3080 }
3081 /* Read the two transition, 16 data, and wire-idle bits. */
3082 for (i = 19; i > 0; i--) {
a095cfc4
BH		 3083 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3084 mdio_delay(vp);
3085 retval = (retval << 1) |
3086 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3087 MDIO_DATA_READ) ? 1 : 0);
3088 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3089 4, Wn4_PhysicalMgmt);
3090 mdio_delay(vp);
1da177e4 3091 }
de847272
BH		 3092
3093 spin_unlock_bh(&vp->mii_lock);
3094
1da177e4
LT		 3095 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3096}
3097
3098static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3099{
62afe595 3100 struct vortex_private *vp = netdev_priv(dev);
1da177e4 3101 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
1da177e4
LT		 3102 int i;
3103
de847272
BH		 3104 spin_lock_bh(&vp->mii_lock);
3105
1da177e4 3106 if (mii_preamble_required)
a095cfc4 3107 mdio_sync(vp, 32);
1da177e4
LT		 3108
3109 /* Shift the command bits out. */
3110 for (i = 31; i >= 0; i--) {
3111 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
a095cfc4
BH		 3112 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3113 mdio_delay(vp);
3114 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3115 4, Wn4_PhysicalMgmt);
3116 mdio_delay(vp);
1da177e4
LT		 3117 }
3118 /* Leave the interface idle. */
3119 for (i = 1; i >= 0; i--) {
a095cfc4
BH		 3120 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3121 mdio_delay(vp);
3122 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3123 4, Wn4_PhysicalMgmt);
3124 mdio_delay(vp);
1da177e4 3125 }
de847272
BH		 3126
3127 spin_unlock_bh(&vp->mii_lock);
1da177e4 3128}
a880c4cd 3129
1da177e4
LT		 3130/* ACPI: Advanced Configuration and Power Interface. */
3131/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3132static void acpi_set_WOL(struct net_device *dev)
3133{
3134 struct vortex_private *vp = netdev_priv(dev);
62afe595 3135 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3136
c17931c5
SK		 3137 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3138
1da177e4
LT		 3139 if (vp->enable_wol) {
3140 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
a095cfc4 3141 window_write16(vp, 2, 7, 0x0c);
1da177e4 3142 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3143 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3144 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4 3145
1a1769f3 3146 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
39738e16 3147 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
1a1769f3
SK		 3148
3149 vp->enable_wol = 0;
3150 return;
3151 }
3c8fad18
DR		 3152
3153 /* Change the power state to D3; RxEnable doesn't take effect. */
3154 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3155 }
1da177e4
LT		 3156}
3157
3158
a880c4cd 3159static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3160{
3161 struct net_device *dev = pci_get_drvdata(pdev);
3162 struct vortex_private *vp;
3163
3164 if (!dev) {
39738e16 3165 pr_err("vortex_remove_one called for Compaq device!\n");
1da177e4
LT		 3166 BUG();
3167 }
3168
3169 vp = netdev_priv(dev);
3170
62afe595
JL		 3171 if (vp->cb_fn_base)
3172 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3173
1da177e4
LT		 3174 unregister_netdev(dev);
3175
3176 if (VORTEX_PCI(vp)) {
3177 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3178 if (vp->pm_state_valid)
3179 pci_restore_state(VORTEX_PCI(vp));
3180 pci_disable_device(VORTEX_PCI(vp));
3181 }
3182 /* Should really use issue_and_wait() here */
62afe595
JL		 3183 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3184 vp->ioaddr + EL3_CMD);
3185
3186 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3187
3188 pci_free_consistent(pdev,
3189 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3190 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3191 vp->rx_ring,
3192 vp->rx_ring_dma);
3193 if (vp->must_free_region)
3194 release_region(dev->base_addr, vp->io_size);
3195 free_netdev(dev);
3196}
3197
3198
3199static struct pci_driver vortex_driver = {
3200 .name = "3c59x",
3201 .probe = vortex_init_one,
3202 .remove = __devexit_p(vortex_remove_one),
3203 .id_table = vortex_pci_tbl,
7bfc4ab5 3204 .driver.pm = VORTEX_PM_OPS,
1da177e4
LT		 3205};
3206
3207
3208static int vortex_have_pci;
3209static int vortex_have_eisa;
3210
3211
a880c4cd 3212static int __init vortex_init(void)
1da177e4
LT		 3213{
3214 int pci_rc, eisa_rc;
3215
29917620 3216 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3217 eisa_rc = vortex_eisa_init();
3218
3219 if (pci_rc == 0)
3220 vortex_have_pci = 1;
3221 if (eisa_rc > 0)
3222 vortex_have_eisa = 1;
3223
3224 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3225}
3226
3227
a880c4cd 3228static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3229{
3230 struct vortex_private *vp;
62afe595 3231 void __iomem *ioaddr;
1da177e4
LT		 3232
3233#ifdef CONFIG_EISA
3234 /* Take care of the EISA devices */
a880c4cd 3235 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3236#endif
6aa20a22 3237
1da177e4 3238 if (compaq_net_device) {
454d7c9b 3239 vp = netdev_priv(compaq_net_device);
62afe595
JL		 3240 ioaddr = ioport_map(compaq_net_device->base_addr,
3241 VORTEX_TOTAL_SIZE);
1da177e4 3242
a880c4cd
SK		 3243 unregister_netdev(compaq_net_device);
3244 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3245 release_region(compaq_net_device->base_addr,
3246 VORTEX_TOTAL_SIZE);
1da177e4 3247
a880c4cd 3248 free_netdev(compaq_net_device);
1da177e4
LT		 3249 }
3250}
3251
3252
a880c4cd 3253static void __exit vortex_cleanup(void)
1da177e4
LT		 3254{
3255 if (vortex_have_pci)
a880c4cd 3256 pci_unregister_driver(&vortex_driver);
1da177e4 3257 if (vortex_have_eisa)
a880c4cd 3258 vortex_eisa_cleanup();
1da177e4
LT		 3259}
3260
3261
3262module_init(vortex_init);
3263module_exit(vortex_cleanup);
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