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[PATCH] jme: Fix FIFO flush issue
[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT		 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
2e582300 25#include <linux/version.h>
937ef75a
JP		 26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
d7699f87
GFT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
4330c2f2 38#include <linux/delay.h>
29bdd921 39#include <linux/spinlock.h>
8c198884
GFT		 40#include <linux/in.h>
41#include <linux/ip.h>
79ce639c
GFT		 42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
42b1055e 45#include <linux/if_vlan.h>
38d1bc09 46#include <linux/slab.h>
3b70a6fa 47#include <net/ip6_checksum.h>
d7699f87
GFT		 48#include "jme.h"
49
cd0ff491
GFT		 50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 61
6d06d88c 62#ifndef JME_NEW_PM_API
3d12cc1b
GFT		 63static void
64jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
65{
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
67 pci_enable_wake(jme->pdev, PCI_D1, enable);
68 pci_enable_wake(jme->pdev, PCI_D2, enable);
69 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
70 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
71#else
72 pci_pme_active(jme->pdev, enable);
73#endif
74}
6d06d88c 75#endif
3d12cc1b 76
3bf61c55
GFT		 77static int
78jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 79{
80 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 81 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 82
186fc259 83read_again:
cd0ff491 84 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 85 smi_phy_addr(phy) |
86 smi_reg_addr(reg));
d7699f87
GFT		 87
88 wmb();
cd0ff491 89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 90 udelay(20);
b3821cc5
GFT		 91 val = jread32(jme, JME_SMI);
92 if ((val & SMI_OP_REQ) == 0)
3bf61c55 93 break;
cd0ff491 94 }
d7699f87 95
cd0ff491 96 if (i == 0) {
937ef75a 97 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 98 return 0;
cd0ff491 99 }
d7699f87 100
cd0ff491 101 if (again--)
186fc259
GFT		 102 goto read_again;
103
cd0ff491 104 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 105}
106
3bf61c55
GFT		 107static void
108jme_mdio_write(struct net_device *netdev,
109 int phy, int reg, int val)
d7699f87
GFT		 110{
111 struct jme_adapter *jme = netdev_priv(netdev);
112 int i;
113
3bf61c55
GFT		 114 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
115 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
116 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 117
118 wmb();
cdcdc9eb
GFT		 119 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
120 udelay(20);
8d27293f 121 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 122 break;
123 }
d7699f87 124
3bf61c55 125 if (i == 0)
937ef75a 126 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT		 127}
128
cd0ff491 129static inline void
3bf61c55 130jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 131{
cd0ff491 132 u32 val;
3bf61c55
GFT		 133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
8c198884
GFT		 136 MII_ADVERTISE, ADVERTISE_ALL |
137 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 138
cd0ff491 139 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 140 jme_mdio_write(jme->dev,
141 jme->mii_if.phy_id,
142 MII_CTRL1000,
143 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 144
fcf45b4c
GFT		 145 val = jme_mdio_read(jme->dev,
146 jme->mii_if.phy_id,
147 MII_BMCR);
148
149 jme_mdio_write(jme->dev,
150 jme->mii_if.phy_id,
151 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT		 152}
153
b3821cc5
GFT		 154static void
155jme_setup_wakeup_frame(struct jme_adapter *jme,
a4181cd4 156 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 157{
158 int i;
159
160 /*
161 * Setup CRC pattern
162 */
163 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
164 wmb();
165 jwrite32(jme, JME_WFODP, crc);
166 wmb();
167
168 /*
169 * Setup Mask
170 */
cd0ff491 171 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 172 jwrite32(jme, JME_WFOI,
173 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
174 (fnr & WFOI_FRAME_SEL));
175 wmb();
176 jwrite32(jme, JME_WFODP, mask[i]);
177 wmb();
178 }
179}
3bf61c55 180
dc4185bd
GFT		 181static inline void
182jme_mac_rxclk_off(struct jme_adapter *jme)
183{
184 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
185 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
186}
187
188static inline void
189jme_mac_rxclk_on(struct jme_adapter *jme)
190{
191 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
192 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
193}
194
195static inline void
196jme_mac_txclk_off(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_mac_txclk_on(struct jme_adapter *jme)
204{
205 u32 speed = jme->reg_ghc & GHC_SPEED;
206 if (speed == GHC_SPEED_1000M)
207 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
208 else
209 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
210 jwrite32f(jme, JME_GHC, jme->reg_ghc);
211}
212
213static inline void
214jme_reset_ghc_speed(struct jme_adapter *jme)
215{
216 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_reset_250A2_workaround(struct jme_adapter *jme)
222{
223 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
224 GPREG1_RSSPATCH);
225 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
226}
227
228static inline void
229jme_assert_ghc_reset(struct jme_adapter *jme)
230{
231 jme->reg_ghc |= GHC_SWRST;
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
233}
234
235static inline void
236jme_clear_ghc_reset(struct jme_adapter *jme)
237{
238 jme->reg_ghc &= ~GHC_SWRST;
239 jwrite32f(jme, JME_GHC, jme->reg_ghc);
240}
241
cd0ff491 242static inline void
3bf61c55
GFT		 243jme_reset_mac_processor(struct jme_adapter *jme)
244{
a4181cd4 245 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT		 246 u32 crc = 0xCDCDCDCD;
247 u32 gpreg0;
b3821cc5
GFT		 248 int i;
249
dc4185bd
GFT		 250 jme_reset_ghc_speed(jme);
251 jme_reset_250A2_workaround(jme);
252
253 jme_mac_rxclk_on(jme);
254 jme_mac_txclk_on(jme);
255 udelay(1);
256 jme_assert_ghc_reset(jme);
257 udelay(1);
258 jme_mac_rxclk_off(jme);
259 jme_mac_txclk_off(jme);
260 udelay(1);
261 jme_clear_ghc_reset(jme);
262 udelay(1);
263 jme_mac_rxclk_on(jme);
264 jme_mac_txclk_on(jme);
265 udelay(1);
266 jme_mac_rxclk_off(jme);
267 jme_mac_txclk_off(jme);
cd0ff491
GFT		 268
269 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
270 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
271 jwrite32(jme, JME_RXQDC, 0x00000000);
272 jwrite32(jme, JME_RXNDA, 0x00000000);
273 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
274 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
275 jwrite32(jme, JME_TXQDC, 0x00000000);
276 jwrite32(jme, JME_TXNDA, 0x00000000);
277
4330c2f2
GFT		 278 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
279 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 280 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 281 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 282 if (jme->fpgaver)
cdcdc9eb
GFT		 283 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
284 else
285 gpreg0 = GPREG0_DEFAULT;
286 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT		 287}
288
289static inline void
3bf61c55 290jme_clear_pm(struct jme_adapter *jme)
d7699f87 291{
3d12cc1b 292 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
d7699f87
GFT		 293}
294
3bf61c55
GFT		 295static int
296jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 297{
cd0ff491 298 u32 val;
d7699f87
GFT		 299 int i;
300
301 val = jread32(jme, JME_SMBCSR);
302
cd0ff491 303 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 304 val |= SMBCSR_CNACK;
305 jwrite32(jme, JME_SMBCSR, val);
306 val |= SMBCSR_RELOAD;
307 jwrite32(jme, JME_SMBCSR, val);
308 mdelay(12);
309
cd0ff491 310 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 311 mdelay(1);
312 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
313 break;
314 }
315
cd0ff491 316 if (i == 0) {
937ef75a 317 pr_err("eeprom reload timeout\n");
d7699f87
GFT		 318 return -EIO;
319 }
320 }
3bf61c55 321
d7699f87
GFT		 322 return 0;
323}
324
3bf61c55
GFT		 325static void
326jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 327{
328 struct jme_adapter *jme = netdev_priv(netdev);
329 unsigned char macaddr[6];
cd0ff491 330 u32 val;
d7699f87 331
cd0ff491 332 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 333 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 334 macaddr[0] = (val >> 0) & 0xFF;
335 macaddr[1] = (val >> 8) & 0xFF;
336 macaddr[2] = (val >> 16) & 0xFF;
337 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 338 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 339 macaddr[4] = (val >> 0) & 0xFF;
340 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 341 memcpy(netdev->dev_addr, macaddr, 6);
342 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 343}
344
cd0ff491 345static inline void
3bf61c55
GFT		 346jme_set_rx_pcc(struct jme_adapter *jme, int p)
347{
cd0ff491 348 switch (p) {
192570e0
GFT		 349 case PCC_OFF:
350 jwrite32(jme, JME_PCCRX0,
351 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
352 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
353 break;
3bf61c55
GFT		 354 case PCC_P1:
355 jwrite32(jme, JME_PCCRX0,
356 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
357 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
358 break;
359 case PCC_P2:
360 jwrite32(jme, JME_PCCRX0,
361 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
362 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
363 break;
364 case PCC_P3:
365 jwrite32(jme, JME_PCCRX0,
366 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
367 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
368 break;
369 default:
370 break;
371 }
192570e0 372 wmb();
3bf61c55 373
cd0ff491 374 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
7ca9ebee 375 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 376}
377
fcf45b4c 378static void
3bf61c55 379jme_start_irq(struct jme_adapter *jme)
d7699f87 380{
3bf61c55
GFT		 381 register struct dynpcc_info *dpi = &(jme->dpi);
382
383 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 384 dpi->cur = PCC_P1;
385 dpi->attempt = PCC_P1;
386 dpi->cnt = 0;
387
388 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 389 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
390 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 391 PCCTXQ0_EN
392 );
393
d7699f87
GFT		 394 /*
395 * Enable Interrupts
396 */
397 jwrite32(jme, JME_IENS, INTR_ENABLE);
398}
399
cd0ff491 400static inline void
3bf61c55 401jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 402{
403 /*
404 * Disable Interrupts
405 */
cd0ff491 406 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 407}
408
cd0ff491 409static u32
cdcdc9eb
GFT		 410jme_linkstat_from_phy(struct jme_adapter *jme)
411{
cd0ff491 412 u32 phylink, bmsr;
cdcdc9eb
GFT		 413
414 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
415 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 416 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 417 phylink |= PHY_LINK_AUTONEG_COMPLETE;
418
419 return phylink;
420}
421
cd0ff491 422static inline void
55d19799 423jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT		 424{
425 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
426}
427
428static inline void
55d19799 429jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT		 430{
431 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
432}
433
fcf45b4c
GFT		 434static int
435jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 436{
437 struct jme_adapter *jme = netdev_priv(netdev);
dc4185bd 438 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 439 char linkmsg[64];
fcf45b4c 440 int rc = 0;
d7699f87 441
b3821cc5 442 linkmsg[0] = '\0';
cdcdc9eb 443
cd0ff491 444 if (jme->fpgaver)
cdcdc9eb
GFT		 445 phylink = jme_linkstat_from_phy(jme);
446 else
447 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 448
cd0ff491
GFT		 449 if (phylink & PHY_LINK_UP) {
450 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 451 /*
452 * If we did not enable AN
453 * Speed/Duplex Info should be obtained from SMI
454 */
455 phylink = PHY_LINK_UP;
456
457 bmcr = jme_mdio_read(jme->dev,
458 jme->mii_if.phy_id,
459 MII_BMCR);
460
461 phylink |= ((bmcr & BMCR_SPEED1000) &&
462 (bmcr & BMCR_SPEED100) == 0) ?
463 PHY_LINK_SPEED_1000M :
464 (bmcr & BMCR_SPEED100) ?
465 PHY_LINK_SPEED_100M :
466 PHY_LINK_SPEED_10M;
467
468 phylink |= (bmcr & BMCR_FULLDPLX) ?
469 PHY_LINK_DUPLEX : 0;
79ce639c 470
b3821cc5 471 strcat(linkmsg, "Forced: ");
cd0ff491 472 } else {
8c198884
GFT		 473 /*
474 * Keep polling for speed/duplex resolve complete
475 */
cd0ff491 476 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 477 --cnt) {
478
479 udelay(1);
8c198884 480
cd0ff491 481 if (jme->fpgaver)
cdcdc9eb
GFT		 482 phylink = jme_linkstat_from_phy(jme);
483 else
484 phylink = jread32(jme, JME_PHY_LINK);
8c198884 485 }
cd0ff491 486 if (!cnt)
937ef75a 487 pr_err("Waiting speed resolve timeout\n");
79ce639c 488
b3821cc5 489 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 490 }
491
cd0ff491 492 if (jme->phylink == phylink) {
fcf45b4c
GFT		 493 rc = 1;
494 goto out;
495 }
cd0ff491 496 if (testonly)
fcf45b4c
GFT		 497 goto out;
498
499 jme->phylink = phylink;
500
dc4185bd
GFT		 501 /*
502 * The speed/duplex setting of jme->reg_ghc already cleared
503 * by jme_reset_mac_processor()
504 */
cd0ff491
GFT		 505 switch (phylink & PHY_LINK_SPEED_MASK) {
506 case PHY_LINK_SPEED_10M:
dc4185bd 507 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 508 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 509 break;
510 case PHY_LINK_SPEED_100M:
dc4185bd 511 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 512 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 513 break;
514 case PHY_LINK_SPEED_1000M:
dc4185bd 515 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 516 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 517 break;
518 default:
519 break;
d7699f87 520 }
d7699f87 521
cd0ff491 522 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 523 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
809b2798 524 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
dc4185bd 525 jme->reg_ghc |= GHC_DPX;
cd0ff491 526 } else {
d7699f87 527 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 528 TXMCS_BACKOFF |
529 TXMCS_CARRIERSENSE |
530 TXMCS_COLLISION);
809b2798 531 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 532 }
7ee473a3 533
dc4185bd
GFT		 534 jwrite32(jme, JME_GHC, jme->reg_ghc);
535
7ee473a3 536 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
dc4185bd
GFT		 537 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
538 GPREG1_RSSPATCH);
7ee473a3 539 if (!(phylink & PHY_LINK_DUPLEX))
dc4185bd 540 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
7ee473a3
GFT		 541 switch (phylink & PHY_LINK_SPEED_MASK) {
542 case PHY_LINK_SPEED_10M:
55d19799 543 jme_set_phyfifo_8level(jme);
dc4185bd 544 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 545 break;
546 case PHY_LINK_SPEED_100M:
55d19799 547 jme_set_phyfifo_5level(jme);
dc4185bd 548 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 549 break;
550 case PHY_LINK_SPEED_1000M:
55d19799 551 jme_set_phyfifo_8level(jme);
7ee473a3
GFT		 552 break;
553 default:
554 break;
555 }
556 }
dc4185bd 557 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 558
3b70a6fa
GFT		 559 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
560 "Full-Duplex, " :
561 "Half-Duplex, ");
562 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
563 "MDI-X" :
564 "MDI");
937ef75a 565 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT		 566 netif_carrier_on(netdev);
567 } else {
568 if (testonly)
fcf45b4c
GFT		 569 goto out;
570
937ef75a 571 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 572 jme->phylink = 0;
cd0ff491 573 netif_carrier_off(netdev);
d7699f87 574 }
fcf45b4c
GFT		 575
576out:
577 return rc;
d7699f87
GFT		 578}
579
3bf61c55
GFT		 580static int
581jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 582{
d7699f87
GFT		 583 struct jme_ring *txring = &(jme->txring[0]);
584
585 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 586 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
587 &(txring->dmaalloc),
588 GFP_ATOMIC);
fcf45b4c 589
0ede469c
GFT		 590 if (!txring->alloc)
591 goto err_set_null;
d7699f87
GFT		 592
593 /*
594 * 16 Bytes align
595 */
cd0ff491 596 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 597 RING_DESC_ALIGN);
4330c2f2 598 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 599 txring->next_to_use = 0;
cdcdc9eb 600 atomic_set(&txring->next_to_clean, 0);
b3821cc5 601 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 602
0ede469c
GFT		 603 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
604 jme->tx_ring_size, GFP_ATOMIC);
605 if (unlikely(!(txring->bufinf)))
606 goto err_free_txring;
607
d7699f87 608 /*
b3821cc5 609 * Initialize Transmit Descriptors
d7699f87 610 */
b3821cc5 611 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 612 memset(txring->bufinf, 0,
b3821cc5 613 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 614
615 return 0;
0ede469c
GFT		 616
617err_free_txring:
618 dma_free_coherent(&(jme->pdev->dev),
619 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
620 txring->alloc,
621 txring->dmaalloc);
622
623err_set_null:
624 txring->desc = NULL;
625 txring->dmaalloc = 0;
626 txring->dma = 0;
627 txring->bufinf = NULL;
628
629 return -ENOMEM;
d7699f87
GFT		 630}
631
3bf61c55
GFT		 632static void
633jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 634{
635 int i;
636 struct jme_ring *txring = &(jme->txring[0]);
0ede469c 637 struct jme_buffer_info *txbi;
d7699f87 638
cd0ff491 639 if (txring->alloc) {
0ede469c
GFT		 640 if (txring->bufinf) {
641 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
642 txbi = txring->bufinf + i;
643 if (txbi->skb) {
644 dev_kfree_skb(txbi->skb);
645 txbi->skb = NULL;
646 }
647 txbi->mapping = 0;
648 txbi->len = 0;
649 txbi->nr_desc = 0;
650 txbi->start_xmit = 0;
d7699f87 651 }
0ede469c 652 kfree(txring->bufinf);
d7699f87
GFT		 653 }
654
655 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 656 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 657 txring->alloc,
658 txring->dmaalloc);
3bf61c55
GFT		 659
660 txring->alloc = NULL;
661 txring->desc = NULL;
662 txring->dmaalloc = 0;
663 txring->dma = 0;
0ede469c 664 txring->bufinf = NULL;
d7699f87 665 }
3bf61c55 666 txring->next_to_use = 0;
cdcdc9eb 667 atomic_set(&txring->next_to_clean, 0);
79ce639c 668 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 669}
670
cd0ff491 671static inline void
3bf61c55 672jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 673{
674 /*
675 * Select Queue 0
676 */
677 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 678 wmb();
d7699f87
GFT		 679
680 /*
681 * Setup TX Queue 0 DMA Bass Address
682 */
fcf45b4c 683 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 684 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 685 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 686
687 /*
688 * Setup TX Descptor Count
689 */
b3821cc5 690 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 691
692 /*
693 * Enable TX Engine
694 */
695 wmb();
dc4185bd 696 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT		 697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
d7699f87 699
dc4185bd
GFT		 700 /*
701 * Start clock for TX MAC Processor
702 */
703 jme_mac_txclk_on(jme);
d7699f87
GFT		 704}
705
cd0ff491 706static inline void
29bdd921
GFT		 707jme_restart_tx_engine(struct jme_adapter *jme)
708{
709 /*
710 * Restart TX Engine
711 */
712 jwrite32(jme, JME_TXCS, jme->reg_txcs |
713 TXCS_SELECT_QUEUE0 |
714 TXCS_ENABLE);
715}
716
cd0ff491 717static inline void
3bf61c55 718jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 719{
720 int i;
cd0ff491 721 u32 val;
d7699f87
GFT		 722
723 /*
724 * Disable TX Engine
725 */
fcf45b4c 726 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 727 wmb();
d7699f87
GFT		 728
729 val = jread32(jme, JME_TXCS);
cd0ff491 730 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 731 mdelay(1);
d7699f87 732 val = jread32(jme, JME_TXCS);
cd0ff491 733 rmb();
d7699f87
GFT		 734 }
735
cd0ff491 736 if (!i)
937ef75a 737 pr_err("Disable TX engine timeout\n");
dc4185bd
GFT		 738
739 /*
740 * Stop clock for TX MAC Processor
741 */
742 jme_mac_txclk_off(jme);
d7699f87
GFT		 743}
744
3bf61c55
GFT		 745static void
746jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 747{
0ede469c 748 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 749 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 750 struct jme_buffer_info *rxbi = rxring->bufinf;
751 rxdesc += i;
752 rxbi += i;
753
754 rxdesc->dw[0] = 0;
755 rxdesc->dw[1] = 0;
3bf61c55 756 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 757 rxdesc->desc1.bufaddrl = cpu_to_le32(
758 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 759 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 760 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 761 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 762 wmb();
3bf61c55 763 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 764}
765
3bf61c55
GFT		 766static int
767jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 768{
769 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 770 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 771 struct sk_buff *skb;
1eef180c 772 dma_addr_t mapping;
4330c2f2 773
79ce639c
GFT		 774 skb = netdev_alloc_skb(jme->dev,
775 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 776 if (unlikely(!skb))
4330c2f2 777 return -ENOMEM;
3b70a6fa
GFT		 778#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
779 skb->dev = jme->dev;
780#endif
3bf61c55 781
1eef180c
GFT		 782 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
783 offset_in_page(skb->data), skb_tailroom(skb),
784 PCI_DMA_FROMDEVICE);
6c20aa97
GFT		 785#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)
786 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping)))
787#else
788 if (unlikely(pci_dma_mapping_error(mapping)))
789#endif
790 {
1eef180c
GFT		 791 dev_kfree_skb(skb);
792 return -ENOMEM;
793 }
794
795 if (likely(rxbi->mapping))
796 pci_unmap_page(jme->pdev, rxbi->mapping,
797 rxbi->len, PCI_DMA_FROMDEVICE);
798
4330c2f2 799 rxbi->skb = skb;
3bf61c55 800 rxbi->len = skb_tailroom(skb);
1eef180c 801 rxbi->mapping = mapping;
4330c2f2
GFT		 802 return 0;
803}
804
3bf61c55
GFT		 805static void
806jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 807{
808 struct jme_ring *rxring = &(jme->rxring[0]);
809 struct jme_buffer_info *rxbi = rxring->bufinf;
810 rxbi += i;
811
cd0ff491 812 if (rxbi->skb) {
b3821cc5 813 pci_unmap_page(jme->pdev,
4330c2f2 814 rxbi->mapping,
3bf61c55 815 rxbi->len,
4330c2f2
GFT		 816 PCI_DMA_FROMDEVICE);
817 dev_kfree_skb(rxbi->skb);
818 rxbi->skb = NULL;
819 rxbi->mapping = 0;
3bf61c55 820 rxbi->len = 0;
4330c2f2
GFT		 821 }
822}
823
3bf61c55
GFT		 824static void
825jme_free_rx_resources(struct jme_adapter *jme)
826{
827 int i;
828 struct jme_ring *rxring = &(jme->rxring[0]);
829
cd0ff491 830 if (rxring->alloc) {
0ede469c
GFT		 831 if (rxring->bufinf) {
832 for (i = 0 ; i < jme->rx_ring_size ; ++i)
833 jme_free_rx_buf(jme, i);
834 kfree(rxring->bufinf);
835 }
3bf61c55
GFT		 836
837 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 838 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 839 rxring->alloc,
840 rxring->dmaalloc);
841 rxring->alloc = NULL;
842 rxring->desc = NULL;
843 rxring->dmaalloc = 0;
844 rxring->dma = 0;
0ede469c 845 rxring->bufinf = NULL;
3bf61c55
GFT		 846 }
847 rxring->next_to_use = 0;
cdcdc9eb 848 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 849}
850
851static int
852jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 853{
854 int i;
855 struct jme_ring *rxring = &(jme->rxring[0]);
856
857 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 858 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
859 &(rxring->dmaalloc),
860 GFP_ATOMIC);
0ede469c
GFT		 861 if (!rxring->alloc)
862 goto err_set_null;
d7699f87
GFT		 863
864 /*
865 * 16 Bytes align
866 */
cd0ff491 867 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 868 RING_DESC_ALIGN);
4330c2f2 869 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 870 rxring->next_to_use = 0;
cdcdc9eb 871 atomic_set(&rxring->next_to_clean, 0);
d7699f87 872
0ede469c
GFT		 873 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
874 jme->rx_ring_size, GFP_ATOMIC);
875 if (unlikely(!(rxring->bufinf)))
876 goto err_free_rxring;
877
d7699f87
GFT		 878 /*
879 * Initiallize Receive Descriptors
880 */
0ede469c
GFT		 881 memset(rxring->bufinf, 0,
882 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 883 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
884 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 885 jme_free_rx_resources(jme);
886 return -ENOMEM;
887 }
d7699f87
GFT		 888
889 jme_set_clean_rxdesc(jme, i);
890 }
891
d7699f87 892 return 0;
0ede469c
GFT		 893
894err_free_rxring:
895 dma_free_coherent(&(jme->pdev->dev),
896 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
897 rxring->alloc,
898 rxring->dmaalloc);
899err_set_null:
900 rxring->desc = NULL;
901 rxring->dmaalloc = 0;
902 rxring->dma = 0;
903 rxring->bufinf = NULL;
904
905 return -ENOMEM;
d7699f87
GFT		 906}
907
cd0ff491 908static inline void
3bf61c55 909jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 910{
cd0ff491
GFT		 911 /*
912 * Select Queue 0
913 */
914 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
915 RXCS_QUEUESEL_Q0);
916 wmb();
917
d7699f87
GFT		 918 /*
919 * Setup RX DMA Bass Address
920 */
0ede469c 921 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 922 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
0ede469c 923 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 924
925 /*
b3821cc5 926 * Setup RX Descriptor Count
d7699f87 927 */
b3821cc5 928 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 929
3bf61c55 930 /*
d7699f87
GFT		 931 * Setup Unicast Filter
932 */
e523cd89 933 jme_set_unicastaddr(jme->dev);
d7699f87
GFT		 934 jme_set_multi(jme->dev);
935
936 /*
937 * Enable RX Engine
938 */
939 wmb();
dc4185bd 940 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 941 RXCS_QUEUESEL_Q0 |
942 RXCS_ENABLE |
943 RXCS_QST);
dc4185bd
GFT		 944
945 /*
946 * Start clock for RX MAC Processor
947 */
948 jme_mac_rxclk_on(jme);
d7699f87
GFT		 949}
950
cd0ff491 951static inline void
3bf61c55 952jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 953{
954 /*
3bf61c55 955 * Start RX Engine
4330c2f2 956 */
79ce639c 957 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 958 RXCS_QUEUESEL_Q0 |
959 RXCS_ENABLE |
960 RXCS_QST);
961}
962
cd0ff491 963static inline void
3bf61c55 964jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 965{
966 int i;
cd0ff491 967 u32 val;
d7699f87
GFT		 968
969 /*
970 * Disable RX Engine
971 */
29bdd921 972 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 973 wmb();
d7699f87
GFT		 974
975 val = jread32(jme, JME_RXCS);
cd0ff491 976 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 977 mdelay(1);
d7699f87 978 val = jread32(jme, JME_RXCS);
cd0ff491 979 rmb();
d7699f87
GFT		 980 }
981
cd0ff491 982 if (!i)
937ef75a 983 pr_err("Disable RX engine timeout\n");
d7699f87 984
dc4185bd
GFT		 985 /*
986 * Stop clock for RX MAC Processor
987 */
988 jme_mac_rxclk_off(jme);
d7699f87
GFT		 989}
990
93f698ca
GFT		 991static u16
992jme_udpsum(struct sk_buff *skb)
993{
994 u16 csum = 0xFFFFu;
65ff9ddf
GFT		 995#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
996 struct iphdr *iph;
997 int iphlen;
998 struct udphdr *udph;
999#endif
93f698ca
GFT		 1000
1001 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
1002 return csum;
1003 if (skb->protocol != htons(ETH_P_IP))
1004 return csum;
65ff9ddf
GFT		 1005#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1006 iph = (struct iphdr *)skb_pull(skb, ETH_HLEN);
1007 iphlen = (iph->ihl << 2);
1008 if ((iph->protocol != IPPROTO_UDP) ||
1009 (skb->len < (iphlen + sizeof(struct udphdr)))) {
1010 skb_push(skb, ETH_HLEN);
1011 return csum;
1012 }
1013 udph = (struct udphdr *)skb_pull(skb, iphlen);
1014 csum = udph->check;
1015 skb_push(skb, iphlen);
1016 skb_push(skb, ETH_HLEN);
1017#else
93f698ca
GFT		 1018 skb_set_network_header(skb, ETH_HLEN);
1019 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
1020 (skb->len < (ETH_HLEN +
1021 (ip_hdr(skb)->ihl << 2) +
1022 sizeof(struct udphdr)))) {
1023 skb_reset_network_header(skb);
1024 return csum;
1025 }
1026 skb_set_transport_header(skb,
1027 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
1028 csum = udp_hdr(skb)->check;
1029 skb_reset_transport_header(skb);
1030 skb_reset_network_header(skb);
65ff9ddf 1031#endif
93f698ca
GFT		 1032
1033 return csum;
1034}
1035
192570e0 1036static int
93f698ca 1037jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
192570e0 1038{
cd0ff491 1039 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 1040 return false;
1041
0ede469c
GFT		 1042 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1043 == RXWBFLAG_TCPON)) {
1044 if (flags & RXWBFLAG_IPV4)
7ca9ebee 1045 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
0ede469c 1046 return false;
192570e0
GFT		 1047 }
1048
0ede469c 1049 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
93f698ca 1050 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
0ede469c 1051 if (flags & RXWBFLAG_IPV4)
937ef75a 1052 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
0ede469c 1053 return false;
192570e0
GFT		 1054 }
1055
0ede469c
GFT		 1056 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1057 == RXWBFLAG_IPV4)) {
937ef75a 1058 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
0ede469c 1059 return false;
192570e0
GFT		 1060 }
1061
1062 return true;
1063}
1064
3bf61c55 1065static void
42b1055e 1066jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 1067{
d7699f87 1068 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1069 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 1070 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 1071 struct sk_buff *skb;
3bf61c55 1072 int framesize;
d7699f87 1073
3bf61c55
GFT		 1074 rxdesc += idx;
1075 rxbi += idx;
d7699f87 1076
3bf61c55
GFT		 1077 skb = rxbi->skb;
1078 pci_dma_sync_single_for_cpu(jme->pdev,
1079 rxbi->mapping,
1080 rxbi->len,
1081 PCI_DMA_FROMDEVICE);
1082
cd0ff491 1083 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 1084 pci_dma_sync_single_for_device(jme->pdev,
1085 rxbi->mapping,
1086 rxbi->len,
1087 PCI_DMA_FROMDEVICE);
1088
1089 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1090 } else {
3bf61c55
GFT		 1091 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1092 - RX_PREPAD_SIZE;
1093
1094 skb_reserve(skb, RX_PREPAD_SIZE);
1095 skb_put(skb, framesize);
1096 skb->protocol = eth_type_trans(skb, jme->dev);
1097
93f698ca 1098 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
8c198884 1099 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1100 else
614c0bfd 1101#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
29bdd921 1102 skb->ip_summed = CHECKSUM_NONE;
08f5fcfa
ED		 1103#else
1104 skb_checksum_none_assert(skb);
1105#endif
8c198884 1106
5141719b 1107#ifndef __UNIFY_VLAN_RX_PATH__
3b70a6fa 1108 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 1109 if (jme->vlgrp) {
cdcdc9eb 1110 jme->jme_vlan_rx(skb, jme->vlgrp,
3b70a6fa 1111 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 1112 NET_STAT(jme).rx_bytes += 4;
7ca9ebee 1113 } else {
7ca9ebee 1114 dev_kfree_skb(skb);
b3821cc5 1115 }
cd0ff491 1116 } else {
cdcdc9eb 1117 jme->jme_rx(skb);
b3821cc5 1118 }
5141719b
JP		 1119#else
1120 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1121 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1122
1123 __vlan_hwaccel_put_tag(skb, vid);
1124 NET_STAT(jme).rx_bytes += 4;
1125 }
1126 jme->jme_rx(skb);
1127#endif
3bf61c55 1128
3b70a6fa
GFT		 1129 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1130 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 1131 ++(NET_STAT(jme).multicast);
1132
3bf61c55
GFT		 1133 NET_STAT(jme).rx_bytes += framesize;
1134 ++(NET_STAT(jme).rx_packets);
1135 }
1136
1137 jme_set_clean_rxdesc(jme, idx);
1138
1139}
1140
1141static int
1142jme_process_receive(struct jme_adapter *jme, int limit)
1143{
1144 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1145 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1146 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1147
cd0ff491 1148 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 1149 goto out_inc;
1150
cd0ff491 1151 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 1152 goto out_inc;
1153
cd0ff491 1154 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 1155 goto out_inc;
1156
cdcdc9eb 1157 i = atomic_read(&rxring->next_to_clean);
0ede469c 1158 while (limit > 0) {
3bf61c55
GFT		 1159 rxdesc = rxring->desc;
1160 rxdesc += i;
1161
3b70a6fa 1162 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 1163 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1164 goto out;
0ede469c 1165 --limit;
d7699f87 1166
9134abda 1167 rmb();
4330c2f2
GFT		 1168 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1169
cd0ff491 1170 if (unlikely(desccnt > 1 ||
192570e0 1171 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1172
cd0ff491 1173 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1174 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1175 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1176 ++(NET_STAT(jme).rx_fifo_errors);
1177 else
1178 ++(NET_STAT(jme).rx_errors);
4330c2f2 1179
cd0ff491 1180 if (desccnt > 1)
3bf61c55 1181 limit -= desccnt - 1;
4330c2f2 1182
cd0ff491 1183 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1184 jme_set_clean_rxdesc(jme, j);
b3821cc5 1185 j = (j + 1) & (mask);
4330c2f2 1186 }
3bf61c55 1187
cd0ff491 1188 } else {
42b1055e 1189 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1190 }
4330c2f2 1191
b3821cc5 1192 i = (i + desccnt) & (mask);
3bf61c55 1193 }
4330c2f2 1194
3bf61c55 1195out:
cdcdc9eb 1196 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1197
192570e0
GFT		 1198out_inc:
1199 atomic_inc(&jme->rx_cleaning);
1200
3bf61c55 1201 return limit > 0 ? limit : 0;
4330c2f2 1202
3bf61c55 1203}
d7699f87 1204
79ce639c
GFT		 1205static void
1206jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1207{
cd0ff491 1208 if (likely(atmp == dpi->cur)) {
192570e0 1209 dpi->cnt = 0;
79ce639c 1210 return;
192570e0 1211 }
79ce639c 1212
cd0ff491 1213 if (dpi->attempt == atmp) {
79ce639c 1214 ++(dpi->cnt);
cd0ff491 1215 } else {
79ce639c
GFT		 1216 dpi->attempt = atmp;
1217 dpi->cnt = 0;
1218 }
1219
1220}
1221
1222static void
1223jme_dynamic_pcc(struct jme_adapter *jme)
1224{
1225 register struct dynpcc_info *dpi = &(jme->dpi);
1226
cd0ff491 1227 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1228 jme_attempt_pcc(dpi, PCC_P3);
7ca9ebee
GFT		 1229 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1230 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT		 1231 jme_attempt_pcc(dpi, PCC_P2);
1232 else
1233 jme_attempt_pcc(dpi, PCC_P1);
1234
cd0ff491
GFT		 1235 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1236 if (dpi->attempt < dpi->cur)
1237 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1238 jme_set_rx_pcc(jme, dpi->attempt);
1239 dpi->cur = dpi->attempt;
1240 dpi->cnt = 0;
1241 }
1242}
1243
1244static void
1245jme_start_pcc_timer(struct jme_adapter *jme)
1246{
1247 struct dynpcc_info *dpi = &(jme->dpi);
1248 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1249 dpi->last_pkts = NET_STAT(jme).rx_packets;
1250 dpi->intr_cnt = 0;
1251 jwrite32(jme, JME_TMCSR,
1252 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1253}
1254
cd0ff491 1255static inline void
29bdd921
GFT		 1256jme_stop_pcc_timer(struct jme_adapter *jme)
1257{
1258 jwrite32(jme, JME_TMCSR, 0);
1259}
1260
cd0ff491
GFT		 1261static void
1262jme_shutdown_nic(struct jme_adapter *jme)
1263{
1264 u32 phylink;
1265
1266 phylink = jme_linkstat_from_phy(jme);
1267
1268 if (!(phylink & PHY_LINK_UP)) {
1269 /*
1270 * Disable all interrupt before issue timer
1271 */
1272 jme_stop_irq(jme);
1273 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1274 }
1275}
1276
79ce639c
GFT		 1277static void
1278jme_pcc_tasklet(unsigned long arg)
1279{
cd0ff491 1280 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1281 struct net_device *netdev = jme->dev;
1282
cd0ff491
GFT		 1283 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1284 jme_shutdown_nic(jme);
1285 return;
1286 }
29bdd921 1287
cd0ff491 1288 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1289 (atomic_read(&jme->link_changing) != 1)
1290 )) {
1291 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1292 return;
1293 }
29bdd921 1294
cd0ff491 1295 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1296 jme_dynamic_pcc(jme);
1297
79ce639c
GFT		 1298 jme_start_pcc_timer(jme);
1299}
1300
cd0ff491 1301static inline void
192570e0
GFT		 1302jme_polling_mode(struct jme_adapter *jme)
1303{
1304 jme_set_rx_pcc(jme, PCC_OFF);
1305}
1306
cd0ff491 1307static inline void
192570e0
GFT		 1308jme_interrupt_mode(struct jme_adapter *jme)
1309{
1310 jme_set_rx_pcc(jme, PCC_P1);
1311}
1312
cd0ff491
GFT		 1313static inline int
1314jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1315{
1316 u32 apmc;
1317 apmc = jread32(jme, JME_APMC);
1318 return apmc & JME_APMC_PSEUDO_HP_EN;
1319}
1320
1321static void
1322jme_start_shutdown_timer(struct jme_adapter *jme)
1323{
1324 u32 apmc;
1325
1326 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1327 apmc &= ~JME_APMC_EPIEN_CTRL;
1328 if (!no_extplug) {
1329 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1330 wmb();
1331 }
1332 jwrite32f(jme, JME_APMC, apmc);
1333
1334 jwrite32f(jme, JME_TIMER2, 0);
1335 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1336 jwrite32(jme, JME_TMCSR,
1337 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1338}
1339
1340static void
1341jme_stop_shutdown_timer(struct jme_adapter *jme)
1342{
1343 u32 apmc;
1344
1345 jwrite32f(jme, JME_TMCSR, 0);
1346 jwrite32f(jme, JME_TIMER2, 0);
1347 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1348
1349 apmc = jread32(jme, JME_APMC);
1350 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1351 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1352 wmb();
1353 jwrite32f(jme, JME_APMC, apmc);
1354}
1355
3bf61c55
GFT		 1356static void
1357jme_link_change_tasklet(unsigned long arg)
1358{
cd0ff491 1359 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1360 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1361 int rc;
1362
cd0ff491
GFT		 1363 while (!atomic_dec_and_test(&jme->link_changing)) {
1364 atomic_inc(&jme->link_changing);
937ef75a 1365 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
58c92f28 1366 while (atomic_read(&jme->link_changing) != 1)
937ef75a 1367 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1368 }
fcf45b4c 1369
cd0ff491 1370 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1371 goto out;
1372
29bdd921 1373 jme->old_mtu = netdev->mtu;
fcf45b4c 1374 netif_stop_queue(netdev);
cd0ff491
GFT		 1375 if (jme_pseudo_hotplug_enabled(jme))
1376 jme_stop_shutdown_timer(jme);
1377
1378 jme_stop_pcc_timer(jme);
1379 tasklet_disable(&jme->txclean_task);
1380 tasklet_disable(&jme->rxclean_task);
1381 tasklet_disable(&jme->rxempty_task);
1382
1383 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT		 1384 jme_disable_rx_engine(jme);
1385 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1386 jme_reset_mac_processor(jme);
1387 jme_free_rx_resources(jme);
1388 jme_free_tx_resources(jme);
192570e0 1389
cd0ff491 1390 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1391 jme_polling_mode(jme);
cd0ff491
GFT		 1392
1393 netif_carrier_off(netdev);
fcf45b4c
GFT		 1394 }
1395
1396 jme_check_link(netdev, 0);
cd0ff491 1397 if (netif_carrier_ok(netdev)) {
fcf45b4c 1398 rc = jme_setup_rx_resources(jme);
cd0ff491 1399 if (rc) {
937ef75a 1400 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1401 goto out_enable_tasklet;
fcf45b4c
GFT		 1402 }
1403
fcf45b4c 1404 rc = jme_setup_tx_resources(jme);
cd0ff491 1405 if (rc) {
937ef75a 1406 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT		 1407 goto err_out_free_rx_resources;
1408 }
1409
1410 jme_enable_rx_engine(jme);
1411 jme_enable_tx_engine(jme);
1412
1413 netif_start_queue(netdev);
192570e0 1414
cd0ff491 1415 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1416 jme_interrupt_mode(jme);
192570e0 1417
79ce639c 1418 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1419 } else if (jme_pseudo_hotplug_enabled(jme)) {
1420 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1421 }
1422
cd0ff491 1423 goto out_enable_tasklet;
fcf45b4c
GFT		 1424
1425err_out_free_rx_resources:
1426 jme_free_rx_resources(jme);
cd0ff491
GFT		 1427out_enable_tasklet:
1428 tasklet_enable(&jme->txclean_task);
1429 tasklet_hi_enable(&jme->rxclean_task);
1430 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1431out:
1432 atomic_inc(&jme->link_changing);
3bf61c55 1433}
d7699f87 1434
3bf61c55
GFT		 1435static void
1436jme_rx_clean_tasklet(unsigned long arg)
1437{
cd0ff491 1438 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1439 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1440
192570e0
GFT		 1441 jme_process_receive(jme, jme->rx_ring_size);
1442 ++(dpi->intr_cnt);
42b1055e 1443
192570e0 1444}
fcf45b4c 1445
192570e0 1446static int
cdcdc9eb 1447jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1448{
cdcdc9eb 1449 struct jme_adapter *jme = jme_napi_priv(holder);
3b70a6fa 1450 DECLARE_NETDEV
192570e0 1451 int rest;
fcf45b4c 1452
cdcdc9eb 1453 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1454
cd0ff491 1455 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1456 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1457 ++(NET_STAT(jme).rx_dropped);
1458 jme_restart_rx_engine(jme);
1459 }
1460 atomic_inc(&jme->rx_empty);
1461
cd0ff491 1462 if (rest) {
cdcdc9eb 1463 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1464 jme_interrupt_mode(jme);
1465 }
1466
cdcdc9eb
GFT		 1467 JME_NAPI_WEIGHT_SET(budget, rest);
1468 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1469}
1470
1471static void
1472jme_rx_empty_tasklet(unsigned long arg)
1473{
cd0ff491 1474 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1475
cd0ff491 1476 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1477 return;
1478
cd0ff491 1479 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1480 return;
1481
7ca9ebee 1482 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1483
fcf45b4c 1484 jme_rx_clean_tasklet(arg);
cdcdc9eb 1485
cd0ff491 1486 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1487 atomic_dec(&jme->rx_empty);
1488 ++(NET_STAT(jme).rx_dropped);
1489 jme_restart_rx_engine(jme);
1490 }
1491 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1492}
1493
b3821cc5
GFT		 1494static void
1495jme_wake_queue_if_stopped(struct jme_adapter *jme)
1496{
0ede469c 1497 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1498
1499 smp_wmb();
cd0ff491 1500 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1501 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
937ef75a 1502 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1503 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1504 }
1505
1506}
1507
3bf61c55
GFT		 1508static void
1509jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1510{
cd0ff491 1511 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1512 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1513 struct txdesc *txdesc = txring->desc;
3bf61c55 1514 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1515 int i, j, cnt = 0, max, err, mask;
3bf61c55 1516
937ef75a 1517 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT		 1518
1519 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1520 goto out;
1521
cd0ff491 1522 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1523 goto out;
1524
cd0ff491 1525 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1526 goto out;
1527
b3821cc5
GFT		 1528 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1529 mask = jme->tx_ring_mask;
3bf61c55 1530
cd0ff491 1531 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1532
1533 ctxbi = txbi + i;
1534
cd0ff491 1535 if (likely(ctxbi->skb &&
b3821cc5 1536 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1537
cd0ff491 1538 tx_dbg(jme, "txclean: %d+%d@%lu\n",
937ef75a 1539 i, ctxbi->nr_desc, jiffies);
3bf61c55 1540
cd0ff491 1541 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1542
cd0ff491 1543 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1544 ttxbi = txbi + ((i + j) & (mask));
1545 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1546
b3821cc5 1547 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1548 ttxbi->mapping,
1549 ttxbi->len,
1550 PCI_DMA_TODEVICE);
1551
3bf61c55
GFT		 1552 ttxbi->mapping = 0;
1553 ttxbi->len = 0;
1554 }
1555
1556 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1557
1558 cnt += ctxbi->nr_desc;
1559
cd0ff491 1560 if (unlikely(err)) {
8c198884 1561 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1562 } else {
8c198884 1563 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1564 NET_STAT(jme).tx_bytes += ctxbi->len;
1565 }
1566
1567 ctxbi->skb = NULL;
1568 ctxbi->len = 0;
cdcdc9eb 1569 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1570
1571 } else {
3bf61c55
GFT		 1572 break;
1573 }
1574
b3821cc5 1575 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1576
1577 ctxbi->nr_desc = 0;
d7699f87
GFT		 1578 }
1579
937ef75a 1580 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1581 atomic_set(&txring->next_to_clean, i);
79ce639c 1582 atomic_add(cnt, &txring->nr_free);
3bf61c55 1583
b3821cc5
GFT		 1584 jme_wake_queue_if_stopped(jme);
1585
fcf45b4c
GFT		 1586out:
1587 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1588}
1589
79ce639c 1590static void
cd0ff491 1591jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1592{
3bf61c55
GFT		 1593 /*
1594 * Disable interrupt
1595 */
1596 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1597
cd0ff491 1598 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1599 /*
1600 * Link change event is critical
1601 * all other events are ignored
1602 */
1603 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1604 tasklet_schedule(&jme->linkch_task);
29bdd921 1605 goto out_reenable;
fcf45b4c 1606 }
d7699f87 1607
cd0ff491 1608 if (intrstat & INTR_TMINTR) {
47220951 1609 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1610 tasklet_schedule(&jme->pcc_task);
47220951 1611 }
79ce639c 1612
cd0ff491 1613 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1614 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1615 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1616 }
1617
cd0ff491 1618 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1619 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1620 INTR_PCCRX0 |
1621 INTR_RX0EMP)) |
1622 INTR_RX0);
1623 }
d7699f87 1624
cd0ff491
GFT		 1625 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1626 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1627 atomic_inc(&jme->rx_empty);
1628
cd0ff491
GFT		 1629 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1630 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1631 jme_polling_mode(jme);
cdcdc9eb 1632 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1633 }
1634 }
cd0ff491
GFT		 1635 } else {
1636 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1637 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1638 tasklet_hi_schedule(&jme->rxempty_task);
1639 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1640 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1641 }
4330c2f2 1642 }
d7699f87 1643
29bdd921 1644out_reenable:
3bf61c55 1645 /*
fcf45b4c 1646 * Re-enable interrupt
3bf61c55 1647 */
fcf45b4c 1648 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1649}
1650
3b70a6fa
GFT		 1651#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1652static irqreturn_t
1653jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1654#else
79ce639c
GFT		 1655static irqreturn_t
1656jme_intr(int irq, void *dev_id)
3b70a6fa 1657#endif
79ce639c 1658{
cd0ff491
GFT		 1659 struct net_device *netdev = dev_id;
1660 struct jme_adapter *jme = netdev_priv(netdev);
1661 u32 intrstat;
79ce639c
GFT		 1662
1663 intrstat = jread32(jme, JME_IEVE);
1664
1665 /*
1666 * Check if it's really an interrupt for us
1667 */
7ee473a3 1668 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1669 return IRQ_NONE;
79ce639c
GFT		 1670
1671 /*
1672 * Check if the device still exist
1673 */
cd0ff491
GFT		 1674 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1675 return IRQ_NONE;
79ce639c
GFT		 1676
1677 jme_intr_msi(jme, intrstat);
1678
cd0ff491 1679 return IRQ_HANDLED;
d7699f87
GFT		 1680}
1681
3b70a6fa
GFT		 1682#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1683static irqreturn_t
1684jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1685#else
79ce639c
GFT		 1686static irqreturn_t
1687jme_msi(int irq, void *dev_id)
3b70a6fa 1688#endif
79ce639c 1689{
cd0ff491
GFT		 1690 struct net_device *netdev = dev_id;
1691 struct jme_adapter *jme = netdev_priv(netdev);
1692 u32 intrstat;
79ce639c 1693
0ede469c 1694 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1695
1696 jme_intr_msi(jme, intrstat);
1697
cd0ff491 1698 return IRQ_HANDLED;
79ce639c
GFT		 1699}
1700
79ce639c
GFT		 1701static void
1702jme_reset_link(struct jme_adapter *jme)
1703{
1704 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1705}
1706
fcf45b4c
GFT		 1707static void
1708jme_restart_an(struct jme_adapter *jme)
1709{
cd0ff491 1710 u32 bmcr;
fcf45b4c 1711
cd0ff491 1712 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1713 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1714 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1715 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1716 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1717}
1718
1719static int
1720jme_request_irq(struct jme_adapter *jme)
1721{
1722 int rc;
cd0ff491 1723 struct net_device *netdev = jme->dev;
3b70a6fa
GFT		 1724#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1725 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1726 int irq_flags = SA_SHIRQ;
1727#else
cd0ff491
GFT		 1728 irq_handler_t handler = jme_intr;
1729 int irq_flags = IRQF_SHARED;
3b70a6fa 1730#endif
cd0ff491
GFT		 1731
1732 if (!pci_enable_msi(jme->pdev)) {
1733 set_bit(JME_FLAG_MSI, &jme->flags);
1734 handler = jme_msi;
1735 irq_flags = 0;
1736 }
1737
1738 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1739 netdev);
1740 if (rc) {
937ef75a
JP		 1741 netdev_err(netdev,
1742 "Unable to request %s interrupt (return: %d)\n",
1743 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1744 rc);
79ce639c 1745
cd0ff491
GFT		 1746 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1747 pci_disable_msi(jme->pdev);
1748 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1749 }
cd0ff491 1750 } else {
79ce639c
GFT		 1751 netdev->irq = jme->pdev->irq;
1752 }
1753
cd0ff491 1754 return rc;
79ce639c
GFT		 1755}
1756
1757static void
1758jme_free_irq(struct jme_adapter *jme)
1759{
cd0ff491
GFT		 1760 free_irq(jme->pdev->irq, jme->dev);
1761 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1762 pci_disable_msi(jme->pdev);
1763 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1764 jme->dev->irq = jme->pdev->irq;
cd0ff491 1765 }
fcf45b4c
GFT		 1766}
1767
ed457bcc
GFT		 1768static inline void
1769jme_new_phy_on(struct jme_adapter *jme)
1770{
1771 u32 reg;
1772
1773 reg = jread32(jme, JME_PHY_PWR);
1774 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1775 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1776 jwrite32(jme, JME_PHY_PWR, reg);
1777
1778 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1779 reg &= ~PE1_GPREG0_PBG;
1780 reg |= PE1_GPREG0_ENBG;
1781 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1782}
1783
1784static inline void
1785jme_new_phy_off(struct jme_adapter *jme)
1786{
1787 u32 reg;
1788
1789 reg = jread32(jme, JME_PHY_PWR);
1790 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1791 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1792 jwrite32(jme, JME_PHY_PWR, reg);
1793
1794 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1795 reg &= ~PE1_GPREG0_PBG;
1796 reg |= PE1_GPREG0_PDD3COLD;
1797 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1798}
1799
e58b908e
GFT		 1800static inline void
1801jme_phy_on(struct jme_adapter *jme)
1802{
1803 u32 bmcr;
1804
1805 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1806 bmcr &= ~BMCR_PDOWN;
1807 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
ed457bcc
GFT		 1808
1809 if (new_phy_power_ctrl(jme->chip_main_rev))
1810 jme_new_phy_on(jme);
1811}
1812
1813static inline void
1814jme_phy_off(struct jme_adapter *jme)
1815{
1816 u32 bmcr;
1817
1818 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1819 bmcr |= BMCR_PDOWN;
1820 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1821
1822 if (new_phy_power_ctrl(jme->chip_main_rev))
1823 jme_new_phy_off(jme);
e58b908e
GFT		 1824}
1825
e021d63c
AL		 1826static int
1827jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1828{
1829 u32 phy_addr;
1830
1831 phy_addr = JM_PHY_SPEC_REG_READ | specreg;
1832 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1833 phy_addr);
1834 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1835 JM_PHY_SPEC_DATA_REG);
1836}
1837
1838static void
1839jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1840{
1841 u32 phy_addr;
1842
1843 phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
1844 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1845 phy_data);
1846 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1847 phy_addr);
1848}
1849
1850static int
1851jme_phy_calibration(struct jme_adapter *jme)
1852{
1853 u32 ctrl1000, phy_data;
1854
1855 jme_phy_off(jme);
1856 jme_phy_on(jme);
1857 /* Enabel PHY test mode 1 */
1858 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1859 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1860 ctrl1000 |= PHY_GAD_TEST_MODE_1;
1861 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1862
1863 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1864 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
1865 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
1866 JM_PHY_EXT_COMM_2_CALI_ENABLE;
1867 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1868 msleep(20);
1869 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1870 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
1871 JM_PHY_EXT_COMM_2_CALI_MODE_0 |
1872 JM_PHY_EXT_COMM_2_CALI_LATCH);
1873 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1874
1875 /* Disable PHY test mode */
1876 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1877 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1878 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1879 return 0;
1880}
1881
1882static int
1883jme_phy_setEA(struct jme_adapter *jme)
1884{
1885 u32 phy_comm0 = 0, phy_comm1 = 0;
1886 u8 nic_ctrl;
1887
1888 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1889 if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
1890 return 0;
1891
1892 switch (jme->pdev->device) {
1893 case PCI_DEVICE_ID_JMICRON_JMC250:
1894 if (((jme->chip_main_rev == 5) &&
1895 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1896 (jme->chip_sub_rev == 3))) ||
1897 (jme->chip_main_rev >= 6)) {
1898 phy_comm0 = 0x008A;
1899 phy_comm1 = 0x4109;
1900 }
1901 if ((jme->chip_main_rev == 3) &&
1902 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1903 phy_comm0 = 0xE088;
1904 break;
1905 case PCI_DEVICE_ID_JMICRON_JMC260:
1906 if (((jme->chip_main_rev == 5) &&
1907 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1908 (jme->chip_sub_rev == 3))) ||
1909 (jme->chip_main_rev >= 6)) {
1910 phy_comm0 = 0x008A;
1911 phy_comm1 = 0x4109;
1912 }
1913 if ((jme->chip_main_rev == 3) &&
1914 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1915 phy_comm0 = 0xE088;
1916 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1917 phy_comm0 = 0x608A;
1918 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1919 phy_comm0 = 0x408A;
1920 break;
1921 default:
1922 return -ENODEV;
1923 }
1924 if (phy_comm0)
1925 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1926 if (phy_comm1)
1927 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1928
1929 return 0;
1930}
1931
3bf61c55
GFT		 1932static int
1933jme_open(struct net_device *netdev)
d7699f87
GFT		 1934{
1935 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1936 int rc;
79ce639c 1937
42b1055e 1938 jme_clear_pm(jme);
cdcdc9eb 1939 JME_NAPI_ENABLE(jme);
d7699f87 1940
0ede469c 1941 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1942 tasklet_enable(&jme->txclean_task);
1943 tasklet_hi_enable(&jme->rxclean_task);
1944 tasklet_hi_enable(&jme->rxempty_task);
1945
79ce639c 1946 rc = jme_request_irq(jme);
cd0ff491 1947 if (rc)
4330c2f2 1948 goto err_out;
79ce639c 1949
d7699f87 1950 jme_start_irq(jme);
42b1055e 1951
ed457bcc
GFT		 1952 jme_phy_on(jme);
1953 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1954 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 1955 else
42b1055e 1956 jme_reset_phy_processor(jme);
e021d63c
AL		 1957 jme_phy_calibration(jme);
1958 jme_phy_setEA(jme);
29bdd921 1959 jme_reset_link(jme);
d7699f87
GFT		 1960
1961 return 0;
1962
d7699f87
GFT		 1963err_out:
1964 netif_stop_queue(netdev);
1965 netif_carrier_off(netdev);
4330c2f2 1966 return rc;
d7699f87
GFT		 1967}
1968
42b1055e
GFT		 1969static void
1970jme_set_100m_half(struct jme_adapter *jme)
1971{
cd0ff491 1972 u32 bmcr, tmp;
42b1055e 1973
a82e368c 1974 jme_phy_on(jme);
42b1055e
GFT		 1975 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1976 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1977 BMCR_SPEED1000 | BMCR_FULLDPLX);
1978 tmp |= BMCR_SPEED100;
1979
1980 if (bmcr != tmp)
1981 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1982
cd0ff491 1983 if (jme->fpgaver)
cdcdc9eb
GFT		 1984 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1985 else
1986 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1987}
1988
47220951
GFT		 1989#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1990static void
1991jme_wait_link(struct jme_adapter *jme)
1992{
cd0ff491 1993 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1994
1995 mdelay(1000);
1996 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1997 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1998 mdelay(10);
1999 phylink = jme_linkstat_from_phy(jme);
2000 }
2001}
2002
a82e368c
GFT		 2003static void
2004jme_powersave_phy(struct jme_adapter *jme)
2005{
2006 if (jme->reg_pmcs) {
2007 jme_set_100m_half(jme);
a82e368c
GFT		 2008 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2009 jme_wait_link(jme);
61891ee4 2010 jme_clear_pm(jme);
a82e368c
GFT		 2011 } else {
2012 jme_phy_off(jme);
2013 }
2014}
2015
3bf61c55
GFT		 2016static int
2017jme_close(struct net_device *netdev)
d7699f87
GFT		 2018{
2019 struct jme_adapter *jme = netdev_priv(netdev);
2020
2021 netif_stop_queue(netdev);
2022 netif_carrier_off(netdev);
2023
2024 jme_stop_irq(jme);
79ce639c 2025 jme_free_irq(jme);
d7699f87 2026
cdcdc9eb 2027 JME_NAPI_DISABLE(jme);
192570e0 2028
0ede469c
GFT		 2029 tasklet_disable(&jme->linkch_task);
2030 tasklet_disable(&jme->txclean_task);
2031 tasklet_disable(&jme->rxclean_task);
2032 tasklet_disable(&jme->rxempty_task);
8c198884 2033
cd0ff491
GFT		 2034 jme_disable_rx_engine(jme);
2035 jme_disable_tx_engine(jme);
8c198884 2036 jme_reset_mac_processor(jme);
d7699f87
GFT		 2037 jme_free_rx_resources(jme);
2038 jme_free_tx_resources(jme);
42b1055e 2039 jme->phylink = 0;
b3821cc5
GFT		 2040 jme_phy_off(jme);
2041
2042 return 0;
2043}
2044
2045static int
2046jme_alloc_txdesc(struct jme_adapter *jme,
2047 struct sk_buff *skb)
2048{
0ede469c 2049 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 2050 int idx, nr_alloc, mask = jme->tx_ring_mask;
2051
2052 idx = txring->next_to_use;
2053 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
2054
cd0ff491 2055 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 2056 return -1;
2057
2058 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 2059
b3821cc5
GFT		 2060 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
2061
2062 return idx;
2063}
2064
2065static void
2066jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 2067 struct txdesc *txdesc,
b3821cc5
GFT		 2068 struct jme_buffer_info *txbi,
2069 struct page *page,
cd0ff491
GFT		 2070 u32 page_offset,
2071 u32 len,
ce2c537d 2072 bool hidma)
b3821cc5
GFT		 2073{
2074 dma_addr_t dmaaddr;
2075
2076 dmaaddr = pci_map_page(pdev,
2077 page,
2078 page_offset,
2079 len,
2080 PCI_DMA_TODEVICE);
2081
2082 pci_dma_sync_single_for_device(pdev,
2083 dmaaddr,
2084 len,
2085 PCI_DMA_TODEVICE);
2086
2087 txdesc->dw[0] = 0;
2088 txdesc->dw[1] = 0;
2089 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 2090 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 2091 txdesc->desc2.datalen = cpu_to_le16(len);
2092 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
2093 txdesc->desc2.bufaddrl = cpu_to_le32(
2094 (__u64)dmaaddr & 0xFFFFFFFFUL);
2095
2096 txbi->mapping = dmaaddr;
2097 txbi->len = len;
2098}
2099
2100static void
2101jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2102{
0ede469c 2103 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2104 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 2105 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
ce2c537d 2106 bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT		 2107 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2108 int mask = jme->tx_ring_mask;
a2f95d81 2109 const struct skb_frag_struct *frag;
cd0ff491 2110 u32 len;
b3821cc5 2111
cd0ff491
GFT		 2112 for (i = 0 ; i < nr_frags ; ++i) {
2113 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 2114 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2115 ctxbi = txbi + ((idx + i + 2) & (mask));
2116
c6324444 2117#ifndef __USE_SKB_FRAG_API__
b3821cc5
GFT		 2118 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
2119 frag->page_offset, frag->size, hidma);
c6324444
IC		 2120#else
2121 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2122 skb_frag_page(frag),
a2f95d81 2123 frag->page_offset, skb_frag_size(frag), hidma);
c6324444 2124#endif
42b1055e 2125 }
b3821cc5 2126
cd0ff491 2127 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 2128 ctxdesc = txdesc + ((idx + 1) & (mask));
2129 ctxbi = txbi + ((idx + 1) & (mask));
2130 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2131 offset_in_page(skb->data), len, hidma);
2132
2133}
2134
2135static int
2136jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2137{
3b70a6fa 2138 if (unlikely(
0ede469c 2139#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 2140 skb_shinfo(skb)->tso_size
2141#else
2142 skb_shinfo(skb)->gso_size
2143#endif
2144 && skb_header_cloned(skb) &&
b3821cc5
GFT		 2145 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2146 dev_kfree_skb(skb);
2147 return -1;
2148 }
2149
2150 return 0;
2151}
2152
2153static int
3b70a6fa 2154jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 2155{
0ede469c 2156#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 2157 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2158#else
2159 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2160#endif
cd0ff491 2161 if (*mss) {
b3821cc5
GFT		 2162 *flags |= TXFLAG_LSEN;
2163
cd0ff491 2164 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 2165 struct iphdr *iph = ip_hdr(skb);
2166
2167 iph->check = 0;
cd0ff491 2168 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 2169 iph->daddr, 0,
2170 IPPROTO_TCP,
2171 0);
cd0ff491 2172 } else {
b3821cc5
GFT		 2173 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2174
cd0ff491 2175 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 2176 &ip6h->daddr, 0,
2177 IPPROTO_TCP,
2178 0);
2179 }
2180
2181 return 0;
2182 }
2183
2184 return 1;
2185}
2186
2187static void
cd0ff491 2188jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 2189{
3b70a6fa
GFT		 2190#ifdef CHECKSUM_PARTIAL
2191 if (skb->ip_summed == CHECKSUM_PARTIAL)
2192#else
2193 if (skb->ip_summed == CHECKSUM_HW)
2194#endif
2195 {
cd0ff491 2196 u8 ip_proto;
b3821cc5 2197
3b70a6fa
GFT		 2198#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2199 if (skb->protocol == htons(ETH_P_IP))
2200 ip_proto = ip_hdr(skb)->protocol;
2201 else if (skb->protocol == htons(ETH_P_IPV6))
2202 ip_proto = ipv6_hdr(skb)->nexthdr;
2203 else
2204 ip_proto = 0;
2205#else
b3821cc5 2206 switch (skb->protocol) {
cd0ff491 2207 case htons(ETH_P_IP):
b3821cc5
GFT		 2208 ip_proto = ip_hdr(skb)->protocol;
2209 break;
cd0ff491 2210 case htons(ETH_P_IPV6):
b3821cc5
GFT		 2211 ip_proto = ipv6_hdr(skb)->nexthdr;
2212 break;
2213 default:
2214 ip_proto = 0;
2215 break;
2216 }
3b70a6fa 2217#endif
b3821cc5 2218
cd0ff491 2219 switch (ip_proto) {
b3821cc5
GFT		 2220 case IPPROTO_TCP:
2221 *flags |= TXFLAG_TCPCS;
2222 break;
2223 case IPPROTO_UDP:
2224 *flags |= TXFLAG_UDPCS;
2225 break;
2226 default:
937ef75a 2227 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT		 2228 break;
2229 }
2230 }
2231}
2232
cd0ff491 2233static inline void
3b70a6fa 2234jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2235{
cd0ff491 2236 if (vlan_tx_tag_present(skb)) {
b3821cc5 2237 *flags |= TXFLAG_TAGON;
3b70a6fa 2238 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2239 }
b3821cc5
GFT		 2240}
2241
2242static int
3b70a6fa 2243jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2244{
0ede469c 2245 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2246 struct txdesc *txdesc;
b3821cc5 2247 struct jme_buffer_info *txbi;
cd0ff491 2248 u8 flags;
b3821cc5 2249
cd0ff491 2250 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 2251 txbi = txring->bufinf + idx;
2252
2253 txdesc->dw[0] = 0;
2254 txdesc->dw[1] = 0;
2255 txdesc->dw[2] = 0;
2256 txdesc->dw[3] = 0;
2257 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2258 /*
2259 * Set OWN bit at final.
2260 * When kernel transmit faster than NIC.
2261 * And NIC trying to send this descriptor before we tell
2262 * it to start sending this TX queue.
2263 * Other fields are already filled correctly.
2264 */
2265 wmb();
2266 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 2267 /*
2268 * Set checksum flags while not tso
2269 */
2270 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2271 jme_tx_csum(jme, skb, &flags);
b3821cc5 2272 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
3b70a6fa 2273 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 2274 txdesc->desc1.flags = flags;
2275 /*
2276 * Set tx buffer info after telling NIC to send
2277 * For better tx_clean timing
2278 */
2279 wmb();
2280 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2281 txbi->skb = skb;
2282 txbi->len = skb->len;
cd0ff491
GFT		 2283 txbi->start_xmit = jiffies;
2284 if (!txbi->start_xmit)
8d27293f 2285 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 2286
2287 return 0;
2288}
2289
b3821cc5
GFT		 2290static void
2291jme_stop_queue_if_full(struct jme_adapter *jme)
2292{
0ede469c 2293 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 2294 struct jme_buffer_info *txbi = txring->bufinf;
2295 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2296
cd0ff491 2297 txbi += idx;
b3821cc5
GFT		 2298
2299 smp_wmb();
cd0ff491 2300 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2301 netif_stop_queue(jme->dev);
937ef75a 2302 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2303 smp_wmb();
cd0ff491
GFT		 2304 if (atomic_read(&txring->nr_free)
2305 >= (jme->tx_wake_threshold)) {
b3821cc5 2306 netif_wake_queue(jme->dev);
937ef75a 2307 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT		 2308 }
2309 }
2310
cd0ff491 2311 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 2312 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2313 txbi->skb)) {
2314 netif_stop_queue(jme->dev);
e3b96dc9
GFT		 2315 netif_info(jme, tx_queued, jme->dev,
2316 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2317 }
b3821cc5
GFT		 2318}
2319
3bf61c55
GFT		 2320/*
2321 * This function is already protected by netif_tx_lock()
2322 */
cd0ff491 2323
7ca9ebee 2324#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
3bf61c55 2325static int
7ca9ebee
GFT		 2326#else
2327static netdev_tx_t
2328#endif
3bf61c55 2329jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2330{
cd0ff491 2331 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2332 int idx;
d7699f87 2333
cd0ff491 2334 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 2335 ++(NET_STAT(jme).tx_dropped);
2336 return NETDEV_TX_OK;
2337 }
2338
2339 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2340
cd0ff491 2341 if (unlikely(idx < 0)) {
b3821cc5 2342 netif_stop_queue(netdev);
937ef75a
JP		 2343 netif_err(jme, tx_err, jme->dev,
2344 "BUG! Tx ring full when queue awake!\n");
d7699f87 2345
cd0ff491 2346 return NETDEV_TX_BUSY;
b3821cc5
GFT		 2347 }
2348
3b70a6fa 2349 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2350
4330c2f2
GFT		 2351 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2352 TXCS_SELECT_QUEUE0 |
2353 TXCS_QUEUE0S |
2354 TXCS_ENABLE);
0ede469c 2355#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
d7699f87 2356 netdev->trans_start = jiffies;
0ede469c 2357#endif
d7699f87 2358
937ef75a
JP		 2359 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2360 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT		 2361 jme_stop_queue_if_full(jme);
2362
cd0ff491 2363 return NETDEV_TX_OK;
d7699f87
GFT		 2364}
2365
e523cd89
GFT		 2366static void
2367jme_set_unicastaddr(struct net_device *netdev)
2368{
2369 struct jme_adapter *jme = netdev_priv(netdev);
2370 u32 val;
2371
2372 val = (netdev->dev_addr[3] & 0xff) << 24 |
2373 (netdev->dev_addr[2] & 0xff) << 16 |
2374 (netdev->dev_addr[1] & 0xff) << 8 |
2375 (netdev->dev_addr[0] & 0xff);
2376 jwrite32(jme, JME_RXUMA_LO, val);
2377 val = (netdev->dev_addr[5] & 0xff) << 8 |
2378 (netdev->dev_addr[4] & 0xff);
2379 jwrite32(jme, JME_RXUMA_HI, val);
2380}
2381
3bf61c55
GFT		 2382static int
2383jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2384{
cd0ff491 2385 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2386 struct sockaddr *addr = p;
d7699f87 2387
cd0ff491 2388 if (netif_running(netdev))
d7699f87
GFT		 2389 return -EBUSY;
2390
cd0ff491 2391 spin_lock_bh(&jme->macaddr_lock);
d7699f87 2392 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
e523cd89 2393 jme_set_unicastaddr(netdev);
cd0ff491 2394 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 2395
2396 return 0;
2397}
2398
3bf61c55
GFT		 2399static void
2400jme_set_multi(struct net_device *netdev)
d7699f87 2401{
3bf61c55 2402 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2403 u32 mc_hash[2] = {};
7ca9ebee 2404#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
d7699f87 2405 int i;
7ca9ebee 2406#endif
d7699f87 2407
cd0ff491 2408 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2409
2410 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2411
cd0ff491 2412 if (netdev->flags & IFF_PROMISC) {
8c198884 2413 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2414 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2415 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2416 } else if (netdev->flags & IFF_MULTICAST) {
8e14c278 2417#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
3bf61c55 2418 struct dev_mc_list *mclist;
8e14c278
JP		 2419#else
2420 struct netdev_hw_addr *ha;
2421#endif
3bf61c55 2422 int bit_nr;
d7699f87 2423
8c198884 2424 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
7ca9ebee 2425#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
3bf61c55
GFT		 2426 for (i = 0, mclist = netdev->mc_list;
2427 mclist && i < netdev->mc_count;
2428 ++i, mclist = mclist->next) {
8e14c278 2429#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
7ca9ebee 2430 netdev_for_each_mc_addr(mclist, netdev) {
8e14c278
JP		 2431#else
2432 netdev_for_each_mc_addr(ha, netdev) {
7ca9ebee 2433#endif
8e14c278 2434#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
cd0ff491 2435 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
8e14c278
JP		 2436#else
2437 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2438#endif
cd0ff491
GFT		 2439 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2440 }
d7699f87 2441
4330c2f2
GFT		 2442 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2443 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2444 }
2445
d7699f87 2446 wmb();
8c198884
GFT		 2447 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2448
cd0ff491 2449 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2450}
2451
3bf61c55 2452static int
8c198884 2453jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2454{
cd0ff491 2455 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2456
cd0ff491 2457 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2458 return 0;
2459
cd0ff491
GFT		 2460 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2461 ((new_mtu) < IPV6_MIN_MTU))
2462 return -EINVAL;
79ce639c 2463
79ce639c 2464
767e5b98 2465#ifndef __USE_NDO_FIX_FEATURES__
cd0ff491 2466 if (new_mtu > 1900) {
1a0b42f4
MM		 2467 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2468 NETIF_F_TSO | NETIF_F_TSO6);
cd0ff491
GFT		 2469 } else {
2470 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
1a0b42f4 2471 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491 2472 if (test_bit(JME_FLAG_TSO, &jme->flags))
1a0b42f4 2473 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c 2474 }
767e5b98 2475#endif
79ce639c 2476
cd0ff491 2477 netdev->mtu = new_mtu;
767e5b98
MM		 2478#ifdef __USE_NDO_FIX_FEATURES__
2479 netdev_update_features(netdev);
2480#endif
d3c3d293
GFT		 2481
2482 jme_restart_rx_engine(jme);
cd0ff491 2483 jme_reset_link(jme);
79ce639c
GFT		 2484
2485 return 0;
d7699f87
GFT		 2486}
2487
8c198884
GFT		 2488static void
2489jme_tx_timeout(struct net_device *netdev)
2490{
cd0ff491 2491 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2492
cdcdc9eb
GFT		 2493 jme->phylink = 0;
2494 jme_reset_phy_processor(jme);
cd0ff491 2495 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2496 jme_set_settings(netdev, &jme->old_ecmd);
2497
8c198884 2498 /*
cdcdc9eb 2499 * Force to Reset the link again
8c198884 2500 */
29bdd921 2501 jme_reset_link(jme);
8c198884
GFT		 2502}
2503
1e5ebebc
GFT		 2504static inline void jme_pause_rx(struct jme_adapter *jme)
2505{
2506 atomic_dec(&jme->link_changing);
2507
2508 jme_set_rx_pcc(jme, PCC_OFF);
2509 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2510 JME_NAPI_DISABLE(jme);
2511 } else {
2512 tasklet_disable(&jme->rxclean_task);
2513 tasklet_disable(&jme->rxempty_task);
2514 }
2515}
2516
2517static inline void jme_resume_rx(struct jme_adapter *jme)
2518{
2519 struct dynpcc_info *dpi = &(jme->dpi);
2520
2521 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2522 JME_NAPI_ENABLE(jme);
2523 } else {
2524 tasklet_hi_enable(&jme->rxclean_task);
2525 tasklet_hi_enable(&jme->rxempty_task);
2526 }
2527 dpi->cur = PCC_P1;
2528 dpi->attempt = PCC_P1;
2529 dpi->cnt = 0;
2530 jme_set_rx_pcc(jme, PCC_P1);
2531
2532 atomic_inc(&jme->link_changing);
2533}
2534
5141719b 2535#ifndef __UNIFY_VLAN_RX_PATH__
42b1055e
GFT		 2536static void
2537jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2538{
2539 struct jme_adapter *jme = netdev_priv(netdev);
2540
1e5ebebc 2541 jme_pause_rx(jme);
42b1055e 2542 jme->vlgrp = grp;
1e5ebebc 2543 jme_resume_rx(jme);
42b1055e 2544}
5141719b 2545#endif
42b1055e 2546
7ca9ebee
GFT		 2547#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2548static void
2549jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2550{
2551 struct jme_adapter *jme = netdev_priv(netdev);
2552
7ca9ebee 2553 if(jme->vlgrp) {
1e5ebebc 2554 jme_pause_rx(jme);
7ca9ebee
GFT		 2555#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2556 jme->vlgrp->vlan_devices[vid] = NULL;
2557#else
2558 vlan_group_set_device(jme->vlgrp, vid, NULL);
2559#endif
1e5ebebc 2560 jme_resume_rx(jme);
7ca9ebee 2561 }
7ca9ebee
GFT		 2562}
2563#endif
2564
3bf61c55
GFT		 2565static void
2566jme_get_drvinfo(struct net_device *netdev,
2567 struct ethtool_drvinfo *info)
d7699f87 2568{
cd0ff491 2569 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2570
c0e78193
RJ		 2571 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2572 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2573 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
d7699f87
GFT		 2574}
2575
8c198884
GFT		 2576static int
2577jme_get_regs_len(struct net_device *netdev)
2578{
cd0ff491 2579 return JME_REG_LEN;
8c198884
GFT		 2580}
2581
2582static void
cd0ff491 2583mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2584{
2585 int i;
2586
cd0ff491 2587 for (i = 0 ; i < len ; i += 4)
79ce639c 2588 p[i >> 2] = jread32(jme, reg + i);
186fc259 2589}
8c198884 2590
186fc259 2591static void
cd0ff491 2592mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2593{
2594 int i;
cd0ff491 2595 u16 *p16 = (u16 *)p;
186fc259 2596
cd0ff491 2597 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2598 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2599}
2600
2601static void
2602jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2603{
cd0ff491
GFT		 2604 struct jme_adapter *jme = netdev_priv(netdev);
2605 u32 *p32 = (u32 *)p;
8c198884 2606
186fc259 2607 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2608
2609 regs->version = 1;
2610 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2611
2612 p32 += 0x100 >> 2;
2613 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2614
2615 p32 += 0x100 >> 2;
2616 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2617
2618 p32 += 0x100 >> 2;
2619 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2620
186fc259
GFT		 2621 p32 += 0x100 >> 2;
2622 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2623}
2624
2625static int
2626jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2627{
2628 struct jme_adapter *jme = netdev_priv(netdev);
2629
8c198884
GFT		 2630 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2631 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2632
cd0ff491 2633 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2634 ecmd->use_adaptive_rx_coalesce = false;
2635 ecmd->rx_coalesce_usecs = 0;
2636 ecmd->rx_max_coalesced_frames = 0;
2637 return 0;
2638 }
2639
2640 ecmd->use_adaptive_rx_coalesce = true;
2641
cd0ff491 2642 switch (jme->dpi.cur) {
8c198884
GFT		 2643 case PCC_P1:
2644 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2645 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2646 break;
2647 case PCC_P2:
2648 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2649 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2650 break;
2651 case PCC_P3:
2652 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2653 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2654 break;
2655 default:
2656 break;
2657 }
2658
2659 return 0;
2660}
2661
192570e0
GFT		 2662static int
2663jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2664{
2665 struct jme_adapter *jme = netdev_priv(netdev);
2666 struct dynpcc_info *dpi = &(jme->dpi);
2667
cd0ff491 2668 if (netif_running(netdev))
cdcdc9eb
GFT		 2669 return -EBUSY;
2670
7ca9ebee
GFT		 2671 if (ecmd->use_adaptive_rx_coalesce &&
2672 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2673 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb 2674 jme->jme_rx = netif_rx;
5141719b 2675#ifndef __UNIFY_VLAN_RX_PATH__
cdcdc9eb 2676 jme->jme_vlan_rx = vlan_hwaccel_rx;
5141719b 2677#endif
192570e0
GFT		 2678 dpi->cur = PCC_P1;
2679 dpi->attempt = PCC_P1;
2680 dpi->cnt = 0;
2681 jme_set_rx_pcc(jme, PCC_P1);
2682 jme_interrupt_mode(jme);
7ca9ebee
GFT		 2683 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2684 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2685 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb 2686 jme->jme_rx = netif_receive_skb;
5141719b 2687#ifndef __UNIFY_VLAN_RX_PATH__
cdcdc9eb 2688 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
5141719b 2689#endif
192570e0
GFT		 2690 jme_interrupt_mode(jme);
2691 }
2692
2693 return 0;
2694}
2695
8c198884
GFT		 2696static void
2697jme_get_pauseparam(struct net_device *netdev,
2698 struct ethtool_pauseparam *ecmd)
2699{
2700 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2701 u32 val;
8c198884
GFT		 2702
2703 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2704 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2705
cd0ff491
GFT		 2706 spin_lock_bh(&jme->phy_lock);
2707 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2708 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2709
2710 ecmd->autoneg =
2711 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2712}
2713
2714static int
2715jme_set_pauseparam(struct net_device *netdev,
2716 struct ethtool_pauseparam *ecmd)
2717{
2718 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2719 u32 val;
8c198884 2720
cd0ff491 2721 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2722 (ecmd->tx_pause != 0)) {
2723
cd0ff491 2724 if (ecmd->tx_pause)
8c198884
GFT		 2725 jme->reg_txpfc |= TXPFC_PF_EN;
2726 else
2727 jme->reg_txpfc &= ~TXPFC_PF_EN;
2728
2729 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2730 }
2731
cd0ff491
GFT		 2732 spin_lock_bh(&jme->rxmcs_lock);
2733 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2734 (ecmd->rx_pause != 0)) {
2735
cd0ff491 2736 if (ecmd->rx_pause)
8c198884
GFT		 2737 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2738 else
2739 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2740
2741 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2742 }
cd0ff491 2743 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2744
cd0ff491
GFT		 2745 spin_lock_bh(&jme->phy_lock);
2746 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2747 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2748 (ecmd->autoneg != 0)) {
2749
cd0ff491 2750 if (ecmd->autoneg)
8c198884
GFT		 2751 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2752 else
2753 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2754
b3821cc5
GFT		 2755 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2756 MII_ADVERTISE, val);
8c198884 2757 }
cd0ff491 2758 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2759
2760 return 0;
2761}
2762
29bdd921
GFT		 2763static void
2764jme_get_wol(struct net_device *netdev,
2765 struct ethtool_wolinfo *wol)
2766{
2767 struct jme_adapter *jme = netdev_priv(netdev);
2768
2769 wol->supported = WAKE_MAGIC | WAKE_PHY;
2770
2771 wol->wolopts = 0;
2772
cd0ff491 2773 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2774 wol->wolopts |= WAKE_PHY;
2775
cd0ff491 2776 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2777 wol->wolopts |= WAKE_MAGIC;
2778
2779}
2780
2781static int
2782jme_set_wol(struct net_device *netdev,
2783 struct ethtool_wolinfo *wol)
2784{
2785 struct jme_adapter *jme = netdev_priv(netdev);
2786
cd0ff491 2787 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2788 WAKE_UCAST |
2789 WAKE_MCAST |
2790 WAKE_BCAST |
2791 WAKE_ARP))
2792 return -EOPNOTSUPP;
2793
2794 jme->reg_pmcs = 0;
2795
cd0ff491 2796 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2797 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2798
cd0ff491 2799 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2800 jme->reg_pmcs |= PMCS_MFEN;
2801
cd0ff491 2802 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3d12cc1b
GFT		 2803#ifndef JME_NEW_PM_API
2804 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2805#endif
7370b85a 2806#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3d12cc1b 2807 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
7370b85a 2808#endif
e3b96dc9 2809
29bdd921
GFT		 2810 return 0;
2811}
b3821cc5 2812
3bf61c55
GFT		 2813static int
2814jme_get_settings(struct net_device *netdev,
2815 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2816{
2817 struct jme_adapter *jme = netdev_priv(netdev);
2818 int rc;
8c198884 2819
cd0ff491 2820 spin_lock_bh(&jme->phy_lock);
d7699f87 2821 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2822 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2823 return rc;
2824}
2825
3bf61c55
GFT		 2826static int
2827jme_set_settings(struct net_device *netdev,
2828 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2829{
2830 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2831 int rc, fdc = 0;
fcf45b4c 2832
8588b84b
DD		 2833 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2834 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2835 return -EINVAL;
2836
e6b41b51
GFT		 2837 /*
2838 * Check If user changed duplex only while force_media.
2839 * Hardware would not generate link change interrupt.
2840 */
cd0ff491 2841 if (jme->mii_if.force_media &&
79ce639c
GFT		 2842 ecmd->autoneg != AUTONEG_ENABLE &&
2843 (jme->mii_if.full_duplex != ecmd->duplex))
2844 fdc = 1;
2845
cd0ff491 2846 spin_lock_bh(&jme->phy_lock);
d7699f87 2847 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2848 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2849
cd0ff491 2850 if (!rc) {
e6b41b51
GFT		 2851 if (fdc)
2852 jme_reset_link(jme);
29bdd921 2853 jme->old_ecmd = *ecmd;
aa1e7189
GFT		 2854 set_bit(JME_FLAG_SSET, &jme->flags);
2855 }
2856
2857 return rc;
2858}
2859
2860static int
2861jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2862{
2863 int rc;
2864 struct jme_adapter *jme = netdev_priv(netdev);
2865 struct mii_ioctl_data *mii_data = if_mii(rq);
2866 unsigned int duplex_chg;
2867
2868 if (cmd == SIOCSMIIREG) {
2869 u16 val = mii_data->val_in;
2870 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2871 (val & BMCR_SPEED1000))
2872 return -EINVAL;
2873 }
2874
2875 spin_lock_bh(&jme->phy_lock);
2876 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2877 spin_unlock_bh(&jme->phy_lock);
2878
2879 if (!rc && (cmd == SIOCSMIIREG)) {
2880 if (duplex_chg)
2881 jme_reset_link(jme);
2882 jme_get_settings(netdev, &jme->old_ecmd);
2883 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2884 }
2885
d7699f87
GFT		 2886 return rc;
2887}
2888
cd0ff491 2889static u32
3bf61c55
GFT		 2890jme_get_link(struct net_device *netdev)
2891{
d7699f87
GFT		 2892 struct jme_adapter *jme = netdev_priv(netdev);
2893 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2894}
2895
8c198884 2896static u32
cd0ff491
GFT		 2897jme_get_msglevel(struct net_device *netdev)
2898{
2899 struct jme_adapter *jme = netdev_priv(netdev);
2900 return jme->msg_enable;
2901}
2902
2903static void
2904jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2905{
cd0ff491
GFT		 2906 struct jme_adapter *jme = netdev_priv(netdev);
2907 jme->msg_enable = value;
2908}
8c198884 2909
767e5b98 2910#ifndef __USE_NDO_FIX_FEATURES__
cd0ff491
GFT		 2911static u32
2912jme_get_rx_csum(struct net_device *netdev)
2913{
2914 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2915 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2916}
2917
2918static int
2919jme_set_rx_csum(struct net_device *netdev, u32 on)
2920{
cd0ff491 2921 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2922
cd0ff491
GFT		 2923 spin_lock_bh(&jme->rxmcs_lock);
2924 if (on)
8c198884
GFT		 2925 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2926 else
2927 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2928 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2929 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2930
2931 return 0;
2932}
2933
2934static int
2935jme_set_tx_csum(struct net_device *netdev, u32 on)
2936{
cd0ff491 2937 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2938
cd0ff491
GFT		 2939 if (on) {
2940 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2941 if (netdev->mtu <= 1900)
1a0b42f4
MM		 2942 netdev->features |=
2943 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491
GFT		 2944 } else {
2945 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
1a0b42f4
MM		 2946 netdev->features &=
2947 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
b3821cc5 2948 }
8c198884
GFT		 2949
2950 return 0;
2951}
2952
b3821cc5
GFT		 2953static int
2954jme_set_tso(struct net_device *netdev, u32 on)
2955{
cd0ff491 2956 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2957
cd0ff491
GFT		 2958 if (on) {
2959 set_bit(JME_FLAG_TSO, &jme->flags);
2960 if (netdev->mtu <= 1900)
1a0b42f4 2961 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT		 2962 } else {
2963 clear_bit(JME_FLAG_TSO, &jme->flags);
1a0b42f4 2964 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT		 2965 }
2966
cd0ff491 2967 return 0;
b3821cc5 2968}
767e5b98 2969#else
e0ae0351 2970#ifndef __NEW_FIX_FEATURES_TYPE__
767e5b98
MM		 2971static u32
2972jme_fix_features(struct net_device *netdev, u32 features)
e0ae0351
MM		 2973#else
2974static netdev_features_t
2975jme_fix_features(struct net_device *netdev, netdev_features_t features)
2976#endif
767e5b98
MM		 2977{
2978 if (netdev->mtu > 1900)
2979 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2980 return features;
2981}
2982
2983static int
e0ae0351 2984#ifndef __NEW_FIX_FEATURES_TYPE__
767e5b98 2985jme_set_features(struct net_device *netdev, u32 features)
e0ae0351
MM		 2986#else
2987jme_set_features(struct net_device *netdev, netdev_features_t features)
2988#endif
767e5b98
MM		 2989{
2990 struct jme_adapter *jme = netdev_priv(netdev);
2991
2992 spin_lock_bh(&jme->rxmcs_lock);
2993 if (features & NETIF_F_RXCSUM)
2994 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2995 else
2996 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2997 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2998 spin_unlock_bh(&jme->rxmcs_lock);
2999
3000 return 0;
3001}
3002#endif
b3821cc5 3003
8c198884
GFT		 3004static int
3005jme_nway_reset(struct net_device *netdev)
3006{
cd0ff491 3007 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 3008 jme_restart_an(jme);
3009 return 0;
3010}
3011
cd0ff491 3012static u8
186fc259
GFT		 3013jme_smb_read(struct jme_adapter *jme, unsigned int addr)
3014{
cd0ff491 3015 u32 val;
186fc259
GFT		 3016 int to;
3017
3018 val = jread32(jme, JME_SMBCSR);
3019 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 3020 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 3021 msleep(1);
3022 val = jread32(jme, JME_SMBCSR);
3023 }
cd0ff491 3024 if (!to) {
937ef75a 3025 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 3026 return 0xFF;
3027 }
3028
3029 jwrite32(jme, JME_SMBINTF,
3030 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
3031 SMBINTF_HWRWN_READ |
3032 SMBINTF_HWCMD);
3033
3034 val = jread32(jme, JME_SMBINTF);
3035 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 3036 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 3037 msleep(1);
3038 val = jread32(jme, JME_SMBINTF);
3039 }
cd0ff491 3040 if (!to) {
937ef75a 3041 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 3042 return 0xFF;
3043 }
3044
3045 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
3046}
3047
3048static void
cd0ff491 3049jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 3050{
cd0ff491 3051 u32 val;
186fc259
GFT		 3052 int to;
3053
3054 val = jread32(jme, JME_SMBCSR);
3055 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 3056 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 3057 msleep(1);
3058 val = jread32(jme, JME_SMBCSR);
3059 }
cd0ff491 3060 if (!to) {
937ef75a 3061 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 3062 return;
3063 }
3064
3065 jwrite32(jme, JME_SMBINTF,
3066 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
3067 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
3068 SMBINTF_HWRWN_WRITE |
3069 SMBINTF_HWCMD);
3070
3071 val = jread32(jme, JME_SMBINTF);
3072 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 3073 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 3074 msleep(1);
3075 val = jread32(jme, JME_SMBINTF);
3076 }
cd0ff491 3077 if (!to) {
937ef75a 3078 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 3079 return;
3080 }
3081
3082 mdelay(2);
3083}
3084
3085static int
3086jme_get_eeprom_len(struct net_device *netdev)
3087{
cd0ff491
GFT		 3088 struct jme_adapter *jme = netdev_priv(netdev);
3089 u32 val;
186fc259 3090 val = jread32(jme, JME_SMBCSR);
cd0ff491 3091 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 3092}
3093
3094static int
3095jme_get_eeprom(struct net_device *netdev,
3096 struct ethtool_eeprom *eeprom, u8 *data)
3097{
cd0ff491 3098 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 3099 int i, offset = eeprom->offset, len = eeprom->len;
3100
3101 /*
8d27293f 3102 * ethtool will check the boundary for us
186fc259
GFT		 3103 */
3104 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 3105 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 3106 data[i] = jme_smb_read(jme, i + offset);
3107
3108 return 0;
3109}
3110
3111static int
3112jme_set_eeprom(struct net_device *netdev,
3113 struct ethtool_eeprom *eeprom, u8 *data)
3114{
cd0ff491 3115 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 3116 int i, offset = eeprom->offset, len = eeprom->len;
3117
3118 if (eeprom->magic != JME_EEPROM_MAGIC)
3119 return -EINVAL;
3120
3121 /*
8d27293f 3122 * ethtool will check the boundary for us
186fc259 3123 */
cd0ff491 3124 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 3125 jme_smb_write(jme, i + offset, data[i]);
3126
3127 return 0;
3128}
3129
3b70a6fa
GFT		 3130#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
3131static struct ethtool_ops jme_ethtool_ops = {
3132#else
d7699f87 3133static const struct ethtool_ops jme_ethtool_ops = {
3b70a6fa 3134#endif
cd0ff491 3135 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 3136 .get_regs_len = jme_get_regs_len,
3137 .get_regs = jme_get_regs,
3138 .get_coalesce = jme_get_coalesce,
192570e0 3139 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 3140 .get_pauseparam = jme_get_pauseparam,
3141 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 3142 .get_wol = jme_get_wol,
3143 .set_wol = jme_set_wol,
d7699f87
GFT		 3144 .get_settings = jme_get_settings,
3145 .set_settings = jme_set_settings,
3146 .get_link = jme_get_link,
cd0ff491
GFT		 3147 .get_msglevel = jme_get_msglevel,
3148 .set_msglevel = jme_set_msglevel,
767e5b98 3149#ifndef __USE_NDO_FIX_FEATURES__
8c198884
GFT		 3150 .get_rx_csum = jme_get_rx_csum,
3151 .set_rx_csum = jme_set_rx_csum,
3152 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT		 3153 .set_tso = jme_set_tso,
3154 .set_sg = ethtool_op_set_sg,
767e5b98 3155#endif
8c198884 3156 .nway_reset = jme_nway_reset,
186fc259
GFT		 3157 .get_eeprom_len = jme_get_eeprom_len,
3158 .get_eeprom = jme_get_eeprom,
3159 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 3160};
3161
3bf61c55
GFT		 3162static int
3163jme_pci_dma64(struct pci_dev *pdev)
d7699f87 3164{
3b70a6fa 3165 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 3166#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3167 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
3168#else
3169 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
3170#endif
3171 )
3172#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3173 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3174#else
cd0ff491 3175 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
0ede469c 3176#endif
3bf61c55
GFT		 3177 return 1;
3178
3b70a6fa 3179 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 3180#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3181 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
3182#else
3183 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
3184#endif
3185 )
3186#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3187 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
3188#else
cd0ff491 3189 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
0ede469c 3190#endif
8c198884
GFT		 3191 return 1;
3192
0ede469c
GFT		 3193#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3194 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
3195 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3196#else
cd0ff491
GFT		 3197 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3198 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
0ede469c 3199#endif
3bf61c55
GFT		 3200 return 0;
3201
3202 return -1;
3203}
3204
cd0ff491 3205static inline void
cdcdc9eb
GFT		 3206jme_phy_init(struct jme_adapter *jme)
3207{
cd0ff491 3208 u16 reg26;
cdcdc9eb
GFT		 3209
3210 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3211 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3212}
3213
cd0ff491 3214static inline void
cdcdc9eb 3215jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 3216{
cd0ff491 3217 u32 chipmode;
cdcdc9eb
GFT		 3218
3219 chipmode = jread32(jme, JME_CHIPMODE);
3220
3221 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 3222 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
98ef18f1
GFT		 3223 jme->chip_main_rev = jme->chiprev & 0xF;
3224 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT		 3225}
3226
3b70a6fa
GFT		 3227#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3228static const struct net_device_ops jme_netdev_ops = {
3229 .ndo_open = jme_open,
3230 .ndo_stop = jme_close,
3231 .ndo_validate_addr = eth_validate_addr,
aa1e7189 3232 .ndo_do_ioctl = jme_ioctl,
3b70a6fa
GFT		 3233 .ndo_start_xmit = jme_start_xmit,
3234 .ndo_set_mac_address = jme_set_macaddr,
1ec30a25 3235#ifndef __USE_NDO_SET_RX_MODE__
3b70a6fa 3236 .ndo_set_multicast_list = jme_set_multi,
1ec30a25
JP		 3237#else
3238 .ndo_set_rx_mode = jme_set_multi,
3239#endif
3b70a6fa
GFT		 3240 .ndo_change_mtu = jme_change_mtu,
3241 .ndo_tx_timeout = jme_tx_timeout,
5141719b 3242#ifndef __UNIFY_VLAN_RX_PATH__
3b70a6fa 3243 .ndo_vlan_rx_register = jme_vlan_rx_register,
5141719b 3244#endif
767e5b98
MM		 3245#ifdef __USE_NDO_FIX_FEATURES__
3246 .ndo_fix_features = jme_fix_features,
3247 .ndo_set_features = jme_set_features,
3248#endif
3b70a6fa
GFT		 3249};
3250#endif
3251
3bf61c55
GFT		 3252static int __devinit
3253jme_init_one(struct pci_dev *pdev,
3254 const struct pci_device_id *ent)
3255{
cdcdc9eb 3256 int rc = 0, using_dac, i;
d7699f87
GFT		 3257 struct net_device *netdev;
3258 struct jme_adapter *jme;
cd0ff491
GFT		 3259 u16 bmcr, bmsr;
3260 u32 apmc;
d7699f87
GFT		 3261
3262 /*
3263 * set up PCI device basics
3264 */
4330c2f2 3265 rc = pci_enable_device(pdev);
cd0ff491 3266 if (rc) {
937ef75a 3267 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT		 3268 goto err_out;
3269 }
d7699f87 3270
3bf61c55 3271 using_dac = jme_pci_dma64(pdev);
cd0ff491 3272 if (using_dac < 0) {
937ef75a 3273 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT		 3274 rc = -EIO;
3275 goto err_out_disable_pdev;
3276 }
3277
cd0ff491 3278 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
937ef75a 3279 pr_err("No PCI resource region found\n");
4330c2f2
GFT		 3280 rc = -ENOMEM;
3281 goto err_out_disable_pdev;
3282 }
d7699f87 3283
4330c2f2 3284 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 3285 if (rc) {
937ef75a 3286 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT		 3287 goto err_out_disable_pdev;
3288 }
d7699f87
GFT		 3289
3290 pci_set_master(pdev);
3291
3292 /*
3293 * alloc and init net device
3294 */
3bf61c55 3295 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 3296 if (!netdev) {
4330c2f2
GFT		 3297 rc = -ENOMEM;
3298 goto err_out_release_regions;
d7699f87 3299 }
3b70a6fa
GFT		 3300#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3301 netdev->netdev_ops = &jme_netdev_ops;
3302#else
d7699f87
GFT		 3303 netdev->open = jme_open;
3304 netdev->stop = jme_close;
aa1e7189 3305 netdev->do_ioctl = jme_ioctl;
d7699f87 3306 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT		 3307 netdev->set_mac_address = jme_set_macaddr;
3308 netdev->set_multicast_list = jme_set_multi;
3309 netdev->change_mtu = jme_change_mtu;
8c198884 3310 netdev->tx_timeout = jme_tx_timeout;
42b1055e 3311 netdev->vlan_rx_register = jme_vlan_rx_register;
7ca9ebee
GFT		 3312#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3313 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3314#endif
3bf61c55 3315 NETDEV_GET_STATS(netdev, &jme_get_stats);
3b70a6fa
GFT		 3316#endif
3317 netdev->ethtool_ops = &jme_ethtool_ops;
3318 netdev->watchdog_timeo = TX_TIMEOUT;
767e5b98
MM		 3319#ifdef __USE_NDO_FIX_FEATURES__
3320 netdev->hw_features = NETIF_F_IP_CSUM |
3321 NETIF_F_IPV6_CSUM |
3322 NETIF_F_SG |
3323 NETIF_F_TSO |
3324 NETIF_F_TSO6 |
3325 NETIF_F_RXCSUM;
3326#endif
1a0b42f4
MM		 3327 netdev->features = NETIF_F_IP_CSUM |
3328 NETIF_F_IPV6_CSUM |
b3821cc5
GFT		 3329 NETIF_F_SG |
3330 NETIF_F_TSO |
3331 NETIF_F_TSO6 |
42b1055e
GFT		 3332 NETIF_F_HW_VLAN_TX |
3333 NETIF_F_HW_VLAN_RX;
cd0ff491 3334 if (using_dac)
8c198884 3335 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 3336
3337 SET_NETDEV_DEV(netdev, &pdev->dev);
3338 pci_set_drvdata(pdev, netdev);
3339
3340 /*
3341 * init adapter info
3342 */
3343 jme = netdev_priv(netdev);
3344 jme->pdev = pdev;
3345 jme->dev = netdev;
cdcdc9eb 3346 jme->jme_rx = netif_rx;
5141719b 3347#ifndef __UNIFY_VLAN_RX_PATH__
cdcdc9eb 3348 jme->jme_vlan_rx = vlan_hwaccel_rx;
5141719b 3349#endif
29bdd921 3350 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 3351 jme->phylink = 0;
b3821cc5 3352 jme->tx_ring_size = 1 << 10;
0ede469c 3353 jme->tx_ring_mask = jme->tx_ring_size - 1;
b3821cc5
GFT		 3354 jme->tx_wake_threshold = 1 << 9;
3355 jme->rx_ring_size = 1 << 9;
3356 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 3357 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 3358 jme->regs = ioremap(pci_resource_start(pdev, 0),
3359 pci_resource_len(pdev, 0));
4330c2f2 3360 if (!(jme->regs)) {
937ef75a 3361 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT		 3362 rc = -ENOMEM;
3363 goto err_out_free_netdev;
3364 }
4330c2f2 3365
cd0ff491
GFT		 3366 if (no_pseudohp) {
3367 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3368 jwrite32(jme, JME_APMC, apmc);
3369 } else if (force_pseudohp) {
3370 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3371 jwrite32(jme, JME_APMC, apmc);
3372 }
3373
cdcdc9eb 3374 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 3375
d7699f87 3376 spin_lock_init(&jme->phy_lock);
fcf45b4c 3377 spin_lock_init(&jme->macaddr_lock);
8c198884 3378 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 3379
fcf45b4c
GFT		 3380 atomic_set(&jme->link_changing, 1);
3381 atomic_set(&jme->rx_cleaning, 1);
3382 atomic_set(&jme->tx_cleaning, 1);
192570e0 3383 atomic_set(&jme->rx_empty, 1);
fcf45b4c 3384
79ce639c 3385 tasklet_init(&jme->pcc_task,
7ca9ebee 3386 jme_pcc_tasklet,
79ce639c 3387 (unsigned long) jme);
4330c2f2 3388 tasklet_init(&jme->linkch_task,
7ca9ebee 3389 jme_link_change_tasklet,
4330c2f2
GFT		 3390 (unsigned long) jme);
3391 tasklet_init(&jme->txclean_task,
7ca9ebee 3392 jme_tx_clean_tasklet,
4330c2f2
GFT		 3393 (unsigned long) jme);
3394 tasklet_init(&jme->rxclean_task,
7ca9ebee 3395 jme_rx_clean_tasklet,
4330c2f2 3396 (unsigned long) jme);
fcf45b4c 3397 tasklet_init(&jme->rxempty_task,
7ca9ebee 3398 jme_rx_empty_tasklet,
fcf45b4c 3399 (unsigned long) jme);
0ede469c 3400 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 3401 tasklet_disable_nosync(&jme->txclean_task);
3402 tasklet_disable_nosync(&jme->rxclean_task);
3403 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 3404 jme->dpi.cur = PCC_P1;
3405
cd0ff491 3406 jme->reg_ghc = 0;
79ce639c 3407 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 3408 jme->reg_rxmcs = RXMCS_DEFAULT;
3409 jme->reg_txpfc = 0;
47220951 3410 jme->reg_pmcs = PMCS_MFEN;
dc4185bd 3411 jme->reg_gpreg1 = GPREG1_DEFAULT;
767e5b98 3412#ifndef __USE_NDO_FIX_FEATURES__
cd0ff491
GFT		 3413 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3414 set_bit(JME_FLAG_TSO, &jme->flags);
767e5b98
MM		 3415#else
3416
3417 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3418 netdev->features |= NETIF_F_RXCSUM;
3419#endif
192570e0 3420
fcf45b4c
GFT		 3421 /*
3422 * Get Max Read Req Size from PCI Config Space
3423 */
cd0ff491
GFT		 3424 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3425 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3426 switch (jme->mrrs) {
3427 case MRRS_128B:
3428 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3429 break;
3430 case MRRS_256B:
3431 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3432 break;
3433 default:
3434 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3435 break;
cd54cf32 3436 }
fcf45b4c 3437
d7699f87 3438 /*
cdcdc9eb 3439 * Must check before reset_mac_processor
d7699f87 3440 */
cdcdc9eb
GFT		 3441 jme_check_hw_ver(jme);
3442 jme->mii_if.dev = netdev;
cd0ff491 3443 if (jme->fpgaver) {
cdcdc9eb 3444 jme->mii_if.phy_id = 0;
cd0ff491 3445 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 3446 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3447 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3448 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 3449 jme->mii_if.phy_id = i;
3450 break;
3451 }
3452 }
3453
cd0ff491 3454 if (!jme->mii_if.phy_id) {
cdcdc9eb 3455 rc = -EIO;
937ef75a
JP		 3456 pr_err("Can not find phy_id\n");
3457 goto err_out_unmap;
cdcdc9eb
GFT		 3458 }
3459
3460 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3461 } else {
cdcdc9eb
GFT		 3462 jme->mii_if.phy_id = 1;
3463 }
cd0ff491 3464 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 3465 jme->mii_if.supports_gmii = true;
3466 else
3467 jme->mii_if.supports_gmii = false;
aa1e7189
GFT		 3468 jme->mii_if.phy_id_mask = 0x1F;
3469 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT		 3470 jme->mii_if.mdio_read = jme_mdio_read;
3471 jme->mii_if.mdio_write = jme_mdio_write;
3472
61891ee4
GFT		 3473 jme_clear_pm(jme);
3474 pci_set_power_state(jme->pdev, PCI_D0);
3475#ifndef JME_NEW_PM_API
3476 jme_pci_wakeup_enable(jme, true);
3477#endif
3478#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
e3b96dc9 3479 device_set_wakeup_enable(&pdev->dev, true);
61891ee4
GFT		 3480#endif
3481
55d19799 3482 jme_set_phyfifo_5level(jme);
711edd99 3483#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
98ef18f1 3484 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
711edd99
SS		 3485#else
3486 jme->pcirev = pdev->revision;
3487#endif
cd0ff491 3488 if (!jme->fpgaver)
cdcdc9eb 3489 jme_phy_init(jme);
42b1055e 3490 jme_phy_off(jme);
cdcdc9eb
GFT		 3491
3492 /*
3493 * Reset MAC processor and reload EEPROM for MAC Address
3494 */
d7699f87 3495 jme_reset_mac_processor(jme);
4330c2f2 3496 rc = jme_reload_eeprom(jme);
cd0ff491 3497 if (rc) {
937ef75a 3498 pr_err("Reload eeprom for reading MAC Address error\n");
0ede469c 3499 goto err_out_unmap;
4330c2f2 3500 }
d7699f87
GFT		 3501 jme_load_macaddr(netdev);
3502
d7699f87
GFT		 3503 /*
3504 * Tell stack that we are not ready to work until open()
3505 */
3506 netif_carrier_off(netdev);
d7699f87 3507
4330c2f2 3508 rc = register_netdev(netdev);
cd0ff491 3509 if (rc) {
937ef75a 3510 pr_err("Cannot register net device\n");
0ede469c 3511 goto err_out_unmap;
4330c2f2 3512 }
d7699f87 3513
98ef18f1 3514 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
937ef75a 3515 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
7ca9ebee
GFT		 3516 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3517 "JMC250 Gigabit Ethernet" :
3518 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3519 "JMC260 Fast Ethernet" : "Unknown",
3520 (jme->fpgaver != 0) ? " (FPGA)" : "",
3521 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
98ef18f1 3522 jme->pcirev,
937ef75a
JP		 3523 netdev->dev_addr[0],
3524 netdev->dev_addr[1],
3525 netdev->dev_addr[2],
3526 netdev->dev_addr[3],
3527 netdev->dev_addr[4],
3528 netdev->dev_addr[5]);
d7699f87
GFT		 3529
3530 return 0;
3531
3532err_out_unmap:
3533 iounmap(jme->regs);
3534err_out_free_netdev:
3535 pci_set_drvdata(pdev, NULL);
3536 free_netdev(netdev);
4330c2f2
GFT		 3537err_out_release_regions:
3538 pci_release_regions(pdev);
d7699f87 3539err_out_disable_pdev:
cd0ff491 3540 pci_disable_device(pdev);
d7699f87 3541err_out:
4330c2f2 3542 return rc;
d7699f87
GFT		 3543}
3544
3bf61c55
GFT		 3545static void __devexit
3546jme_remove_one(struct pci_dev *pdev)
3547{
d7699f87
GFT		 3548 struct net_device *netdev = pci_get_drvdata(pdev);
3549 struct jme_adapter *jme = netdev_priv(netdev);
3550
3551 unregister_netdev(netdev);
3552 iounmap(jme->regs);
3553 pci_set_drvdata(pdev, NULL);
3554 free_netdev(netdev);
3555 pci_release_regions(pdev);
3556 pci_disable_device(pdev);
3557
3558}
3559
a82e368c
GFT		 3560static void
3561jme_shutdown(struct pci_dev *pdev)
3562{
3563 struct net_device *netdev = pci_get_drvdata(pdev);
3564 struct jme_adapter *jme = netdev_priv(netdev);
3565
61891ee4
GFT		 3566 jme_powersave_phy(jme);
3567#ifndef JME_NEW_PM_API
3568 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3569#endif
3d12cc1b 3570#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
61891ee4 3571 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
a82e368c
GFT		 3572#endif
3573}
3574
fda5634a
GFT		 3575#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3576 #ifdef CONFIG_PM
3577 #define JME_HAVE_PM
3578 #endif
3579#else
3580 #ifdef CONFIG_PM_SLEEP
3581 #define JME_HAVE_PM
3582 #endif
3583#endif
3584
3585#ifdef JME_HAVE_PM
29bdd921 3586static int
3d12cc1b 3587#ifdef JME_NEW_PM_API
7370b85a 3588jme_suspend(struct device *dev)
3d12cc1b
GFT		 3589#else
3590jme_suspend(struct pci_dev *pdev, pm_message_t state)
7370b85a 3591#endif
29bdd921 3592{
3d12cc1b 3593#ifdef JME_NEW_PM_API
7370b85a
RW		 3594 struct pci_dev *pdev = to_pci_dev(dev);
3595#endif
29bdd921
GFT		 3596 struct net_device *netdev = pci_get_drvdata(pdev);
3597 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 3598
3599 atomic_dec(&jme->link_changing);
3600
3601 netif_device_detach(netdev);
3602 netif_stop_queue(netdev);
3603 jme_stop_irq(jme);
29bdd921 3604
cd0ff491
GFT		 3605 tasklet_disable(&jme->txclean_task);
3606 tasklet_disable(&jme->rxclean_task);
3607 tasklet_disable(&jme->rxempty_task);
3608
cd0ff491
GFT		 3609 if (netif_carrier_ok(netdev)) {
3610 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 3611 jme_polling_mode(jme);
3612
29bdd921 3613 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 3614 jme_disable_rx_engine(jme);
3615 jme_disable_tx_engine(jme);
29bdd921
GFT		 3616 jme_reset_mac_processor(jme);
3617 jme_free_rx_resources(jme);
3618 jme_free_tx_resources(jme);
3619 netif_carrier_off(netdev);
3620 jme->phylink = 0;
3621 }
3622
cd0ff491
GFT		 3623 tasklet_enable(&jme->txclean_task);
3624 tasklet_hi_enable(&jme->rxclean_task);
3625 tasklet_hi_enable(&jme->rxempty_task);
29bdd921 3626
a82e368c 3627 jme_powersave_phy(jme);
3d12cc1b 3628#ifndef JME_NEW_PM_API
7370b85a 3629 pci_save_state(pdev);
61891ee4 3630 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
a82e368c 3631 pci_set_power_state(pdev, PCI_D3hot);
7370b85a 3632#endif
29bdd921
GFT		 3633
3634 return 0;
3635}
3636
3637static int
3d12cc1b 3638#ifdef JME_NEW_PM_API
7370b85a 3639jme_resume(struct device *dev)
3d12cc1b
GFT		 3640#else
3641jme_resume(struct pci_dev *pdev)
7370b85a 3642#endif
29bdd921 3643{
3d12cc1b 3644#ifdef JME_NEW_PM_API
7370b85a
RW		 3645 struct pci_dev *pdev = to_pci_dev(dev);
3646#endif
29bdd921
GFT		 3647 struct net_device *netdev = pci_get_drvdata(pdev);
3648 struct jme_adapter *jme = netdev_priv(netdev);
3649
3650 jme_clear_pm(jme);
3d12cc1b
GFT		 3651#ifndef JME_NEW_PM_API
3652 pci_set_power_state(pdev, PCI_D0);
29bdd921 3653 pci_restore_state(pdev);
7370b85a 3654#endif
29bdd921 3655
ed457bcc
GFT		 3656 jme_phy_on(jme);
3657 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3658 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 3659 else
29bdd921 3660 jme_reset_phy_processor(jme);
e021d63c
AL		 3661 jme_phy_calibration(jme);
3662 jme_phy_setEA(jme);
29bdd921
GFT		 3663 jme_start_irq(jme);
3664 netif_device_attach(netdev);
3665
3666 atomic_inc(&jme->link_changing);
3667
3668 jme_reset_link(jme);
3669
3670 return 0;
3671}
7370b85a 3672
e3b96dc9 3673#ifdef JME_NEW_PM_API
7370b85a
RW		 3674static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3675#define JME_PM_OPS (&jme_pm_ops)
3676#endif
3677
3678#else
3679
e3b96dc9 3680#ifdef JME_NEW_PM_API
7370b85a
RW		 3681#define JME_PM_OPS NULL
3682#endif
7ee473a3 3683#endif
29bdd921 3684
7ca9ebee 3685#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
d7699f87 3686static struct pci_device_id jme_pci_tbl[] = {
7ca9ebee
GFT		 3687#else
3688static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3689#endif
cd0ff491
GFT		 3690 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3691 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3692 { }
3693};
3694
3695static struct pci_driver jme_driver = {
cd0ff491
GFT		 3696 .name = DRV_NAME,
3697 .id_table = jme_pci_tbl,
3698 .probe = jme_init_one,
3699 .remove = __devexit_p(jme_remove_one),
a82e368c 3700 .shutdown = jme_shutdown,
e3b96dc9 3701#ifndef JME_NEW_PM_API
7370b85a
RW		 3702 .suspend = jme_suspend,
3703 .resume = jme_resume
3704#else
3705 .driver.pm = JME_PM_OPS,
3706#endif
d7699f87
GFT		 3707};
3708
3bf61c55
GFT		 3709static int __init
3710jme_init_module(void)
d7699f87 3711{
937ef75a 3712 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3713 return pci_register_driver(&jme_driver);
3714}
3715
3bf61c55
GFT		 3716static void __exit
3717jme_cleanup_module(void)
d7699f87
GFT		 3718{
3719 pci_unregister_driver(&jme_driver);
3720}
3721
3722module_init(jme_init_module);
3723module_exit(jme_cleanup_module);
3724
3bf61c55 3725MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3726MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3727MODULE_LICENSE("GPL");
3728MODULE_VERSION(DRV_VERSION);
3729MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
JMicron Ethernet Linux driver