Import jme 0.8 source
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
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GFT
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
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GFT
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24/*
79ce639c
GFT
25 * Note:
26 * Backdoor for changing "FIFO Threshold for processing next packet"
27 * Using:
28 * ethtool -C eth1 adaptive-rx on adaptive-tx on \
29 * rx-usecs 250 rx-frames-low N
30 * N := 16 | 32 | 64 | 128
31 */
32
33/*
4330c2f2 34 * Timeline before release:
4330c2f2 35 * Stage 5: Advanced offloading support.
79ce639c
GFT
36 * 0.9:
37 * - Implement scatter-gather offloading.
38 * Use pci_map_page on scattered sk_buff for HIGHMEM support
4330c2f2 39 * - Implement TCP Segement offloading.
79ce639c 40 * Due to TX FIFO size, we should turn off tso when mtu > 1500.
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GFT
41 *
42 * Stage 6: CPU Load balancing.
79ce639c 43 * 1.0:
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44 * - Implement MSI-X.
45 * Along with multiple RX queue, for CPU load balancing.
4330c2f2
GFT
46 *
47 * Stage 7:
48 * - Cleanup/re-orginize code, performence tuneing(alignment etc...).
49 * - Test and Release 1.0
8c198884
GFT
50 *
51 * Non-Critical:
52 * - Use NAPI instead of rx_tasklet?
53 * PCC Support Both Packet Counter and Timeout Interrupt for
54 * receive and transmit complete, does NAPI really needed?
55 * - Decode register dump for ethtool.
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GFT
56 */
57
4330c2f2 58#include <linux/version.h>
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GFT
59#include <linux/module.h>
60#include <linux/kernel.h>
61#include <linux/pci.h>
62#include <linux/netdevice.h>
63#include <linux/etherdevice.h>
64#include <linux/ethtool.h>
65#include <linux/mii.h>
66#include <linux/crc32.h>
4330c2f2 67#include <linux/delay.h>
29bdd921 68#include <linux/spinlock.h>
8c198884
GFT
69#include <linux/in.h>
70#include <linux/ip.h>
79ce639c
GFT
71#include <linux/ipv6.h>
72#include <linux/tcp.h>
73#include <linux/udp.h>
42b1055e 74#include <linux/if_vlan.h>
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75#include "jme.h"
76
4330c2f2 77#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
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78static struct net_device_stats *
79jme_get_stats(struct net_device *netdev)
4330c2f2
GFT
80{
81 struct jme_adapter *jme = netdev_priv(netdev);
82 return &jme->stats;
83}
84#endif
85
3bf61c55
GFT
86static int
87jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT
88{
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i, val;
91
92 jwrite32(jme, JME_SMI, SMI_OP_REQ |
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GFT
93 smi_phy_addr(phy) |
94 smi_reg_addr(reg));
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95
96 wmb();
79ce639c 97 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
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98 udelay(1);
99 if (((val = jread32(jme, JME_SMI)) & SMI_OP_REQ) == 0)
100 break;
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GFT
101 }
102
103 if (i == 0) {
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104 jeprintk(netdev->name, "phy read timeout : %d\n", reg);
105 return 0;
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GFT
106 }
107
3bf61c55 108 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
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109}
110
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111static void
112jme_mdio_write(struct net_device *netdev,
113 int phy, int reg, int val)
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114{
115 struct jme_adapter *jme = netdev_priv(netdev);
116 int i;
117
3bf61c55
GFT
118 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
119 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
120 smi_phy_addr(phy) | smi_reg_addr(reg));
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121
122 wmb();
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GFT
123 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
124 udelay(1);
125 if (((val = jread32(jme, JME_SMI)) & SMI_OP_REQ) == 0)
126 break;
127 }
d7699f87 128
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GFT
129 if (i == 0)
130 jeprintk(netdev->name, "phy write timeout : %d\n", reg);
d7699f87 131
3bf61c55 132 return;
d7699f87
GFT
133}
134
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135__always_inline static void
136jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 137{
fcf45b4c 138 __u32 val;
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139
140 jme_mdio_write(jme->dev,
141 jme->mii_if.phy_id,
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GFT
142 MII_ADVERTISE, ADVERTISE_ALL |
143 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
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144
145 jme_mdio_write(jme->dev,
146 jme->mii_if.phy_id,
147 MII_CTRL1000,
148 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
149
fcf45b4c
GFT
150 val = jme_mdio_read(jme->dev,
151 jme->mii_if.phy_id,
152 MII_BMCR);
153
154 jme_mdio_write(jme->dev,
155 jme->mii_if.phy_id,
156 MII_BMCR, val | BMCR_RESET);
157
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GFT
158 return;
159}
160
161
162__always_inline static void
163jme_reset_mac_processor(struct jme_adapter *jme)
164{
165 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 166 udelay(2);
3bf61c55 167 jwrite32(jme, JME_GHC, jme->reg_ghc);
4330c2f2
GFT
168 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
169 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
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GFT
170 jwrite32(jme, JME_WFODP, 0);
171 jwrite32(jme, JME_WFOI, 0);
4330c2f2
GFT
172 jwrite32(jme, JME_GPREG0, GPREG0_DEFAULT);
173 jwrite32(jme, JME_GPREG1, 0);
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GFT
174}
175
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176__always_inline static void
177jme_clear_pm(struct jme_adapter *jme)
d7699f87 178{
29bdd921 179 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 180 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 181 pci_enable_wake(jme->pdev, PCI_D0, false);
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GFT
182}
183
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184static int
185jme_reload_eeprom(struct jme_adapter *jme)
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GFT
186{
187 __u32 val;
188 int i;
189
190 val = jread32(jme, JME_SMBCSR);
191
192 if(val & SMBCSR_EEPROMD)
193 {
194 val |= SMBCSR_CNACK;
195 jwrite32(jme, JME_SMBCSR, val);
196 val |= SMBCSR_RELOAD;
197 jwrite32(jme, JME_SMBCSR, val);
198 mdelay(12);
199
200 for (i = JME_SMB_TIMEOUT; i > 0; --i)
201 {
202 mdelay(1);
203 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
204 break;
205 }
206
207 if(i == 0) {
4330c2f2 208 jeprintk(jme->dev->name, "eeprom reload timeout\n");
d7699f87
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209 return -EIO;
210 }
211 }
212 else
213 return -EIO;
3bf61c55 214
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215 return 0;
216}
217
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218static void
219jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT
220{
221 struct jme_adapter *jme = netdev_priv(netdev);
222 unsigned char macaddr[6];
223 __u32 val;
224
fcf45b4c 225 spin_lock(&jme->macaddr_lock);
4330c2f2 226 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT
227 macaddr[0] = (val >> 0) & 0xFF;
228 macaddr[1] = (val >> 8) & 0xFF;
229 macaddr[2] = (val >> 16) & 0xFF;
230 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 231 val = jread32(jme, JME_RXUMA_HI);
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GFT
232 macaddr[4] = (val >> 0) & 0xFF;
233 macaddr[5] = (val >> 8) & 0xFF;
234 memcpy(netdev->dev_addr, macaddr, 6);
fcf45b4c 235 spin_unlock(&jme->macaddr_lock);
3bf61c55
GFT
236}
237
fcf45b4c 238__always_inline static void
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GFT
239jme_set_rx_pcc(struct jme_adapter *jme, int p)
240{
241 switch(p) {
242 case PCC_P1:
243 jwrite32(jme, JME_PCCRX0,
244 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
245 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
246 break;
247 case PCC_P2:
248 jwrite32(jme, JME_PCCRX0,
249 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
250 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
251 break;
252 case PCC_P3:
253 jwrite32(jme, JME_PCCRX0,
254 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
255 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
256 break;
257 default:
258 break;
259 }
260
261 dprintk(jme->dev->name, "Switched to PCC_P%d\n", p);
d7699f87
GFT
262}
263
fcf45b4c 264static void
3bf61c55 265jme_start_irq(struct jme_adapter *jme)
d7699f87 266{
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GFT
267 register struct dynpcc_info *dpi = &(jme->dpi);
268
269 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
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270 dpi->cur = PCC_P1;
271 dpi->attempt = PCC_P1;
272 dpi->cnt = 0;
273
274 jwrite32(jme, JME_PCCTX,
8c198884
GFT
275 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
276 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
277 PCCTXQ0_EN
278 );
279
d7699f87
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280 /*
281 * Enable Interrupts
282 */
283 jwrite32(jme, JME_IENS, INTR_ENABLE);
284}
285
3bf61c55
GFT
286__always_inline static void
287jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
288{
289 /*
290 * Disable Interrupts
291 */
292 jwrite32(jme, JME_IENC, INTR_ENABLE);
293}
294
4330c2f2 295
3bf61c55
GFT
296__always_inline static void
297jme_enable_shadow(struct jme_adapter *jme)
4330c2f2
GFT
298{
299 jwrite32(jme,
300 JME_SHBA_LO,
301 ((__u32)jme->shadow_dma & ~((__u32)0x1F)) | SHBA_POSTEN);
302}
303
3bf61c55
GFT
304__always_inline static void
305jme_disable_shadow(struct jme_adapter *jme)
4330c2f2
GFT
306{
307 jwrite32(jme, JME_SHBA_LO, 0x0);
308}
309
fcf45b4c
GFT
310static int
311jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
312{
313 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 314 __u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 315 char linkmsg[64];
fcf45b4c 316 int rc = 0;
d7699f87
GFT
317
318 phylink = jread32(jme, JME_PHY_LINK);
319
320 if (phylink & PHY_LINK_UP) {
8c198884
GFT
321 if(!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
322 /*
323 * If we did not enable AN
324 * Speed/Duplex Info should be obtained from SMI
325 */
326 phylink = PHY_LINK_UP;
327
328 bmcr = jme_mdio_read(jme->dev,
329 jme->mii_if.phy_id,
330 MII_BMCR);
331
79ce639c 332
8c198884
GFT
333 phylink |= ((bmcr & BMCR_SPEED1000) &&
334 (bmcr & BMCR_SPEED100) == 0) ?
335 PHY_LINK_SPEED_1000M :
336 (bmcr & BMCR_SPEED100) ?
337 PHY_LINK_SPEED_100M :
338 PHY_LINK_SPEED_10M;
339
340 phylink |= (bmcr & BMCR_FULLDPLX) ?
341 PHY_LINK_DUPLEX : 0;
79ce639c
GFT
342
343 strcpy(linkmsg, "Forced: ");
8c198884
GFT
344 }
345 else {
346 /*
347 * Keep polling for speed/duplex resolve complete
348 */
349 while(!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
350 --cnt) {
351
352 udelay(1);
353 phylink = jread32(jme, JME_PHY_LINK);
354
355 }
356
357 if(!cnt)
358 jeprintk(netdev->name,
359 "Waiting speed resolve timeout.\n");
79ce639c
GFT
360
361 strcpy(linkmsg, "ANed: ");
d7699f87
GFT
362 }
363
fcf45b4c
GFT
364 if(jme->phylink == phylink) {
365 rc = 1;
366 goto out;
367 }
368 if(testonly)
369 goto out;
370
371 jme->phylink = phylink;
372
d7699f87
GFT
373 switch(phylink & PHY_LINK_SPEED_MASK) {
374 case PHY_LINK_SPEED_10M:
375 ghc = GHC_SPEED_10M;
376 strcpy(linkmsg, "10 Mbps, ");
377 break;
378 case PHY_LINK_SPEED_100M:
379 ghc = GHC_SPEED_100M;
380 strcpy(linkmsg, "100 Mbps, ");
381 break;
382 case PHY_LINK_SPEED_1000M:
383 ghc = GHC_SPEED_1000M;
384 strcpy(linkmsg, "1000 Mbps, ");
385 break;
386 default:
387 ghc = 0;
388 break;
389 }
390 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
fcf45b4c 391
d7699f87 392 strcat(linkmsg, (phylink &PHY_LINK_DUPLEX) ?
fcf45b4c
GFT
393 "Full-Duplex, " :
394 "Half-Duplex, ");
395
396 if(phylink & PHY_LINK_MDI_STAT)
fcf45b4c 397 strcat(linkmsg, "MDI-X");
8c198884
GFT
398 else
399 strcat(linkmsg, "MDI");
d7699f87
GFT
400
401 if(phylink & PHY_LINK_DUPLEX)
402 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
8c198884 403 else {
d7699f87 404 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
405 TXMCS_BACKOFF |
406 TXMCS_CARRIERSENSE |
407 TXMCS_COLLISION);
8c198884
GFT
408 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
409 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
410 TXTRHD_TXREN |
411 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
412 }
d7699f87 413
fcf45b4c
GFT
414 jme->reg_ghc = ghc;
415 jwrite32(jme, JME_GHC, ghc);
416
4330c2f2 417 jprintk(netdev->name, "Link is up at %s.\n", linkmsg);
d7699f87
GFT
418 netif_carrier_on(netdev);
419 }
420 else {
fcf45b4c
GFT
421 if(testonly)
422 goto out;
423
4330c2f2 424 jprintk(netdev->name, "Link is down.\n");
fcf45b4c 425 jme->phylink = 0;
d7699f87
GFT
426 netif_carrier_off(netdev);
427 }
fcf45b4c
GFT
428
429out:
430 return rc;
d7699f87
GFT
431}
432
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GFT
433
434static int
435jme_alloc_txdesc(struct jme_adapter *jme,
436 int nr_alloc)
4330c2f2 437{
3bf61c55
GFT
438 struct jme_ring *txring = jme->txring;
439 int idx;
440
441 idx = txring->next_to_use;
442
79ce639c 443 if(unlikely(atomic_read(&txring->nr_free) < nr_alloc))
3bf61c55
GFT
444 return -1;
445
79ce639c 446 atomic_sub(nr_alloc, &txring->nr_free);
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GFT
447
448 if((txring->next_to_use += nr_alloc) >= RING_DESC_NR)
449 txring->next_to_use -= RING_DESC_NR;
3bf61c55
GFT
450
451 return idx;
4330c2f2
GFT
452}
453
79ce639c
GFT
454static void
455jme_tx_csum(struct sk_buff *skb, unsigned mtu, __u8 *flags)
456{
457 if(skb->ip_summed == CHECKSUM_PARTIAL) {
458 __u8 ip_proto;
459
460 switch (skb->protocol) {
461 case __constant_htons(ETH_P_IP):
462 ip_proto = ip_hdr(skb)->protocol;
463 break;
464 case __constant_htons(ETH_P_IPV6):
465 ip_proto = ipv6_hdr(skb)->nexthdr;
466 break;
467 default:
468 ip_proto = 0;
469 break;
470 }
471
472
473 switch(ip_proto) {
474 case IPPROTO_TCP:
475 *flags |= TXFLAG_TCPCS;
476 break;
477 case IPPROTO_UDP:
478 *flags |= TXFLAG_UDPCS;
479 break;
480 default:
481 jeprintk("jme", "Error upper layer protocol.\n");
482 break;
483 }
484 }
485}
486
42b1055e
GFT
487__always_inline static void
488jme_tx_vlan(struct sk_buff *skb, volatile __u16 *vlan, __u8 *flags)
489{
490 if(vlan_tx_tag_present(skb)) {
491 *flags |= TXFLAG_TAGON;
492 *vlan = vlan_tx_tag_get(skb);
493 }
494}
495
3bf61c55
GFT
496static int
497jme_set_new_txdesc(struct jme_adapter *jme,
498 struct sk_buff *skb)
d7699f87
GFT
499{
500 struct jme_ring *txring = jme->txring;
3bf61c55
GFT
501 volatile struct txdesc *txdesc = txring->desc, *ctxdesc;
502 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
4330c2f2 503 dma_addr_t dmaaddr;
3bf61c55 504 int i, idx, nr_desc;
8c198884 505 __u8 flags;
3bf61c55
GFT
506
507 nr_desc = 2;
508 idx = jme_alloc_txdesc(jme, nr_desc);
509
510 if(unlikely(idx<0))
511 return NETDEV_TX_BUSY;
512
513 for(i = 1 ; i < nr_desc ; ++i) {
514 ctxdesc = txdesc + ((idx + i) & (RING_DESC_NR-1));
515 ctxbi = txbi + ((idx + i) & (RING_DESC_NR-1));
4330c2f2 516
3bf61c55
GFT
517 dmaaddr = pci_map_single(jme->pdev,
518 skb->data,
519 skb->len,
520 PCI_DMA_TODEVICE);
521
522 pci_dma_sync_single_for_device(jme->pdev,
523 dmaaddr,
524 skb->len,
525 PCI_DMA_TODEVICE);
526
527 ctxdesc->dw[0] = 0;
528 ctxdesc->dw[1] = 0;
529 ctxdesc->desc2.flags = TXFLAG_OWN;
530 if(jme->dev->features & NETIF_F_HIGHDMA)
531 ctxdesc->desc2.flags |= TXFLAG_64BIT;
532 ctxdesc->desc2.datalen = cpu_to_le16(skb->len);
533 ctxdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
fcf45b4c
GFT
534 ctxdesc->desc2.bufaddrl = cpu_to_le32(
535 (__u64)dmaaddr & 0xFFFFFFFFUL);
3bf61c55
GFT
536
537 ctxbi->mapping = dmaaddr;
538 ctxbi->len = skb->len;
539 }
540
541 ctxdesc = txdesc + idx;
542 ctxbi = txbi + idx;
543
544 ctxdesc->dw[0] = 0;
545 ctxdesc->dw[1] = 0;
546 ctxdesc->dw[2] = 0;
547 ctxdesc->dw[3] = 0;
548 ctxdesc->desc1.pktsize = cpu_to_le16(skb->len);
d7699f87
GFT
549 /*
550 * Set OWN bit at final.
3bf61c55
GFT
551 * When kernel transmit faster than NIC.
552 * And NIC trying to send this descriptor before we tell
d7699f87
GFT
553 * it to start sending this TX queue.
554 * Other fields are already filled correctly.
555 */
556 wmb();
8c198884 557 flags = TXFLAG_OWN | TXFLAG_INT;
79ce639c 558 jme_tx_csum(skb, jme->dev->mtu, &flags);
42b1055e 559 jme_tx_vlan(skb, &(ctxdesc->desc1.vlan), &flags);
8c198884 560 ctxdesc->desc1.flags = flags;
3bf61c55
GFT
561 /*
562 * Set tx buffer info after telling NIC to send
563 * For better tx_clean timing
564 */
565 wmb();
566 ctxbi->nr_desc = nr_desc;
567 ctxbi->skb = skb;
568
569 tx_dbg(jme->dev->name, "Xmit: %d+%d\n", idx, nr_desc);
d7699f87 570
3bf61c55 571 return 0;
d7699f87
GFT
572}
573
574
3bf61c55
GFT
575static int
576jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 577{
d7699f87
GFT
578 struct jme_ring *txring = &(jme->txring[0]);
579
580 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
581 TX_RING_ALLOC_SIZE,
3bf61c55 582 &(txring->dmaalloc),
fcf45b4c
GFT
583 GFP_ATOMIC);
584
4330c2f2
GFT
585 if(!txring->alloc) {
586 txring->desc = NULL;
587 txring->dmaalloc = 0;
588 txring->dma = 0;
d7699f87 589 return -ENOMEM;
4330c2f2 590 }
d7699f87
GFT
591
592 /*
593 * 16 Bytes align
594 */
3bf61c55
GFT
595 txring->desc = (void*)ALIGN((unsigned long)(txring->alloc),
596 RING_DESC_ALIGN);
4330c2f2 597 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87
GFT
598 txring->next_to_use = 0;
599 txring->next_to_clean = 0;
79ce639c 600 atomic_set(&txring->nr_free, RING_DESC_NR);
d7699f87
GFT
601
602 /*
603 * Initiallize Transmit Descriptors
604 */
605 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE);
3bf61c55
GFT
606 memset(txring->bufinf, 0,
607 sizeof(struct jme_buffer_info) * RING_DESC_NR);
d7699f87
GFT
608
609 return 0;
610}
611
3bf61c55
GFT
612static void
613jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
614{
615 int i;
616 struct jme_ring *txring = &(jme->txring[0]);
4330c2f2 617 struct jme_buffer_info *txbi = txring->bufinf;
d7699f87
GFT
618
619 if(txring->alloc) {
3bf61c55 620 for(i = 0 ; i < RING_DESC_NR ; ++i) {
4330c2f2
GFT
621 txbi = txring->bufinf + i;
622 if(txbi->skb) {
623 dev_kfree_skb(txbi->skb);
624 txbi->skb = NULL;
d7699f87 625 }
3bf61c55
GFT
626 txbi->mapping = 0;
627 txbi->len = 0;
628 txbi->nr_desc = 0;
d7699f87
GFT
629 }
630
631 dma_free_coherent(&(jme->pdev->dev),
632 TX_RING_ALLOC_SIZE,
633 txring->alloc,
634 txring->dmaalloc);
3bf61c55
GFT
635
636 txring->alloc = NULL;
637 txring->desc = NULL;
638 txring->dmaalloc = 0;
639 txring->dma = 0;
d7699f87 640 }
3bf61c55
GFT
641 txring->next_to_use = 0;
642 txring->next_to_clean = 0;
79ce639c 643 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
644
645}
646
3bf61c55
GFT
647__always_inline static void
648jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
649{
650 /*
651 * Select Queue 0
652 */
653 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
654
655 /*
656 * Setup TX Queue 0 DMA Bass Address
657 */
fcf45b4c 658 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 659 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 660 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
661
662 /*
663 * Setup TX Descptor Count
664 */
665 jwrite32(jme, JME_TXQDC, RING_DESC_NR);
666
667 /*
668 * Enable TX Engine
669 */
670 wmb();
4330c2f2
GFT
671 jwrite32(jme, JME_TXCS, jme->reg_txcs |
672 TXCS_SELECT_QUEUE0 |
673 TXCS_ENABLE);
d7699f87
GFT
674
675}
676
3bf61c55 677__always_inline static void
29bdd921
GFT
678jme_restart_tx_engine(struct jme_adapter *jme)
679{
680 /*
681 * Restart TX Engine
682 */
683 jwrite32(jme, JME_TXCS, jme->reg_txcs |
684 TXCS_SELECT_QUEUE0 |
685 TXCS_ENABLE);
686}
687
688__always_inline static void
3bf61c55 689jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
690{
691 int i;
692 __u32 val;
693
694 /*
695 * Disable TX Engine
696 */
fcf45b4c 697 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
d7699f87
GFT
698
699 val = jread32(jme, JME_TXCS);
700 for(i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i)
701 {
fcf45b4c 702 mdelay(1);
d7699f87
GFT
703 val = jread32(jme, JME_TXCS);
704 }
705
8c198884 706 if(!i) {
4330c2f2 707 jeprintk(jme->dev->name, "Disable TX engine timeout.\n");
8c198884
GFT
708 jme_reset_mac_processor(jme);
709 }
d7699f87
GFT
710
711
712}
713
3bf61c55
GFT
714static void
715jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87
GFT
716{
717 struct jme_ring *rxring = jme->rxring;
3bf61c55 718 register volatile struct rxdesc* rxdesc = rxring->desc;
4330c2f2
GFT
719 struct jme_buffer_info *rxbi = rxring->bufinf;
720 rxdesc += i;
721 rxbi += i;
722
723 rxdesc->dw[0] = 0;
724 rxdesc->dw[1] = 0;
3bf61c55 725 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
726 rxdesc->desc1.bufaddrl = cpu_to_le32(
727 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55
GFT
728 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
729 if(jme->dev->features & NETIF_F_HIGHDMA)
730 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 731 wmb();
3bf61c55 732 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
733}
734
3bf61c55
GFT
735static int
736jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
737{
738 struct jme_ring *rxring = &(jme->rxring[0]);
739 struct jme_buffer_info *rxbi = rxring->bufinf;
740 unsigned long offset;
741 struct sk_buff* skb;
742
79ce639c
GFT
743 skb = netdev_alloc_skb(jme->dev,
744 jme->dev->mtu + RX_EXTRA_LEN);
4330c2f2
GFT
745 if(unlikely(!skb))
746 return -ENOMEM;
3bf61c55
GFT
747
748 if(unlikely(skb_is_nonlinear(skb))) {
749 dprintk(jme->dev->name,
750 "Allocated skb fragged(%d).\n",
751 skb_shinfo(skb)->nr_frags);
4330c2f2
GFT
752 dev_kfree_skb(skb);
753 return -ENOMEM;
754 }
755
3bf61c55
GFT
756 if(unlikely(offset =
757 (unsigned long)(skb->data)
79ce639c 758 & ((unsigned long)RX_BUF_DMA_ALIGN - 1)))
4330c2f2 759 skb_reserve(skb, RX_BUF_DMA_ALIGN - offset);
4330c2f2
GFT
760
761 rxbi += i;
762 rxbi->skb = skb;
3bf61c55 763 rxbi->len = skb_tailroom(skb);
4330c2f2
GFT
764 rxbi->mapping = pci_map_single(jme->pdev,
765 skb->data,
3bf61c55 766 rxbi->len,
4330c2f2
GFT
767 PCI_DMA_FROMDEVICE);
768
769 return 0;
770}
771
3bf61c55
GFT
772static void
773jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
774{
775 struct jme_ring *rxring = &(jme->rxring[0]);
776 struct jme_buffer_info *rxbi = rxring->bufinf;
777 rxbi += i;
778
779 if(rxbi->skb) {
780 pci_unmap_single(jme->pdev,
781 rxbi->mapping,
3bf61c55 782 rxbi->len,
4330c2f2
GFT
783 PCI_DMA_FROMDEVICE);
784 dev_kfree_skb(rxbi->skb);
785 rxbi->skb = NULL;
786 rxbi->mapping = 0;
3bf61c55 787 rxbi->len = 0;
4330c2f2
GFT
788 }
789}
790
3bf61c55
GFT
791static void
792jme_free_rx_resources(struct jme_adapter *jme)
793{
794 int i;
795 struct jme_ring *rxring = &(jme->rxring[0]);
796
797 if(rxring->alloc) {
798 for(i = 0 ; i < RING_DESC_NR ; ++i)
799 jme_free_rx_buf(jme, i);
800
801 dma_free_coherent(&(jme->pdev->dev),
802 RX_RING_ALLOC_SIZE,
803 rxring->alloc,
804 rxring->dmaalloc);
805 rxring->alloc = NULL;
806 rxring->desc = NULL;
807 rxring->dmaalloc = 0;
808 rxring->dma = 0;
809 }
810 rxring->next_to_use = 0;
811 rxring->next_to_clean = 0;
812}
813
814static int
815jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
816{
817 int i;
818 struct jme_ring *rxring = &(jme->rxring[0]);
819
820 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
821 RX_RING_ALLOC_SIZE,
3bf61c55 822 &(rxring->dmaalloc),
fcf45b4c 823 GFP_ATOMIC);
4330c2f2
GFT
824 if(!rxring->alloc) {
825 rxring->desc = NULL;
826 rxring->dmaalloc = 0;
827 rxring->dma = 0;
d7699f87 828 return -ENOMEM;
4330c2f2 829 }
d7699f87
GFT
830
831 /*
832 * 16 Bytes align
833 */
3bf61c55
GFT
834 rxring->desc = (void*)ALIGN((unsigned long)(rxring->alloc),
835 RING_DESC_ALIGN);
4330c2f2 836 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87
GFT
837 rxring->next_to_use = 0;
838 rxring->next_to_clean = 0;
839
d7699f87
GFT
840 /*
841 * Initiallize Receive Descriptors
842 */
843 for(i = 0 ; i < RING_DESC_NR ; ++i) {
3bf61c55
GFT
844 if(unlikely(jme_make_new_rx_buf(jme, i))) {
845 jme_free_rx_resources(jme);
846 return -ENOMEM;
847 }
d7699f87
GFT
848
849 jme_set_clean_rxdesc(jme, i);
850 }
851
d7699f87
GFT
852 return 0;
853}
854
3bf61c55
GFT
855__always_inline static void
856jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 857{
d7699f87
GFT
858 /*
859 * Setup RX DMA Bass Address
860 */
fcf45b4c 861 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
3bf61c55 862 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fcf45b4c 863 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
864
865 /*
866 * Setup RX Descptor Count
867 */
868 jwrite32(jme, JME_RXQDC, RING_DESC_NR);
869
3bf61c55 870 /*
d7699f87
GFT
871 * Setup Unicast Filter
872 */
873 jme_set_multi(jme->dev);
874
875 /*
876 * Enable RX Engine
877 */
878 wmb();
79ce639c 879 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
880 RXCS_QUEUESEL_Q0 |
881 RXCS_ENABLE |
882 RXCS_QST);
d7699f87
GFT
883}
884
3bf61c55
GFT
885__always_inline static void
886jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
887{
888 /*
3bf61c55 889 * Start RX Engine
4330c2f2 890 */
79ce639c 891 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
892 RXCS_QUEUESEL_Q0 |
893 RXCS_ENABLE |
894 RXCS_QST);
895}
896
897
3bf61c55
GFT
898__always_inline static void
899jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
900{
901 int i;
902 __u32 val;
903
904 /*
905 * Disable RX Engine
906 */
29bdd921 907 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
d7699f87
GFT
908
909 val = jread32(jme, JME_RXCS);
910 for(i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i)
911 {
29bdd921 912 mdelay(1);
d7699f87
GFT
913 val = jread32(jme, JME_RXCS);
914 }
915
916 if(!i)
4330c2f2 917 jeprintk(jme->dev->name, "Disable RX engine timeout.\n");
d7699f87
GFT
918
919}
920
3bf61c55 921static void
42b1055e 922jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 923{
d7699f87 924 struct jme_ring *rxring = &(jme->rxring[0]);
3bf61c55
GFT
925 volatile struct rxdesc *rxdesc = rxring->desc;
926 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 927 struct sk_buff *skb;
3bf61c55 928 int framesize;
d7699f87 929
3bf61c55
GFT
930 rxdesc += idx;
931 rxbi += idx;
d7699f87 932
3bf61c55
GFT
933 skb = rxbi->skb;
934 pci_dma_sync_single_for_cpu(jme->pdev,
935 rxbi->mapping,
936 rxbi->len,
937 PCI_DMA_FROMDEVICE);
938
939 if(unlikely(jme_make_new_rx_buf(jme, idx))) {
940 pci_dma_sync_single_for_device(jme->pdev,
941 rxbi->mapping,
942 rxbi->len,
943 PCI_DMA_FROMDEVICE);
944
945 ++(NET_STAT(jme).rx_dropped);
946 }
947 else {
948 framesize = le16_to_cpu(rxdesc->descwb.framesize)
949 - RX_PREPAD_SIZE;
950
951 skb_reserve(skb, RX_PREPAD_SIZE);
952 skb_put(skb, framesize);
953 skb->protocol = eth_type_trans(skb, jme->dev);
954
42b1055e
GFT
955 if((rxdesc->descwb.flags &
956 (RXWBFLAG_TCPON |
957 RXWBFLAG_UDPON |
958 RXWBFLAG_IPV4)))
8c198884 959 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921
GFT
960 else
961 skb->ip_summed = CHECKSUM_NONE;
8c198884 962
42b1055e
GFT
963 if(jme->vlgrp && (rxdesc->descwb.flags & RXWBFLAG_TAGON))
964 vlan_hwaccel_rx(skb, jme->vlgrp,
965 le32_to_cpu(rxdesc->descwb.vlan));
966 else
967 netif_rx(skb);
3bf61c55
GFT
968
969 if(le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST_MUL)
970 ++(NET_STAT(jme).multicast);
971
972 jme->dev->last_rx = jiffies;
973 NET_STAT(jme).rx_bytes += framesize;
974 ++(NET_STAT(jme).rx_packets);
975 }
976
977 jme_set_clean_rxdesc(jme, idx);
978
979}
980
981static int
8c198884
GFT
982jme_rxsum_bad(struct jme_adapter *jme, __u16 flags)
983{
79ce639c
GFT
984 if(unlikely((flags & RXWBFLAG_TCPON) &&
985 !(flags & RXWBFLAG_TCPCS))) {
986 csum_dbg(jme->dev->name, "TCP Checksum error.\n");
987 return 1;
988 }
989 else if(unlikely((flags & RXWBFLAG_UDPON) &&
990 !(flags & RXWBFLAG_UDPCS))) {
991 csum_dbg(jme->dev->name, "UDP Checksum error.\n");
992 return 1;
993 }
994 else if(unlikely((flags & RXWBFLAG_IPV4) &&
995 !(flags & RXWBFLAG_IPCS))) {
996 csum_dbg(jme->dev->name, "IPV4 Checksum error.\n");
997 return 1;
8c198884
GFT
998 }
999 else {
1000 return 0;
1001 }
1002}
1003
1004static int
3bf61c55
GFT
1005jme_process_receive(struct jme_adapter *jme, int limit)
1006{
1007 struct jme_ring *rxring = &(jme->rxring[0]);
1008 volatile struct rxdesc *rxdesc = rxring->desc;
1009 int i, j, ccnt, desccnt;
1010
1011 i = rxring->next_to_clean;
1012 while( limit-- > 0 )
d7699f87 1013 {
3bf61c55
GFT
1014 rxdesc = rxring->desc;
1015 rxdesc += i;
1016
4330c2f2 1017 if((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
3bf61c55
GFT
1018 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1019 goto out;
d7699f87 1020
4330c2f2
GFT
1021 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1022
3bf61c55 1023 rx_dbg(jme->dev->name, "RX: Cleaning %d\n", i);
4330c2f2 1024
8c198884
GFT
1025 if(unlikely(desccnt > 1 ||
1026 rxdesc->descwb.errstat & RXWBERR_ALLERR ||
1027 jme_rxsum_bad(jme, rxdesc->descwb.flags))) {
d7699f87 1028
3bf61c55
GFT
1029 if(rxdesc->descwb.errstat & RXWBERR_CRCERR)
1030 ++(NET_STAT(jme).rx_crc_errors);
1031 else if(rxdesc->descwb.errstat & RXWBERR_OVERUN)
1032 ++(NET_STAT(jme).rx_fifo_errors);
1033 else
1034 ++(NET_STAT(jme).rx_errors);
4330c2f2 1035
79ce639c
GFT
1036 if(desccnt > 1) {
1037 rx_dbg(jme->dev->name,
1038 "RX: More than one(%d) descriptor, "
1039 "framelen=%d\n",
1040 desccnt, le16_to_cpu(rxdesc->descwb.framesize));
3bf61c55 1041 limit -= desccnt - 1;
79ce639c 1042 }
4330c2f2 1043
3bf61c55 1044 for(j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2
GFT
1045 jme_set_clean_rxdesc(jme, j);
1046
1047 if(unlikely(++j == RING_DESC_NR))
1048 j = 0;
1049 }
3bf61c55 1050
d7699f87
GFT
1051 }
1052 else {
42b1055e 1053 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1054 }
4330c2f2 1055
3bf61c55
GFT
1056 if((i += desccnt) >= RING_DESC_NR)
1057 i -= RING_DESC_NR;
1058 }
4330c2f2 1059
3bf61c55
GFT
1060out:
1061 rx_dbg(jme->dev->name, "RX: Stop at %d\n", i);
1062 rx_dbg(jme->dev->name, "RX: RXNDA offset %d\n",
1063 (jread32(jme, JME_RXNDA) - jread32(jme, JME_RXDBA_LO))
1064 >> 4);
4330c2f2 1065
3bf61c55 1066 rxring->next_to_clean = i;
4330c2f2 1067
3bf61c55 1068 return limit > 0 ? limit : 0;
4330c2f2 1069
3bf61c55 1070}
d7699f87 1071
3bf61c55 1072static void
79ce639c
GFT
1073jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1074{
1075 if(likely(atmp == dpi->cur))
1076 return;
1077
1078 if(dpi->attempt == atmp) {
1079 ++(dpi->cnt);
1080 }
1081 else {
1082 dpi->attempt = atmp;
1083 dpi->cnt = 0;
1084 }
1085
1086}
1087
1088static void
1089jme_dynamic_pcc(struct jme_adapter *jme)
1090{
1091 register struct dynpcc_info *dpi = &(jme->dpi);
1092
1093 if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1094 jme_attempt_pcc(dpi, PCC_P3);
1095 else if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P2_THRESHOLD
1096 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1097 jme_attempt_pcc(dpi, PCC_P2);
1098 else
1099 jme_attempt_pcc(dpi, PCC_P1);
1100
1101 if(unlikely(dpi->attempt != dpi->cur && dpi->cnt > 20)) {
1102 jme_set_rx_pcc(jme, dpi->attempt);
1103 dpi->cur = dpi->attempt;
1104 dpi->cnt = 0;
1105 }
1106}
1107
1108static void
1109jme_start_pcc_timer(struct jme_adapter *jme)
1110{
1111 struct dynpcc_info *dpi = &(jme->dpi);
1112 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1113 dpi->last_pkts = NET_STAT(jme).rx_packets;
1114 dpi->intr_cnt = 0;
1115 jwrite32(jme, JME_TMCSR,
1116 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1117}
1118
1119static void
29bdd921
GFT
1120jme_stop_pcc_timer(struct jme_adapter *jme)
1121{
1122 jwrite32(jme, JME_TMCSR, 0);
1123}
1124
1125static void
79ce639c
GFT
1126jme_pcc_tasklet(unsigned long arg)
1127{
1128 struct jme_adapter *jme = (struct jme_adapter*)arg;
1129 struct net_device *netdev = jme->dev;
1130
29bdd921
GFT
1131
1132 if(unlikely(netif_queue_stopped(netdev) ||
1133 (atomic_read(&jme->link_changing) != 1)
1134 )) {
1135 jme_stop_pcc_timer(jme);
79ce639c
GFT
1136 return;
1137 }
29bdd921 1138
79ce639c
GFT
1139 jme_dynamic_pcc(jme);
1140 jme_start_pcc_timer(jme);
1141}
1142
1143static void
3bf61c55
GFT
1144jme_link_change_tasklet(unsigned long arg)
1145{
1146 struct jme_adapter *jme = (struct jme_adapter*)arg;
fcf45b4c
GFT
1147 struct net_device *netdev = jme->dev;
1148 int timeout = WAIT_TASKLET_TIMEOUT;
1149 int rc;
1150
1151 if(!atomic_dec_and_test(&jme->link_changing))
1152 goto out;
1153
29bdd921 1154 if(jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1155 goto out;
1156
29bdd921 1157 jme->old_mtu = netdev->mtu;
fcf45b4c
GFT
1158 netif_stop_queue(netdev);
1159
1160 while(--timeout > 0 &&
1161 (
1162 atomic_read(&jme->rx_cleaning) != 1 ||
1163 atomic_read(&jme->tx_cleaning) != 1
1164 )) {
1165
1166 mdelay(1);
1167 }
1168
1169 if(netif_carrier_ok(netdev)) {
29bdd921 1170 jme_stop_pcc_timer(jme);
fcf45b4c
GFT
1171 jme_reset_mac_processor(jme);
1172 jme_free_rx_resources(jme);
1173 jme_free_tx_resources(jme);
1174 }
1175
1176 jme_check_link(netdev, 0);
1177 if(netif_carrier_ok(netdev)) {
1178 rc = jme_setup_rx_resources(jme);
1179 if(rc) {
1180 jeprintk(netdev->name,
1181 "Allocating resources for RX error"
1182 ", Device STOPPED!\n");
1183 goto out;
1184 }
1185
1186
1187 rc = jme_setup_tx_resources(jme);
1188 if(rc) {
1189 jeprintk(netdev->name,
1190 "Allocating resources for TX error"
1191 ", Device STOPPED!\n");
1192 goto err_out_free_rx_resources;
1193 }
1194
1195 jme_enable_rx_engine(jme);
1196 jme_enable_tx_engine(jme);
1197
1198 netif_start_queue(netdev);
79ce639c 1199 jme_start_pcc_timer(jme);
fcf45b4c
GFT
1200 }
1201
1202 goto out;
1203
1204err_out_free_rx_resources:
1205 jme_free_rx_resources(jme);
1206out:
1207 atomic_inc(&jme->link_changing);
3bf61c55 1208}
d7699f87 1209
3bf61c55
GFT
1210static void
1211jme_rx_clean_tasklet(unsigned long arg)
1212{
1213 struct jme_adapter *jme = (struct jme_adapter*)arg;
79ce639c 1214 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1215
79ce639c 1216 if(unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
fcf45b4c 1217 goto out;
42b1055e 1218
79ce639c 1219 if(unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1220 goto out;
1221
1222 if(unlikely(netif_queue_stopped(jme->dev)))
1223 goto out;
1224
3bf61c55 1225 jme_process_receive(jme, RING_DESC_NR);
79ce639c 1226 ++(dpi->intr_cnt);
fcf45b4c
GFT
1227
1228out:
1229 atomic_inc(&jme->rx_cleaning);
1230}
1231
1232static void
1233jme_rx_empty_tasklet(unsigned long arg)
1234{
1235 struct jme_adapter *jme = (struct jme_adapter*)arg;
1236
79ce639c 1237 if(unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1238 return;
1239
1240 if(unlikely(netif_queue_stopped(jme->dev)))
1241 return;
1242
29bdd921
GFT
1243 queue_dbg(jme->dev->name, "RX Queue empty!\n");
1244
fcf45b4c
GFT
1245 jme_rx_clean_tasklet(arg);
1246 jme_restart_rx_engine(jme);
4330c2f2
GFT
1247}
1248
3bf61c55
GFT
1249static void
1250jme_tx_clean_tasklet(unsigned long arg)
4330c2f2
GFT
1251{
1252 struct jme_adapter *jme = (struct jme_adapter*)arg;
3bf61c55
GFT
1253 struct jme_ring *txring = &(jme->txring[0]);
1254 volatile struct txdesc *txdesc = txring->desc;
1255 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
8c198884 1256 int i, j, cnt = 0, max, err;
3bf61c55 1257
79ce639c 1258 if(unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1259 goto out;
1260
79ce639c 1261 if(unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1262 goto out;
1263
1264 if(unlikely(netif_queue_stopped(jme->dev)))
1265 goto out;
1266
79ce639c 1267 max = RING_DESC_NR - atomic_read(&txring->nr_free);
3bf61c55
GFT
1268
1269 tx_dbg(jme->dev->name, "Tx Tasklet: In\n");
1270
1271 for(i = txring->next_to_clean ; cnt < max ; ) {
1272
1273 ctxbi = txbi + i;
1274
8c198884
GFT
1275 if(ctxbi->skb && !(txdesc[i].descwb.flags & TXWBFLAG_OWN)) {
1276
1277 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55
GFT
1278
1279 tx_dbg(jme->dev->name,
1280 "Tx Tasklet: Clean %d+%d\n",
1281 i, ctxbi->nr_desc);
1282
1283 for(j = 1 ; j < ctxbi->nr_desc ; ++j) {
1284 ttxbi = txbi + ((i + j) & (RING_DESC_NR - 1));
1285 txdesc[(i+j)&(RING_DESC_NR-1)].dw[0] = 0;
1286
1287 pci_unmap_single(jme->pdev,
1288 ttxbi->mapping,
1289 ttxbi->len,
1290 PCI_DMA_TODEVICE);
1291
8c198884
GFT
1292 if(likely(!err))
1293 NET_STAT(jme).tx_bytes += ttxbi->len;
1294
3bf61c55
GFT
1295 ttxbi->mapping = 0;
1296 ttxbi->len = 0;
1297 }
1298
1299 dev_kfree_skb(ctxbi->skb);
1300 ctxbi->skb = NULL;
1301
1302 cnt += ctxbi->nr_desc;
1303
8c198884
GFT
1304 if(unlikely(err))
1305 ++(NET_STAT(jme).tx_carrier_errors);
1306 else
1307 ++(NET_STAT(jme).tx_packets);
3bf61c55
GFT
1308 }
1309 else {
1310 if(!ctxbi->skb)
1311 tx_dbg(jme->dev->name,
1312 "Tx Tasklet:"
1313 " Stoped due to no skb.\n");
1314 else
1315 tx_dbg(jme->dev->name,
1316 "Tx Tasklet:"
1317 "Stoped due to not done.\n");
1318 break;
1319 }
1320
1321 if(unlikely((i += ctxbi->nr_desc) >= RING_DESC_NR))
1322 i -= RING_DESC_NR;
1323
1324 ctxbi->nr_desc = 0;
d7699f87
GFT
1325 }
1326
3bf61c55
GFT
1327 tx_dbg(jme->dev->name,
1328 "Tx Tasklet: Stop %d Jiffies %lu\n",
1329 i, jiffies);
1330 txring->next_to_clean = i;
1331
79ce639c 1332 atomic_add(cnt, &txring->nr_free);
3bf61c55 1333
fcf45b4c
GFT
1334out:
1335 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1336}
1337
79ce639c
GFT
1338static void
1339jme_intr_msi(struct jme_adapter *jme, __u32 intrstat)
d7699f87 1340{
3bf61c55
GFT
1341 /*
1342 * Disable interrupt
1343 */
1344 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1345
29bdd921
GFT
1346 /*
1347 * Write 1 clear interrupt status
1348 */
1349 jwrite32f(jme, JME_IEVE, intrstat);
1350
79ce639c 1351 if(intrstat & (INTR_LINKCH | INTR_SWINTR)) {
3bf61c55 1352 tasklet_schedule(&jme->linkch_task);
29bdd921 1353 goto out_reenable;
fcf45b4c 1354 }
d7699f87 1355
79ce639c
GFT
1356 if(intrstat & INTR_TMINTR)
1357 tasklet_schedule(&jme->pcc_task);
1358
fcf45b4c
GFT
1359 if(intrstat & INTR_RX0EMP)
1360 tasklet_schedule(&jme->rxempty_task);
d7699f87 1361
fcf45b4c 1362 if(intrstat & (INTR_PCCRX0TO | INTR_PCCRX0))
4330c2f2 1363 tasklet_schedule(&jme->rxclean_task);
d7699f87 1364
3bf61c55 1365 if(intrstat & (INTR_PCCTXTO | INTR_PCCTX))
4330c2f2 1366 tasklet_schedule(&jme->txclean_task);
d7699f87 1367
4330c2f2 1368 if((intrstat & ~INTR_ENABLE) != 0) {
3bf61c55
GFT
1369 /*
1370 * Some interrupt not handled
1371 * but not enabled also (for debug)
1372 */
4330c2f2 1373 }
d7699f87 1374
29bdd921 1375out_reenable:
3bf61c55 1376 /*
fcf45b4c 1377 * Re-enable interrupt
3bf61c55 1378 */
fcf45b4c 1379 jwrite32f(jme, JME_IENS, INTR_ENABLE);
3bf61c55 1380
79ce639c
GFT
1381
1382}
1383
1384static irqreturn_t
1385jme_intr(int irq, void *dev_id)
1386{
1387 struct net_device *netdev = dev_id;
1388 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c
GFT
1389 __u32 intrstat;
1390
1391 intrstat = jread32(jme, JME_IEVE);
1392
1393 /*
1394 * Check if it's really an interrupt for us
1395 */
29bdd921
GFT
1396 if(unlikely(intrstat == 0))
1397 return IRQ_NONE;
79ce639c
GFT
1398
1399 /*
1400 * Check if the device still exist
1401 */
29bdd921
GFT
1402 if(unlikely(intrstat == ~((typeof(intrstat))0)))
1403 return IRQ_NONE;
79ce639c
GFT
1404
1405 jme_intr_msi(jme, intrstat);
1406
29bdd921 1407 return IRQ_HANDLED;
d7699f87
GFT
1408}
1409
79ce639c
GFT
1410static irqreturn_t
1411jme_msi(int irq, void *dev_id)
1412{
1413 struct net_device *netdev = dev_id;
1414 struct jme_adapter *jme = netdev_priv(netdev);
1415 __u32 intrstat;
1416
1417 pci_dma_sync_single_for_cpu(jme->pdev,
1418 jme->shadow_dma,
1419 sizeof(__u32) * SHADOW_REG_NR,
1420 PCI_DMA_FROMDEVICE);
1421 intrstat = jme->shadow_regs[SHADOW_IEVE];
1422 jme->shadow_regs[SHADOW_IEVE] = 0;
1423
1424 jme_intr_msi(jme, intrstat);
1425
1426 return IRQ_HANDLED;
1427}
1428
1429
1430static void
1431jme_reset_link(struct jme_adapter *jme)
1432{
1433 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1434}
1435
fcf45b4c
GFT
1436static void
1437jme_restart_an(struct jme_adapter *jme)
1438{
1439 __u32 bmcr;
79ce639c 1440 unsigned long flags;
fcf45b4c 1441
79ce639c 1442 spin_lock_irqsave(&jme->phy_lock, flags);
fcf45b4c
GFT
1443 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1444 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1445 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
79ce639c
GFT
1446 spin_unlock_irqrestore(&jme->phy_lock, flags);
1447}
1448
1449static int
1450jme_request_irq(struct jme_adapter *jme)
1451{
1452 int rc;
1453 struct net_device *netdev = jme->dev;
1454 irq_handler_t handler = jme_intr;
1455 int irq_flags = IRQF_SHARED;
1456
1457 if (!pci_enable_msi(jme->pdev)) {
1458 jme->flags |= JME_FLAG_MSI;
1459 handler = jme_msi;
1460 irq_flags = 0;
1461 }
1462
1463 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1464 netdev);
1465 if(rc) {
1466 jeprintk(netdev->name,
1467 "Unable to allocate %s interrupt (return: %d)\n",
29bdd921 1468 jme->flags & JME_FLAG_MSI ? "MSI":"INTx", rc);
79ce639c
GFT
1469
1470 if(jme->flags & JME_FLAG_MSI) {
1471 pci_disable_msi(jme->pdev);
1472 jme->flags &= ~JME_FLAG_MSI;
1473 }
1474 }
1475 else {
1476 netdev->irq = jme->pdev->irq;
1477 }
1478
1479 return rc;
1480}
1481
1482static void
1483jme_free_irq(struct jme_adapter *jme)
1484{
1485 free_irq(jme->pdev->irq, jme->dev);
1486 if (jme->flags & JME_FLAG_MSI) {
1487 pci_disable_msi(jme->pdev);
1488 jme->flags &= ~JME_FLAG_MSI;
1489 jme->dev->irq = jme->pdev->irq;
1490 }
fcf45b4c
GFT
1491}
1492
3bf61c55
GFT
1493static int
1494jme_open(struct net_device *netdev)
d7699f87
GFT
1495{
1496 struct jme_adapter *jme = netdev_priv(netdev);
fcf45b4c
GFT
1497 int rc, timeout = 100;
1498
1499 while(
1500 --timeout > 0 &&
1501 (
1502 atomic_read(&jme->link_changing) != 1 ||
1503 atomic_read(&jme->rx_cleaning) != 1 ||
1504 atomic_read(&jme->tx_cleaning) != 1
1505 )
1506 )
1507 msleep(10);
1508
79ce639c
GFT
1509 if(!timeout) {
1510 rc = -EBUSY;
1511 goto err_out;
1512 }
1513
42b1055e 1514 jme_clear_pm(jme);
fcf45b4c 1515 jme_reset_mac_processor(jme);
d7699f87 1516
79ce639c
GFT
1517 rc = jme_request_irq(jme);
1518 if(rc)
4330c2f2 1519 goto err_out;
79ce639c 1520
4330c2f2 1521 jme_enable_shadow(jme);
d7699f87 1522 jme_start_irq(jme);
42b1055e
GFT
1523
1524 if(jme->flags & JME_FLAG_SSET)
1525 jme_set_settings(netdev, &jme->old_ecmd);
1526 else
1527 jme_reset_phy_processor(jme);
1528
29bdd921 1529 jme_reset_link(jme);
d7699f87
GFT
1530
1531 return 0;
1532
d7699f87
GFT
1533err_out:
1534 netif_stop_queue(netdev);
1535 netif_carrier_off(netdev);
4330c2f2 1536 return rc;
d7699f87
GFT
1537}
1538
42b1055e
GFT
1539static void
1540jme_set_100m_half(struct jme_adapter *jme)
1541{
1542 __u32 bmcr, tmp;
1543
1544 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1545 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1546 BMCR_SPEED1000 | BMCR_FULLDPLX);
1547 tmp |= BMCR_SPEED100;
1548
1549 if (bmcr != tmp)
1550 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1551
1552 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1553}
1554
1555static void
1556jme_phy_off(struct jme_adapter *jme)
1557{
1558 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1559}
1560
1561
3bf61c55
GFT
1562static int
1563jme_close(struct net_device *netdev)
d7699f87
GFT
1564{
1565 struct jme_adapter *jme = netdev_priv(netdev);
1566
1567 netif_stop_queue(netdev);
1568 netif_carrier_off(netdev);
1569
1570 jme_stop_irq(jme);
4330c2f2 1571 jme_disable_shadow(jme);
79ce639c 1572 jme_free_irq(jme);
d7699f87 1573
4330c2f2
GFT
1574 tasklet_kill(&jme->linkch_task);
1575 tasklet_kill(&jme->txclean_task);
1576 tasklet_kill(&jme->rxclean_task);
fcf45b4c 1577 tasklet_kill(&jme->rxempty_task);
8c198884
GFT
1578
1579 jme_reset_mac_processor(jme);
d7699f87
GFT
1580 jme_free_rx_resources(jme);
1581 jme_free_tx_resources(jme);
42b1055e
GFT
1582 jme->phylink = 0;
1583
1584 if(jme->reg_pmcs) {
1585 jme_set_100m_half(jme);
1586 pci_enable_wake(jme->pdev, PCI_D0, true);
1587 pci_enable_wake(jme->pdev, PCI_D3hot, true);
1588 pci_enable_wake(jme->pdev, PCI_D3cold, true);
1589 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1590 }
1591 else {
1592 jme_phy_off(jme);
1593 }
d7699f87
GFT
1594
1595 return 0;
1596}
1597
3bf61c55
GFT
1598/*
1599 * This function is already protected by netif_tx_lock()
1600 */
1601static int
1602jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87
GFT
1603{
1604 struct jme_adapter *jme = netdev_priv(netdev);
3bf61c55 1605 int rc;
d7699f87 1606
fcf45b4c
GFT
1607 if(unlikely(netif_queue_stopped(jme->dev)))
1608 return NETDEV_TX_BUSY;
1609
79ce639c
GFT
1610#if 0
1611/*Testing*/
1612 ("jme", "Frags: %d Headlen: %d Len: %d Sum:%d\n",
1613 skb_shinfo(skb)->nr_frags,
1614 skb_headlen(skb),
1615 skb->len,
1616 skb->ip_summed);
1617/*********/
1618#endif
1619
3bf61c55 1620 rc = jme_set_new_txdesc(jme, skb);
d7699f87 1621
3bf61c55
GFT
1622 if(unlikely(rc != NETDEV_TX_OK))
1623 return rc;
d7699f87 1624
4330c2f2
GFT
1625 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1626 TXCS_SELECT_QUEUE0 |
1627 TXCS_QUEUE0S |
1628 TXCS_ENABLE);
d7699f87
GFT
1629 netdev->trans_start = jiffies;
1630
4330c2f2 1631 return NETDEV_TX_OK;
d7699f87
GFT
1632}
1633
3bf61c55
GFT
1634static int
1635jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87
GFT
1636{
1637 struct jme_adapter *jme = netdev_priv(netdev);
1638 struct sockaddr *addr = p;
1639 __u32 val;
1640
1641 if(netif_running(netdev))
1642 return -EBUSY;
1643
fcf45b4c 1644 spin_lock(&jme->macaddr_lock);
d7699f87
GFT
1645 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1646
1647 val = addr->sa_data[3] << 24 |
1648 addr->sa_data[2] << 16 |
1649 addr->sa_data[1] << 8 |
1650 addr->sa_data[0];
4330c2f2 1651 jwrite32(jme, JME_RXUMA_LO, val);
d7699f87
GFT
1652 val = addr->sa_data[5] << 8 |
1653 addr->sa_data[4];
4330c2f2 1654 jwrite32(jme, JME_RXUMA_HI, val);
fcf45b4c 1655 spin_unlock(&jme->macaddr_lock);
d7699f87
GFT
1656
1657 return 0;
1658}
1659
3bf61c55
GFT
1660static void
1661jme_set_multi(struct net_device *netdev)
d7699f87 1662{
3bf61c55 1663 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1664 u32 mc_hash[2] = {};
d7699f87 1665 int i;
8c198884 1666 unsigned long flags;
d7699f87 1667
8c198884
GFT
1668 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1669
1670 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 1671
3bf61c55 1672 if (netdev->flags & IFF_PROMISC) {
8c198884 1673 jme->reg_rxmcs |= RXMCS_ALLFRAME;
3bf61c55
GFT
1674 }
1675 else if (netdev->flags & IFF_ALLMULTI) {
8c198884 1676 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
3bf61c55 1677 }
d7699f87 1678 else if(netdev->flags & IFF_MULTICAST) {
3bf61c55
GFT
1679 struct dev_mc_list *mclist;
1680 int bit_nr;
d7699f87 1681
8c198884 1682 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
3bf61c55
GFT
1683 for (i = 0, mclist = netdev->mc_list;
1684 mclist && i < netdev->mc_count;
1685 ++i, mclist = mclist->next) {
1686
d7699f87
GFT
1687 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1688 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
d7699f87
GFT
1689 }
1690
4330c2f2
GFT
1691 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1692 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
1693 }
1694
d7699f87 1695 wmb();
8c198884
GFT
1696 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1697
1698 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
d7699f87
GFT
1699}
1700
3bf61c55 1701static int
8c198884 1702jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 1703{
79ce639c
GFT
1704 struct jme_adapter *jme = netdev_priv(netdev);
1705
29bdd921
GFT
1706 if(new_mtu == jme->old_mtu)
1707 return 0;
1708
79ce639c 1709 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
42b1055e 1710 ((new_mtu) < IPV6_MIN_MTU))
79ce639c
GFT
1711 return -EINVAL;
1712
1713 if(new_mtu > 4000) {
1714 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1715 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1716 jme_restart_rx_engine(jme);
1717 }
1718 else {
1719 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1720 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1721 jme_restart_rx_engine(jme);
1722 }
1723
1724 if(new_mtu > 1900) {
1725 netdev->features &= ~NETIF_F_HW_CSUM;
1726 }
1727 else {
1728 netdev->features |= NETIF_F_HW_CSUM;
1729 }
1730
1731 netdev->mtu = new_mtu;
1732 jme_reset_link(jme);
1733
1734 return 0;
d7699f87
GFT
1735}
1736
3bf61c55 1737static void
8c198884
GFT
1738jme_tx_timeout(struct net_device *netdev)
1739{
1740 struct jme_adapter *jme = netdev_priv(netdev);
1741
1742 /*
1743 * Reset the link
1744 * And the link change will reinitiallize all RX/TX resources
1745 */
42b1055e 1746 jme->phylink = 0;
29bdd921 1747 jme_reset_link(jme);
8c198884
GFT
1748}
1749
1750static void
42b1055e
GFT
1751jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
1752{
1753 struct jme_adapter *jme = netdev_priv(netdev);
1754
1755 jme->vlgrp = grp;
1756}
1757
1758static void
3bf61c55
GFT
1759jme_get_drvinfo(struct net_device *netdev,
1760 struct ethtool_drvinfo *info)
d7699f87
GFT
1761{
1762 struct jme_adapter *jme = netdev_priv(netdev);
1763
1764 strcpy(info->driver, DRV_NAME);
1765 strcpy(info->version, DRV_VERSION);
1766 strcpy(info->bus_info, pci_name(jme->pdev));
1767}
1768
3bf61c55 1769static int
8c198884
GFT
1770jme_get_regs_len(struct net_device *netdev)
1771{
1772 return 0x400;
1773}
1774
1775static void
1776mmapio_memcpy(struct jme_adapter *jme, __u32 *p, __u32 reg, int len)
1777{
1778 int i;
1779
1780 for(i = 0 ; i < len ; i += 4)
79ce639c 1781 p[i >> 2] = jread32(jme, reg + i);
8c198884
GFT
1782
1783}
1784
1785static void
1786jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
1787{
1788 struct jme_adapter *jme = netdev_priv(netdev);
1789 __u32 *p32 = (__u32*)p;
1790
1791 memset(p, 0, 0x400);
1792
1793 regs->version = 1;
1794 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
1795
1796 p32 += 0x100 >> 2;
1797 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
1798
1799 p32 += 0x100 >> 2;
1800 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
1801
1802 p32 += 0x100 >> 2;
1803 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
1804
1805}
1806
1807static int
1808jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
1809{
1810 struct jme_adapter *jme = netdev_priv(netdev);
1811
1812 ecmd->use_adaptive_rx_coalesce = true;
1813 ecmd->tx_coalesce_usecs = PCC_TX_TO;
1814 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
1815
1816 switch(jme->dpi.cur) {
1817 case PCC_P1:
1818 ecmd->rx_coalesce_usecs = PCC_P1_TO;
1819 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
1820 break;
1821 case PCC_P2:
1822 ecmd->rx_coalesce_usecs = PCC_P2_TO;
1823 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
1824 break;
1825 case PCC_P3:
1826 ecmd->rx_coalesce_usecs = PCC_P3_TO;
1827 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
1828 break;
1829 default:
1830 break;
1831 }
1832
1833 return 0;
1834}
1835
79ce639c
GFT
1836/*
1837 * It's not actually for coalesce.
1838 * It changes internell FIFO related setting for testing.
1839 */
1840static int
1841jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
1842{
1843 struct jme_adapter *jme = netdev_priv(netdev);
1844
1845 if(ecmd->use_adaptive_rx_coalesce &&
1846 ecmd->use_adaptive_tx_coalesce &&
1847 ecmd->rx_coalesce_usecs == 250 &&
1848 (ecmd->rx_max_coalesced_frames_low == 16 ||
1849 ecmd->rx_max_coalesced_frames_low == 32 ||
1850 ecmd->rx_max_coalesced_frames_low == 64 ||
1851 ecmd->rx_max_coalesced_frames_low == 128)) {
1852 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1853 switch(ecmd->rx_max_coalesced_frames_low) {
1854 case 16:
1855 jme->reg_rxcs |= RXCS_FIFOTHNP_16QW;
1856 break;
1857 case 32:
1858 jme->reg_rxcs |= RXCS_FIFOTHNP_32QW;
1859 break;
1860 case 64:
1861 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1862 break;
1863 case 128:
1864 default:
1865 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1866 }
1867 jme_restart_rx_engine(jme);
1868 }
1869 else {
1870 return -EINVAL;
1871 }
1872
1873 return 0;
1874}
1875
8c198884
GFT
1876static void
1877jme_get_pauseparam(struct net_device *netdev,
1878 struct ethtool_pauseparam *ecmd)
1879{
1880 struct jme_adapter *jme = netdev_priv(netdev);
1881 unsigned long flags;
1882 __u32 val;
1883
1884 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
1885 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
1886
1887 spin_lock_irqsave(&jme->phy_lock, flags);
1888 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1889 spin_unlock_irqrestore(&jme->phy_lock, flags);
1890 ecmd->autoneg = (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
1891}
1892
1893static int
1894jme_set_pauseparam(struct net_device *netdev,
1895 struct ethtool_pauseparam *ecmd)
1896{
1897 struct jme_adapter *jme = netdev_priv(netdev);
1898 unsigned long flags;
1899 __u32 val;
1900
1901 if( ((jme->reg_txpfc & TXPFC_PF_EN) != 0) !=
1902 (ecmd->tx_pause != 0)) {
1903
1904 if(ecmd->tx_pause)
1905 jme->reg_txpfc |= TXPFC_PF_EN;
1906 else
1907 jme->reg_txpfc &= ~TXPFC_PF_EN;
1908
1909 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
1910 }
1911
1912 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1913 if( ((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) !=
1914 (ecmd->rx_pause != 0)) {
1915
1916 if(ecmd->rx_pause)
1917 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
1918 else
1919 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
1920
1921 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1922 }
1923 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1924
1925 spin_lock_irqsave(&jme->phy_lock, flags);
1926 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1927 if( ((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) !=
1928 (ecmd->autoneg != 0)) {
1929
1930 if(ecmd->autoneg)
1931 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1932 else
1933 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1934
1935 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE, val);
1936 }
1937 spin_unlock_irqrestore(&jme->phy_lock, flags);
1938
1939 return 0;
1940}
1941
29bdd921
GFT
1942static void
1943jme_get_wol(struct net_device *netdev,
1944 struct ethtool_wolinfo *wol)
1945{
1946 struct jme_adapter *jme = netdev_priv(netdev);
1947
1948 wol->supported = WAKE_MAGIC | WAKE_PHY;
1949
1950 wol->wolopts = 0;
1951
1952 if(jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1953 wol->wolopts |= WAKE_PHY;
1954
1955 if(jme->reg_pmcs & PMCS_MFEN)
1956 wol->wolopts |= WAKE_MAGIC;
1957
1958}
1959
1960static int
1961jme_set_wol(struct net_device *netdev,
1962 struct ethtool_wolinfo *wol)
1963{
1964 struct jme_adapter *jme = netdev_priv(netdev);
1965
1966 if(wol->wolopts & (WAKE_MAGICSECURE |
1967 WAKE_UCAST |
1968 WAKE_MCAST |
1969 WAKE_BCAST |
1970 WAKE_ARP))
1971 return -EOPNOTSUPP;
1972
1973 jme->reg_pmcs = 0;
1974
1975 if(wol->wolopts & WAKE_PHY)
1976 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
1977
1978 if(wol->wolopts & WAKE_MAGIC)
1979 jme->reg_pmcs |= PMCS_MFEN;
1980
42b1055e 1981
29bdd921
GFT
1982 return 0;
1983}
1984
8c198884 1985static int
3bf61c55
GFT
1986jme_get_settings(struct net_device *netdev,
1987 struct ethtool_cmd *ecmd)
d7699f87
GFT
1988{
1989 struct jme_adapter *jme = netdev_priv(netdev);
1990 int rc;
79ce639c 1991 unsigned long flags;
8c198884 1992
79ce639c 1993 spin_lock_irqsave(&jme->phy_lock, flags);
d7699f87 1994 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
79ce639c 1995 spin_unlock_irqrestore(&jme->phy_lock, flags);
d7699f87
GFT
1996 return rc;
1997}
1998
3bf61c55
GFT
1999static int
2000jme_set_settings(struct net_device *netdev,
2001 struct ethtool_cmd *ecmd)
d7699f87
GFT
2002{
2003 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2004 int rc, fdc=0;
fcf45b4c
GFT
2005 unsigned long flags;
2006
8c198884
GFT
2007 if(ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2008 return -EINVAL;
2009
79ce639c
GFT
2010 if(jme->mii_if.force_media &&
2011 ecmd->autoneg != AUTONEG_ENABLE &&
2012 (jme->mii_if.full_duplex != ecmd->duplex))
2013 fdc = 1;
2014
fcf45b4c 2015 spin_lock_irqsave(&jme->phy_lock, flags);
d7699f87 2016 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
fcf45b4c
GFT
2017 spin_unlock_irqrestore(&jme->phy_lock, flags);
2018
79ce639c
GFT
2019 if(!rc && fdc)
2020 jme_reset_link(jme);
2021
29bdd921
GFT
2022 if(!rc) {
2023 jme->flags |= JME_FLAG_SSET;
2024 jme->old_ecmd = *ecmd;
2025 }
2026
d7699f87
GFT
2027 return rc;
2028}
2029
3bf61c55
GFT
2030static __u32
2031jme_get_link(struct net_device *netdev)
2032{
d7699f87
GFT
2033 struct jme_adapter *jme = netdev_priv(netdev);
2034 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2035}
2036
8c198884
GFT
2037static u32
2038jme_get_rx_csum(struct net_device *netdev)
2039{
2040 struct jme_adapter *jme = netdev_priv(netdev);
2041
2042 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2043}
2044
2045static int
2046jme_set_rx_csum(struct net_device *netdev, u32 on)
2047{
2048 struct jme_adapter *jme = netdev_priv(netdev);
2049 unsigned long flags;
2050
2051 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2052 if(on)
2053 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2054 else
2055 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2056 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2057 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2058
2059 return 0;
2060}
2061
2062static int
2063jme_set_tx_csum(struct net_device *netdev, u32 on)
2064{
42b1055e 2065 if(on && netdev->mtu <= 1900)
8c198884
GFT
2066 netdev->features |= NETIF_F_HW_CSUM;
2067 else
2068 netdev->features &= ~NETIF_F_HW_CSUM;
2069
2070 return 0;
2071}
2072
2073static int
2074jme_nway_reset(struct net_device *netdev)
2075{
2076 struct jme_adapter *jme = netdev_priv(netdev);
2077 jme_restart_an(jme);
2078 return 0;
2079}
2080
d7699f87
GFT
2081static const struct ethtool_ops jme_ethtool_ops = {
2082 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2083 .get_regs_len = jme_get_regs_len,
2084 .get_regs = jme_get_regs,
2085 .get_coalesce = jme_get_coalesce,
79ce639c 2086 .set_coalesce = jme_set_coalesce,
8c198884
GFT
2087 .get_pauseparam = jme_get_pauseparam,
2088 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2089 .get_wol = jme_get_wol,
2090 .set_wol = jme_set_wol,
d7699f87
GFT
2091 .get_settings = jme_get_settings,
2092 .set_settings = jme_set_settings,
2093 .get_link = jme_get_link,
8c198884
GFT
2094 .get_rx_csum = jme_get_rx_csum,
2095 .set_rx_csum = jme_set_rx_csum,
2096 .set_tx_csum = jme_set_tx_csum,
2097 .nway_reset = jme_nway_reset,
d7699f87
GFT
2098};
2099
3bf61c55
GFT
2100static int
2101jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2102{
3bf61c55 2103 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
42b1055e
GFT
2104 if(!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
2105 dprintk("jme", "64Bit DMA Selected.\n");
3bf61c55 2106 return 1;
42b1055e 2107 }
3bf61c55 2108
8c198884 2109 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
42b1055e
GFT
2110 if(!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK)) {
2111 dprintk("jme", "40Bit DMA Selected.\n");
8c198884 2112 return 1;
42b1055e 2113 }
8c198884 2114
3bf61c55 2115 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
42b1055e
GFT
2116 if(!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
2117 dprintk("jme", "32Bit DMA Selected.\n");
3bf61c55 2118 return 0;
42b1055e 2119 }
3bf61c55
GFT
2120
2121 return -1;
2122}
2123
42b1055e
GFT
2124__always_inline static void
2125jme_set_phy_ps(struct jme_adapter *jme)
2126{
2127 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, 0x00001000);
2128}
2129
3bf61c55
GFT
2130static int __devinit
2131jme_init_one(struct pci_dev *pdev,
2132 const struct pci_device_id *ent)
2133{
2134 int rc = 0, using_dac;
d7699f87
GFT
2135 struct net_device *netdev;
2136 struct jme_adapter *jme;
d7699f87
GFT
2137
2138 /*
2139 * set up PCI device basics
2140 */
4330c2f2
GFT
2141 rc = pci_enable_device(pdev);
2142 if(rc) {
2143 printk(KERN_ERR PFX "Cannot enable PCI device.\n");
2144 goto err_out;
2145 }
d7699f87 2146
3bf61c55
GFT
2147 using_dac = jme_pci_dma64(pdev);
2148 if(using_dac < 0) {
2149 printk(KERN_ERR PFX "Cannot set PCI DMA Mask.\n");
2150 rc = -EIO;
2151 goto err_out_disable_pdev;
2152 }
2153
4330c2f2
GFT
2154 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2155 printk(KERN_ERR PFX "No PCI resource region found.\n");
2156 rc = -ENOMEM;
2157 goto err_out_disable_pdev;
2158 }
d7699f87 2159
4330c2f2
GFT
2160 rc = pci_request_regions(pdev, DRV_NAME);
2161 if(rc) {
2162 printk(KERN_ERR PFX "Cannot obtain PCI resource region.\n");
2163 goto err_out_disable_pdev;
2164 }
d7699f87
GFT
2165
2166 pci_set_master(pdev);
2167
2168 /*
2169 * alloc and init net device
2170 */
3bf61c55 2171 netdev = alloc_etherdev(sizeof(*jme));
d7699f87 2172 if(!netdev) {
42b1055e 2173 printk(KERN_ERR PFX "Cannot allocate netdev structure.\n");
4330c2f2
GFT
2174 rc = -ENOMEM;
2175 goto err_out_release_regions;
d7699f87
GFT
2176 }
2177 netdev->open = jme_open;
2178 netdev->stop = jme_close;
2179 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT
2180 netdev->set_mac_address = jme_set_macaddr;
2181 netdev->set_multicast_list = jme_set_multi;
2182 netdev->change_mtu = jme_change_mtu;
2183 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884
GFT
2184 netdev->tx_timeout = jme_tx_timeout;
2185 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2186 netdev->vlan_rx_register = jme_vlan_rx_register;
3bf61c55 2187 NETDEV_GET_STATS(netdev, &jme_get_stats);
42b1055e
GFT
2188 netdev->features = NETIF_F_HW_CSUM |
2189 NETIF_F_HW_VLAN_TX |
2190 NETIF_F_HW_VLAN_RX;
3bf61c55 2191 if(using_dac)
8c198884 2192 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
2193
2194 SET_NETDEV_DEV(netdev, &pdev->dev);
2195 pci_set_drvdata(pdev, netdev);
2196
2197 /*
2198 * init adapter info
2199 */
2200 jme = netdev_priv(netdev);
2201 jme->pdev = pdev;
2202 jme->dev = netdev;
29bdd921 2203 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2204 jme->phylink = 0;
d7699f87
GFT
2205 jme->regs = ioremap(pci_resource_start(pdev, 0),
2206 pci_resource_len(pdev, 0));
4330c2f2 2207 if (!(jme->regs)) {
42b1055e 2208 printk(KERN_ERR PFX "Mapping PCI resource region error.\n");
d7699f87
GFT
2209 rc = -ENOMEM;
2210 goto err_out_free_netdev;
2211 }
4330c2f2
GFT
2212 jme->shadow_regs = pci_alloc_consistent(pdev,
2213 sizeof(__u32) * SHADOW_REG_NR,
2214 &(jme->shadow_dma));
2215 if (!(jme->shadow_regs)) {
42b1055e 2216 printk(KERN_ERR PFX "Allocating shadow register mapping error.\n");
4330c2f2
GFT
2217 rc = -ENOMEM;
2218 goto err_out_unmap;
2219 }
2220
d7699f87 2221 spin_lock_init(&jme->phy_lock);
fcf45b4c 2222 spin_lock_init(&jme->macaddr_lock);
8c198884 2223 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2224
fcf45b4c
GFT
2225 atomic_set(&jme->link_changing, 1);
2226 atomic_set(&jme->rx_cleaning, 1);
2227 atomic_set(&jme->tx_cleaning, 1);
2228
79ce639c
GFT
2229 tasklet_init(&jme->pcc_task,
2230 &jme_pcc_tasklet,
2231 (unsigned long) jme);
4330c2f2
GFT
2232 tasklet_init(&jme->linkch_task,
2233 &jme_link_change_tasklet,
2234 (unsigned long) jme);
2235 tasklet_init(&jme->txclean_task,
2236 &jme_tx_clean_tasklet,
2237 (unsigned long) jme);
2238 tasklet_init(&jme->rxclean_task,
2239 &jme_rx_clean_tasklet,
2240 (unsigned long) jme);
fcf45b4c
GFT
2241 tasklet_init(&jme->rxempty_task,
2242 &jme_rx_empty_tasklet,
2243 (unsigned long) jme);
d7699f87
GFT
2244 jme->mii_if.dev = netdev;
2245 jme->mii_if.phy_id = 1;
2246 jme->mii_if.supports_gmii = 1;
2247 jme->mii_if.mdio_read = jme_mdio_read;
2248 jme->mii_if.mdio_write = jme_mdio_write;
2249
8c198884
GFT
2250 jme->dpi.cur = PCC_P1;
2251
2252 jme->reg_ghc = GHC_DPX | GHC_SPEED_1000M;
79ce639c 2253 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
2254 jme->reg_rxmcs = RXMCS_DEFAULT;
2255 jme->reg_txpfc = 0;
29bdd921 2256 jme->reg_pmcs = 0;
d7699f87 2257 /*
fcf45b4c
GFT
2258 * Get Max Read Req Size from PCI Config Space
2259 */
2260 pci_read_config_byte(pdev, PCI_CONF_DCSR_MRRS, &jme->mrrs);
2261 switch(jme->mrrs) {
2262 case MRRS_128B:
2263 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2264 break;
2265 case MRRS_256B:
2266 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2267 break;
2268 default:
2269 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2270 break;
2271 };
2272
2273
2274 /*
d7699f87
GFT
2275 * Reset MAC processor and reload EEPROM for MAC Address
2276 */
2277 jme_clear_pm(jme);
42b1055e
GFT
2278 jme_set_phy_ps(jme);
2279 jme_phy_off(jme);
d7699f87 2280 jme_reset_mac_processor(jme);
4330c2f2
GFT
2281 rc = jme_reload_eeprom(jme);
2282 if(rc) {
3bf61c55
GFT
2283 printk(KERN_ERR PFX
2284 "Rload eeprom for reading MAC Address error.\n");
4330c2f2
GFT
2285 goto err_out_free_shadow;
2286 }
d7699f87
GFT
2287 jme_load_macaddr(netdev);
2288
2289
2290 /*
2291 * Tell stack that we are not ready to work until open()
2292 */
2293 netif_carrier_off(netdev);
2294 netif_stop_queue(netdev);
2295
2296 /*
2297 * Register netdev
2298 */
4330c2f2
GFT
2299 rc = register_netdev(netdev);
2300 if(rc) {
2301 printk(KERN_ERR PFX "Cannot register net device.\n");
2302 goto err_out_free_shadow;
2303 }
d7699f87 2304
4330c2f2 2305 jprintk(netdev->name,
8c198884 2306 "JMC250 gigabit eth %02x:%02x:%02x:%02x:%02x:%02x\n",
4330c2f2
GFT
2307 netdev->dev_addr[0],
2308 netdev->dev_addr[1],
2309 netdev->dev_addr[2],
2310 netdev->dev_addr[3],
2311 netdev->dev_addr[4],
8c198884 2312 netdev->dev_addr[5]);
d7699f87
GFT
2313
2314 return 0;
2315
4330c2f2
GFT
2316err_out_free_shadow:
2317 pci_free_consistent(pdev,
2318 sizeof(__u32) * SHADOW_REG_NR,
2319 jme->shadow_regs,
2320 jme->shadow_dma);
d7699f87
GFT
2321err_out_unmap:
2322 iounmap(jme->regs);
2323err_out_free_netdev:
2324 pci_set_drvdata(pdev, NULL);
2325 free_netdev(netdev);
4330c2f2
GFT
2326err_out_release_regions:
2327 pci_release_regions(pdev);
d7699f87
GFT
2328err_out_disable_pdev:
2329 pci_disable_device(pdev);
d7699f87 2330err_out:
4330c2f2 2331 return rc;
d7699f87
GFT
2332}
2333
3bf61c55
GFT
2334static void __devexit
2335jme_remove_one(struct pci_dev *pdev)
2336{
d7699f87
GFT
2337 struct net_device *netdev = pci_get_drvdata(pdev);
2338 struct jme_adapter *jme = netdev_priv(netdev);
2339
2340 unregister_netdev(netdev);
4330c2f2
GFT
2341 pci_free_consistent(pdev,
2342 sizeof(__u32) * SHADOW_REG_NR,
2343 jme->shadow_regs,
2344 jme->shadow_dma);
d7699f87
GFT
2345 iounmap(jme->regs);
2346 pci_set_drvdata(pdev, NULL);
2347 free_netdev(netdev);
2348 pci_release_regions(pdev);
2349 pci_disable_device(pdev);
2350
2351}
2352
29bdd921
GFT
2353static int
2354jme_suspend(struct pci_dev *pdev, pm_message_t state)
2355{
2356 struct net_device *netdev = pci_get_drvdata(pdev);
2357 struct jme_adapter *jme = netdev_priv(netdev);
2358 int timeout = 100;
2359
2360 atomic_dec(&jme->link_changing);
2361
2362 netif_device_detach(netdev);
2363 netif_stop_queue(netdev);
2364 jme_stop_irq(jme);
2365 jme_free_irq(jme);
2366
2367 while(--timeout > 0 &&
2368 (
2369 atomic_read(&jme->rx_cleaning) != 1 ||
2370 atomic_read(&jme->tx_cleaning) != 1
2371 )) {
2372 mdelay(1);
2373 }
2374 if(!timeout) {
2375 jeprintk(netdev->name, "Waiting tasklets timeout.\n");
2376 return -EBUSY;
2377 }
2378 jme_disable_shadow(jme);
2379
2380 if(netif_carrier_ok(netdev)) {
2381 jme_stop_pcc_timer(jme);
2382 jme_reset_mac_processor(jme);
2383 jme_free_rx_resources(jme);
2384 jme_free_tx_resources(jme);
2385 netif_carrier_off(netdev);
2386 jme->phylink = 0;
2387 }
2388
29bdd921
GFT
2389
2390 pci_save_state(pdev);
2391 if(jme->reg_pmcs) {
42b1055e 2392 jme_set_100m_half(jme);
29bdd921 2393 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e
GFT
2394 pci_enable_wake(pdev, PCI_D3hot, true);
2395 pci_enable_wake(pdev, PCI_D3cold, true);
29bdd921
GFT
2396 }
2397 else {
42b1055e
GFT
2398 jme_phy_off(jme);
2399 pci_enable_wake(pdev, PCI_D3hot, false);
2400 pci_enable_wake(pdev, PCI_D3cold, false);
29bdd921
GFT
2401 }
2402 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2403
2404 return 0;
2405}
2406
2407static int
2408jme_resume(struct pci_dev *pdev)
2409{
2410 struct net_device *netdev = pci_get_drvdata(pdev);
2411 struct jme_adapter *jme = netdev_priv(netdev);
2412
2413 jme_clear_pm(jme);
2414 pci_restore_state(pdev);
2415
2416 if(jme->flags & JME_FLAG_SSET)
2417 jme_set_settings(netdev, &jme->old_ecmd);
2418 else
2419 jme_reset_phy_processor(jme);
2420
2421 jme_reset_mac_processor(jme);
2422 jme_enable_shadow(jme);
2423 jme_request_irq(jme);
2424 jme_start_irq(jme);
2425 netif_device_attach(netdev);
2426
2427 atomic_inc(&jme->link_changing);
2428
2429 jme_reset_link(jme);
2430
2431 return 0;
2432}
2433
d7699f87
GFT
2434static struct pci_device_id jme_pci_tbl[] = {
2435 { PCI_VDEVICE(JMICRON, 0x250) },
2436 { }
2437};
2438
2439static struct pci_driver jme_driver = {
2440 .name = DRV_NAME,
2441 .id_table = jme_pci_tbl,
2442 .probe = jme_init_one,
2443 .remove = __devexit_p(jme_remove_one),
d7699f87
GFT
2444#ifdef CONFIG_PM
2445 .suspend = jme_suspend,
2446 .resume = jme_resume,
2447#endif /* CONFIG_PM */
d7699f87
GFT
2448};
2449
3bf61c55
GFT
2450static int __init
2451jme_init_module(void)
d7699f87 2452{
4330c2f2
GFT
2453 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
2454 "driver version %s\n", DRV_VERSION);
d7699f87
GFT
2455 return pci_register_driver(&jme_driver);
2456}
2457
3bf61c55
GFT
2458static void __exit
2459jme_cleanup_module(void)
d7699f87
GFT
2460{
2461 pci_unregister_driver(&jme_driver);
2462}
2463
2464module_init(jme_init_module);
2465module_exit(jme_cleanup_module);
2466
3bf61c55 2467MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
2468MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
2469MODULE_LICENSE("GPL");
2470MODULE_VERSION(DRV_VERSION);
2471MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
2472