Import jme 0.8 source
[jme.git] / jme.c
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 /*
25  * Note:
26  *      Backdoor for changing "FIFO Threshold for processing next packet"
27  *         Using:
28  *              ethtool -C eth1 adaptive-rx on adaptive-tx on \
29  *              rx-usecs 250 rx-frames-low N
30  *         N := 16 | 32 | 64 | 128
31  */
32
33 /*
34  * Timeline before release:
35  *      Stage 5: Advanced offloading support.
36  *      0.9:
37  *      -  Implement scatter-gather offloading.
38  *         Use pci_map_page on scattered sk_buff for HIGHMEM support
39  *      -  Implement TCP Segement offloading.
40  *              Due to TX FIFO size, we should turn off tso when mtu > 1500.
41  *
42  *      Stage 6: CPU Load balancing.
43  *      1.0:
44  *      -  Implement MSI-X.
45  *         Along with multiple RX queue, for CPU load balancing.
46  *
47  *      Stage 7:
48  *      -  Cleanup/re-orginize code, performence tuneing(alignment etc...).
49  *      -  Test and Release 1.0
50  *
51  *      Non-Critical:
52  *      -  Use NAPI instead of rx_tasklet?
53  *              PCC Support Both Packet Counter and Timeout Interrupt for
54  *              receive and transmit complete, does NAPI really needed?
55  *      -  Decode register dump for ethtool.
56  */
57
58 #include <linux/version.h>
59 #include <linux/module.h>
60 #include <linux/kernel.h>
61 #include <linux/pci.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/ethtool.h>
65 #include <linux/mii.h>
66 #include <linux/crc32.h>
67 #include <linux/delay.h>
68 #include <linux/spinlock.h>
69 #include <linux/in.h>
70 #include <linux/ip.h>
71 #include <linux/ipv6.h>
72 #include <linux/tcp.h>
73 #include <linux/udp.h>
74 #include <linux/if_vlan.h>
75 #include "jme.h"
76
77 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
78 static struct net_device_stats *
79 jme_get_stats(struct net_device *netdev)
80 {
81         struct jme_adapter *jme = netdev_priv(netdev);
82         return &jme->stats;
83 }
84 #endif
85
86 static int
87 jme_mdio_read(struct net_device *netdev, int phy, int reg)
88 {
89         struct jme_adapter *jme = netdev_priv(netdev);
90         int i, val;
91
92         jwrite32(jme, JME_SMI, SMI_OP_REQ |
93                                 smi_phy_addr(phy) |
94                                 smi_reg_addr(reg));
95
96         wmb();
97         for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
98                 udelay(1);
99                 if (((val = jread32(jme, JME_SMI)) & SMI_OP_REQ) == 0)
100                         break;
101         }
102
103         if (i == 0) {
104                 jeprintk(netdev->name, "phy read timeout : %d\n", reg);
105                 return 0;
106         }
107
108         return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
109 }
110
111 static void
112 jme_mdio_write(struct net_device *netdev,
113                                 int phy, int reg, int val)
114 {
115         struct jme_adapter *jme = netdev_priv(netdev);
116         int i;
117
118         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
119                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
120                 smi_phy_addr(phy) | smi_reg_addr(reg));
121
122         wmb();
123         for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
124                 udelay(1);
125                 if (((val = jread32(jme, JME_SMI)) & SMI_OP_REQ) == 0)
126                         break;
127         }
128
129         if (i == 0)
130                 jeprintk(netdev->name, "phy write timeout : %d\n", reg);
131
132         return;
133 }
134
135 __always_inline static void
136 jme_reset_phy_processor(struct jme_adapter *jme)
137 {
138         __u32 val;
139
140         jme_mdio_write(jme->dev,
141                         jme->mii_if.phy_id,
142                         MII_ADVERTISE, ADVERTISE_ALL |
143                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
144
145         jme_mdio_write(jme->dev,
146                         jme->mii_if.phy_id,
147                         MII_CTRL1000,
148                         ADVERTISE_1000FULL | ADVERTISE_1000HALF);
149
150         val = jme_mdio_read(jme->dev,
151                                 jme->mii_if.phy_id,
152                                 MII_BMCR);
153
154         jme_mdio_write(jme->dev,
155                         jme->mii_if.phy_id,
156                         MII_BMCR, val | BMCR_RESET);
157
158         return;
159 }
160
161
162 __always_inline static void
163 jme_reset_mac_processor(struct jme_adapter *jme)
164 {
165         jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
166         udelay(2);
167         jwrite32(jme, JME_GHC, jme->reg_ghc);
168         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
169         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
170         jwrite32(jme, JME_WFODP, 0);
171         jwrite32(jme, JME_WFOI, 0);
172         jwrite32(jme, JME_GPREG0, GPREG0_DEFAULT);
173         jwrite32(jme, JME_GPREG1, 0);
174 }
175
176 __always_inline static void
177 jme_clear_pm(struct jme_adapter *jme)
178 {
179         jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
180         pci_set_power_state(jme->pdev, PCI_D0);
181         pci_enable_wake(jme->pdev, PCI_D0, false);
182 }
183
184 static int
185 jme_reload_eeprom(struct jme_adapter *jme)
186 {
187         __u32 val;
188         int i;
189
190         val = jread32(jme, JME_SMBCSR);
191
192         if(val & SMBCSR_EEPROMD)
193         {
194                 val |= SMBCSR_CNACK;
195                 jwrite32(jme, JME_SMBCSR, val);
196                 val |= SMBCSR_RELOAD;
197                 jwrite32(jme, JME_SMBCSR, val);
198                 mdelay(12);
199
200                 for (i = JME_SMB_TIMEOUT; i > 0; --i)
201                 {
202                         mdelay(1);
203                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
204                                 break;
205                 }
206
207                 if(i == 0) {
208                         jeprintk(jme->dev->name, "eeprom reload timeout\n");
209                         return -EIO;
210                 }
211         }
212         else
213                 return -EIO;
214
215         return 0;
216 }
217
218 static void
219 jme_load_macaddr(struct net_device *netdev)
220 {
221         struct jme_adapter *jme = netdev_priv(netdev);
222         unsigned char macaddr[6];
223         __u32 val;
224
225         spin_lock(&jme->macaddr_lock);
226         val = jread32(jme, JME_RXUMA_LO);
227         macaddr[0] = (val >>  0) & 0xFF;
228         macaddr[1] = (val >>  8) & 0xFF;
229         macaddr[2] = (val >> 16) & 0xFF;
230         macaddr[3] = (val >> 24) & 0xFF;
231         val = jread32(jme, JME_RXUMA_HI);
232         macaddr[4] = (val >>  0) & 0xFF;
233         macaddr[5] = (val >>  8) & 0xFF;
234         memcpy(netdev->dev_addr, macaddr, 6);
235         spin_unlock(&jme->macaddr_lock);
236 }
237
238 __always_inline static void
239 jme_set_rx_pcc(struct jme_adapter *jme, int p)
240 {
241         switch(p) {
242         case PCC_P1:
243                 jwrite32(jme, JME_PCCRX0,
244                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
245                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
246                 break;
247         case PCC_P2:
248                 jwrite32(jme, JME_PCCRX0,
249                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
250                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
251                 break;
252         case PCC_P3:
253                 jwrite32(jme, JME_PCCRX0,
254                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
255                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
256                 break;
257         default:
258                 break;
259         }
260
261         dprintk(jme->dev->name, "Switched to PCC_P%d\n", p);
262 }
263
264 static void
265 jme_start_irq(struct jme_adapter *jme)
266 {
267         register struct dynpcc_info *dpi = &(jme->dpi);
268
269         jme_set_rx_pcc(jme, PCC_P1);
270         dpi->cur                = PCC_P1;
271         dpi->attempt            = PCC_P1;
272         dpi->cnt                = 0;
273
274         jwrite32(jme, JME_PCCTX,
275                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
276                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
277                         PCCTXQ0_EN
278                 );
279
280         /*
281          * Enable Interrupts
282          */
283         jwrite32(jme, JME_IENS, INTR_ENABLE);
284 }
285
286 __always_inline static void
287 jme_stop_irq(struct jme_adapter *jme)
288 {
289         /*
290          * Disable Interrupts
291          */
292         jwrite32(jme, JME_IENC, INTR_ENABLE);
293 }
294
295
296 __always_inline static void
297 jme_enable_shadow(struct jme_adapter *jme)
298 {
299         jwrite32(jme,
300                  JME_SHBA_LO,
301                  ((__u32)jme->shadow_dma & ~((__u32)0x1F)) | SHBA_POSTEN);
302 }
303
304 __always_inline static void
305 jme_disable_shadow(struct jme_adapter *jme)
306 {
307         jwrite32(jme, JME_SHBA_LO, 0x0);
308 }
309
310 static int
311 jme_check_link(struct net_device *netdev, int testonly)
312 {
313         struct jme_adapter *jme = netdev_priv(netdev);
314         __u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
315         char linkmsg[64];
316         int rc = 0;
317
318         phylink = jread32(jme, JME_PHY_LINK);
319
320         if (phylink & PHY_LINK_UP) {
321                 if(!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
322                         /*
323                          * If we did not enable AN
324                          * Speed/Duplex Info should be obtained from SMI
325                          */
326                         phylink = PHY_LINK_UP;
327
328                         bmcr = jme_mdio_read(jme->dev,
329                                                 jme->mii_if.phy_id,
330                                                 MII_BMCR);
331
332
333                         phylink |= ((bmcr & BMCR_SPEED1000) &&
334                                         (bmcr & BMCR_SPEED100) == 0) ?
335                                         PHY_LINK_SPEED_1000M :
336                                         (bmcr & BMCR_SPEED100) ?
337                                         PHY_LINK_SPEED_100M :
338                                         PHY_LINK_SPEED_10M;
339
340                         phylink |= (bmcr & BMCR_FULLDPLX) ?
341                                          PHY_LINK_DUPLEX : 0;
342
343                         strcpy(linkmsg, "Forced: ");
344                 }
345                 else {
346                         /*
347                          * Keep polling for speed/duplex resolve complete
348                          */
349                         while(!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
350                                 --cnt) {
351
352                                 udelay(1);
353                                 phylink = jread32(jme, JME_PHY_LINK);
354
355                         }
356
357                         if(!cnt)
358                                 jeprintk(netdev->name,
359                                         "Waiting speed resolve timeout.\n");
360
361                         strcpy(linkmsg, "ANed: ");
362                 }
363
364                 if(jme->phylink == phylink) {
365                         rc = 1;
366                         goto out;
367                 }
368                 if(testonly)
369                         goto out;
370
371                 jme->phylink = phylink;
372
373                 switch(phylink & PHY_LINK_SPEED_MASK) {
374                         case PHY_LINK_SPEED_10M:
375                                 ghc = GHC_SPEED_10M;
376                                 strcpy(linkmsg, "10 Mbps, ");
377                                 break;
378                         case PHY_LINK_SPEED_100M:
379                                 ghc = GHC_SPEED_100M;
380                                 strcpy(linkmsg, "100 Mbps, ");
381                                 break;
382                         case PHY_LINK_SPEED_1000M:
383                                 ghc = GHC_SPEED_1000M;
384                                 strcpy(linkmsg, "1000 Mbps, ");
385                                 break;
386                         default:
387                                 ghc = 0;
388                                 break;
389                 }
390                 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
391
392                 strcat(linkmsg, (phylink &PHY_LINK_DUPLEX) ?
393                                         "Full-Duplex, " :
394                                         "Half-Duplex, ");
395
396                 if(phylink & PHY_LINK_MDI_STAT)
397                         strcat(linkmsg, "MDI-X");
398                 else
399                         strcat(linkmsg, "MDI");
400
401                 if(phylink & PHY_LINK_DUPLEX)
402                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
403                 else {
404                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
405                                                 TXMCS_BACKOFF |
406                                                 TXMCS_CARRIERSENSE |
407                                                 TXMCS_COLLISION);
408                         jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
409                                 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
410                                 TXTRHD_TXREN |
411                                 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
412                 }
413
414                 jme->reg_ghc = ghc;
415                 jwrite32(jme, JME_GHC, ghc);
416
417                 jprintk(netdev->name, "Link is up at %s.\n", linkmsg);
418                 netif_carrier_on(netdev);
419         }
420         else {
421                 if(testonly)
422                         goto out;
423
424                 jprintk(netdev->name, "Link is down.\n");
425                 jme->phylink = 0;
426                 netif_carrier_off(netdev);
427         }
428
429 out:
430         return rc;
431 }
432
433
434 static int
435 jme_alloc_txdesc(struct jme_adapter *jme,
436                         int nr_alloc)
437 {
438         struct jme_ring *txring = jme->txring;
439         int idx;
440
441         idx = txring->next_to_use;
442
443         if(unlikely(atomic_read(&txring->nr_free) < nr_alloc))
444                 return -1;
445
446         atomic_sub(nr_alloc, &txring->nr_free);
447
448         if((txring->next_to_use += nr_alloc) >= RING_DESC_NR)
449                 txring->next_to_use -= RING_DESC_NR;
450
451         return idx;
452 }
453
454 static void
455 jme_tx_csum(struct sk_buff *skb, unsigned mtu, __u8 *flags)
456 {
457         if(skb->ip_summed == CHECKSUM_PARTIAL) {
458                 __u8 ip_proto;
459
460                 switch (skb->protocol) {
461                 case __constant_htons(ETH_P_IP):
462                         ip_proto = ip_hdr(skb)->protocol;
463                         break;
464                 case __constant_htons(ETH_P_IPV6):
465                         ip_proto = ipv6_hdr(skb)->nexthdr;
466                         break;
467                 default:
468                         ip_proto = 0;
469                         break;
470                 }
471
472
473                 switch(ip_proto) {
474                 case IPPROTO_TCP:
475                         *flags |= TXFLAG_TCPCS;
476                         break;
477                 case IPPROTO_UDP:
478                         *flags |= TXFLAG_UDPCS;
479                         break;
480                 default:
481                         jeprintk("jme", "Error upper layer protocol.\n");
482                         break;
483                 }
484         }
485 }
486
487 __always_inline static void
488 jme_tx_vlan(struct sk_buff *skb, volatile __u16 *vlan, __u8 *flags)
489 {
490         if(vlan_tx_tag_present(skb)) {
491                 *flags |= TXFLAG_TAGON;
492                 *vlan = vlan_tx_tag_get(skb);
493         }
494 }
495
496 static int
497 jme_set_new_txdesc(struct jme_adapter *jme,
498                         struct sk_buff *skb)
499 {
500         struct jme_ring *txring = jme->txring;
501         volatile struct txdesc *txdesc = txring->desc, *ctxdesc;
502         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
503         dma_addr_t dmaaddr;
504         int i, idx, nr_desc;
505         __u8 flags;
506
507         nr_desc = 2;
508         idx = jme_alloc_txdesc(jme, nr_desc);
509
510         if(unlikely(idx<0))
511                 return NETDEV_TX_BUSY;
512
513         for(i = 1 ; i < nr_desc  ; ++i) {
514                 ctxdesc = txdesc + ((idx + i) & (RING_DESC_NR-1));
515                 ctxbi = txbi + ((idx + i) & (RING_DESC_NR-1));
516
517                 dmaaddr = pci_map_single(jme->pdev,
518                                          skb->data,
519                                          skb->len,
520                                          PCI_DMA_TODEVICE);
521
522                 pci_dma_sync_single_for_device(jme->pdev,
523                                                dmaaddr,
524                                                skb->len,
525                                                PCI_DMA_TODEVICE);
526
527                 ctxdesc->dw[0] = 0;
528                 ctxdesc->dw[1] = 0;
529                 ctxdesc->desc2.flags    = TXFLAG_OWN;
530                 if(jme->dev->features & NETIF_F_HIGHDMA)
531                         ctxdesc->desc2.flags |= TXFLAG_64BIT;
532                 ctxdesc->desc2.datalen  = cpu_to_le16(skb->len);
533                 ctxdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
534                 ctxdesc->desc2.bufaddrl = cpu_to_le32(
535                                                 (__u64)dmaaddr & 0xFFFFFFFFUL);
536
537                 ctxbi->mapping = dmaaddr;
538                 ctxbi->len = skb->len;
539         }
540
541         ctxdesc = txdesc + idx;
542         ctxbi = txbi + idx;
543
544         ctxdesc->dw[0] = 0;
545         ctxdesc->dw[1] = 0;
546         ctxdesc->dw[2] = 0;
547         ctxdesc->dw[3] = 0;
548         ctxdesc->desc1.pktsize = cpu_to_le16(skb->len);
549         /*
550          * Set OWN bit at final.
551          * When kernel transmit faster than NIC.
552          * And NIC trying to send this descriptor before we tell
553          * it to start sending this TX queue.
554          * Other fields are already filled correctly.
555          */
556         wmb();
557         flags = TXFLAG_OWN | TXFLAG_INT; 
558         jme_tx_csum(skb, jme->dev->mtu, &flags);
559         jme_tx_vlan(skb, &(ctxdesc->desc1.vlan), &flags);
560         ctxdesc->desc1.flags = flags;
561         /*
562          * Set tx buffer info after telling NIC to send
563          * For better tx_clean timing
564          */
565         wmb();
566         ctxbi->nr_desc = nr_desc;
567         ctxbi->skb = skb;
568
569         tx_dbg(jme->dev->name, "Xmit: %d+%d\n", idx, nr_desc);
570
571         return 0;
572 }
573
574
575 static int
576 jme_setup_tx_resources(struct jme_adapter *jme)
577 {
578         struct jme_ring *txring = &(jme->txring[0]);
579
580         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
581                                            TX_RING_ALLOC_SIZE,
582                                            &(txring->dmaalloc),
583                                            GFP_ATOMIC);
584
585         if(!txring->alloc) {
586                 txring->desc = NULL;
587                 txring->dmaalloc = 0;
588                 txring->dma = 0;
589                 return -ENOMEM;
590         }
591
592         /*
593          * 16 Bytes align
594          */
595         txring->desc            = (void*)ALIGN((unsigned long)(txring->alloc),
596                                                 RING_DESC_ALIGN);
597         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
598         txring->next_to_use     = 0;
599         txring->next_to_clean   = 0;
600         atomic_set(&txring->nr_free, RING_DESC_NR);
601
602         /*
603          * Initiallize Transmit Descriptors
604          */
605         memset(txring->alloc, 0, TX_RING_ALLOC_SIZE);
606         memset(txring->bufinf, 0,
607                 sizeof(struct jme_buffer_info) * RING_DESC_NR);
608
609         return 0;
610 }
611
612 static void
613 jme_free_tx_resources(struct jme_adapter *jme)
614 {
615         int i;
616         struct jme_ring *txring = &(jme->txring[0]);
617         struct jme_buffer_info *txbi = txring->bufinf;
618
619         if(txring->alloc) {
620                 for(i = 0 ; i < RING_DESC_NR ; ++i) {
621                         txbi = txring->bufinf + i;
622                         if(txbi->skb) {
623                                 dev_kfree_skb(txbi->skb);
624                                 txbi->skb = NULL;
625                         }
626                         txbi->mapping   = 0;
627                         txbi->len       = 0;
628                         txbi->nr_desc   = 0;
629                 }
630
631                 dma_free_coherent(&(jme->pdev->dev),
632                                   TX_RING_ALLOC_SIZE,
633                                   txring->alloc,
634                                   txring->dmaalloc);
635
636                 txring->alloc           = NULL;
637                 txring->desc            = NULL;
638                 txring->dmaalloc        = 0;
639                 txring->dma             = 0;
640         }
641         txring->next_to_use     = 0;
642         txring->next_to_clean   = 0;
643         atomic_set(&txring->nr_free, 0);
644
645 }
646
647 __always_inline static void
648 jme_enable_tx_engine(struct jme_adapter *jme)
649 {
650         /*
651          * Select Queue 0
652          */
653         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
654
655         /*
656          * Setup TX Queue 0 DMA Bass Address
657          */
658         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
659         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
660         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
661
662         /*
663          * Setup TX Descptor Count
664          */
665         jwrite32(jme, JME_TXQDC, RING_DESC_NR);
666
667         /*
668          * Enable TX Engine
669          */
670         wmb();
671         jwrite32(jme, JME_TXCS, jme->reg_txcs |
672                                 TXCS_SELECT_QUEUE0 |
673                                 TXCS_ENABLE);
674
675 }
676
677 __always_inline static void
678 jme_restart_tx_engine(struct jme_adapter *jme)
679 {
680         /*
681          * Restart TX Engine
682          */
683         jwrite32(jme, JME_TXCS, jme->reg_txcs |
684                                 TXCS_SELECT_QUEUE0 |
685                                 TXCS_ENABLE);
686 }
687
688 __always_inline static void
689 jme_disable_tx_engine(struct jme_adapter *jme)
690 {
691         int i;
692         __u32 val;
693
694         /*
695          * Disable TX Engine
696          */
697         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
698
699         val = jread32(jme, JME_TXCS);
700         for(i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i)
701         {
702                 mdelay(1);
703                 val = jread32(jme, JME_TXCS);
704         }
705
706         if(!i) {
707                 jeprintk(jme->dev->name, "Disable TX engine timeout.\n");
708                 jme_reset_mac_processor(jme);
709         }
710
711
712 }
713
714 static void
715 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
716 {
717         struct jme_ring *rxring = jme->rxring;
718         register volatile struct rxdesc* rxdesc = rxring->desc;
719         struct jme_buffer_info *rxbi = rxring->bufinf;
720         rxdesc += i;
721         rxbi += i;
722
723         rxdesc->dw[0] = 0;
724         rxdesc->dw[1] = 0;
725         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
726         rxdesc->desc1.bufaddrl  = cpu_to_le32(
727                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
728         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
729         if(jme->dev->features & NETIF_F_HIGHDMA)
730                 rxdesc->desc1.flags = RXFLAG_64BIT;
731         wmb();
732         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
733 }
734
735 static int
736 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
737 {
738         struct jme_ring *rxring = &(jme->rxring[0]);
739         struct jme_buffer_info *rxbi = rxring->bufinf;
740         unsigned long offset;
741         struct sk_buff* skb;
742
743         skb = netdev_alloc_skb(jme->dev,
744                 jme->dev->mtu + RX_EXTRA_LEN);
745         if(unlikely(!skb))
746                 return -ENOMEM;
747
748         if(unlikely(skb_is_nonlinear(skb))) {
749                 dprintk(jme->dev->name,
750                         "Allocated skb fragged(%d).\n",
751                         skb_shinfo(skb)->nr_frags);
752                 dev_kfree_skb(skb);
753                 return -ENOMEM;
754         }
755
756         if(unlikely(offset =
757                         (unsigned long)(skb->data)
758                         & ((unsigned long)RX_BUF_DMA_ALIGN - 1)))
759                 skb_reserve(skb, RX_BUF_DMA_ALIGN - offset);
760
761         rxbi += i;
762         rxbi->skb = skb;
763         rxbi->len = skb_tailroom(skb);
764         rxbi->mapping = pci_map_single(jme->pdev,
765                                        skb->data,
766                                        rxbi->len,
767                                        PCI_DMA_FROMDEVICE);
768
769         return 0;
770 }
771
772 static void
773 jme_free_rx_buf(struct jme_adapter *jme, int i)
774 {
775         struct jme_ring *rxring = &(jme->rxring[0]);
776         struct jme_buffer_info *rxbi = rxring->bufinf;
777         rxbi += i;
778
779         if(rxbi->skb) {
780                 pci_unmap_single(jme->pdev,
781                                  rxbi->mapping,
782                                  rxbi->len,
783                                  PCI_DMA_FROMDEVICE);
784                 dev_kfree_skb(rxbi->skb);
785                 rxbi->skb = NULL;
786                 rxbi->mapping = 0;
787                 rxbi->len = 0;
788         }
789 }
790
791 static void
792 jme_free_rx_resources(struct jme_adapter *jme)
793 {
794         int i;
795         struct jme_ring *rxring = &(jme->rxring[0]);
796
797         if(rxring->alloc) {
798                 for(i = 0 ; i < RING_DESC_NR ; ++i)
799                         jme_free_rx_buf(jme, i);
800
801                 dma_free_coherent(&(jme->pdev->dev),
802                                   RX_RING_ALLOC_SIZE,
803                                   rxring->alloc,
804                                   rxring->dmaalloc);
805                 rxring->alloc    = NULL;
806                 rxring->desc     = NULL;
807                 rxring->dmaalloc = 0;
808                 rxring->dma      = 0;
809         }
810         rxring->next_to_use   = 0;
811         rxring->next_to_clean = 0;
812 }
813
814 static int
815 jme_setup_rx_resources(struct jme_adapter *jme)
816 {
817         int i;
818         struct jme_ring *rxring = &(jme->rxring[0]);
819
820         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
821                                            RX_RING_ALLOC_SIZE,
822                                            &(rxring->dmaalloc),
823                                            GFP_ATOMIC);
824         if(!rxring->alloc) {
825                 rxring->desc = NULL;
826                 rxring->dmaalloc = 0;
827                 rxring->dma = 0;
828                 return -ENOMEM;
829         }
830
831         /*
832          * 16 Bytes align
833          */
834         rxring->desc            = (void*)ALIGN((unsigned long)(rxring->alloc),
835                                                 RING_DESC_ALIGN);
836         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
837         rxring->next_to_use     = 0;
838         rxring->next_to_clean   = 0;
839
840         /*
841          * Initiallize Receive Descriptors
842          */
843         for(i = 0 ; i < RING_DESC_NR ; ++i) {
844                 if(unlikely(jme_make_new_rx_buf(jme, i))) {
845                         jme_free_rx_resources(jme);
846                         return -ENOMEM;
847                 }
848
849                 jme_set_clean_rxdesc(jme, i);
850         }
851
852         return 0;
853 }
854
855 __always_inline static void
856 jme_enable_rx_engine(struct jme_adapter *jme)
857 {
858         /*
859          * Setup RX DMA Bass Address
860          */
861         jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
862         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
863         jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
864
865         /*
866          * Setup RX Descptor Count
867          */
868         jwrite32(jme, JME_RXQDC, RING_DESC_NR);
869
870         /*
871          * Setup Unicast Filter
872          */
873         jme_set_multi(jme->dev);
874
875         /*
876          * Enable RX Engine
877          */
878         wmb();
879         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
880                                 RXCS_QUEUESEL_Q0 |
881                                 RXCS_ENABLE |
882                                 RXCS_QST);
883 }
884
885 __always_inline static void
886 jme_restart_rx_engine(struct jme_adapter *jme)
887 {
888         /*
889          * Start RX Engine
890          */
891         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
892                                 RXCS_QUEUESEL_Q0 |
893                                 RXCS_ENABLE |
894                                 RXCS_QST);
895 }
896
897
898 __always_inline static void
899 jme_disable_rx_engine(struct jme_adapter *jme)
900 {
901         int i;
902         __u32 val;
903
904         /*
905          * Disable RX Engine
906          */
907         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
908
909         val = jread32(jme, JME_RXCS);
910         for(i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i)
911         {
912                 mdelay(1);
913                 val = jread32(jme, JME_RXCS);
914         }
915
916         if(!i)
917                 jeprintk(jme->dev->name, "Disable RX engine timeout.\n");
918
919 }
920
921 static void
922 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
923 {
924         struct jme_ring *rxring = &(jme->rxring[0]);
925         volatile struct rxdesc *rxdesc = rxring->desc;
926         struct jme_buffer_info *rxbi = rxring->bufinf;
927         struct sk_buff *skb;
928         int framesize;
929
930         rxdesc += idx;
931         rxbi += idx;
932
933         skb = rxbi->skb;
934         pci_dma_sync_single_for_cpu(jme->pdev,
935                                         rxbi->mapping,
936                                         rxbi->len,
937                                         PCI_DMA_FROMDEVICE);
938
939         if(unlikely(jme_make_new_rx_buf(jme, idx))) {
940                 pci_dma_sync_single_for_device(jme->pdev,
941                                                 rxbi->mapping,
942                                                 rxbi->len,
943                                                 PCI_DMA_FROMDEVICE);
944
945                 ++(NET_STAT(jme).rx_dropped);
946         }
947         else {
948                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
949                                 - RX_PREPAD_SIZE;
950
951                 skb_reserve(skb, RX_PREPAD_SIZE);
952                 skb_put(skb, framesize);
953                 skb->protocol = eth_type_trans(skb, jme->dev);
954
955                 if((rxdesc->descwb.flags &
956                                         (RXWBFLAG_TCPON |
957                                         RXWBFLAG_UDPON |
958                                         RXWBFLAG_IPV4)))
959                         skb->ip_summed = CHECKSUM_UNNECESSARY;
960                 else
961                         skb->ip_summed = CHECKSUM_NONE;
962
963                 if(jme->vlgrp && (rxdesc->descwb.flags & RXWBFLAG_TAGON))
964                         vlan_hwaccel_rx(skb, jme->vlgrp,
965                                         le32_to_cpu(rxdesc->descwb.vlan));
966                 else
967                         netif_rx(skb);
968
969                 if(le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST_MUL)
970                         ++(NET_STAT(jme).multicast);
971
972                 jme->dev->last_rx = jiffies;
973                 NET_STAT(jme).rx_bytes += framesize;
974                 ++(NET_STAT(jme).rx_packets);
975         }
976
977         jme_set_clean_rxdesc(jme, idx);
978
979 }
980
981 static int
982 jme_rxsum_bad(struct jme_adapter *jme, __u16 flags)
983 {
984         if(unlikely((flags & RXWBFLAG_TCPON) &&
985         !(flags & RXWBFLAG_TCPCS))) {
986                 csum_dbg(jme->dev->name, "TCP Checksum error.\n");
987                 return 1;
988         }
989         else if(unlikely((flags & RXWBFLAG_UDPON) &&
990         !(flags & RXWBFLAG_UDPCS))) {
991                 csum_dbg(jme->dev->name, "UDP Checksum error.\n");
992                 return 1;
993         }
994         else if(unlikely((flags & RXWBFLAG_IPV4) &&
995         !(flags & RXWBFLAG_IPCS))) {
996                 csum_dbg(jme->dev->name, "IPV4 Checksum error.\n");
997                 return 1;
998         }
999         else {
1000                 return 0;
1001         }
1002 }
1003
1004 static int
1005 jme_process_receive(struct jme_adapter *jme, int limit)
1006 {
1007         struct jme_ring *rxring = &(jme->rxring[0]);
1008         volatile struct rxdesc *rxdesc = rxring->desc;
1009         int i, j, ccnt, desccnt;
1010
1011         i = rxring->next_to_clean;
1012         while( limit-- > 0 )
1013         {
1014                 rxdesc = rxring->desc;
1015                 rxdesc += i;
1016
1017                 if((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
1018                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1019                         goto out;
1020
1021                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1022
1023                 rx_dbg(jme->dev->name, "RX: Cleaning %d\n", i);
1024
1025                 if(unlikely(desccnt > 1 ||
1026                 rxdesc->descwb.errstat & RXWBERR_ALLERR ||
1027                 jme_rxsum_bad(jme, rxdesc->descwb.flags))) {
1028
1029                         if(rxdesc->descwb.errstat & RXWBERR_CRCERR)
1030                                 ++(NET_STAT(jme).rx_crc_errors);
1031                         else if(rxdesc->descwb.errstat & RXWBERR_OVERUN)
1032                                 ++(NET_STAT(jme).rx_fifo_errors);
1033                         else
1034                                 ++(NET_STAT(jme).rx_errors);
1035
1036                         if(desccnt > 1) {
1037                                 rx_dbg(jme->dev->name,
1038                                         "RX: More than one(%d) descriptor, "
1039                                         "framelen=%d\n",
1040                                         desccnt, le16_to_cpu(rxdesc->descwb.framesize));
1041                                 limit -= desccnt - 1;
1042                         }
1043
1044                         for(j = i, ccnt = desccnt ; ccnt-- ; ) {
1045                                 jme_set_clean_rxdesc(jme, j);
1046
1047                                 if(unlikely(++j == RING_DESC_NR))
1048                                         j = 0;
1049                         }
1050
1051                 }
1052                 else {
1053                         jme_alloc_and_feed_skb(jme, i);
1054                 }
1055
1056                 if((i += desccnt) >= RING_DESC_NR)
1057                         i -= RING_DESC_NR;
1058         }
1059
1060 out:
1061         rx_dbg(jme->dev->name, "RX: Stop at %d\n", i);
1062         rx_dbg(jme->dev->name, "RX: RXNDA offset %d\n",
1063                 (jread32(jme, JME_RXNDA) - jread32(jme, JME_RXDBA_LO))
1064                         >> 4);
1065
1066         rxring->next_to_clean = i;
1067
1068         return limit > 0 ? limit : 0;
1069
1070 }
1071
1072 static void
1073 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1074 {
1075         if(likely(atmp == dpi->cur))
1076                 return;
1077
1078         if(dpi->attempt == atmp) {
1079                 ++(dpi->cnt);
1080         }
1081         else {
1082                 dpi->attempt = atmp;
1083                 dpi->cnt = 0;
1084         }
1085
1086 }
1087
1088 static void
1089 jme_dynamic_pcc(struct jme_adapter *jme)
1090 {
1091         register struct dynpcc_info *dpi = &(jme->dpi);
1092
1093         if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1094                 jme_attempt_pcc(dpi, PCC_P3);
1095         else if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P2_THRESHOLD
1096         || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1097                 jme_attempt_pcc(dpi, PCC_P2);
1098         else
1099                 jme_attempt_pcc(dpi, PCC_P1);
1100
1101         if(unlikely(dpi->attempt != dpi->cur && dpi->cnt > 20)) {
1102                 jme_set_rx_pcc(jme, dpi->attempt);
1103                 dpi->cur = dpi->attempt;
1104                 dpi->cnt = 0;
1105         }
1106 }
1107
1108 static void
1109 jme_start_pcc_timer(struct jme_adapter *jme)
1110 {
1111         struct dynpcc_info *dpi = &(jme->dpi);
1112         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1113         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1114         dpi->intr_cnt           = 0;
1115         jwrite32(jme, JME_TMCSR,
1116                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1117 }
1118
1119 static void
1120 jme_stop_pcc_timer(struct jme_adapter *jme)
1121 {
1122         jwrite32(jme, JME_TMCSR, 0);
1123 }
1124
1125 static void
1126 jme_pcc_tasklet(unsigned long arg)
1127 {
1128         struct jme_adapter *jme = (struct jme_adapter*)arg;
1129         struct net_device *netdev = jme->dev;
1130
1131
1132         if(unlikely(netif_queue_stopped(netdev) ||
1133                 (atomic_read(&jme->link_changing) != 1)
1134         )) {
1135                 jme_stop_pcc_timer(jme);
1136                 return;
1137         }
1138
1139         jme_dynamic_pcc(jme);
1140         jme_start_pcc_timer(jme);
1141 }
1142
1143 static void
1144 jme_link_change_tasklet(unsigned long arg)
1145 {
1146         struct jme_adapter *jme = (struct jme_adapter*)arg;
1147         struct net_device *netdev = jme->dev;
1148         int timeout = WAIT_TASKLET_TIMEOUT;
1149         int rc;
1150
1151         if(!atomic_dec_and_test(&jme->link_changing))
1152                 goto out;
1153
1154         if(jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1155                 goto out;
1156
1157         jme->old_mtu = netdev->mtu;
1158         netif_stop_queue(netdev);
1159
1160         while(--timeout > 0 &&
1161                 (
1162                 atomic_read(&jme->rx_cleaning) != 1 ||
1163                 atomic_read(&jme->tx_cleaning) != 1
1164                 )) {
1165
1166                 mdelay(1);
1167         }
1168
1169         if(netif_carrier_ok(netdev)) {
1170                 jme_stop_pcc_timer(jme);
1171                 jme_reset_mac_processor(jme);
1172                 jme_free_rx_resources(jme);
1173                 jme_free_tx_resources(jme);
1174         }
1175
1176         jme_check_link(netdev, 0);
1177         if(netif_carrier_ok(netdev)) {
1178                 rc = jme_setup_rx_resources(jme);
1179                 if(rc) {
1180                         jeprintk(netdev->name,
1181                                 "Allocating resources for RX error"
1182                                 ", Device STOPPED!\n");
1183                         goto out;
1184                 }
1185
1186
1187                 rc = jme_setup_tx_resources(jme);
1188                 if(rc) {
1189                         jeprintk(netdev->name,
1190                                 "Allocating resources for TX error"
1191                                 ", Device STOPPED!\n");
1192                         goto err_out_free_rx_resources;
1193                 }
1194
1195                 jme_enable_rx_engine(jme);
1196                 jme_enable_tx_engine(jme);
1197
1198                 netif_start_queue(netdev);
1199                 jme_start_pcc_timer(jme);
1200         }
1201
1202         goto out;
1203
1204 err_out_free_rx_resources:
1205         jme_free_rx_resources(jme);
1206 out:
1207         atomic_inc(&jme->link_changing);
1208 }
1209
1210 static void
1211 jme_rx_clean_tasklet(unsigned long arg)
1212 {
1213         struct jme_adapter *jme = (struct jme_adapter*)arg;
1214         struct dynpcc_info *dpi = &(jme->dpi);
1215
1216         if(unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1217                 goto out;
1218
1219         if(unlikely(atomic_read(&jme->link_changing) != 1))
1220                 goto out;
1221
1222         if(unlikely(netif_queue_stopped(jme->dev)))
1223                 goto out;
1224
1225         jme_process_receive(jme, RING_DESC_NR);
1226         ++(dpi->intr_cnt);
1227
1228 out:
1229         atomic_inc(&jme->rx_cleaning);
1230 }
1231
1232 static void
1233 jme_rx_empty_tasklet(unsigned long arg)
1234 {
1235         struct jme_adapter *jme = (struct jme_adapter*)arg;
1236
1237         if(unlikely(atomic_read(&jme->link_changing) != 1))
1238                 return;
1239
1240         if(unlikely(netif_queue_stopped(jme->dev)))
1241                 return;
1242
1243         queue_dbg(jme->dev->name, "RX Queue empty!\n");
1244
1245         jme_rx_clean_tasklet(arg);
1246         jme_restart_rx_engine(jme);
1247 }
1248
1249 static void
1250 jme_tx_clean_tasklet(unsigned long arg)
1251 {
1252         struct jme_adapter *jme = (struct jme_adapter*)arg;
1253         struct jme_ring *txring = &(jme->txring[0]);
1254         volatile struct txdesc *txdesc = txring->desc;
1255         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1256         int i, j, cnt = 0, max, err;
1257
1258         if(unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1259                 goto out;
1260
1261         if(unlikely(atomic_read(&jme->link_changing) != 1))
1262                 goto out;
1263
1264         if(unlikely(netif_queue_stopped(jme->dev)))
1265                 goto out;
1266
1267         max = RING_DESC_NR - atomic_read(&txring->nr_free);
1268
1269         tx_dbg(jme->dev->name, "Tx Tasklet: In\n");
1270
1271         for(i = txring->next_to_clean ; cnt < max ; ) {
1272
1273                 ctxbi = txbi + i;
1274
1275                 if(ctxbi->skb && !(txdesc[i].descwb.flags & TXWBFLAG_OWN)) {
1276
1277                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1278
1279                         tx_dbg(jme->dev->name,
1280                                 "Tx Tasklet: Clean %d+%d\n",
1281                                 i, ctxbi->nr_desc);
1282
1283                         for(j = 1 ; j < ctxbi->nr_desc ; ++j) {
1284                                 ttxbi = txbi + ((i + j) & (RING_DESC_NR - 1));
1285                                 txdesc[(i+j)&(RING_DESC_NR-1)].dw[0] = 0;
1286
1287                                 pci_unmap_single(jme->pdev,
1288                                                  ttxbi->mapping,
1289                                                  ttxbi->len,
1290                                                  PCI_DMA_TODEVICE);
1291
1292                                 if(likely(!err))
1293                                         NET_STAT(jme).tx_bytes += ttxbi->len;
1294
1295                                 ttxbi->mapping = 0;
1296                                 ttxbi->len = 0;
1297                         }
1298
1299                         dev_kfree_skb(ctxbi->skb);
1300                         ctxbi->skb = NULL;
1301
1302                         cnt += ctxbi->nr_desc;
1303
1304                         if(unlikely(err))
1305                                 ++(NET_STAT(jme).tx_carrier_errors);
1306                         else
1307                                 ++(NET_STAT(jme).tx_packets);
1308                 }
1309                 else {
1310                         if(!ctxbi->skb)
1311                                 tx_dbg(jme->dev->name,
1312                                         "Tx Tasklet:"
1313                                         " Stoped due to no skb.\n");
1314                         else
1315                                 tx_dbg(jme->dev->name,
1316                                         "Tx Tasklet:"
1317                                         "Stoped due to not done.\n");
1318                         break;
1319                 }
1320
1321                 if(unlikely((i += ctxbi->nr_desc) >= RING_DESC_NR))
1322                         i -= RING_DESC_NR;
1323
1324                 ctxbi->nr_desc = 0;
1325         }
1326
1327         tx_dbg(jme->dev->name,
1328                 "Tx Tasklet: Stop %d Jiffies %lu\n",
1329                 i, jiffies);
1330         txring->next_to_clean = i;
1331
1332         atomic_add(cnt, &txring->nr_free);
1333
1334 out:
1335         atomic_inc(&jme->tx_cleaning);
1336 }
1337
1338 static void
1339 jme_intr_msi(struct jme_adapter *jme, __u32 intrstat)
1340 {
1341         /*
1342          * Disable interrupt
1343          */
1344         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1345
1346         /*
1347          * Write 1 clear interrupt status
1348          */
1349         jwrite32f(jme, JME_IEVE, intrstat);
1350
1351         if(intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1352                 tasklet_schedule(&jme->linkch_task);
1353                 goto out_reenable;
1354         }
1355
1356         if(intrstat & INTR_TMINTR)
1357                 tasklet_schedule(&jme->pcc_task);
1358
1359         if(intrstat & INTR_RX0EMP)
1360                 tasklet_schedule(&jme->rxempty_task);
1361
1362         if(intrstat & (INTR_PCCRX0TO | INTR_PCCRX0))
1363                 tasklet_schedule(&jme->rxclean_task);
1364
1365         if(intrstat & (INTR_PCCTXTO | INTR_PCCTX))
1366                 tasklet_schedule(&jme->txclean_task);
1367
1368         if((intrstat & ~INTR_ENABLE) != 0) {
1369                 /*
1370                  * Some interrupt not handled
1371                  * but not enabled also (for debug)
1372                  */
1373         }
1374
1375 out_reenable:
1376         /*
1377          * Re-enable interrupt
1378          */
1379         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1380
1381
1382 }
1383
1384 static irqreturn_t
1385 jme_intr(int irq, void *dev_id)
1386 {
1387         struct net_device *netdev = dev_id;
1388         struct jme_adapter *jme = netdev_priv(netdev);
1389         __u32 intrstat;
1390
1391         intrstat = jread32(jme, JME_IEVE);
1392
1393         /*
1394          * Check if it's really an interrupt for us
1395          */
1396         if(unlikely(intrstat == 0))
1397                 return IRQ_NONE;
1398
1399         /*
1400          * Check if the device still exist
1401          */
1402         if(unlikely(intrstat == ~((typeof(intrstat))0)))
1403                 return IRQ_NONE;
1404
1405         jme_intr_msi(jme, intrstat);
1406
1407         return IRQ_HANDLED;
1408 }
1409
1410 static irqreturn_t
1411 jme_msi(int irq, void *dev_id)
1412 {
1413         struct net_device *netdev = dev_id;
1414         struct jme_adapter *jme = netdev_priv(netdev);
1415         __u32 intrstat;
1416
1417         pci_dma_sync_single_for_cpu(jme->pdev,
1418                                     jme->shadow_dma,
1419                                     sizeof(__u32) * SHADOW_REG_NR,
1420                                     PCI_DMA_FROMDEVICE);
1421         intrstat = jme->shadow_regs[SHADOW_IEVE];
1422         jme->shadow_regs[SHADOW_IEVE] = 0;
1423
1424         jme_intr_msi(jme, intrstat);
1425
1426         return IRQ_HANDLED;
1427 }
1428
1429
1430 static void
1431 jme_reset_link(struct jme_adapter *jme)
1432 {
1433         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1434 }
1435
1436 static void
1437 jme_restart_an(struct jme_adapter *jme)
1438 {
1439         __u32 bmcr;
1440         unsigned long flags;
1441
1442         spin_lock_irqsave(&jme->phy_lock, flags);
1443         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1444         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1445         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1446         spin_unlock_irqrestore(&jme->phy_lock, flags);
1447 }
1448
1449 static int
1450 jme_request_irq(struct jme_adapter *jme)
1451 {
1452         int rc;
1453         struct net_device *netdev = jme->dev;
1454         irq_handler_t handler = jme_intr;
1455         int irq_flags = IRQF_SHARED;
1456
1457         if (!pci_enable_msi(jme->pdev)) {
1458                 jme->flags |= JME_FLAG_MSI;
1459                 handler = jme_msi;
1460                 irq_flags = 0;
1461         }
1462
1463         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1464                           netdev);
1465         if(rc) {
1466                 jeprintk(netdev->name,
1467                         "Unable to allocate %s interrupt (return: %d)\n",
1468                         jme->flags & JME_FLAG_MSI ? "MSI":"INTx", rc);
1469
1470                 if(jme->flags & JME_FLAG_MSI) {
1471                         pci_disable_msi(jme->pdev);
1472                         jme->flags &= ~JME_FLAG_MSI;
1473                 }
1474         }
1475         else {
1476                 netdev->irq = jme->pdev->irq;
1477         }
1478
1479         return rc;
1480 }
1481
1482 static void
1483 jme_free_irq(struct jme_adapter *jme)
1484 {
1485         free_irq(jme->pdev->irq, jme->dev);
1486         if (jme->flags & JME_FLAG_MSI) {
1487                 pci_disable_msi(jme->pdev);
1488                 jme->flags &= ~JME_FLAG_MSI;
1489                 jme->dev->irq = jme->pdev->irq;
1490         }
1491 }
1492
1493 static int
1494 jme_open(struct net_device *netdev)
1495 {
1496         struct jme_adapter *jme = netdev_priv(netdev);
1497         int rc, timeout = 100;
1498
1499         while(
1500                 --timeout > 0 &&
1501                 (
1502                 atomic_read(&jme->link_changing) != 1 ||
1503                 atomic_read(&jme->rx_cleaning) != 1 ||
1504                 atomic_read(&jme->tx_cleaning) != 1
1505                 )
1506         )
1507                 msleep(10);
1508
1509         if(!timeout) {
1510                 rc = -EBUSY;
1511                 goto err_out;
1512         }
1513
1514         jme_clear_pm(jme);
1515         jme_reset_mac_processor(jme);
1516
1517         rc = jme_request_irq(jme);
1518         if(rc)
1519                 goto err_out;
1520
1521         jme_enable_shadow(jme);
1522         jme_start_irq(jme);
1523
1524         if(jme->flags & JME_FLAG_SSET)
1525                 jme_set_settings(netdev, &jme->old_ecmd);
1526         else
1527                 jme_reset_phy_processor(jme);
1528
1529         jme_reset_link(jme);
1530
1531         return 0;
1532
1533 err_out:
1534         netif_stop_queue(netdev);
1535         netif_carrier_off(netdev);
1536         return rc;
1537 }
1538
1539 static void
1540 jme_set_100m_half(struct jme_adapter *jme)
1541 {
1542         __u32 bmcr, tmp;
1543
1544         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1545         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1546                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1547         tmp |= BMCR_SPEED100;
1548
1549         if (bmcr != tmp)
1550                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1551
1552         jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1553 }
1554
1555 static void
1556 jme_phy_off(struct jme_adapter *jme)
1557 {
1558         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1559 }
1560
1561
1562 static int
1563 jme_close(struct net_device *netdev)
1564 {
1565         struct jme_adapter *jme = netdev_priv(netdev);
1566
1567         netif_stop_queue(netdev);
1568         netif_carrier_off(netdev);
1569
1570         jme_stop_irq(jme);
1571         jme_disable_shadow(jme);
1572         jme_free_irq(jme);
1573
1574         tasklet_kill(&jme->linkch_task);
1575         tasklet_kill(&jme->txclean_task);
1576         tasklet_kill(&jme->rxclean_task);
1577         tasklet_kill(&jme->rxempty_task);
1578
1579         jme_reset_mac_processor(jme);
1580         jme_free_rx_resources(jme);
1581         jme_free_tx_resources(jme);
1582         jme->phylink = 0;
1583
1584         if(jme->reg_pmcs) {
1585                 jme_set_100m_half(jme);
1586                 pci_enable_wake(jme->pdev, PCI_D0, true);
1587                 pci_enable_wake(jme->pdev, PCI_D3hot, true);
1588                 pci_enable_wake(jme->pdev, PCI_D3cold, true);
1589                 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1590         }
1591         else {
1592                 jme_phy_off(jme);
1593         }
1594
1595         return 0;
1596 }
1597
1598 /*
1599  * This function is already protected by netif_tx_lock()
1600  */
1601 static int
1602 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1603 {
1604         struct jme_adapter *jme = netdev_priv(netdev);
1605         int rc;
1606
1607         if(unlikely(netif_queue_stopped(jme->dev)))
1608                 return NETDEV_TX_BUSY;
1609
1610 #if 0
1611 /*Testing*/
1612         ("jme", "Frags: %d Headlen: %d Len: %d Sum:%d\n", 
1613                 skb_shinfo(skb)->nr_frags,
1614                 skb_headlen(skb),
1615                 skb->len,
1616                 skb->ip_summed);
1617 /*********/
1618 #endif
1619
1620         rc = jme_set_new_txdesc(jme, skb);
1621
1622         if(unlikely(rc != NETDEV_TX_OK))
1623                 return rc;
1624
1625         jwrite32(jme, JME_TXCS, jme->reg_txcs |
1626                                 TXCS_SELECT_QUEUE0 |
1627                                 TXCS_QUEUE0S |
1628                                 TXCS_ENABLE);
1629         netdev->trans_start = jiffies;
1630
1631         return NETDEV_TX_OK;
1632 }
1633
1634 static int
1635 jme_set_macaddr(struct net_device *netdev, void *p)
1636 {
1637         struct jme_adapter *jme = netdev_priv(netdev);
1638         struct sockaddr *addr = p;
1639         __u32 val;
1640
1641         if(netif_running(netdev))
1642                 return -EBUSY;
1643
1644         spin_lock(&jme->macaddr_lock);
1645         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1646
1647         val = addr->sa_data[3] << 24 |
1648               addr->sa_data[2] << 16 |
1649               addr->sa_data[1] <<  8 |
1650               addr->sa_data[0];
1651         jwrite32(jme, JME_RXUMA_LO, val);
1652         val = addr->sa_data[5] << 8 |
1653               addr->sa_data[4];
1654         jwrite32(jme, JME_RXUMA_HI, val);
1655         spin_unlock(&jme->macaddr_lock);
1656
1657         return 0;
1658 }
1659
1660 static void
1661 jme_set_multi(struct net_device *netdev)
1662 {
1663         struct jme_adapter *jme = netdev_priv(netdev);
1664         u32 mc_hash[2] = {};
1665         int i;
1666         unsigned long flags;
1667
1668         spin_lock_irqsave(&jme->rxmcs_lock, flags);
1669
1670         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1671
1672         if (netdev->flags & IFF_PROMISC) {
1673                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1674         }
1675         else if (netdev->flags & IFF_ALLMULTI) {
1676                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1677         }
1678         else if(netdev->flags & IFF_MULTICAST) {
1679                 struct dev_mc_list *mclist;
1680                 int bit_nr;
1681
1682                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1683                 for (i = 0, mclist = netdev->mc_list;
1684                         mclist && i < netdev->mc_count;
1685                         ++i, mclist = mclist->next) {
1686
1687                         bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1688                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
1689                 }
1690
1691                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1692                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
1693         }
1694
1695         wmb();
1696         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1697
1698         spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1699 }
1700
1701 static int
1702 jme_change_mtu(struct net_device *netdev, int new_mtu)
1703 {
1704         struct jme_adapter *jme = netdev_priv(netdev);
1705
1706         if(new_mtu == jme->old_mtu)
1707                 return 0;
1708
1709         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
1710                 ((new_mtu) < IPV6_MIN_MTU))
1711                 return -EINVAL;
1712
1713         if(new_mtu > 4000) {
1714                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1715                 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1716                 jme_restart_rx_engine(jme);
1717         }
1718         else {
1719                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1720                 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1721                 jme_restart_rx_engine(jme);
1722         }
1723
1724         if(new_mtu > 1900) {
1725                 netdev->features &= ~NETIF_F_HW_CSUM;
1726         }
1727         else {
1728                 netdev->features |= NETIF_F_HW_CSUM;
1729         }
1730
1731         netdev->mtu = new_mtu;
1732         jme_reset_link(jme);
1733
1734         return 0;
1735 }
1736
1737 static void
1738 jme_tx_timeout(struct net_device *netdev)
1739 {
1740         struct jme_adapter *jme = netdev_priv(netdev);
1741
1742         /*
1743          * Reset the link
1744          * And the link change will reinitiallize all RX/TX resources
1745          */
1746         jme->phylink = 0;
1747         jme_reset_link(jme);
1748 }
1749
1750 static void
1751 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
1752 {
1753         struct jme_adapter *jme = netdev_priv(netdev);
1754
1755         jme->vlgrp = grp;
1756 }
1757
1758 static void
1759 jme_get_drvinfo(struct net_device *netdev,
1760                      struct ethtool_drvinfo *info)
1761 {
1762         struct jme_adapter *jme = netdev_priv(netdev);
1763
1764         strcpy(info->driver, DRV_NAME);
1765         strcpy(info->version, DRV_VERSION);
1766         strcpy(info->bus_info, pci_name(jme->pdev));
1767 }
1768
1769 static int
1770 jme_get_regs_len(struct net_device *netdev)
1771 {
1772         return 0x400;
1773 }
1774
1775 static void
1776 mmapio_memcpy(struct jme_adapter *jme, __u32 *p, __u32 reg, int len)
1777 {
1778         int i;
1779
1780         for(i = 0 ; i < len ; i += 4)
1781                 p[i >> 2] = jread32(jme, reg + i);
1782
1783 }
1784
1785 static void
1786 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
1787 {
1788         struct jme_adapter *jme = netdev_priv(netdev);
1789         __u32 *p32 = (__u32*)p;
1790
1791         memset(p, 0, 0x400);
1792
1793         regs->version = 1;
1794         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
1795
1796         p32 += 0x100 >> 2;
1797         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
1798
1799         p32 += 0x100 >> 2;
1800         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
1801
1802         p32 += 0x100 >> 2;
1803         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
1804
1805 }
1806
1807 static int
1808 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
1809 {
1810         struct jme_adapter *jme = netdev_priv(netdev);
1811
1812         ecmd->use_adaptive_rx_coalesce = true;
1813         ecmd->tx_coalesce_usecs = PCC_TX_TO;
1814         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
1815
1816         switch(jme->dpi.cur) {
1817         case PCC_P1:
1818                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
1819                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
1820                 break;
1821         case PCC_P2:
1822                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
1823                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
1824                 break;
1825         case PCC_P3:
1826                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
1827                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
1828                 break;
1829         default:
1830                 break;
1831         }
1832
1833         return 0;
1834 }
1835
1836 /*
1837  * It's not actually for coalesce.
1838  * It changes internell FIFO related setting for testing.
1839  */
1840 static int
1841 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
1842 {
1843         struct jme_adapter *jme = netdev_priv(netdev);
1844
1845         if(ecmd->use_adaptive_rx_coalesce &&
1846         ecmd->use_adaptive_tx_coalesce &&
1847         ecmd->rx_coalesce_usecs == 250 &&
1848         (ecmd->rx_max_coalesced_frames_low == 16 ||
1849         ecmd->rx_max_coalesced_frames_low == 32 ||
1850         ecmd->rx_max_coalesced_frames_low == 64 ||
1851         ecmd->rx_max_coalesced_frames_low == 128)) {
1852                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1853                 switch(ecmd->rx_max_coalesced_frames_low) {
1854                 case 16:
1855                         jme->reg_rxcs |= RXCS_FIFOTHNP_16QW;
1856                         break;
1857                 case 32:
1858                         jme->reg_rxcs |= RXCS_FIFOTHNP_32QW;
1859                         break;
1860                 case 64:
1861                         jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1862                         break;
1863                 case 128:
1864                 default:
1865                         jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1866                 }
1867                 jme_restart_rx_engine(jme);
1868         }
1869         else {
1870                 return -EINVAL;
1871         }
1872
1873         return 0;
1874 }
1875
1876 static void
1877 jme_get_pauseparam(struct net_device *netdev,
1878                         struct ethtool_pauseparam *ecmd)
1879 {
1880         struct jme_adapter *jme = netdev_priv(netdev);
1881         unsigned long flags;
1882         __u32 val;
1883
1884         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
1885         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
1886
1887         spin_lock_irqsave(&jme->phy_lock, flags);
1888         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1889         spin_unlock_irqrestore(&jme->phy_lock, flags);
1890         ecmd->autoneg = (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
1891 }
1892
1893 static int
1894 jme_set_pauseparam(struct net_device *netdev,
1895                         struct ethtool_pauseparam *ecmd)
1896 {
1897         struct jme_adapter *jme = netdev_priv(netdev);
1898         unsigned long flags;
1899         __u32 val;
1900
1901         if( ((jme->reg_txpfc & TXPFC_PF_EN) != 0) !=
1902                 (ecmd->tx_pause != 0)) {
1903
1904                 if(ecmd->tx_pause)
1905                         jme->reg_txpfc |= TXPFC_PF_EN;
1906                 else
1907                         jme->reg_txpfc &= ~TXPFC_PF_EN;
1908
1909                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
1910         }
1911
1912         spin_lock_irqsave(&jme->rxmcs_lock, flags);
1913         if( ((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) !=
1914                 (ecmd->rx_pause != 0)) {
1915
1916                 if(ecmd->rx_pause)
1917                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
1918                 else
1919                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
1920
1921                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1922         }
1923         spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1924
1925         spin_lock_irqsave(&jme->phy_lock, flags);
1926         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1927         if( ((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) != 
1928                 (ecmd->autoneg != 0)) {
1929
1930                 if(ecmd->autoneg)
1931                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1932                 else
1933                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1934
1935                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE, val);
1936         }
1937         spin_unlock_irqrestore(&jme->phy_lock, flags);
1938
1939         return 0;
1940 }
1941
1942 static void
1943 jme_get_wol(struct net_device *netdev,
1944                 struct ethtool_wolinfo *wol)
1945 {
1946         struct jme_adapter *jme = netdev_priv(netdev);
1947
1948         wol->supported = WAKE_MAGIC | WAKE_PHY;
1949
1950         wol->wolopts = 0;
1951
1952         if(jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1953                 wol->wolopts |= WAKE_PHY;
1954
1955         if(jme->reg_pmcs & PMCS_MFEN)
1956                 wol->wolopts |= WAKE_MAGIC;
1957
1958 }
1959
1960 static int
1961 jme_set_wol(struct net_device *netdev,
1962                 struct ethtool_wolinfo *wol)
1963 {
1964         struct jme_adapter *jme = netdev_priv(netdev);
1965
1966         if(wol->wolopts & (WAKE_MAGICSECURE |
1967                                 WAKE_UCAST |
1968                                 WAKE_MCAST |
1969                                 WAKE_BCAST |
1970                                 WAKE_ARP))
1971                 return -EOPNOTSUPP;
1972
1973         jme->reg_pmcs = 0;
1974
1975         if(wol->wolopts & WAKE_PHY)
1976                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
1977
1978         if(wol->wolopts & WAKE_MAGIC)
1979                 jme->reg_pmcs |= PMCS_MFEN;
1980
1981
1982         return 0;
1983 }
1984  
1985 static int
1986 jme_get_settings(struct net_device *netdev,
1987                      struct ethtool_cmd *ecmd)
1988 {
1989         struct jme_adapter *jme = netdev_priv(netdev);
1990         int rc;
1991         unsigned long flags;
1992
1993         spin_lock_irqsave(&jme->phy_lock, flags);
1994         rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
1995         spin_unlock_irqrestore(&jme->phy_lock, flags);
1996         return rc;
1997 }
1998
1999 static int
2000 jme_set_settings(struct net_device *netdev,
2001                      struct ethtool_cmd *ecmd)
2002 {
2003         struct jme_adapter *jme = netdev_priv(netdev);
2004         int rc, fdc=0;
2005         unsigned long flags;
2006
2007         if(ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2008                 return -EINVAL;
2009
2010         if(jme->mii_if.force_media &&
2011         ecmd->autoneg != AUTONEG_ENABLE &&
2012         (jme->mii_if.full_duplex != ecmd->duplex))
2013                 fdc = 1;
2014
2015         spin_lock_irqsave(&jme->phy_lock, flags);
2016         rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2017         spin_unlock_irqrestore(&jme->phy_lock, flags);
2018
2019         if(!rc && fdc)
2020                 jme_reset_link(jme);
2021
2022         if(!rc) {
2023                 jme->flags |= JME_FLAG_SSET;
2024                 jme->old_ecmd = *ecmd;
2025         }
2026
2027         return rc;
2028 }
2029
2030 static __u32
2031 jme_get_link(struct net_device *netdev)
2032 {
2033         struct jme_adapter *jme = netdev_priv(netdev);
2034         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2035 }
2036
2037 static u32
2038 jme_get_rx_csum(struct net_device *netdev)
2039 {
2040         struct jme_adapter *jme = netdev_priv(netdev);
2041
2042         return jme->reg_rxmcs & RXMCS_CHECKSUM;
2043 }
2044
2045 static int
2046 jme_set_rx_csum(struct net_device *netdev, u32 on)
2047 {
2048         struct jme_adapter *jme = netdev_priv(netdev);
2049         unsigned long flags;
2050         
2051         spin_lock_irqsave(&jme->rxmcs_lock, flags);
2052         if(on)
2053                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2054         else
2055                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2056         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2057         spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2058
2059         return 0;
2060 }
2061
2062 static int
2063 jme_set_tx_csum(struct net_device *netdev, u32 on)
2064 {
2065         if(on && netdev->mtu <= 1900)
2066                 netdev->features |= NETIF_F_HW_CSUM;
2067         else
2068                 netdev->features &= ~NETIF_F_HW_CSUM;
2069
2070         return 0;
2071 }
2072
2073 static int
2074 jme_nway_reset(struct net_device *netdev)
2075 {
2076         struct jme_adapter *jme = netdev_priv(netdev);
2077         jme_restart_an(jme);
2078         return 0;
2079 }
2080
2081 static const struct ethtool_ops jme_ethtool_ops = {
2082         .get_drvinfo            = jme_get_drvinfo,
2083         .get_regs_len           = jme_get_regs_len,
2084         .get_regs               = jme_get_regs,
2085         .get_coalesce           = jme_get_coalesce,
2086         .set_coalesce           = jme_set_coalesce,
2087         .get_pauseparam         = jme_get_pauseparam,
2088         .set_pauseparam         = jme_set_pauseparam,
2089         .get_wol                = jme_get_wol,
2090         .set_wol                = jme_set_wol,
2091         .get_settings           = jme_get_settings,
2092         .set_settings           = jme_set_settings,
2093         .get_link               = jme_get_link,
2094         .get_rx_csum            = jme_get_rx_csum,
2095         .set_rx_csum            = jme_set_rx_csum,
2096         .set_tx_csum            = jme_set_tx_csum,
2097         .nway_reset             = jme_nway_reset,
2098 };
2099
2100 static int
2101 jme_pci_dma64(struct pci_dev *pdev)
2102 {
2103         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2104                 if(!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
2105                         dprintk("jme", "64Bit DMA Selected.\n");
2106                         return 1;
2107                 }
2108
2109         if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2110                 if(!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK)) {
2111                         dprintk("jme", "40Bit DMA Selected.\n");
2112                         return 1;
2113                 }
2114
2115         if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2116                 if(!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
2117                         dprintk("jme", "32Bit DMA Selected.\n");
2118                         return 0;
2119                 }
2120
2121         return -1;
2122 }
2123
2124 __always_inline static void
2125 jme_set_phy_ps(struct jme_adapter *jme)
2126 {
2127         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, 0x00001000);
2128 }
2129
2130 static int __devinit
2131 jme_init_one(struct pci_dev *pdev,
2132              const struct pci_device_id *ent)
2133 {
2134         int rc = 0, using_dac;
2135         struct net_device *netdev;
2136         struct jme_adapter *jme;
2137
2138         /*
2139          * set up PCI device basics
2140          */
2141         rc = pci_enable_device(pdev);
2142         if(rc) {
2143                 printk(KERN_ERR PFX "Cannot enable PCI device.\n");
2144                 goto err_out;
2145         }
2146
2147         using_dac = jme_pci_dma64(pdev);
2148         if(using_dac < 0) {
2149                 printk(KERN_ERR PFX "Cannot set PCI DMA Mask.\n");
2150                 rc = -EIO;
2151                 goto err_out_disable_pdev;
2152         }
2153
2154         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2155                 printk(KERN_ERR PFX "No PCI resource region found.\n");
2156                 rc = -ENOMEM;
2157                 goto err_out_disable_pdev;
2158         }
2159
2160         rc = pci_request_regions(pdev, DRV_NAME);
2161         if(rc) {
2162                 printk(KERN_ERR PFX "Cannot obtain PCI resource region.\n");
2163                 goto err_out_disable_pdev;
2164         }
2165
2166         pci_set_master(pdev);
2167
2168         /*
2169          * alloc and init net device
2170          */
2171         netdev = alloc_etherdev(sizeof(*jme));
2172         if(!netdev) {
2173                 printk(KERN_ERR PFX "Cannot allocate netdev structure.\n");
2174                 rc = -ENOMEM;
2175                 goto err_out_release_regions;
2176         }
2177         netdev->open                    = jme_open;
2178         netdev->stop                    = jme_close;
2179         netdev->hard_start_xmit         = jme_start_xmit;
2180         netdev->set_mac_address         = jme_set_macaddr;
2181         netdev->set_multicast_list      = jme_set_multi;
2182         netdev->change_mtu              = jme_change_mtu;
2183         netdev->ethtool_ops             = &jme_ethtool_ops;
2184         netdev->tx_timeout              = jme_tx_timeout;
2185         netdev->watchdog_timeo          = TX_TIMEOUT;
2186         netdev->vlan_rx_register        = jme_vlan_rx_register;
2187         NETDEV_GET_STATS(netdev, &jme_get_stats);
2188         netdev->features                =       NETIF_F_HW_CSUM |
2189                                                 NETIF_F_HW_VLAN_TX |
2190                                                 NETIF_F_HW_VLAN_RX;
2191         if(using_dac)
2192                 netdev->features        |=      NETIF_F_HIGHDMA;
2193
2194         SET_NETDEV_DEV(netdev, &pdev->dev);
2195         pci_set_drvdata(pdev, netdev);
2196
2197         /*
2198          * init adapter info
2199          */
2200         jme = netdev_priv(netdev);
2201         jme->pdev = pdev;
2202         jme->dev = netdev;
2203         jme->old_mtu = netdev->mtu = 1500;
2204         jme->phylink = 0;
2205         jme->regs = ioremap(pci_resource_start(pdev, 0),
2206                              pci_resource_len(pdev, 0));
2207         if (!(jme->regs)) {
2208                 printk(KERN_ERR PFX "Mapping PCI resource region error.\n");
2209                 rc = -ENOMEM;
2210                 goto err_out_free_netdev;
2211         }
2212         jme->shadow_regs = pci_alloc_consistent(pdev,
2213                                                 sizeof(__u32) * SHADOW_REG_NR,
2214                                                 &(jme->shadow_dma));
2215         if (!(jme->shadow_regs)) {
2216                 printk(KERN_ERR PFX "Allocating shadow register mapping error.\n");
2217                 rc = -ENOMEM;
2218                 goto err_out_unmap;
2219         }
2220
2221         spin_lock_init(&jme->phy_lock);
2222         spin_lock_init(&jme->macaddr_lock);
2223         spin_lock_init(&jme->rxmcs_lock);
2224
2225         atomic_set(&jme->link_changing, 1);
2226         atomic_set(&jme->rx_cleaning, 1);
2227         atomic_set(&jme->tx_cleaning, 1);
2228
2229         tasklet_init(&jme->pcc_task,
2230                      &jme_pcc_tasklet,
2231                      (unsigned long) jme);
2232         tasklet_init(&jme->linkch_task,
2233                      &jme_link_change_tasklet,
2234                      (unsigned long) jme);
2235         tasklet_init(&jme->txclean_task,
2236                      &jme_tx_clean_tasklet,
2237                      (unsigned long) jme);
2238         tasklet_init(&jme->rxclean_task,
2239                      &jme_rx_clean_tasklet,
2240                      (unsigned long) jme);
2241         tasklet_init(&jme->rxempty_task,
2242                      &jme_rx_empty_tasklet,
2243                      (unsigned long) jme);
2244         jme->mii_if.dev = netdev;
2245         jme->mii_if.phy_id = 1;
2246         jme->mii_if.supports_gmii = 1;
2247         jme->mii_if.mdio_read = jme_mdio_read;
2248         jme->mii_if.mdio_write = jme_mdio_write;
2249
2250         jme->dpi.cur = PCC_P1;
2251
2252         jme->reg_ghc = GHC_DPX | GHC_SPEED_1000M;
2253         jme->reg_rxcs = RXCS_DEFAULT;
2254         jme->reg_rxmcs = RXMCS_DEFAULT;
2255         jme->reg_txpfc = 0;
2256         jme->reg_pmcs = 0;
2257         /*
2258          * Get Max Read Req Size from PCI Config Space
2259          */
2260         pci_read_config_byte(pdev, PCI_CONF_DCSR_MRRS, &jme->mrrs);
2261         switch(jme->mrrs) {
2262                 case MRRS_128B:
2263                         jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2264                         break;
2265                 case MRRS_256B:
2266                         jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2267                         break;
2268                 default:
2269                         jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2270                         break;
2271         };
2272
2273
2274         /*
2275          * Reset MAC processor and reload EEPROM for MAC Address
2276          */
2277         jme_clear_pm(jme);
2278         jme_set_phy_ps(jme);
2279         jme_phy_off(jme);
2280         jme_reset_mac_processor(jme);
2281         rc = jme_reload_eeprom(jme);
2282         if(rc) {
2283                 printk(KERN_ERR PFX
2284                         "Rload eeprom for reading MAC Address error.\n");
2285                 goto err_out_free_shadow;
2286         }
2287         jme_load_macaddr(netdev);
2288
2289
2290         /*
2291          * Tell stack that we are not ready to work until open()
2292          */
2293         netif_carrier_off(netdev);
2294         netif_stop_queue(netdev);
2295
2296         /*
2297          * Register netdev
2298          */
2299         rc = register_netdev(netdev);
2300         if(rc) {
2301                 printk(KERN_ERR PFX "Cannot register net device.\n");
2302                 goto err_out_free_shadow;
2303         }
2304
2305         jprintk(netdev->name,
2306                 "JMC250 gigabit eth %02x:%02x:%02x:%02x:%02x:%02x\n",
2307                 netdev->dev_addr[0],
2308                 netdev->dev_addr[1],
2309                 netdev->dev_addr[2],
2310                 netdev->dev_addr[3],
2311                 netdev->dev_addr[4],
2312                 netdev->dev_addr[5]);
2313
2314         return 0;
2315
2316 err_out_free_shadow:
2317         pci_free_consistent(pdev,
2318                             sizeof(__u32) * SHADOW_REG_NR,
2319                             jme->shadow_regs,
2320                             jme->shadow_dma);
2321 err_out_unmap:
2322         iounmap(jme->regs);
2323 err_out_free_netdev:
2324         pci_set_drvdata(pdev, NULL);
2325         free_netdev(netdev);
2326 err_out_release_regions:
2327         pci_release_regions(pdev);
2328 err_out_disable_pdev:
2329         pci_disable_device(pdev);
2330 err_out:
2331         return rc;
2332 }
2333
2334 static void __devexit
2335 jme_remove_one(struct pci_dev *pdev)
2336 {
2337         struct net_device *netdev = pci_get_drvdata(pdev);
2338         struct jme_adapter *jme = netdev_priv(netdev);
2339
2340         unregister_netdev(netdev);
2341         pci_free_consistent(pdev,
2342                             sizeof(__u32) * SHADOW_REG_NR,
2343                             jme->shadow_regs,
2344                             jme->shadow_dma);
2345         iounmap(jme->regs);
2346         pci_set_drvdata(pdev, NULL);
2347         free_netdev(netdev);
2348         pci_release_regions(pdev);
2349         pci_disable_device(pdev);
2350
2351 }
2352
2353 static int
2354 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2355 {
2356         struct net_device *netdev = pci_get_drvdata(pdev);
2357         struct jme_adapter *jme = netdev_priv(netdev);
2358         int timeout = 100;
2359
2360         atomic_dec(&jme->link_changing);
2361
2362         netif_device_detach(netdev);
2363         netif_stop_queue(netdev);
2364         jme_stop_irq(jme);
2365         jme_free_irq(jme);
2366
2367         while(--timeout > 0 &&
2368         (
2369                 atomic_read(&jme->rx_cleaning) != 1 ||
2370                 atomic_read(&jme->tx_cleaning) != 1
2371         )) {
2372                 mdelay(1);
2373         }
2374         if(!timeout) {
2375                 jeprintk(netdev->name, "Waiting tasklets timeout.\n");
2376                 return -EBUSY;
2377         }
2378         jme_disable_shadow(jme);
2379
2380         if(netif_carrier_ok(netdev)) {
2381                 jme_stop_pcc_timer(jme);
2382                 jme_reset_mac_processor(jme);
2383                 jme_free_rx_resources(jme);
2384                 jme_free_tx_resources(jme);
2385                 netif_carrier_off(netdev);
2386                 jme->phylink = 0;
2387         }
2388
2389
2390         pci_save_state(pdev);
2391         if(jme->reg_pmcs) {
2392                 jme_set_100m_half(jme);
2393                 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2394                 pci_enable_wake(pdev, PCI_D3hot, true);
2395                 pci_enable_wake(pdev, PCI_D3cold, true);
2396         }
2397         else {
2398                 jme_phy_off(jme);
2399                 pci_enable_wake(pdev, PCI_D3hot, false);
2400                 pci_enable_wake(pdev, PCI_D3cold, false);
2401         }
2402         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2403
2404         return 0;
2405 }
2406
2407 static int
2408 jme_resume(struct pci_dev *pdev)
2409 {
2410         struct net_device *netdev = pci_get_drvdata(pdev);
2411         struct jme_adapter *jme = netdev_priv(netdev);
2412
2413         jme_clear_pm(jme);
2414         pci_restore_state(pdev);
2415
2416         if(jme->flags & JME_FLAG_SSET)
2417                 jme_set_settings(netdev, &jme->old_ecmd);
2418         else
2419                 jme_reset_phy_processor(jme);
2420
2421         jme_reset_mac_processor(jme);
2422         jme_enable_shadow(jme);
2423         jme_request_irq(jme);
2424         jme_start_irq(jme);
2425         netif_device_attach(netdev);
2426
2427         atomic_inc(&jme->link_changing);
2428
2429         jme_reset_link(jme);
2430
2431         return 0;
2432 }
2433
2434 static struct pci_device_id jme_pci_tbl[] = {
2435         { PCI_VDEVICE(JMICRON, 0x250) },
2436         { }
2437 };
2438
2439 static struct pci_driver jme_driver = {
2440         .name           = DRV_NAME,
2441         .id_table       = jme_pci_tbl,
2442         .probe          = jme_init_one,
2443         .remove         = __devexit_p(jme_remove_one),
2444 #ifdef CONFIG_PM
2445         .suspend        = jme_suspend,
2446         .resume         = jme_resume,
2447 #endif /* CONFIG_PM */
2448 };
2449
2450 static int __init
2451 jme_init_module(void)
2452 {
2453         printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
2454                "driver version %s\n", DRV_VERSION);
2455         return pci_register_driver(&jme_driver);
2456 }
2457
2458 static void __exit
2459 jme_cleanup_module(void)
2460 {
2461         pci_unregister_driver(&jme_driver);
2462 }
2463
2464 module_init(jme_init_module);
2465 module_exit(jme_cleanup_module);
2466
2467 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
2468 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
2469 MODULE_LICENSE("GPL");
2470 MODULE_VERSION(DRV_VERSION);
2471 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
2472