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ethtool: Use full 32 bit speed range in ethtool's set_settings
[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT		 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
2e582300 25#include <linux/version.h>
937ef75a
JP		 26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
d7699f87
GFT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
4330c2f2 38#include <linux/delay.h>
29bdd921 39#include <linux/spinlock.h>
8c198884
GFT		 40#include <linux/in.h>
41#include <linux/ip.h>
79ce639c
GFT		 42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
42b1055e 45#include <linux/if_vlan.h>
38d1bc09 46#include <linux/slab.h>
3b70a6fa 47#include <net/ip6_checksum.h>
d7699f87
GFT		 48#include "jme.h"
49
cd0ff491
GFT		 50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 61
3d12cc1b
GFT		 62static void
63jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
64{
65#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
66 pci_enable_wake(jme->pdev, PCI_D1, enable);
67 pci_enable_wake(jme->pdev, PCI_D2, enable);
68 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
69 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
70#else
71 pci_pme_active(jme->pdev, enable);
72#endif
73}
74
3bf61c55
GFT		 75static int
76jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 77{
78 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 79 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 80
186fc259 81read_again:
cd0ff491 82 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 83 smi_phy_addr(phy) |
84 smi_reg_addr(reg));
d7699f87
GFT		 85
86 wmb();
cd0ff491 87 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 88 udelay(20);
b3821cc5
GFT		 89 val = jread32(jme, JME_SMI);
90 if ((val & SMI_OP_REQ) == 0)
3bf61c55 91 break;
cd0ff491 92 }
d7699f87 93
cd0ff491 94 if (i == 0) {
937ef75a 95 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 96 return 0;
cd0ff491 97 }
d7699f87 98
cd0ff491 99 if (again--)
186fc259
GFT		 100 goto read_again;
101
cd0ff491 102 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 103}
104
3bf61c55
GFT		 105static void
106jme_mdio_write(struct net_device *netdev,
107 int phy, int reg, int val)
d7699f87
GFT		 108{
109 struct jme_adapter *jme = netdev_priv(netdev);
110 int i;
111
3bf61c55
GFT		 112 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
113 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
114 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 115
116 wmb();
cdcdc9eb
GFT		 117 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
118 udelay(20);
8d27293f 119 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 120 break;
121 }
d7699f87 122
3bf61c55 123 if (i == 0)
937ef75a 124 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT		 125}
126
cd0ff491 127static inline void
3bf61c55 128jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 129{
cd0ff491 130 u32 val;
3bf61c55
GFT		 131
132 jme_mdio_write(jme->dev,
133 jme->mii_if.phy_id,
8c198884
GFT		 134 MII_ADVERTISE, ADVERTISE_ALL |
135 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 136
cd0ff491 137 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 138 jme_mdio_write(jme->dev,
139 jme->mii_if.phy_id,
140 MII_CTRL1000,
141 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 142
fcf45b4c
GFT		 143 val = jme_mdio_read(jme->dev,
144 jme->mii_if.phy_id,
145 MII_BMCR);
146
147 jme_mdio_write(jme->dev,
148 jme->mii_if.phy_id,
149 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT		 150}
151
b3821cc5
GFT		 152static void
153jme_setup_wakeup_frame(struct jme_adapter *jme,
a4181cd4 154 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 155{
156 int i;
157
158 /*
159 * Setup CRC pattern
160 */
161 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
162 wmb();
163 jwrite32(jme, JME_WFODP, crc);
164 wmb();
165
166 /*
167 * Setup Mask
168 */
cd0ff491 169 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 170 jwrite32(jme, JME_WFOI,
171 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
172 (fnr & WFOI_FRAME_SEL));
173 wmb();
174 jwrite32(jme, JME_WFODP, mask[i]);
175 wmb();
176 }
177}
3bf61c55 178
dc4185bd
GFT		 179static inline void
180jme_mac_rxclk_off(struct jme_adapter *jme)
181{
182 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
183 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
184}
185
186static inline void
187jme_mac_rxclk_on(struct jme_adapter *jme)
188{
189 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
190 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
191}
192
193static inline void
194jme_mac_txclk_off(struct jme_adapter *jme)
195{
196 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
197 jwrite32f(jme, JME_GHC, jme->reg_ghc);
198}
199
200static inline void
201jme_mac_txclk_on(struct jme_adapter *jme)
202{
203 u32 speed = jme->reg_ghc & GHC_SPEED;
204 if (speed == GHC_SPEED_1000M)
205 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
206 else
207 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
208 jwrite32f(jme, JME_GHC, jme->reg_ghc);
209}
210
211static inline void
212jme_reset_ghc_speed(struct jme_adapter *jme)
213{
214 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
215 jwrite32f(jme, JME_GHC, jme->reg_ghc);
216}
217
218static inline void
219jme_reset_250A2_workaround(struct jme_adapter *jme)
220{
221 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
222 GPREG1_RSSPATCH);
223 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
224}
225
226static inline void
227jme_assert_ghc_reset(struct jme_adapter *jme)
228{
229 jme->reg_ghc |= GHC_SWRST;
230 jwrite32f(jme, JME_GHC, jme->reg_ghc);
231}
232
233static inline void
234jme_clear_ghc_reset(struct jme_adapter *jme)
235{
236 jme->reg_ghc &= ~GHC_SWRST;
237 jwrite32f(jme, JME_GHC, jme->reg_ghc);
238}
239
cd0ff491 240static inline void
3bf61c55
GFT		 241jme_reset_mac_processor(struct jme_adapter *jme)
242{
a4181cd4 243 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT		 244 u32 crc = 0xCDCDCDCD;
245 u32 gpreg0;
b3821cc5
GFT		 246 int i;
247
dc4185bd
GFT		 248 jme_reset_ghc_speed(jme);
249 jme_reset_250A2_workaround(jme);
250
251 jme_mac_rxclk_on(jme);
252 jme_mac_txclk_on(jme);
253 udelay(1);
254 jme_assert_ghc_reset(jme);
255 udelay(1);
256 jme_mac_rxclk_off(jme);
257 jme_mac_txclk_off(jme);
258 udelay(1);
259 jme_clear_ghc_reset(jme);
260 udelay(1);
261 jme_mac_rxclk_on(jme);
262 jme_mac_txclk_on(jme);
263 udelay(1);
264 jme_mac_rxclk_off(jme);
265 jme_mac_txclk_off(jme);
cd0ff491
GFT		 266
267 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
268 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
269 jwrite32(jme, JME_RXQDC, 0x00000000);
270 jwrite32(jme, JME_RXNDA, 0x00000000);
271 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
272 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
273 jwrite32(jme, JME_TXQDC, 0x00000000);
274 jwrite32(jme, JME_TXNDA, 0x00000000);
275
4330c2f2
GFT		 276 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
277 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 278 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 279 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 280 if (jme->fpgaver)
cdcdc9eb
GFT		 281 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
282 else
283 gpreg0 = GPREG0_DEFAULT;
284 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT		 285}
286
287static inline void
3bf61c55 288jme_clear_pm(struct jme_adapter *jme)
d7699f87 289{
3d12cc1b 290 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
d7699f87
GFT		 291}
292
3bf61c55
GFT		 293static int
294jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 295{
cd0ff491 296 u32 val;
d7699f87
GFT		 297 int i;
298
299 val = jread32(jme, JME_SMBCSR);
300
cd0ff491 301 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 302 val |= SMBCSR_CNACK;
303 jwrite32(jme, JME_SMBCSR, val);
304 val |= SMBCSR_RELOAD;
305 jwrite32(jme, JME_SMBCSR, val);
306 mdelay(12);
307
cd0ff491 308 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 309 mdelay(1);
310 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
311 break;
312 }
313
cd0ff491 314 if (i == 0) {
937ef75a 315 pr_err("eeprom reload timeout\n");
d7699f87
GFT		 316 return -EIO;
317 }
318 }
3bf61c55 319
d7699f87
GFT		 320 return 0;
321}
322
3bf61c55
GFT		 323static void
324jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 325{
326 struct jme_adapter *jme = netdev_priv(netdev);
327 unsigned char macaddr[6];
cd0ff491 328 u32 val;
d7699f87 329
cd0ff491 330 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 331 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 332 macaddr[0] = (val >> 0) & 0xFF;
333 macaddr[1] = (val >> 8) & 0xFF;
334 macaddr[2] = (val >> 16) & 0xFF;
335 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 336 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 337 macaddr[4] = (val >> 0) & 0xFF;
338 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 339 memcpy(netdev->dev_addr, macaddr, 6);
340 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 341}
342
cd0ff491 343static inline void
3bf61c55
GFT		 344jme_set_rx_pcc(struct jme_adapter *jme, int p)
345{
cd0ff491 346 switch (p) {
192570e0
GFT		 347 case PCC_OFF:
348 jwrite32(jme, JME_PCCRX0,
349 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
350 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
351 break;
3bf61c55
GFT		 352 case PCC_P1:
353 jwrite32(jme, JME_PCCRX0,
354 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
355 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
356 break;
357 case PCC_P2:
358 jwrite32(jme, JME_PCCRX0,
359 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
360 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
361 break;
362 case PCC_P3:
363 jwrite32(jme, JME_PCCRX0,
364 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
365 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
366 break;
367 default:
368 break;
369 }
192570e0 370 wmb();
3bf61c55 371
cd0ff491 372 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
7ca9ebee 373 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 374}
375
fcf45b4c 376static void
3bf61c55 377jme_start_irq(struct jme_adapter *jme)
d7699f87 378{
3bf61c55
GFT		 379 register struct dynpcc_info *dpi = &(jme->dpi);
380
381 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 382 dpi->cur = PCC_P1;
383 dpi->attempt = PCC_P1;
384 dpi->cnt = 0;
385
386 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 387 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
388 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 389 PCCTXQ0_EN
390 );
391
d7699f87
GFT		 392 /*
393 * Enable Interrupts
394 */
395 jwrite32(jme, JME_IENS, INTR_ENABLE);
396}
397
cd0ff491 398static inline void
3bf61c55 399jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 400{
401 /*
402 * Disable Interrupts
403 */
cd0ff491 404 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 405}
406
cd0ff491 407static u32
cdcdc9eb
GFT		 408jme_linkstat_from_phy(struct jme_adapter *jme)
409{
cd0ff491 410 u32 phylink, bmsr;
cdcdc9eb
GFT		 411
412 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
413 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 414 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 415 phylink |= PHY_LINK_AUTONEG_COMPLETE;
416
417 return phylink;
418}
419
cd0ff491 420static inline void
55d19799 421jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT		 422{
423 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
424}
425
426static inline void
55d19799 427jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT		 428{
429 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
430}
431
fcf45b4c
GFT		 432static int
433jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 434{
435 struct jme_adapter *jme = netdev_priv(netdev);
dc4185bd 436 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 437 char linkmsg[64];
fcf45b4c 438 int rc = 0;
d7699f87 439
b3821cc5 440 linkmsg[0] = '\0';
cdcdc9eb 441
cd0ff491 442 if (jme->fpgaver)
cdcdc9eb
GFT		 443 phylink = jme_linkstat_from_phy(jme);
444 else
445 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 446
cd0ff491
GFT		 447 if (phylink & PHY_LINK_UP) {
448 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 449 /*
450 * If we did not enable AN
451 * Speed/Duplex Info should be obtained from SMI
452 */
453 phylink = PHY_LINK_UP;
454
455 bmcr = jme_mdio_read(jme->dev,
456 jme->mii_if.phy_id,
457 MII_BMCR);
458
459 phylink |= ((bmcr & BMCR_SPEED1000) &&
460 (bmcr & BMCR_SPEED100) == 0) ?
461 PHY_LINK_SPEED_1000M :
462 (bmcr & BMCR_SPEED100) ?
463 PHY_LINK_SPEED_100M :
464 PHY_LINK_SPEED_10M;
465
466 phylink |= (bmcr & BMCR_FULLDPLX) ?
467 PHY_LINK_DUPLEX : 0;
79ce639c 468
b3821cc5 469 strcat(linkmsg, "Forced: ");
cd0ff491 470 } else {
8c198884
GFT		 471 /*
472 * Keep polling for speed/duplex resolve complete
473 */
cd0ff491 474 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 475 --cnt) {
476
477 udelay(1);
8c198884 478
cd0ff491 479 if (jme->fpgaver)
cdcdc9eb
GFT		 480 phylink = jme_linkstat_from_phy(jme);
481 else
482 phylink = jread32(jme, JME_PHY_LINK);
8c198884 483 }
cd0ff491 484 if (!cnt)
937ef75a 485 pr_err("Waiting speed resolve timeout\n");
79ce639c 486
b3821cc5 487 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 488 }
489
cd0ff491 490 if (jme->phylink == phylink) {
fcf45b4c
GFT		 491 rc = 1;
492 goto out;
493 }
cd0ff491 494 if (testonly)
fcf45b4c
GFT		 495 goto out;
496
497 jme->phylink = phylink;
498
dc4185bd
GFT		 499 /*
500 * The speed/duplex setting of jme->reg_ghc already cleared
501 * by jme_reset_mac_processor()
502 */
cd0ff491
GFT		 503 switch (phylink & PHY_LINK_SPEED_MASK) {
504 case PHY_LINK_SPEED_10M:
dc4185bd 505 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 506 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 507 break;
508 case PHY_LINK_SPEED_100M:
dc4185bd 509 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 510 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 511 break;
512 case PHY_LINK_SPEED_1000M:
dc4185bd 513 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 514 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 515 break;
516 default:
517 break;
d7699f87 518 }
d7699f87 519
cd0ff491 520 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 521 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
809b2798 522 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
dc4185bd 523 jme->reg_ghc |= GHC_DPX;
cd0ff491 524 } else {
d7699f87 525 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 526 TXMCS_BACKOFF |
527 TXMCS_CARRIERSENSE |
528 TXMCS_COLLISION);
809b2798 529 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 530 }
7ee473a3 531
dc4185bd
GFT		 532 jwrite32(jme, JME_GHC, jme->reg_ghc);
533
7ee473a3 534 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
dc4185bd
GFT		 535 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
536 GPREG1_RSSPATCH);
7ee473a3 537 if (!(phylink & PHY_LINK_DUPLEX))
dc4185bd 538 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
7ee473a3
GFT		 539 switch (phylink & PHY_LINK_SPEED_MASK) {
540 case PHY_LINK_SPEED_10M:
55d19799 541 jme_set_phyfifo_8level(jme);
dc4185bd 542 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 543 break;
544 case PHY_LINK_SPEED_100M:
55d19799 545 jme_set_phyfifo_5level(jme);
dc4185bd 546 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 547 break;
548 case PHY_LINK_SPEED_1000M:
55d19799 549 jme_set_phyfifo_8level(jme);
7ee473a3
GFT		 550 break;
551 default:
552 break;
553 }
554 }
dc4185bd 555 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 556
3b70a6fa
GFT		 557 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
558 "Full-Duplex, " :
559 "Half-Duplex, ");
560 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
561 "MDI-X" :
562 "MDI");
937ef75a 563 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT		 564 netif_carrier_on(netdev);
565 } else {
566 if (testonly)
fcf45b4c
GFT		 567 goto out;
568
937ef75a 569 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 570 jme->phylink = 0;
cd0ff491 571 netif_carrier_off(netdev);
d7699f87 572 }
fcf45b4c
GFT		 573
574out:
575 return rc;
d7699f87
GFT		 576}
577
3bf61c55
GFT		 578static int
579jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 580{
d7699f87
GFT		 581 struct jme_ring *txring = &(jme->txring[0]);
582
583 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 584 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
585 &(txring->dmaalloc),
586 GFP_ATOMIC);
fcf45b4c 587
0ede469c
GFT		 588 if (!txring->alloc)
589 goto err_set_null;
d7699f87
GFT		 590
591 /*
592 * 16 Bytes align
593 */
cd0ff491 594 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 595 RING_DESC_ALIGN);
4330c2f2 596 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 597 txring->next_to_use = 0;
cdcdc9eb 598 atomic_set(&txring->next_to_clean, 0);
b3821cc5 599 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 600
0ede469c
GFT		 601 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
602 jme->tx_ring_size, GFP_ATOMIC);
603 if (unlikely(!(txring->bufinf)))
604 goto err_free_txring;
605
d7699f87 606 /*
b3821cc5 607 * Initialize Transmit Descriptors
d7699f87 608 */
b3821cc5 609 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 610 memset(txring->bufinf, 0,
b3821cc5 611 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 612
613 return 0;
0ede469c
GFT		 614
615err_free_txring:
616 dma_free_coherent(&(jme->pdev->dev),
617 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
618 txring->alloc,
619 txring->dmaalloc);
620
621err_set_null:
622 txring->desc = NULL;
623 txring->dmaalloc = 0;
624 txring->dma = 0;
625 txring->bufinf = NULL;
626
627 return -ENOMEM;
d7699f87
GFT		 628}
629
3bf61c55
GFT		 630static void
631jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 632{
633 int i;
634 struct jme_ring *txring = &(jme->txring[0]);
0ede469c 635 struct jme_buffer_info *txbi;
d7699f87 636
cd0ff491 637 if (txring->alloc) {
0ede469c
GFT		 638 if (txring->bufinf) {
639 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
640 txbi = txring->bufinf + i;
641 if (txbi->skb) {
642 dev_kfree_skb(txbi->skb);
643 txbi->skb = NULL;
644 }
645 txbi->mapping = 0;
646 txbi->len = 0;
647 txbi->nr_desc = 0;
648 txbi->start_xmit = 0;
d7699f87 649 }
0ede469c 650 kfree(txring->bufinf);
d7699f87
GFT		 651 }
652
653 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 654 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 655 txring->alloc,
656 txring->dmaalloc);
3bf61c55
GFT		 657
658 txring->alloc = NULL;
659 txring->desc = NULL;
660 txring->dmaalloc = 0;
661 txring->dma = 0;
0ede469c 662 txring->bufinf = NULL;
d7699f87 663 }
3bf61c55 664 txring->next_to_use = 0;
cdcdc9eb 665 atomic_set(&txring->next_to_clean, 0);
79ce639c 666 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 667}
668
cd0ff491 669static inline void
3bf61c55 670jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 671{
672 /*
673 * Select Queue 0
674 */
675 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 676 wmb();
d7699f87
GFT		 677
678 /*
679 * Setup TX Queue 0 DMA Bass Address
680 */
fcf45b4c 681 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 682 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 683 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 684
685 /*
686 * Setup TX Descptor Count
687 */
b3821cc5 688 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 689
690 /*
691 * Enable TX Engine
692 */
693 wmb();
dc4185bd 694 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT		 695 TXCS_SELECT_QUEUE0 |
696 TXCS_ENABLE);
d7699f87 697
dc4185bd
GFT		 698 /*
699 * Start clock for TX MAC Processor
700 */
701 jme_mac_txclk_on(jme);
d7699f87
GFT		 702}
703
cd0ff491 704static inline void
29bdd921
GFT		 705jme_restart_tx_engine(struct jme_adapter *jme)
706{
707 /*
708 * Restart TX Engine
709 */
710 jwrite32(jme, JME_TXCS, jme->reg_txcs |
711 TXCS_SELECT_QUEUE0 |
712 TXCS_ENABLE);
713}
714
cd0ff491 715static inline void
3bf61c55 716jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 717{
718 int i;
cd0ff491 719 u32 val;
d7699f87
GFT		 720
721 /*
722 * Disable TX Engine
723 */
fcf45b4c 724 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 725 wmb();
d7699f87
GFT		 726
727 val = jread32(jme, JME_TXCS);
cd0ff491 728 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 729 mdelay(1);
d7699f87 730 val = jread32(jme, JME_TXCS);
cd0ff491 731 rmb();
d7699f87
GFT		 732 }
733
cd0ff491 734 if (!i)
937ef75a 735 pr_err("Disable TX engine timeout\n");
dc4185bd
GFT		 736
737 /*
738 * Stop clock for TX MAC Processor
739 */
740 jme_mac_txclk_off(jme);
d7699f87
GFT		 741}
742
3bf61c55
GFT		 743static void
744jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 745{
0ede469c 746 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 747 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 748 struct jme_buffer_info *rxbi = rxring->bufinf;
749 rxdesc += i;
750 rxbi += i;
751
752 rxdesc->dw[0] = 0;
753 rxdesc->dw[1] = 0;
3bf61c55 754 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 755 rxdesc->desc1.bufaddrl = cpu_to_le32(
756 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 757 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 758 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 759 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 760 wmb();
3bf61c55 761 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 762}
763
3bf61c55
GFT		 764static int
765jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 766{
767 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 768 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 769 struct sk_buff *skb;
4330c2f2 770
79ce639c
GFT		 771 skb = netdev_alloc_skb(jme->dev,
772 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 773 if (unlikely(!skb))
4330c2f2 774 return -ENOMEM;
3b70a6fa
GFT		 775#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
776 skb->dev = jme->dev;
777#endif
3bf61c55 778
4330c2f2 779 rxbi->skb = skb;
3bf61c55 780 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT		 781 rxbi->mapping = pci_map_page(jme->pdev,
782 virt_to_page(skb->data),
783 offset_in_page(skb->data),
784 rxbi->len,
785 PCI_DMA_FROMDEVICE);
4330c2f2
GFT		 786
787 return 0;
788}
789
3bf61c55
GFT		 790static void
791jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 792{
793 struct jme_ring *rxring = &(jme->rxring[0]);
794 struct jme_buffer_info *rxbi = rxring->bufinf;
795 rxbi += i;
796
cd0ff491 797 if (rxbi->skb) {
b3821cc5 798 pci_unmap_page(jme->pdev,
4330c2f2 799 rxbi->mapping,
3bf61c55 800 rxbi->len,
4330c2f2
GFT		 801 PCI_DMA_FROMDEVICE);
802 dev_kfree_skb(rxbi->skb);
803 rxbi->skb = NULL;
804 rxbi->mapping = 0;
3bf61c55 805 rxbi->len = 0;
4330c2f2
GFT		 806 }
807}
808
3bf61c55
GFT		 809static void
810jme_free_rx_resources(struct jme_adapter *jme)
811{
812 int i;
813 struct jme_ring *rxring = &(jme->rxring[0]);
814
cd0ff491 815 if (rxring->alloc) {
0ede469c
GFT		 816 if (rxring->bufinf) {
817 for (i = 0 ; i < jme->rx_ring_size ; ++i)
818 jme_free_rx_buf(jme, i);
819 kfree(rxring->bufinf);
820 }
3bf61c55
GFT		 821
822 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 823 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 824 rxring->alloc,
825 rxring->dmaalloc);
826 rxring->alloc = NULL;
827 rxring->desc = NULL;
828 rxring->dmaalloc = 0;
829 rxring->dma = 0;
0ede469c 830 rxring->bufinf = NULL;
3bf61c55
GFT		 831 }
832 rxring->next_to_use = 0;
cdcdc9eb 833 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 834}
835
836static int
837jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 838{
839 int i;
840 struct jme_ring *rxring = &(jme->rxring[0]);
841
842 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 843 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
844 &(rxring->dmaalloc),
845 GFP_ATOMIC);
0ede469c
GFT		 846 if (!rxring->alloc)
847 goto err_set_null;
d7699f87
GFT		 848
849 /*
850 * 16 Bytes align
851 */
cd0ff491 852 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 853 RING_DESC_ALIGN);
4330c2f2 854 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 855 rxring->next_to_use = 0;
cdcdc9eb 856 atomic_set(&rxring->next_to_clean, 0);
d7699f87 857
0ede469c
GFT		 858 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
859 jme->rx_ring_size, GFP_ATOMIC);
860 if (unlikely(!(rxring->bufinf)))
861 goto err_free_rxring;
862
d7699f87
GFT		 863 /*
864 * Initiallize Receive Descriptors
865 */
0ede469c
GFT		 866 memset(rxring->bufinf, 0,
867 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 868 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
869 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 870 jme_free_rx_resources(jme);
871 return -ENOMEM;
872 }
d7699f87
GFT		 873
874 jme_set_clean_rxdesc(jme, i);
875 }
876
d7699f87 877 return 0;
0ede469c
GFT		 878
879err_free_rxring:
880 dma_free_coherent(&(jme->pdev->dev),
881 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
882 rxring->alloc,
883 rxring->dmaalloc);
884err_set_null:
885 rxring->desc = NULL;
886 rxring->dmaalloc = 0;
887 rxring->dma = 0;
888 rxring->bufinf = NULL;
889
890 return -ENOMEM;
d7699f87
GFT		 891}
892
cd0ff491 893static inline void
3bf61c55 894jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 895{
cd0ff491
GFT		 896 /*
897 * Select Queue 0
898 */
899 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
900 RXCS_QUEUESEL_Q0);
901 wmb();
902
d7699f87
GFT		 903 /*
904 * Setup RX DMA Bass Address
905 */
0ede469c 906 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 907 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
0ede469c 908 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 909
910 /*
b3821cc5 911 * Setup RX Descriptor Count
d7699f87 912 */
b3821cc5 913 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 914
3bf61c55 915 /*
d7699f87
GFT		 916 * Setup Unicast Filter
917 */
e523cd89 918 jme_set_unicastaddr(jme->dev);
d7699f87
GFT		 919 jme_set_multi(jme->dev);
920
921 /*
922 * Enable RX Engine
923 */
924 wmb();
dc4185bd 925 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 926 RXCS_QUEUESEL_Q0 |
927 RXCS_ENABLE |
928 RXCS_QST);
dc4185bd
GFT		 929
930 /*
931 * Start clock for RX MAC Processor
932 */
933 jme_mac_rxclk_on(jme);
d7699f87
GFT		 934}
935
cd0ff491 936static inline void
3bf61c55 937jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 938{
939 /*
3bf61c55 940 * Start RX Engine
4330c2f2 941 */
79ce639c 942 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 943 RXCS_QUEUESEL_Q0 |
944 RXCS_ENABLE |
945 RXCS_QST);
946}
947
cd0ff491 948static inline void
3bf61c55 949jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 950{
951 int i;
cd0ff491 952 u32 val;
d7699f87
GFT		 953
954 /*
955 * Disable RX Engine
956 */
29bdd921 957 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 958 wmb();
d7699f87
GFT		 959
960 val = jread32(jme, JME_RXCS);
cd0ff491 961 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 962 mdelay(1);
d7699f87 963 val = jread32(jme, JME_RXCS);
cd0ff491 964 rmb();
d7699f87
GFT		 965 }
966
cd0ff491 967 if (!i)
937ef75a 968 pr_err("Disable RX engine timeout\n");
d7699f87 969
dc4185bd
GFT		 970 /*
971 * Stop clock for RX MAC Processor
972 */
973 jme_mac_rxclk_off(jme);
d7699f87
GFT		 974}
975
93f698ca
GFT		 976static u16
977jme_udpsum(struct sk_buff *skb)
978{
979 u16 csum = 0xFFFFu;
980
981 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
982 return csum;
983 if (skb->protocol != htons(ETH_P_IP))
984 return csum;
985 skb_set_network_header(skb, ETH_HLEN);
986 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
987 (skb->len < (ETH_HLEN +
988 (ip_hdr(skb)->ihl << 2) +
989 sizeof(struct udphdr)))) {
990 skb_reset_network_header(skb);
991 return csum;
992 }
993 skb_set_transport_header(skb,
994 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
995 csum = udp_hdr(skb)->check;
996 skb_reset_transport_header(skb);
997 skb_reset_network_header(skb);
998
999 return csum;
1000}
1001
192570e0 1002static int
93f698ca 1003jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
192570e0 1004{
cd0ff491 1005 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 1006 return false;
1007
0ede469c
GFT		 1008 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1009 == RXWBFLAG_TCPON)) {
1010 if (flags & RXWBFLAG_IPV4)
7ca9ebee 1011 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
0ede469c 1012 return false;
192570e0
GFT		 1013 }
1014
0ede469c 1015 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
93f698ca 1016 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
0ede469c 1017 if (flags & RXWBFLAG_IPV4)
937ef75a 1018 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
0ede469c 1019 return false;
192570e0
GFT		 1020 }
1021
0ede469c
GFT		 1022 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1023 == RXWBFLAG_IPV4)) {
937ef75a 1024 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
0ede469c 1025 return false;
192570e0
GFT		 1026 }
1027
1028 return true;
1029}
1030
3bf61c55 1031static void
42b1055e 1032jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 1033{
d7699f87 1034 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1035 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 1036 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 1037 struct sk_buff *skb;
3bf61c55 1038 int framesize;
d7699f87 1039
3bf61c55
GFT		 1040 rxdesc += idx;
1041 rxbi += idx;
d7699f87 1042
3bf61c55
GFT		 1043 skb = rxbi->skb;
1044 pci_dma_sync_single_for_cpu(jme->pdev,
1045 rxbi->mapping,
1046 rxbi->len,
1047 PCI_DMA_FROMDEVICE);
1048
cd0ff491 1049 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 1050 pci_dma_sync_single_for_device(jme->pdev,
1051 rxbi->mapping,
1052 rxbi->len,
1053 PCI_DMA_FROMDEVICE);
1054
1055 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1056 } else {
3bf61c55
GFT		 1057 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1058 - RX_PREPAD_SIZE;
1059
1060 skb_reserve(skb, RX_PREPAD_SIZE);
1061 skb_put(skb, framesize);
1062 skb->protocol = eth_type_trans(skb, jme->dev);
1063
93f698ca 1064 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
8c198884 1065 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1066 else
614c0bfd 1067#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
29bdd921 1068 skb->ip_summed = CHECKSUM_NONE;
08f5fcfa
ED		 1069#else
1070 skb_checksum_none_assert(skb);
1071#endif
8c198884 1072
3b70a6fa 1073 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 1074 if (jme->vlgrp) {
cdcdc9eb 1075 jme->jme_vlan_rx(skb, jme->vlgrp,
3b70a6fa 1076 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 1077 NET_STAT(jme).rx_bytes += 4;
7ca9ebee 1078 } else {
7ca9ebee 1079 dev_kfree_skb(skb);
b3821cc5 1080 }
cd0ff491 1081 } else {
cdcdc9eb 1082 jme->jme_rx(skb);
b3821cc5 1083 }
3bf61c55 1084
3b70a6fa
GFT		 1085 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1086 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 1087 ++(NET_STAT(jme).multicast);
1088
3bf61c55
GFT		 1089 NET_STAT(jme).rx_bytes += framesize;
1090 ++(NET_STAT(jme).rx_packets);
1091 }
1092
1093 jme_set_clean_rxdesc(jme, idx);
1094
1095}
1096
1097static int
1098jme_process_receive(struct jme_adapter *jme, int limit)
1099{
1100 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1101 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1102 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1103
cd0ff491 1104 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 1105 goto out_inc;
1106
cd0ff491 1107 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 1108 goto out_inc;
1109
cd0ff491 1110 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 1111 goto out_inc;
1112
cdcdc9eb 1113 i = atomic_read(&rxring->next_to_clean);
0ede469c 1114 while (limit > 0) {
3bf61c55
GFT		 1115 rxdesc = rxring->desc;
1116 rxdesc += i;
1117
3b70a6fa 1118 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 1119 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1120 goto out;
0ede469c 1121 --limit;
d7699f87 1122
9134abda 1123 rmb();
4330c2f2
GFT		 1124 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1125
cd0ff491 1126 if (unlikely(desccnt > 1 ||
192570e0 1127 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1128
cd0ff491 1129 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1130 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1131 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1132 ++(NET_STAT(jme).rx_fifo_errors);
1133 else
1134 ++(NET_STAT(jme).rx_errors);
4330c2f2 1135
cd0ff491 1136 if (desccnt > 1)
3bf61c55 1137 limit -= desccnt - 1;
4330c2f2 1138
cd0ff491 1139 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1140 jme_set_clean_rxdesc(jme, j);
b3821cc5 1141 j = (j + 1) & (mask);
4330c2f2 1142 }
3bf61c55 1143
cd0ff491 1144 } else {
42b1055e 1145 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1146 }
4330c2f2 1147
b3821cc5 1148 i = (i + desccnt) & (mask);
3bf61c55 1149 }
4330c2f2 1150
3bf61c55 1151out:
cdcdc9eb 1152 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1153
192570e0
GFT		 1154out_inc:
1155 atomic_inc(&jme->rx_cleaning);
1156
3bf61c55 1157 return limit > 0 ? limit : 0;
4330c2f2 1158
3bf61c55 1159}
d7699f87 1160
79ce639c
GFT		 1161static void
1162jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1163{
cd0ff491 1164 if (likely(atmp == dpi->cur)) {
192570e0 1165 dpi->cnt = 0;
79ce639c 1166 return;
192570e0 1167 }
79ce639c 1168
cd0ff491 1169 if (dpi->attempt == atmp) {
79ce639c 1170 ++(dpi->cnt);
cd0ff491 1171 } else {
79ce639c
GFT		 1172 dpi->attempt = atmp;
1173 dpi->cnt = 0;
1174 }
1175
1176}
1177
1178static void
1179jme_dynamic_pcc(struct jme_adapter *jme)
1180{
1181 register struct dynpcc_info *dpi = &(jme->dpi);
1182
cd0ff491 1183 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1184 jme_attempt_pcc(dpi, PCC_P3);
7ca9ebee
GFT		 1185 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1186 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT		 1187 jme_attempt_pcc(dpi, PCC_P2);
1188 else
1189 jme_attempt_pcc(dpi, PCC_P1);
1190
cd0ff491
GFT		 1191 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1192 if (dpi->attempt < dpi->cur)
1193 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1194 jme_set_rx_pcc(jme, dpi->attempt);
1195 dpi->cur = dpi->attempt;
1196 dpi->cnt = 0;
1197 }
1198}
1199
1200static void
1201jme_start_pcc_timer(struct jme_adapter *jme)
1202{
1203 struct dynpcc_info *dpi = &(jme->dpi);
1204 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1205 dpi->last_pkts = NET_STAT(jme).rx_packets;
1206 dpi->intr_cnt = 0;
1207 jwrite32(jme, JME_TMCSR,
1208 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1209}
1210
cd0ff491 1211static inline void
29bdd921
GFT		 1212jme_stop_pcc_timer(struct jme_adapter *jme)
1213{
1214 jwrite32(jme, JME_TMCSR, 0);
1215}
1216
cd0ff491
GFT		 1217static void
1218jme_shutdown_nic(struct jme_adapter *jme)
1219{
1220 u32 phylink;
1221
1222 phylink = jme_linkstat_from_phy(jme);
1223
1224 if (!(phylink & PHY_LINK_UP)) {
1225 /*
1226 * Disable all interrupt before issue timer
1227 */
1228 jme_stop_irq(jme);
1229 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1230 }
1231}
1232
79ce639c
GFT		 1233static void
1234jme_pcc_tasklet(unsigned long arg)
1235{
cd0ff491 1236 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1237 struct net_device *netdev = jme->dev;
1238
cd0ff491
GFT		 1239 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1240 jme_shutdown_nic(jme);
1241 return;
1242 }
29bdd921 1243
cd0ff491 1244 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1245 (atomic_read(&jme->link_changing) != 1)
1246 )) {
1247 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1248 return;
1249 }
29bdd921 1250
cd0ff491 1251 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1252 jme_dynamic_pcc(jme);
1253
79ce639c
GFT		 1254 jme_start_pcc_timer(jme);
1255}
1256
cd0ff491 1257static inline void
192570e0
GFT		 1258jme_polling_mode(struct jme_adapter *jme)
1259{
1260 jme_set_rx_pcc(jme, PCC_OFF);
1261}
1262
cd0ff491 1263static inline void
192570e0
GFT		 1264jme_interrupt_mode(struct jme_adapter *jme)
1265{
1266 jme_set_rx_pcc(jme, PCC_P1);
1267}
1268
cd0ff491
GFT		 1269static inline int
1270jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1271{
1272 u32 apmc;
1273 apmc = jread32(jme, JME_APMC);
1274 return apmc & JME_APMC_PSEUDO_HP_EN;
1275}
1276
1277static void
1278jme_start_shutdown_timer(struct jme_adapter *jme)
1279{
1280 u32 apmc;
1281
1282 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1283 apmc &= ~JME_APMC_EPIEN_CTRL;
1284 if (!no_extplug) {
1285 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1286 wmb();
1287 }
1288 jwrite32f(jme, JME_APMC, apmc);
1289
1290 jwrite32f(jme, JME_TIMER2, 0);
1291 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1292 jwrite32(jme, JME_TMCSR,
1293 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1294}
1295
1296static void
1297jme_stop_shutdown_timer(struct jme_adapter *jme)
1298{
1299 u32 apmc;
1300
1301 jwrite32f(jme, JME_TMCSR, 0);
1302 jwrite32f(jme, JME_TIMER2, 0);
1303 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1304
1305 apmc = jread32(jme, JME_APMC);
1306 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1307 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1308 wmb();
1309 jwrite32f(jme, JME_APMC, apmc);
1310}
1311
3bf61c55
GFT		 1312static void
1313jme_link_change_tasklet(unsigned long arg)
1314{
cd0ff491 1315 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1316 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1317 int rc;
1318
cd0ff491
GFT		 1319 while (!atomic_dec_and_test(&jme->link_changing)) {
1320 atomic_inc(&jme->link_changing);
937ef75a 1321 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
58c92f28 1322 while (atomic_read(&jme->link_changing) != 1)
937ef75a 1323 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1324 }
fcf45b4c 1325
cd0ff491 1326 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1327 goto out;
1328
29bdd921 1329 jme->old_mtu = netdev->mtu;
fcf45b4c 1330 netif_stop_queue(netdev);
cd0ff491
GFT		 1331 if (jme_pseudo_hotplug_enabled(jme))
1332 jme_stop_shutdown_timer(jme);
1333
1334 jme_stop_pcc_timer(jme);
1335 tasklet_disable(&jme->txclean_task);
1336 tasklet_disable(&jme->rxclean_task);
1337 tasklet_disable(&jme->rxempty_task);
1338
1339 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT		 1340 jme_disable_rx_engine(jme);
1341 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1342 jme_reset_mac_processor(jme);
1343 jme_free_rx_resources(jme);
1344 jme_free_tx_resources(jme);
192570e0 1345
cd0ff491 1346 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1347 jme_polling_mode(jme);
cd0ff491
GFT		 1348
1349 netif_carrier_off(netdev);
fcf45b4c
GFT		 1350 }
1351
1352 jme_check_link(netdev, 0);
cd0ff491 1353 if (netif_carrier_ok(netdev)) {
fcf45b4c 1354 rc = jme_setup_rx_resources(jme);
cd0ff491 1355 if (rc) {
937ef75a 1356 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1357 goto out_enable_tasklet;
fcf45b4c
GFT		 1358 }
1359
fcf45b4c 1360 rc = jme_setup_tx_resources(jme);
cd0ff491 1361 if (rc) {
937ef75a 1362 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT		 1363 goto err_out_free_rx_resources;
1364 }
1365
1366 jme_enable_rx_engine(jme);
1367 jme_enable_tx_engine(jme);
1368
1369 netif_start_queue(netdev);
192570e0 1370
cd0ff491 1371 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1372 jme_interrupt_mode(jme);
192570e0 1373
79ce639c 1374 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1375 } else if (jme_pseudo_hotplug_enabled(jme)) {
1376 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1377 }
1378
cd0ff491 1379 goto out_enable_tasklet;
fcf45b4c
GFT		 1380
1381err_out_free_rx_resources:
1382 jme_free_rx_resources(jme);
cd0ff491
GFT		 1383out_enable_tasklet:
1384 tasklet_enable(&jme->txclean_task);
1385 tasklet_hi_enable(&jme->rxclean_task);
1386 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1387out:
1388 atomic_inc(&jme->link_changing);
3bf61c55 1389}
d7699f87 1390
3bf61c55
GFT		 1391static void
1392jme_rx_clean_tasklet(unsigned long arg)
1393{
cd0ff491 1394 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1395 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1396
192570e0
GFT		 1397 jme_process_receive(jme, jme->rx_ring_size);
1398 ++(dpi->intr_cnt);
42b1055e 1399
192570e0 1400}
fcf45b4c 1401
192570e0 1402static int
cdcdc9eb 1403jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1404{
cdcdc9eb 1405 struct jme_adapter *jme = jme_napi_priv(holder);
3b70a6fa 1406 DECLARE_NETDEV
192570e0 1407 int rest;
fcf45b4c 1408
cdcdc9eb 1409 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1410
cd0ff491 1411 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1412 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1413 ++(NET_STAT(jme).rx_dropped);
1414 jme_restart_rx_engine(jme);
1415 }
1416 atomic_inc(&jme->rx_empty);
1417
cd0ff491 1418 if (rest) {
cdcdc9eb 1419 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1420 jme_interrupt_mode(jme);
1421 }
1422
cdcdc9eb
GFT		 1423 JME_NAPI_WEIGHT_SET(budget, rest);
1424 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1425}
1426
1427static void
1428jme_rx_empty_tasklet(unsigned long arg)
1429{
cd0ff491 1430 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1431
cd0ff491 1432 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1433 return;
1434
cd0ff491 1435 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1436 return;
1437
7ca9ebee 1438 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1439
fcf45b4c 1440 jme_rx_clean_tasklet(arg);
cdcdc9eb 1441
cd0ff491 1442 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1443 atomic_dec(&jme->rx_empty);
1444 ++(NET_STAT(jme).rx_dropped);
1445 jme_restart_rx_engine(jme);
1446 }
1447 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1448}
1449
b3821cc5
GFT		 1450static void
1451jme_wake_queue_if_stopped(struct jme_adapter *jme)
1452{
0ede469c 1453 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1454
1455 smp_wmb();
cd0ff491 1456 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1457 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
937ef75a 1458 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1459 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1460 }
1461
1462}
1463
3bf61c55
GFT		 1464static void
1465jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1466{
cd0ff491 1467 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1468 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1469 struct txdesc *txdesc = txring->desc;
3bf61c55 1470 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1471 int i, j, cnt = 0, max, err, mask;
3bf61c55 1472
937ef75a 1473 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT		 1474
1475 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1476 goto out;
1477
cd0ff491 1478 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1479 goto out;
1480
cd0ff491 1481 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1482 goto out;
1483
b3821cc5
GFT		 1484 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1485 mask = jme->tx_ring_mask;
3bf61c55 1486
cd0ff491 1487 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1488
1489 ctxbi = txbi + i;
1490
cd0ff491 1491 if (likely(ctxbi->skb &&
b3821cc5 1492 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1493
cd0ff491 1494 tx_dbg(jme, "txclean: %d+%d@%lu\n",
937ef75a 1495 i, ctxbi->nr_desc, jiffies);
3bf61c55 1496
cd0ff491 1497 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1498
cd0ff491 1499 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1500 ttxbi = txbi + ((i + j) & (mask));
1501 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1502
b3821cc5 1503 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1504 ttxbi->mapping,
1505 ttxbi->len,
1506 PCI_DMA_TODEVICE);
1507
3bf61c55
GFT		 1508 ttxbi->mapping = 0;
1509 ttxbi->len = 0;
1510 }
1511
1512 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1513
1514 cnt += ctxbi->nr_desc;
1515
cd0ff491 1516 if (unlikely(err)) {
8c198884 1517 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1518 } else {
8c198884 1519 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1520 NET_STAT(jme).tx_bytes += ctxbi->len;
1521 }
1522
1523 ctxbi->skb = NULL;
1524 ctxbi->len = 0;
cdcdc9eb 1525 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1526
1527 } else {
3bf61c55
GFT		 1528 break;
1529 }
1530
b3821cc5 1531 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1532
1533 ctxbi->nr_desc = 0;
d7699f87
GFT		 1534 }
1535
937ef75a 1536 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1537 atomic_set(&txring->next_to_clean, i);
79ce639c 1538 atomic_add(cnt, &txring->nr_free);
3bf61c55 1539
b3821cc5
GFT		 1540 jme_wake_queue_if_stopped(jme);
1541
fcf45b4c
GFT		 1542out:
1543 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1544}
1545
79ce639c 1546static void
cd0ff491 1547jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1548{
3bf61c55
GFT		 1549 /*
1550 * Disable interrupt
1551 */
1552 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1553
cd0ff491 1554 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1555 /*
1556 * Link change event is critical
1557 * all other events are ignored
1558 */
1559 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1560 tasklet_schedule(&jme->linkch_task);
29bdd921 1561 goto out_reenable;
fcf45b4c 1562 }
d7699f87 1563
cd0ff491 1564 if (intrstat & INTR_TMINTR) {
47220951 1565 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1566 tasklet_schedule(&jme->pcc_task);
47220951 1567 }
79ce639c 1568
cd0ff491 1569 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1570 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1571 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1572 }
1573
cd0ff491 1574 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1575 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1576 INTR_PCCRX0 |
1577 INTR_RX0EMP)) |
1578 INTR_RX0);
1579 }
d7699f87 1580
cd0ff491
GFT		 1581 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1582 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1583 atomic_inc(&jme->rx_empty);
1584
cd0ff491
GFT		 1585 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1586 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1587 jme_polling_mode(jme);
cdcdc9eb 1588 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1589 }
1590 }
cd0ff491
GFT		 1591 } else {
1592 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1593 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1594 tasklet_hi_schedule(&jme->rxempty_task);
1595 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1596 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1597 }
4330c2f2 1598 }
d7699f87 1599
29bdd921 1600out_reenable:
3bf61c55 1601 /*
fcf45b4c 1602 * Re-enable interrupt
3bf61c55 1603 */
fcf45b4c 1604 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1605}
1606
3b70a6fa
GFT		 1607#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1608static irqreturn_t
1609jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1610#else
79ce639c
GFT		 1611static irqreturn_t
1612jme_intr(int irq, void *dev_id)
3b70a6fa 1613#endif
79ce639c 1614{
cd0ff491
GFT		 1615 struct net_device *netdev = dev_id;
1616 struct jme_adapter *jme = netdev_priv(netdev);
1617 u32 intrstat;
79ce639c
GFT		 1618
1619 intrstat = jread32(jme, JME_IEVE);
1620
1621 /*
1622 * Check if it's really an interrupt for us
1623 */
7ee473a3 1624 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1625 return IRQ_NONE;
79ce639c
GFT		 1626
1627 /*
1628 * Check if the device still exist
1629 */
cd0ff491
GFT		 1630 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1631 return IRQ_NONE;
79ce639c
GFT		 1632
1633 jme_intr_msi(jme, intrstat);
1634
cd0ff491 1635 return IRQ_HANDLED;
d7699f87
GFT		 1636}
1637
3b70a6fa
GFT		 1638#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1639static irqreturn_t
1640jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1641#else
79ce639c
GFT		 1642static irqreturn_t
1643jme_msi(int irq, void *dev_id)
3b70a6fa 1644#endif
79ce639c 1645{
cd0ff491
GFT		 1646 struct net_device *netdev = dev_id;
1647 struct jme_adapter *jme = netdev_priv(netdev);
1648 u32 intrstat;
79ce639c 1649
0ede469c 1650 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1651
1652 jme_intr_msi(jme, intrstat);
1653
cd0ff491 1654 return IRQ_HANDLED;
79ce639c
GFT		 1655}
1656
79ce639c
GFT		 1657static void
1658jme_reset_link(struct jme_adapter *jme)
1659{
1660 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1661}
1662
fcf45b4c
GFT		 1663static void
1664jme_restart_an(struct jme_adapter *jme)
1665{
cd0ff491 1666 u32 bmcr;
fcf45b4c 1667
cd0ff491 1668 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1669 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1670 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1671 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1672 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1673}
1674
1675static int
1676jme_request_irq(struct jme_adapter *jme)
1677{
1678 int rc;
cd0ff491 1679 struct net_device *netdev = jme->dev;
3b70a6fa
GFT		 1680#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1681 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1682 int irq_flags = SA_SHIRQ;
1683#else
cd0ff491
GFT		 1684 irq_handler_t handler = jme_intr;
1685 int irq_flags = IRQF_SHARED;
3b70a6fa 1686#endif
cd0ff491
GFT		 1687
1688 if (!pci_enable_msi(jme->pdev)) {
1689 set_bit(JME_FLAG_MSI, &jme->flags);
1690 handler = jme_msi;
1691 irq_flags = 0;
1692 }
1693
1694 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1695 netdev);
1696 if (rc) {
937ef75a
JP		 1697 netdev_err(netdev,
1698 "Unable to request %s interrupt (return: %d)\n",
1699 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1700 rc);
79ce639c 1701
cd0ff491
GFT		 1702 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1703 pci_disable_msi(jme->pdev);
1704 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1705 }
cd0ff491 1706 } else {
79ce639c
GFT		 1707 netdev->irq = jme->pdev->irq;
1708 }
1709
cd0ff491 1710 return rc;
79ce639c
GFT		 1711}
1712
1713static void
1714jme_free_irq(struct jme_adapter *jme)
1715{
cd0ff491
GFT		 1716 free_irq(jme->pdev->irq, jme->dev);
1717 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1718 pci_disable_msi(jme->pdev);
1719 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1720 jme->dev->irq = jme->pdev->irq;
cd0ff491 1721 }
fcf45b4c
GFT		 1722}
1723
ed457bcc
GFT		 1724static inline void
1725jme_new_phy_on(struct jme_adapter *jme)
1726{
1727 u32 reg;
1728
1729 reg = jread32(jme, JME_PHY_PWR);
1730 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1731 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1732 jwrite32(jme, JME_PHY_PWR, reg);
1733
1734 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1735 reg &= ~PE1_GPREG0_PBG;
1736 reg |= PE1_GPREG0_ENBG;
1737 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1738}
1739
1740static inline void
1741jme_new_phy_off(struct jme_adapter *jme)
1742{
1743 u32 reg;
1744
1745 reg = jread32(jme, JME_PHY_PWR);
1746 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1747 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1748 jwrite32(jme, JME_PHY_PWR, reg);
1749
1750 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1751 reg &= ~PE1_GPREG0_PBG;
1752 reg |= PE1_GPREG0_PDD3COLD;
1753 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1754}
1755
e58b908e
GFT		 1756static inline void
1757jme_phy_on(struct jme_adapter *jme)
1758{
1759 u32 bmcr;
1760
1761 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1762 bmcr &= ~BMCR_PDOWN;
1763 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
ed457bcc
GFT		 1764
1765 if (new_phy_power_ctrl(jme->chip_main_rev))
1766 jme_new_phy_on(jme);
1767}
1768
1769static inline void
1770jme_phy_off(struct jme_adapter *jme)
1771{
1772 u32 bmcr;
1773
1774 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1775 bmcr |= BMCR_PDOWN;
1776 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1777
1778 if (new_phy_power_ctrl(jme->chip_main_rev))
1779 jme_new_phy_off(jme);
e58b908e
GFT		 1780}
1781
3bf61c55
GFT		 1782static int
1783jme_open(struct net_device *netdev)
d7699f87
GFT		 1784{
1785 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1786 int rc;
79ce639c 1787
42b1055e 1788 jme_clear_pm(jme);
cdcdc9eb 1789 JME_NAPI_ENABLE(jme);
d7699f87 1790
0ede469c 1791 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1792 tasklet_enable(&jme->txclean_task);
1793 tasklet_hi_enable(&jme->rxclean_task);
1794 tasklet_hi_enable(&jme->rxempty_task);
1795
79ce639c 1796 rc = jme_request_irq(jme);
cd0ff491 1797 if (rc)
4330c2f2 1798 goto err_out;
79ce639c 1799
d7699f87 1800 jme_start_irq(jme);
42b1055e 1801
ed457bcc
GFT		 1802 jme_phy_on(jme);
1803 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1804 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 1805 else
42b1055e
GFT		 1806 jme_reset_phy_processor(jme);
1807
29bdd921 1808 jme_reset_link(jme);
d7699f87
GFT		 1809
1810 return 0;
1811
d7699f87
GFT		 1812err_out:
1813 netif_stop_queue(netdev);
1814 netif_carrier_off(netdev);
4330c2f2 1815 return rc;
d7699f87
GFT		 1816}
1817
42b1055e
GFT		 1818static void
1819jme_set_100m_half(struct jme_adapter *jme)
1820{
cd0ff491 1821 u32 bmcr, tmp;
42b1055e 1822
a82e368c 1823 jme_phy_on(jme);
42b1055e
GFT		 1824 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1825 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1826 BMCR_SPEED1000 | BMCR_FULLDPLX);
1827 tmp |= BMCR_SPEED100;
1828
1829 if (bmcr != tmp)
1830 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1831
cd0ff491 1832 if (jme->fpgaver)
cdcdc9eb
GFT		 1833 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1834 else
1835 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1836}
1837
47220951
GFT		 1838#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1839static void
1840jme_wait_link(struct jme_adapter *jme)
1841{
cd0ff491 1842 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1843
1844 mdelay(1000);
1845 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1846 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1847 mdelay(10);
1848 phylink = jme_linkstat_from_phy(jme);
1849 }
1850}
1851
a82e368c
GFT		 1852static void
1853jme_powersave_phy(struct jme_adapter *jme)
1854{
1855 if (jme->reg_pmcs) {
1856 jme_set_100m_half(jme);
1857
1858 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1859 jme_wait_link(jme);
1860
1861 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1862 } else {
1863 jme_phy_off(jme);
1864 }
1865}
1866
3bf61c55
GFT		 1867static int
1868jme_close(struct net_device *netdev)
d7699f87
GFT		 1869{
1870 struct jme_adapter *jme = netdev_priv(netdev);
1871
1872 netif_stop_queue(netdev);
1873 netif_carrier_off(netdev);
1874
1875 jme_stop_irq(jme);
79ce639c 1876 jme_free_irq(jme);
d7699f87 1877
cdcdc9eb 1878 JME_NAPI_DISABLE(jme);
192570e0 1879
0ede469c
GFT		 1880 tasklet_disable(&jme->linkch_task);
1881 tasklet_disable(&jme->txclean_task);
1882 tasklet_disable(&jme->rxclean_task);
1883 tasklet_disable(&jme->rxempty_task);
8c198884 1884
cd0ff491
GFT		 1885 jme_disable_rx_engine(jme);
1886 jme_disable_tx_engine(jme);
8c198884 1887 jme_reset_mac_processor(jme);
d7699f87
GFT		 1888 jme_free_rx_resources(jme);
1889 jme_free_tx_resources(jme);
42b1055e 1890 jme->phylink = 0;
b3821cc5
GFT		 1891 jme_phy_off(jme);
1892
1893 return 0;
1894}
1895
1896static int
1897jme_alloc_txdesc(struct jme_adapter *jme,
1898 struct sk_buff *skb)
1899{
0ede469c 1900 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1901 int idx, nr_alloc, mask = jme->tx_ring_mask;
1902
1903 idx = txring->next_to_use;
1904 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1905
cd0ff491 1906 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 1907 return -1;
1908
1909 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1910
b3821cc5
GFT		 1911 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1912
1913 return idx;
1914}
1915
1916static void
1917jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1918 struct txdesc *txdesc,
b3821cc5
GFT		 1919 struct jme_buffer_info *txbi,
1920 struct page *page,
cd0ff491
GFT		 1921 u32 page_offset,
1922 u32 len,
1923 u8 hidma)
b3821cc5
GFT		 1924{
1925 dma_addr_t dmaaddr;
1926
1927 dmaaddr = pci_map_page(pdev,
1928 page,
1929 page_offset,
1930 len,
1931 PCI_DMA_TODEVICE);
1932
1933 pci_dma_sync_single_for_device(pdev,
1934 dmaaddr,
1935 len,
1936 PCI_DMA_TODEVICE);
1937
1938 txdesc->dw[0] = 0;
1939 txdesc->dw[1] = 0;
1940 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1941 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 1942 txdesc->desc2.datalen = cpu_to_le16(len);
1943 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1944 txdesc->desc2.bufaddrl = cpu_to_le32(
1945 (__u64)dmaaddr & 0xFFFFFFFFUL);
1946
1947 txbi->mapping = dmaaddr;
1948 txbi->len = len;
1949}
1950
1951static void
1952jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1953{
0ede469c 1954 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1955 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1956 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1957 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT		 1958 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1959 int mask = jme->tx_ring_mask;
1960 struct skb_frag_struct *frag;
cd0ff491 1961 u32 len;
b3821cc5 1962
cd0ff491
GFT		 1963 for (i = 0 ; i < nr_frags ; ++i) {
1964 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 1965 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1966 ctxbi = txbi + ((idx + i + 2) & (mask));
1967
1968 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1969 frag->page_offset, frag->size, hidma);
42b1055e 1970 }
b3821cc5 1971
cd0ff491 1972 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 1973 ctxdesc = txdesc + ((idx + 1) & (mask));
1974 ctxbi = txbi + ((idx + 1) & (mask));
1975 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1976 offset_in_page(skb->data), len, hidma);
1977
1978}
1979
1980static int
1981jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1982{
3b70a6fa 1983 if (unlikely(
0ede469c 1984#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 1985 skb_shinfo(skb)->tso_size
1986#else
1987 skb_shinfo(skb)->gso_size
1988#endif
1989 && skb_header_cloned(skb) &&
b3821cc5
GFT		 1990 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1991 dev_kfree_skb(skb);
1992 return -1;
1993 }
1994
1995 return 0;
1996}
1997
1998static int
3b70a6fa 1999jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 2000{
0ede469c 2001#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 2002 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2003#else
2004 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2005#endif
cd0ff491 2006 if (*mss) {
b3821cc5
GFT		 2007 *flags |= TXFLAG_LSEN;
2008
cd0ff491 2009 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 2010 struct iphdr *iph = ip_hdr(skb);
2011
2012 iph->check = 0;
cd0ff491 2013 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 2014 iph->daddr, 0,
2015 IPPROTO_TCP,
2016 0);
cd0ff491 2017 } else {
b3821cc5
GFT		 2018 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2019
cd0ff491 2020 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 2021 &ip6h->daddr, 0,
2022 IPPROTO_TCP,
2023 0);
2024 }
2025
2026 return 0;
2027 }
2028
2029 return 1;
2030}
2031
2032static void
cd0ff491 2033jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 2034{
3b70a6fa
GFT		 2035#ifdef CHECKSUM_PARTIAL
2036 if (skb->ip_summed == CHECKSUM_PARTIAL)
2037#else
2038 if (skb->ip_summed == CHECKSUM_HW)
2039#endif
2040 {
cd0ff491 2041 u8 ip_proto;
b3821cc5 2042
3b70a6fa
GFT		 2043#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2044 if (skb->protocol == htons(ETH_P_IP))
2045 ip_proto = ip_hdr(skb)->protocol;
2046 else if (skb->protocol == htons(ETH_P_IPV6))
2047 ip_proto = ipv6_hdr(skb)->nexthdr;
2048 else
2049 ip_proto = 0;
2050#else
b3821cc5 2051 switch (skb->protocol) {
cd0ff491 2052 case htons(ETH_P_IP):
b3821cc5
GFT		 2053 ip_proto = ip_hdr(skb)->protocol;
2054 break;
cd0ff491 2055 case htons(ETH_P_IPV6):
b3821cc5
GFT		 2056 ip_proto = ipv6_hdr(skb)->nexthdr;
2057 break;
2058 default:
2059 ip_proto = 0;
2060 break;
2061 }
3b70a6fa 2062#endif
b3821cc5 2063
cd0ff491 2064 switch (ip_proto) {
b3821cc5
GFT		 2065 case IPPROTO_TCP:
2066 *flags |= TXFLAG_TCPCS;
2067 break;
2068 case IPPROTO_UDP:
2069 *flags |= TXFLAG_UDPCS;
2070 break;
2071 default:
937ef75a 2072 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT		 2073 break;
2074 }
2075 }
2076}
2077
cd0ff491 2078static inline void
3b70a6fa 2079jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2080{
cd0ff491 2081 if (vlan_tx_tag_present(skb)) {
b3821cc5 2082 *flags |= TXFLAG_TAGON;
3b70a6fa 2083 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2084 }
b3821cc5
GFT		 2085}
2086
2087static int
3b70a6fa 2088jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2089{
0ede469c 2090 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2091 struct txdesc *txdesc;
b3821cc5 2092 struct jme_buffer_info *txbi;
cd0ff491 2093 u8 flags;
b3821cc5 2094
cd0ff491 2095 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 2096 txbi = txring->bufinf + idx;
2097
2098 txdesc->dw[0] = 0;
2099 txdesc->dw[1] = 0;
2100 txdesc->dw[2] = 0;
2101 txdesc->dw[3] = 0;
2102 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2103 /*
2104 * Set OWN bit at final.
2105 * When kernel transmit faster than NIC.
2106 * And NIC trying to send this descriptor before we tell
2107 * it to start sending this TX queue.
2108 * Other fields are already filled correctly.
2109 */
2110 wmb();
2111 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 2112 /*
2113 * Set checksum flags while not tso
2114 */
2115 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2116 jme_tx_csum(jme, skb, &flags);
b3821cc5 2117 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
3b70a6fa 2118 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 2119 txdesc->desc1.flags = flags;
2120 /*
2121 * Set tx buffer info after telling NIC to send
2122 * For better tx_clean timing
2123 */
2124 wmb();
2125 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2126 txbi->skb = skb;
2127 txbi->len = skb->len;
cd0ff491
GFT		 2128 txbi->start_xmit = jiffies;
2129 if (!txbi->start_xmit)
8d27293f 2130 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 2131
2132 return 0;
2133}
2134
b3821cc5
GFT		 2135static void
2136jme_stop_queue_if_full(struct jme_adapter *jme)
2137{
0ede469c 2138 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 2139 struct jme_buffer_info *txbi = txring->bufinf;
2140 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2141
cd0ff491 2142 txbi += idx;
b3821cc5
GFT		 2143
2144 smp_wmb();
cd0ff491 2145 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2146 netif_stop_queue(jme->dev);
937ef75a 2147 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2148 smp_wmb();
cd0ff491
GFT		 2149 if (atomic_read(&txring->nr_free)
2150 >= (jme->tx_wake_threshold)) {
b3821cc5 2151 netif_wake_queue(jme->dev);
937ef75a 2152 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT		 2153 }
2154 }
2155
cd0ff491 2156 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 2157 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2158 txbi->skb)) {
2159 netif_stop_queue(jme->dev);
937ef75a 2160 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2161 }
b3821cc5
GFT		 2162}
2163
3bf61c55
GFT		 2164/*
2165 * This function is already protected by netif_tx_lock()
2166 */
cd0ff491 2167
7ca9ebee 2168#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
3bf61c55 2169static int
7ca9ebee
GFT		 2170#else
2171static netdev_tx_t
2172#endif
3bf61c55 2173jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2174{
cd0ff491 2175 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2176 int idx;
d7699f87 2177
cd0ff491 2178 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 2179 ++(NET_STAT(jme).tx_dropped);
2180 return NETDEV_TX_OK;
2181 }
2182
2183 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2184
cd0ff491 2185 if (unlikely(idx < 0)) {
b3821cc5 2186 netif_stop_queue(netdev);
937ef75a
JP		 2187 netif_err(jme, tx_err, jme->dev,
2188 "BUG! Tx ring full when queue awake!\n");
d7699f87 2189
cd0ff491 2190 return NETDEV_TX_BUSY;
b3821cc5
GFT		 2191 }
2192
3b70a6fa 2193 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2194
4330c2f2
GFT		 2195 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2196 TXCS_SELECT_QUEUE0 |
2197 TXCS_QUEUE0S |
2198 TXCS_ENABLE);
0ede469c 2199#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
d7699f87 2200 netdev->trans_start = jiffies;
0ede469c 2201#endif
d7699f87 2202
937ef75a
JP		 2203 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2204 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT		 2205 jme_stop_queue_if_full(jme);
2206
cd0ff491 2207 return NETDEV_TX_OK;
d7699f87
GFT		 2208}
2209
e523cd89
GFT		 2210static void
2211jme_set_unicastaddr(struct net_device *netdev)
2212{
2213 struct jme_adapter *jme = netdev_priv(netdev);
2214 u32 val;
2215
2216 val = (netdev->dev_addr[3] & 0xff) << 24 |
2217 (netdev->dev_addr[2] & 0xff) << 16 |
2218 (netdev->dev_addr[1] & 0xff) << 8 |
2219 (netdev->dev_addr[0] & 0xff);
2220 jwrite32(jme, JME_RXUMA_LO, val);
2221 val = (netdev->dev_addr[5] & 0xff) << 8 |
2222 (netdev->dev_addr[4] & 0xff);
2223 jwrite32(jme, JME_RXUMA_HI, val);
2224}
2225
3bf61c55
GFT		 2226static int
2227jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2228{
cd0ff491 2229 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2230 struct sockaddr *addr = p;
d7699f87 2231
cd0ff491 2232 if (netif_running(netdev))
d7699f87
GFT		 2233 return -EBUSY;
2234
cd0ff491 2235 spin_lock_bh(&jme->macaddr_lock);
d7699f87 2236 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
e523cd89 2237 jme_set_unicastaddr(netdev);
cd0ff491 2238 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 2239
2240 return 0;
2241}
2242
3bf61c55
GFT		 2243static void
2244jme_set_multi(struct net_device *netdev)
d7699f87 2245{
3bf61c55 2246 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2247 u32 mc_hash[2] = {};
7ca9ebee 2248#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
d7699f87 2249 int i;
7ca9ebee 2250#endif
d7699f87 2251
cd0ff491 2252 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2253
2254 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2255
cd0ff491 2256 if (netdev->flags & IFF_PROMISC) {
8c198884 2257 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2258 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2259 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2260 } else if (netdev->flags & IFF_MULTICAST) {
8e14c278 2261#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
3bf61c55 2262 struct dev_mc_list *mclist;
8e14c278
JP		 2263#else
2264 struct netdev_hw_addr *ha;
2265#endif
3bf61c55 2266 int bit_nr;
d7699f87 2267
8c198884 2268 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
7ca9ebee 2269#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
3bf61c55
GFT		 2270 for (i = 0, mclist = netdev->mc_list;
2271 mclist && i < netdev->mc_count;
2272 ++i, mclist = mclist->next) {
8e14c278 2273#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
7ca9ebee 2274 netdev_for_each_mc_addr(mclist, netdev) {
8e14c278
JP		 2275#else
2276 netdev_for_each_mc_addr(ha, netdev) {
7ca9ebee 2277#endif
8e14c278 2278#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
cd0ff491 2279 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
8e14c278
JP		 2280#else
2281 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2282#endif
cd0ff491
GFT		 2283 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2284 }
d7699f87 2285
4330c2f2
GFT		 2286 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2287 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2288 }
2289
d7699f87 2290 wmb();
8c198884
GFT		 2291 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2292
cd0ff491 2293 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2294}
2295
3bf61c55 2296static int
8c198884 2297jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2298{
cd0ff491 2299 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2300
cd0ff491 2301 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2302 return 0;
2303
cd0ff491
GFT		 2304 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2305 ((new_mtu) < IPV6_MIN_MTU))
2306 return -EINVAL;
79ce639c 2307
cd0ff491 2308 if (new_mtu > 4000) {
79ce639c
GFT		 2309 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2310 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2311 jme_restart_rx_engine(jme);
cd0ff491 2312 } else {
79ce639c
GFT		 2313 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2314 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2315 jme_restart_rx_engine(jme);
2316 }
2317
cd0ff491 2318 if (new_mtu > 1900) {
1a0b42f4
MM		 2319 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2320 NETIF_F_TSO | NETIF_F_TSO6);
cd0ff491
GFT		 2321 } else {
2322 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
1a0b42f4 2323 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491 2324 if (test_bit(JME_FLAG_TSO, &jme->flags))
1a0b42f4 2325 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT		 2326 }
2327
cd0ff491
GFT		 2328 netdev->mtu = new_mtu;
2329 jme_reset_link(jme);
79ce639c
GFT		 2330
2331 return 0;
d7699f87
GFT		 2332}
2333
8c198884
GFT		 2334static void
2335jme_tx_timeout(struct net_device *netdev)
2336{
cd0ff491 2337 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2338
cdcdc9eb
GFT		 2339 jme->phylink = 0;
2340 jme_reset_phy_processor(jme);
cd0ff491 2341 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2342 jme_set_settings(netdev, &jme->old_ecmd);
2343
8c198884 2344 /*
cdcdc9eb 2345 * Force to Reset the link again
8c198884 2346 */
29bdd921 2347 jme_reset_link(jme);
8c198884
GFT		 2348}
2349
1e5ebebc
GFT		 2350static inline void jme_pause_rx(struct jme_adapter *jme)
2351{
2352 atomic_dec(&jme->link_changing);
2353
2354 jme_set_rx_pcc(jme, PCC_OFF);
2355 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2356 JME_NAPI_DISABLE(jme);
2357 } else {
2358 tasklet_disable(&jme->rxclean_task);
2359 tasklet_disable(&jme->rxempty_task);
2360 }
2361}
2362
2363static inline void jme_resume_rx(struct jme_adapter *jme)
2364{
2365 struct dynpcc_info *dpi = &(jme->dpi);
2366
2367 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2368 JME_NAPI_ENABLE(jme);
2369 } else {
2370 tasklet_hi_enable(&jme->rxclean_task);
2371 tasklet_hi_enable(&jme->rxempty_task);
2372 }
2373 dpi->cur = PCC_P1;
2374 dpi->attempt = PCC_P1;
2375 dpi->cnt = 0;
2376 jme_set_rx_pcc(jme, PCC_P1);
2377
2378 atomic_inc(&jme->link_changing);
2379}
2380
42b1055e
GFT		 2381static void
2382jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2383{
2384 struct jme_adapter *jme = netdev_priv(netdev);
2385
1e5ebebc 2386 jme_pause_rx(jme);
42b1055e 2387 jme->vlgrp = grp;
1e5ebebc 2388 jme_resume_rx(jme);
42b1055e
GFT		 2389}
2390
7ca9ebee
GFT		 2391#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2392static void
2393jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2394{
2395 struct jme_adapter *jme = netdev_priv(netdev);
2396
7ca9ebee 2397 if(jme->vlgrp) {
1e5ebebc 2398 jme_pause_rx(jme);
7ca9ebee
GFT		 2399#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2400 jme->vlgrp->vlan_devices[vid] = NULL;
2401#else
2402 vlan_group_set_device(jme->vlgrp, vid, NULL);
2403#endif
1e5ebebc 2404 jme_resume_rx(jme);
7ca9ebee 2405 }
7ca9ebee
GFT		 2406}
2407#endif
2408
3bf61c55
GFT		 2409static void
2410jme_get_drvinfo(struct net_device *netdev,
2411 struct ethtool_drvinfo *info)
d7699f87 2412{
cd0ff491 2413 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2414
cd0ff491
GFT		 2415 strcpy(info->driver, DRV_NAME);
2416 strcpy(info->version, DRV_VERSION);
2417 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT		 2418}
2419
8c198884
GFT		 2420static int
2421jme_get_regs_len(struct net_device *netdev)
2422{
cd0ff491 2423 return JME_REG_LEN;
8c198884
GFT		 2424}
2425
2426static void
cd0ff491 2427mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2428{
2429 int i;
2430
cd0ff491 2431 for (i = 0 ; i < len ; i += 4)
79ce639c 2432 p[i >> 2] = jread32(jme, reg + i);
186fc259 2433}
8c198884 2434
186fc259 2435static void
cd0ff491 2436mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2437{
2438 int i;
cd0ff491 2439 u16 *p16 = (u16 *)p;
186fc259 2440
cd0ff491 2441 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2442 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2443}
2444
2445static void
2446jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2447{
cd0ff491
GFT		 2448 struct jme_adapter *jme = netdev_priv(netdev);
2449 u32 *p32 = (u32 *)p;
8c198884 2450
186fc259 2451 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2452
2453 regs->version = 1;
2454 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2455
2456 p32 += 0x100 >> 2;
2457 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2458
2459 p32 += 0x100 >> 2;
2460 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2461
2462 p32 += 0x100 >> 2;
2463 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2464
186fc259
GFT		 2465 p32 += 0x100 >> 2;
2466 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2467}
2468
2469static int
2470jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2471{
2472 struct jme_adapter *jme = netdev_priv(netdev);
2473
8c198884
GFT		 2474 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2475 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2476
cd0ff491 2477 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2478 ecmd->use_adaptive_rx_coalesce = false;
2479 ecmd->rx_coalesce_usecs = 0;
2480 ecmd->rx_max_coalesced_frames = 0;
2481 return 0;
2482 }
2483
2484 ecmd->use_adaptive_rx_coalesce = true;
2485
cd0ff491 2486 switch (jme->dpi.cur) {
8c198884
GFT		 2487 case PCC_P1:
2488 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2489 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2490 break;
2491 case PCC_P2:
2492 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2493 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2494 break;
2495 case PCC_P3:
2496 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2497 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2498 break;
2499 default:
2500 break;
2501 }
2502
2503 return 0;
2504}
2505
192570e0
GFT		 2506static int
2507jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2508{
2509 struct jme_adapter *jme = netdev_priv(netdev);
2510 struct dynpcc_info *dpi = &(jme->dpi);
2511
cd0ff491 2512 if (netif_running(netdev))
cdcdc9eb
GFT		 2513 return -EBUSY;
2514
7ca9ebee
GFT		 2515 if (ecmd->use_adaptive_rx_coalesce &&
2516 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2517 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2518 jme->jme_rx = netif_rx;
2519 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT		 2520 dpi->cur = PCC_P1;
2521 dpi->attempt = PCC_P1;
2522 dpi->cnt = 0;
2523 jme_set_rx_pcc(jme, PCC_P1);
2524 jme_interrupt_mode(jme);
7ca9ebee
GFT		 2525 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2526 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2527 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2528 jme->jme_rx = netif_receive_skb;
2529 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT		 2530 jme_interrupt_mode(jme);
2531 }
2532
2533 return 0;
2534}
2535
8c198884
GFT		 2536static void
2537jme_get_pauseparam(struct net_device *netdev,
2538 struct ethtool_pauseparam *ecmd)
2539{
2540 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2541 u32 val;
8c198884
GFT		 2542
2543 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2544 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2545
cd0ff491
GFT		 2546 spin_lock_bh(&jme->phy_lock);
2547 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2548 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2549
2550 ecmd->autoneg =
2551 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2552}
2553
2554static int
2555jme_set_pauseparam(struct net_device *netdev,
2556 struct ethtool_pauseparam *ecmd)
2557{
2558 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2559 u32 val;
8c198884 2560
cd0ff491 2561 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2562 (ecmd->tx_pause != 0)) {
2563
cd0ff491 2564 if (ecmd->tx_pause)
8c198884
GFT		 2565 jme->reg_txpfc |= TXPFC_PF_EN;
2566 else
2567 jme->reg_txpfc &= ~TXPFC_PF_EN;
2568
2569 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2570 }
2571
cd0ff491
GFT		 2572 spin_lock_bh(&jme->rxmcs_lock);
2573 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2574 (ecmd->rx_pause != 0)) {
2575
cd0ff491 2576 if (ecmd->rx_pause)
8c198884
GFT		 2577 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2578 else
2579 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2580
2581 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2582 }
cd0ff491 2583 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2584
cd0ff491
GFT		 2585 spin_lock_bh(&jme->phy_lock);
2586 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2587 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2588 (ecmd->autoneg != 0)) {
2589
cd0ff491 2590 if (ecmd->autoneg)
8c198884
GFT		 2591 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2592 else
2593 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2594
b3821cc5
GFT		 2595 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2596 MII_ADVERTISE, val);
8c198884 2597 }
cd0ff491 2598 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2599
2600 return 0;
2601}
2602
29bdd921
GFT		 2603static void
2604jme_get_wol(struct net_device *netdev,
2605 struct ethtool_wolinfo *wol)
2606{
2607 struct jme_adapter *jme = netdev_priv(netdev);
2608
2609 wol->supported = WAKE_MAGIC | WAKE_PHY;
2610
2611 wol->wolopts = 0;
2612
cd0ff491 2613 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2614 wol->wolopts |= WAKE_PHY;
2615
cd0ff491 2616 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2617 wol->wolopts |= WAKE_MAGIC;
2618
2619}
2620
2621static int
2622jme_set_wol(struct net_device *netdev,
2623 struct ethtool_wolinfo *wol)
2624{
2625 struct jme_adapter *jme = netdev_priv(netdev);
2626
cd0ff491 2627 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2628 WAKE_UCAST |
2629 WAKE_MCAST |
2630 WAKE_BCAST |
2631 WAKE_ARP))
2632 return -EOPNOTSUPP;
2633
2634 jme->reg_pmcs = 0;
2635
cd0ff491 2636 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2637 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2638
cd0ff491 2639 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2640 jme->reg_pmcs |= PMCS_MFEN;
2641
cd0ff491 2642 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2643
3d12cc1b
GFT		 2644#ifndef JME_NEW_PM_API
2645 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2646#endif
7370b85a 2647#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3d12cc1b 2648 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
7370b85a 2649#endif
29bdd921
GFT		 2650 return 0;
2651}
b3821cc5 2652
3bf61c55
GFT		 2653static int
2654jme_get_settings(struct net_device *netdev,
2655 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2656{
2657 struct jme_adapter *jme = netdev_priv(netdev);
2658 int rc;
8c198884 2659
cd0ff491 2660 spin_lock_bh(&jme->phy_lock);
d7699f87 2661 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2662 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2663 return rc;
2664}
2665
3bf61c55
GFT		 2666static int
2667jme_set_settings(struct net_device *netdev,
2668 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2669{
2670 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2671 int rc, fdc = 0;
fcf45b4c 2672
8588b84b
DD		 2673 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2674 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2675 return -EINVAL;
2676
e6b41b51
GFT		 2677 /*
2678 * Check If user changed duplex only while force_media.
2679 * Hardware would not generate link change interrupt.
2680 */
cd0ff491 2681 if (jme->mii_if.force_media &&
79ce639c
GFT		 2682 ecmd->autoneg != AUTONEG_ENABLE &&
2683 (jme->mii_if.full_duplex != ecmd->duplex))
2684 fdc = 1;
2685
cd0ff491 2686 spin_lock_bh(&jme->phy_lock);
d7699f87 2687 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2688 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2689
cd0ff491 2690 if (!rc) {
e6b41b51
GFT		 2691 if (fdc)
2692 jme_reset_link(jme);
29bdd921 2693 jme->old_ecmd = *ecmd;
aa1e7189
GFT		 2694 set_bit(JME_FLAG_SSET, &jme->flags);
2695 }
2696
2697 return rc;
2698}
2699
2700static int
2701jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2702{
2703 int rc;
2704 struct jme_adapter *jme = netdev_priv(netdev);
2705 struct mii_ioctl_data *mii_data = if_mii(rq);
2706 unsigned int duplex_chg;
2707
2708 if (cmd == SIOCSMIIREG) {
2709 u16 val = mii_data->val_in;
2710 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2711 (val & BMCR_SPEED1000))
2712 return -EINVAL;
2713 }
2714
2715 spin_lock_bh(&jme->phy_lock);
2716 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2717 spin_unlock_bh(&jme->phy_lock);
2718
2719 if (!rc && (cmd == SIOCSMIIREG)) {
2720 if (duplex_chg)
2721 jme_reset_link(jme);
2722 jme_get_settings(netdev, &jme->old_ecmd);
2723 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2724 }
2725
d7699f87
GFT		 2726 return rc;
2727}
2728
cd0ff491 2729static u32
3bf61c55
GFT		 2730jme_get_link(struct net_device *netdev)
2731{
d7699f87
GFT		 2732 struct jme_adapter *jme = netdev_priv(netdev);
2733 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2734}
2735
8c198884 2736static u32
cd0ff491
GFT		 2737jme_get_msglevel(struct net_device *netdev)
2738{
2739 struct jme_adapter *jme = netdev_priv(netdev);
2740 return jme->msg_enable;
2741}
2742
2743static void
2744jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2745{
cd0ff491
GFT		 2746 struct jme_adapter *jme = netdev_priv(netdev);
2747 jme->msg_enable = value;
2748}
8c198884 2749
cd0ff491
GFT		 2750static u32
2751jme_get_rx_csum(struct net_device *netdev)
2752{
2753 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2754 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2755}
2756
2757static int
2758jme_set_rx_csum(struct net_device *netdev, u32 on)
2759{
cd0ff491 2760 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2761
cd0ff491
GFT		 2762 spin_lock_bh(&jme->rxmcs_lock);
2763 if (on)
8c198884
GFT		 2764 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2765 else
2766 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2767 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2768 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2769
2770 return 0;
2771}
2772
2773static int
2774jme_set_tx_csum(struct net_device *netdev, u32 on)
2775{
cd0ff491 2776 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2777
cd0ff491
GFT		 2778 if (on) {
2779 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2780 if (netdev->mtu <= 1900)
1a0b42f4
MM		 2781 netdev->features |=
2782 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491
GFT		 2783 } else {
2784 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
1a0b42f4
MM		 2785 netdev->features &=
2786 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
b3821cc5 2787 }
8c198884
GFT		 2788
2789 return 0;
2790}
2791
b3821cc5
GFT		 2792static int
2793jme_set_tso(struct net_device *netdev, u32 on)
2794{
cd0ff491 2795 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2796
cd0ff491
GFT		 2797 if (on) {
2798 set_bit(JME_FLAG_TSO, &jme->flags);
2799 if (netdev->mtu <= 1900)
1a0b42f4 2800 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT		 2801 } else {
2802 clear_bit(JME_FLAG_TSO, &jme->flags);
1a0b42f4 2803 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT		 2804 }
2805
cd0ff491 2806 return 0;
b3821cc5
GFT		 2807}
2808
8c198884
GFT		 2809static int
2810jme_nway_reset(struct net_device *netdev)
2811{
cd0ff491 2812 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2813 jme_restart_an(jme);
2814 return 0;
2815}
2816
cd0ff491 2817static u8
186fc259
GFT		 2818jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2819{
cd0ff491 2820 u32 val;
186fc259
GFT		 2821 int to;
2822
2823 val = jread32(jme, JME_SMBCSR);
2824 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2825 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2826 msleep(1);
2827 val = jread32(jme, JME_SMBCSR);
2828 }
cd0ff491 2829 if (!to) {
937ef75a 2830 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2831 return 0xFF;
2832 }
2833
2834 jwrite32(jme, JME_SMBINTF,
2835 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2836 SMBINTF_HWRWN_READ |
2837 SMBINTF_HWCMD);
2838
2839 val = jread32(jme, JME_SMBINTF);
2840 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2841 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2842 msleep(1);
2843 val = jread32(jme, JME_SMBINTF);
2844 }
cd0ff491 2845 if (!to) {
937ef75a 2846 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2847 return 0xFF;
2848 }
2849
2850 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2851}
2852
2853static void
cd0ff491 2854jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2855{
cd0ff491 2856 u32 val;
186fc259
GFT		 2857 int to;
2858
2859 val = jread32(jme, JME_SMBCSR);
2860 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2861 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2862 msleep(1);
2863 val = jread32(jme, JME_SMBCSR);
2864 }
cd0ff491 2865 if (!to) {
937ef75a 2866 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2867 return;
2868 }
2869
2870 jwrite32(jme, JME_SMBINTF,
2871 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2872 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2873 SMBINTF_HWRWN_WRITE |
2874 SMBINTF_HWCMD);
2875
2876 val = jread32(jme, JME_SMBINTF);
2877 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2878 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2879 msleep(1);
2880 val = jread32(jme, JME_SMBINTF);
2881 }
cd0ff491 2882 if (!to) {
937ef75a 2883 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2884 return;
2885 }
2886
2887 mdelay(2);
2888}
2889
2890static int
2891jme_get_eeprom_len(struct net_device *netdev)
2892{
cd0ff491
GFT		 2893 struct jme_adapter *jme = netdev_priv(netdev);
2894 u32 val;
186fc259 2895 val = jread32(jme, JME_SMBCSR);
cd0ff491 2896 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 2897}
2898
2899static int
2900jme_get_eeprom(struct net_device *netdev,
2901 struct ethtool_eeprom *eeprom, u8 *data)
2902{
cd0ff491 2903 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2904 int i, offset = eeprom->offset, len = eeprom->len;
2905
2906 /*
8d27293f 2907 * ethtool will check the boundary for us
186fc259
GFT		 2908 */
2909 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2910 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2911 data[i] = jme_smb_read(jme, i + offset);
2912
2913 return 0;
2914}
2915
2916static int
2917jme_set_eeprom(struct net_device *netdev,
2918 struct ethtool_eeprom *eeprom, u8 *data)
2919{
cd0ff491 2920 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2921 int i, offset = eeprom->offset, len = eeprom->len;
2922
2923 if (eeprom->magic != JME_EEPROM_MAGIC)
2924 return -EINVAL;
2925
2926 /*
8d27293f 2927 * ethtool will check the boundary for us
186fc259 2928 */
cd0ff491 2929 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2930 jme_smb_write(jme, i + offset, data[i]);
2931
2932 return 0;
2933}
2934
3b70a6fa
GFT		 2935#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2936static struct ethtool_ops jme_ethtool_ops = {
2937#else
d7699f87 2938static const struct ethtool_ops jme_ethtool_ops = {
3b70a6fa 2939#endif
cd0ff491 2940 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 2941 .get_regs_len = jme_get_regs_len,
2942 .get_regs = jme_get_regs,
2943 .get_coalesce = jme_get_coalesce,
192570e0 2944 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 2945 .get_pauseparam = jme_get_pauseparam,
2946 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 2947 .get_wol = jme_get_wol,
2948 .set_wol = jme_set_wol,
d7699f87
GFT		 2949 .get_settings = jme_get_settings,
2950 .set_settings = jme_set_settings,
2951 .get_link = jme_get_link,
cd0ff491
GFT		 2952 .get_msglevel = jme_get_msglevel,
2953 .set_msglevel = jme_set_msglevel,
8c198884
GFT		 2954 .get_rx_csum = jme_get_rx_csum,
2955 .set_rx_csum = jme_set_rx_csum,
2956 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT		 2957 .set_tso = jme_set_tso,
2958 .set_sg = ethtool_op_set_sg,
8c198884 2959 .nway_reset = jme_nway_reset,
186fc259
GFT		 2960 .get_eeprom_len = jme_get_eeprom_len,
2961 .get_eeprom = jme_get_eeprom,
2962 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 2963};
2964
3bf61c55
GFT		 2965static int
2966jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2967{
3b70a6fa 2968 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 2969#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2970 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2971#else
2972 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2973#endif
2974 )
2975#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2976 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2977#else
cd0ff491 2978 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
0ede469c 2979#endif
3bf61c55
GFT		 2980 return 1;
2981
3b70a6fa 2982 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 2983#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2984 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2985#else
2986 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2987#endif
2988 )
2989#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2990 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2991#else
cd0ff491 2992 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
0ede469c 2993#endif
8c198884
GFT		 2994 return 1;
2995
0ede469c
GFT		 2996#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2997 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2998 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2999#else
cd0ff491
GFT		 3000 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3001 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
0ede469c 3002#endif
3bf61c55
GFT		 3003 return 0;
3004
3005 return -1;
3006}
3007
cd0ff491 3008static inline void
cdcdc9eb
GFT		 3009jme_phy_init(struct jme_adapter *jme)
3010{
cd0ff491 3011 u16 reg26;
cdcdc9eb
GFT		 3012
3013 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3014 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3015}
3016
cd0ff491 3017static inline void
cdcdc9eb 3018jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 3019{
cd0ff491 3020 u32 chipmode;
cdcdc9eb
GFT		 3021
3022 chipmode = jread32(jme, JME_CHIPMODE);
3023
3024 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 3025 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
98ef18f1
GFT		 3026 jme->chip_main_rev = jme->chiprev & 0xF;
3027 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT		 3028}
3029
3b70a6fa
GFT		 3030#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3031static const struct net_device_ops jme_netdev_ops = {
3032 .ndo_open = jme_open,
3033 .ndo_stop = jme_close,
3034 .ndo_validate_addr = eth_validate_addr,
aa1e7189 3035 .ndo_do_ioctl = jme_ioctl,
3b70a6fa
GFT		 3036 .ndo_start_xmit = jme_start_xmit,
3037 .ndo_set_mac_address = jme_set_macaddr,
3038 .ndo_set_multicast_list = jme_set_multi,
3039 .ndo_change_mtu = jme_change_mtu,
3040 .ndo_tx_timeout = jme_tx_timeout,
3041 .ndo_vlan_rx_register = jme_vlan_rx_register,
3042};
3043#endif
3044
3bf61c55
GFT		 3045static int __devinit
3046jme_init_one(struct pci_dev *pdev,
3047 const struct pci_device_id *ent)
3048{
cdcdc9eb 3049 int rc = 0, using_dac, i;
d7699f87
GFT		 3050 struct net_device *netdev;
3051 struct jme_adapter *jme;
cd0ff491
GFT		 3052 u16 bmcr, bmsr;
3053 u32 apmc;
d7699f87
GFT		 3054
3055 /*
3056 * set up PCI device basics
3057 */
4330c2f2 3058 rc = pci_enable_device(pdev);
cd0ff491 3059 if (rc) {
937ef75a 3060 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT		 3061 goto err_out;
3062 }
d7699f87 3063
3bf61c55 3064 using_dac = jme_pci_dma64(pdev);
cd0ff491 3065 if (using_dac < 0) {
937ef75a 3066 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT		 3067 rc = -EIO;
3068 goto err_out_disable_pdev;
3069 }
3070
cd0ff491 3071 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
937ef75a 3072 pr_err("No PCI resource region found\n");
4330c2f2
GFT		 3073 rc = -ENOMEM;
3074 goto err_out_disable_pdev;
3075 }
d7699f87 3076
4330c2f2 3077 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 3078 if (rc) {
937ef75a 3079 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT		 3080 goto err_out_disable_pdev;
3081 }
d7699f87
GFT		 3082
3083 pci_set_master(pdev);
3084
3085 /*
3086 * alloc and init net device
3087 */
3bf61c55 3088 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 3089 if (!netdev) {
937ef75a 3090 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT		 3091 rc = -ENOMEM;
3092 goto err_out_release_regions;
d7699f87 3093 }
3b70a6fa
GFT		 3094#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3095 netdev->netdev_ops = &jme_netdev_ops;
3096#else
d7699f87
GFT		 3097 netdev->open = jme_open;
3098 netdev->stop = jme_close;
aa1e7189 3099 netdev->do_ioctl = jme_ioctl;
d7699f87 3100 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT		 3101 netdev->set_mac_address = jme_set_macaddr;
3102 netdev->set_multicast_list = jme_set_multi;
3103 netdev->change_mtu = jme_change_mtu;
8c198884 3104 netdev->tx_timeout = jme_tx_timeout;
42b1055e 3105 netdev->vlan_rx_register = jme_vlan_rx_register;
7ca9ebee
GFT		 3106#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3107 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3108#endif
3bf61c55 3109 NETDEV_GET_STATS(netdev, &jme_get_stats);
3b70a6fa
GFT		 3110#endif
3111 netdev->ethtool_ops = &jme_ethtool_ops;
3112 netdev->watchdog_timeo = TX_TIMEOUT;
1a0b42f4
MM		 3113 netdev->features = NETIF_F_IP_CSUM |
3114 NETIF_F_IPV6_CSUM |
b3821cc5
GFT		 3115 NETIF_F_SG |
3116 NETIF_F_TSO |
3117 NETIF_F_TSO6 |
42b1055e
GFT		 3118 NETIF_F_HW_VLAN_TX |
3119 NETIF_F_HW_VLAN_RX;
cd0ff491 3120 if (using_dac)
8c198884 3121 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 3122
3123 SET_NETDEV_DEV(netdev, &pdev->dev);
3124 pci_set_drvdata(pdev, netdev);
3125
3126 /*
3127 * init adapter info
3128 */
3129 jme = netdev_priv(netdev);
3130 jme->pdev = pdev;
3131 jme->dev = netdev;
cdcdc9eb
GFT		 3132 jme->jme_rx = netif_rx;
3133 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 3134 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 3135 jme->phylink = 0;
b3821cc5 3136 jme->tx_ring_size = 1 << 10;
0ede469c 3137 jme->tx_ring_mask = jme->tx_ring_size - 1;
b3821cc5
GFT		 3138 jme->tx_wake_threshold = 1 << 9;
3139 jme->rx_ring_size = 1 << 9;
3140 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 3141 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 3142 jme->regs = ioremap(pci_resource_start(pdev, 0),
3143 pci_resource_len(pdev, 0));
4330c2f2 3144 if (!(jme->regs)) {
937ef75a 3145 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT		 3146 rc = -ENOMEM;
3147 goto err_out_free_netdev;
3148 }
4330c2f2 3149
cd0ff491
GFT		 3150 if (no_pseudohp) {
3151 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3152 jwrite32(jme, JME_APMC, apmc);
3153 } else if (force_pseudohp) {
3154 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3155 jwrite32(jme, JME_APMC, apmc);
3156 }
3157
cdcdc9eb 3158 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 3159
d7699f87 3160 spin_lock_init(&jme->phy_lock);
fcf45b4c 3161 spin_lock_init(&jme->macaddr_lock);
8c198884 3162 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 3163
fcf45b4c
GFT		 3164 atomic_set(&jme->link_changing, 1);
3165 atomic_set(&jme->rx_cleaning, 1);
3166 atomic_set(&jme->tx_cleaning, 1);
192570e0 3167 atomic_set(&jme->rx_empty, 1);
fcf45b4c 3168
79ce639c 3169 tasklet_init(&jme->pcc_task,
7ca9ebee 3170 jme_pcc_tasklet,
79ce639c 3171 (unsigned long) jme);
4330c2f2 3172 tasklet_init(&jme->linkch_task,
7ca9ebee 3173 jme_link_change_tasklet,
4330c2f2
GFT		 3174 (unsigned long) jme);
3175 tasklet_init(&jme->txclean_task,
7ca9ebee 3176 jme_tx_clean_tasklet,
4330c2f2
GFT		 3177 (unsigned long) jme);
3178 tasklet_init(&jme->rxclean_task,
7ca9ebee 3179 jme_rx_clean_tasklet,
4330c2f2 3180 (unsigned long) jme);
fcf45b4c 3181 tasklet_init(&jme->rxempty_task,
7ca9ebee 3182 jme_rx_empty_tasklet,
fcf45b4c 3183 (unsigned long) jme);
0ede469c 3184 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 3185 tasklet_disable_nosync(&jme->txclean_task);
3186 tasklet_disable_nosync(&jme->rxclean_task);
3187 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 3188 jme->dpi.cur = PCC_P1;
3189
cd0ff491 3190 jme->reg_ghc = 0;
79ce639c 3191 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 3192 jme->reg_rxmcs = RXMCS_DEFAULT;
3193 jme->reg_txpfc = 0;
47220951 3194 jme->reg_pmcs = PMCS_MFEN;
dc4185bd 3195 jme->reg_gpreg1 = GPREG1_DEFAULT;
cd0ff491
GFT		 3196 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3197 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 3198
3d12cc1b
GFT		 3199 jme_clear_pm(jme);
3200 pci_set_power_state(jme->pdev, PCI_D0);
3201#ifndef JME_NEW_PM_API
3202 jme_pci_wakeup_enable(jme, true);
3203#endif
3204#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3205 device_set_wakeup_enable(&jme->pdev->dev, true);
3206#endif
3207
fcf45b4c
GFT		 3208 /*
3209 * Get Max Read Req Size from PCI Config Space
3210 */
cd0ff491
GFT		 3211 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3212 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3213 switch (jme->mrrs) {
3214 case MRRS_128B:
3215 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3216 break;
3217 case MRRS_256B:
3218 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3219 break;
3220 default:
3221 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3222 break;
cd54cf32 3223 }
fcf45b4c 3224
d7699f87 3225 /*
cdcdc9eb 3226 * Must check before reset_mac_processor
d7699f87 3227 */
cdcdc9eb
GFT		 3228 jme_check_hw_ver(jme);
3229 jme->mii_if.dev = netdev;
cd0ff491 3230 if (jme->fpgaver) {
cdcdc9eb 3231 jme->mii_if.phy_id = 0;
cd0ff491 3232 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 3233 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3234 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3235 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 3236 jme->mii_if.phy_id = i;
3237 break;
3238 }
3239 }
3240
cd0ff491 3241 if (!jme->mii_if.phy_id) {
cdcdc9eb 3242 rc = -EIO;
937ef75a
JP		 3243 pr_err("Can not find phy_id\n");
3244 goto err_out_unmap;
cdcdc9eb
GFT		 3245 }
3246
3247 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3248 } else {
cdcdc9eb
GFT		 3249 jme->mii_if.phy_id = 1;
3250 }
cd0ff491 3251 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 3252 jme->mii_if.supports_gmii = true;
3253 else
3254 jme->mii_if.supports_gmii = false;
aa1e7189
GFT		 3255 jme->mii_if.phy_id_mask = 0x1F;
3256 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT		 3257 jme->mii_if.mdio_read = jme_mdio_read;
3258 jme->mii_if.mdio_write = jme_mdio_write;
3259
55d19799 3260 jme_set_phyfifo_5level(jme);
711edd99 3261#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
98ef18f1 3262 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
711edd99
SS		 3263#else
3264 jme->pcirev = pdev->revision;
3265#endif
cd0ff491 3266 if (!jme->fpgaver)
cdcdc9eb 3267 jme_phy_init(jme);
42b1055e 3268 jme_phy_off(jme);
cdcdc9eb
GFT		 3269
3270 /*
3271 * Reset MAC processor and reload EEPROM for MAC Address
3272 */
d7699f87 3273 jme_reset_mac_processor(jme);
4330c2f2 3274 rc = jme_reload_eeprom(jme);
cd0ff491 3275 if (rc) {
937ef75a 3276 pr_err("Reload eeprom for reading MAC Address error\n");
0ede469c 3277 goto err_out_unmap;
4330c2f2 3278 }
d7699f87
GFT		 3279 jme_load_macaddr(netdev);
3280
d7699f87
GFT		 3281 /*
3282 * Tell stack that we are not ready to work until open()
3283 */
3284 netif_carrier_off(netdev);
d7699f87 3285
4330c2f2 3286 rc = register_netdev(netdev);
cd0ff491 3287 if (rc) {
937ef75a 3288 pr_err("Cannot register net device\n");
0ede469c 3289 goto err_out_unmap;
4330c2f2 3290 }
d7699f87 3291
98ef18f1 3292 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
937ef75a 3293 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
7ca9ebee
GFT		 3294 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3295 "JMC250 Gigabit Ethernet" :
3296 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3297 "JMC260 Fast Ethernet" : "Unknown",
3298 (jme->fpgaver != 0) ? " (FPGA)" : "",
3299 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
98ef18f1 3300 jme->pcirev,
937ef75a
JP		 3301 netdev->dev_addr[0],
3302 netdev->dev_addr[1],
3303 netdev->dev_addr[2],
3304 netdev->dev_addr[3],
3305 netdev->dev_addr[4],
3306 netdev->dev_addr[5]);
d7699f87
GFT		 3307
3308 return 0;
3309
3310err_out_unmap:
3311 iounmap(jme->regs);
3312err_out_free_netdev:
3313 pci_set_drvdata(pdev, NULL);
3314 free_netdev(netdev);
4330c2f2
GFT		 3315err_out_release_regions:
3316 pci_release_regions(pdev);
d7699f87 3317err_out_disable_pdev:
cd0ff491 3318 pci_disable_device(pdev);
d7699f87 3319err_out:
4330c2f2 3320 return rc;
d7699f87
GFT		 3321}
3322
3bf61c55
GFT		 3323static void __devexit
3324jme_remove_one(struct pci_dev *pdev)
3325{
d7699f87
GFT		 3326 struct net_device *netdev = pci_get_drvdata(pdev);
3327 struct jme_adapter *jme = netdev_priv(netdev);
3328
3329 unregister_netdev(netdev);
3330 iounmap(jme->regs);
3331 pci_set_drvdata(pdev, NULL);
3332 free_netdev(netdev);
3333 pci_release_regions(pdev);
3334 pci_disable_device(pdev);
3335
3336}
3337
a82e368c
GFT		 3338static void
3339jme_shutdown(struct pci_dev *pdev)
3340{
3341 struct net_device *netdev = pci_get_drvdata(pdev);
3342 struct jme_adapter *jme = netdev_priv(netdev);
3343
3d12cc1b
GFT		 3344 if (jme->reg_pmcs) {
3345 jme_powersave_phy(jme);
3346 jme_pci_wakeup_enable(jme, true);
3347#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3348 device_set_wakeup_enable(&jme->pdev->dev, true);
a82e368c 3349#endif
3d12cc1b
GFT		 3350 } else {
3351 jme_phy_off(jme);
3352 }
a82e368c
GFT		 3353}
3354
fda5634a
GFT		 3355#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3356 #ifdef CONFIG_PM
3357 #define JME_HAVE_PM
3358 #endif
3359#else
3360 #ifdef CONFIG_PM_SLEEP
3361 #define JME_HAVE_PM
3362 #endif
3363#endif
3364
3365#ifdef JME_HAVE_PM
29bdd921 3366static int
3d12cc1b 3367#ifdef JME_NEW_PM_API
7370b85a 3368jme_suspend(struct device *dev)
3d12cc1b
GFT		 3369#else
3370jme_suspend(struct pci_dev *pdev, pm_message_t state)
7370b85a 3371#endif
29bdd921 3372{
3d12cc1b 3373#ifdef JME_NEW_PM_API
7370b85a
RW		 3374 struct pci_dev *pdev = to_pci_dev(dev);
3375#endif
29bdd921
GFT		 3376 struct net_device *netdev = pci_get_drvdata(pdev);
3377 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 3378
3379 atomic_dec(&jme->link_changing);
3380
3381 netif_device_detach(netdev);
3382 netif_stop_queue(netdev);
3383 jme_stop_irq(jme);
29bdd921 3384
cd0ff491
GFT		 3385 tasklet_disable(&jme->txclean_task);
3386 tasklet_disable(&jme->rxclean_task);
3387 tasklet_disable(&jme->rxempty_task);
3388
cd0ff491
GFT		 3389 if (netif_carrier_ok(netdev)) {
3390 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 3391 jme_polling_mode(jme);
3392
29bdd921 3393 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 3394 jme_disable_rx_engine(jme);
3395 jme_disable_tx_engine(jme);
29bdd921
GFT		 3396 jme_reset_mac_processor(jme);
3397 jme_free_rx_resources(jme);
3398 jme_free_tx_resources(jme);
3399 netif_carrier_off(netdev);
3400 jme->phylink = 0;
3401 }
3402
cd0ff491
GFT		 3403 tasklet_enable(&jme->txclean_task);
3404 tasklet_hi_enable(&jme->rxclean_task);
3405 tasklet_hi_enable(&jme->rxempty_task);
29bdd921 3406
a82e368c 3407 jme_powersave_phy(jme);
3d12cc1b 3408#ifndef JME_NEW_PM_API
7370b85a 3409 pci_save_state(pdev);
3d12cc1b 3410 jme_pci_wakeup_enable(jme, true);
a82e368c 3411 pci_set_power_state(pdev, PCI_D3hot);
7370b85a 3412#endif
3d12cc1b 3413 jme_clear_pm(jme);
29bdd921
GFT		 3414
3415 return 0;
3416}
3417
3418static int
3d12cc1b 3419#ifdef JME_NEW_PM_API
7370b85a 3420jme_resume(struct device *dev)
3d12cc1b
GFT		 3421#else
3422jme_resume(struct pci_dev *pdev)
7370b85a 3423#endif
29bdd921 3424{
3d12cc1b 3425#ifdef JME_NEW_PM_API
7370b85a
RW		 3426 struct pci_dev *pdev = to_pci_dev(dev);
3427#endif
29bdd921
GFT		 3428 struct net_device *netdev = pci_get_drvdata(pdev);
3429 struct jme_adapter *jme = netdev_priv(netdev);
3430
3431 jme_clear_pm(jme);
3d12cc1b
GFT		 3432#ifndef JME_NEW_PM_API
3433 pci_set_power_state(pdev, PCI_D0);
29bdd921 3434 pci_restore_state(pdev);
7370b85a 3435#endif
29bdd921 3436
ed457bcc
GFT		 3437 jme_phy_on(jme);
3438 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3439 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 3440 else
29bdd921
GFT		 3441 jme_reset_phy_processor(jme);
3442
29bdd921
GFT		 3443 jme_start_irq(jme);
3444 netif_device_attach(netdev);
3445
3446 atomic_inc(&jme->link_changing);
3447
3448 jme_reset_link(jme);
3449
3450 return 0;
3451}
7370b85a
RW		 3452
3453#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
3454static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3455#define JME_PM_OPS (&jme_pm_ops)
3456#endif
3457
3458#else
3459
3460#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
3461#define JME_PM_OPS NULL
3462#endif
7ee473a3 3463#endif
29bdd921 3464
7ca9ebee 3465#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
d7699f87 3466static struct pci_device_id jme_pci_tbl[] = {
7ca9ebee
GFT		 3467#else
3468static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3469#endif
cd0ff491
GFT		 3470 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3471 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3472 { }
3473};
3474
3475static struct pci_driver jme_driver = {
cd0ff491
GFT		 3476 .name = DRV_NAME,
3477 .id_table = jme_pci_tbl,
3478 .probe = jme_init_one,
3479 .remove = __devexit_p(jme_remove_one),
a82e368c 3480 .shutdown = jme_shutdown,
7370b85a
RW		 3481#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,38)
3482 .suspend = jme_suspend,
3483 .resume = jme_resume
3484#else
3485 .driver.pm = JME_PM_OPS,
3486#endif
d7699f87
GFT		 3487};
3488
3bf61c55
GFT		 3489static int __init
3490jme_init_module(void)
d7699f87 3491{
937ef75a 3492 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3493 return pci_register_driver(&jme_driver);
3494}
3495
3bf61c55
GFT		 3496static void __exit
3497jme_cleanup_module(void)
d7699f87
GFT		 3498{
3499 pci_unregister_driver(&jme_driver);
3500}
3501
3502module_init(jme_init_module);
3503module_exit(jme_cleanup_module);
3504
3bf61c55 3505MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3506MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3507MODULE_LICENSE("GPL");
3508MODULE_VERSION(DRV_VERSION);
3509MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3510
JMicron Ethernet Linux driver