jme: Update CHANGELOG
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
2e582300 25#include <linux/version.h>
937ef75a
JP
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
d7699f87
GFT
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
4330c2f2 38#include <linux/delay.h>
29bdd921 39#include <linux/spinlock.h>
8c198884
GFT
40#include <linux/in.h>
41#include <linux/ip.h>
79ce639c
GFT
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
42b1055e 45#include <linux/if_vlan.h>
38d1bc09 46#include <linux/slab.h>
3b70a6fa 47#include <net/ip6_checksum.h>
d7699f87
GFT
48#include "jme.h"
49
cd0ff491
GFT
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 61
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GFT
62static int
63jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT
64{
65 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 67
186fc259 68read_again:
cd0ff491 69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT
70 smi_phy_addr(phy) |
71 smi_reg_addr(reg));
d7699f87
GFT
72
73 wmb();
cd0ff491 74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 75 udelay(20);
b3821cc5
GFT
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
3bf61c55 78 break;
cd0ff491 79 }
d7699f87 80
cd0ff491 81 if (i == 0) {
937ef75a 82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 83 return 0;
cd0ff491 84 }
d7699f87 85
cd0ff491 86 if (again--)
186fc259
GFT
87 goto read_again;
88
cd0ff491 89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT
90}
91
3bf61c55
GFT
92static void
93jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
d7699f87
GFT
95{
96 struct jme_adapter *jme = netdev_priv(netdev);
97 int i;
98
3bf61c55
GFT
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
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GFT
102
103 wmb();
cdcdc9eb
GFT
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
105 udelay(20);
8d27293f 106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT
107 break;
108 }
d7699f87 109
3bf61c55 110 if (i == 0)
937ef75a 111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT
112}
113
cd0ff491 114static inline void
3bf61c55 115jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 116{
cd0ff491 117 u32 val;
3bf61c55
GFT
118
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
8c198884
GFT
121 MII_ADVERTISE, ADVERTISE_ALL |
122 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 123
cd0ff491 124 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
125 jme_mdio_write(jme->dev,
126 jme->mii_if.phy_id,
127 MII_CTRL1000,
128 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 129
fcf45b4c
GFT
130 val = jme_mdio_read(jme->dev,
131 jme->mii_if.phy_id,
132 MII_BMCR);
133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
136 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT
137}
138
b3821cc5
GFT
139static void
140jme_setup_wakeup_frame(struct jme_adapter *jme,
cd0ff491 141 u32 *mask, u32 crc, int fnr)
b3821cc5
GFT
142{
143 int i;
144
145 /*
146 * Setup CRC pattern
147 */
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
149 wmb();
150 jwrite32(jme, JME_WFODP, crc);
151 wmb();
152
153 /*
154 * Setup Mask
155 */
cd0ff491 156 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
160 wmb();
161 jwrite32(jme, JME_WFODP, mask[i]);
162 wmb();
163 }
164}
3bf61c55 165
cd0ff491 166static inline void
3bf61c55
GFT
167jme_reset_mac_processor(struct jme_adapter *jme)
168{
cd0ff491
GFT
169 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
170 u32 crc = 0xCDCDCDCD;
171 u32 gpreg0;
b3821cc5
GFT
172 int i;
173
3bf61c55 174 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 175 udelay(2);
3bf61c55 176 jwrite32(jme, JME_GHC, jme->reg_ghc);
cd0ff491
GFT
177
178 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
179 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
180 jwrite32(jme, JME_RXQDC, 0x00000000);
181 jwrite32(jme, JME_RXNDA, 0x00000000);
182 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
183 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
184 jwrite32(jme, JME_TXQDC, 0x00000000);
185 jwrite32(jme, JME_TXNDA, 0x00000000);
186
4330c2f2
GFT
187 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
188 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 189 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 190 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 191 if (jme->fpgaver)
cdcdc9eb
GFT
192 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
193 else
194 gpreg0 = GPREG0_DEFAULT;
195 jwrite32(jme, JME_GPREG0, gpreg0);
7ee473a3 196 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
d7699f87
GFT
197}
198
cd0ff491
GFT
199static inline void
200jme_reset_ghc_speed(struct jme_adapter *jme)
201{
202 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
203 jwrite32(jme, JME_GHC, jme->reg_ghc);
204}
205
206static inline void
3bf61c55 207jme_clear_pm(struct jme_adapter *jme)
d7699f87 208{
29bdd921 209 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 210 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 211 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT
212}
213
3bf61c55
GFT
214static int
215jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 216{
cd0ff491 217 u32 val;
d7699f87
GFT
218 int i;
219
220 val = jread32(jme, JME_SMBCSR);
221
cd0ff491 222 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT
223 val |= SMBCSR_CNACK;
224 jwrite32(jme, JME_SMBCSR, val);
225 val |= SMBCSR_RELOAD;
226 jwrite32(jme, JME_SMBCSR, val);
227 mdelay(12);
228
cd0ff491 229 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT
230 mdelay(1);
231 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
232 break;
233 }
234
cd0ff491 235 if (i == 0) {
937ef75a 236 pr_err("eeprom reload timeout\n");
d7699f87
GFT
237 return -EIO;
238 }
239 }
3bf61c55 240
d7699f87
GFT
241 return 0;
242}
243
3bf61c55
GFT
244static void
245jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT
246{
247 struct jme_adapter *jme = netdev_priv(netdev);
248 unsigned char macaddr[6];
cd0ff491 249 u32 val;
d7699f87 250
cd0ff491 251 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 252 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT
253 macaddr[0] = (val >> 0) & 0xFF;
254 macaddr[1] = (val >> 8) & 0xFF;
255 macaddr[2] = (val >> 16) & 0xFF;
256 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 257 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT
258 macaddr[4] = (val >> 0) & 0xFF;
259 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT
260 memcpy(netdev->dev_addr, macaddr, 6);
261 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT
262}
263
cd0ff491 264static inline void
3bf61c55
GFT
265jme_set_rx_pcc(struct jme_adapter *jme, int p)
266{
cd0ff491 267 switch (p) {
192570e0
GFT
268 case PCC_OFF:
269 jwrite32(jme, JME_PCCRX0,
270 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
271 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
272 break;
3bf61c55
GFT
273 case PCC_P1:
274 jwrite32(jme, JME_PCCRX0,
275 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
276 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
277 break;
278 case PCC_P2:
279 jwrite32(jme, JME_PCCRX0,
280 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
281 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
282 break;
283 case PCC_P3:
284 jwrite32(jme, JME_PCCRX0,
285 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
286 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
287 break;
288 default:
289 break;
290 }
192570e0 291 wmb();
3bf61c55 292
cd0ff491 293 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
7ca9ebee 294 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT
295}
296
fcf45b4c 297static void
3bf61c55 298jme_start_irq(struct jme_adapter *jme)
d7699f87 299{
3bf61c55
GFT
300 register struct dynpcc_info *dpi = &(jme->dpi);
301
302 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT
303 dpi->cur = PCC_P1;
304 dpi->attempt = PCC_P1;
305 dpi->cnt = 0;
306
307 jwrite32(jme, JME_PCCTX,
8c198884
GFT
308 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
309 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
310 PCCTXQ0_EN
311 );
312
d7699f87
GFT
313 /*
314 * Enable Interrupts
315 */
316 jwrite32(jme, JME_IENS, INTR_ENABLE);
317}
318
cd0ff491 319static inline void
3bf61c55 320jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
321{
322 /*
323 * Disable Interrupts
324 */
cd0ff491 325 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT
326}
327
cd0ff491 328static u32
cdcdc9eb
GFT
329jme_linkstat_from_phy(struct jme_adapter *jme)
330{
cd0ff491 331 u32 phylink, bmsr;
cdcdc9eb
GFT
332
333 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
334 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 335 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT
336 phylink |= PHY_LINK_AUTONEG_COMPLETE;
337
338 return phylink;
339}
340
cd0ff491 341static inline void
58c92f28 342jme_set_phyfifoa(struct jme_adapter *jme)
cd0ff491
GFT
343{
344 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
345}
346
347static inline void
58c92f28 348jme_set_phyfifob(struct jme_adapter *jme)
cd0ff491
GFT
349{
350 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
351}
352
fcf45b4c
GFT
353static int
354jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
355{
356 struct jme_adapter *jme = netdev_priv(netdev);
7ee473a3 357 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
79ce639c 358 char linkmsg[64];
fcf45b4c 359 int rc = 0;
d7699f87 360
b3821cc5 361 linkmsg[0] = '\0';
cdcdc9eb 362
cd0ff491 363 if (jme->fpgaver)
cdcdc9eb
GFT
364 phylink = jme_linkstat_from_phy(jme);
365 else
366 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 367
cd0ff491
GFT
368 if (phylink & PHY_LINK_UP) {
369 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT
370 /*
371 * If we did not enable AN
372 * Speed/Duplex Info should be obtained from SMI
373 */
374 phylink = PHY_LINK_UP;
375
376 bmcr = jme_mdio_read(jme->dev,
377 jme->mii_if.phy_id,
378 MII_BMCR);
379
380 phylink |= ((bmcr & BMCR_SPEED1000) &&
381 (bmcr & BMCR_SPEED100) == 0) ?
382 PHY_LINK_SPEED_1000M :
383 (bmcr & BMCR_SPEED100) ?
384 PHY_LINK_SPEED_100M :
385 PHY_LINK_SPEED_10M;
386
387 phylink |= (bmcr & BMCR_FULLDPLX) ?
388 PHY_LINK_DUPLEX : 0;
79ce639c 389
b3821cc5 390 strcat(linkmsg, "Forced: ");
cd0ff491 391 } else {
8c198884
GFT
392 /*
393 * Keep polling for speed/duplex resolve complete
394 */
cd0ff491 395 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT
396 --cnt) {
397
398 udelay(1);
8c198884 399
cd0ff491 400 if (jme->fpgaver)
cdcdc9eb
GFT
401 phylink = jme_linkstat_from_phy(jme);
402 else
403 phylink = jread32(jme, JME_PHY_LINK);
8c198884 404 }
cd0ff491 405 if (!cnt)
937ef75a 406 pr_err("Waiting speed resolve timeout\n");
79ce639c 407
b3821cc5 408 strcat(linkmsg, "ANed: ");
d7699f87
GFT
409 }
410
cd0ff491 411 if (jme->phylink == phylink) {
fcf45b4c
GFT
412 rc = 1;
413 goto out;
414 }
cd0ff491 415 if (testonly)
fcf45b4c
GFT
416 goto out;
417
418 jme->phylink = phylink;
419
3b70a6fa
GFT
420 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
421 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
422 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
cd0ff491
GFT
423 switch (phylink & PHY_LINK_SPEED_MASK) {
424 case PHY_LINK_SPEED_10M:
3b70a6fa
GFT
425 ghc |= GHC_SPEED_10M |
426 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 427 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT
428 break;
429 case PHY_LINK_SPEED_100M:
3b70a6fa
GFT
430 ghc |= GHC_SPEED_100M |
431 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 432 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT
433 break;
434 case PHY_LINK_SPEED_1000M:
3b70a6fa
GFT
435 ghc |= GHC_SPEED_1000M |
436 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
cd0ff491 437 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT
438 break;
439 default:
440 break;
d7699f87 441 }
d7699f87 442
cd0ff491 443 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 444 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
7ee473a3 445 ghc |= GHC_DPX;
cd0ff491 446 } else {
d7699f87 447 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
448 TXMCS_BACKOFF |
449 TXMCS_CARRIERSENSE |
450 TXMCS_COLLISION);
8c198884
GFT
451 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
452 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
453 TXTRHD_TXREN |
454 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
455 }
7ee473a3
GFT
456
457 gpreg1 = GPREG1_DEFAULT;
458 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
459 if (!(phylink & PHY_LINK_DUPLEX))
460 gpreg1 |= GPREG1_HALFMODEPATCH;
461 switch (phylink & PHY_LINK_SPEED_MASK) {
462 case PHY_LINK_SPEED_10M:
463 jme_set_phyfifoa(jme);
464 gpreg1 |= GPREG1_RSSPATCH;
465 break;
466 case PHY_LINK_SPEED_100M:
467 jme_set_phyfifob(jme);
468 gpreg1 |= GPREG1_RSSPATCH;
469 break;
470 case PHY_LINK_SPEED_1000M:
471 jme_set_phyfifoa(jme);
472 break;
473 default:
474 break;
475 }
476 }
d7699f87 477
3b70a6fa 478 jwrite32(jme, JME_GPREG1, gpreg1);
fcf45b4c 479 jwrite32(jme, JME_GHC, ghc);
3b70a6fa 480 jme->reg_ghc = ghc;
fcf45b4c 481
3b70a6fa
GFT
482 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
483 "Full-Duplex, " :
484 "Half-Duplex, ");
485 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
486 "MDI-X" :
487 "MDI");
937ef75a 488 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT
489 netif_carrier_on(netdev);
490 } else {
491 if (testonly)
fcf45b4c
GFT
492 goto out;
493
937ef75a 494 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 495 jme->phylink = 0;
cd0ff491 496 netif_carrier_off(netdev);
d7699f87 497 }
fcf45b4c
GFT
498
499out:
500 return rc;
d7699f87
GFT
501}
502
3bf61c55
GFT
503static int
504jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 505{
d7699f87
GFT
506 struct jme_ring *txring = &(jme->txring[0]);
507
508 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
509 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
510 &(txring->dmaalloc),
511 GFP_ATOMIC);
fcf45b4c 512
0ede469c
GFT
513 if (!txring->alloc)
514 goto err_set_null;
d7699f87
GFT
515
516 /*
517 * 16 Bytes align
518 */
cd0ff491 519 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 520 RING_DESC_ALIGN);
4330c2f2 521 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 522 txring->next_to_use = 0;
cdcdc9eb 523 atomic_set(&txring->next_to_clean, 0);
b3821cc5 524 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 525
0ede469c
GFT
526 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
527 jme->tx_ring_size, GFP_ATOMIC);
528 if (unlikely(!(txring->bufinf)))
529 goto err_free_txring;
530
d7699f87 531 /*
b3821cc5 532 * Initialize Transmit Descriptors
d7699f87 533 */
b3821cc5 534 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 535 memset(txring->bufinf, 0,
b3821cc5 536 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT
537
538 return 0;
0ede469c
GFT
539
540err_free_txring:
541 dma_free_coherent(&(jme->pdev->dev),
542 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
543 txring->alloc,
544 txring->dmaalloc);
545
546err_set_null:
547 txring->desc = NULL;
548 txring->dmaalloc = 0;
549 txring->dma = 0;
550 txring->bufinf = NULL;
551
552 return -ENOMEM;
d7699f87
GFT
553}
554
3bf61c55
GFT
555static void
556jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
557{
558 int i;
559 struct jme_ring *txring = &(jme->txring[0]);
0ede469c 560 struct jme_buffer_info *txbi;
d7699f87 561
cd0ff491 562 if (txring->alloc) {
0ede469c
GFT
563 if (txring->bufinf) {
564 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
565 txbi = txring->bufinf + i;
566 if (txbi->skb) {
567 dev_kfree_skb(txbi->skb);
568 txbi->skb = NULL;
569 }
570 txbi->mapping = 0;
571 txbi->len = 0;
572 txbi->nr_desc = 0;
573 txbi->start_xmit = 0;
d7699f87 574 }
0ede469c 575 kfree(txring->bufinf);
d7699f87
GFT
576 }
577
578 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 579 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT
580 txring->alloc,
581 txring->dmaalloc);
3bf61c55
GFT
582
583 txring->alloc = NULL;
584 txring->desc = NULL;
585 txring->dmaalloc = 0;
586 txring->dma = 0;
0ede469c 587 txring->bufinf = NULL;
d7699f87 588 }
3bf61c55 589 txring->next_to_use = 0;
cdcdc9eb 590 atomic_set(&txring->next_to_clean, 0);
79ce639c 591 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
592}
593
cd0ff491 594static inline void
3bf61c55 595jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
596{
597 /*
598 * Select Queue 0
599 */
600 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 601 wmb();
d7699f87
GFT
602
603 /*
604 * Setup TX Queue 0 DMA Bass Address
605 */
fcf45b4c 606 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 607 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 608 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
609
610 /*
611 * Setup TX Descptor Count
612 */
b3821cc5 613 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT
614
615 /*
616 * Enable TX Engine
617 */
618 wmb();
4330c2f2
GFT
619 jwrite32(jme, JME_TXCS, jme->reg_txcs |
620 TXCS_SELECT_QUEUE0 |
621 TXCS_ENABLE);
d7699f87
GFT
622
623}
624
cd0ff491 625static inline void
29bdd921
GFT
626jme_restart_tx_engine(struct jme_adapter *jme)
627{
628 /*
629 * Restart TX Engine
630 */
631 jwrite32(jme, JME_TXCS, jme->reg_txcs |
632 TXCS_SELECT_QUEUE0 |
633 TXCS_ENABLE);
634}
635
cd0ff491 636static inline void
3bf61c55 637jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
638{
639 int i;
cd0ff491 640 u32 val;
d7699f87
GFT
641
642 /*
643 * Disable TX Engine
644 */
fcf45b4c 645 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 646 wmb();
d7699f87
GFT
647
648 val = jread32(jme, JME_TXCS);
cd0ff491 649 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 650 mdelay(1);
d7699f87 651 val = jread32(jme, JME_TXCS);
cd0ff491 652 rmb();
d7699f87
GFT
653 }
654
cd0ff491 655 if (!i)
937ef75a 656 pr_err("Disable TX engine timeout\n");
d7699f87
GFT
657}
658
3bf61c55
GFT
659static void
660jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 661{
0ede469c 662 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 663 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT
664 struct jme_buffer_info *rxbi = rxring->bufinf;
665 rxdesc += i;
666 rxbi += i;
667
668 rxdesc->dw[0] = 0;
669 rxdesc->dw[1] = 0;
3bf61c55 670 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
671 rxdesc->desc1.bufaddrl = cpu_to_le32(
672 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 673 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 674 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 675 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 676 wmb();
3bf61c55 677 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
678}
679
3bf61c55
GFT
680static int
681jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
682{
683 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 684 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 685 struct sk_buff *skb;
4330c2f2 686
79ce639c
GFT
687 skb = netdev_alloc_skb(jme->dev,
688 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 689 if (unlikely(!skb))
4330c2f2 690 return -ENOMEM;
3b70a6fa
GFT
691#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
692 skb->dev = jme->dev;
693#endif
3bf61c55 694
4330c2f2 695 rxbi->skb = skb;
3bf61c55 696 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT
697 rxbi->mapping = pci_map_page(jme->pdev,
698 virt_to_page(skb->data),
699 offset_in_page(skb->data),
700 rxbi->len,
701 PCI_DMA_FROMDEVICE);
4330c2f2
GFT
702
703 return 0;
704}
705
3bf61c55
GFT
706static void
707jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
708{
709 struct jme_ring *rxring = &(jme->rxring[0]);
710 struct jme_buffer_info *rxbi = rxring->bufinf;
711 rxbi += i;
712
cd0ff491 713 if (rxbi->skb) {
b3821cc5 714 pci_unmap_page(jme->pdev,
4330c2f2 715 rxbi->mapping,
3bf61c55 716 rxbi->len,
4330c2f2
GFT
717 PCI_DMA_FROMDEVICE);
718 dev_kfree_skb(rxbi->skb);
719 rxbi->skb = NULL;
720 rxbi->mapping = 0;
3bf61c55 721 rxbi->len = 0;
4330c2f2
GFT
722 }
723}
724
3bf61c55
GFT
725static void
726jme_free_rx_resources(struct jme_adapter *jme)
727{
728 int i;
729 struct jme_ring *rxring = &(jme->rxring[0]);
730
cd0ff491 731 if (rxring->alloc) {
0ede469c
GFT
732 if (rxring->bufinf) {
733 for (i = 0 ; i < jme->rx_ring_size ; ++i)
734 jme_free_rx_buf(jme, i);
735 kfree(rxring->bufinf);
736 }
3bf61c55
GFT
737
738 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 739 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT
740 rxring->alloc,
741 rxring->dmaalloc);
742 rxring->alloc = NULL;
743 rxring->desc = NULL;
744 rxring->dmaalloc = 0;
745 rxring->dma = 0;
0ede469c 746 rxring->bufinf = NULL;
3bf61c55
GFT
747 }
748 rxring->next_to_use = 0;
cdcdc9eb 749 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT
750}
751
752static int
753jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
754{
755 int i;
756 struct jme_ring *rxring = &(jme->rxring[0]);
757
758 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
759 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
760 &(rxring->dmaalloc),
761 GFP_ATOMIC);
0ede469c
GFT
762 if (!rxring->alloc)
763 goto err_set_null;
d7699f87
GFT
764
765 /*
766 * 16 Bytes align
767 */
cd0ff491 768 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 769 RING_DESC_ALIGN);
4330c2f2 770 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 771 rxring->next_to_use = 0;
cdcdc9eb 772 atomic_set(&rxring->next_to_clean, 0);
d7699f87 773
0ede469c
GFT
774 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
775 jme->rx_ring_size, GFP_ATOMIC);
776 if (unlikely(!(rxring->bufinf)))
777 goto err_free_rxring;
778
d7699f87
GFT
779 /*
780 * Initiallize Receive Descriptors
781 */
0ede469c
GFT
782 memset(rxring->bufinf, 0,
783 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT
784 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
785 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT
786 jme_free_rx_resources(jme);
787 return -ENOMEM;
788 }
d7699f87
GFT
789
790 jme_set_clean_rxdesc(jme, i);
791 }
792
d7699f87 793 return 0;
0ede469c
GFT
794
795err_free_rxring:
796 dma_free_coherent(&(jme->pdev->dev),
797 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
798 rxring->alloc,
799 rxring->dmaalloc);
800err_set_null:
801 rxring->desc = NULL;
802 rxring->dmaalloc = 0;
803 rxring->dma = 0;
804 rxring->bufinf = NULL;
805
806 return -ENOMEM;
d7699f87
GFT
807}
808
cd0ff491 809static inline void
3bf61c55 810jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 811{
d7699f87 812 /*
cd0ff491
GFT
813 * Select Queue 0
814 */
815 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
816 RXCS_QUEUESEL_Q0);
817 wmb();
818
819 /*
d7699f87
GFT
820 * Setup RX DMA Bass Address
821 */
0ede469c 822 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 823 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
0ede469c 824 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT
825
826 /*
b3821cc5 827 * Setup RX Descriptor Count
d7699f87 828 */
b3821cc5 829 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 830
3bf61c55 831 /*
d7699f87
GFT
832 * Setup Unicast Filter
833 */
834 jme_set_multi(jme->dev);
835
836 /*
837 * Enable RX Engine
838 */
839 wmb();
79ce639c 840 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
841 RXCS_QUEUESEL_Q0 |
842 RXCS_ENABLE |
843 RXCS_QST);
d7699f87
GFT
844}
845
cd0ff491 846static inline void
3bf61c55 847jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
848{
849 /*
3bf61c55 850 * Start RX Engine
4330c2f2 851 */
79ce639c 852 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
853 RXCS_QUEUESEL_Q0 |
854 RXCS_ENABLE |
855 RXCS_QST);
856}
857
cd0ff491 858static inline void
3bf61c55 859jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
860{
861 int i;
cd0ff491 862 u32 val;
d7699f87
GFT
863
864 /*
865 * Disable RX Engine
866 */
29bdd921 867 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 868 wmb();
d7699f87
GFT
869
870 val = jread32(jme, JME_RXCS);
cd0ff491 871 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 872 mdelay(1);
d7699f87 873 val = jread32(jme, JME_RXCS);
cd0ff491 874 rmb();
d7699f87
GFT
875 }
876
cd0ff491 877 if (!i)
937ef75a 878 pr_err("Disable RX engine timeout\n");
d7699f87
GFT
879
880}
881
192570e0 882static int
cd0ff491 883jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
192570e0 884{
cd0ff491 885 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT
886 return false;
887
0ede469c
GFT
888 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
889 == RXWBFLAG_TCPON)) {
890 if (flags & RXWBFLAG_IPV4)
7ca9ebee 891 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
0ede469c 892 return false;
192570e0
GFT
893 }
894
0ede469c
GFT
895 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
896 == RXWBFLAG_UDPON)) {
897 if (flags & RXWBFLAG_IPV4)
937ef75a 898 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
0ede469c 899 return false;
192570e0
GFT
900 }
901
0ede469c
GFT
902 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
903 == RXWBFLAG_IPV4)) {
937ef75a 904 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
0ede469c 905 return false;
192570e0
GFT
906 }
907
908 return true;
909}
910
3bf61c55 911static void
42b1055e 912jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 913{
d7699f87 914 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 915 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 916 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 917 struct sk_buff *skb;
3bf61c55 918 int framesize;
d7699f87 919
3bf61c55
GFT
920 rxdesc += idx;
921 rxbi += idx;
d7699f87 922
3bf61c55
GFT
923 skb = rxbi->skb;
924 pci_dma_sync_single_for_cpu(jme->pdev,
925 rxbi->mapping,
926 rxbi->len,
927 PCI_DMA_FROMDEVICE);
928
cd0ff491 929 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT
930 pci_dma_sync_single_for_device(jme->pdev,
931 rxbi->mapping,
932 rxbi->len,
933 PCI_DMA_FROMDEVICE);
934
935 ++(NET_STAT(jme).rx_dropped);
cd0ff491 936 } else {
3bf61c55
GFT
937 framesize = le16_to_cpu(rxdesc->descwb.framesize)
938 - RX_PREPAD_SIZE;
939
940 skb_reserve(skb, RX_PREPAD_SIZE);
941 skb_put(skb, framesize);
942 skb->protocol = eth_type_trans(skb, jme->dev);
943
3b70a6fa 944 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
8c198884 945 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 946 else
08f5fcfa 947#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
29bdd921 948 skb->ip_summed = CHECKSUM_NONE;
08f5fcfa
ED
949#else
950 skb_checksum_none_assert(skb);
951#endif
8c198884 952
3b70a6fa 953 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 954 if (jme->vlgrp) {
cdcdc9eb 955 jme->jme_vlan_rx(skb, jme->vlgrp,
3b70a6fa 956 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 957 NET_STAT(jme).rx_bytes += 4;
7ca9ebee 958 } else {
7ca9ebee 959 dev_kfree_skb(skb);
b3821cc5 960 }
cd0ff491 961 } else {
cdcdc9eb 962 jme->jme_rx(skb);
b3821cc5 963 }
3bf61c55 964
3b70a6fa
GFT
965 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
966 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT
967 ++(NET_STAT(jme).multicast);
968
3bf61c55
GFT
969 NET_STAT(jme).rx_bytes += framesize;
970 ++(NET_STAT(jme).rx_packets);
971 }
972
973 jme_set_clean_rxdesc(jme, idx);
974
975}
976
8c198884 977static int
3bf61c55
GFT
978jme_process_receive(struct jme_adapter *jme, int limit)
979{
980 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 981 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 982 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 983
cd0ff491 984 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT
985 goto out_inc;
986
cd0ff491 987 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT
988 goto out_inc;
989
cd0ff491 990 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT
991 goto out_inc;
992
cdcdc9eb 993 i = atomic_read(&rxring->next_to_clean);
0ede469c 994 while (limit > 0) {
3bf61c55
GFT
995 rxdesc = rxring->desc;
996 rxdesc += i;
997
3b70a6fa 998 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT
999 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1000 goto out;
0ede469c 1001 --limit;
d7699f87 1002
9134abda 1003 rmb();
4330c2f2
GFT
1004 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1005
cd0ff491 1006 if (unlikely(desccnt > 1 ||
192570e0 1007 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1008
cd0ff491 1009 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1010 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1011 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT
1012 ++(NET_STAT(jme).rx_fifo_errors);
1013 else
1014 ++(NET_STAT(jme).rx_errors);
4330c2f2 1015
cd0ff491 1016 if (desccnt > 1)
3bf61c55 1017 limit -= desccnt - 1;
4330c2f2 1018
cd0ff491 1019 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1020 jme_set_clean_rxdesc(jme, j);
b3821cc5 1021 j = (j + 1) & (mask);
4330c2f2 1022 }
3bf61c55 1023
cd0ff491 1024 } else {
42b1055e 1025 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1026 }
4330c2f2 1027
b3821cc5 1028 i = (i + desccnt) & (mask);
3bf61c55 1029 }
4330c2f2 1030
3bf61c55 1031out:
cdcdc9eb 1032 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1033
192570e0
GFT
1034out_inc:
1035 atomic_inc(&jme->rx_cleaning);
1036
3bf61c55 1037 return limit > 0 ? limit : 0;
4330c2f2 1038
3bf61c55 1039}
d7699f87 1040
3bf61c55 1041static void
79ce639c
GFT
1042jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1043{
cd0ff491 1044 if (likely(atmp == dpi->cur)) {
192570e0 1045 dpi->cnt = 0;
79ce639c 1046 return;
192570e0 1047 }
79ce639c 1048
cd0ff491 1049 if (dpi->attempt == atmp) {
79ce639c 1050 ++(dpi->cnt);
cd0ff491 1051 } else {
79ce639c
GFT
1052 dpi->attempt = atmp;
1053 dpi->cnt = 0;
1054 }
1055
1056}
1057
1058static void
1059jme_dynamic_pcc(struct jme_adapter *jme)
1060{
1061 register struct dynpcc_info *dpi = &(jme->dpi);
1062
cd0ff491 1063 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1064 jme_attempt_pcc(dpi, PCC_P3);
7ca9ebee
GFT
1065 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1066 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT
1067 jme_attempt_pcc(dpi, PCC_P2);
1068 else
1069 jme_attempt_pcc(dpi, PCC_P1);
1070
cd0ff491
GFT
1071 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1072 if (dpi->attempt < dpi->cur)
1073 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT
1074 jme_set_rx_pcc(jme, dpi->attempt);
1075 dpi->cur = dpi->attempt;
1076 dpi->cnt = 0;
1077 }
1078}
1079
1080static void
1081jme_start_pcc_timer(struct jme_adapter *jme)
1082{
1083 struct dynpcc_info *dpi = &(jme->dpi);
1084 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1085 dpi->last_pkts = NET_STAT(jme).rx_packets;
1086 dpi->intr_cnt = 0;
1087 jwrite32(jme, JME_TMCSR,
1088 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1089}
1090
cd0ff491 1091static inline void
29bdd921
GFT
1092jme_stop_pcc_timer(struct jme_adapter *jme)
1093{
1094 jwrite32(jme, JME_TMCSR, 0);
1095}
1096
1097static void
cd0ff491
GFT
1098jme_shutdown_nic(struct jme_adapter *jme)
1099{
1100 u32 phylink;
1101
1102 phylink = jme_linkstat_from_phy(jme);
1103
1104 if (!(phylink & PHY_LINK_UP)) {
1105 /*
1106 * Disable all interrupt before issue timer
1107 */
1108 jme_stop_irq(jme);
1109 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1110 }
1111}
1112
1113static void
79ce639c
GFT
1114jme_pcc_tasklet(unsigned long arg)
1115{
cd0ff491 1116 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT
1117 struct net_device *netdev = jme->dev;
1118
cd0ff491
GFT
1119 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1120 jme_shutdown_nic(jme);
1121 return;
1122 }
29bdd921 1123
cd0ff491 1124 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT
1125 (atomic_read(&jme->link_changing) != 1)
1126 )) {
1127 jme_stop_pcc_timer(jme);
79ce639c
GFT
1128 return;
1129 }
29bdd921 1130
cd0ff491 1131 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT
1132 jme_dynamic_pcc(jme);
1133
79ce639c
GFT
1134 jme_start_pcc_timer(jme);
1135}
1136
cd0ff491 1137static inline void
192570e0
GFT
1138jme_polling_mode(struct jme_adapter *jme)
1139{
1140 jme_set_rx_pcc(jme, PCC_OFF);
1141}
1142
cd0ff491 1143static inline void
192570e0
GFT
1144jme_interrupt_mode(struct jme_adapter *jme)
1145{
1146 jme_set_rx_pcc(jme, PCC_P1);
1147}
1148
cd0ff491
GFT
1149static inline int
1150jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1151{
1152 u32 apmc;
1153 apmc = jread32(jme, JME_APMC);
1154 return apmc & JME_APMC_PSEUDO_HP_EN;
1155}
1156
1157static void
1158jme_start_shutdown_timer(struct jme_adapter *jme)
1159{
1160 u32 apmc;
1161
1162 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1163 apmc &= ~JME_APMC_EPIEN_CTRL;
1164 if (!no_extplug) {
1165 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1166 wmb();
1167 }
1168 jwrite32f(jme, JME_APMC, apmc);
1169
1170 jwrite32f(jme, JME_TIMER2, 0);
1171 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1172 jwrite32(jme, JME_TMCSR,
1173 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1174}
1175
1176static void
1177jme_stop_shutdown_timer(struct jme_adapter *jme)
1178{
1179 u32 apmc;
1180
1181 jwrite32f(jme, JME_TMCSR, 0);
1182 jwrite32f(jme, JME_TIMER2, 0);
1183 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1184
1185 apmc = jread32(jme, JME_APMC);
1186 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1187 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1188 wmb();
1189 jwrite32f(jme, JME_APMC, apmc);
1190}
1191
79ce639c 1192static void
3bf61c55
GFT
1193jme_link_change_tasklet(unsigned long arg)
1194{
cd0ff491 1195 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1196 struct net_device *netdev = jme->dev;
fcf45b4c
GFT
1197 int rc;
1198
cd0ff491
GFT
1199 while (!atomic_dec_and_test(&jme->link_changing)) {
1200 atomic_inc(&jme->link_changing);
937ef75a 1201 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
58c92f28 1202 while (atomic_read(&jme->link_changing) != 1)
937ef75a 1203 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1204 }
fcf45b4c 1205
cd0ff491 1206 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1207 goto out;
1208
29bdd921 1209 jme->old_mtu = netdev->mtu;
fcf45b4c 1210 netif_stop_queue(netdev);
cd0ff491
GFT
1211 if (jme_pseudo_hotplug_enabled(jme))
1212 jme_stop_shutdown_timer(jme);
1213
1214 jme_stop_pcc_timer(jme);
1215 tasklet_disable(&jme->txclean_task);
1216 tasklet_disable(&jme->rxclean_task);
1217 tasklet_disable(&jme->rxempty_task);
1218
1219 if (netif_carrier_ok(netdev)) {
1220 jme_reset_ghc_speed(jme);
1221 jme_disable_rx_engine(jme);
1222 jme_disable_tx_engine(jme);
fcf45b4c
GFT
1223 jme_reset_mac_processor(jme);
1224 jme_free_rx_resources(jme);
1225 jme_free_tx_resources(jme);
192570e0 1226
cd0ff491 1227 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1228 jme_polling_mode(jme);
cd0ff491
GFT
1229
1230 netif_carrier_off(netdev);
fcf45b4c
GFT
1231 }
1232
1233 jme_check_link(netdev, 0);
cd0ff491 1234 if (netif_carrier_ok(netdev)) {
fcf45b4c 1235 rc = jme_setup_rx_resources(jme);
cd0ff491 1236 if (rc) {
937ef75a 1237 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1238 goto out_enable_tasklet;
fcf45b4c
GFT
1239 }
1240
fcf45b4c 1241 rc = jme_setup_tx_resources(jme);
cd0ff491 1242 if (rc) {
937ef75a 1243 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT
1244 goto err_out_free_rx_resources;
1245 }
1246
1247 jme_enable_rx_engine(jme);
1248 jme_enable_tx_engine(jme);
1249
1250 netif_start_queue(netdev);
192570e0 1251
cd0ff491 1252 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1253 jme_interrupt_mode(jme);
192570e0 1254
79ce639c 1255 jme_start_pcc_timer(jme);
cd0ff491
GFT
1256 } else if (jme_pseudo_hotplug_enabled(jme)) {
1257 jme_start_shutdown_timer(jme);
fcf45b4c
GFT
1258 }
1259
cd0ff491 1260 goto out_enable_tasklet;
fcf45b4c
GFT
1261
1262err_out_free_rx_resources:
1263 jme_free_rx_resources(jme);
cd0ff491
GFT
1264out_enable_tasklet:
1265 tasklet_enable(&jme->txclean_task);
1266 tasklet_hi_enable(&jme->rxclean_task);
1267 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT
1268out:
1269 atomic_inc(&jme->link_changing);
3bf61c55 1270}
d7699f87 1271
3bf61c55
GFT
1272static void
1273jme_rx_clean_tasklet(unsigned long arg)
1274{
cd0ff491 1275 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1276 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1277
192570e0
GFT
1278 jme_process_receive(jme, jme->rx_ring_size);
1279 ++(dpi->intr_cnt);
42b1055e 1280
192570e0 1281}
fcf45b4c 1282
192570e0 1283static int
cdcdc9eb 1284jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1285{
cdcdc9eb 1286 struct jme_adapter *jme = jme_napi_priv(holder);
3b70a6fa 1287 DECLARE_NETDEV
192570e0 1288 int rest;
fcf45b4c 1289
cdcdc9eb 1290 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1291
cd0ff491 1292 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1293 atomic_dec(&jme->rx_empty);
192570e0
GFT
1294 ++(NET_STAT(jme).rx_dropped);
1295 jme_restart_rx_engine(jme);
1296 }
1297 atomic_inc(&jme->rx_empty);
1298
cd0ff491 1299 if (rest) {
cdcdc9eb 1300 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT
1301 jme_interrupt_mode(jme);
1302 }
1303
cdcdc9eb
GFT
1304 JME_NAPI_WEIGHT_SET(budget, rest);
1305 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT
1306}
1307
1308static void
1309jme_rx_empty_tasklet(unsigned long arg)
1310{
cd0ff491 1311 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1312
cd0ff491 1313 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1314 return;
1315
cd0ff491 1316 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1317 return;
1318
7ca9ebee 1319 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1320
fcf45b4c 1321 jme_rx_clean_tasklet(arg);
cdcdc9eb 1322
cd0ff491 1323 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT
1324 atomic_dec(&jme->rx_empty);
1325 ++(NET_STAT(jme).rx_dropped);
1326 jme_restart_rx_engine(jme);
1327 }
1328 atomic_inc(&jme->rx_empty);
4330c2f2
GFT
1329}
1330
3bf61c55 1331static void
b3821cc5
GFT
1332jme_wake_queue_if_stopped(struct jme_adapter *jme)
1333{
0ede469c 1334 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1335
1336 smp_wmb();
cd0ff491 1337 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1338 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
937ef75a 1339 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1340 netif_wake_queue(jme->dev);
b3821cc5
GFT
1341 }
1342
1343}
1344
1345static void
3bf61c55 1346jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1347{
cd0ff491 1348 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1349 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1350 struct txdesc *txdesc = txring->desc;
3bf61c55 1351 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1352 int i, j, cnt = 0, max, err, mask;
3bf61c55 1353
937ef75a 1354 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT
1355
1356 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1357 goto out;
1358
cd0ff491 1359 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1360 goto out;
1361
cd0ff491 1362 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1363 goto out;
1364
b3821cc5
GFT
1365 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1366 mask = jme->tx_ring_mask;
3bf61c55 1367
cd0ff491 1368 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT
1369
1370 ctxbi = txbi + i;
1371
cd0ff491 1372 if (likely(ctxbi->skb &&
b3821cc5 1373 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1374
cd0ff491 1375 tx_dbg(jme, "txclean: %d+%d@%lu\n",
937ef75a 1376 i, ctxbi->nr_desc, jiffies);
3bf61c55 1377
cd0ff491 1378 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1379
cd0ff491 1380 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT
1381 ttxbi = txbi + ((i + j) & (mask));
1382 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1383
b3821cc5 1384 pci_unmap_page(jme->pdev,
3bf61c55
GFT
1385 ttxbi->mapping,
1386 ttxbi->len,
1387 PCI_DMA_TODEVICE);
1388
3bf61c55
GFT
1389 ttxbi->mapping = 0;
1390 ttxbi->len = 0;
1391 }
1392
1393 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT
1394
1395 cnt += ctxbi->nr_desc;
1396
cd0ff491 1397 if (unlikely(err)) {
8c198884 1398 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1399 } else {
8c198884 1400 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT
1401 NET_STAT(jme).tx_bytes += ctxbi->len;
1402 }
1403
1404 ctxbi->skb = NULL;
1405 ctxbi->len = 0;
cdcdc9eb 1406 ctxbi->start_xmit = 0;
cd0ff491
GFT
1407
1408 } else {
3bf61c55
GFT
1409 break;
1410 }
1411
b3821cc5 1412 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT
1413
1414 ctxbi->nr_desc = 0;
d7699f87
GFT
1415 }
1416
937ef75a 1417 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1418 atomic_set(&txring->next_to_clean, i);
79ce639c 1419 atomic_add(cnt, &txring->nr_free);
3bf61c55 1420
b3821cc5
GFT
1421 jme_wake_queue_if_stopped(jme);
1422
fcf45b4c
GFT
1423out:
1424 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1425}
1426
79ce639c 1427static void
cd0ff491 1428jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1429{
3bf61c55
GFT
1430 /*
1431 * Disable interrupt
1432 */
1433 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1434
cd0ff491 1435 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT
1436 /*
1437 * Link change event is critical
1438 * all other events are ignored
1439 */
1440 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1441 tasklet_schedule(&jme->linkch_task);
29bdd921 1442 goto out_reenable;
fcf45b4c 1443 }
d7699f87 1444
cd0ff491 1445 if (intrstat & INTR_TMINTR) {
47220951 1446 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1447 tasklet_schedule(&jme->pcc_task);
47220951 1448 }
79ce639c 1449
cd0ff491 1450 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1451 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1452 tasklet_schedule(&jme->txclean_task);
47220951
GFT
1453 }
1454
cd0ff491 1455 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT
1456 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1457 INTR_PCCRX0 |
1458 INTR_RX0EMP)) |
1459 INTR_RX0);
1460 }
d7699f87 1461
cd0ff491
GFT
1462 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1463 if (intrstat & INTR_RX0EMP)
192570e0
GFT
1464 atomic_inc(&jme->rx_empty);
1465
cd0ff491
GFT
1466 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1467 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1468 jme_polling_mode(jme);
cdcdc9eb 1469 JME_RX_SCHEDULE(jme);
192570e0
GFT
1470 }
1471 }
cd0ff491
GFT
1472 } else {
1473 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1474 atomic_inc(&jme->rx_empty);
cd0ff491
GFT
1475 tasklet_hi_schedule(&jme->rxempty_task);
1476 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1477 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1478 }
4330c2f2 1479 }
d7699f87 1480
29bdd921 1481out_reenable:
3bf61c55 1482 /*
fcf45b4c 1483 * Re-enable interrupt
3bf61c55 1484 */
fcf45b4c 1485 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT
1486}
1487
3b70a6fa
GFT
1488#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1489static irqreturn_t
1490jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1491#else
79ce639c
GFT
1492static irqreturn_t
1493jme_intr(int irq, void *dev_id)
3b70a6fa 1494#endif
79ce639c 1495{
cd0ff491
GFT
1496 struct net_device *netdev = dev_id;
1497 struct jme_adapter *jme = netdev_priv(netdev);
1498 u32 intrstat;
79ce639c
GFT
1499
1500 intrstat = jread32(jme, JME_IEVE);
1501
1502 /*
1503 * Check if it's really an interrupt for us
1504 */
7ee473a3 1505 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1506 return IRQ_NONE;
79ce639c
GFT
1507
1508 /*
1509 * Check if the device still exist
1510 */
cd0ff491
GFT
1511 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1512 return IRQ_NONE;
79ce639c
GFT
1513
1514 jme_intr_msi(jme, intrstat);
1515
cd0ff491 1516 return IRQ_HANDLED;
d7699f87
GFT
1517}
1518
3b70a6fa
GFT
1519#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1520static irqreturn_t
1521jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1522#else
79ce639c
GFT
1523static irqreturn_t
1524jme_msi(int irq, void *dev_id)
3b70a6fa 1525#endif
79ce639c 1526{
cd0ff491
GFT
1527 struct net_device *netdev = dev_id;
1528 struct jme_adapter *jme = netdev_priv(netdev);
1529 u32 intrstat;
79ce639c 1530
0ede469c 1531 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT
1532
1533 jme_intr_msi(jme, intrstat);
1534
cd0ff491 1535 return IRQ_HANDLED;
79ce639c
GFT
1536}
1537
79ce639c
GFT
1538static void
1539jme_reset_link(struct jme_adapter *jme)
1540{
1541 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1542}
1543
fcf45b4c
GFT
1544static void
1545jme_restart_an(struct jme_adapter *jme)
1546{
cd0ff491 1547 u32 bmcr;
fcf45b4c 1548
cd0ff491 1549 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT
1550 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1551 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1552 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1553 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT
1554}
1555
1556static int
1557jme_request_irq(struct jme_adapter *jme)
1558{
1559 int rc;
cd0ff491 1560 struct net_device *netdev = jme->dev;
3b70a6fa
GFT
1561#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1562 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1563 int irq_flags = SA_SHIRQ;
1564#else
cd0ff491
GFT
1565 irq_handler_t handler = jme_intr;
1566 int irq_flags = IRQF_SHARED;
3b70a6fa 1567#endif
cd0ff491
GFT
1568
1569 if (!pci_enable_msi(jme->pdev)) {
1570 set_bit(JME_FLAG_MSI, &jme->flags);
1571 handler = jme_msi;
1572 irq_flags = 0;
1573 }
1574
1575 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1576 netdev);
1577 if (rc) {
937ef75a
JP
1578 netdev_err(netdev,
1579 "Unable to request %s interrupt (return: %d)\n",
1580 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1581 rc);
79ce639c 1582
cd0ff491
GFT
1583 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1584 pci_disable_msi(jme->pdev);
1585 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1586 }
cd0ff491 1587 } else {
79ce639c
GFT
1588 netdev->irq = jme->pdev->irq;
1589 }
1590
cd0ff491 1591 return rc;
79ce639c
GFT
1592}
1593
1594static void
1595jme_free_irq(struct jme_adapter *jme)
1596{
cd0ff491
GFT
1597 free_irq(jme->pdev->irq, jme->dev);
1598 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1599 pci_disable_msi(jme->pdev);
1600 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1601 jme->dev->irq = jme->pdev->irq;
cd0ff491 1602 }
fcf45b4c
GFT
1603}
1604
e58b908e
GFT
1605static inline void
1606jme_phy_on(struct jme_adapter *jme)
1607{
1608 u32 bmcr;
1609
1610 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1611 bmcr &= ~BMCR_PDOWN;
1612 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1613}
1614
3bf61c55
GFT
1615static int
1616jme_open(struct net_device *netdev)
d7699f87
GFT
1617{
1618 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1619 int rc;
79ce639c 1620
42b1055e 1621 jme_clear_pm(jme);
cdcdc9eb 1622 JME_NAPI_ENABLE(jme);
d7699f87 1623
0ede469c 1624 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT
1625 tasklet_enable(&jme->txclean_task);
1626 tasklet_hi_enable(&jme->rxclean_task);
1627 tasklet_hi_enable(&jme->rxempty_task);
1628
79ce639c 1629 rc = jme_request_irq(jme);
cd0ff491 1630 if (rc)
4330c2f2 1631 goto err_out;
79ce639c 1632
d7699f87 1633 jme_start_irq(jme);
42b1055e 1634
e58b908e
GFT
1635 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1636 jme_phy_on(jme);
42b1055e 1637 jme_set_settings(netdev, &jme->old_ecmd);
e58b908e 1638 } else {
42b1055e 1639 jme_reset_phy_processor(jme);
e58b908e 1640 }
42b1055e 1641
29bdd921 1642 jme_reset_link(jme);
d7699f87
GFT
1643
1644 return 0;
1645
d7699f87
GFT
1646err_out:
1647 netif_stop_queue(netdev);
1648 netif_carrier_off(netdev);
4330c2f2 1649 return rc;
d7699f87
GFT
1650}
1651
7ee473a3 1652#ifdef CONFIG_PM
42b1055e
GFT
1653static void
1654jme_set_100m_half(struct jme_adapter *jme)
1655{
cd0ff491 1656 u32 bmcr, tmp;
42b1055e
GFT
1657
1658 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1659 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1660 BMCR_SPEED1000 | BMCR_FULLDPLX);
1661 tmp |= BMCR_SPEED100;
1662
1663 if (bmcr != tmp)
1664 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1665
cd0ff491 1666 if (jme->fpgaver)
cdcdc9eb
GFT
1667 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1668 else
1669 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT
1670}
1671
47220951
GFT
1672#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1673static void
1674jme_wait_link(struct jme_adapter *jme)
1675{
cd0ff491 1676 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT
1677
1678 mdelay(1000);
1679 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1680 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT
1681 mdelay(10);
1682 phylink = jme_linkstat_from_phy(jme);
1683 }
1684}
7ee473a3 1685#endif
47220951 1686
cd0ff491 1687static inline void
42b1055e
GFT
1688jme_phy_off(struct jme_adapter *jme)
1689{
1690 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1691}
1692
3bf61c55
GFT
1693static int
1694jme_close(struct net_device *netdev)
d7699f87
GFT
1695{
1696 struct jme_adapter *jme = netdev_priv(netdev);
1697
1698 netif_stop_queue(netdev);
1699 netif_carrier_off(netdev);
1700
1701 jme_stop_irq(jme);
79ce639c 1702 jme_free_irq(jme);
d7699f87 1703
cdcdc9eb 1704 JME_NAPI_DISABLE(jme);
192570e0 1705
0ede469c
GFT
1706 tasklet_disable(&jme->linkch_task);
1707 tasklet_disable(&jme->txclean_task);
1708 tasklet_disable(&jme->rxclean_task);
1709 tasklet_disable(&jme->rxempty_task);
8c198884 1710
cd0ff491
GFT
1711 jme_reset_ghc_speed(jme);
1712 jme_disable_rx_engine(jme);
1713 jme_disable_tx_engine(jme);
8c198884 1714 jme_reset_mac_processor(jme);
d7699f87
GFT
1715 jme_free_rx_resources(jme);
1716 jme_free_tx_resources(jme);
42b1055e 1717 jme->phylink = 0;
b3821cc5
GFT
1718 jme_phy_off(jme);
1719
1720 return 0;
1721}
1722
1723static int
1724jme_alloc_txdesc(struct jme_adapter *jme,
1725 struct sk_buff *skb)
1726{
0ede469c 1727 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1728 int idx, nr_alloc, mask = jme->tx_ring_mask;
1729
1730 idx = txring->next_to_use;
1731 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1732
cd0ff491 1733 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT
1734 return -1;
1735
1736 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1737
b3821cc5
GFT
1738 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1739
1740 return idx;
1741}
1742
1743static void
1744jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1745 struct txdesc *txdesc,
b3821cc5
GFT
1746 struct jme_buffer_info *txbi,
1747 struct page *page,
cd0ff491
GFT
1748 u32 page_offset,
1749 u32 len,
1750 u8 hidma)
b3821cc5
GFT
1751{
1752 dma_addr_t dmaaddr;
1753
1754 dmaaddr = pci_map_page(pdev,
1755 page,
1756 page_offset,
1757 len,
1758 PCI_DMA_TODEVICE);
1759
1760 pci_dma_sync_single_for_device(pdev,
1761 dmaaddr,
1762 len,
1763 PCI_DMA_TODEVICE);
1764
1765 txdesc->dw[0] = 0;
1766 txdesc->dw[1] = 0;
1767 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1768 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT
1769 txdesc->desc2.datalen = cpu_to_le16(len);
1770 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1771 txdesc->desc2.bufaddrl = cpu_to_le32(
1772 (__u64)dmaaddr & 0xFFFFFFFFUL);
1773
1774 txbi->mapping = dmaaddr;
1775 txbi->len = len;
1776}
1777
1778static void
1779jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1780{
0ede469c 1781 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1782 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1783 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1784 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT
1785 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1786 int mask = jme->tx_ring_mask;
1787 struct skb_frag_struct *frag;
cd0ff491 1788 u32 len;
b3821cc5 1789
cd0ff491
GFT
1790 for (i = 0 ; i < nr_frags ; ++i) {
1791 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT
1792 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1793 ctxbi = txbi + ((idx + i + 2) & (mask));
1794
1795 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1796 frag->page_offset, frag->size, hidma);
42b1055e 1797 }
b3821cc5 1798
cd0ff491 1799 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT
1800 ctxdesc = txdesc + ((idx + 1) & (mask));
1801 ctxbi = txbi + ((idx + 1) & (mask));
1802 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1803 offset_in_page(skb->data), len, hidma);
1804
1805}
1806
1807static int
1808jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1809{
3b70a6fa 1810 if (unlikely(
0ede469c 1811#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT
1812 skb_shinfo(skb)->tso_size
1813#else
1814 skb_shinfo(skb)->gso_size
1815#endif
1816 && skb_header_cloned(skb) &&
b3821cc5
GFT
1817 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1818 dev_kfree_skb(skb);
1819 return -1;
1820 }
1821
1822 return 0;
1823}
1824
1825static int
3b70a6fa 1826jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1827{
0ede469c 1828#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT
1829 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1830#else
1831 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1832#endif
cd0ff491 1833 if (*mss) {
b3821cc5
GFT
1834 *flags |= TXFLAG_LSEN;
1835
cd0ff491 1836 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT
1837 struct iphdr *iph = ip_hdr(skb);
1838
1839 iph->check = 0;
cd0ff491 1840 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT
1841 iph->daddr, 0,
1842 IPPROTO_TCP,
1843 0);
cd0ff491 1844 } else {
b3821cc5
GFT
1845 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1846
cd0ff491 1847 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT
1848 &ip6h->daddr, 0,
1849 IPPROTO_TCP,
1850 0);
1851 }
1852
1853 return 0;
1854 }
1855
1856 return 1;
1857}
1858
1859static void
cd0ff491 1860jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1861{
3b70a6fa
GFT
1862#ifdef CHECKSUM_PARTIAL
1863 if (skb->ip_summed == CHECKSUM_PARTIAL)
1864#else
1865 if (skb->ip_summed == CHECKSUM_HW)
1866#endif
1867 {
cd0ff491 1868 u8 ip_proto;
b3821cc5 1869
3b70a6fa
GFT
1870#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1871 if (skb->protocol == htons(ETH_P_IP))
1872 ip_proto = ip_hdr(skb)->protocol;
1873 else if (skb->protocol == htons(ETH_P_IPV6))
1874 ip_proto = ipv6_hdr(skb)->nexthdr;
1875 else
1876 ip_proto = 0;
1877#else
b3821cc5 1878 switch (skb->protocol) {
cd0ff491 1879 case htons(ETH_P_IP):
b3821cc5
GFT
1880 ip_proto = ip_hdr(skb)->protocol;
1881 break;
cd0ff491 1882 case htons(ETH_P_IPV6):
b3821cc5
GFT
1883 ip_proto = ipv6_hdr(skb)->nexthdr;
1884 break;
1885 default:
1886 ip_proto = 0;
1887 break;
1888 }
3b70a6fa 1889#endif
b3821cc5 1890
cd0ff491 1891 switch (ip_proto) {
b3821cc5
GFT
1892 case IPPROTO_TCP:
1893 *flags |= TXFLAG_TCPCS;
1894 break;
1895 case IPPROTO_UDP:
1896 *flags |= TXFLAG_UDPCS;
1897 break;
1898 default:
937ef75a 1899 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT
1900 break;
1901 }
1902 }
1903}
1904
cd0ff491 1905static inline void
3b70a6fa 1906jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 1907{
cd0ff491 1908 if (vlan_tx_tag_present(skb)) {
b3821cc5 1909 *flags |= TXFLAG_TAGON;
3b70a6fa 1910 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 1911 }
b3821cc5
GFT
1912}
1913
1914static int
3b70a6fa 1915jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 1916{
0ede469c 1917 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1918 struct txdesc *txdesc;
b3821cc5 1919 struct jme_buffer_info *txbi;
cd0ff491 1920 u8 flags;
b3821cc5 1921
cd0ff491 1922 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT
1923 txbi = txring->bufinf + idx;
1924
1925 txdesc->dw[0] = 0;
1926 txdesc->dw[1] = 0;
1927 txdesc->dw[2] = 0;
1928 txdesc->dw[3] = 0;
1929 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1930 /*
1931 * Set OWN bit at final.
1932 * When kernel transmit faster than NIC.
1933 * And NIC trying to send this descriptor before we tell
1934 * it to start sending this TX queue.
1935 * Other fields are already filled correctly.
1936 */
1937 wmb();
1938 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT
1939 /*
1940 * Set checksum flags while not tso
1941 */
1942 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1943 jme_tx_csum(jme, skb, &flags);
b3821cc5 1944 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
3b70a6fa 1945 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT
1946 txdesc->desc1.flags = flags;
1947 /*
1948 * Set tx buffer info after telling NIC to send
1949 * For better tx_clean timing
1950 */
1951 wmb();
1952 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1953 txbi->skb = skb;
1954 txbi->len = skb->len;
cd0ff491
GFT
1955 txbi->start_xmit = jiffies;
1956 if (!txbi->start_xmit)
8d27293f 1957 txbi->start_xmit = (0UL-1);
d7699f87
GFT
1958
1959 return 0;
1960}
1961
b3821cc5
GFT
1962static void
1963jme_stop_queue_if_full(struct jme_adapter *jme)
1964{
0ede469c 1965 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT
1966 struct jme_buffer_info *txbi = txring->bufinf;
1967 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 1968
cd0ff491 1969 txbi += idx;
b3821cc5
GFT
1970
1971 smp_wmb();
cd0ff491 1972 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 1973 netif_stop_queue(jme->dev);
937ef75a 1974 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 1975 smp_wmb();
cd0ff491
GFT
1976 if (atomic_read(&txring->nr_free)
1977 >= (jme->tx_wake_threshold)) {
b3821cc5 1978 netif_wake_queue(jme->dev);
937ef75a 1979 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT
1980 }
1981 }
1982
cd0ff491 1983 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT
1984 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1985 txbi->skb)) {
1986 netif_stop_queue(jme->dev);
937ef75a 1987 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 1988 }
b3821cc5
GFT
1989}
1990
3bf61c55
GFT
1991/*
1992 * This function is already protected by netif_tx_lock()
1993 */
cd0ff491 1994
7ca9ebee 1995#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
3bf61c55 1996static int
7ca9ebee
GFT
1997#else
1998static netdev_tx_t
1999#endif
3bf61c55 2000jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2001{
cd0ff491 2002 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2003 int idx;
d7699f87 2004
cd0ff491 2005 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT
2006 ++(NET_STAT(jme).tx_dropped);
2007 return NETDEV_TX_OK;
2008 }
2009
2010 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2011
cd0ff491 2012 if (unlikely(idx < 0)) {
b3821cc5 2013 netif_stop_queue(netdev);
937ef75a
JP
2014 netif_err(jme, tx_err, jme->dev,
2015 "BUG! Tx ring full when queue awake!\n");
d7699f87 2016
cd0ff491 2017 return NETDEV_TX_BUSY;
b3821cc5
GFT
2018 }
2019
3b70a6fa 2020 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2021
4330c2f2
GFT
2022 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2023 TXCS_SELECT_QUEUE0 |
2024 TXCS_QUEUE0S |
2025 TXCS_ENABLE);
0ede469c 2026#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
d7699f87 2027 netdev->trans_start = jiffies;
0ede469c 2028#endif
d7699f87 2029
937ef75a
JP
2030 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2031 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT
2032 jme_stop_queue_if_full(jme);
2033
cd0ff491 2034 return NETDEV_TX_OK;
d7699f87
GFT
2035}
2036
3bf61c55
GFT
2037static int
2038jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2039{
cd0ff491 2040 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2041 struct sockaddr *addr = p;
cd0ff491 2042 u32 val;
d7699f87 2043
cd0ff491 2044 if (netif_running(netdev))
d7699f87
GFT
2045 return -EBUSY;
2046
cd0ff491 2047 spin_lock_bh(&jme->macaddr_lock);
d7699f87
GFT
2048 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2049
186fc259
GFT
2050 val = (addr->sa_data[3] & 0xff) << 24 |
2051 (addr->sa_data[2] & 0xff) << 16 |
2052 (addr->sa_data[1] & 0xff) << 8 |
2053 (addr->sa_data[0] & 0xff);
4330c2f2 2054 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT
2055 val = (addr->sa_data[5] & 0xff) << 8 |
2056 (addr->sa_data[4] & 0xff);
4330c2f2 2057 jwrite32(jme, JME_RXUMA_HI, val);
cd0ff491 2058 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT
2059
2060 return 0;
2061}
2062
3bf61c55
GFT
2063static void
2064jme_set_multi(struct net_device *netdev)
d7699f87 2065{
3bf61c55 2066 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2067 u32 mc_hash[2] = {};
7ca9ebee 2068#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
d7699f87 2069 int i;
7ca9ebee 2070#endif
d7699f87 2071
cd0ff491 2072 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT
2073
2074 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2075
cd0ff491 2076 if (netdev->flags & IFF_PROMISC) {
8c198884 2077 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2078 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2079 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2080 } else if (netdev->flags & IFF_MULTICAST) {
8e14c278 2081#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
3bf61c55 2082 struct dev_mc_list *mclist;
8e14c278
JP
2083#else
2084 struct netdev_hw_addr *ha;
2085#endif
3bf61c55 2086 int bit_nr;
d7699f87 2087
8c198884 2088 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
7ca9ebee 2089#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
3bf61c55
GFT
2090 for (i = 0, mclist = netdev->mc_list;
2091 mclist && i < netdev->mc_count;
2092 ++i, mclist = mclist->next) {
8e14c278 2093#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
7ca9ebee 2094 netdev_for_each_mc_addr(mclist, netdev) {
8e14c278
JP
2095#else
2096 netdev_for_each_mc_addr(ha, netdev) {
7ca9ebee 2097#endif
8e14c278 2098#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
cd0ff491 2099 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
8e14c278
JP
2100#else
2101 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2102#endif
cd0ff491
GFT
2103 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2104 }
d7699f87 2105
4330c2f2
GFT
2106 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2107 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
2108 }
2109
d7699f87 2110 wmb();
8c198884
GFT
2111 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2112
cd0ff491 2113 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT
2114}
2115
3bf61c55 2116static int
8c198884 2117jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2118{
cd0ff491 2119 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2120
cd0ff491 2121 if (new_mtu == jme->old_mtu)
29bdd921
GFT
2122 return 0;
2123
cd0ff491
GFT
2124 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2125 ((new_mtu) < IPV6_MIN_MTU))
2126 return -EINVAL;
79ce639c 2127
cd0ff491 2128 if (new_mtu > 4000) {
79ce639c
GFT
2129 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2130 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2131 jme_restart_rx_engine(jme);
cd0ff491 2132 } else {
79ce639c
GFT
2133 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2134 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2135 jme_restart_rx_engine(jme);
2136 }
2137
cd0ff491 2138 if (new_mtu > 1900) {
b3821cc5 2139 netdev->features &= ~(NETIF_F_HW_CSUM |
3b70a6fa
GFT
2140 NETIF_F_TSO
2141#ifdef NETIF_F_TSO6
2142 | NETIF_F_TSO6
2143#endif
2144 );
cd0ff491
GFT
2145 } else {
2146 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
b3821cc5 2147 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491 2148 if (test_bit(JME_FLAG_TSO, &jme->flags))
3b70a6fa
GFT
2149 netdev->features |= NETIF_F_TSO
2150#ifdef NETIF_F_TSO6
2151 | NETIF_F_TSO6
2152#endif
2153 ;
79ce639c
GFT
2154 }
2155
cd0ff491
GFT
2156 netdev->mtu = new_mtu;
2157 jme_reset_link(jme);
79ce639c
GFT
2158
2159 return 0;
d7699f87
GFT
2160}
2161
3bf61c55 2162static void
8c198884
GFT
2163jme_tx_timeout(struct net_device *netdev)
2164{
cd0ff491 2165 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2166
cdcdc9eb
GFT
2167 jme->phylink = 0;
2168 jme_reset_phy_processor(jme);
cd0ff491 2169 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT
2170 jme_set_settings(netdev, &jme->old_ecmd);
2171
8c198884 2172 /*
cdcdc9eb 2173 * Force to Reset the link again
8c198884 2174 */
29bdd921 2175 jme_reset_link(jme);
8c198884
GFT
2176}
2177
1e5ebebc
GFT
2178static inline void jme_pause_rx(struct jme_adapter *jme)
2179{
2180 atomic_dec(&jme->link_changing);
2181
2182 jme_set_rx_pcc(jme, PCC_OFF);
2183 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2184 JME_NAPI_DISABLE(jme);
2185 } else {
2186 tasklet_disable(&jme->rxclean_task);
2187 tasklet_disable(&jme->rxempty_task);
2188 }
2189}
2190
2191static inline void jme_resume_rx(struct jme_adapter *jme)
2192{
2193 struct dynpcc_info *dpi = &(jme->dpi);
2194
2195 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2196 JME_NAPI_ENABLE(jme);
2197 } else {
2198 tasklet_hi_enable(&jme->rxclean_task);
2199 tasklet_hi_enable(&jme->rxempty_task);
2200 }
2201 dpi->cur = PCC_P1;
2202 dpi->attempt = PCC_P1;
2203 dpi->cnt = 0;
2204 jme_set_rx_pcc(jme, PCC_P1);
2205
2206 atomic_inc(&jme->link_changing);
2207}
2208
8c198884 2209static void
42b1055e
GFT
2210jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2211{
2212 struct jme_adapter *jme = netdev_priv(netdev);
2213
1e5ebebc 2214 jme_pause_rx(jme);
42b1055e 2215 jme->vlgrp = grp;
1e5ebebc 2216 jme_resume_rx(jme);
42b1055e
GFT
2217}
2218
7ca9ebee
GFT
2219#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2220static void
2221jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2222{
2223 struct jme_adapter *jme = netdev_priv(netdev);
2224
7ca9ebee 2225 if(jme->vlgrp) {
1e5ebebc 2226 jme_pause_rx(jme);
7ca9ebee
GFT
2227#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2228 jme->vlgrp->vlan_devices[vid] = NULL;
2229#else
2230 vlan_group_set_device(jme->vlgrp, vid, NULL);
2231#endif
1e5ebebc 2232 jme_resume_rx(jme);
7ca9ebee 2233 }
7ca9ebee
GFT
2234}
2235#endif
2236
42b1055e 2237static void
3bf61c55
GFT
2238jme_get_drvinfo(struct net_device *netdev,
2239 struct ethtool_drvinfo *info)
d7699f87 2240{
cd0ff491 2241 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2242
cd0ff491
GFT
2243 strcpy(info->driver, DRV_NAME);
2244 strcpy(info->version, DRV_VERSION);
2245 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT
2246}
2247
3bf61c55 2248static int
8c198884
GFT
2249jme_get_regs_len(struct net_device *netdev)
2250{
cd0ff491 2251 return JME_REG_LEN;
8c198884
GFT
2252}
2253
2254static void
cd0ff491 2255mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT
2256{
2257 int i;
2258
cd0ff491 2259 for (i = 0 ; i < len ; i += 4)
79ce639c 2260 p[i >> 2] = jread32(jme, reg + i);
186fc259 2261}
8c198884 2262
186fc259 2263static void
cd0ff491 2264mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT
2265{
2266 int i;
cd0ff491 2267 u16 *p16 = (u16 *)p;
186fc259 2268
cd0ff491 2269 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2270 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT
2271}
2272
2273static void
2274jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2275{
cd0ff491
GFT
2276 struct jme_adapter *jme = netdev_priv(netdev);
2277 u32 *p32 = (u32 *)p;
8c198884 2278
186fc259 2279 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT
2280
2281 regs->version = 1;
2282 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2283
2284 p32 += 0x100 >> 2;
2285 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2286
2287 p32 += 0x100 >> 2;
2288 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2289
2290 p32 += 0x100 >> 2;
2291 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2292
186fc259
GFT
2293 p32 += 0x100 >> 2;
2294 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT
2295}
2296
2297static int
2298jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2299{
2300 struct jme_adapter *jme = netdev_priv(netdev);
2301
8c198884
GFT
2302 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2303 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2304
cd0ff491 2305 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT
2306 ecmd->use_adaptive_rx_coalesce = false;
2307 ecmd->rx_coalesce_usecs = 0;
2308 ecmd->rx_max_coalesced_frames = 0;
2309 return 0;
2310 }
2311
2312 ecmd->use_adaptive_rx_coalesce = true;
2313
cd0ff491 2314 switch (jme->dpi.cur) {
8c198884
GFT
2315 case PCC_P1:
2316 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2317 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2318 break;
2319 case PCC_P2:
2320 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2321 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2322 break;
2323 case PCC_P3:
2324 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2325 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2326 break;
2327 default:
2328 break;
2329 }
2330
2331 return 0;
2332}
2333
192570e0
GFT
2334static int
2335jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2336{
2337 struct jme_adapter *jme = netdev_priv(netdev);
2338 struct dynpcc_info *dpi = &(jme->dpi);
2339
cd0ff491 2340 if (netif_running(netdev))
cdcdc9eb
GFT
2341 return -EBUSY;
2342
7ca9ebee
GFT
2343 if (ecmd->use_adaptive_rx_coalesce &&
2344 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2345 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2346 jme->jme_rx = netif_rx;
2347 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT
2348 dpi->cur = PCC_P1;
2349 dpi->attempt = PCC_P1;
2350 dpi->cnt = 0;
2351 jme_set_rx_pcc(jme, PCC_P1);
2352 jme_interrupt_mode(jme);
7ca9ebee
GFT
2353 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2354 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2355 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2356 jme->jme_rx = netif_receive_skb;
2357 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT
2358 jme_interrupt_mode(jme);
2359 }
2360
2361 return 0;
2362}
2363
8c198884
GFT
2364static void
2365jme_get_pauseparam(struct net_device *netdev,
2366 struct ethtool_pauseparam *ecmd)
2367{
2368 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2369 u32 val;
8c198884
GFT
2370
2371 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2372 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2373
cd0ff491
GFT
2374 spin_lock_bh(&jme->phy_lock);
2375 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2376 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT
2377
2378 ecmd->autoneg =
2379 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT
2380}
2381
2382static int
2383jme_set_pauseparam(struct net_device *netdev,
2384 struct ethtool_pauseparam *ecmd)
2385{
2386 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2387 u32 val;
8c198884 2388
cd0ff491 2389 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT
2390 (ecmd->tx_pause != 0)) {
2391
cd0ff491 2392 if (ecmd->tx_pause)
8c198884
GFT
2393 jme->reg_txpfc |= TXPFC_PF_EN;
2394 else
2395 jme->reg_txpfc &= ~TXPFC_PF_EN;
2396
2397 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2398 }
2399
cd0ff491
GFT
2400 spin_lock_bh(&jme->rxmcs_lock);
2401 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT
2402 (ecmd->rx_pause != 0)) {
2403
cd0ff491 2404 if (ecmd->rx_pause)
8c198884
GFT
2405 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2406 else
2407 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2408
2409 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2410 }
cd0ff491 2411 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2412
cd0ff491
GFT
2413 spin_lock_bh(&jme->phy_lock);
2414 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2415 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT
2416 (ecmd->autoneg != 0)) {
2417
cd0ff491 2418 if (ecmd->autoneg)
8c198884
GFT
2419 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2420 else
2421 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2422
b3821cc5
GFT
2423 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2424 MII_ADVERTISE, val);
8c198884 2425 }
cd0ff491 2426 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT
2427
2428 return 0;
2429}
2430
29bdd921
GFT
2431static void
2432jme_get_wol(struct net_device *netdev,
2433 struct ethtool_wolinfo *wol)
2434{
2435 struct jme_adapter *jme = netdev_priv(netdev);
2436
2437 wol->supported = WAKE_MAGIC | WAKE_PHY;
2438
2439 wol->wolopts = 0;
2440
cd0ff491 2441 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT
2442 wol->wolopts |= WAKE_PHY;
2443
cd0ff491 2444 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT
2445 wol->wolopts |= WAKE_MAGIC;
2446
2447}
2448
2449static int
2450jme_set_wol(struct net_device *netdev,
2451 struct ethtool_wolinfo *wol)
2452{
2453 struct jme_adapter *jme = netdev_priv(netdev);
2454
cd0ff491 2455 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT
2456 WAKE_UCAST |
2457 WAKE_MCAST |
2458 WAKE_BCAST |
2459 WAKE_ARP))
2460 return -EOPNOTSUPP;
2461
2462 jme->reg_pmcs = 0;
2463
cd0ff491 2464 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT
2465 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2466
cd0ff491 2467 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT
2468 jme->reg_pmcs |= PMCS_MFEN;
2469
cd0ff491 2470 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2471
29bdd921
GFT
2472 return 0;
2473}
b3821cc5 2474
8c198884 2475static int
3bf61c55
GFT
2476jme_get_settings(struct net_device *netdev,
2477 struct ethtool_cmd *ecmd)
d7699f87
GFT
2478{
2479 struct jme_adapter *jme = netdev_priv(netdev);
2480 int rc;
8c198884 2481
cd0ff491 2482 spin_lock_bh(&jme->phy_lock);
d7699f87 2483 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2484 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT
2485 return rc;
2486}
2487
3bf61c55
GFT
2488static int
2489jme_set_settings(struct net_device *netdev,
2490 struct ethtool_cmd *ecmd)
d7699f87
GFT
2491{
2492 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2493 int rc, fdc = 0;
fcf45b4c 2494
cd0ff491 2495 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT
2496 return -EINVAL;
2497
e6b41b51
GFT
2498 /*
2499 * Check If user changed duplex only while force_media.
2500 * Hardware would not generate link change interrupt.
2501 */
cd0ff491 2502 if (jme->mii_if.force_media &&
79ce639c
GFT
2503 ecmd->autoneg != AUTONEG_ENABLE &&
2504 (jme->mii_if.full_duplex != ecmd->duplex))
2505 fdc = 1;
2506
cd0ff491 2507 spin_lock_bh(&jme->phy_lock);
d7699f87 2508 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2509 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2510
cd0ff491 2511 if (!rc) {
e6b41b51
GFT
2512 if (fdc)
2513 jme_reset_link(jme);
29bdd921 2514 jme->old_ecmd = *ecmd;
aa1e7189
GFT
2515 set_bit(JME_FLAG_SSET, &jme->flags);
2516 }
2517
2518 return rc;
2519}
2520
2521static int
2522jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2523{
2524 int rc;
2525 struct jme_adapter *jme = netdev_priv(netdev);
2526 struct mii_ioctl_data *mii_data = if_mii(rq);
2527 unsigned int duplex_chg;
2528
2529 if (cmd == SIOCSMIIREG) {
2530 u16 val = mii_data->val_in;
2531 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2532 (val & BMCR_SPEED1000))
2533 return -EINVAL;
2534 }
2535
2536 spin_lock_bh(&jme->phy_lock);
2537 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2538 spin_unlock_bh(&jme->phy_lock);
2539
2540 if (!rc && (cmd == SIOCSMIIREG)) {
2541 if (duplex_chg)
2542 jme_reset_link(jme);
2543 jme_get_settings(netdev, &jme->old_ecmd);
2544 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT
2545 }
2546
d7699f87
GFT
2547 return rc;
2548}
2549
cd0ff491 2550static u32
3bf61c55
GFT
2551jme_get_link(struct net_device *netdev)
2552{
d7699f87
GFT
2553 struct jme_adapter *jme = netdev_priv(netdev);
2554 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2555}
2556
8c198884 2557static u32
cd0ff491
GFT
2558jme_get_msglevel(struct net_device *netdev)
2559{
2560 struct jme_adapter *jme = netdev_priv(netdev);
2561 return jme->msg_enable;
2562}
2563
2564static void
2565jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2566{
cd0ff491
GFT
2567 struct jme_adapter *jme = netdev_priv(netdev);
2568 jme->msg_enable = value;
2569}
8c198884 2570
cd0ff491
GFT
2571static u32
2572jme_get_rx_csum(struct net_device *netdev)
2573{
2574 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2575 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2576}
2577
2578static int
2579jme_set_rx_csum(struct net_device *netdev, u32 on)
2580{
cd0ff491 2581 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2582
cd0ff491
GFT
2583 spin_lock_bh(&jme->rxmcs_lock);
2584 if (on)
8c198884
GFT
2585 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2586 else
2587 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2588 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2589 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT
2590
2591 return 0;
2592}
2593
2594static int
2595jme_set_tx_csum(struct net_device *netdev, u32 on)
2596{
cd0ff491 2597 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2598
cd0ff491
GFT
2599 if (on) {
2600 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2601 if (netdev->mtu <= 1900)
b3821cc5 2602 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491
GFT
2603 } else {
2604 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
8c198884 2605 netdev->features &= ~NETIF_F_HW_CSUM;
b3821cc5 2606 }
8c198884
GFT
2607
2608 return 0;
2609}
2610
2611static int
b3821cc5
GFT
2612jme_set_tso(struct net_device *netdev, u32 on)
2613{
cd0ff491 2614 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2615
cd0ff491
GFT
2616 if (on) {
2617 set_bit(JME_FLAG_TSO, &jme->flags);
2618 if (netdev->mtu <= 1900)
3b70a6fa
GFT
2619 netdev->features |= NETIF_F_TSO
2620#ifdef NETIF_F_TSO6
2621 | NETIF_F_TSO6
2622#endif
2623 ;
cd0ff491
GFT
2624 } else {
2625 clear_bit(JME_FLAG_TSO, &jme->flags);
3b70a6fa
GFT
2626 netdev->features &= ~(NETIF_F_TSO
2627#ifdef NETIF_F_TSO6
2628 | NETIF_F_TSO6
2629#endif
2630 );
b3821cc5
GFT
2631 }
2632
cd0ff491 2633 return 0;
b3821cc5
GFT
2634}
2635
2636static int
8c198884
GFT
2637jme_nway_reset(struct net_device *netdev)
2638{
cd0ff491 2639 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2640 jme_restart_an(jme);
2641 return 0;
2642}
2643
cd0ff491 2644static u8
186fc259
GFT
2645jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2646{
cd0ff491 2647 u32 val;
186fc259
GFT
2648 int to;
2649
2650 val = jread32(jme, JME_SMBCSR);
2651 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2652 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2653 msleep(1);
2654 val = jread32(jme, JME_SMBCSR);
2655 }
cd0ff491 2656 if (!to) {
937ef75a 2657 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2658 return 0xFF;
2659 }
2660
2661 jwrite32(jme, JME_SMBINTF,
2662 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2663 SMBINTF_HWRWN_READ |
2664 SMBINTF_HWCMD);
2665
2666 val = jread32(jme, JME_SMBINTF);
2667 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2668 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2669 msleep(1);
2670 val = jread32(jme, JME_SMBINTF);
2671 }
cd0ff491 2672 if (!to) {
937ef75a 2673 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2674 return 0xFF;
2675 }
2676
2677 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2678}
2679
2680static void
cd0ff491 2681jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2682{
cd0ff491 2683 u32 val;
186fc259
GFT
2684 int to;
2685
2686 val = jread32(jme, JME_SMBCSR);
2687 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2688 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2689 msleep(1);
2690 val = jread32(jme, JME_SMBCSR);
2691 }
cd0ff491 2692 if (!to) {
937ef75a 2693 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2694 return;
2695 }
2696
2697 jwrite32(jme, JME_SMBINTF,
2698 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2699 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2700 SMBINTF_HWRWN_WRITE |
2701 SMBINTF_HWCMD);
2702
2703 val = jread32(jme, JME_SMBINTF);
2704 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2705 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2706 msleep(1);
2707 val = jread32(jme, JME_SMBINTF);
2708 }
cd0ff491 2709 if (!to) {
937ef75a 2710 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2711 return;
2712 }
2713
2714 mdelay(2);
2715}
2716
2717static int
2718jme_get_eeprom_len(struct net_device *netdev)
2719{
cd0ff491
GFT
2720 struct jme_adapter *jme = netdev_priv(netdev);
2721 u32 val;
186fc259 2722 val = jread32(jme, JME_SMBCSR);
cd0ff491 2723 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT
2724}
2725
2726static int
2727jme_get_eeprom(struct net_device *netdev,
2728 struct ethtool_eeprom *eeprom, u8 *data)
2729{
cd0ff491 2730 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2731 int i, offset = eeprom->offset, len = eeprom->len;
2732
2733 /*
8d27293f 2734 * ethtool will check the boundary for us
186fc259
GFT
2735 */
2736 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2737 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2738 data[i] = jme_smb_read(jme, i + offset);
2739
2740 return 0;
2741}
2742
2743static int
2744jme_set_eeprom(struct net_device *netdev,
2745 struct ethtool_eeprom *eeprom, u8 *data)
2746{
cd0ff491 2747 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2748 int i, offset = eeprom->offset, len = eeprom->len;
2749
2750 if (eeprom->magic != JME_EEPROM_MAGIC)
2751 return -EINVAL;
2752
2753 /*
8d27293f 2754 * ethtool will check the boundary for us
186fc259 2755 */
cd0ff491 2756 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2757 jme_smb_write(jme, i + offset, data[i]);
2758
2759 return 0;
2760}
2761
3b70a6fa
GFT
2762#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2763static struct ethtool_ops jme_ethtool_ops = {
2764#else
d7699f87 2765static const struct ethtool_ops jme_ethtool_ops = {
3b70a6fa 2766#endif
cd0ff491 2767 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2768 .get_regs_len = jme_get_regs_len,
2769 .get_regs = jme_get_regs,
2770 .get_coalesce = jme_get_coalesce,
192570e0 2771 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT
2772 .get_pauseparam = jme_get_pauseparam,
2773 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2774 .get_wol = jme_get_wol,
2775 .set_wol = jme_set_wol,
d7699f87
GFT
2776 .get_settings = jme_get_settings,
2777 .set_settings = jme_set_settings,
2778 .get_link = jme_get_link,
cd0ff491
GFT
2779 .get_msglevel = jme_get_msglevel,
2780 .set_msglevel = jme_set_msglevel,
8c198884
GFT
2781 .get_rx_csum = jme_get_rx_csum,
2782 .set_rx_csum = jme_set_rx_csum,
2783 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT
2784 .set_tso = jme_set_tso,
2785 .set_sg = ethtool_op_set_sg,
8c198884 2786 .nway_reset = jme_nway_reset,
186fc259
GFT
2787 .get_eeprom_len = jme_get_eeprom_len,
2788 .get_eeprom = jme_get_eeprom,
2789 .set_eeprom = jme_set_eeprom,
d7699f87
GFT
2790};
2791
3bf61c55
GFT
2792static int
2793jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2794{
3b70a6fa 2795 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT
2796#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2797 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2798#else
2799 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2800#endif
2801 )
2802#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2803 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2804#else
cd0ff491 2805 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
0ede469c 2806#endif
3bf61c55
GFT
2807 return 1;
2808
3b70a6fa 2809 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT
2810#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2811 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2812#else
2813 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2814#endif
2815 )
2816#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2817 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2818#else
cd0ff491 2819 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
0ede469c 2820#endif
8c198884
GFT
2821 return 1;
2822
0ede469c
GFT
2823#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2824 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2825 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2826#else
cd0ff491
GFT
2827 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2828 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
0ede469c 2829#endif
3bf61c55
GFT
2830 return 0;
2831
2832 return -1;
2833}
2834
cd0ff491 2835static inline void
cdcdc9eb
GFT
2836jme_phy_init(struct jme_adapter *jme)
2837{
cd0ff491 2838 u16 reg26;
cdcdc9eb
GFT
2839
2840 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2841 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2842}
2843
cd0ff491 2844static inline void
cdcdc9eb 2845jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2846{
cd0ff491 2847 u32 chipmode;
cdcdc9eb
GFT
2848
2849 chipmode = jread32(jme, JME_CHIPMODE);
2850
2851 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 2852 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
42b1055e
GFT
2853}
2854
3b70a6fa
GFT
2855#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2856static const struct net_device_ops jme_netdev_ops = {
2857 .ndo_open = jme_open,
2858 .ndo_stop = jme_close,
2859 .ndo_validate_addr = eth_validate_addr,
aa1e7189 2860 .ndo_do_ioctl = jme_ioctl,
3b70a6fa
GFT
2861 .ndo_start_xmit = jme_start_xmit,
2862 .ndo_set_mac_address = jme_set_macaddr,
2863 .ndo_set_multicast_list = jme_set_multi,
2864 .ndo_change_mtu = jme_change_mtu,
2865 .ndo_tx_timeout = jme_tx_timeout,
2866 .ndo_vlan_rx_register = jme_vlan_rx_register,
2867};
2868#endif
2869
3bf61c55
GFT
2870static int __devinit
2871jme_init_one(struct pci_dev *pdev,
2872 const struct pci_device_id *ent)
2873{
cdcdc9eb 2874 int rc = 0, using_dac, i;
d7699f87
GFT
2875 struct net_device *netdev;
2876 struct jme_adapter *jme;
cd0ff491
GFT
2877 u16 bmcr, bmsr;
2878 u32 apmc;
d7699f87
GFT
2879
2880 /*
2881 * set up PCI device basics
2882 */
4330c2f2 2883 rc = pci_enable_device(pdev);
cd0ff491 2884 if (rc) {
937ef75a 2885 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT
2886 goto err_out;
2887 }
d7699f87 2888
3bf61c55 2889 using_dac = jme_pci_dma64(pdev);
cd0ff491 2890 if (using_dac < 0) {
937ef75a 2891 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT
2892 rc = -EIO;
2893 goto err_out_disable_pdev;
2894 }
2895
cd0ff491 2896 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
937ef75a 2897 pr_err("No PCI resource region found\n");
4330c2f2
GFT
2898 rc = -ENOMEM;
2899 goto err_out_disable_pdev;
2900 }
d7699f87 2901
4330c2f2 2902 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 2903 if (rc) {
937ef75a 2904 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT
2905 goto err_out_disable_pdev;
2906 }
d7699f87
GFT
2907
2908 pci_set_master(pdev);
2909
2910 /*
2911 * alloc and init net device
2912 */
3bf61c55 2913 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 2914 if (!netdev) {
937ef75a 2915 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT
2916 rc = -ENOMEM;
2917 goto err_out_release_regions;
d7699f87 2918 }
3b70a6fa
GFT
2919#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2920 netdev->netdev_ops = &jme_netdev_ops;
2921#else
d7699f87
GFT
2922 netdev->open = jme_open;
2923 netdev->stop = jme_close;
aa1e7189 2924 netdev->do_ioctl = jme_ioctl;
d7699f87 2925 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT
2926 netdev->set_mac_address = jme_set_macaddr;
2927 netdev->set_multicast_list = jme_set_multi;
2928 netdev->change_mtu = jme_change_mtu;
8c198884 2929 netdev->tx_timeout = jme_tx_timeout;
42b1055e 2930 netdev->vlan_rx_register = jme_vlan_rx_register;
7ca9ebee
GFT
2931#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2932 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
2933#endif
3bf61c55 2934 NETDEV_GET_STATS(netdev, &jme_get_stats);
3b70a6fa
GFT
2935#endif
2936 netdev->ethtool_ops = &jme_ethtool_ops;
2937 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2938 netdev->features = NETIF_F_HW_CSUM |
b3821cc5
GFT
2939 NETIF_F_SG |
2940 NETIF_F_TSO |
3b70a6fa 2941#ifdef NETIF_F_TSO6
b3821cc5 2942 NETIF_F_TSO6 |
3b70a6fa 2943#endif
42b1055e
GFT
2944 NETIF_F_HW_VLAN_TX |
2945 NETIF_F_HW_VLAN_RX;
cd0ff491 2946 if (using_dac)
8c198884 2947 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
2948
2949 SET_NETDEV_DEV(netdev, &pdev->dev);
2950 pci_set_drvdata(pdev, netdev);
2951
2952 /*
2953 * init adapter info
2954 */
2955 jme = netdev_priv(netdev);
2956 jme->pdev = pdev;
2957 jme->dev = netdev;
cdcdc9eb
GFT
2958 jme->jme_rx = netif_rx;
2959 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2960 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2961 jme->phylink = 0;
b3821cc5 2962 jme->tx_ring_size = 1 << 10;
0ede469c 2963 jme->tx_ring_mask = jme->tx_ring_size - 1;
b3821cc5
GFT
2964 jme->tx_wake_threshold = 1 << 9;
2965 jme->rx_ring_size = 1 << 9;
2966 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2967 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT
2968 jme->regs = ioremap(pci_resource_start(pdev, 0),
2969 pci_resource_len(pdev, 0));
4330c2f2 2970 if (!(jme->regs)) {
937ef75a 2971 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT
2972 rc = -ENOMEM;
2973 goto err_out_free_netdev;
2974 }
4330c2f2 2975
cd0ff491
GFT
2976 if (no_pseudohp) {
2977 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2978 jwrite32(jme, JME_APMC, apmc);
2979 } else if (force_pseudohp) {
2980 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2981 jwrite32(jme, JME_APMC, apmc);
2982 }
2983
cdcdc9eb 2984 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2985
d7699f87 2986 spin_lock_init(&jme->phy_lock);
fcf45b4c 2987 spin_lock_init(&jme->macaddr_lock);
8c198884 2988 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2989
fcf45b4c
GFT
2990 atomic_set(&jme->link_changing, 1);
2991 atomic_set(&jme->rx_cleaning, 1);
2992 atomic_set(&jme->tx_cleaning, 1);
192570e0 2993 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2994
79ce639c 2995 tasklet_init(&jme->pcc_task,
7ca9ebee 2996 jme_pcc_tasklet,
79ce639c 2997 (unsigned long) jme);
4330c2f2 2998 tasklet_init(&jme->linkch_task,
7ca9ebee 2999 jme_link_change_tasklet,
4330c2f2
GFT
3000 (unsigned long) jme);
3001 tasklet_init(&jme->txclean_task,
7ca9ebee 3002 jme_tx_clean_tasklet,
4330c2f2
GFT
3003 (unsigned long) jme);
3004 tasklet_init(&jme->rxclean_task,
7ca9ebee 3005 jme_rx_clean_tasklet,
4330c2f2 3006 (unsigned long) jme);
fcf45b4c 3007 tasklet_init(&jme->rxempty_task,
7ca9ebee 3008 jme_rx_empty_tasklet,
fcf45b4c 3009 (unsigned long) jme);
0ede469c 3010 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT
3011 tasklet_disable_nosync(&jme->txclean_task);
3012 tasklet_disable_nosync(&jme->rxclean_task);
3013 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT
3014 jme->dpi.cur = PCC_P1;
3015
cd0ff491 3016 jme->reg_ghc = 0;
79ce639c 3017 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
3018 jme->reg_rxmcs = RXMCS_DEFAULT;
3019 jme->reg_txpfc = 0;
47220951 3020 jme->reg_pmcs = PMCS_MFEN;
cd0ff491
GFT
3021 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3022 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 3023
d7699f87 3024 /*
fcf45b4c
GFT
3025 * Get Max Read Req Size from PCI Config Space
3026 */
cd0ff491
GFT
3027 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3028 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3029 switch (jme->mrrs) {
3030 case MRRS_128B:
3031 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3032 break;
3033 case MRRS_256B:
3034 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3035 break;
3036 default:
3037 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3038 break;
cd54cf32 3039 }
fcf45b4c 3040
fcf45b4c 3041 /*
cdcdc9eb 3042 * Must check before reset_mac_processor
d7699f87 3043 */
cdcdc9eb
GFT
3044 jme_check_hw_ver(jme);
3045 jme->mii_if.dev = netdev;
cd0ff491 3046 if (jme->fpgaver) {
cdcdc9eb 3047 jme->mii_if.phy_id = 0;
cd0ff491 3048 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT
3049 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3050 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3051 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT
3052 jme->mii_if.phy_id = i;
3053 break;
3054 }
3055 }
3056
cd0ff491 3057 if (!jme->mii_if.phy_id) {
cdcdc9eb 3058 rc = -EIO;
937ef75a
JP
3059 pr_err("Can not find phy_id\n");
3060 goto err_out_unmap;
cdcdc9eb
GFT
3061 }
3062
3063 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3064 } else {
cdcdc9eb
GFT
3065 jme->mii_if.phy_id = 1;
3066 }
cd0ff491 3067 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
3068 jme->mii_if.supports_gmii = true;
3069 else
3070 jme->mii_if.supports_gmii = false;
aa1e7189
GFT
3071 jme->mii_if.phy_id_mask = 0x1F;
3072 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT
3073 jme->mii_if.mdio_read = jme_mdio_read;
3074 jme->mii_if.mdio_write = jme_mdio_write;
3075
d7699f87 3076 jme_clear_pm(jme);
58c92f28 3077 jme_set_phyfifoa(jme);
cd0ff491
GFT
3078 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
3079 if (!jme->fpgaver)
cdcdc9eb 3080 jme_phy_init(jme);
42b1055e 3081 jme_phy_off(jme);
cdcdc9eb
GFT
3082
3083 /*
3084 * Reset MAC processor and reload EEPROM for MAC Address
3085 */
d7699f87 3086 jme_reset_mac_processor(jme);
4330c2f2 3087 rc = jme_reload_eeprom(jme);
cd0ff491 3088 if (rc) {
937ef75a 3089 pr_err("Reload eeprom for reading MAC Address error\n");
0ede469c 3090 goto err_out_unmap;
4330c2f2 3091 }
d7699f87
GFT
3092 jme_load_macaddr(netdev);
3093
d7699f87
GFT
3094 /*
3095 * Tell stack that we are not ready to work until open()
3096 */
3097 netif_carrier_off(netdev);
3098 netif_stop_queue(netdev);
3099
3100 /*
3101 * Register netdev
3102 */
4330c2f2 3103 rc = register_netdev(netdev);
cd0ff491 3104 if (rc) {
937ef75a 3105 pr_err("Cannot register net device\n");
0ede469c 3106 goto err_out_unmap;
4330c2f2 3107 }
d7699f87 3108
937ef75a
JP
3109 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x "
3110 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
7ca9ebee
GFT
3111 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3112 "JMC250 Gigabit Ethernet" :
3113 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3114 "JMC260 Fast Ethernet" : "Unknown",
3115 (jme->fpgaver != 0) ? " (FPGA)" : "",
3116 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
937ef75a
JP
3117 jme->rev,
3118 netdev->dev_addr[0],
3119 netdev->dev_addr[1],
3120 netdev->dev_addr[2],
3121 netdev->dev_addr[3],
3122 netdev->dev_addr[4],
3123 netdev->dev_addr[5]);
d7699f87
GFT
3124
3125 return 0;
3126
3127err_out_unmap:
3128 iounmap(jme->regs);
3129err_out_free_netdev:
3130 pci_set_drvdata(pdev, NULL);
3131 free_netdev(netdev);
4330c2f2
GFT
3132err_out_release_regions:
3133 pci_release_regions(pdev);
d7699f87 3134err_out_disable_pdev:
cd0ff491 3135 pci_disable_device(pdev);
d7699f87 3136err_out:
4330c2f2 3137 return rc;
d7699f87
GFT
3138}
3139
3bf61c55
GFT
3140static void __devexit
3141jme_remove_one(struct pci_dev *pdev)
3142{
d7699f87
GFT
3143 struct net_device *netdev = pci_get_drvdata(pdev);
3144 struct jme_adapter *jme = netdev_priv(netdev);
3145
3146 unregister_netdev(netdev);
3147 iounmap(jme->regs);
3148 pci_set_drvdata(pdev, NULL);
3149 free_netdev(netdev);
3150 pci_release_regions(pdev);
3151 pci_disable_device(pdev);
3152
3153}
3154
7ee473a3 3155#ifdef CONFIG_PM
29bdd921
GFT
3156static int
3157jme_suspend(struct pci_dev *pdev, pm_message_t state)
3158{
3159 struct net_device *netdev = pci_get_drvdata(pdev);
3160 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT
3161
3162 atomic_dec(&jme->link_changing);
3163
3164 netif_device_detach(netdev);
3165 netif_stop_queue(netdev);
3166 jme_stop_irq(jme);
29bdd921 3167
cd0ff491
GFT
3168 tasklet_disable(&jme->txclean_task);
3169 tasklet_disable(&jme->rxclean_task);
3170 tasklet_disable(&jme->rxempty_task);
3171
cd0ff491
GFT
3172 if (netif_carrier_ok(netdev)) {
3173 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT
3174 jme_polling_mode(jme);
3175
29bdd921 3176 jme_stop_pcc_timer(jme);
cd0ff491
GFT
3177 jme_reset_ghc_speed(jme);
3178 jme_disable_rx_engine(jme);
3179 jme_disable_tx_engine(jme);
29bdd921
GFT
3180 jme_reset_mac_processor(jme);
3181 jme_free_rx_resources(jme);
3182 jme_free_tx_resources(jme);
3183 netif_carrier_off(netdev);
3184 jme->phylink = 0;
3185 }
3186
cd0ff491
GFT
3187 tasklet_enable(&jme->txclean_task);
3188 tasklet_hi_enable(&jme->rxclean_task);
3189 tasklet_hi_enable(&jme->rxempty_task);
29bdd921
GFT
3190
3191 pci_save_state(pdev);
cd0ff491 3192 if (jme->reg_pmcs) {
42b1055e 3193 jme_set_100m_half(jme);
47220951 3194
cd0ff491 3195 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
47220951
GFT
3196 jme_wait_link(jme);
3197
29bdd921 3198 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
cd0ff491 3199
42b1055e 3200 pci_enable_wake(pdev, PCI_D3cold, true);
cd0ff491 3201 } else {
42b1055e 3202 jme_phy_off(jme);
29bdd921 3203 }
cd0ff491 3204 pci_set_power_state(pdev, PCI_D3cold);
29bdd921
GFT
3205
3206 return 0;
3207}
3208
3209static int
3210jme_resume(struct pci_dev *pdev)
3211{
3212 struct net_device *netdev = pci_get_drvdata(pdev);
3213 struct jme_adapter *jme = netdev_priv(netdev);
3214
3215 jme_clear_pm(jme);
3216 pci_restore_state(pdev);
3217
e58b908e
GFT
3218 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3219 jme_phy_on(jme);
29bdd921 3220 jme_set_settings(netdev, &jme->old_ecmd);
e58b908e 3221 } else {
29bdd921 3222 jme_reset_phy_processor(jme);
e58b908e 3223 }
29bdd921 3224
29bdd921
GFT
3225 jme_start_irq(jme);
3226 netif_device_attach(netdev);
3227
3228 atomic_inc(&jme->link_changing);
3229
3230 jme_reset_link(jme);
3231
3232 return 0;
3233}
7ee473a3 3234#endif
29bdd921 3235
7ca9ebee 3236#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
d7699f87 3237static struct pci_device_id jme_pci_tbl[] = {
7ca9ebee
GFT
3238#else
3239static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3240#endif
cd0ff491
GFT
3241 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3242 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT
3243 { }
3244};
3245
3246static struct pci_driver jme_driver = {
cd0ff491
GFT
3247 .name = DRV_NAME,
3248 .id_table = jme_pci_tbl,
3249 .probe = jme_init_one,
3250 .remove = __devexit_p(jme_remove_one),
d7699f87 3251#ifdef CONFIG_PM
cd0ff491
GFT
3252 .suspend = jme_suspend,
3253 .resume = jme_resume,
d7699f87 3254#endif /* CONFIG_PM */
d7699f87
GFT
3255};
3256
3bf61c55
GFT
3257static int __init
3258jme_init_module(void)
d7699f87 3259{
937ef75a 3260 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT
3261 return pci_register_driver(&jme_driver);
3262}
3263
3bf61c55
GFT
3264static void __exit
3265jme_cleanup_module(void)
d7699f87
GFT
3266{
3267 pci_unregister_driver(&jme_driver);
3268}
3269
3270module_init(jme_init_module);
3271module_exit(jme_cleanup_module);
3272
3bf61c55 3273MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
3274MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3275MODULE_LICENSE("GPL");
3276MODULE_VERSION(DRV_VERSION);
3277MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3278