Import jme 1.0.3-backport source
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
3bf61c55
GFT
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
d7699f87
GFT
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
4330c2f2 24#include <linux/version.h>
d7699f87
GFT
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/pci.h>
28#include <linux/netdevice.h>
29#include <linux/etherdevice.h>
30#include <linux/ethtool.h>
31#include <linux/mii.h>
32#include <linux/crc32.h>
4330c2f2 33#include <linux/delay.h>
29bdd921 34#include <linux/spinlock.h>
8c198884
GFT
35#include <linux/in.h>
36#include <linux/ip.h>
79ce639c
GFT
37#include <linux/ipv6.h>
38#include <linux/tcp.h>
39#include <linux/udp.h>
42b1055e 40#include <linux/if_vlan.h>
d7699f87
GFT
41#include "jme.h"
42
cd0ff491
GFT
43static int force_pseudohp = -1;
44static int no_pseudohp = -1;
45static int no_extplug = -1;
46module_param(force_pseudohp, int, 0);
47MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49module_param(no_pseudohp, int, 0);
50MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51module_param(no_extplug, int, 0);
52MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 54
3bf61c55
GFT
55static int
56jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT
57{
58 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 60
186fc259 61read_again:
cd0ff491 62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT
63 smi_phy_addr(phy) |
64 smi_reg_addr(reg));
d7699f87
GFT
65
66 wmb();
cd0ff491 67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 68 udelay(20);
b3821cc5
GFT
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
3bf61c55 71 break;
cd0ff491 72 }
d7699f87 73
cd0ff491
GFT
74 if (i == 0) {
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 76 return 0;
cd0ff491 77 }
d7699f87 78
cd0ff491 79 if (again--)
186fc259
GFT
80 goto read_again;
81
cd0ff491 82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT
83}
84
3bf61c55
GFT
85static void
86jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
d7699f87
GFT
88{
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
3bf61c55
GFT
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
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GFT
95
96 wmb();
cdcdc9eb
GFT
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98 udelay(20);
8d27293f 99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT
100 break;
101 }
d7699f87 102
3bf61c55 103 if (i == 0)
cd0ff491 104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
d7699f87 105
3bf61c55 106 return;
d7699f87
GFT
107}
108
cd0ff491 109static inline void
3bf61c55 110jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 111{
cd0ff491 112 u32 val;
3bf61c55
GFT
113
114 jme_mdio_write(jme->dev,
115 jme->mii_if.phy_id,
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GFT
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 118
cd0ff491 119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 124
fcf45b4c
GFT
125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
3bf61c55
GFT
133 return;
134}
135
b3821cc5
GFT
136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
cd0ff491 138 u32 *mask, u32 crc, int fnr)
b3821cc5
GFT
139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
cd0ff491 153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
3bf61c55 162
cd0ff491 163static inline void
3bf61c55
GFT
164jme_reset_mac_processor(struct jme_adapter *jme)
165{
cd0ff491
GFT
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
b3821cc5
GFT
169 int i;
170
3bf61c55 171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 172 udelay(2);
3bf61c55 173 jwrite32(jme, JME_GHC, jme->reg_ghc);
cd0ff491
GFT
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
4330c2f2
GFT
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 187 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 188 if (jme->fpgaver)
cdcdc9eb
GFT
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
7ee473a3 193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
d7699f87
GFT
194}
195
cd0ff491
GFT
196static inline void
197jme_reset_ghc_speed(struct jme_adapter *jme)
198{
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201}
202
203static inline void
3bf61c55 204jme_clear_pm(struct jme_adapter *jme)
d7699f87 205{
29bdd921 206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 207 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 208 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT
209}
210
3bf61c55
GFT
211static int
212jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 213{
cd0ff491 214 u32 val;
d7699f87
GFT
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
cd0ff491 219 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
cd0ff491 226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
cd0ff491
GFT
232 if (i == 0) {
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
d7699f87
GFT
234 return -EIO;
235 }
236 }
3bf61c55 237
d7699f87
GFT
238 return 0;
239}
240
3bf61c55
GFT
241static void
242jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT
243{
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
cd0ff491 246 u32 val;
d7699f87 247
cd0ff491 248 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 249 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 254 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT
259}
260
cd0ff491 261static inline void
3bf61c55
GFT
262jme_set_rx_pcc(struct jme_adapter *jme, int p)
263{
cd0ff491 264 switch (p) {
192570e0
GFT
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
3bf61c55
GFT
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
192570e0 288 wmb();
3bf61c55 289
cd0ff491
GFT
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
d7699f87
GFT
292}
293
fcf45b4c 294static void
3bf61c55 295jme_start_irq(struct jme_adapter *jme)
d7699f87 296{
3bf61c55
GFT
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
8c198884
GFT
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
307 PCCTXQ0_EN
308 );
309
d7699f87
GFT
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314}
315
cd0ff491 316static inline void
3bf61c55 317jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
318{
319 /*
320 * Disable Interrupts
321 */
cd0ff491 322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT
323}
324
cd0ff491 325static inline void
3bf61c55 326jme_enable_shadow(struct jme_adapter *jme)
4330c2f2
GFT
327{
328 jwrite32(jme,
329 JME_SHBA_LO,
cd0ff491 330 ((u32)jme->shadow_dma & ~((u32)0x1F)) | SHBA_POSTEN);
4330c2f2
GFT
331}
332
cd0ff491 333static inline void
3bf61c55 334jme_disable_shadow(struct jme_adapter *jme)
4330c2f2
GFT
335{
336 jwrite32(jme, JME_SHBA_LO, 0x0);
337}
338
cd0ff491 339static u32
cdcdc9eb
GFT
340jme_linkstat_from_phy(struct jme_adapter *jme)
341{
cd0ff491 342 u32 phylink, bmsr;
cdcdc9eb
GFT
343
344 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
345 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 346 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT
347 phylink |= PHY_LINK_AUTONEG_COMPLETE;
348
349 return phylink;
350}
351
cd0ff491 352static inline void
58c92f28 353jme_set_phyfifoa(struct jme_adapter *jme)
cd0ff491
GFT
354{
355 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
356}
357
358static inline void
58c92f28 359jme_set_phyfifob(struct jme_adapter *jme)
cd0ff491
GFT
360{
361 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
362}
363
fcf45b4c
GFT
364static int
365jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
366{
367 struct jme_adapter *jme = netdev_priv(netdev);
7ee473a3 368 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
79ce639c 369 char linkmsg[64];
fcf45b4c 370 int rc = 0;
d7699f87 371
b3821cc5 372 linkmsg[0] = '\0';
cdcdc9eb 373
cd0ff491 374 if (jme->fpgaver)
cdcdc9eb
GFT
375 phylink = jme_linkstat_from_phy(jme);
376 else
377 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 378
cd0ff491
GFT
379 if (phylink & PHY_LINK_UP) {
380 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT
381 /*
382 * If we did not enable AN
383 * Speed/Duplex Info should be obtained from SMI
384 */
385 phylink = PHY_LINK_UP;
386
387 bmcr = jme_mdio_read(jme->dev,
388 jme->mii_if.phy_id,
389 MII_BMCR);
390
391 phylink |= ((bmcr & BMCR_SPEED1000) &&
392 (bmcr & BMCR_SPEED100) == 0) ?
393 PHY_LINK_SPEED_1000M :
394 (bmcr & BMCR_SPEED100) ?
395 PHY_LINK_SPEED_100M :
396 PHY_LINK_SPEED_10M;
397
398 phylink |= (bmcr & BMCR_FULLDPLX) ?
399 PHY_LINK_DUPLEX : 0;
79ce639c 400
b3821cc5 401 strcat(linkmsg, "Forced: ");
cd0ff491 402 } else {
8c198884
GFT
403 /*
404 * Keep polling for speed/duplex resolve complete
405 */
cd0ff491 406 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT
407 --cnt) {
408
409 udelay(1);
8c198884 410
cd0ff491 411 if (jme->fpgaver)
cdcdc9eb
GFT
412 phylink = jme_linkstat_from_phy(jme);
413 else
414 phylink = jread32(jme, JME_PHY_LINK);
8c198884 415 }
cd0ff491
GFT
416 if (!cnt)
417 jeprintk(jme->pdev,
8c198884 418 "Waiting speed resolve timeout.\n");
79ce639c 419
b3821cc5 420 strcat(linkmsg, "ANed: ");
d7699f87
GFT
421 }
422
cd0ff491 423 if (jme->phylink == phylink) {
fcf45b4c
GFT
424 rc = 1;
425 goto out;
426 }
cd0ff491 427 if (testonly)
fcf45b4c
GFT
428 goto out;
429
430 jme->phylink = phylink;
431
cdcdc9eb
GFT
432 ghc = jme->reg_ghc & ~(GHC_SPEED_10M |
433 GHC_SPEED_100M |
434 GHC_SPEED_1000M |
435 GHC_DPX);
cd0ff491
GFT
436 switch (phylink & PHY_LINK_SPEED_MASK) {
437 case PHY_LINK_SPEED_10M:
438 ghc |= GHC_SPEED_10M;
439 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT
440 break;
441 case PHY_LINK_SPEED_100M:
442 ghc |= GHC_SPEED_100M;
443 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT
444 break;
445 case PHY_LINK_SPEED_1000M:
446 ghc |= GHC_SPEED_1000M;
447 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT
448 break;
449 default:
450 break;
d7699f87 451 }
d7699f87 452
cd0ff491 453 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 454 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
7ee473a3 455 ghc |= GHC_DPX;
cd0ff491 456 } else {
d7699f87 457 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
458 TXMCS_BACKOFF |
459 TXMCS_CARRIERSENSE |
460 TXMCS_COLLISION);
8c198884
GFT
461 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
462 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
463 TXTRHD_TXREN |
464 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
465 }
7ee473a3
GFT
466 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
467 "Full-Duplex, " :
468 "Half-Duplex, ");
469
470 if (phylink & PHY_LINK_MDI_STAT)
471 strcat(linkmsg, "MDI-X");
472 else
473 strcat(linkmsg, "MDI");
474
475 gpreg1 = GPREG1_DEFAULT;
476 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
477 if (!(phylink & PHY_LINK_DUPLEX))
478 gpreg1 |= GPREG1_HALFMODEPATCH;
479 switch (phylink & PHY_LINK_SPEED_MASK) {
480 case PHY_LINK_SPEED_10M:
481 jme_set_phyfifoa(jme);
482 gpreg1 |= GPREG1_RSSPATCH;
483 break;
484 case PHY_LINK_SPEED_100M:
485 jme_set_phyfifob(jme);
486 gpreg1 |= GPREG1_RSSPATCH;
487 break;
488 case PHY_LINK_SPEED_1000M:
489 jme_set_phyfifoa(jme);
490 break;
491 default:
492 break;
493 }
494 }
495 jwrite32(jme, JME_GPREG1, gpreg1);
d7699f87 496
fcf45b4c
GFT
497 jme->reg_ghc = ghc;
498 jwrite32(jme, JME_GHC, ghc);
499
cd0ff491
GFT
500 msg_link(jme, "Link is up at %s.\n", linkmsg);
501 netif_carrier_on(netdev);
502 } else {
503 if (testonly)
fcf45b4c
GFT
504 goto out;
505
cd0ff491 506 msg_link(jme, "Link is down.\n");
fcf45b4c 507 jme->phylink = 0;
cd0ff491 508 netif_carrier_off(netdev);
d7699f87 509 }
fcf45b4c
GFT
510
511out:
512 return rc;
d7699f87
GFT
513}
514
3bf61c55
GFT
515static int
516jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 517{
d7699f87
GFT
518 struct jme_ring *txring = &(jme->txring[0]);
519
520 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
521 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
522 &(txring->dmaalloc),
523 GFP_ATOMIC);
fcf45b4c 524
cd0ff491 525 if (!txring->alloc) {
4330c2f2
GFT
526 txring->desc = NULL;
527 txring->dmaalloc = 0;
528 txring->dma = 0;
d7699f87 529 return -ENOMEM;
4330c2f2 530 }
d7699f87
GFT
531
532 /*
533 * 16 Bytes align
534 */
cd0ff491 535 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 536 RING_DESC_ALIGN);
4330c2f2 537 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 538 txring->next_to_use = 0;
cdcdc9eb 539 atomic_set(&txring->next_to_clean, 0);
b3821cc5 540 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87
GFT
541
542 /*
b3821cc5 543 * Initialize Transmit Descriptors
d7699f87 544 */
b3821cc5 545 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 546 memset(txring->bufinf, 0,
b3821cc5 547 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT
548
549 return 0;
550}
551
3bf61c55
GFT
552static void
553jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
554{
555 int i;
556 struct jme_ring *txring = &(jme->txring[0]);
4330c2f2 557 struct jme_buffer_info *txbi = txring->bufinf;
d7699f87 558
cd0ff491
GFT
559 if (txring->alloc) {
560 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
4330c2f2 561 txbi = txring->bufinf + i;
cd0ff491 562 if (txbi->skb) {
4330c2f2
GFT
563 dev_kfree_skb(txbi->skb);
564 txbi->skb = NULL;
d7699f87 565 }
47220951
GFT
566 txbi->mapping = 0;
567 txbi->len = 0;
568 txbi->nr_desc = 0;
569 txbi->start_xmit = 0;
d7699f87
GFT
570 }
571
572 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 573 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT
574 txring->alloc,
575 txring->dmaalloc);
3bf61c55
GFT
576
577 txring->alloc = NULL;
578 txring->desc = NULL;
579 txring->dmaalloc = 0;
580 txring->dma = 0;
d7699f87 581 }
3bf61c55 582 txring->next_to_use = 0;
cdcdc9eb 583 atomic_set(&txring->next_to_clean, 0);
79ce639c 584 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
585
586}
587
cd0ff491 588static inline void
3bf61c55 589jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
590{
591 /*
592 * Select Queue 0
593 */
594 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 595 wmb();
d7699f87
GFT
596
597 /*
598 * Setup TX Queue 0 DMA Bass Address
599 */
fcf45b4c 600 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 601 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 602 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
603
604 /*
605 * Setup TX Descptor Count
606 */
b3821cc5 607 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT
608
609 /*
610 * Enable TX Engine
611 */
612 wmb();
4330c2f2
GFT
613 jwrite32(jme, JME_TXCS, jme->reg_txcs |
614 TXCS_SELECT_QUEUE0 |
615 TXCS_ENABLE);
d7699f87
GFT
616
617}
618
cd0ff491 619static inline void
29bdd921
GFT
620jme_restart_tx_engine(struct jme_adapter *jme)
621{
622 /*
623 * Restart TX Engine
624 */
625 jwrite32(jme, JME_TXCS, jme->reg_txcs |
626 TXCS_SELECT_QUEUE0 |
627 TXCS_ENABLE);
628}
629
cd0ff491 630static inline void
3bf61c55 631jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
632{
633 int i;
cd0ff491 634 u32 val;
d7699f87
GFT
635
636 /*
637 * Disable TX Engine
638 */
fcf45b4c 639 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 640 wmb();
d7699f87
GFT
641
642 val = jread32(jme, JME_TXCS);
cd0ff491 643 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 644 mdelay(1);
d7699f87 645 val = jread32(jme, JME_TXCS);
cd0ff491 646 rmb();
d7699f87
GFT
647 }
648
cd0ff491
GFT
649 if (!i)
650 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
d7699f87
GFT
651}
652
3bf61c55
GFT
653static void
654jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87
GFT
655{
656 struct jme_ring *rxring = jme->rxring;
cd0ff491 657 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT
658 struct jme_buffer_info *rxbi = rxring->bufinf;
659 rxdesc += i;
660 rxbi += i;
661
662 rxdesc->dw[0] = 0;
663 rxdesc->dw[1] = 0;
3bf61c55 664 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
665 rxdesc->desc1.bufaddrl = cpu_to_le32(
666 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 667 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 668 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 669 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 670 wmb();
3bf61c55 671 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
672}
673
3bf61c55
GFT
674static int
675jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
676{
677 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 678 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 679 struct sk_buff *skb;
4330c2f2 680
79ce639c
GFT
681 skb = netdev_alloc_skb(jme->dev,
682 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 683 if (unlikely(!skb))
4330c2f2 684 return -ENOMEM;
3bf61c55 685
4330c2f2 686 rxbi->skb = skb;
3bf61c55 687 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT
688 rxbi->mapping = pci_map_page(jme->pdev,
689 virt_to_page(skb->data),
690 offset_in_page(skb->data),
691 rxbi->len,
692 PCI_DMA_FROMDEVICE);
4330c2f2
GFT
693
694 return 0;
695}
696
3bf61c55
GFT
697static void
698jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
699{
700 struct jme_ring *rxring = &(jme->rxring[0]);
701 struct jme_buffer_info *rxbi = rxring->bufinf;
702 rxbi += i;
703
cd0ff491 704 if (rxbi->skb) {
b3821cc5 705 pci_unmap_page(jme->pdev,
4330c2f2 706 rxbi->mapping,
3bf61c55 707 rxbi->len,
4330c2f2
GFT
708 PCI_DMA_FROMDEVICE);
709 dev_kfree_skb(rxbi->skb);
710 rxbi->skb = NULL;
711 rxbi->mapping = 0;
3bf61c55 712 rxbi->len = 0;
4330c2f2
GFT
713 }
714}
715
3bf61c55
GFT
716static void
717jme_free_rx_resources(struct jme_adapter *jme)
718{
719 int i;
720 struct jme_ring *rxring = &(jme->rxring[0]);
721
cd0ff491
GFT
722 if (rxring->alloc) {
723 for (i = 0 ; i < jme->rx_ring_size ; ++i)
3bf61c55
GFT
724 jme_free_rx_buf(jme, i);
725
726 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 727 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT
728 rxring->alloc,
729 rxring->dmaalloc);
730 rxring->alloc = NULL;
731 rxring->desc = NULL;
732 rxring->dmaalloc = 0;
733 rxring->dma = 0;
734 }
735 rxring->next_to_use = 0;
cdcdc9eb 736 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT
737}
738
739static int
740jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
741{
742 int i;
743 struct jme_ring *rxring = &(jme->rxring[0]);
744
745 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
746 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
747 &(rxring->dmaalloc),
748 GFP_ATOMIC);
cd0ff491 749 if (!rxring->alloc) {
4330c2f2
GFT
750 rxring->desc = NULL;
751 rxring->dmaalloc = 0;
752 rxring->dma = 0;
d7699f87 753 return -ENOMEM;
4330c2f2 754 }
d7699f87
GFT
755
756 /*
757 * 16 Bytes align
758 */
cd0ff491 759 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 760 RING_DESC_ALIGN);
4330c2f2 761 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 762 rxring->next_to_use = 0;
cdcdc9eb 763 atomic_set(&rxring->next_to_clean, 0);
d7699f87 764
d7699f87
GFT
765 /*
766 * Initiallize Receive Descriptors
767 */
cd0ff491
GFT
768 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
769 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT
770 jme_free_rx_resources(jme);
771 return -ENOMEM;
772 }
d7699f87
GFT
773
774 jme_set_clean_rxdesc(jme, i);
775 }
776
d7699f87
GFT
777 return 0;
778}
779
cd0ff491 780static inline void
3bf61c55 781jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 782{
d7699f87 783 /*
cd0ff491
GFT
784 * Select Queue 0
785 */
786 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
787 RXCS_QUEUESEL_Q0);
788 wmb();
789
790 /*
d7699f87
GFT
791 * Setup RX DMA Bass Address
792 */
fcf45b4c 793 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
3bf61c55 794 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fcf45b4c 795 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
796
797 /*
b3821cc5 798 * Setup RX Descriptor Count
d7699f87 799 */
b3821cc5 800 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 801
3bf61c55 802 /*
d7699f87
GFT
803 * Setup Unicast Filter
804 */
805 jme_set_multi(jme->dev);
806
807 /*
808 * Enable RX Engine
809 */
810 wmb();
79ce639c 811 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
812 RXCS_QUEUESEL_Q0 |
813 RXCS_ENABLE |
814 RXCS_QST);
d7699f87
GFT
815}
816
cd0ff491 817static inline void
3bf61c55 818jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
819{
820 /*
3bf61c55 821 * Start RX Engine
4330c2f2 822 */
79ce639c 823 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
824 RXCS_QUEUESEL_Q0 |
825 RXCS_ENABLE |
826 RXCS_QST);
827}
828
cd0ff491 829static inline void
3bf61c55 830jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
831{
832 int i;
cd0ff491 833 u32 val;
d7699f87
GFT
834
835 /*
836 * Disable RX Engine
837 */
29bdd921 838 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 839 wmb();
d7699f87
GFT
840
841 val = jread32(jme, JME_RXCS);
cd0ff491 842 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 843 mdelay(1);
d7699f87 844 val = jread32(jme, JME_RXCS);
cd0ff491 845 rmb();
d7699f87
GFT
846 }
847
cd0ff491
GFT
848 if (!i)
849 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
d7699f87
GFT
850
851}
852
192570e0 853static int
cd0ff491 854jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
192570e0 855{
cd0ff491 856 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT
857 return false;
858
cd0ff491
GFT
859 if (unlikely(!(flags & RXWBFLAG_MF) &&
860 (flags & RXWBFLAG_TCPON) && !(flags & RXWBFLAG_TCPCS))) {
861 msg_rx_err(jme, "TCP Checksum error.\n");
cdcdc9eb 862 goto out_sumerr;
192570e0
GFT
863 }
864
cd0ff491
GFT
865 if (unlikely(!(flags & RXWBFLAG_MF) &&
866 (flags & RXWBFLAG_UDPON) && !(flags & RXWBFLAG_UDPCS))) {
867 msg_rx_err(jme, "UDP Checksum error.\n");
cdcdc9eb 868 goto out_sumerr;
192570e0
GFT
869 }
870
cd0ff491
GFT
871 if (unlikely((flags & RXWBFLAG_IPV4) && !(flags & RXWBFLAG_IPCS))) {
872 msg_rx_err(jme, "IPv4 Checksum error.\n");
cdcdc9eb 873 goto out_sumerr;
192570e0
GFT
874 }
875
876 return true;
cdcdc9eb
GFT
877
878out_sumerr:
cdcdc9eb 879 return false;
192570e0
GFT
880}
881
3bf61c55 882static void
42b1055e 883jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 884{
d7699f87 885 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 886 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 887 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 888 struct sk_buff *skb;
3bf61c55 889 int framesize;
d7699f87 890
3bf61c55
GFT
891 rxdesc += idx;
892 rxbi += idx;
d7699f87 893
3bf61c55
GFT
894 skb = rxbi->skb;
895 pci_dma_sync_single_for_cpu(jme->pdev,
896 rxbi->mapping,
897 rxbi->len,
898 PCI_DMA_FROMDEVICE);
899
cd0ff491 900 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT
901 pci_dma_sync_single_for_device(jme->pdev,
902 rxbi->mapping,
903 rxbi->len,
904 PCI_DMA_FROMDEVICE);
905
906 ++(NET_STAT(jme).rx_dropped);
cd0ff491 907 } else {
3bf61c55
GFT
908 framesize = le16_to_cpu(rxdesc->descwb.framesize)
909 - RX_PREPAD_SIZE;
910
911 skb_reserve(skb, RX_PREPAD_SIZE);
912 skb_put(skb, framesize);
913 skb->protocol = eth_type_trans(skb, jme->dev);
914
cd0ff491 915 if (jme_rxsum_ok(jme, rxdesc->descwb.flags))
8c198884 916 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921
GFT
917 else
918 skb->ip_summed = CHECKSUM_NONE;
8c198884 919
cd0ff491
GFT
920 if (rxdesc->descwb.flags & RXWBFLAG_TAGON) {
921 if (jme->vlgrp) {
cdcdc9eb 922 jme->jme_vlan_rx(skb, jme->vlgrp,
42b1055e 923 le32_to_cpu(rxdesc->descwb.vlan));
b3821cc5
GFT
924 NET_STAT(jme).rx_bytes += 4;
925 }
cd0ff491 926 } else {
cdcdc9eb 927 jme->jme_rx(skb);
b3821cc5 928 }
3bf61c55 929
cd0ff491 930 if ((le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST) ==
b3821cc5 931 RXWBFLAG_DEST_MUL)
3bf61c55
GFT
932 ++(NET_STAT(jme).multicast);
933
934 jme->dev->last_rx = jiffies;
935 NET_STAT(jme).rx_bytes += framesize;
936 ++(NET_STAT(jme).rx_packets);
937 }
938
939 jme_set_clean_rxdesc(jme, idx);
940
941}
942
8c198884 943static int
3bf61c55
GFT
944jme_process_receive(struct jme_adapter *jme, int limit)
945{
946 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 947 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 948 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 949
cd0ff491 950 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT
951 goto out_inc;
952
cd0ff491 953 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT
954 goto out_inc;
955
cd0ff491 956 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT
957 goto out_inc;
958
cdcdc9eb 959 i = atomic_read(&rxring->next_to_clean);
cd0ff491 960 while (limit-- > 0) {
3bf61c55
GFT
961 rxdesc = rxring->desc;
962 rxdesc += i;
963
cd0ff491 964 if ((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
3bf61c55
GFT
965 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
966 goto out;
d7699f87 967
4330c2f2
GFT
968 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
969
cd0ff491 970 if (unlikely(desccnt > 1 ||
192570e0 971 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 972
cd0ff491 973 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 974 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 975 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT
976 ++(NET_STAT(jme).rx_fifo_errors);
977 else
978 ++(NET_STAT(jme).rx_errors);
4330c2f2 979
cd0ff491 980 if (desccnt > 1)
3bf61c55 981 limit -= desccnt - 1;
4330c2f2 982
cd0ff491 983 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 984 jme_set_clean_rxdesc(jme, j);
b3821cc5 985 j = (j + 1) & (mask);
4330c2f2 986 }
3bf61c55 987
cd0ff491 988 } else {
42b1055e 989 jme_alloc_and_feed_skb(jme, i);
3bf61c55 990 }
4330c2f2 991
b3821cc5 992 i = (i + desccnt) & (mask);
3bf61c55 993 }
4330c2f2 994
3bf61c55 995out:
cdcdc9eb 996 atomic_set(&rxring->next_to_clean, i);
4330c2f2 997
192570e0
GFT
998out_inc:
999 atomic_inc(&jme->rx_cleaning);
1000
3bf61c55 1001 return limit > 0 ? limit : 0;
4330c2f2 1002
3bf61c55 1003}
d7699f87 1004
3bf61c55 1005static void
79ce639c
GFT
1006jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1007{
cd0ff491 1008 if (likely(atmp == dpi->cur)) {
192570e0 1009 dpi->cnt = 0;
79ce639c 1010 return;
192570e0 1011 }
79ce639c 1012
cd0ff491 1013 if (dpi->attempt == atmp) {
79ce639c 1014 ++(dpi->cnt);
cd0ff491 1015 } else {
79ce639c
GFT
1016 dpi->attempt = atmp;
1017 dpi->cnt = 0;
1018 }
1019
1020}
1021
1022static void
1023jme_dynamic_pcc(struct jme_adapter *jme)
1024{
1025 register struct dynpcc_info *dpi = &(jme->dpi);
1026
cd0ff491 1027 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1028 jme_attempt_pcc(dpi, PCC_P3);
cd0ff491 1029 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
79ce639c
GFT
1030 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1031 jme_attempt_pcc(dpi, PCC_P2);
1032 else
1033 jme_attempt_pcc(dpi, PCC_P1);
1034
cd0ff491
GFT
1035 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1036 if (dpi->attempt < dpi->cur)
1037 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT
1038 jme_set_rx_pcc(jme, dpi->attempt);
1039 dpi->cur = dpi->attempt;
1040 dpi->cnt = 0;
1041 }
1042}
1043
1044static void
1045jme_start_pcc_timer(struct jme_adapter *jme)
1046{
1047 struct dynpcc_info *dpi = &(jme->dpi);
1048 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1049 dpi->last_pkts = NET_STAT(jme).rx_packets;
1050 dpi->intr_cnt = 0;
1051 jwrite32(jme, JME_TMCSR,
1052 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1053}
1054
cd0ff491 1055static inline void
29bdd921
GFT
1056jme_stop_pcc_timer(struct jme_adapter *jme)
1057{
1058 jwrite32(jme, JME_TMCSR, 0);
1059}
1060
1061static void
cd0ff491
GFT
1062jme_shutdown_nic(struct jme_adapter *jme)
1063{
1064 u32 phylink;
1065
1066 phylink = jme_linkstat_from_phy(jme);
1067
1068 if (!(phylink & PHY_LINK_UP)) {
1069 /*
1070 * Disable all interrupt before issue timer
1071 */
1072 jme_stop_irq(jme);
1073 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1074 }
1075}
1076
1077static void
79ce639c
GFT
1078jme_pcc_tasklet(unsigned long arg)
1079{
cd0ff491 1080 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT
1081 struct net_device *netdev = jme->dev;
1082
cd0ff491
GFT
1083 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1084 jme_shutdown_nic(jme);
1085 return;
1086 }
29bdd921 1087
cd0ff491 1088 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT
1089 (atomic_read(&jme->link_changing) != 1)
1090 )) {
1091 jme_stop_pcc_timer(jme);
79ce639c
GFT
1092 return;
1093 }
29bdd921 1094
cd0ff491 1095 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT
1096 jme_dynamic_pcc(jme);
1097
79ce639c
GFT
1098 jme_start_pcc_timer(jme);
1099}
1100
cd0ff491 1101static inline void
192570e0
GFT
1102jme_polling_mode(struct jme_adapter *jme)
1103{
1104 jme_set_rx_pcc(jme, PCC_OFF);
1105}
1106
cd0ff491 1107static inline void
192570e0
GFT
1108jme_interrupt_mode(struct jme_adapter *jme)
1109{
1110 jme_set_rx_pcc(jme, PCC_P1);
1111}
1112
cd0ff491
GFT
1113static inline int
1114jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1115{
1116 u32 apmc;
1117 apmc = jread32(jme, JME_APMC);
1118 return apmc & JME_APMC_PSEUDO_HP_EN;
1119}
1120
1121static void
1122jme_start_shutdown_timer(struct jme_adapter *jme)
1123{
1124 u32 apmc;
1125
1126 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1127 apmc &= ~JME_APMC_EPIEN_CTRL;
1128 if (!no_extplug) {
1129 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1130 wmb();
1131 }
1132 jwrite32f(jme, JME_APMC, apmc);
1133
1134 jwrite32f(jme, JME_TIMER2, 0);
1135 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1136 jwrite32(jme, JME_TMCSR,
1137 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1138}
1139
1140static void
1141jme_stop_shutdown_timer(struct jme_adapter *jme)
1142{
1143 u32 apmc;
1144
1145 jwrite32f(jme, JME_TMCSR, 0);
1146 jwrite32f(jme, JME_TIMER2, 0);
1147 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1148
1149 apmc = jread32(jme, JME_APMC);
1150 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1151 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1152 wmb();
1153 jwrite32f(jme, JME_APMC, apmc);
1154}
1155
79ce639c 1156static void
3bf61c55
GFT
1157jme_link_change_tasklet(unsigned long arg)
1158{
cd0ff491 1159 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1160 struct net_device *netdev = jme->dev;
fcf45b4c
GFT
1161 int rc;
1162
cd0ff491
GFT
1163 while (!atomic_dec_and_test(&jme->link_changing)) {
1164 atomic_inc(&jme->link_changing);
1165 msg_intr(jme, "Get link change lock failed.\n");
58c92f28 1166 while (atomic_read(&jme->link_changing) != 1)
cd0ff491
GFT
1167 msg_intr(jme, "Waiting link change lock.\n");
1168 }
fcf45b4c 1169
cd0ff491 1170 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1171 goto out;
1172
29bdd921 1173 jme->old_mtu = netdev->mtu;
fcf45b4c 1174 netif_stop_queue(netdev);
cd0ff491
GFT
1175 if (jme_pseudo_hotplug_enabled(jme))
1176 jme_stop_shutdown_timer(jme);
1177
1178 jme_stop_pcc_timer(jme);
1179 tasklet_disable(&jme->txclean_task);
1180 tasklet_disable(&jme->rxclean_task);
1181 tasklet_disable(&jme->rxempty_task);
1182
1183 if (netif_carrier_ok(netdev)) {
1184 jme_reset_ghc_speed(jme);
1185 jme_disable_rx_engine(jme);
1186 jme_disable_tx_engine(jme);
fcf45b4c
GFT
1187 jme_reset_mac_processor(jme);
1188 jme_free_rx_resources(jme);
1189 jme_free_tx_resources(jme);
192570e0 1190
cd0ff491 1191 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1192 jme_polling_mode(jme);
cd0ff491
GFT
1193
1194 netif_carrier_off(netdev);
fcf45b4c
GFT
1195 }
1196
1197 jme_check_link(netdev, 0);
cd0ff491 1198 if (netif_carrier_ok(netdev)) {
fcf45b4c 1199 rc = jme_setup_rx_resources(jme);
cd0ff491
GFT
1200 if (rc) {
1201 jeprintk(jme->pdev, "Allocating resources for RX error"
fcf45b4c 1202 ", Device STOPPED!\n");
cd0ff491 1203 goto out_enable_tasklet;
fcf45b4c
GFT
1204 }
1205
fcf45b4c 1206 rc = jme_setup_tx_resources(jme);
cd0ff491
GFT
1207 if (rc) {
1208 jeprintk(jme->pdev, "Allocating resources for TX error"
fcf45b4c
GFT
1209 ", Device STOPPED!\n");
1210 goto err_out_free_rx_resources;
1211 }
1212
1213 jme_enable_rx_engine(jme);
1214 jme_enable_tx_engine(jme);
1215
1216 netif_start_queue(netdev);
192570e0 1217
cd0ff491 1218 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1219 jme_interrupt_mode(jme);
192570e0 1220
79ce639c 1221 jme_start_pcc_timer(jme);
cd0ff491
GFT
1222 } else if (jme_pseudo_hotplug_enabled(jme)) {
1223 jme_start_shutdown_timer(jme);
fcf45b4c
GFT
1224 }
1225
cd0ff491 1226 goto out_enable_tasklet;
fcf45b4c
GFT
1227
1228err_out_free_rx_resources:
1229 jme_free_rx_resources(jme);
cd0ff491
GFT
1230out_enable_tasklet:
1231 tasklet_enable(&jme->txclean_task);
1232 tasklet_hi_enable(&jme->rxclean_task);
1233 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT
1234out:
1235 atomic_inc(&jme->link_changing);
3bf61c55 1236}
d7699f87 1237
3bf61c55
GFT
1238static void
1239jme_rx_clean_tasklet(unsigned long arg)
1240{
cd0ff491 1241 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1242 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1243
192570e0
GFT
1244 jme_process_receive(jme, jme->rx_ring_size);
1245 ++(dpi->intr_cnt);
42b1055e 1246
192570e0 1247}
fcf45b4c 1248
192570e0 1249static int
cdcdc9eb 1250jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1251{
cdcdc9eb 1252 struct jme_adapter *jme = jme_napi_priv(holder);
192570e0
GFT
1253 struct net_device *netdev = jme->dev;
1254 int rest;
fcf45b4c 1255
cdcdc9eb 1256 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1257
cd0ff491 1258 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1259 atomic_dec(&jme->rx_empty);
192570e0
GFT
1260 ++(NET_STAT(jme).rx_dropped);
1261 jme_restart_rx_engine(jme);
1262 }
1263 atomic_inc(&jme->rx_empty);
1264
cd0ff491 1265 if (rest) {
cdcdc9eb 1266 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT
1267 jme_interrupt_mode(jme);
1268 }
1269
cdcdc9eb
GFT
1270 JME_NAPI_WEIGHT_SET(budget, rest);
1271 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT
1272}
1273
1274static void
1275jme_rx_empty_tasklet(unsigned long arg)
1276{
cd0ff491 1277 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1278
cd0ff491 1279 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1280 return;
1281
cd0ff491 1282 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1283 return;
1284
cd0ff491 1285 msg_rx_status(jme, "RX Queue Full!\n");
29bdd921 1286
fcf45b4c 1287 jme_rx_clean_tasklet(arg);
cdcdc9eb 1288
cd0ff491 1289 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT
1290 atomic_dec(&jme->rx_empty);
1291 ++(NET_STAT(jme).rx_dropped);
1292 jme_restart_rx_engine(jme);
1293 }
1294 atomic_inc(&jme->rx_empty);
4330c2f2
GFT
1295}
1296
3bf61c55 1297static void
b3821cc5
GFT
1298jme_wake_queue_if_stopped(struct jme_adapter *jme)
1299{
1300 struct jme_ring *txring = jme->txring;
1301
1302 smp_wmb();
cd0ff491 1303 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1304 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
cd0ff491 1305 msg_tx_done(jme, "TX Queue Waked.\n");
b3821cc5 1306 netif_wake_queue(jme->dev);
b3821cc5
GFT
1307 }
1308
1309}
1310
1311static void
3bf61c55 1312jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1313{
cd0ff491 1314 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1315 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1316 struct txdesc *txdesc = txring->desc;
3bf61c55 1317 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1318 int i, j, cnt = 0, max, err, mask;
3bf61c55 1319
cd0ff491
GFT
1320 tx_dbg(jme, "Into txclean.\n");
1321
1322 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1323 goto out;
1324
cd0ff491 1325 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1326 goto out;
1327
cd0ff491 1328 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1329 goto out;
1330
b3821cc5
GFT
1331 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1332 mask = jme->tx_ring_mask;
3bf61c55 1333
cd0ff491 1334 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT
1335
1336 ctxbi = txbi + i;
1337
cd0ff491 1338 if (likely(ctxbi->skb &&
b3821cc5 1339 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1340
cd0ff491
GFT
1341 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1342 i, ctxbi->nr_desc, jiffies);
3bf61c55 1343
cd0ff491 1344 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1345
cd0ff491 1346 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT
1347 ttxbi = txbi + ((i + j) & (mask));
1348 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1349
b3821cc5 1350 pci_unmap_page(jme->pdev,
3bf61c55
GFT
1351 ttxbi->mapping,
1352 ttxbi->len,
1353 PCI_DMA_TODEVICE);
1354
3bf61c55
GFT
1355 ttxbi->mapping = 0;
1356 ttxbi->len = 0;
1357 }
1358
1359 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT
1360
1361 cnt += ctxbi->nr_desc;
1362
cd0ff491 1363 if (unlikely(err)) {
8c198884 1364 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1365 } else {
8c198884 1366 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT
1367 NET_STAT(jme).tx_bytes += ctxbi->len;
1368 }
1369
1370 ctxbi->skb = NULL;
1371 ctxbi->len = 0;
cdcdc9eb 1372 ctxbi->start_xmit = 0;
cd0ff491
GFT
1373
1374 } else {
3bf61c55
GFT
1375 break;
1376 }
1377
b3821cc5 1378 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT
1379
1380 ctxbi->nr_desc = 0;
d7699f87
GFT
1381 }
1382
cd0ff491 1383 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
cdcdc9eb 1384 atomic_set(&txring->next_to_clean, i);
79ce639c 1385 atomic_add(cnt, &txring->nr_free);
3bf61c55 1386
b3821cc5
GFT
1387 jme_wake_queue_if_stopped(jme);
1388
fcf45b4c
GFT
1389out:
1390 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1391}
1392
79ce639c 1393static void
cd0ff491 1394jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1395{
3bf61c55
GFT
1396 /*
1397 * Disable interrupt
1398 */
1399 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1400
cd0ff491 1401 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT
1402 /*
1403 * Link change event is critical
1404 * all other events are ignored
1405 */
1406 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1407 tasklet_schedule(&jme->linkch_task);
29bdd921 1408 goto out_reenable;
fcf45b4c 1409 }
d7699f87 1410
cd0ff491 1411 if (intrstat & INTR_TMINTR) {
47220951 1412 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1413 tasklet_schedule(&jme->pcc_task);
47220951 1414 }
79ce639c 1415
cd0ff491 1416 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1417 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1418 tasklet_schedule(&jme->txclean_task);
47220951
GFT
1419 }
1420
cd0ff491 1421 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT
1422 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1423 INTR_PCCRX0 |
1424 INTR_RX0EMP)) |
1425 INTR_RX0);
1426 }
d7699f87 1427
cd0ff491
GFT
1428 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1429 if (intrstat & INTR_RX0EMP)
192570e0
GFT
1430 atomic_inc(&jme->rx_empty);
1431
cd0ff491
GFT
1432 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1433 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1434 jme_polling_mode(jme);
cdcdc9eb 1435 JME_RX_SCHEDULE(jme);
192570e0
GFT
1436 }
1437 }
cd0ff491
GFT
1438 } else {
1439 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1440 atomic_inc(&jme->rx_empty);
cd0ff491
GFT
1441 tasklet_hi_schedule(&jme->rxempty_task);
1442 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1443 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1444 }
4330c2f2 1445 }
d7699f87 1446
29bdd921 1447out_reenable:
3bf61c55 1448 /*
fcf45b4c 1449 * Re-enable interrupt
3bf61c55 1450 */
fcf45b4c 1451 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT
1452}
1453
1454static irqreturn_t
1455jme_intr(int irq, void *dev_id)
1456{
cd0ff491
GFT
1457 struct net_device *netdev = dev_id;
1458 struct jme_adapter *jme = netdev_priv(netdev);
1459 u32 intrstat;
79ce639c
GFT
1460
1461 intrstat = jread32(jme, JME_IEVE);
1462
1463 /*
1464 * Check if it's really an interrupt for us
1465 */
7ee473a3 1466 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1467 return IRQ_NONE;
79ce639c
GFT
1468
1469 /*
1470 * Check if the device still exist
1471 */
cd0ff491
GFT
1472 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1473 return IRQ_NONE;
79ce639c
GFT
1474
1475 jme_intr_msi(jme, intrstat);
1476
cd0ff491 1477 return IRQ_HANDLED;
d7699f87
GFT
1478}
1479
79ce639c
GFT
1480static irqreturn_t
1481jme_msi(int irq, void *dev_id)
1482{
cd0ff491
GFT
1483 struct net_device *netdev = dev_id;
1484 struct jme_adapter *jme = netdev_priv(netdev);
1485 u32 intrstat;
79ce639c
GFT
1486
1487 pci_dma_sync_single_for_cpu(jme->pdev,
1488 jme->shadow_dma,
cd0ff491 1489 sizeof(u32) * SHADOW_REG_NR,
79ce639c
GFT
1490 PCI_DMA_FROMDEVICE);
1491 intrstat = jme->shadow_regs[SHADOW_IEVE];
1492 jme->shadow_regs[SHADOW_IEVE] = 0;
1493
1494 jme_intr_msi(jme, intrstat);
1495
cd0ff491 1496 return IRQ_HANDLED;
79ce639c
GFT
1497}
1498
79ce639c
GFT
1499static void
1500jme_reset_link(struct jme_adapter *jme)
1501{
1502 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1503}
1504
fcf45b4c
GFT
1505static void
1506jme_restart_an(struct jme_adapter *jme)
1507{
cd0ff491 1508 u32 bmcr;
fcf45b4c 1509
cd0ff491 1510 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT
1511 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1512 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1513 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1514 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT
1515}
1516
1517static int
1518jme_request_irq(struct jme_adapter *jme)
1519{
1520 int rc;
cd0ff491
GFT
1521 struct net_device *netdev = jme->dev;
1522 irq_handler_t handler = jme_intr;
1523 int irq_flags = IRQF_SHARED;
1524
1525 if (!pci_enable_msi(jme->pdev)) {
1526 set_bit(JME_FLAG_MSI, &jme->flags);
1527 handler = jme_msi;
1528 irq_flags = 0;
1529 }
1530
1531 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1532 netdev);
1533 if (rc) {
1534 jeprintk(jme->pdev,
b3821cc5 1535 "Unable to request %s interrupt (return: %d)\n",
cd0ff491
GFT
1536 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1537 rc);
79ce639c 1538
cd0ff491
GFT
1539 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1540 pci_disable_msi(jme->pdev);
1541 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1542 }
cd0ff491 1543 } else {
79ce639c
GFT
1544 netdev->irq = jme->pdev->irq;
1545 }
1546
cd0ff491 1547 return rc;
79ce639c
GFT
1548}
1549
1550static void
1551jme_free_irq(struct jme_adapter *jme)
1552{
cd0ff491
GFT
1553 free_irq(jme->pdev->irq, jme->dev);
1554 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1555 pci_disable_msi(jme->pdev);
1556 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1557 jme->dev->irq = jme->pdev->irq;
cd0ff491 1558 }
fcf45b4c
GFT
1559}
1560
3bf61c55
GFT
1561static int
1562jme_open(struct net_device *netdev)
d7699f87
GFT
1563{
1564 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1565 int rc;
79ce639c 1566
42b1055e 1567 jme_clear_pm(jme);
cdcdc9eb 1568 JME_NAPI_ENABLE(jme);
d7699f87 1569
cd0ff491
GFT
1570 tasklet_enable(&jme->txclean_task);
1571 tasklet_hi_enable(&jme->rxclean_task);
1572 tasklet_hi_enable(&jme->rxempty_task);
1573
79ce639c 1574 rc = jme_request_irq(jme);
cd0ff491 1575 if (rc)
4330c2f2 1576 goto err_out;
79ce639c 1577
4330c2f2 1578 jme_enable_shadow(jme);
d7699f87 1579 jme_start_irq(jme);
42b1055e 1580
cd0ff491 1581 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e
GFT
1582 jme_set_settings(netdev, &jme->old_ecmd);
1583 else
1584 jme_reset_phy_processor(jme);
1585
29bdd921 1586 jme_reset_link(jme);
d7699f87
GFT
1587
1588 return 0;
1589
d7699f87
GFT
1590err_out:
1591 netif_stop_queue(netdev);
1592 netif_carrier_off(netdev);
4330c2f2 1593 return rc;
d7699f87
GFT
1594}
1595
7ee473a3 1596#ifdef CONFIG_PM
42b1055e
GFT
1597static void
1598jme_set_100m_half(struct jme_adapter *jme)
1599{
cd0ff491 1600 u32 bmcr, tmp;
42b1055e
GFT
1601
1602 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1603 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1604 BMCR_SPEED1000 | BMCR_FULLDPLX);
1605 tmp |= BMCR_SPEED100;
1606
1607 if (bmcr != tmp)
1608 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1609
cd0ff491 1610 if (jme->fpgaver)
cdcdc9eb
GFT
1611 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1612 else
1613 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT
1614}
1615
47220951
GFT
1616#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1617static void
1618jme_wait_link(struct jme_adapter *jme)
1619{
cd0ff491 1620 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT
1621
1622 mdelay(1000);
1623 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1624 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT
1625 mdelay(10);
1626 phylink = jme_linkstat_from_phy(jme);
1627 }
1628}
7ee473a3 1629#endif
47220951 1630
cd0ff491 1631static inline void
42b1055e
GFT
1632jme_phy_off(struct jme_adapter *jme)
1633{
1634 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1635}
1636
3bf61c55
GFT
1637static int
1638jme_close(struct net_device *netdev)
d7699f87
GFT
1639{
1640 struct jme_adapter *jme = netdev_priv(netdev);
1641
1642 netif_stop_queue(netdev);
1643 netif_carrier_off(netdev);
1644
1645 jme_stop_irq(jme);
4330c2f2 1646 jme_disable_shadow(jme);
79ce639c 1647 jme_free_irq(jme);
d7699f87 1648
cdcdc9eb 1649 JME_NAPI_DISABLE(jme);
192570e0 1650
4330c2f2
GFT
1651 tasklet_kill(&jme->linkch_task);
1652 tasklet_kill(&jme->txclean_task);
1653 tasklet_kill(&jme->rxclean_task);
fcf45b4c 1654 tasklet_kill(&jme->rxempty_task);
8c198884 1655
cd0ff491
GFT
1656 jme_reset_ghc_speed(jme);
1657 jme_disable_rx_engine(jme);
1658 jme_disable_tx_engine(jme);
8c198884 1659 jme_reset_mac_processor(jme);
d7699f87
GFT
1660 jme_free_rx_resources(jme);
1661 jme_free_tx_resources(jme);
42b1055e 1662 jme->phylink = 0;
b3821cc5
GFT
1663 jme_phy_off(jme);
1664
1665 return 0;
1666}
1667
1668static int
1669jme_alloc_txdesc(struct jme_adapter *jme,
1670 struct sk_buff *skb)
1671{
1672 struct jme_ring *txring = jme->txring;
1673 int idx, nr_alloc, mask = jme->tx_ring_mask;
1674
1675 idx = txring->next_to_use;
1676 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1677
cd0ff491 1678 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT
1679 return -1;
1680
1681 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1682
b3821cc5
GFT
1683 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1684
1685 return idx;
1686}
1687
1688static void
1689jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1690 struct txdesc *txdesc,
b3821cc5
GFT
1691 struct jme_buffer_info *txbi,
1692 struct page *page,
cd0ff491
GFT
1693 u32 page_offset,
1694 u32 len,
1695 u8 hidma)
b3821cc5
GFT
1696{
1697 dma_addr_t dmaaddr;
1698
1699 dmaaddr = pci_map_page(pdev,
1700 page,
1701 page_offset,
1702 len,
1703 PCI_DMA_TODEVICE);
1704
1705 pci_dma_sync_single_for_device(pdev,
1706 dmaaddr,
1707 len,
1708 PCI_DMA_TODEVICE);
1709
1710 txdesc->dw[0] = 0;
1711 txdesc->dw[1] = 0;
1712 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1713 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT
1714 txdesc->desc2.datalen = cpu_to_le16(len);
1715 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1716 txdesc->desc2.bufaddrl = cpu_to_le32(
1717 (__u64)dmaaddr & 0xFFFFFFFFUL);
1718
1719 txbi->mapping = dmaaddr;
1720 txbi->len = len;
1721}
1722
1723static void
1724jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1725{
1726 struct jme_ring *txring = jme->txring;
cd0ff491 1727 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1728 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1729 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT
1730 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1731 int mask = jme->tx_ring_mask;
1732 struct skb_frag_struct *frag;
cd0ff491 1733 u32 len;
b3821cc5 1734
cd0ff491
GFT
1735 for (i = 0 ; i < nr_frags ; ++i) {
1736 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT
1737 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1738 ctxbi = txbi + ((idx + i + 2) & (mask));
1739
1740 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1741 frag->page_offset, frag->size, hidma);
42b1055e 1742 }
b3821cc5 1743
cd0ff491 1744 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT
1745 ctxdesc = txdesc + ((idx + 1) & (mask));
1746 ctxbi = txbi + ((idx + 1) & (mask));
1747 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1748 offset_in_page(skb->data), len, hidma);
1749
1750}
1751
1752static int
1753jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1754{
cd0ff491 1755 if (unlikely(skb_shinfo(skb)->gso_size &&
b3821cc5
GFT
1756 skb_header_cloned(skb) &&
1757 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1758 dev_kfree_skb(skb);
1759 return -1;
1760 }
1761
1762 return 0;
1763}
1764
1765static int
1766jme_tx_tso(struct sk_buff *skb,
cd0ff491 1767 u16 *mss, u8 *flags)
b3821cc5 1768{
cd0ff491
GFT
1769 *mss = skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT;
1770 if (*mss) {
b3821cc5
GFT
1771 *flags |= TXFLAG_LSEN;
1772
cd0ff491 1773 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT
1774 struct iphdr *iph = ip_hdr(skb);
1775
1776 iph->check = 0;
cd0ff491 1777 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT
1778 iph->daddr, 0,
1779 IPPROTO_TCP,
1780 0);
cd0ff491 1781 } else {
b3821cc5
GFT
1782 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1783
cd0ff491 1784 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT
1785 &ip6h->daddr, 0,
1786 IPPROTO_TCP,
1787 0);
1788 }
1789
1790 return 0;
1791 }
1792
1793 return 1;
1794}
1795
1796static void
cd0ff491 1797jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1798{
cd0ff491
GFT
1799 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1800 u8 ip_proto;
b3821cc5
GFT
1801
1802 switch (skb->protocol) {
cd0ff491 1803 case htons(ETH_P_IP):
b3821cc5
GFT
1804 ip_proto = ip_hdr(skb)->protocol;
1805 break;
cd0ff491 1806 case htons(ETH_P_IPV6):
b3821cc5
GFT
1807 ip_proto = ipv6_hdr(skb)->nexthdr;
1808 break;
1809 default:
1810 ip_proto = 0;
1811 break;
1812 }
1813
cd0ff491 1814 switch (ip_proto) {
b3821cc5
GFT
1815 case IPPROTO_TCP:
1816 *flags |= TXFLAG_TCPCS;
1817 break;
1818 case IPPROTO_UDP:
1819 *flags |= TXFLAG_UDPCS;
1820 break;
1821 default:
cd0ff491 1822 msg_tx_err(jme, "Error upper layer protocol.\n");
b3821cc5
GFT
1823 break;
1824 }
1825 }
1826}
1827
cd0ff491
GFT
1828static inline void
1829jme_tx_vlan(struct sk_buff *skb, u16 *vlan, u8 *flags)
b3821cc5 1830{
cd0ff491 1831 if (vlan_tx_tag_present(skb)) {
b3821cc5
GFT
1832 *flags |= TXFLAG_TAGON;
1833 *vlan = vlan_tx_tag_get(skb);
42b1055e 1834 }
b3821cc5
GFT
1835}
1836
1837static int
1838jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1839{
1840 struct jme_ring *txring = jme->txring;
cd0ff491 1841 struct txdesc *txdesc;
b3821cc5 1842 struct jme_buffer_info *txbi;
cd0ff491 1843 u8 flags;
b3821cc5 1844
cd0ff491 1845 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT
1846 txbi = txring->bufinf + idx;
1847
1848 txdesc->dw[0] = 0;
1849 txdesc->dw[1] = 0;
1850 txdesc->dw[2] = 0;
1851 txdesc->dw[3] = 0;
1852 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1853 /*
1854 * Set OWN bit at final.
1855 * When kernel transmit faster than NIC.
1856 * And NIC trying to send this descriptor before we tell
1857 * it to start sending this TX queue.
1858 * Other fields are already filled correctly.
1859 */
1860 wmb();
1861 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT
1862 /*
1863 * Set checksum flags while not tso
1864 */
1865 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1866 jme_tx_csum(jme, skb, &flags);
b3821cc5
GFT
1867 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1868 txdesc->desc1.flags = flags;
1869 /*
1870 * Set tx buffer info after telling NIC to send
1871 * For better tx_clean timing
1872 */
1873 wmb();
1874 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1875 txbi->skb = skb;
1876 txbi->len = skb->len;
cd0ff491
GFT
1877 txbi->start_xmit = jiffies;
1878 if (!txbi->start_xmit)
8d27293f 1879 txbi->start_xmit = (0UL-1);
d7699f87
GFT
1880
1881 return 0;
1882}
1883
b3821cc5
GFT
1884static void
1885jme_stop_queue_if_full(struct jme_adapter *jme)
1886{
1887 struct jme_ring *txring = jme->txring;
cd0ff491
GFT
1888 struct jme_buffer_info *txbi = txring->bufinf;
1889 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 1890
cd0ff491 1891 txbi += idx;
b3821cc5
GFT
1892
1893 smp_wmb();
cd0ff491 1894 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 1895 netif_stop_queue(jme->dev);
cd0ff491 1896 msg_tx_queued(jme, "TX Queue Paused.\n");
b3821cc5 1897 smp_wmb();
cd0ff491
GFT
1898 if (atomic_read(&txring->nr_free)
1899 >= (jme->tx_wake_threshold)) {
b3821cc5 1900 netif_wake_queue(jme->dev);
cd0ff491 1901 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
b3821cc5
GFT
1902 }
1903 }
1904
cd0ff491 1905 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT
1906 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1907 txbi->skb)) {
1908 netif_stop_queue(jme->dev);
cd0ff491 1909 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
cdcdc9eb 1910 }
b3821cc5
GFT
1911}
1912
3bf61c55
GFT
1913/*
1914 * This function is already protected by netif_tx_lock()
1915 */
cd0ff491 1916
3bf61c55
GFT
1917static int
1918jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 1919{
cd0ff491 1920 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 1921 int idx;
d7699f87 1922
cd0ff491 1923 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT
1924 ++(NET_STAT(jme).tx_dropped);
1925 return NETDEV_TX_OK;
1926 }
1927
1928 idx = jme_alloc_txdesc(jme, skb);
79ce639c 1929
cd0ff491 1930 if (unlikely(idx < 0)) {
b3821cc5 1931 netif_stop_queue(netdev);
cd0ff491 1932 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
d7699f87 1933
cd0ff491 1934 return NETDEV_TX_BUSY;
b3821cc5
GFT
1935 }
1936
1937 jme_map_tx_skb(jme, skb, idx);
1938 jme_fill_first_tx_desc(jme, skb, idx);
1939
4330c2f2
GFT
1940 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1941 TXCS_SELECT_QUEUE0 |
1942 TXCS_QUEUE0S |
1943 TXCS_ENABLE);
d7699f87
GFT
1944 netdev->trans_start = jiffies;
1945
cd0ff491
GFT
1946 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1947 skb_shinfo(skb)->nr_frags + 2,
1948 jiffies);
b3821cc5
GFT
1949 jme_stop_queue_if_full(jme);
1950
cd0ff491 1951 return NETDEV_TX_OK;
d7699f87
GFT
1952}
1953
3bf61c55
GFT
1954static int
1955jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 1956{
cd0ff491 1957 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1958 struct sockaddr *addr = p;
cd0ff491 1959 u32 val;
d7699f87 1960
cd0ff491 1961 if (netif_running(netdev))
d7699f87
GFT
1962 return -EBUSY;
1963
cd0ff491 1964 spin_lock_bh(&jme->macaddr_lock);
d7699f87
GFT
1965 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1966
186fc259
GFT
1967 val = (addr->sa_data[3] & 0xff) << 24 |
1968 (addr->sa_data[2] & 0xff) << 16 |
1969 (addr->sa_data[1] & 0xff) << 8 |
1970 (addr->sa_data[0] & 0xff);
4330c2f2 1971 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT
1972 val = (addr->sa_data[5] & 0xff) << 8 |
1973 (addr->sa_data[4] & 0xff);
4330c2f2 1974 jwrite32(jme, JME_RXUMA_HI, val);
cd0ff491 1975 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT
1976
1977 return 0;
1978}
1979
3bf61c55
GFT
1980static void
1981jme_set_multi(struct net_device *netdev)
d7699f87 1982{
3bf61c55 1983 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1984 u32 mc_hash[2] = {};
d7699f87
GFT
1985 int i;
1986
cd0ff491 1987 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT
1988
1989 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 1990
cd0ff491 1991 if (netdev->flags & IFF_PROMISC) {
8c198884 1992 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 1993 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 1994 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 1995 } else if (netdev->flags & IFF_MULTICAST) {
3bf61c55
GFT
1996 struct dev_mc_list *mclist;
1997 int bit_nr;
d7699f87 1998
8c198884 1999 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
3bf61c55
GFT
2000 for (i = 0, mclist = netdev->mc_list;
2001 mclist && i < netdev->mc_count;
2002 ++i, mclist = mclist->next) {
2003
cd0ff491
GFT
2004 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2005 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2006 }
d7699f87 2007
4330c2f2
GFT
2008 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2009 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
2010 }
2011
d7699f87 2012 wmb();
8c198884
GFT
2013 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2014
cd0ff491 2015 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT
2016}
2017
3bf61c55 2018static int
8c198884 2019jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2020{
cd0ff491 2021 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2022
cd0ff491 2023 if (new_mtu == jme->old_mtu)
29bdd921
GFT
2024 return 0;
2025
cd0ff491
GFT
2026 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2027 ((new_mtu) < IPV6_MIN_MTU))
2028 return -EINVAL;
79ce639c 2029
cd0ff491 2030 if (new_mtu > 4000) {
79ce639c
GFT
2031 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2032 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2033 jme_restart_rx_engine(jme);
cd0ff491 2034 } else {
79ce639c
GFT
2035 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2036 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2037 jme_restart_rx_engine(jme);
2038 }
2039
cd0ff491 2040 if (new_mtu > 1900) {
b3821cc5
GFT
2041 netdev->features &= ~(NETIF_F_HW_CSUM |
2042 NETIF_F_TSO |
2043 NETIF_F_TSO6);
cd0ff491
GFT
2044 } else {
2045 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
b3821cc5 2046 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491 2047 if (test_bit(JME_FLAG_TSO, &jme->flags))
b3821cc5 2048 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT
2049 }
2050
cd0ff491
GFT
2051 netdev->mtu = new_mtu;
2052 jme_reset_link(jme);
79ce639c
GFT
2053
2054 return 0;
d7699f87
GFT
2055}
2056
3bf61c55 2057static void
8c198884
GFT
2058jme_tx_timeout(struct net_device *netdev)
2059{
cd0ff491 2060 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2061
cdcdc9eb
GFT
2062 jme->phylink = 0;
2063 jme_reset_phy_processor(jme);
cd0ff491 2064 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT
2065 jme_set_settings(netdev, &jme->old_ecmd);
2066
8c198884 2067 /*
cdcdc9eb 2068 * Force to Reset the link again
8c198884 2069 */
29bdd921 2070 jme_reset_link(jme);
8c198884
GFT
2071}
2072
2073static void
42b1055e
GFT
2074jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2075{
2076 struct jme_adapter *jme = netdev_priv(netdev);
2077
2078 jme->vlgrp = grp;
2079}
2080
2081static void
3bf61c55
GFT
2082jme_get_drvinfo(struct net_device *netdev,
2083 struct ethtool_drvinfo *info)
d7699f87 2084{
cd0ff491 2085 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2086
cd0ff491
GFT
2087 strcpy(info->driver, DRV_NAME);
2088 strcpy(info->version, DRV_VERSION);
2089 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT
2090}
2091
3bf61c55 2092static int
8c198884
GFT
2093jme_get_regs_len(struct net_device *netdev)
2094{
cd0ff491 2095 return JME_REG_LEN;
8c198884
GFT
2096}
2097
2098static void
cd0ff491 2099mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT
2100{
2101 int i;
2102
cd0ff491 2103 for (i = 0 ; i < len ; i += 4)
79ce639c 2104 p[i >> 2] = jread32(jme, reg + i);
186fc259 2105}
8c198884 2106
186fc259 2107static void
cd0ff491 2108mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT
2109{
2110 int i;
cd0ff491 2111 u16 *p16 = (u16 *)p;
186fc259 2112
cd0ff491 2113 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2114 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT
2115}
2116
2117static void
2118jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2119{
cd0ff491
GFT
2120 struct jme_adapter *jme = netdev_priv(netdev);
2121 u32 *p32 = (u32 *)p;
8c198884 2122
186fc259 2123 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT
2124
2125 regs->version = 1;
2126 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2127
2128 p32 += 0x100 >> 2;
2129 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2130
2131 p32 += 0x100 >> 2;
2132 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2133
2134 p32 += 0x100 >> 2;
2135 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2136
186fc259
GFT
2137 p32 += 0x100 >> 2;
2138 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT
2139}
2140
2141static int
2142jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2143{
2144 struct jme_adapter *jme = netdev_priv(netdev);
2145
8c198884
GFT
2146 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2147 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2148
cd0ff491 2149 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT
2150 ecmd->use_adaptive_rx_coalesce = false;
2151 ecmd->rx_coalesce_usecs = 0;
2152 ecmd->rx_max_coalesced_frames = 0;
2153 return 0;
2154 }
2155
2156 ecmd->use_adaptive_rx_coalesce = true;
2157
cd0ff491 2158 switch (jme->dpi.cur) {
8c198884
GFT
2159 case PCC_P1:
2160 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2161 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2162 break;
2163 case PCC_P2:
2164 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2165 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2166 break;
2167 case PCC_P3:
2168 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2169 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2170 break;
2171 default:
2172 break;
2173 }
2174
2175 return 0;
2176}
2177
192570e0
GFT
2178static int
2179jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2180{
2181 struct jme_adapter *jme = netdev_priv(netdev);
2182 struct dynpcc_info *dpi = &(jme->dpi);
2183
cd0ff491 2184 if (netif_running(netdev))
cdcdc9eb
GFT
2185 return -EBUSY;
2186
cd0ff491
GFT
2187 if (ecmd->use_adaptive_rx_coalesce
2188 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2189 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2190 jme->jme_rx = netif_rx;
2191 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT
2192 dpi->cur = PCC_P1;
2193 dpi->attempt = PCC_P1;
2194 dpi->cnt = 0;
2195 jme_set_rx_pcc(jme, PCC_P1);
2196 jme_interrupt_mode(jme);
cd0ff491
GFT
2197 } else if (!(ecmd->use_adaptive_rx_coalesce)
2198 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2199 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2200 jme->jme_rx = netif_receive_skb;
2201 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT
2202 jme_interrupt_mode(jme);
2203 }
2204
2205 return 0;
2206}
2207
8c198884
GFT
2208static void
2209jme_get_pauseparam(struct net_device *netdev,
2210 struct ethtool_pauseparam *ecmd)
2211{
2212 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2213 u32 val;
8c198884
GFT
2214
2215 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2216 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2217
cd0ff491
GFT
2218 spin_lock_bh(&jme->phy_lock);
2219 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2220 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT
2221
2222 ecmd->autoneg =
2223 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT
2224}
2225
2226static int
2227jme_set_pauseparam(struct net_device *netdev,
2228 struct ethtool_pauseparam *ecmd)
2229{
2230 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2231 u32 val;
8c198884 2232
cd0ff491 2233 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT
2234 (ecmd->tx_pause != 0)) {
2235
cd0ff491 2236 if (ecmd->tx_pause)
8c198884
GFT
2237 jme->reg_txpfc |= TXPFC_PF_EN;
2238 else
2239 jme->reg_txpfc &= ~TXPFC_PF_EN;
2240
2241 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2242 }
2243
cd0ff491
GFT
2244 spin_lock_bh(&jme->rxmcs_lock);
2245 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT
2246 (ecmd->rx_pause != 0)) {
2247
cd0ff491 2248 if (ecmd->rx_pause)
8c198884
GFT
2249 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2250 else
2251 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2252
2253 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2254 }
cd0ff491 2255 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2256
cd0ff491
GFT
2257 spin_lock_bh(&jme->phy_lock);
2258 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2259 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT
2260 (ecmd->autoneg != 0)) {
2261
cd0ff491 2262 if (ecmd->autoneg)
8c198884
GFT
2263 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2264 else
2265 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2266
b3821cc5
GFT
2267 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2268 MII_ADVERTISE, val);
8c198884 2269 }
cd0ff491 2270 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT
2271
2272 return 0;
2273}
2274
29bdd921
GFT
2275static void
2276jme_get_wol(struct net_device *netdev,
2277 struct ethtool_wolinfo *wol)
2278{
2279 struct jme_adapter *jme = netdev_priv(netdev);
2280
2281 wol->supported = WAKE_MAGIC | WAKE_PHY;
2282
2283 wol->wolopts = 0;
2284
cd0ff491 2285 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT
2286 wol->wolopts |= WAKE_PHY;
2287
cd0ff491 2288 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT
2289 wol->wolopts |= WAKE_MAGIC;
2290
2291}
2292
2293static int
2294jme_set_wol(struct net_device *netdev,
2295 struct ethtool_wolinfo *wol)
2296{
2297 struct jme_adapter *jme = netdev_priv(netdev);
2298
cd0ff491 2299 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT
2300 WAKE_UCAST |
2301 WAKE_MCAST |
2302 WAKE_BCAST |
2303 WAKE_ARP))
2304 return -EOPNOTSUPP;
2305
2306 jme->reg_pmcs = 0;
2307
cd0ff491 2308 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT
2309 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2310
cd0ff491 2311 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT
2312 jme->reg_pmcs |= PMCS_MFEN;
2313
cd0ff491 2314 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2315
29bdd921
GFT
2316 return 0;
2317}
b3821cc5 2318
8c198884 2319static int
3bf61c55
GFT
2320jme_get_settings(struct net_device *netdev,
2321 struct ethtool_cmd *ecmd)
d7699f87
GFT
2322{
2323 struct jme_adapter *jme = netdev_priv(netdev);
2324 int rc;
8c198884 2325
cd0ff491 2326 spin_lock_bh(&jme->phy_lock);
d7699f87 2327 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2328 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT
2329 return rc;
2330}
2331
3bf61c55
GFT
2332static int
2333jme_set_settings(struct net_device *netdev,
2334 struct ethtool_cmd *ecmd)
d7699f87
GFT
2335{
2336 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2337 int rc, fdc = 0;
fcf45b4c 2338
cd0ff491 2339 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT
2340 return -EINVAL;
2341
cd0ff491 2342 if (jme->mii_if.force_media &&
79ce639c
GFT
2343 ecmd->autoneg != AUTONEG_ENABLE &&
2344 (jme->mii_if.full_duplex != ecmd->duplex))
2345 fdc = 1;
2346
cd0ff491 2347 spin_lock_bh(&jme->phy_lock);
d7699f87 2348 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2349 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2350
cd0ff491 2351 if (!rc && fdc)
79ce639c
GFT
2352 jme_reset_link(jme);
2353
cd0ff491
GFT
2354 if (!rc) {
2355 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT
2356 jme->old_ecmd = *ecmd;
2357 }
2358
d7699f87
GFT
2359 return rc;
2360}
2361
cd0ff491 2362static u32
3bf61c55
GFT
2363jme_get_link(struct net_device *netdev)
2364{
d7699f87
GFT
2365 struct jme_adapter *jme = netdev_priv(netdev);
2366 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2367}
2368
8c198884 2369static u32
cd0ff491
GFT
2370jme_get_msglevel(struct net_device *netdev)
2371{
2372 struct jme_adapter *jme = netdev_priv(netdev);
2373 return jme->msg_enable;
2374}
2375
2376static void
2377jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2378{
cd0ff491
GFT
2379 struct jme_adapter *jme = netdev_priv(netdev);
2380 jme->msg_enable = value;
2381}
8c198884 2382
cd0ff491
GFT
2383static u32
2384jme_get_rx_csum(struct net_device *netdev)
2385{
2386 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2387 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2388}
2389
2390static int
2391jme_set_rx_csum(struct net_device *netdev, u32 on)
2392{
cd0ff491 2393 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2394
cd0ff491
GFT
2395 spin_lock_bh(&jme->rxmcs_lock);
2396 if (on)
8c198884
GFT
2397 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2398 else
2399 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2400 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2401 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT
2402
2403 return 0;
2404}
2405
2406static int
2407jme_set_tx_csum(struct net_device *netdev, u32 on)
2408{
cd0ff491 2409 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2410
cd0ff491
GFT
2411 if (on) {
2412 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2413 if (netdev->mtu <= 1900)
b3821cc5 2414 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491
GFT
2415 } else {
2416 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
8c198884 2417 netdev->features &= ~NETIF_F_HW_CSUM;
b3821cc5 2418 }
8c198884
GFT
2419
2420 return 0;
2421}
2422
2423static int
b3821cc5
GFT
2424jme_set_tso(struct net_device *netdev, u32 on)
2425{
cd0ff491 2426 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2427
cd0ff491
GFT
2428 if (on) {
2429 set_bit(JME_FLAG_TSO, &jme->flags);
2430 if (netdev->mtu <= 1900)
b3821cc5 2431 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT
2432 } else {
2433 clear_bit(JME_FLAG_TSO, &jme->flags);
2434 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT
2435 }
2436
cd0ff491 2437 return 0;
b3821cc5
GFT
2438}
2439
2440static int
8c198884
GFT
2441jme_nway_reset(struct net_device *netdev)
2442{
cd0ff491 2443 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2444 jme_restart_an(jme);
2445 return 0;
2446}
2447
cd0ff491 2448static u8
186fc259
GFT
2449jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2450{
cd0ff491 2451 u32 val;
186fc259
GFT
2452 int to;
2453
2454 val = jread32(jme, JME_SMBCSR);
2455 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2456 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2457 msleep(1);
2458 val = jread32(jme, JME_SMBCSR);
2459 }
cd0ff491
GFT
2460 if (!to) {
2461 msg_hw(jme, "SMB Bus Busy.\n");
186fc259
GFT
2462 return 0xFF;
2463 }
2464
2465 jwrite32(jme, JME_SMBINTF,
2466 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2467 SMBINTF_HWRWN_READ |
2468 SMBINTF_HWCMD);
2469
2470 val = jread32(jme, JME_SMBINTF);
2471 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2472 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2473 msleep(1);
2474 val = jread32(jme, JME_SMBINTF);
2475 }
cd0ff491
GFT
2476 if (!to) {
2477 msg_hw(jme, "SMB Bus Busy.\n");
186fc259
GFT
2478 return 0xFF;
2479 }
2480
2481 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2482}
2483
2484static void
cd0ff491 2485jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2486{
cd0ff491 2487 u32 val;
186fc259
GFT
2488 int to;
2489
2490 val = jread32(jme, JME_SMBCSR);
2491 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2492 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2493 msleep(1);
2494 val = jread32(jme, JME_SMBCSR);
2495 }
cd0ff491
GFT
2496 if (!to) {
2497 msg_hw(jme, "SMB Bus Busy.\n");
186fc259
GFT
2498 return;
2499 }
2500
2501 jwrite32(jme, JME_SMBINTF,
2502 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2503 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2504 SMBINTF_HWRWN_WRITE |
2505 SMBINTF_HWCMD);
2506
2507 val = jread32(jme, JME_SMBINTF);
2508 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2509 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2510 msleep(1);
2511 val = jread32(jme, JME_SMBINTF);
2512 }
cd0ff491
GFT
2513 if (!to) {
2514 msg_hw(jme, "SMB Bus Busy.\n");
186fc259
GFT
2515 return;
2516 }
2517
2518 mdelay(2);
2519}
2520
2521static int
2522jme_get_eeprom_len(struct net_device *netdev)
2523{
cd0ff491
GFT
2524 struct jme_adapter *jme = netdev_priv(netdev);
2525 u32 val;
186fc259 2526 val = jread32(jme, JME_SMBCSR);
cd0ff491 2527 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT
2528}
2529
2530static int
2531jme_get_eeprom(struct net_device *netdev,
2532 struct ethtool_eeprom *eeprom, u8 *data)
2533{
cd0ff491 2534 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2535 int i, offset = eeprom->offset, len = eeprom->len;
2536
2537 /*
8d27293f 2538 * ethtool will check the boundary for us
186fc259
GFT
2539 */
2540 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2541 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2542 data[i] = jme_smb_read(jme, i + offset);
2543
2544 return 0;
2545}
2546
2547static int
2548jme_set_eeprom(struct net_device *netdev,
2549 struct ethtool_eeprom *eeprom, u8 *data)
2550{
cd0ff491 2551 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2552 int i, offset = eeprom->offset, len = eeprom->len;
2553
2554 if (eeprom->magic != JME_EEPROM_MAGIC)
2555 return -EINVAL;
2556
2557 /*
8d27293f 2558 * ethtool will check the boundary for us
186fc259 2559 */
cd0ff491 2560 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2561 jme_smb_write(jme, i + offset, data[i]);
2562
2563 return 0;
2564}
2565
d7699f87 2566static const struct ethtool_ops jme_ethtool_ops = {
cd0ff491 2567 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2568 .get_regs_len = jme_get_regs_len,
2569 .get_regs = jme_get_regs,
2570 .get_coalesce = jme_get_coalesce,
192570e0 2571 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT
2572 .get_pauseparam = jme_get_pauseparam,
2573 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2574 .get_wol = jme_get_wol,
2575 .set_wol = jme_set_wol,
d7699f87
GFT
2576 .get_settings = jme_get_settings,
2577 .set_settings = jme_set_settings,
2578 .get_link = jme_get_link,
cd0ff491
GFT
2579 .get_msglevel = jme_get_msglevel,
2580 .set_msglevel = jme_set_msglevel,
8c198884
GFT
2581 .get_rx_csum = jme_get_rx_csum,
2582 .set_rx_csum = jme_set_rx_csum,
2583 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT
2584 .set_tso = jme_set_tso,
2585 .set_sg = ethtool_op_set_sg,
8c198884 2586 .nway_reset = jme_nway_reset,
186fc259
GFT
2587 .get_eeprom_len = jme_get_eeprom_len,
2588 .get_eeprom = jme_get_eeprom,
2589 .set_eeprom = jme_set_eeprom,
d7699f87
GFT
2590};
2591
3bf61c55
GFT
2592static int
2593jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2594{
cd0ff491
GFT
2595 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2596 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
3bf61c55
GFT
2597 return 1;
2598
cd0ff491
GFT
2599 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2600 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
8c198884
GFT
2601 return 1;
2602
cd0ff491
GFT
2603 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2604 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
3bf61c55
GFT
2605 return 0;
2606
2607 return -1;
2608}
2609
cd0ff491 2610static inline void
cdcdc9eb
GFT
2611jme_phy_init(struct jme_adapter *jme)
2612{
cd0ff491 2613 u16 reg26;
cdcdc9eb
GFT
2614
2615 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2616 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2617}
2618
cd0ff491 2619static inline void
cdcdc9eb 2620jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2621{
cd0ff491 2622 u32 chipmode;
cdcdc9eb
GFT
2623
2624 chipmode = jread32(jme, JME_CHIPMODE);
2625
2626 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 2627 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
42b1055e
GFT
2628}
2629
3bf61c55
GFT
2630static int __devinit
2631jme_init_one(struct pci_dev *pdev,
2632 const struct pci_device_id *ent)
2633{
cdcdc9eb 2634 int rc = 0, using_dac, i;
d7699f87
GFT
2635 struct net_device *netdev;
2636 struct jme_adapter *jme;
cd0ff491
GFT
2637 u16 bmcr, bmsr;
2638 u32 apmc;
d7699f87
GFT
2639
2640 /*
2641 * set up PCI device basics
2642 */
4330c2f2 2643 rc = pci_enable_device(pdev);
cd0ff491
GFT
2644 if (rc) {
2645 jeprintk(pdev, "Cannot enable PCI device.\n");
4330c2f2
GFT
2646 goto err_out;
2647 }
d7699f87 2648
3bf61c55 2649 using_dac = jme_pci_dma64(pdev);
cd0ff491
GFT
2650 if (using_dac < 0) {
2651 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
3bf61c55
GFT
2652 rc = -EIO;
2653 goto err_out_disable_pdev;
2654 }
2655
cd0ff491
GFT
2656 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2657 jeprintk(pdev, "No PCI resource region found.\n");
4330c2f2
GFT
2658 rc = -ENOMEM;
2659 goto err_out_disable_pdev;
2660 }
d7699f87 2661
4330c2f2 2662 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491
GFT
2663 if (rc) {
2664 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
4330c2f2
GFT
2665 goto err_out_disable_pdev;
2666 }
d7699f87
GFT
2667
2668 pci_set_master(pdev);
2669
2670 /*
2671 * alloc and init net device
2672 */
3bf61c55 2673 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491
GFT
2674 if (!netdev) {
2675 jeprintk(pdev, "Cannot allocate netdev structure.\n");
4330c2f2
GFT
2676 rc = -ENOMEM;
2677 goto err_out_release_regions;
d7699f87
GFT
2678 }
2679 netdev->open = jme_open;
2680 netdev->stop = jme_close;
2681 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT
2682 netdev->set_mac_address = jme_set_macaddr;
2683 netdev->set_multicast_list = jme_set_multi;
2684 netdev->change_mtu = jme_change_mtu;
2685 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884
GFT
2686 netdev->tx_timeout = jme_tx_timeout;
2687 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2688 netdev->vlan_rx_register = jme_vlan_rx_register;
3bf61c55 2689 NETDEV_GET_STATS(netdev, &jme_get_stats);
42b1055e 2690 netdev->features = NETIF_F_HW_CSUM |
b3821cc5
GFT
2691 NETIF_F_SG |
2692 NETIF_F_TSO |
2693 NETIF_F_TSO6 |
42b1055e
GFT
2694 NETIF_F_HW_VLAN_TX |
2695 NETIF_F_HW_VLAN_RX;
cd0ff491 2696 if (using_dac)
8c198884 2697 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
2698
2699 SET_NETDEV_DEV(netdev, &pdev->dev);
2700 pci_set_drvdata(pdev, netdev);
2701
2702 /*
2703 * init adapter info
2704 */
2705 jme = netdev_priv(netdev);
2706 jme->pdev = pdev;
2707 jme->dev = netdev;
cdcdc9eb
GFT
2708 jme->jme_rx = netif_rx;
2709 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2710 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2711 jme->phylink = 0;
b3821cc5
GFT
2712 jme->tx_ring_size = 1 << 10;
2713 jme->tx_ring_mask = jme->tx_ring_size - 1;
2714 jme->tx_wake_threshold = 1 << 9;
2715 jme->rx_ring_size = 1 << 9;
2716 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2717 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT
2718 jme->regs = ioremap(pci_resource_start(pdev, 0),
2719 pci_resource_len(pdev, 0));
4330c2f2 2720 if (!(jme->regs)) {
cd0ff491 2721 jeprintk(pdev, "Mapping PCI resource region error.\n");
d7699f87
GFT
2722 rc = -ENOMEM;
2723 goto err_out_free_netdev;
2724 }
4330c2f2 2725 jme->shadow_regs = pci_alloc_consistent(pdev,
cd0ff491
GFT
2726 sizeof(u32) * SHADOW_REG_NR,
2727 &(jme->shadow_dma));
4330c2f2 2728 if (!(jme->shadow_regs)) {
cd0ff491 2729 jeprintk(pdev, "Allocating shadow register mapping error.\n");
4330c2f2
GFT
2730 rc = -ENOMEM;
2731 goto err_out_unmap;
2732 }
2733
cd0ff491
GFT
2734 if (no_pseudohp) {
2735 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2736 jwrite32(jme, JME_APMC, apmc);
2737 } else if (force_pseudohp) {
2738 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2739 jwrite32(jme, JME_APMC, apmc);
2740 }
2741
cdcdc9eb 2742 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2743
d7699f87 2744 spin_lock_init(&jme->phy_lock);
fcf45b4c 2745 spin_lock_init(&jme->macaddr_lock);
8c198884 2746 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2747
fcf45b4c
GFT
2748 atomic_set(&jme->link_changing, 1);
2749 atomic_set(&jme->rx_cleaning, 1);
2750 atomic_set(&jme->tx_cleaning, 1);
192570e0 2751 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2752
79ce639c
GFT
2753 tasklet_init(&jme->pcc_task,
2754 &jme_pcc_tasklet,
2755 (unsigned long) jme);
4330c2f2
GFT
2756 tasklet_init(&jme->linkch_task,
2757 &jme_link_change_tasklet,
2758 (unsigned long) jme);
2759 tasklet_init(&jme->txclean_task,
2760 &jme_tx_clean_tasklet,
2761 (unsigned long) jme);
2762 tasklet_init(&jme->rxclean_task,
2763 &jme_rx_clean_tasklet,
2764 (unsigned long) jme);
fcf45b4c
GFT
2765 tasklet_init(&jme->rxempty_task,
2766 &jme_rx_empty_tasklet,
2767 (unsigned long) jme);
cd0ff491
GFT
2768 tasklet_disable_nosync(&jme->txclean_task);
2769 tasklet_disable_nosync(&jme->rxclean_task);
2770 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT
2771 jme->dpi.cur = PCC_P1;
2772
cd0ff491 2773 jme->reg_ghc = 0;
79ce639c 2774 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
2775 jme->reg_rxmcs = RXMCS_DEFAULT;
2776 jme->reg_txpfc = 0;
47220951 2777 jme->reg_pmcs = PMCS_MFEN;
cd0ff491
GFT
2778 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2779 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 2780
d7699f87 2781 /*
fcf45b4c
GFT
2782 * Get Max Read Req Size from PCI Config Space
2783 */
cd0ff491
GFT
2784 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2785 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2786 switch (jme->mrrs) {
2787 case MRRS_128B:
2788 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2789 break;
2790 case MRRS_256B:
2791 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2792 break;
2793 default:
2794 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2795 break;
fcf45b4c
GFT
2796 };
2797
fcf45b4c 2798 /*
cdcdc9eb 2799 * Must check before reset_mac_processor
d7699f87 2800 */
cdcdc9eb
GFT
2801 jme_check_hw_ver(jme);
2802 jme->mii_if.dev = netdev;
cd0ff491 2803 if (jme->fpgaver) {
cdcdc9eb 2804 jme->mii_if.phy_id = 0;
cd0ff491 2805 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT
2806 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2807 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 2808 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT
2809 jme->mii_if.phy_id = i;
2810 break;
2811 }
2812 }
2813
cd0ff491 2814 if (!jme->mii_if.phy_id) {
cdcdc9eb 2815 rc = -EIO;
cd0ff491 2816 jeprintk(pdev, "Can not find phy_id.\n");
cdcdc9eb
GFT
2817 goto err_out_free_shadow;
2818 }
2819
2820 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 2821 } else {
cdcdc9eb
GFT
2822 jme->mii_if.phy_id = 1;
2823 }
cd0ff491 2824 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
2825 jme->mii_if.supports_gmii = true;
2826 else
2827 jme->mii_if.supports_gmii = false;
cdcdc9eb
GFT
2828 jme->mii_if.mdio_read = jme_mdio_read;
2829 jme->mii_if.mdio_write = jme_mdio_write;
2830
d7699f87 2831 jme_clear_pm(jme);
58c92f28 2832 jme_set_phyfifoa(jme);
cd0ff491
GFT
2833 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2834 if (!jme->fpgaver)
cdcdc9eb 2835 jme_phy_init(jme);
42b1055e 2836 jme_phy_off(jme);
cdcdc9eb
GFT
2837
2838 /*
2839 * Reset MAC processor and reload EEPROM for MAC Address
2840 */
d7699f87 2841 jme_reset_mac_processor(jme);
4330c2f2 2842 rc = jme_reload_eeprom(jme);
cd0ff491
GFT
2843 if (rc) {
2844 jeprintk(pdev,
b3821cc5 2845 "Reload eeprom for reading MAC Address error.\n");
4330c2f2
GFT
2846 goto err_out_free_shadow;
2847 }
d7699f87
GFT
2848 jme_load_macaddr(netdev);
2849
d7699f87
GFT
2850 /*
2851 * Tell stack that we are not ready to work until open()
2852 */
2853 netif_carrier_off(netdev);
2854 netif_stop_queue(netdev);
2855
2856 /*
2857 * Register netdev
2858 */
4330c2f2 2859 rc = register_netdev(netdev);
cd0ff491
GFT
2860 if (rc) {
2861 jeprintk(pdev, "Cannot register net device.\n");
4330c2f2
GFT
2862 goto err_out_free_shadow;
2863 }
d7699f87 2864
cd0ff491 2865 msg_probe(jme,
58c92f28 2866 "JMC250 gigabit%s ver:%x rev:%x "
cd0ff491
GFT
2867 "macaddr:%02x:%02x:%02x:%02x:%02x:%02x\n",
2868 (jme->fpgaver != 0) ? " (FPGA)" : "",
58c92f28
GFT
2869 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2870 jme->rev,
cd0ff491
GFT
2871 netdev->dev_addr[0],
2872 netdev->dev_addr[1],
2873 netdev->dev_addr[2],
2874 netdev->dev_addr[3],
2875 netdev->dev_addr[4],
2876 netdev->dev_addr[5]);
d7699f87
GFT
2877
2878 return 0;
2879
4330c2f2
GFT
2880err_out_free_shadow:
2881 pci_free_consistent(pdev,
cd0ff491 2882 sizeof(u32) * SHADOW_REG_NR,
4330c2f2
GFT
2883 jme->shadow_regs,
2884 jme->shadow_dma);
d7699f87
GFT
2885err_out_unmap:
2886 iounmap(jme->regs);
2887err_out_free_netdev:
2888 pci_set_drvdata(pdev, NULL);
2889 free_netdev(netdev);
4330c2f2
GFT
2890err_out_release_regions:
2891 pci_release_regions(pdev);
d7699f87 2892err_out_disable_pdev:
cd0ff491 2893 pci_disable_device(pdev);
d7699f87 2894err_out:
4330c2f2 2895 return rc;
d7699f87
GFT
2896}
2897
3bf61c55
GFT
2898static void __devexit
2899jme_remove_one(struct pci_dev *pdev)
2900{
d7699f87
GFT
2901 struct net_device *netdev = pci_get_drvdata(pdev);
2902 struct jme_adapter *jme = netdev_priv(netdev);
2903
2904 unregister_netdev(netdev);
4330c2f2 2905 pci_free_consistent(pdev,
cd0ff491 2906 sizeof(u32) * SHADOW_REG_NR,
4330c2f2
GFT
2907 jme->shadow_regs,
2908 jme->shadow_dma);
d7699f87
GFT
2909 iounmap(jme->regs);
2910 pci_set_drvdata(pdev, NULL);
2911 free_netdev(netdev);
2912 pci_release_regions(pdev);
2913 pci_disable_device(pdev);
2914
2915}
2916
7ee473a3 2917#ifdef CONFIG_PM
29bdd921
GFT
2918static int
2919jme_suspend(struct pci_dev *pdev, pm_message_t state)
2920{
2921 struct net_device *netdev = pci_get_drvdata(pdev);
2922 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT
2923
2924 atomic_dec(&jme->link_changing);
2925
2926 netif_device_detach(netdev);
2927 netif_stop_queue(netdev);
2928 jme_stop_irq(jme);
29bdd921 2929
cd0ff491
GFT
2930 tasklet_disable(&jme->txclean_task);
2931 tasklet_disable(&jme->rxclean_task);
2932 tasklet_disable(&jme->rxempty_task);
2933
29bdd921
GFT
2934 jme_disable_shadow(jme);
2935
cd0ff491
GFT
2936 if (netif_carrier_ok(netdev)) {
2937 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT
2938 jme_polling_mode(jme);
2939
29bdd921 2940 jme_stop_pcc_timer(jme);
cd0ff491
GFT
2941 jme_reset_ghc_speed(jme);
2942 jme_disable_rx_engine(jme);
2943 jme_disable_tx_engine(jme);
29bdd921
GFT
2944 jme_reset_mac_processor(jme);
2945 jme_free_rx_resources(jme);
2946 jme_free_tx_resources(jme);
2947 netif_carrier_off(netdev);
2948 jme->phylink = 0;
2949 }
2950
cd0ff491
GFT
2951 tasklet_enable(&jme->txclean_task);
2952 tasklet_hi_enable(&jme->rxclean_task);
2953 tasklet_hi_enable(&jme->rxempty_task);
29bdd921
GFT
2954
2955 pci_save_state(pdev);
cd0ff491 2956 if (jme->reg_pmcs) {
42b1055e 2957 jme_set_100m_half(jme);
47220951 2958
cd0ff491 2959 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
47220951
GFT
2960 jme_wait_link(jme);
2961
29bdd921 2962 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
cd0ff491 2963
42b1055e 2964 pci_enable_wake(pdev, PCI_D3cold, true);
cd0ff491 2965 } else {
42b1055e 2966 jme_phy_off(jme);
29bdd921 2967 }
cd0ff491 2968 pci_set_power_state(pdev, PCI_D3cold);
29bdd921
GFT
2969
2970 return 0;
2971}
2972
2973static int
2974jme_resume(struct pci_dev *pdev)
2975{
2976 struct net_device *netdev = pci_get_drvdata(pdev);
2977 struct jme_adapter *jme = netdev_priv(netdev);
2978
2979 jme_clear_pm(jme);
2980 pci_restore_state(pdev);
2981
cd0ff491 2982 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921
GFT
2983 jme_set_settings(netdev, &jme->old_ecmd);
2984 else
2985 jme_reset_phy_processor(jme);
2986
29bdd921 2987 jme_enable_shadow(jme);
29bdd921
GFT
2988 jme_start_irq(jme);
2989 netif_device_attach(netdev);
2990
2991 atomic_inc(&jme->link_changing);
2992
2993 jme_reset_link(jme);
2994
2995 return 0;
2996}
7ee473a3 2997#endif
29bdd921 2998
d7699f87 2999static struct pci_device_id jme_pci_tbl[] = {
cd0ff491
GFT
3000 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3001 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT
3002 { }
3003};
3004
3005static struct pci_driver jme_driver = {
cd0ff491
GFT
3006 .name = DRV_NAME,
3007 .id_table = jme_pci_tbl,
3008 .probe = jme_init_one,
3009 .remove = __devexit_p(jme_remove_one),
d7699f87 3010#ifdef CONFIG_PM
cd0ff491
GFT
3011 .suspend = jme_suspend,
3012 .resume = jme_resume,
d7699f87 3013#endif /* CONFIG_PM */
d7699f87
GFT
3014};
3015
3bf61c55
GFT
3016static int __init
3017jme_init_module(void)
d7699f87 3018{
4330c2f2
GFT
3019 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
3020 "driver version %s\n", DRV_VERSION);
d7699f87
GFT
3021 return pci_register_driver(&jme_driver);
3022}
3023
3bf61c55
GFT
3024static void __exit
3025jme_cleanup_module(void)
d7699f87
GFT
3026{
3027 pci_unregister_driver(&jme_driver);
3028}
3029
3030module_init(jme_init_module);
3031module_exit(jme_cleanup_module);
3032
3bf61c55 3033MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
3034MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3035MODULE_LICENSE("GPL");
3036MODULE_VERSION(DRV_VERSION);
3037MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3038