jme: Prevent possible read re-order error
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
3bf61c55
GFT
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
d7699f87
GFT
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
2e582300 24#include <linux/version.h>
937ef75a
JP
25#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27#endif
28
d7699f87
GFT
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/mii.h>
36#include <linux/crc32.h>
4330c2f2 37#include <linux/delay.h>
29bdd921 38#include <linux/spinlock.h>
8c198884
GFT
39#include <linux/in.h>
40#include <linux/ip.h>
79ce639c
GFT
41#include <linux/ipv6.h>
42#include <linux/tcp.h>
43#include <linux/udp.h>
42b1055e 44#include <linux/if_vlan.h>
38d1bc09 45#include <linux/slab.h>
3b70a6fa 46#include <net/ip6_checksum.h>
d7699f87
GFT
47#include "jme.h"
48
cd0ff491
GFT
49static int force_pseudohp = -1;
50static int no_pseudohp = -1;
51static int no_extplug = -1;
52module_param(force_pseudohp, int, 0);
53MODULE_PARM_DESC(force_pseudohp,
54 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
55module_param(no_pseudohp, int, 0);
56MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
57module_param(no_extplug, int, 0);
58MODULE_PARM_DESC(no_extplug,
59 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 60
3bf61c55
GFT
61static int
62jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT
63{
64 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 65 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 66
186fc259 67read_again:
cd0ff491 68 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT
69 smi_phy_addr(phy) |
70 smi_reg_addr(reg));
d7699f87
GFT
71
72 wmb();
cd0ff491 73 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 74 udelay(20);
b3821cc5
GFT
75 val = jread32(jme, JME_SMI);
76 if ((val & SMI_OP_REQ) == 0)
3bf61c55 77 break;
cd0ff491 78 }
d7699f87 79
cd0ff491 80 if (i == 0) {
937ef75a 81 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 82 return 0;
cd0ff491 83 }
d7699f87 84
cd0ff491 85 if (again--)
186fc259
GFT
86 goto read_again;
87
cd0ff491 88 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT
89}
90
3bf61c55
GFT
91static void
92jme_mdio_write(struct net_device *netdev,
93 int phy, int reg, int val)
d7699f87
GFT
94{
95 struct jme_adapter *jme = netdev_priv(netdev);
96 int i;
97
3bf61c55
GFT
98 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
99 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
100 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT
101
102 wmb();
cdcdc9eb
GFT
103 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
104 udelay(20);
8d27293f 105 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT
106 break;
107 }
d7699f87 108
3bf61c55 109 if (i == 0)
937ef75a 110 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT
111}
112
cd0ff491 113static inline void
3bf61c55 114jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 115{
cd0ff491 116 u32 val;
3bf61c55
GFT
117
118 jme_mdio_write(jme->dev,
119 jme->mii_if.phy_id,
8c198884
GFT
120 MII_ADVERTISE, ADVERTISE_ALL |
121 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 122
cd0ff491 123 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
124 jme_mdio_write(jme->dev,
125 jme->mii_if.phy_id,
126 MII_CTRL1000,
127 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 128
fcf45b4c
GFT
129 val = jme_mdio_read(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR);
132
133 jme_mdio_write(jme->dev,
134 jme->mii_if.phy_id,
135 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT
136}
137
b3821cc5
GFT
138static void
139jme_setup_wakeup_frame(struct jme_adapter *jme,
cd0ff491 140 u32 *mask, u32 crc, int fnr)
b3821cc5
GFT
141{
142 int i;
143
144 /*
145 * Setup CRC pattern
146 */
147 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
148 wmb();
149 jwrite32(jme, JME_WFODP, crc);
150 wmb();
151
152 /*
153 * Setup Mask
154 */
cd0ff491 155 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT
156 jwrite32(jme, JME_WFOI,
157 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
158 (fnr & WFOI_FRAME_SEL));
159 wmb();
160 jwrite32(jme, JME_WFODP, mask[i]);
161 wmb();
162 }
163}
3bf61c55 164
cd0ff491 165static inline void
3bf61c55
GFT
166jme_reset_mac_processor(struct jme_adapter *jme)
167{
cd0ff491
GFT
168 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
169 u32 crc = 0xCDCDCDCD;
170 u32 gpreg0;
b3821cc5
GFT
171 int i;
172
3bf61c55 173 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 174 udelay(2);
3bf61c55 175 jwrite32(jme, JME_GHC, jme->reg_ghc);
cd0ff491
GFT
176
177 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
178 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
179 jwrite32(jme, JME_RXQDC, 0x00000000);
180 jwrite32(jme, JME_RXNDA, 0x00000000);
181 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
182 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
183 jwrite32(jme, JME_TXQDC, 0x00000000);
184 jwrite32(jme, JME_TXNDA, 0x00000000);
185
4330c2f2
GFT
186 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
187 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 188 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 189 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 190 if (jme->fpgaver)
cdcdc9eb
GFT
191 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
192 else
193 gpreg0 = GPREG0_DEFAULT;
194 jwrite32(jme, JME_GPREG0, gpreg0);
7ee473a3 195 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
d7699f87
GFT
196}
197
cd0ff491
GFT
198static inline void
199jme_reset_ghc_speed(struct jme_adapter *jme)
200{
201 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
202 jwrite32(jme, JME_GHC, jme->reg_ghc);
203}
204
205static inline void
3bf61c55 206jme_clear_pm(struct jme_adapter *jme)
d7699f87 207{
29bdd921 208 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 209 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 210 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT
211}
212
3bf61c55
GFT
213static int
214jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 215{
cd0ff491 216 u32 val;
d7699f87
GFT
217 int i;
218
219 val = jread32(jme, JME_SMBCSR);
220
cd0ff491 221 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT
222 val |= SMBCSR_CNACK;
223 jwrite32(jme, JME_SMBCSR, val);
224 val |= SMBCSR_RELOAD;
225 jwrite32(jme, JME_SMBCSR, val);
226 mdelay(12);
227
cd0ff491 228 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT
229 mdelay(1);
230 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
231 break;
232 }
233
cd0ff491 234 if (i == 0) {
937ef75a 235 pr_err("eeprom reload timeout\n");
d7699f87
GFT
236 return -EIO;
237 }
238 }
3bf61c55 239
d7699f87
GFT
240 return 0;
241}
242
3bf61c55
GFT
243static void
244jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT
245{
246 struct jme_adapter *jme = netdev_priv(netdev);
247 unsigned char macaddr[6];
cd0ff491 248 u32 val;
d7699f87 249
cd0ff491 250 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 251 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT
252 macaddr[0] = (val >> 0) & 0xFF;
253 macaddr[1] = (val >> 8) & 0xFF;
254 macaddr[2] = (val >> 16) & 0xFF;
255 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 256 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT
257 macaddr[4] = (val >> 0) & 0xFF;
258 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT
259 memcpy(netdev->dev_addr, macaddr, 6);
260 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT
261}
262
cd0ff491 263static inline void
3bf61c55
GFT
264jme_set_rx_pcc(struct jme_adapter *jme, int p)
265{
cd0ff491 266 switch (p) {
192570e0
GFT
267 case PCC_OFF:
268 jwrite32(jme, JME_PCCRX0,
269 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
270 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 break;
3bf61c55
GFT
272 case PCC_P1:
273 jwrite32(jme, JME_PCCRX0,
274 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
275 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
276 break;
277 case PCC_P2:
278 jwrite32(jme, JME_PCCRX0,
279 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
280 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
281 break;
282 case PCC_P3:
283 jwrite32(jme, JME_PCCRX0,
284 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
285 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
286 break;
287 default:
288 break;
289 }
192570e0 290 wmb();
3bf61c55 291
cd0ff491 292 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
7ca9ebee 293 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT
294}
295
fcf45b4c 296static void
3bf61c55 297jme_start_irq(struct jme_adapter *jme)
d7699f87 298{
3bf61c55
GFT
299 register struct dynpcc_info *dpi = &(jme->dpi);
300
301 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT
302 dpi->cur = PCC_P1;
303 dpi->attempt = PCC_P1;
304 dpi->cnt = 0;
305
306 jwrite32(jme, JME_PCCTX,
8c198884
GFT
307 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
308 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
309 PCCTXQ0_EN
310 );
311
d7699f87
GFT
312 /*
313 * Enable Interrupts
314 */
315 jwrite32(jme, JME_IENS, INTR_ENABLE);
316}
317
cd0ff491 318static inline void
3bf61c55 319jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
320{
321 /*
322 * Disable Interrupts
323 */
cd0ff491 324 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT
325}
326
cd0ff491 327static u32
cdcdc9eb
GFT
328jme_linkstat_from_phy(struct jme_adapter *jme)
329{
cd0ff491 330 u32 phylink, bmsr;
cdcdc9eb
GFT
331
332 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
333 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 334 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT
335 phylink |= PHY_LINK_AUTONEG_COMPLETE;
336
337 return phylink;
338}
339
cd0ff491 340static inline void
58c92f28 341jme_set_phyfifoa(struct jme_adapter *jme)
cd0ff491
GFT
342{
343 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
344}
345
346static inline void
58c92f28 347jme_set_phyfifob(struct jme_adapter *jme)
cd0ff491
GFT
348{
349 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
350}
351
fcf45b4c
GFT
352static int
353jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
354{
355 struct jme_adapter *jme = netdev_priv(netdev);
7ee473a3 356 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
79ce639c 357 char linkmsg[64];
fcf45b4c 358 int rc = 0;
d7699f87 359
b3821cc5 360 linkmsg[0] = '\0';
cdcdc9eb 361
cd0ff491 362 if (jme->fpgaver)
cdcdc9eb
GFT
363 phylink = jme_linkstat_from_phy(jme);
364 else
365 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 366
cd0ff491
GFT
367 if (phylink & PHY_LINK_UP) {
368 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT
369 /*
370 * If we did not enable AN
371 * Speed/Duplex Info should be obtained from SMI
372 */
373 phylink = PHY_LINK_UP;
374
375 bmcr = jme_mdio_read(jme->dev,
376 jme->mii_if.phy_id,
377 MII_BMCR);
378
379 phylink |= ((bmcr & BMCR_SPEED1000) &&
380 (bmcr & BMCR_SPEED100) == 0) ?
381 PHY_LINK_SPEED_1000M :
382 (bmcr & BMCR_SPEED100) ?
383 PHY_LINK_SPEED_100M :
384 PHY_LINK_SPEED_10M;
385
386 phylink |= (bmcr & BMCR_FULLDPLX) ?
387 PHY_LINK_DUPLEX : 0;
79ce639c 388
b3821cc5 389 strcat(linkmsg, "Forced: ");
cd0ff491 390 } else {
8c198884
GFT
391 /*
392 * Keep polling for speed/duplex resolve complete
393 */
cd0ff491 394 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT
395 --cnt) {
396
397 udelay(1);
8c198884 398
cd0ff491 399 if (jme->fpgaver)
cdcdc9eb
GFT
400 phylink = jme_linkstat_from_phy(jme);
401 else
402 phylink = jread32(jme, JME_PHY_LINK);
8c198884 403 }
cd0ff491 404 if (!cnt)
937ef75a 405 pr_err("Waiting speed resolve timeout\n");
79ce639c 406
b3821cc5 407 strcat(linkmsg, "ANed: ");
d7699f87
GFT
408 }
409
cd0ff491 410 if (jme->phylink == phylink) {
fcf45b4c
GFT
411 rc = 1;
412 goto out;
413 }
cd0ff491 414 if (testonly)
fcf45b4c
GFT
415 goto out;
416
417 jme->phylink = phylink;
418
3b70a6fa
GFT
419 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
420 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
421 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
cd0ff491
GFT
422 switch (phylink & PHY_LINK_SPEED_MASK) {
423 case PHY_LINK_SPEED_10M:
3b70a6fa
GFT
424 ghc |= GHC_SPEED_10M |
425 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 426 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT
427 break;
428 case PHY_LINK_SPEED_100M:
3b70a6fa
GFT
429 ghc |= GHC_SPEED_100M |
430 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 431 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT
432 break;
433 case PHY_LINK_SPEED_1000M:
3b70a6fa
GFT
434 ghc |= GHC_SPEED_1000M |
435 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
cd0ff491 436 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT
437 break;
438 default:
439 break;
d7699f87 440 }
d7699f87 441
cd0ff491 442 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 443 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
7ee473a3 444 ghc |= GHC_DPX;
cd0ff491 445 } else {
d7699f87 446 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
447 TXMCS_BACKOFF |
448 TXMCS_CARRIERSENSE |
449 TXMCS_COLLISION);
8c198884
GFT
450 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
451 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
452 TXTRHD_TXREN |
453 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
454 }
7ee473a3
GFT
455
456 gpreg1 = GPREG1_DEFAULT;
457 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
458 if (!(phylink & PHY_LINK_DUPLEX))
459 gpreg1 |= GPREG1_HALFMODEPATCH;
460 switch (phylink & PHY_LINK_SPEED_MASK) {
461 case PHY_LINK_SPEED_10M:
462 jme_set_phyfifoa(jme);
463 gpreg1 |= GPREG1_RSSPATCH;
464 break;
465 case PHY_LINK_SPEED_100M:
466 jme_set_phyfifob(jme);
467 gpreg1 |= GPREG1_RSSPATCH;
468 break;
469 case PHY_LINK_SPEED_1000M:
470 jme_set_phyfifoa(jme);
471 break;
472 default:
473 break;
474 }
475 }
d7699f87 476
3b70a6fa 477 jwrite32(jme, JME_GPREG1, gpreg1);
fcf45b4c 478 jwrite32(jme, JME_GHC, ghc);
3b70a6fa 479 jme->reg_ghc = ghc;
fcf45b4c 480
3b70a6fa
GFT
481 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
482 "Full-Duplex, " :
483 "Half-Duplex, ");
484 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
485 "MDI-X" :
486 "MDI");
937ef75a 487 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT
488 netif_carrier_on(netdev);
489 } else {
490 if (testonly)
fcf45b4c
GFT
491 goto out;
492
937ef75a 493 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 494 jme->phylink = 0;
cd0ff491 495 netif_carrier_off(netdev);
d7699f87 496 }
fcf45b4c
GFT
497
498out:
499 return rc;
d7699f87
GFT
500}
501
3bf61c55
GFT
502static int
503jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 504{
d7699f87
GFT
505 struct jme_ring *txring = &(jme->txring[0]);
506
507 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
508 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
509 &(txring->dmaalloc),
510 GFP_ATOMIC);
fcf45b4c 511
0ede469c
GFT
512 if (!txring->alloc)
513 goto err_set_null;
d7699f87
GFT
514
515 /*
516 * 16 Bytes align
517 */
cd0ff491 518 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 519 RING_DESC_ALIGN);
4330c2f2 520 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 521 txring->next_to_use = 0;
cdcdc9eb 522 atomic_set(&txring->next_to_clean, 0);
b3821cc5 523 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 524
0ede469c
GFT
525 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
526 jme->tx_ring_size, GFP_ATOMIC);
527 if (unlikely(!(txring->bufinf)))
528 goto err_free_txring;
529
d7699f87 530 /*
b3821cc5 531 * Initialize Transmit Descriptors
d7699f87 532 */
b3821cc5 533 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 534 memset(txring->bufinf, 0,
b3821cc5 535 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT
536
537 return 0;
0ede469c
GFT
538
539err_free_txring:
540 dma_free_coherent(&(jme->pdev->dev),
541 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
542 txring->alloc,
543 txring->dmaalloc);
544
545err_set_null:
546 txring->desc = NULL;
547 txring->dmaalloc = 0;
548 txring->dma = 0;
549 txring->bufinf = NULL;
550
551 return -ENOMEM;
d7699f87
GFT
552}
553
3bf61c55
GFT
554static void
555jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
556{
557 int i;
558 struct jme_ring *txring = &(jme->txring[0]);
0ede469c 559 struct jme_buffer_info *txbi;
d7699f87 560
cd0ff491 561 if (txring->alloc) {
0ede469c
GFT
562 if (txring->bufinf) {
563 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
564 txbi = txring->bufinf + i;
565 if (txbi->skb) {
566 dev_kfree_skb(txbi->skb);
567 txbi->skb = NULL;
568 }
569 txbi->mapping = 0;
570 txbi->len = 0;
571 txbi->nr_desc = 0;
572 txbi->start_xmit = 0;
d7699f87 573 }
0ede469c 574 kfree(txring->bufinf);
d7699f87
GFT
575 }
576
577 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 578 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT
579 txring->alloc,
580 txring->dmaalloc);
3bf61c55
GFT
581
582 txring->alloc = NULL;
583 txring->desc = NULL;
584 txring->dmaalloc = 0;
585 txring->dma = 0;
0ede469c 586 txring->bufinf = NULL;
d7699f87 587 }
3bf61c55 588 txring->next_to_use = 0;
cdcdc9eb 589 atomic_set(&txring->next_to_clean, 0);
79ce639c 590 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
591}
592
cd0ff491 593static inline void
3bf61c55 594jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
595{
596 /*
597 * Select Queue 0
598 */
599 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 600 wmb();
d7699f87
GFT
601
602 /*
603 * Setup TX Queue 0 DMA Bass Address
604 */
fcf45b4c 605 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 606 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 607 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
608
609 /*
610 * Setup TX Descptor Count
611 */
b3821cc5 612 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT
613
614 /*
615 * Enable TX Engine
616 */
617 wmb();
4330c2f2
GFT
618 jwrite32(jme, JME_TXCS, jme->reg_txcs |
619 TXCS_SELECT_QUEUE0 |
620 TXCS_ENABLE);
d7699f87
GFT
621
622}
623
cd0ff491 624static inline void
29bdd921
GFT
625jme_restart_tx_engine(struct jme_adapter *jme)
626{
627 /*
628 * Restart TX Engine
629 */
630 jwrite32(jme, JME_TXCS, jme->reg_txcs |
631 TXCS_SELECT_QUEUE0 |
632 TXCS_ENABLE);
633}
634
cd0ff491 635static inline void
3bf61c55 636jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
637{
638 int i;
cd0ff491 639 u32 val;
d7699f87
GFT
640
641 /*
642 * Disable TX Engine
643 */
fcf45b4c 644 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 645 wmb();
d7699f87
GFT
646
647 val = jread32(jme, JME_TXCS);
cd0ff491 648 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 649 mdelay(1);
d7699f87 650 val = jread32(jme, JME_TXCS);
cd0ff491 651 rmb();
d7699f87
GFT
652 }
653
cd0ff491 654 if (!i)
937ef75a 655 pr_err("Disable TX engine timeout\n");
d7699f87
GFT
656}
657
3bf61c55
GFT
658static void
659jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 660{
0ede469c 661 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 662 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT
663 struct jme_buffer_info *rxbi = rxring->bufinf;
664 rxdesc += i;
665 rxbi += i;
666
667 rxdesc->dw[0] = 0;
668 rxdesc->dw[1] = 0;
3bf61c55 669 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
670 rxdesc->desc1.bufaddrl = cpu_to_le32(
671 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 672 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 673 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 674 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 675 wmb();
3bf61c55 676 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
677}
678
3bf61c55
GFT
679static int
680jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
681{
682 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 683 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 684 struct sk_buff *skb;
4330c2f2 685
79ce639c
GFT
686 skb = netdev_alloc_skb(jme->dev,
687 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 688 if (unlikely(!skb))
4330c2f2 689 return -ENOMEM;
3b70a6fa
GFT
690#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
691 skb->dev = jme->dev;
692#endif
3bf61c55 693
4330c2f2 694 rxbi->skb = skb;
3bf61c55 695 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT
696 rxbi->mapping = pci_map_page(jme->pdev,
697 virt_to_page(skb->data),
698 offset_in_page(skb->data),
699 rxbi->len,
700 PCI_DMA_FROMDEVICE);
4330c2f2
GFT
701
702 return 0;
703}
704
3bf61c55
GFT
705static void
706jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
707{
708 struct jme_ring *rxring = &(jme->rxring[0]);
709 struct jme_buffer_info *rxbi = rxring->bufinf;
710 rxbi += i;
711
cd0ff491 712 if (rxbi->skb) {
b3821cc5 713 pci_unmap_page(jme->pdev,
4330c2f2 714 rxbi->mapping,
3bf61c55 715 rxbi->len,
4330c2f2
GFT
716 PCI_DMA_FROMDEVICE);
717 dev_kfree_skb(rxbi->skb);
718 rxbi->skb = NULL;
719 rxbi->mapping = 0;
3bf61c55 720 rxbi->len = 0;
4330c2f2
GFT
721 }
722}
723
3bf61c55
GFT
724static void
725jme_free_rx_resources(struct jme_adapter *jme)
726{
727 int i;
728 struct jme_ring *rxring = &(jme->rxring[0]);
729
cd0ff491 730 if (rxring->alloc) {
0ede469c
GFT
731 if (rxring->bufinf) {
732 for (i = 0 ; i < jme->rx_ring_size ; ++i)
733 jme_free_rx_buf(jme, i);
734 kfree(rxring->bufinf);
735 }
3bf61c55
GFT
736
737 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 738 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT
739 rxring->alloc,
740 rxring->dmaalloc);
741 rxring->alloc = NULL;
742 rxring->desc = NULL;
743 rxring->dmaalloc = 0;
744 rxring->dma = 0;
0ede469c 745 rxring->bufinf = NULL;
3bf61c55
GFT
746 }
747 rxring->next_to_use = 0;
cdcdc9eb 748 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT
749}
750
751static int
752jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
753{
754 int i;
755 struct jme_ring *rxring = &(jme->rxring[0]);
756
757 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
758 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
759 &(rxring->dmaalloc),
760 GFP_ATOMIC);
0ede469c
GFT
761 if (!rxring->alloc)
762 goto err_set_null;
d7699f87
GFT
763
764 /*
765 * 16 Bytes align
766 */
cd0ff491 767 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 768 RING_DESC_ALIGN);
4330c2f2 769 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 770 rxring->next_to_use = 0;
cdcdc9eb 771 atomic_set(&rxring->next_to_clean, 0);
d7699f87 772
0ede469c
GFT
773 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
774 jme->rx_ring_size, GFP_ATOMIC);
775 if (unlikely(!(rxring->bufinf)))
776 goto err_free_rxring;
777
d7699f87
GFT
778 /*
779 * Initiallize Receive Descriptors
780 */
0ede469c
GFT
781 memset(rxring->bufinf, 0,
782 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT
783 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
784 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT
785 jme_free_rx_resources(jme);
786 return -ENOMEM;
787 }
d7699f87
GFT
788
789 jme_set_clean_rxdesc(jme, i);
790 }
791
d7699f87 792 return 0;
0ede469c
GFT
793
794err_free_rxring:
795 dma_free_coherent(&(jme->pdev->dev),
796 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
797 rxring->alloc,
798 rxring->dmaalloc);
799err_set_null:
800 rxring->desc = NULL;
801 rxring->dmaalloc = 0;
802 rxring->dma = 0;
803 rxring->bufinf = NULL;
804
805 return -ENOMEM;
d7699f87
GFT
806}
807
cd0ff491 808static inline void
3bf61c55 809jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 810{
d7699f87 811 /*
cd0ff491
GFT
812 * Select Queue 0
813 */
814 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
815 RXCS_QUEUESEL_Q0);
816 wmb();
817
818 /*
d7699f87
GFT
819 * Setup RX DMA Bass Address
820 */
0ede469c 821 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 822 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
0ede469c 823 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT
824
825 /*
b3821cc5 826 * Setup RX Descriptor Count
d7699f87 827 */
b3821cc5 828 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 829
3bf61c55 830 /*
d7699f87
GFT
831 * Setup Unicast Filter
832 */
833 jme_set_multi(jme->dev);
834
835 /*
836 * Enable RX Engine
837 */
838 wmb();
79ce639c 839 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
840 RXCS_QUEUESEL_Q0 |
841 RXCS_ENABLE |
842 RXCS_QST);
d7699f87
GFT
843}
844
cd0ff491 845static inline void
3bf61c55 846jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
847{
848 /*
3bf61c55 849 * Start RX Engine
4330c2f2 850 */
79ce639c 851 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
852 RXCS_QUEUESEL_Q0 |
853 RXCS_ENABLE |
854 RXCS_QST);
855}
856
cd0ff491 857static inline void
3bf61c55 858jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
859{
860 int i;
cd0ff491 861 u32 val;
d7699f87
GFT
862
863 /*
864 * Disable RX Engine
865 */
29bdd921 866 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 867 wmb();
d7699f87
GFT
868
869 val = jread32(jme, JME_RXCS);
cd0ff491 870 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 871 mdelay(1);
d7699f87 872 val = jread32(jme, JME_RXCS);
cd0ff491 873 rmb();
d7699f87
GFT
874 }
875
cd0ff491 876 if (!i)
937ef75a 877 pr_err("Disable RX engine timeout\n");
d7699f87
GFT
878
879}
880
192570e0 881static int
cd0ff491 882jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
192570e0 883{
cd0ff491 884 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT
885 return false;
886
0ede469c
GFT
887 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
888 == RXWBFLAG_TCPON)) {
889 if (flags & RXWBFLAG_IPV4)
7ca9ebee 890 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
0ede469c 891 return false;
192570e0
GFT
892 }
893
0ede469c
GFT
894 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
895 == RXWBFLAG_UDPON)) {
896 if (flags & RXWBFLAG_IPV4)
937ef75a 897 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
0ede469c 898 return false;
192570e0
GFT
899 }
900
0ede469c
GFT
901 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
902 == RXWBFLAG_IPV4)) {
937ef75a 903 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
0ede469c 904 return false;
192570e0
GFT
905 }
906
907 return true;
908}
909
3bf61c55 910static void
42b1055e 911jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 912{
d7699f87 913 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 914 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 915 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 916 struct sk_buff *skb;
3bf61c55 917 int framesize;
d7699f87 918
3bf61c55
GFT
919 rxdesc += idx;
920 rxbi += idx;
d7699f87 921
3bf61c55
GFT
922 skb = rxbi->skb;
923 pci_dma_sync_single_for_cpu(jme->pdev,
924 rxbi->mapping,
925 rxbi->len,
926 PCI_DMA_FROMDEVICE);
927
cd0ff491 928 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT
929 pci_dma_sync_single_for_device(jme->pdev,
930 rxbi->mapping,
931 rxbi->len,
932 PCI_DMA_FROMDEVICE);
933
934 ++(NET_STAT(jme).rx_dropped);
cd0ff491 935 } else {
3bf61c55
GFT
936 framesize = le16_to_cpu(rxdesc->descwb.framesize)
937 - RX_PREPAD_SIZE;
938
939 skb_reserve(skb, RX_PREPAD_SIZE);
940 skb_put(skb, framesize);
941 skb->protocol = eth_type_trans(skb, jme->dev);
942
3b70a6fa 943 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
8c198884 944 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 945 else
08f5fcfa 946#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
29bdd921 947 skb->ip_summed = CHECKSUM_NONE;
08f5fcfa
ED
948#else
949 skb_checksum_none_assert(skb);
950#endif
8c198884 951
3b70a6fa 952 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 953 if (jme->vlgrp) {
cdcdc9eb 954 jme->jme_vlan_rx(skb, jme->vlgrp,
3b70a6fa 955 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 956 NET_STAT(jme).rx_bytes += 4;
7ca9ebee 957 } else {
7ca9ebee 958 dev_kfree_skb(skb);
b3821cc5 959 }
cd0ff491 960 } else {
cdcdc9eb 961 jme->jme_rx(skb);
b3821cc5 962 }
3bf61c55 963
3b70a6fa
GFT
964 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
965 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT
966 ++(NET_STAT(jme).multicast);
967
3bf61c55
GFT
968 NET_STAT(jme).rx_bytes += framesize;
969 ++(NET_STAT(jme).rx_packets);
970 }
971
972 jme_set_clean_rxdesc(jme, idx);
973
974}
975
8c198884 976static int
3bf61c55
GFT
977jme_process_receive(struct jme_adapter *jme, int limit)
978{
979 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 980 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 981 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 982
cd0ff491 983 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT
984 goto out_inc;
985
cd0ff491 986 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT
987 goto out_inc;
988
cd0ff491 989 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT
990 goto out_inc;
991
cdcdc9eb 992 i = atomic_read(&rxring->next_to_clean);
0ede469c 993 while (limit > 0) {
3bf61c55
GFT
994 rxdesc = rxring->desc;
995 rxdesc += i;
996
3b70a6fa 997 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT
998 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
999 goto out;
0ede469c 1000 --limit;
d7699f87 1001
9134abda 1002 rmb();
4330c2f2
GFT
1003 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1004
cd0ff491 1005 if (unlikely(desccnt > 1 ||
192570e0 1006 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1007
cd0ff491 1008 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1009 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1010 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT
1011 ++(NET_STAT(jme).rx_fifo_errors);
1012 else
1013 ++(NET_STAT(jme).rx_errors);
4330c2f2 1014
cd0ff491 1015 if (desccnt > 1)
3bf61c55 1016 limit -= desccnt - 1;
4330c2f2 1017
cd0ff491 1018 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1019 jme_set_clean_rxdesc(jme, j);
b3821cc5 1020 j = (j + 1) & (mask);
4330c2f2 1021 }
3bf61c55 1022
cd0ff491 1023 } else {
42b1055e 1024 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1025 }
4330c2f2 1026
b3821cc5 1027 i = (i + desccnt) & (mask);
3bf61c55 1028 }
4330c2f2 1029
3bf61c55 1030out:
cdcdc9eb 1031 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1032
192570e0
GFT
1033out_inc:
1034 atomic_inc(&jme->rx_cleaning);
1035
3bf61c55 1036 return limit > 0 ? limit : 0;
4330c2f2 1037
3bf61c55 1038}
d7699f87 1039
3bf61c55 1040static void
79ce639c
GFT
1041jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1042{
cd0ff491 1043 if (likely(atmp == dpi->cur)) {
192570e0 1044 dpi->cnt = 0;
79ce639c 1045 return;
192570e0 1046 }
79ce639c 1047
cd0ff491 1048 if (dpi->attempt == atmp) {
79ce639c 1049 ++(dpi->cnt);
cd0ff491 1050 } else {
79ce639c
GFT
1051 dpi->attempt = atmp;
1052 dpi->cnt = 0;
1053 }
1054
1055}
1056
1057static void
1058jme_dynamic_pcc(struct jme_adapter *jme)
1059{
1060 register struct dynpcc_info *dpi = &(jme->dpi);
1061
cd0ff491 1062 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1063 jme_attempt_pcc(dpi, PCC_P3);
7ca9ebee
GFT
1064 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1065 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT
1066 jme_attempt_pcc(dpi, PCC_P2);
1067 else
1068 jme_attempt_pcc(dpi, PCC_P1);
1069
cd0ff491
GFT
1070 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1071 if (dpi->attempt < dpi->cur)
1072 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT
1073 jme_set_rx_pcc(jme, dpi->attempt);
1074 dpi->cur = dpi->attempt;
1075 dpi->cnt = 0;
1076 }
1077}
1078
1079static void
1080jme_start_pcc_timer(struct jme_adapter *jme)
1081{
1082 struct dynpcc_info *dpi = &(jme->dpi);
1083 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1084 dpi->last_pkts = NET_STAT(jme).rx_packets;
1085 dpi->intr_cnt = 0;
1086 jwrite32(jme, JME_TMCSR,
1087 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1088}
1089
cd0ff491 1090static inline void
29bdd921
GFT
1091jme_stop_pcc_timer(struct jme_adapter *jme)
1092{
1093 jwrite32(jme, JME_TMCSR, 0);
1094}
1095
1096static void
cd0ff491
GFT
1097jme_shutdown_nic(struct jme_adapter *jme)
1098{
1099 u32 phylink;
1100
1101 phylink = jme_linkstat_from_phy(jme);
1102
1103 if (!(phylink & PHY_LINK_UP)) {
1104 /*
1105 * Disable all interrupt before issue timer
1106 */
1107 jme_stop_irq(jme);
1108 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1109 }
1110}
1111
1112static void
79ce639c
GFT
1113jme_pcc_tasklet(unsigned long arg)
1114{
cd0ff491 1115 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT
1116 struct net_device *netdev = jme->dev;
1117
cd0ff491
GFT
1118 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1119 jme_shutdown_nic(jme);
1120 return;
1121 }
29bdd921 1122
cd0ff491 1123 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT
1124 (atomic_read(&jme->link_changing) != 1)
1125 )) {
1126 jme_stop_pcc_timer(jme);
79ce639c
GFT
1127 return;
1128 }
29bdd921 1129
cd0ff491 1130 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT
1131 jme_dynamic_pcc(jme);
1132
79ce639c
GFT
1133 jme_start_pcc_timer(jme);
1134}
1135
cd0ff491 1136static inline void
192570e0
GFT
1137jme_polling_mode(struct jme_adapter *jme)
1138{
1139 jme_set_rx_pcc(jme, PCC_OFF);
1140}
1141
cd0ff491 1142static inline void
192570e0
GFT
1143jme_interrupt_mode(struct jme_adapter *jme)
1144{
1145 jme_set_rx_pcc(jme, PCC_P1);
1146}
1147
cd0ff491
GFT
1148static inline int
1149jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1150{
1151 u32 apmc;
1152 apmc = jread32(jme, JME_APMC);
1153 return apmc & JME_APMC_PSEUDO_HP_EN;
1154}
1155
1156static void
1157jme_start_shutdown_timer(struct jme_adapter *jme)
1158{
1159 u32 apmc;
1160
1161 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1162 apmc &= ~JME_APMC_EPIEN_CTRL;
1163 if (!no_extplug) {
1164 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1165 wmb();
1166 }
1167 jwrite32f(jme, JME_APMC, apmc);
1168
1169 jwrite32f(jme, JME_TIMER2, 0);
1170 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1171 jwrite32(jme, JME_TMCSR,
1172 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1173}
1174
1175static void
1176jme_stop_shutdown_timer(struct jme_adapter *jme)
1177{
1178 u32 apmc;
1179
1180 jwrite32f(jme, JME_TMCSR, 0);
1181 jwrite32f(jme, JME_TIMER2, 0);
1182 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1183
1184 apmc = jread32(jme, JME_APMC);
1185 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1186 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1187 wmb();
1188 jwrite32f(jme, JME_APMC, apmc);
1189}
1190
79ce639c 1191static void
3bf61c55
GFT
1192jme_link_change_tasklet(unsigned long arg)
1193{
cd0ff491 1194 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1195 struct net_device *netdev = jme->dev;
fcf45b4c
GFT
1196 int rc;
1197
cd0ff491
GFT
1198 while (!atomic_dec_and_test(&jme->link_changing)) {
1199 atomic_inc(&jme->link_changing);
937ef75a 1200 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
58c92f28 1201 while (atomic_read(&jme->link_changing) != 1)
937ef75a 1202 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1203 }
fcf45b4c 1204
cd0ff491 1205 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1206 goto out;
1207
29bdd921 1208 jme->old_mtu = netdev->mtu;
fcf45b4c 1209 netif_stop_queue(netdev);
cd0ff491
GFT
1210 if (jme_pseudo_hotplug_enabled(jme))
1211 jme_stop_shutdown_timer(jme);
1212
1213 jme_stop_pcc_timer(jme);
1214 tasklet_disable(&jme->txclean_task);
1215 tasklet_disable(&jme->rxclean_task);
1216 tasklet_disable(&jme->rxempty_task);
1217
1218 if (netif_carrier_ok(netdev)) {
1219 jme_reset_ghc_speed(jme);
1220 jme_disable_rx_engine(jme);
1221 jme_disable_tx_engine(jme);
fcf45b4c
GFT
1222 jme_reset_mac_processor(jme);
1223 jme_free_rx_resources(jme);
1224 jme_free_tx_resources(jme);
192570e0 1225
cd0ff491 1226 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1227 jme_polling_mode(jme);
cd0ff491
GFT
1228
1229 netif_carrier_off(netdev);
fcf45b4c
GFT
1230 }
1231
1232 jme_check_link(netdev, 0);
cd0ff491 1233 if (netif_carrier_ok(netdev)) {
fcf45b4c 1234 rc = jme_setup_rx_resources(jme);
cd0ff491 1235 if (rc) {
937ef75a 1236 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1237 goto out_enable_tasklet;
fcf45b4c
GFT
1238 }
1239
fcf45b4c 1240 rc = jme_setup_tx_resources(jme);
cd0ff491 1241 if (rc) {
937ef75a 1242 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT
1243 goto err_out_free_rx_resources;
1244 }
1245
1246 jme_enable_rx_engine(jme);
1247 jme_enable_tx_engine(jme);
1248
1249 netif_start_queue(netdev);
192570e0 1250
cd0ff491 1251 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1252 jme_interrupt_mode(jme);
192570e0 1253
79ce639c 1254 jme_start_pcc_timer(jme);
cd0ff491
GFT
1255 } else if (jme_pseudo_hotplug_enabled(jme)) {
1256 jme_start_shutdown_timer(jme);
fcf45b4c
GFT
1257 }
1258
cd0ff491 1259 goto out_enable_tasklet;
fcf45b4c
GFT
1260
1261err_out_free_rx_resources:
1262 jme_free_rx_resources(jme);
cd0ff491
GFT
1263out_enable_tasklet:
1264 tasklet_enable(&jme->txclean_task);
1265 tasklet_hi_enable(&jme->rxclean_task);
1266 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT
1267out:
1268 atomic_inc(&jme->link_changing);
3bf61c55 1269}
d7699f87 1270
3bf61c55
GFT
1271static void
1272jme_rx_clean_tasklet(unsigned long arg)
1273{
cd0ff491 1274 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1275 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1276
192570e0
GFT
1277 jme_process_receive(jme, jme->rx_ring_size);
1278 ++(dpi->intr_cnt);
42b1055e 1279
192570e0 1280}
fcf45b4c 1281
192570e0 1282static int
cdcdc9eb 1283jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1284{
cdcdc9eb 1285 struct jme_adapter *jme = jme_napi_priv(holder);
3b70a6fa 1286 DECLARE_NETDEV
192570e0 1287 int rest;
fcf45b4c 1288
cdcdc9eb 1289 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1290
cd0ff491 1291 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1292 atomic_dec(&jme->rx_empty);
192570e0
GFT
1293 ++(NET_STAT(jme).rx_dropped);
1294 jme_restart_rx_engine(jme);
1295 }
1296 atomic_inc(&jme->rx_empty);
1297
cd0ff491 1298 if (rest) {
cdcdc9eb 1299 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT
1300 jme_interrupt_mode(jme);
1301 }
1302
cdcdc9eb
GFT
1303 JME_NAPI_WEIGHT_SET(budget, rest);
1304 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT
1305}
1306
1307static void
1308jme_rx_empty_tasklet(unsigned long arg)
1309{
cd0ff491 1310 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1311
cd0ff491 1312 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1313 return;
1314
cd0ff491 1315 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1316 return;
1317
7ca9ebee 1318 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1319
fcf45b4c 1320 jme_rx_clean_tasklet(arg);
cdcdc9eb 1321
cd0ff491 1322 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT
1323 atomic_dec(&jme->rx_empty);
1324 ++(NET_STAT(jme).rx_dropped);
1325 jme_restart_rx_engine(jme);
1326 }
1327 atomic_inc(&jme->rx_empty);
4330c2f2
GFT
1328}
1329
3bf61c55 1330static void
b3821cc5
GFT
1331jme_wake_queue_if_stopped(struct jme_adapter *jme)
1332{
0ede469c 1333 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1334
1335 smp_wmb();
cd0ff491 1336 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1337 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
937ef75a 1338 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1339 netif_wake_queue(jme->dev);
b3821cc5
GFT
1340 }
1341
1342}
1343
1344static void
3bf61c55 1345jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1346{
cd0ff491 1347 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1348 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1349 struct txdesc *txdesc = txring->desc;
3bf61c55 1350 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1351 int i, j, cnt = 0, max, err, mask;
3bf61c55 1352
937ef75a 1353 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT
1354
1355 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1356 goto out;
1357
cd0ff491 1358 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1359 goto out;
1360
cd0ff491 1361 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1362 goto out;
1363
b3821cc5
GFT
1364 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1365 mask = jme->tx_ring_mask;
3bf61c55 1366
cd0ff491 1367 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT
1368
1369 ctxbi = txbi + i;
1370
cd0ff491 1371 if (likely(ctxbi->skb &&
b3821cc5 1372 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1373
cd0ff491 1374 tx_dbg(jme, "txclean: %d+%d@%lu\n",
937ef75a 1375 i, ctxbi->nr_desc, jiffies);
3bf61c55 1376
cd0ff491 1377 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1378
cd0ff491 1379 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT
1380 ttxbi = txbi + ((i + j) & (mask));
1381 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1382
b3821cc5 1383 pci_unmap_page(jme->pdev,
3bf61c55
GFT
1384 ttxbi->mapping,
1385 ttxbi->len,
1386 PCI_DMA_TODEVICE);
1387
3bf61c55
GFT
1388 ttxbi->mapping = 0;
1389 ttxbi->len = 0;
1390 }
1391
1392 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT
1393
1394 cnt += ctxbi->nr_desc;
1395
cd0ff491 1396 if (unlikely(err)) {
8c198884 1397 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1398 } else {
8c198884 1399 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT
1400 NET_STAT(jme).tx_bytes += ctxbi->len;
1401 }
1402
1403 ctxbi->skb = NULL;
1404 ctxbi->len = 0;
cdcdc9eb 1405 ctxbi->start_xmit = 0;
cd0ff491
GFT
1406
1407 } else {
3bf61c55
GFT
1408 break;
1409 }
1410
b3821cc5 1411 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT
1412
1413 ctxbi->nr_desc = 0;
d7699f87
GFT
1414 }
1415
937ef75a 1416 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1417 atomic_set(&txring->next_to_clean, i);
79ce639c 1418 atomic_add(cnt, &txring->nr_free);
3bf61c55 1419
b3821cc5
GFT
1420 jme_wake_queue_if_stopped(jme);
1421
fcf45b4c
GFT
1422out:
1423 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1424}
1425
79ce639c 1426static void
cd0ff491 1427jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1428{
3bf61c55
GFT
1429 /*
1430 * Disable interrupt
1431 */
1432 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1433
cd0ff491 1434 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT
1435 /*
1436 * Link change event is critical
1437 * all other events are ignored
1438 */
1439 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1440 tasklet_schedule(&jme->linkch_task);
29bdd921 1441 goto out_reenable;
fcf45b4c 1442 }
d7699f87 1443
cd0ff491 1444 if (intrstat & INTR_TMINTR) {
47220951 1445 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1446 tasklet_schedule(&jme->pcc_task);
47220951 1447 }
79ce639c 1448
cd0ff491 1449 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1450 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1451 tasklet_schedule(&jme->txclean_task);
47220951
GFT
1452 }
1453
cd0ff491 1454 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT
1455 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1456 INTR_PCCRX0 |
1457 INTR_RX0EMP)) |
1458 INTR_RX0);
1459 }
d7699f87 1460
cd0ff491
GFT
1461 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1462 if (intrstat & INTR_RX0EMP)
192570e0
GFT
1463 atomic_inc(&jme->rx_empty);
1464
cd0ff491
GFT
1465 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1466 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1467 jme_polling_mode(jme);
cdcdc9eb 1468 JME_RX_SCHEDULE(jme);
192570e0
GFT
1469 }
1470 }
cd0ff491
GFT
1471 } else {
1472 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1473 atomic_inc(&jme->rx_empty);
cd0ff491
GFT
1474 tasklet_hi_schedule(&jme->rxempty_task);
1475 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1476 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1477 }
4330c2f2 1478 }
d7699f87 1479
29bdd921 1480out_reenable:
3bf61c55 1481 /*
fcf45b4c 1482 * Re-enable interrupt
3bf61c55 1483 */
fcf45b4c 1484 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT
1485}
1486
3b70a6fa
GFT
1487#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1488static irqreturn_t
1489jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1490#else
79ce639c
GFT
1491static irqreturn_t
1492jme_intr(int irq, void *dev_id)
3b70a6fa 1493#endif
79ce639c 1494{
cd0ff491
GFT
1495 struct net_device *netdev = dev_id;
1496 struct jme_adapter *jme = netdev_priv(netdev);
1497 u32 intrstat;
79ce639c
GFT
1498
1499 intrstat = jread32(jme, JME_IEVE);
1500
1501 /*
1502 * Check if it's really an interrupt for us
1503 */
7ee473a3 1504 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1505 return IRQ_NONE;
79ce639c
GFT
1506
1507 /*
1508 * Check if the device still exist
1509 */
cd0ff491
GFT
1510 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1511 return IRQ_NONE;
79ce639c
GFT
1512
1513 jme_intr_msi(jme, intrstat);
1514
cd0ff491 1515 return IRQ_HANDLED;
d7699f87
GFT
1516}
1517
3b70a6fa
GFT
1518#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1519static irqreturn_t
1520jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1521#else
79ce639c
GFT
1522static irqreturn_t
1523jme_msi(int irq, void *dev_id)
3b70a6fa 1524#endif
79ce639c 1525{
cd0ff491
GFT
1526 struct net_device *netdev = dev_id;
1527 struct jme_adapter *jme = netdev_priv(netdev);
1528 u32 intrstat;
79ce639c 1529
0ede469c 1530 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT
1531
1532 jme_intr_msi(jme, intrstat);
1533
cd0ff491 1534 return IRQ_HANDLED;
79ce639c
GFT
1535}
1536
79ce639c
GFT
1537static void
1538jme_reset_link(struct jme_adapter *jme)
1539{
1540 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1541}
1542
fcf45b4c
GFT
1543static void
1544jme_restart_an(struct jme_adapter *jme)
1545{
cd0ff491 1546 u32 bmcr;
fcf45b4c 1547
cd0ff491 1548 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT
1549 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1550 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1551 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1552 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT
1553}
1554
1555static int
1556jme_request_irq(struct jme_adapter *jme)
1557{
1558 int rc;
cd0ff491 1559 struct net_device *netdev = jme->dev;
3b70a6fa
GFT
1560#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1561 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1562 int irq_flags = SA_SHIRQ;
1563#else
cd0ff491
GFT
1564 irq_handler_t handler = jme_intr;
1565 int irq_flags = IRQF_SHARED;
3b70a6fa 1566#endif
cd0ff491
GFT
1567
1568 if (!pci_enable_msi(jme->pdev)) {
1569 set_bit(JME_FLAG_MSI, &jme->flags);
1570 handler = jme_msi;
1571 irq_flags = 0;
1572 }
1573
1574 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1575 netdev);
1576 if (rc) {
937ef75a
JP
1577 netdev_err(netdev,
1578 "Unable to request %s interrupt (return: %d)\n",
1579 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1580 rc);
79ce639c 1581
cd0ff491
GFT
1582 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1583 pci_disable_msi(jme->pdev);
1584 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1585 }
cd0ff491 1586 } else {
79ce639c
GFT
1587 netdev->irq = jme->pdev->irq;
1588 }
1589
cd0ff491 1590 return rc;
79ce639c
GFT
1591}
1592
1593static void
1594jme_free_irq(struct jme_adapter *jme)
1595{
cd0ff491
GFT
1596 free_irq(jme->pdev->irq, jme->dev);
1597 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1598 pci_disable_msi(jme->pdev);
1599 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1600 jme->dev->irq = jme->pdev->irq;
cd0ff491 1601 }
fcf45b4c
GFT
1602}
1603
e58b908e
GFT
1604static inline void
1605jme_phy_on(struct jme_adapter *jme)
1606{
1607 u32 bmcr;
1608
1609 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1610 bmcr &= ~BMCR_PDOWN;
1611 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1612}
1613
3bf61c55
GFT
1614static int
1615jme_open(struct net_device *netdev)
d7699f87
GFT
1616{
1617 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1618 int rc;
79ce639c 1619
42b1055e 1620 jme_clear_pm(jme);
cdcdc9eb 1621 JME_NAPI_ENABLE(jme);
d7699f87 1622
0ede469c 1623 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT
1624 tasklet_enable(&jme->txclean_task);
1625 tasklet_hi_enable(&jme->rxclean_task);
1626 tasklet_hi_enable(&jme->rxempty_task);
1627
79ce639c 1628 rc = jme_request_irq(jme);
cd0ff491 1629 if (rc)
4330c2f2 1630 goto err_out;
79ce639c 1631
d7699f87 1632 jme_start_irq(jme);
42b1055e 1633
e58b908e
GFT
1634 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1635 jme_phy_on(jme);
42b1055e 1636 jme_set_settings(netdev, &jme->old_ecmd);
e58b908e 1637 } else {
42b1055e 1638 jme_reset_phy_processor(jme);
e58b908e 1639 }
42b1055e 1640
29bdd921 1641 jme_reset_link(jme);
d7699f87
GFT
1642
1643 return 0;
1644
d7699f87
GFT
1645err_out:
1646 netif_stop_queue(netdev);
1647 netif_carrier_off(netdev);
4330c2f2 1648 return rc;
d7699f87
GFT
1649}
1650
7ee473a3 1651#ifdef CONFIG_PM
42b1055e
GFT
1652static void
1653jme_set_100m_half(struct jme_adapter *jme)
1654{
cd0ff491 1655 u32 bmcr, tmp;
42b1055e
GFT
1656
1657 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1658 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1659 BMCR_SPEED1000 | BMCR_FULLDPLX);
1660 tmp |= BMCR_SPEED100;
1661
1662 if (bmcr != tmp)
1663 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1664
cd0ff491 1665 if (jme->fpgaver)
cdcdc9eb
GFT
1666 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1667 else
1668 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT
1669}
1670
47220951
GFT
1671#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1672static void
1673jme_wait_link(struct jme_adapter *jme)
1674{
cd0ff491 1675 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT
1676
1677 mdelay(1000);
1678 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1679 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT
1680 mdelay(10);
1681 phylink = jme_linkstat_from_phy(jme);
1682 }
1683}
7ee473a3 1684#endif
47220951 1685
cd0ff491 1686static inline void
42b1055e
GFT
1687jme_phy_off(struct jme_adapter *jme)
1688{
1689 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1690}
1691
3bf61c55
GFT
1692static int
1693jme_close(struct net_device *netdev)
d7699f87
GFT
1694{
1695 struct jme_adapter *jme = netdev_priv(netdev);
1696
1697 netif_stop_queue(netdev);
1698 netif_carrier_off(netdev);
1699
1700 jme_stop_irq(jme);
79ce639c 1701 jme_free_irq(jme);
d7699f87 1702
cdcdc9eb 1703 JME_NAPI_DISABLE(jme);
192570e0 1704
0ede469c
GFT
1705 tasklet_disable(&jme->linkch_task);
1706 tasklet_disable(&jme->txclean_task);
1707 tasklet_disable(&jme->rxclean_task);
1708 tasklet_disable(&jme->rxempty_task);
8c198884 1709
cd0ff491
GFT
1710 jme_reset_ghc_speed(jme);
1711 jme_disable_rx_engine(jme);
1712 jme_disable_tx_engine(jme);
8c198884 1713 jme_reset_mac_processor(jme);
d7699f87
GFT
1714 jme_free_rx_resources(jme);
1715 jme_free_tx_resources(jme);
42b1055e 1716 jme->phylink = 0;
b3821cc5
GFT
1717 jme_phy_off(jme);
1718
1719 return 0;
1720}
1721
1722static int
1723jme_alloc_txdesc(struct jme_adapter *jme,
1724 struct sk_buff *skb)
1725{
0ede469c 1726 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1727 int idx, nr_alloc, mask = jme->tx_ring_mask;
1728
1729 idx = txring->next_to_use;
1730 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1731
cd0ff491 1732 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT
1733 return -1;
1734
1735 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1736
b3821cc5
GFT
1737 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1738
1739 return idx;
1740}
1741
1742static void
1743jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1744 struct txdesc *txdesc,
b3821cc5
GFT
1745 struct jme_buffer_info *txbi,
1746 struct page *page,
cd0ff491
GFT
1747 u32 page_offset,
1748 u32 len,
1749 u8 hidma)
b3821cc5
GFT
1750{
1751 dma_addr_t dmaaddr;
1752
1753 dmaaddr = pci_map_page(pdev,
1754 page,
1755 page_offset,
1756 len,
1757 PCI_DMA_TODEVICE);
1758
1759 pci_dma_sync_single_for_device(pdev,
1760 dmaaddr,
1761 len,
1762 PCI_DMA_TODEVICE);
1763
1764 txdesc->dw[0] = 0;
1765 txdesc->dw[1] = 0;
1766 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1767 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT
1768 txdesc->desc2.datalen = cpu_to_le16(len);
1769 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1770 txdesc->desc2.bufaddrl = cpu_to_le32(
1771 (__u64)dmaaddr & 0xFFFFFFFFUL);
1772
1773 txbi->mapping = dmaaddr;
1774 txbi->len = len;
1775}
1776
1777static void
1778jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1779{
0ede469c 1780 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1781 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1782 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1783 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT
1784 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1785 int mask = jme->tx_ring_mask;
1786 struct skb_frag_struct *frag;
cd0ff491 1787 u32 len;
b3821cc5 1788
cd0ff491
GFT
1789 for (i = 0 ; i < nr_frags ; ++i) {
1790 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT
1791 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1792 ctxbi = txbi + ((idx + i + 2) & (mask));
1793
1794 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1795 frag->page_offset, frag->size, hidma);
42b1055e 1796 }
b3821cc5 1797
cd0ff491 1798 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT
1799 ctxdesc = txdesc + ((idx + 1) & (mask));
1800 ctxbi = txbi + ((idx + 1) & (mask));
1801 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1802 offset_in_page(skb->data), len, hidma);
1803
1804}
1805
1806static int
1807jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1808{
3b70a6fa 1809 if (unlikely(
0ede469c 1810#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT
1811 skb_shinfo(skb)->tso_size
1812#else
1813 skb_shinfo(skb)->gso_size
1814#endif
1815 && skb_header_cloned(skb) &&
b3821cc5
GFT
1816 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1817 dev_kfree_skb(skb);
1818 return -1;
1819 }
1820
1821 return 0;
1822}
1823
1824static int
3b70a6fa 1825jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1826{
0ede469c 1827#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT
1828 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1829#else
1830 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1831#endif
cd0ff491 1832 if (*mss) {
b3821cc5
GFT
1833 *flags |= TXFLAG_LSEN;
1834
cd0ff491 1835 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT
1836 struct iphdr *iph = ip_hdr(skb);
1837
1838 iph->check = 0;
cd0ff491 1839 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT
1840 iph->daddr, 0,
1841 IPPROTO_TCP,
1842 0);
cd0ff491 1843 } else {
b3821cc5
GFT
1844 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1845
cd0ff491 1846 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT
1847 &ip6h->daddr, 0,
1848 IPPROTO_TCP,
1849 0);
1850 }
1851
1852 return 0;
1853 }
1854
1855 return 1;
1856}
1857
1858static void
cd0ff491 1859jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1860{
3b70a6fa
GFT
1861#ifdef CHECKSUM_PARTIAL
1862 if (skb->ip_summed == CHECKSUM_PARTIAL)
1863#else
1864 if (skb->ip_summed == CHECKSUM_HW)
1865#endif
1866 {
cd0ff491 1867 u8 ip_proto;
b3821cc5 1868
3b70a6fa
GFT
1869#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1870 if (skb->protocol == htons(ETH_P_IP))
1871 ip_proto = ip_hdr(skb)->protocol;
1872 else if (skb->protocol == htons(ETH_P_IPV6))
1873 ip_proto = ipv6_hdr(skb)->nexthdr;
1874 else
1875 ip_proto = 0;
1876#else
b3821cc5 1877 switch (skb->protocol) {
cd0ff491 1878 case htons(ETH_P_IP):
b3821cc5
GFT
1879 ip_proto = ip_hdr(skb)->protocol;
1880 break;
cd0ff491 1881 case htons(ETH_P_IPV6):
b3821cc5
GFT
1882 ip_proto = ipv6_hdr(skb)->nexthdr;
1883 break;
1884 default:
1885 ip_proto = 0;
1886 break;
1887 }
3b70a6fa 1888#endif
b3821cc5 1889
cd0ff491 1890 switch (ip_proto) {
b3821cc5
GFT
1891 case IPPROTO_TCP:
1892 *flags |= TXFLAG_TCPCS;
1893 break;
1894 case IPPROTO_UDP:
1895 *flags |= TXFLAG_UDPCS;
1896 break;
1897 default:
937ef75a 1898 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT
1899 break;
1900 }
1901 }
1902}
1903
cd0ff491 1904static inline void
3b70a6fa 1905jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 1906{
cd0ff491 1907 if (vlan_tx_tag_present(skb)) {
b3821cc5 1908 *flags |= TXFLAG_TAGON;
3b70a6fa 1909 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 1910 }
b3821cc5
GFT
1911}
1912
1913static int
3b70a6fa 1914jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 1915{
0ede469c 1916 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1917 struct txdesc *txdesc;
b3821cc5 1918 struct jme_buffer_info *txbi;
cd0ff491 1919 u8 flags;
b3821cc5 1920
cd0ff491 1921 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT
1922 txbi = txring->bufinf + idx;
1923
1924 txdesc->dw[0] = 0;
1925 txdesc->dw[1] = 0;
1926 txdesc->dw[2] = 0;
1927 txdesc->dw[3] = 0;
1928 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1929 /*
1930 * Set OWN bit at final.
1931 * When kernel transmit faster than NIC.
1932 * And NIC trying to send this descriptor before we tell
1933 * it to start sending this TX queue.
1934 * Other fields are already filled correctly.
1935 */
1936 wmb();
1937 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT
1938 /*
1939 * Set checksum flags while not tso
1940 */
1941 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1942 jme_tx_csum(jme, skb, &flags);
b3821cc5 1943 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
3b70a6fa 1944 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT
1945 txdesc->desc1.flags = flags;
1946 /*
1947 * Set tx buffer info after telling NIC to send
1948 * For better tx_clean timing
1949 */
1950 wmb();
1951 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1952 txbi->skb = skb;
1953 txbi->len = skb->len;
cd0ff491
GFT
1954 txbi->start_xmit = jiffies;
1955 if (!txbi->start_xmit)
8d27293f 1956 txbi->start_xmit = (0UL-1);
d7699f87
GFT
1957
1958 return 0;
1959}
1960
b3821cc5
GFT
1961static void
1962jme_stop_queue_if_full(struct jme_adapter *jme)
1963{
0ede469c 1964 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT
1965 struct jme_buffer_info *txbi = txring->bufinf;
1966 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 1967
cd0ff491 1968 txbi += idx;
b3821cc5
GFT
1969
1970 smp_wmb();
cd0ff491 1971 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 1972 netif_stop_queue(jme->dev);
937ef75a 1973 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 1974 smp_wmb();
cd0ff491
GFT
1975 if (atomic_read(&txring->nr_free)
1976 >= (jme->tx_wake_threshold)) {
b3821cc5 1977 netif_wake_queue(jme->dev);
937ef75a 1978 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT
1979 }
1980 }
1981
cd0ff491 1982 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT
1983 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1984 txbi->skb)) {
1985 netif_stop_queue(jme->dev);
937ef75a 1986 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 1987 }
b3821cc5
GFT
1988}
1989
3bf61c55
GFT
1990/*
1991 * This function is already protected by netif_tx_lock()
1992 */
cd0ff491 1993
7ca9ebee 1994#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
3bf61c55 1995static int
7ca9ebee
GFT
1996#else
1997static netdev_tx_t
1998#endif
3bf61c55 1999jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2000{
cd0ff491 2001 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2002 int idx;
d7699f87 2003
cd0ff491 2004 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT
2005 ++(NET_STAT(jme).tx_dropped);
2006 return NETDEV_TX_OK;
2007 }
2008
2009 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2010
cd0ff491 2011 if (unlikely(idx < 0)) {
b3821cc5 2012 netif_stop_queue(netdev);
937ef75a
JP
2013 netif_err(jme, tx_err, jme->dev,
2014 "BUG! Tx ring full when queue awake!\n");
d7699f87 2015
cd0ff491 2016 return NETDEV_TX_BUSY;
b3821cc5
GFT
2017 }
2018
3b70a6fa 2019 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2020
4330c2f2
GFT
2021 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2022 TXCS_SELECT_QUEUE0 |
2023 TXCS_QUEUE0S |
2024 TXCS_ENABLE);
0ede469c 2025#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
d7699f87 2026 netdev->trans_start = jiffies;
0ede469c 2027#endif
d7699f87 2028
937ef75a
JP
2029 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2030 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT
2031 jme_stop_queue_if_full(jme);
2032
cd0ff491 2033 return NETDEV_TX_OK;
d7699f87
GFT
2034}
2035
3bf61c55
GFT
2036static int
2037jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2038{
cd0ff491 2039 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2040 struct sockaddr *addr = p;
cd0ff491 2041 u32 val;
d7699f87 2042
cd0ff491 2043 if (netif_running(netdev))
d7699f87
GFT
2044 return -EBUSY;
2045
cd0ff491 2046 spin_lock_bh(&jme->macaddr_lock);
d7699f87
GFT
2047 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2048
186fc259
GFT
2049 val = (addr->sa_data[3] & 0xff) << 24 |
2050 (addr->sa_data[2] & 0xff) << 16 |
2051 (addr->sa_data[1] & 0xff) << 8 |
2052 (addr->sa_data[0] & 0xff);
4330c2f2 2053 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT
2054 val = (addr->sa_data[5] & 0xff) << 8 |
2055 (addr->sa_data[4] & 0xff);
4330c2f2 2056 jwrite32(jme, JME_RXUMA_HI, val);
cd0ff491 2057 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT
2058
2059 return 0;
2060}
2061
3bf61c55
GFT
2062static void
2063jme_set_multi(struct net_device *netdev)
d7699f87 2064{
3bf61c55 2065 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2066 u32 mc_hash[2] = {};
7ca9ebee 2067#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
d7699f87 2068 int i;
7ca9ebee 2069#endif
d7699f87 2070
cd0ff491 2071 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT
2072
2073 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2074
cd0ff491 2075 if (netdev->flags & IFF_PROMISC) {
8c198884 2076 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2077 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2078 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2079 } else if (netdev->flags & IFF_MULTICAST) {
8e14c278 2080#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
3bf61c55 2081 struct dev_mc_list *mclist;
8e14c278
JP
2082#else
2083 struct netdev_hw_addr *ha;
2084#endif
3bf61c55 2085 int bit_nr;
d7699f87 2086
8c198884 2087 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
7ca9ebee 2088#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
3bf61c55
GFT
2089 for (i = 0, mclist = netdev->mc_list;
2090 mclist && i < netdev->mc_count;
2091 ++i, mclist = mclist->next) {
8e14c278 2092#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
7ca9ebee 2093 netdev_for_each_mc_addr(mclist, netdev) {
8e14c278
JP
2094#else
2095 netdev_for_each_mc_addr(ha, netdev) {
7ca9ebee 2096#endif
8e14c278 2097#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
cd0ff491 2098 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
8e14c278
JP
2099#else
2100 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2101#endif
cd0ff491
GFT
2102 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2103 }
d7699f87 2104
4330c2f2
GFT
2105 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2106 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
2107 }
2108
d7699f87 2109 wmb();
8c198884
GFT
2110 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2111
cd0ff491 2112 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT
2113}
2114
3bf61c55 2115static int
8c198884 2116jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2117{
cd0ff491 2118 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2119
cd0ff491 2120 if (new_mtu == jme->old_mtu)
29bdd921
GFT
2121 return 0;
2122
cd0ff491
GFT
2123 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2124 ((new_mtu) < IPV6_MIN_MTU))
2125 return -EINVAL;
79ce639c 2126
cd0ff491 2127 if (new_mtu > 4000) {
79ce639c
GFT
2128 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2129 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2130 jme_restart_rx_engine(jme);
cd0ff491 2131 } else {
79ce639c
GFT
2132 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2133 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2134 jme_restart_rx_engine(jme);
2135 }
2136
cd0ff491 2137 if (new_mtu > 1900) {
b3821cc5 2138 netdev->features &= ~(NETIF_F_HW_CSUM |
3b70a6fa
GFT
2139 NETIF_F_TSO
2140#ifdef NETIF_F_TSO6
2141 | NETIF_F_TSO6
2142#endif
2143 );
cd0ff491
GFT
2144 } else {
2145 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
b3821cc5 2146 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491 2147 if (test_bit(JME_FLAG_TSO, &jme->flags))
3b70a6fa
GFT
2148 netdev->features |= NETIF_F_TSO
2149#ifdef NETIF_F_TSO6
2150 | NETIF_F_TSO6
2151#endif
2152 ;
79ce639c
GFT
2153 }
2154
cd0ff491
GFT
2155 netdev->mtu = new_mtu;
2156 jme_reset_link(jme);
79ce639c
GFT
2157
2158 return 0;
d7699f87
GFT
2159}
2160
3bf61c55 2161static void
8c198884
GFT
2162jme_tx_timeout(struct net_device *netdev)
2163{
cd0ff491 2164 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2165
cdcdc9eb
GFT
2166 jme->phylink = 0;
2167 jme_reset_phy_processor(jme);
cd0ff491 2168 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT
2169 jme_set_settings(netdev, &jme->old_ecmd);
2170
8c198884 2171 /*
cdcdc9eb 2172 * Force to Reset the link again
8c198884 2173 */
29bdd921 2174 jme_reset_link(jme);
8c198884
GFT
2175}
2176
1e5ebebc
GFT
2177static inline void jme_pause_rx(struct jme_adapter *jme)
2178{
2179 atomic_dec(&jme->link_changing);
2180
2181 jme_set_rx_pcc(jme, PCC_OFF);
2182 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2183 JME_NAPI_DISABLE(jme);
2184 } else {
2185 tasklet_disable(&jme->rxclean_task);
2186 tasklet_disable(&jme->rxempty_task);
2187 }
2188}
2189
2190static inline void jme_resume_rx(struct jme_adapter *jme)
2191{
2192 struct dynpcc_info *dpi = &(jme->dpi);
2193
2194 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2195 JME_NAPI_ENABLE(jme);
2196 } else {
2197 tasklet_hi_enable(&jme->rxclean_task);
2198 tasklet_hi_enable(&jme->rxempty_task);
2199 }
2200 dpi->cur = PCC_P1;
2201 dpi->attempt = PCC_P1;
2202 dpi->cnt = 0;
2203 jme_set_rx_pcc(jme, PCC_P1);
2204
2205 atomic_inc(&jme->link_changing);
2206}
2207
8c198884 2208static void
42b1055e
GFT
2209jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2210{
2211 struct jme_adapter *jme = netdev_priv(netdev);
2212
1e5ebebc 2213 jme_pause_rx(jme);
42b1055e 2214 jme->vlgrp = grp;
1e5ebebc 2215 jme_resume_rx(jme);
42b1055e
GFT
2216}
2217
7ca9ebee
GFT
2218#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2219static void
2220jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2221{
2222 struct jme_adapter *jme = netdev_priv(netdev);
2223
7ca9ebee 2224 if(jme->vlgrp) {
1e5ebebc 2225 jme_pause_rx(jme);
7ca9ebee
GFT
2226#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2227 jme->vlgrp->vlan_devices[vid] = NULL;
2228#else
2229 vlan_group_set_device(jme->vlgrp, vid, NULL);
2230#endif
1e5ebebc 2231 jme_resume_rx(jme);
7ca9ebee 2232 }
7ca9ebee
GFT
2233}
2234#endif
2235
42b1055e 2236static void
3bf61c55
GFT
2237jme_get_drvinfo(struct net_device *netdev,
2238 struct ethtool_drvinfo *info)
d7699f87 2239{
cd0ff491 2240 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2241
cd0ff491
GFT
2242 strcpy(info->driver, DRV_NAME);
2243 strcpy(info->version, DRV_VERSION);
2244 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT
2245}
2246
3bf61c55 2247static int
8c198884
GFT
2248jme_get_regs_len(struct net_device *netdev)
2249{
cd0ff491 2250 return JME_REG_LEN;
8c198884
GFT
2251}
2252
2253static void
cd0ff491 2254mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT
2255{
2256 int i;
2257
cd0ff491 2258 for (i = 0 ; i < len ; i += 4)
79ce639c 2259 p[i >> 2] = jread32(jme, reg + i);
186fc259 2260}
8c198884 2261
186fc259 2262static void
cd0ff491 2263mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT
2264{
2265 int i;
cd0ff491 2266 u16 *p16 = (u16 *)p;
186fc259 2267
cd0ff491 2268 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2269 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT
2270}
2271
2272static void
2273jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2274{
cd0ff491
GFT
2275 struct jme_adapter *jme = netdev_priv(netdev);
2276 u32 *p32 = (u32 *)p;
8c198884 2277
186fc259 2278 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT
2279
2280 regs->version = 1;
2281 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2282
2283 p32 += 0x100 >> 2;
2284 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2285
2286 p32 += 0x100 >> 2;
2287 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2288
2289 p32 += 0x100 >> 2;
2290 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2291
186fc259
GFT
2292 p32 += 0x100 >> 2;
2293 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT
2294}
2295
2296static int
2297jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2298{
2299 struct jme_adapter *jme = netdev_priv(netdev);
2300
8c198884
GFT
2301 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2302 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2303
cd0ff491 2304 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT
2305 ecmd->use_adaptive_rx_coalesce = false;
2306 ecmd->rx_coalesce_usecs = 0;
2307 ecmd->rx_max_coalesced_frames = 0;
2308 return 0;
2309 }
2310
2311 ecmd->use_adaptive_rx_coalesce = true;
2312
cd0ff491 2313 switch (jme->dpi.cur) {
8c198884
GFT
2314 case PCC_P1:
2315 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2316 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2317 break;
2318 case PCC_P2:
2319 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2320 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2321 break;
2322 case PCC_P3:
2323 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2324 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2325 break;
2326 default:
2327 break;
2328 }
2329
2330 return 0;
2331}
2332
192570e0
GFT
2333static int
2334jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2335{
2336 struct jme_adapter *jme = netdev_priv(netdev);
2337 struct dynpcc_info *dpi = &(jme->dpi);
2338
cd0ff491 2339 if (netif_running(netdev))
cdcdc9eb
GFT
2340 return -EBUSY;
2341
7ca9ebee
GFT
2342 if (ecmd->use_adaptive_rx_coalesce &&
2343 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2344 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2345 jme->jme_rx = netif_rx;
2346 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT
2347 dpi->cur = PCC_P1;
2348 dpi->attempt = PCC_P1;
2349 dpi->cnt = 0;
2350 jme_set_rx_pcc(jme, PCC_P1);
2351 jme_interrupt_mode(jme);
7ca9ebee
GFT
2352 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2353 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2354 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2355 jme->jme_rx = netif_receive_skb;
2356 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT
2357 jme_interrupt_mode(jme);
2358 }
2359
2360 return 0;
2361}
2362
8c198884
GFT
2363static void
2364jme_get_pauseparam(struct net_device *netdev,
2365 struct ethtool_pauseparam *ecmd)
2366{
2367 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2368 u32 val;
8c198884
GFT
2369
2370 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2371 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2372
cd0ff491
GFT
2373 spin_lock_bh(&jme->phy_lock);
2374 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2375 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT
2376
2377 ecmd->autoneg =
2378 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT
2379}
2380
2381static int
2382jme_set_pauseparam(struct net_device *netdev,
2383 struct ethtool_pauseparam *ecmd)
2384{
2385 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2386 u32 val;
8c198884 2387
cd0ff491 2388 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT
2389 (ecmd->tx_pause != 0)) {
2390
cd0ff491 2391 if (ecmd->tx_pause)
8c198884
GFT
2392 jme->reg_txpfc |= TXPFC_PF_EN;
2393 else
2394 jme->reg_txpfc &= ~TXPFC_PF_EN;
2395
2396 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2397 }
2398
cd0ff491
GFT
2399 spin_lock_bh(&jme->rxmcs_lock);
2400 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT
2401 (ecmd->rx_pause != 0)) {
2402
cd0ff491 2403 if (ecmd->rx_pause)
8c198884
GFT
2404 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2405 else
2406 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2407
2408 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2409 }
cd0ff491 2410 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2411
cd0ff491
GFT
2412 spin_lock_bh(&jme->phy_lock);
2413 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2414 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT
2415 (ecmd->autoneg != 0)) {
2416
cd0ff491 2417 if (ecmd->autoneg)
8c198884
GFT
2418 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2419 else
2420 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2421
b3821cc5
GFT
2422 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2423 MII_ADVERTISE, val);
8c198884 2424 }
cd0ff491 2425 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT
2426
2427 return 0;
2428}
2429
29bdd921
GFT
2430static void
2431jme_get_wol(struct net_device *netdev,
2432 struct ethtool_wolinfo *wol)
2433{
2434 struct jme_adapter *jme = netdev_priv(netdev);
2435
2436 wol->supported = WAKE_MAGIC | WAKE_PHY;
2437
2438 wol->wolopts = 0;
2439
cd0ff491 2440 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT
2441 wol->wolopts |= WAKE_PHY;
2442
cd0ff491 2443 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT
2444 wol->wolopts |= WAKE_MAGIC;
2445
2446}
2447
2448static int
2449jme_set_wol(struct net_device *netdev,
2450 struct ethtool_wolinfo *wol)
2451{
2452 struct jme_adapter *jme = netdev_priv(netdev);
2453
cd0ff491 2454 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT
2455 WAKE_UCAST |
2456 WAKE_MCAST |
2457 WAKE_BCAST |
2458 WAKE_ARP))
2459 return -EOPNOTSUPP;
2460
2461 jme->reg_pmcs = 0;
2462
cd0ff491 2463 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT
2464 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2465
cd0ff491 2466 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT
2467 jme->reg_pmcs |= PMCS_MFEN;
2468
cd0ff491 2469 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2470
29bdd921
GFT
2471 return 0;
2472}
b3821cc5 2473
8c198884 2474static int
3bf61c55
GFT
2475jme_get_settings(struct net_device *netdev,
2476 struct ethtool_cmd *ecmd)
d7699f87
GFT
2477{
2478 struct jme_adapter *jme = netdev_priv(netdev);
2479 int rc;
8c198884 2480
cd0ff491 2481 spin_lock_bh(&jme->phy_lock);
d7699f87 2482 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2483 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT
2484 return rc;
2485}
2486
3bf61c55
GFT
2487static int
2488jme_set_settings(struct net_device *netdev,
2489 struct ethtool_cmd *ecmd)
d7699f87
GFT
2490{
2491 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2492 int rc, fdc = 0;
fcf45b4c 2493
cd0ff491 2494 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT
2495 return -EINVAL;
2496
e6b41b51
GFT
2497 /*
2498 * Check If user changed duplex only while force_media.
2499 * Hardware would not generate link change interrupt.
2500 */
cd0ff491 2501 if (jme->mii_if.force_media &&
79ce639c
GFT
2502 ecmd->autoneg != AUTONEG_ENABLE &&
2503 (jme->mii_if.full_duplex != ecmd->duplex))
2504 fdc = 1;
2505
cd0ff491 2506 spin_lock_bh(&jme->phy_lock);
d7699f87 2507 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2508 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2509
cd0ff491 2510 if (!rc) {
e6b41b51
GFT
2511 if (fdc)
2512 jme_reset_link(jme);
cd0ff491 2513 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT
2514 jme->old_ecmd = *ecmd;
2515 }
2516
d7699f87
GFT
2517 return rc;
2518}
2519
cd0ff491 2520static u32
3bf61c55
GFT
2521jme_get_link(struct net_device *netdev)
2522{
d7699f87
GFT
2523 struct jme_adapter *jme = netdev_priv(netdev);
2524 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2525}
2526
8c198884 2527static u32
cd0ff491
GFT
2528jme_get_msglevel(struct net_device *netdev)
2529{
2530 struct jme_adapter *jme = netdev_priv(netdev);
2531 return jme->msg_enable;
2532}
2533
2534static void
2535jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2536{
cd0ff491
GFT
2537 struct jme_adapter *jme = netdev_priv(netdev);
2538 jme->msg_enable = value;
2539}
8c198884 2540
cd0ff491
GFT
2541static u32
2542jme_get_rx_csum(struct net_device *netdev)
2543{
2544 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2545 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2546}
2547
2548static int
2549jme_set_rx_csum(struct net_device *netdev, u32 on)
2550{
cd0ff491 2551 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2552
cd0ff491
GFT
2553 spin_lock_bh(&jme->rxmcs_lock);
2554 if (on)
8c198884
GFT
2555 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2556 else
2557 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2558 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2559 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT
2560
2561 return 0;
2562}
2563
2564static int
2565jme_set_tx_csum(struct net_device *netdev, u32 on)
2566{
cd0ff491 2567 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2568
cd0ff491
GFT
2569 if (on) {
2570 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2571 if (netdev->mtu <= 1900)
b3821cc5 2572 netdev->features |= NETIF_F_HW_CSUM;
cd0ff491
GFT
2573 } else {
2574 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
8c198884 2575 netdev->features &= ~NETIF_F_HW_CSUM;
b3821cc5 2576 }
8c198884
GFT
2577
2578 return 0;
2579}
2580
2581static int
b3821cc5
GFT
2582jme_set_tso(struct net_device *netdev, u32 on)
2583{
cd0ff491 2584 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2585
cd0ff491
GFT
2586 if (on) {
2587 set_bit(JME_FLAG_TSO, &jme->flags);
2588 if (netdev->mtu <= 1900)
3b70a6fa
GFT
2589 netdev->features |= NETIF_F_TSO
2590#ifdef NETIF_F_TSO6
2591 | NETIF_F_TSO6
2592#endif
2593 ;
cd0ff491
GFT
2594 } else {
2595 clear_bit(JME_FLAG_TSO, &jme->flags);
3b70a6fa
GFT
2596 netdev->features &= ~(NETIF_F_TSO
2597#ifdef NETIF_F_TSO6
2598 | NETIF_F_TSO6
2599#endif
2600 );
b3821cc5
GFT
2601 }
2602
cd0ff491 2603 return 0;
b3821cc5
GFT
2604}
2605
2606static int
8c198884
GFT
2607jme_nway_reset(struct net_device *netdev)
2608{
cd0ff491 2609 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2610 jme_restart_an(jme);
2611 return 0;
2612}
2613
cd0ff491 2614static u8
186fc259
GFT
2615jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2616{
cd0ff491 2617 u32 val;
186fc259
GFT
2618 int to;
2619
2620 val = jread32(jme, JME_SMBCSR);
2621 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2622 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2623 msleep(1);
2624 val = jread32(jme, JME_SMBCSR);
2625 }
cd0ff491 2626 if (!to) {
937ef75a 2627 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2628 return 0xFF;
2629 }
2630
2631 jwrite32(jme, JME_SMBINTF,
2632 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2633 SMBINTF_HWRWN_READ |
2634 SMBINTF_HWCMD);
2635
2636 val = jread32(jme, JME_SMBINTF);
2637 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2638 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2639 msleep(1);
2640 val = jread32(jme, JME_SMBINTF);
2641 }
cd0ff491 2642 if (!to) {
937ef75a 2643 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2644 return 0xFF;
2645 }
2646
2647 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2648}
2649
2650static void
cd0ff491 2651jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2652{
cd0ff491 2653 u32 val;
186fc259
GFT
2654 int to;
2655
2656 val = jread32(jme, JME_SMBCSR);
2657 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2658 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2659 msleep(1);
2660 val = jread32(jme, JME_SMBCSR);
2661 }
cd0ff491 2662 if (!to) {
937ef75a 2663 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2664 return;
2665 }
2666
2667 jwrite32(jme, JME_SMBINTF,
2668 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2669 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2670 SMBINTF_HWRWN_WRITE |
2671 SMBINTF_HWCMD);
2672
2673 val = jread32(jme, JME_SMBINTF);
2674 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2675 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2676 msleep(1);
2677 val = jread32(jme, JME_SMBINTF);
2678 }
cd0ff491 2679 if (!to) {
937ef75a 2680 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2681 return;
2682 }
2683
2684 mdelay(2);
2685}
2686
2687static int
2688jme_get_eeprom_len(struct net_device *netdev)
2689{
cd0ff491
GFT
2690 struct jme_adapter *jme = netdev_priv(netdev);
2691 u32 val;
186fc259 2692 val = jread32(jme, JME_SMBCSR);
cd0ff491 2693 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT
2694}
2695
2696static int
2697jme_get_eeprom(struct net_device *netdev,
2698 struct ethtool_eeprom *eeprom, u8 *data)
2699{
cd0ff491 2700 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2701 int i, offset = eeprom->offset, len = eeprom->len;
2702
2703 /*
8d27293f 2704 * ethtool will check the boundary for us
186fc259
GFT
2705 */
2706 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2707 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2708 data[i] = jme_smb_read(jme, i + offset);
2709
2710 return 0;
2711}
2712
2713static int
2714jme_set_eeprom(struct net_device *netdev,
2715 struct ethtool_eeprom *eeprom, u8 *data)
2716{
cd0ff491 2717 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2718 int i, offset = eeprom->offset, len = eeprom->len;
2719
2720 if (eeprom->magic != JME_EEPROM_MAGIC)
2721 return -EINVAL;
2722
2723 /*
8d27293f 2724 * ethtool will check the boundary for us
186fc259 2725 */
cd0ff491 2726 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2727 jme_smb_write(jme, i + offset, data[i]);
2728
2729 return 0;
2730}
2731
3b70a6fa
GFT
2732#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2733static struct ethtool_ops jme_ethtool_ops = {
2734#else
d7699f87 2735static const struct ethtool_ops jme_ethtool_ops = {
3b70a6fa 2736#endif
cd0ff491 2737 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2738 .get_regs_len = jme_get_regs_len,
2739 .get_regs = jme_get_regs,
2740 .get_coalesce = jme_get_coalesce,
192570e0 2741 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT
2742 .get_pauseparam = jme_get_pauseparam,
2743 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2744 .get_wol = jme_get_wol,
2745 .set_wol = jme_set_wol,
d7699f87
GFT
2746 .get_settings = jme_get_settings,
2747 .set_settings = jme_set_settings,
2748 .get_link = jme_get_link,
cd0ff491
GFT
2749 .get_msglevel = jme_get_msglevel,
2750 .set_msglevel = jme_set_msglevel,
8c198884
GFT
2751 .get_rx_csum = jme_get_rx_csum,
2752 .set_rx_csum = jme_set_rx_csum,
2753 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT
2754 .set_tso = jme_set_tso,
2755 .set_sg = ethtool_op_set_sg,
8c198884 2756 .nway_reset = jme_nway_reset,
186fc259
GFT
2757 .get_eeprom_len = jme_get_eeprom_len,
2758 .get_eeprom = jme_get_eeprom,
2759 .set_eeprom = jme_set_eeprom,
d7699f87
GFT
2760};
2761
3bf61c55
GFT
2762static int
2763jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2764{
3b70a6fa 2765 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT
2766#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2767 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2768#else
2769 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2770#endif
2771 )
2772#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2773 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2774#else
cd0ff491 2775 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
0ede469c 2776#endif
3bf61c55
GFT
2777 return 1;
2778
3b70a6fa 2779 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT
2780#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2781 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2782#else
2783 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2784#endif
2785 )
2786#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2787 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2788#else
cd0ff491 2789 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
0ede469c 2790#endif
8c198884
GFT
2791 return 1;
2792
0ede469c
GFT
2793#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2794 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2795 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2796#else
cd0ff491
GFT
2797 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2798 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
0ede469c 2799#endif
3bf61c55
GFT
2800 return 0;
2801
2802 return -1;
2803}
2804
cd0ff491 2805static inline void
cdcdc9eb
GFT
2806jme_phy_init(struct jme_adapter *jme)
2807{
cd0ff491 2808 u16 reg26;
cdcdc9eb
GFT
2809
2810 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2811 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2812}
2813
cd0ff491 2814static inline void
cdcdc9eb 2815jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2816{
cd0ff491 2817 u32 chipmode;
cdcdc9eb
GFT
2818
2819 chipmode = jread32(jme, JME_CHIPMODE);
2820
2821 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 2822 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
42b1055e
GFT
2823}
2824
3b70a6fa
GFT
2825#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2826static const struct net_device_ops jme_netdev_ops = {
2827 .ndo_open = jme_open,
2828 .ndo_stop = jme_close,
2829 .ndo_validate_addr = eth_validate_addr,
2830 .ndo_start_xmit = jme_start_xmit,
2831 .ndo_set_mac_address = jme_set_macaddr,
2832 .ndo_set_multicast_list = jme_set_multi,
2833 .ndo_change_mtu = jme_change_mtu,
2834 .ndo_tx_timeout = jme_tx_timeout,
2835 .ndo_vlan_rx_register = jme_vlan_rx_register,
2836};
2837#endif
2838
3bf61c55
GFT
2839static int __devinit
2840jme_init_one(struct pci_dev *pdev,
2841 const struct pci_device_id *ent)
2842{
cdcdc9eb 2843 int rc = 0, using_dac, i;
d7699f87
GFT
2844 struct net_device *netdev;
2845 struct jme_adapter *jme;
cd0ff491
GFT
2846 u16 bmcr, bmsr;
2847 u32 apmc;
d7699f87
GFT
2848
2849 /*
2850 * set up PCI device basics
2851 */
4330c2f2 2852 rc = pci_enable_device(pdev);
cd0ff491 2853 if (rc) {
937ef75a 2854 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT
2855 goto err_out;
2856 }
d7699f87 2857
3bf61c55 2858 using_dac = jme_pci_dma64(pdev);
cd0ff491 2859 if (using_dac < 0) {
937ef75a 2860 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT
2861 rc = -EIO;
2862 goto err_out_disable_pdev;
2863 }
2864
cd0ff491 2865 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
937ef75a 2866 pr_err("No PCI resource region found\n");
4330c2f2
GFT
2867 rc = -ENOMEM;
2868 goto err_out_disable_pdev;
2869 }
d7699f87 2870
4330c2f2 2871 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 2872 if (rc) {
937ef75a 2873 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT
2874 goto err_out_disable_pdev;
2875 }
d7699f87
GFT
2876
2877 pci_set_master(pdev);
2878
2879 /*
2880 * alloc and init net device
2881 */
3bf61c55 2882 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 2883 if (!netdev) {
937ef75a 2884 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT
2885 rc = -ENOMEM;
2886 goto err_out_release_regions;
d7699f87 2887 }
3b70a6fa
GFT
2888#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2889 netdev->netdev_ops = &jme_netdev_ops;
2890#else
d7699f87
GFT
2891 netdev->open = jme_open;
2892 netdev->stop = jme_close;
2893 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT
2894 netdev->set_mac_address = jme_set_macaddr;
2895 netdev->set_multicast_list = jme_set_multi;
2896 netdev->change_mtu = jme_change_mtu;
8c198884 2897 netdev->tx_timeout = jme_tx_timeout;
42b1055e 2898 netdev->vlan_rx_register = jme_vlan_rx_register;
7ca9ebee
GFT
2899#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2900 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
2901#endif
3bf61c55 2902 NETDEV_GET_STATS(netdev, &jme_get_stats);
3b70a6fa
GFT
2903#endif
2904 netdev->ethtool_ops = &jme_ethtool_ops;
2905 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2906 netdev->features = NETIF_F_HW_CSUM |
b3821cc5
GFT
2907 NETIF_F_SG |
2908 NETIF_F_TSO |
3b70a6fa 2909#ifdef NETIF_F_TSO6
b3821cc5 2910 NETIF_F_TSO6 |
3b70a6fa 2911#endif
42b1055e
GFT
2912 NETIF_F_HW_VLAN_TX |
2913 NETIF_F_HW_VLAN_RX;
cd0ff491 2914 if (using_dac)
8c198884 2915 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
2916
2917 SET_NETDEV_DEV(netdev, &pdev->dev);
2918 pci_set_drvdata(pdev, netdev);
2919
2920 /*
2921 * init adapter info
2922 */
2923 jme = netdev_priv(netdev);
2924 jme->pdev = pdev;
2925 jme->dev = netdev;
cdcdc9eb
GFT
2926 jme->jme_rx = netif_rx;
2927 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 2928 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2929 jme->phylink = 0;
b3821cc5 2930 jme->tx_ring_size = 1 << 10;
0ede469c 2931 jme->tx_ring_mask = jme->tx_ring_size - 1;
b3821cc5
GFT
2932 jme->tx_wake_threshold = 1 << 9;
2933 jme->rx_ring_size = 1 << 9;
2934 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 2935 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT
2936 jme->regs = ioremap(pci_resource_start(pdev, 0),
2937 pci_resource_len(pdev, 0));
4330c2f2 2938 if (!(jme->regs)) {
937ef75a 2939 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT
2940 rc = -ENOMEM;
2941 goto err_out_free_netdev;
2942 }
4330c2f2 2943
cd0ff491
GFT
2944 if (no_pseudohp) {
2945 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2946 jwrite32(jme, JME_APMC, apmc);
2947 } else if (force_pseudohp) {
2948 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2949 jwrite32(jme, JME_APMC, apmc);
2950 }
2951
cdcdc9eb 2952 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 2953
d7699f87 2954 spin_lock_init(&jme->phy_lock);
fcf45b4c 2955 spin_lock_init(&jme->macaddr_lock);
8c198884 2956 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2957
fcf45b4c
GFT
2958 atomic_set(&jme->link_changing, 1);
2959 atomic_set(&jme->rx_cleaning, 1);
2960 atomic_set(&jme->tx_cleaning, 1);
192570e0 2961 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2962
79ce639c 2963 tasklet_init(&jme->pcc_task,
7ca9ebee 2964 jme_pcc_tasklet,
79ce639c 2965 (unsigned long) jme);
4330c2f2 2966 tasklet_init(&jme->linkch_task,
7ca9ebee 2967 jme_link_change_tasklet,
4330c2f2
GFT
2968 (unsigned long) jme);
2969 tasklet_init(&jme->txclean_task,
7ca9ebee 2970 jme_tx_clean_tasklet,
4330c2f2
GFT
2971 (unsigned long) jme);
2972 tasklet_init(&jme->rxclean_task,
7ca9ebee 2973 jme_rx_clean_tasklet,
4330c2f2 2974 (unsigned long) jme);
fcf45b4c 2975 tasklet_init(&jme->rxempty_task,
7ca9ebee 2976 jme_rx_empty_tasklet,
fcf45b4c 2977 (unsigned long) jme);
0ede469c 2978 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT
2979 tasklet_disable_nosync(&jme->txclean_task);
2980 tasklet_disable_nosync(&jme->rxclean_task);
2981 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT
2982 jme->dpi.cur = PCC_P1;
2983
cd0ff491 2984 jme->reg_ghc = 0;
79ce639c 2985 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
2986 jme->reg_rxmcs = RXMCS_DEFAULT;
2987 jme->reg_txpfc = 0;
47220951 2988 jme->reg_pmcs = PMCS_MFEN;
cd0ff491
GFT
2989 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2990 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 2991
d7699f87 2992 /*
fcf45b4c
GFT
2993 * Get Max Read Req Size from PCI Config Space
2994 */
cd0ff491
GFT
2995 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2996 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2997 switch (jme->mrrs) {
2998 case MRRS_128B:
2999 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3000 break;
3001 case MRRS_256B:
3002 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3003 break;
3004 default:
3005 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3006 break;
cd54cf32 3007 }
fcf45b4c 3008
fcf45b4c 3009 /*
cdcdc9eb 3010 * Must check before reset_mac_processor
d7699f87 3011 */
cdcdc9eb
GFT
3012 jme_check_hw_ver(jme);
3013 jme->mii_if.dev = netdev;
cd0ff491 3014 if (jme->fpgaver) {
cdcdc9eb 3015 jme->mii_if.phy_id = 0;
cd0ff491 3016 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT
3017 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3018 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3019 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT
3020 jme->mii_if.phy_id = i;
3021 break;
3022 }
3023 }
3024
cd0ff491 3025 if (!jme->mii_if.phy_id) {
cdcdc9eb 3026 rc = -EIO;
937ef75a
JP
3027 pr_err("Can not find phy_id\n");
3028 goto err_out_unmap;
cdcdc9eb
GFT
3029 }
3030
3031 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3032 } else {
cdcdc9eb
GFT
3033 jme->mii_if.phy_id = 1;
3034 }
cd0ff491 3035 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
3036 jme->mii_if.supports_gmii = true;
3037 else
3038 jme->mii_if.supports_gmii = false;
cdcdc9eb
GFT
3039 jme->mii_if.mdio_read = jme_mdio_read;
3040 jme->mii_if.mdio_write = jme_mdio_write;
3041
d7699f87 3042 jme_clear_pm(jme);
58c92f28 3043 jme_set_phyfifoa(jme);
cd0ff491
GFT
3044 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
3045 if (!jme->fpgaver)
cdcdc9eb 3046 jme_phy_init(jme);
42b1055e 3047 jme_phy_off(jme);
cdcdc9eb
GFT
3048
3049 /*
3050 * Reset MAC processor and reload EEPROM for MAC Address
3051 */
d7699f87 3052 jme_reset_mac_processor(jme);
4330c2f2 3053 rc = jme_reload_eeprom(jme);
cd0ff491 3054 if (rc) {
937ef75a 3055 pr_err("Reload eeprom for reading MAC Address error\n");
0ede469c 3056 goto err_out_unmap;
4330c2f2 3057 }
d7699f87
GFT
3058 jme_load_macaddr(netdev);
3059
d7699f87
GFT
3060 /*
3061 * Tell stack that we are not ready to work until open()
3062 */
3063 netif_carrier_off(netdev);
3064 netif_stop_queue(netdev);
3065
3066 /*
3067 * Register netdev
3068 */
4330c2f2 3069 rc = register_netdev(netdev);
cd0ff491 3070 if (rc) {
937ef75a 3071 pr_err("Cannot register net device\n");
0ede469c 3072 goto err_out_unmap;
4330c2f2 3073 }
d7699f87 3074
937ef75a
JP
3075 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x "
3076 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
7ca9ebee
GFT
3077 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3078 "JMC250 Gigabit Ethernet" :
3079 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3080 "JMC260 Fast Ethernet" : "Unknown",
3081 (jme->fpgaver != 0) ? " (FPGA)" : "",
3082 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
937ef75a
JP
3083 jme->rev,
3084 netdev->dev_addr[0],
3085 netdev->dev_addr[1],
3086 netdev->dev_addr[2],
3087 netdev->dev_addr[3],
3088 netdev->dev_addr[4],
3089 netdev->dev_addr[5]);
d7699f87
GFT
3090
3091 return 0;
3092
3093err_out_unmap:
3094 iounmap(jme->regs);
3095err_out_free_netdev:
3096 pci_set_drvdata(pdev, NULL);
3097 free_netdev(netdev);
4330c2f2
GFT
3098err_out_release_regions:
3099 pci_release_regions(pdev);
d7699f87 3100err_out_disable_pdev:
cd0ff491 3101 pci_disable_device(pdev);
d7699f87 3102err_out:
4330c2f2 3103 return rc;
d7699f87
GFT
3104}
3105
3bf61c55
GFT
3106static void __devexit
3107jme_remove_one(struct pci_dev *pdev)
3108{
d7699f87
GFT
3109 struct net_device *netdev = pci_get_drvdata(pdev);
3110 struct jme_adapter *jme = netdev_priv(netdev);
3111
3112 unregister_netdev(netdev);
3113 iounmap(jme->regs);
3114 pci_set_drvdata(pdev, NULL);
3115 free_netdev(netdev);
3116 pci_release_regions(pdev);
3117 pci_disable_device(pdev);
3118
3119}
3120
7ee473a3 3121#ifdef CONFIG_PM
29bdd921
GFT
3122static int
3123jme_suspend(struct pci_dev *pdev, pm_message_t state)
3124{
3125 struct net_device *netdev = pci_get_drvdata(pdev);
3126 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT
3127
3128 atomic_dec(&jme->link_changing);
3129
3130 netif_device_detach(netdev);
3131 netif_stop_queue(netdev);
3132 jme_stop_irq(jme);
29bdd921 3133
cd0ff491
GFT
3134 tasklet_disable(&jme->txclean_task);
3135 tasklet_disable(&jme->rxclean_task);
3136 tasklet_disable(&jme->rxempty_task);
3137
cd0ff491
GFT
3138 if (netif_carrier_ok(netdev)) {
3139 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT
3140 jme_polling_mode(jme);
3141
29bdd921 3142 jme_stop_pcc_timer(jme);
cd0ff491
GFT
3143 jme_reset_ghc_speed(jme);
3144 jme_disable_rx_engine(jme);
3145 jme_disable_tx_engine(jme);
29bdd921
GFT
3146 jme_reset_mac_processor(jme);
3147 jme_free_rx_resources(jme);
3148 jme_free_tx_resources(jme);
3149 netif_carrier_off(netdev);
3150 jme->phylink = 0;
3151 }
3152
cd0ff491
GFT
3153 tasklet_enable(&jme->txclean_task);
3154 tasklet_hi_enable(&jme->rxclean_task);
3155 tasklet_hi_enable(&jme->rxempty_task);
29bdd921
GFT
3156
3157 pci_save_state(pdev);
cd0ff491 3158 if (jme->reg_pmcs) {
42b1055e 3159 jme_set_100m_half(jme);
47220951 3160
cd0ff491 3161 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
47220951
GFT
3162 jme_wait_link(jme);
3163
29bdd921 3164 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
cd0ff491 3165
42b1055e 3166 pci_enable_wake(pdev, PCI_D3cold, true);
cd0ff491 3167 } else {
42b1055e 3168 jme_phy_off(jme);
29bdd921 3169 }
cd0ff491 3170 pci_set_power_state(pdev, PCI_D3cold);
29bdd921
GFT
3171
3172 return 0;
3173}
3174
3175static int
3176jme_resume(struct pci_dev *pdev)
3177{
3178 struct net_device *netdev = pci_get_drvdata(pdev);
3179 struct jme_adapter *jme = netdev_priv(netdev);
3180
3181 jme_clear_pm(jme);
3182 pci_restore_state(pdev);
3183
e58b908e
GFT
3184 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3185 jme_phy_on(jme);
29bdd921 3186 jme_set_settings(netdev, &jme->old_ecmd);
e58b908e 3187 } else {
29bdd921 3188 jme_reset_phy_processor(jme);
e58b908e 3189 }
29bdd921 3190
29bdd921
GFT
3191 jme_start_irq(jme);
3192 netif_device_attach(netdev);
3193
3194 atomic_inc(&jme->link_changing);
3195
3196 jme_reset_link(jme);
3197
3198 return 0;
3199}
7ee473a3 3200#endif
29bdd921 3201
7ca9ebee 3202#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
d7699f87 3203static struct pci_device_id jme_pci_tbl[] = {
7ca9ebee
GFT
3204#else
3205static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3206#endif
cd0ff491
GFT
3207 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3208 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT
3209 { }
3210};
3211
3212static struct pci_driver jme_driver = {
cd0ff491
GFT
3213 .name = DRV_NAME,
3214 .id_table = jme_pci_tbl,
3215 .probe = jme_init_one,
3216 .remove = __devexit_p(jme_remove_one),
d7699f87 3217#ifdef CONFIG_PM
cd0ff491
GFT
3218 .suspend = jme_suspend,
3219 .resume = jme_resume,
d7699f87 3220#endif /* CONFIG_PM */
d7699f87
GFT
3221};
3222
3bf61c55
GFT
3223static int __init
3224jme_init_module(void)
d7699f87 3225{
937ef75a 3226 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT
3227 return pci_register_driver(&jme_driver);
3228}
3229
3bf61c55
GFT
3230static void __exit
3231jme_cleanup_module(void)
d7699f87
GFT
3232{
3233 pci_unregister_driver(&jme_driver);
3234}
3235
3236module_init(jme_init_module);
3237module_exit(jme_cleanup_module);
3238
3bf61c55 3239MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
3240MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3241MODULE_LICENSE("GPL");
3242MODULE_VERSION(DRV_VERSION);
3243MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3244