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net: introduce and use netdev_features_t for device features sets
[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT		 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
2e582300 25#include <linux/version.h>
937ef75a
JP		 26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
d7699f87
GFT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
4330c2f2 38#include <linux/delay.h>
29bdd921 39#include <linux/spinlock.h>
8c198884
GFT		 40#include <linux/in.h>
41#include <linux/ip.h>
79ce639c
GFT		 42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
42b1055e 45#include <linux/if_vlan.h>
38d1bc09 46#include <linux/slab.h>
3b70a6fa 47#include <net/ip6_checksum.h>
d7699f87
GFT		 48#include "jme.h"
49
cd0ff491
GFT		 50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 61
6d06d88c 62#ifndef JME_NEW_PM_API
3d12cc1b
GFT		 63static void
64jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
65{
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
67 pci_enable_wake(jme->pdev, PCI_D1, enable);
68 pci_enable_wake(jme->pdev, PCI_D2, enable);
69 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
70 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
71#else
72 pci_pme_active(jme->pdev, enable);
73#endif
74}
6d06d88c 75#endif
3d12cc1b 76
3bf61c55
GFT		 77static int
78jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 79{
80 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 81 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 82
186fc259 83read_again:
cd0ff491 84 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 85 smi_phy_addr(phy) |
86 smi_reg_addr(reg));
d7699f87
GFT		 87
88 wmb();
cd0ff491 89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 90 udelay(20);
b3821cc5
GFT		 91 val = jread32(jme, JME_SMI);
92 if ((val & SMI_OP_REQ) == 0)
3bf61c55 93 break;
cd0ff491 94 }
d7699f87 95
cd0ff491 96 if (i == 0) {
937ef75a 97 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 98 return 0;
cd0ff491 99 }
d7699f87 100
cd0ff491 101 if (again--)
186fc259
GFT		 102 goto read_again;
103
cd0ff491 104 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 105}
106
3bf61c55
GFT		 107static void
108jme_mdio_write(struct net_device *netdev,
109 int phy, int reg, int val)
d7699f87
GFT		 110{
111 struct jme_adapter *jme = netdev_priv(netdev);
112 int i;
113
3bf61c55
GFT		 114 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
115 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
116 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 117
118 wmb();
cdcdc9eb
GFT		 119 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
120 udelay(20);
8d27293f 121 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 122 break;
123 }
d7699f87 124
3bf61c55 125 if (i == 0)
937ef75a 126 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT		 127}
128
cd0ff491 129static inline void
3bf61c55 130jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 131{
cd0ff491 132 u32 val;
3bf61c55
GFT		 133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
8c198884
GFT		 136 MII_ADVERTISE, ADVERTISE_ALL |
137 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 138
cd0ff491 139 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 140 jme_mdio_write(jme->dev,
141 jme->mii_if.phy_id,
142 MII_CTRL1000,
143 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 144
fcf45b4c
GFT		 145 val = jme_mdio_read(jme->dev,
146 jme->mii_if.phy_id,
147 MII_BMCR);
148
149 jme_mdio_write(jme->dev,
150 jme->mii_if.phy_id,
151 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT		 152}
153
b3821cc5
GFT		 154static void
155jme_setup_wakeup_frame(struct jme_adapter *jme,
a4181cd4 156 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 157{
158 int i;
159
160 /*
161 * Setup CRC pattern
162 */
163 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
164 wmb();
165 jwrite32(jme, JME_WFODP, crc);
166 wmb();
167
168 /*
169 * Setup Mask
170 */
cd0ff491 171 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 172 jwrite32(jme, JME_WFOI,
173 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
174 (fnr & WFOI_FRAME_SEL));
175 wmb();
176 jwrite32(jme, JME_WFODP, mask[i]);
177 wmb();
178 }
179}
3bf61c55 180
dc4185bd
GFT		 181static inline void
182jme_mac_rxclk_off(struct jme_adapter *jme)
183{
184 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
185 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
186}
187
188static inline void
189jme_mac_rxclk_on(struct jme_adapter *jme)
190{
191 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
192 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
193}
194
195static inline void
196jme_mac_txclk_off(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_mac_txclk_on(struct jme_adapter *jme)
204{
205 u32 speed = jme->reg_ghc & GHC_SPEED;
206 if (speed == GHC_SPEED_1000M)
207 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
208 else
209 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
210 jwrite32f(jme, JME_GHC, jme->reg_ghc);
211}
212
213static inline void
214jme_reset_ghc_speed(struct jme_adapter *jme)
215{
216 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_reset_250A2_workaround(struct jme_adapter *jme)
222{
223 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
224 GPREG1_RSSPATCH);
225 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
226}
227
228static inline void
229jme_assert_ghc_reset(struct jme_adapter *jme)
230{
231 jme->reg_ghc |= GHC_SWRST;
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
233}
234
235static inline void
236jme_clear_ghc_reset(struct jme_adapter *jme)
237{
238 jme->reg_ghc &= ~GHC_SWRST;
239 jwrite32f(jme, JME_GHC, jme->reg_ghc);
240}
241
cd0ff491 242static inline void
3bf61c55
GFT		 243jme_reset_mac_processor(struct jme_adapter *jme)
244{
a4181cd4 245 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT		 246 u32 crc = 0xCDCDCDCD;
247 u32 gpreg0;
b3821cc5
GFT		 248 int i;
249
dc4185bd
GFT		 250 jme_reset_ghc_speed(jme);
251 jme_reset_250A2_workaround(jme);
252
253 jme_mac_rxclk_on(jme);
254 jme_mac_txclk_on(jme);
255 udelay(1);
256 jme_assert_ghc_reset(jme);
257 udelay(1);
258 jme_mac_rxclk_off(jme);
259 jme_mac_txclk_off(jme);
260 udelay(1);
261 jme_clear_ghc_reset(jme);
262 udelay(1);
263 jme_mac_rxclk_on(jme);
264 jme_mac_txclk_on(jme);
265 udelay(1);
266 jme_mac_rxclk_off(jme);
267 jme_mac_txclk_off(jme);
cd0ff491
GFT		 268
269 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
270 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
271 jwrite32(jme, JME_RXQDC, 0x00000000);
272 jwrite32(jme, JME_RXNDA, 0x00000000);
273 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
274 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
275 jwrite32(jme, JME_TXQDC, 0x00000000);
276 jwrite32(jme, JME_TXNDA, 0x00000000);
277
4330c2f2
GFT		 278 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
279 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 280 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 281 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 282 if (jme->fpgaver)
cdcdc9eb
GFT		 283 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
284 else
285 gpreg0 = GPREG0_DEFAULT;
286 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT		 287}
288
289static inline void
3bf61c55 290jme_clear_pm(struct jme_adapter *jme)
d7699f87 291{
3d12cc1b 292 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
d7699f87
GFT		 293}
294
3bf61c55
GFT		 295static int
296jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 297{
cd0ff491 298 u32 val;
d7699f87
GFT		 299 int i;
300
301 val = jread32(jme, JME_SMBCSR);
302
cd0ff491 303 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 304 val |= SMBCSR_CNACK;
305 jwrite32(jme, JME_SMBCSR, val);
306 val |= SMBCSR_RELOAD;
307 jwrite32(jme, JME_SMBCSR, val);
308 mdelay(12);
309
cd0ff491 310 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 311 mdelay(1);
312 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
313 break;
314 }
315
cd0ff491 316 if (i == 0) {
937ef75a 317 pr_err("eeprom reload timeout\n");
d7699f87
GFT		 318 return -EIO;
319 }
320 }
3bf61c55 321
d7699f87
GFT		 322 return 0;
323}
324
3bf61c55
GFT		 325static void
326jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 327{
328 struct jme_adapter *jme = netdev_priv(netdev);
329 unsigned char macaddr[6];
cd0ff491 330 u32 val;
d7699f87 331
cd0ff491 332 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 333 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 334 macaddr[0] = (val >> 0) & 0xFF;
335 macaddr[1] = (val >> 8) & 0xFF;
336 macaddr[2] = (val >> 16) & 0xFF;
337 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 338 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 339 macaddr[4] = (val >> 0) & 0xFF;
340 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 341 memcpy(netdev->dev_addr, macaddr, 6);
342 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 343}
344
cd0ff491 345static inline void
3bf61c55
GFT		 346jme_set_rx_pcc(struct jme_adapter *jme, int p)
347{
cd0ff491 348 switch (p) {
192570e0
GFT		 349 case PCC_OFF:
350 jwrite32(jme, JME_PCCRX0,
351 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
352 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
353 break;
3bf61c55
GFT		 354 case PCC_P1:
355 jwrite32(jme, JME_PCCRX0,
356 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
357 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
358 break;
359 case PCC_P2:
360 jwrite32(jme, JME_PCCRX0,
361 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
362 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
363 break;
364 case PCC_P3:
365 jwrite32(jme, JME_PCCRX0,
366 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
367 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
368 break;
369 default:
370 break;
371 }
192570e0 372 wmb();
3bf61c55 373
cd0ff491 374 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
7ca9ebee 375 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 376}
377
fcf45b4c 378static void
3bf61c55 379jme_start_irq(struct jme_adapter *jme)
d7699f87 380{
3bf61c55
GFT		 381 register struct dynpcc_info *dpi = &(jme->dpi);
382
383 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 384 dpi->cur = PCC_P1;
385 dpi->attempt = PCC_P1;
386 dpi->cnt = 0;
387
388 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 389 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
390 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 391 PCCTXQ0_EN
392 );
393
d7699f87
GFT		 394 /*
395 * Enable Interrupts
396 */
397 jwrite32(jme, JME_IENS, INTR_ENABLE);
398}
399
cd0ff491 400static inline void
3bf61c55 401jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 402{
403 /*
404 * Disable Interrupts
405 */
cd0ff491 406 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 407}
408
cd0ff491 409static u32
cdcdc9eb
GFT		 410jme_linkstat_from_phy(struct jme_adapter *jme)
411{
cd0ff491 412 u32 phylink, bmsr;
cdcdc9eb
GFT		 413
414 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
415 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 416 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 417 phylink |= PHY_LINK_AUTONEG_COMPLETE;
418
419 return phylink;
420}
421
cd0ff491 422static inline void
55d19799 423jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT		 424{
425 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
426}
427
428static inline void
55d19799 429jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT		 430{
431 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
432}
433
fcf45b4c
GFT		 434static int
435jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 436{
437 struct jme_adapter *jme = netdev_priv(netdev);
dc4185bd 438 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 439 char linkmsg[64];
fcf45b4c 440 int rc = 0;
d7699f87 441
b3821cc5 442 linkmsg[0] = '\0';
cdcdc9eb 443
cd0ff491 444 if (jme->fpgaver)
cdcdc9eb
GFT		 445 phylink = jme_linkstat_from_phy(jme);
446 else
447 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 448
cd0ff491
GFT		 449 if (phylink & PHY_LINK_UP) {
450 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 451 /*
452 * If we did not enable AN
453 * Speed/Duplex Info should be obtained from SMI
454 */
455 phylink = PHY_LINK_UP;
456
457 bmcr = jme_mdio_read(jme->dev,
458 jme->mii_if.phy_id,
459 MII_BMCR);
460
461 phylink |= ((bmcr & BMCR_SPEED1000) &&
462 (bmcr & BMCR_SPEED100) == 0) ?
463 PHY_LINK_SPEED_1000M :
464 (bmcr & BMCR_SPEED100) ?
465 PHY_LINK_SPEED_100M :
466 PHY_LINK_SPEED_10M;
467
468 phylink |= (bmcr & BMCR_FULLDPLX) ?
469 PHY_LINK_DUPLEX : 0;
79ce639c 470
b3821cc5 471 strcat(linkmsg, "Forced: ");
cd0ff491 472 } else {
8c198884
GFT		 473 /*
474 * Keep polling for speed/duplex resolve complete
475 */
cd0ff491 476 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 477 --cnt) {
478
479 udelay(1);
8c198884 480
cd0ff491 481 if (jme->fpgaver)
cdcdc9eb
GFT		 482 phylink = jme_linkstat_from_phy(jme);
483 else
484 phylink = jread32(jme, JME_PHY_LINK);
8c198884 485 }
cd0ff491 486 if (!cnt)
937ef75a 487 pr_err("Waiting speed resolve timeout\n");
79ce639c 488
b3821cc5 489 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 490 }
491
cd0ff491 492 if (jme->phylink == phylink) {
fcf45b4c
GFT		 493 rc = 1;
494 goto out;
495 }
cd0ff491 496 if (testonly)
fcf45b4c
GFT		 497 goto out;
498
499 jme->phylink = phylink;
500
dc4185bd
GFT		 501 /*
502 * The speed/duplex setting of jme->reg_ghc already cleared
503 * by jme_reset_mac_processor()
504 */
cd0ff491
GFT		 505 switch (phylink & PHY_LINK_SPEED_MASK) {
506 case PHY_LINK_SPEED_10M:
dc4185bd 507 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 508 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 509 break;
510 case PHY_LINK_SPEED_100M:
dc4185bd 511 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 512 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 513 break;
514 case PHY_LINK_SPEED_1000M:
dc4185bd 515 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 516 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 517 break;
518 default:
519 break;
d7699f87 520 }
d7699f87 521
cd0ff491 522 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 523 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
809b2798 524 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
dc4185bd 525 jme->reg_ghc |= GHC_DPX;
cd0ff491 526 } else {
d7699f87 527 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 528 TXMCS_BACKOFF |
529 TXMCS_CARRIERSENSE |
530 TXMCS_COLLISION);
809b2798 531 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 532 }
7ee473a3 533
dc4185bd
GFT		 534 jwrite32(jme, JME_GHC, jme->reg_ghc);
535
7ee473a3 536 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
dc4185bd
GFT		 537 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
538 GPREG1_RSSPATCH);
7ee473a3 539 if (!(phylink & PHY_LINK_DUPLEX))
dc4185bd 540 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
7ee473a3
GFT		 541 switch (phylink & PHY_LINK_SPEED_MASK) {
542 case PHY_LINK_SPEED_10M:
55d19799 543 jme_set_phyfifo_8level(jme);
dc4185bd 544 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 545 break;
546 case PHY_LINK_SPEED_100M:
55d19799 547 jme_set_phyfifo_5level(jme);
dc4185bd 548 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 549 break;
550 case PHY_LINK_SPEED_1000M:
55d19799 551 jme_set_phyfifo_8level(jme);
7ee473a3
GFT		 552 break;
553 default:
554 break;
555 }
556 }
dc4185bd 557 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 558
3b70a6fa
GFT		 559 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
560 "Full-Duplex, " :
561 "Half-Duplex, ");
562 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
563 "MDI-X" :
564 "MDI");
937ef75a 565 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT		 566 netif_carrier_on(netdev);
567 } else {
568 if (testonly)
fcf45b4c
GFT		 569 goto out;
570
937ef75a 571 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 572 jme->phylink = 0;
cd0ff491 573 netif_carrier_off(netdev);
d7699f87 574 }
fcf45b4c
GFT		 575
576out:
577 return rc;
d7699f87
GFT		 578}
579
3bf61c55
GFT		 580static int
581jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 582{
d7699f87
GFT		 583 struct jme_ring *txring = &(jme->txring[0]);
584
585 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 586 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
587 &(txring->dmaalloc),
588 GFP_ATOMIC);
fcf45b4c 589
0ede469c
GFT		 590 if (!txring->alloc)
591 goto err_set_null;
d7699f87
GFT		 592
593 /*
594 * 16 Bytes align
595 */
cd0ff491 596 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 597 RING_DESC_ALIGN);
4330c2f2 598 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 599 txring->next_to_use = 0;
cdcdc9eb 600 atomic_set(&txring->next_to_clean, 0);
b3821cc5 601 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 602
0ede469c
GFT		 603 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
604 jme->tx_ring_size, GFP_ATOMIC);
605 if (unlikely(!(txring->bufinf)))
606 goto err_free_txring;
607
d7699f87 608 /*
b3821cc5 609 * Initialize Transmit Descriptors
d7699f87 610 */
b3821cc5 611 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 612 memset(txring->bufinf, 0,
b3821cc5 613 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 614
615 return 0;
0ede469c
GFT		 616
617err_free_txring:
618 dma_free_coherent(&(jme->pdev->dev),
619 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
620 txring->alloc,
621 txring->dmaalloc);
622
623err_set_null:
624 txring->desc = NULL;
625 txring->dmaalloc = 0;
626 txring->dma = 0;
627 txring->bufinf = NULL;
628
629 return -ENOMEM;
d7699f87
GFT		 630}
631
3bf61c55
GFT		 632static void
633jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 634{
635 int i;
636 struct jme_ring *txring = &(jme->txring[0]);
0ede469c 637 struct jme_buffer_info *txbi;
d7699f87 638
cd0ff491 639 if (txring->alloc) {
0ede469c
GFT		 640 if (txring->bufinf) {
641 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
642 txbi = txring->bufinf + i;
643 if (txbi->skb) {
644 dev_kfree_skb(txbi->skb);
645 txbi->skb = NULL;
646 }
647 txbi->mapping = 0;
648 txbi->len = 0;
649 txbi->nr_desc = 0;
650 txbi->start_xmit = 0;
d7699f87 651 }
0ede469c 652 kfree(txring->bufinf);
d7699f87
GFT		 653 }
654
655 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 656 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 657 txring->alloc,
658 txring->dmaalloc);
3bf61c55
GFT		 659
660 txring->alloc = NULL;
661 txring->desc = NULL;
662 txring->dmaalloc = 0;
663 txring->dma = 0;
0ede469c 664 txring->bufinf = NULL;
d7699f87 665 }
3bf61c55 666 txring->next_to_use = 0;
cdcdc9eb 667 atomic_set(&txring->next_to_clean, 0);
79ce639c 668 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 669}
670
cd0ff491 671static inline void
3bf61c55 672jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 673{
674 /*
675 * Select Queue 0
676 */
677 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 678 wmb();
d7699f87
GFT		 679
680 /*
681 * Setup TX Queue 0 DMA Bass Address
682 */
fcf45b4c 683 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 684 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 685 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 686
687 /*
688 * Setup TX Descptor Count
689 */
b3821cc5 690 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 691
692 /*
693 * Enable TX Engine
694 */
695 wmb();
dc4185bd 696 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT		 697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
d7699f87 699
dc4185bd
GFT		 700 /*
701 * Start clock for TX MAC Processor
702 */
703 jme_mac_txclk_on(jme);
d7699f87
GFT		 704}
705
cd0ff491 706static inline void
29bdd921
GFT		 707jme_restart_tx_engine(struct jme_adapter *jme)
708{
709 /*
710 * Restart TX Engine
711 */
712 jwrite32(jme, JME_TXCS, jme->reg_txcs |
713 TXCS_SELECT_QUEUE0 |
714 TXCS_ENABLE);
715}
716
cd0ff491 717static inline void
3bf61c55 718jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 719{
720 int i;
cd0ff491 721 u32 val;
d7699f87
GFT		 722
723 /*
724 * Disable TX Engine
725 */
fcf45b4c 726 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 727 wmb();
d7699f87
GFT		 728
729 val = jread32(jme, JME_TXCS);
cd0ff491 730 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 731 mdelay(1);
d7699f87 732 val = jread32(jme, JME_TXCS);
cd0ff491 733 rmb();
d7699f87
GFT		 734 }
735
cd0ff491 736 if (!i)
937ef75a 737 pr_err("Disable TX engine timeout\n");
dc4185bd
GFT		 738
739 /*
740 * Stop clock for TX MAC Processor
741 */
742 jme_mac_txclk_off(jme);
d7699f87
GFT		 743}
744
3bf61c55
GFT		 745static void
746jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 747{
0ede469c 748 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 749 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 750 struct jme_buffer_info *rxbi = rxring->bufinf;
751 rxdesc += i;
752 rxbi += i;
753
754 rxdesc->dw[0] = 0;
755 rxdesc->dw[1] = 0;
3bf61c55 756 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 757 rxdesc->desc1.bufaddrl = cpu_to_le32(
758 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 759 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 760 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 761 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 762 wmb();
3bf61c55 763 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 764}
765
3bf61c55
GFT		 766static int
767jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 768{
769 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 770 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 771 struct sk_buff *skb;
1eef180c 772 dma_addr_t mapping;
4330c2f2 773
79ce639c
GFT		 774 skb = netdev_alloc_skb(jme->dev,
775 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 776 if (unlikely(!skb))
4330c2f2 777 return -ENOMEM;
3b70a6fa
GFT		 778#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
779 skb->dev = jme->dev;
780#endif
3bf61c55 781
1eef180c
GFT		 782 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
783 offset_in_page(skb->data), skb_tailroom(skb),
784 PCI_DMA_FROMDEVICE);
785 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
786 dev_kfree_skb(skb);
787 return -ENOMEM;
788 }
789
790 if (likely(rxbi->mapping))
791 pci_unmap_page(jme->pdev, rxbi->mapping,
792 rxbi->len, PCI_DMA_FROMDEVICE);
793
4330c2f2 794 rxbi->skb = skb;
3bf61c55 795 rxbi->len = skb_tailroom(skb);
1eef180c 796 rxbi->mapping = mapping;
4330c2f2
GFT		 797 return 0;
798}
799
3bf61c55
GFT		 800static void
801jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 802{
803 struct jme_ring *rxring = &(jme->rxring[0]);
804 struct jme_buffer_info *rxbi = rxring->bufinf;
805 rxbi += i;
806
cd0ff491 807 if (rxbi->skb) {
b3821cc5 808 pci_unmap_page(jme->pdev,
4330c2f2 809 rxbi->mapping,
3bf61c55 810 rxbi->len,
4330c2f2
GFT		 811 PCI_DMA_FROMDEVICE);
812 dev_kfree_skb(rxbi->skb);
813 rxbi->skb = NULL;
814 rxbi->mapping = 0;
3bf61c55 815 rxbi->len = 0;
4330c2f2
GFT		 816 }
817}
818
3bf61c55
GFT		 819static void
820jme_free_rx_resources(struct jme_adapter *jme)
821{
822 int i;
823 struct jme_ring *rxring = &(jme->rxring[0]);
824
cd0ff491 825 if (rxring->alloc) {
0ede469c
GFT		 826 if (rxring->bufinf) {
827 for (i = 0 ; i < jme->rx_ring_size ; ++i)
828 jme_free_rx_buf(jme, i);
829 kfree(rxring->bufinf);
830 }
3bf61c55
GFT		 831
832 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 833 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 834 rxring->alloc,
835 rxring->dmaalloc);
836 rxring->alloc = NULL;
837 rxring->desc = NULL;
838 rxring->dmaalloc = 0;
839 rxring->dma = 0;
0ede469c 840 rxring->bufinf = NULL;
3bf61c55
GFT		 841 }
842 rxring->next_to_use = 0;
cdcdc9eb 843 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 844}
845
846static int
847jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 848{
849 int i;
850 struct jme_ring *rxring = &(jme->rxring[0]);
851
852 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 853 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
854 &(rxring->dmaalloc),
855 GFP_ATOMIC);
0ede469c
GFT		 856 if (!rxring->alloc)
857 goto err_set_null;
d7699f87
GFT		 858
859 /*
860 * 16 Bytes align
861 */
cd0ff491 862 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 863 RING_DESC_ALIGN);
4330c2f2 864 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 865 rxring->next_to_use = 0;
cdcdc9eb 866 atomic_set(&rxring->next_to_clean, 0);
d7699f87 867
0ede469c
GFT		 868 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
869 jme->rx_ring_size, GFP_ATOMIC);
870 if (unlikely(!(rxring->bufinf)))
871 goto err_free_rxring;
872
d7699f87
GFT		 873 /*
874 * Initiallize Receive Descriptors
875 */
0ede469c
GFT		 876 memset(rxring->bufinf, 0,
877 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 878 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
879 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 880 jme_free_rx_resources(jme);
881 return -ENOMEM;
882 }
d7699f87
GFT		 883
884 jme_set_clean_rxdesc(jme, i);
885 }
886
d7699f87 887 return 0;
0ede469c
GFT		 888
889err_free_rxring:
890 dma_free_coherent(&(jme->pdev->dev),
891 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
892 rxring->alloc,
893 rxring->dmaalloc);
894err_set_null:
895 rxring->desc = NULL;
896 rxring->dmaalloc = 0;
897 rxring->dma = 0;
898 rxring->bufinf = NULL;
899
900 return -ENOMEM;
d7699f87
GFT		 901}
902
cd0ff491 903static inline void
3bf61c55 904jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 905{
cd0ff491
GFT		 906 /*
907 * Select Queue 0
908 */
909 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
910 RXCS_QUEUESEL_Q0);
911 wmb();
912
d7699f87
GFT		 913 /*
914 * Setup RX DMA Bass Address
915 */
0ede469c 916 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 917 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
0ede469c 918 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 919
920 /*
b3821cc5 921 * Setup RX Descriptor Count
d7699f87 922 */
b3821cc5 923 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 924
3bf61c55 925 /*
d7699f87
GFT		 926 * Setup Unicast Filter
927 */
e523cd89 928 jme_set_unicastaddr(jme->dev);
d7699f87
GFT		 929 jme_set_multi(jme->dev);
930
931 /*
932 * Enable RX Engine
933 */
934 wmb();
dc4185bd 935 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 936 RXCS_QUEUESEL_Q0 |
937 RXCS_ENABLE |
938 RXCS_QST);
dc4185bd
GFT		 939
940 /*
941 * Start clock for RX MAC Processor
942 */
943 jme_mac_rxclk_on(jme);
d7699f87
GFT		 944}
945
cd0ff491 946static inline void
3bf61c55 947jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 948{
949 /*
3bf61c55 950 * Start RX Engine
4330c2f2 951 */
79ce639c 952 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 953 RXCS_QUEUESEL_Q0 |
954 RXCS_ENABLE |
955 RXCS_QST);
956}
957
cd0ff491 958static inline void
3bf61c55 959jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 960{
961 int i;
cd0ff491 962 u32 val;
d7699f87
GFT		 963
964 /*
965 * Disable RX Engine
966 */
29bdd921 967 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 968 wmb();
d7699f87
GFT		 969
970 val = jread32(jme, JME_RXCS);
cd0ff491 971 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 972 mdelay(1);
d7699f87 973 val = jread32(jme, JME_RXCS);
cd0ff491 974 rmb();
d7699f87
GFT		 975 }
976
cd0ff491 977 if (!i)
937ef75a 978 pr_err("Disable RX engine timeout\n");
d7699f87 979
dc4185bd
GFT		 980 /*
981 * Stop clock for RX MAC Processor
982 */
983 jme_mac_rxclk_off(jme);
d7699f87
GFT		 984}
985
93f698ca
GFT		 986static u16
987jme_udpsum(struct sk_buff *skb)
988{
989 u16 csum = 0xFFFFu;
65ff9ddf
GFT		 990#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
991 struct iphdr *iph;
992 int iphlen;
993 struct udphdr *udph;
994#endif
93f698ca
GFT		 995
996 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
997 return csum;
998 if (skb->protocol != htons(ETH_P_IP))
999 return csum;
65ff9ddf
GFT		 1000#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1001 iph = (struct iphdr *)skb_pull(skb, ETH_HLEN);
1002 iphlen = (iph->ihl << 2);
1003 if ((iph->protocol != IPPROTO_UDP) ||
1004 (skb->len < (iphlen + sizeof(struct udphdr)))) {
1005 skb_push(skb, ETH_HLEN);
1006 return csum;
1007 }
1008 udph = (struct udphdr *)skb_pull(skb, iphlen);
1009 csum = udph->check;
1010 skb_push(skb, iphlen);
1011 skb_push(skb, ETH_HLEN);
1012#else
93f698ca
GFT		 1013 skb_set_network_header(skb, ETH_HLEN);
1014 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
1015 (skb->len < (ETH_HLEN +
1016 (ip_hdr(skb)->ihl << 2) +
1017 sizeof(struct udphdr)))) {
1018 skb_reset_network_header(skb);
1019 return csum;
1020 }
1021 skb_set_transport_header(skb,
1022 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
1023 csum = udp_hdr(skb)->check;
1024 skb_reset_transport_header(skb);
1025 skb_reset_network_header(skb);
65ff9ddf 1026#endif
93f698ca
GFT		 1027
1028 return csum;
1029}
1030
192570e0 1031static int
93f698ca 1032jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
192570e0 1033{
cd0ff491 1034 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 1035 return false;
1036
0ede469c
GFT		 1037 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1038 == RXWBFLAG_TCPON)) {
1039 if (flags & RXWBFLAG_IPV4)
7ca9ebee 1040 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
0ede469c 1041 return false;
192570e0
GFT		 1042 }
1043
0ede469c 1044 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
93f698ca 1045 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
0ede469c 1046 if (flags & RXWBFLAG_IPV4)
937ef75a 1047 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
0ede469c 1048 return false;
192570e0
GFT		 1049 }
1050
0ede469c
GFT		 1051 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1052 == RXWBFLAG_IPV4)) {
937ef75a 1053 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
0ede469c 1054 return false;
192570e0
GFT		 1055 }
1056
1057 return true;
1058}
1059
3bf61c55 1060static void
42b1055e 1061jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 1062{
d7699f87 1063 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1064 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 1065 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 1066 struct sk_buff *skb;
3bf61c55 1067 int framesize;
d7699f87 1068
3bf61c55
GFT		 1069 rxdesc += idx;
1070 rxbi += idx;
d7699f87 1071
3bf61c55
GFT		 1072 skb = rxbi->skb;
1073 pci_dma_sync_single_for_cpu(jme->pdev,
1074 rxbi->mapping,
1075 rxbi->len,
1076 PCI_DMA_FROMDEVICE);
1077
cd0ff491 1078 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 1079 pci_dma_sync_single_for_device(jme->pdev,
1080 rxbi->mapping,
1081 rxbi->len,
1082 PCI_DMA_FROMDEVICE);
1083
1084 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1085 } else {
3bf61c55
GFT		 1086 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1087 - RX_PREPAD_SIZE;
1088
1089 skb_reserve(skb, RX_PREPAD_SIZE);
1090 skb_put(skb, framesize);
1091 skb->protocol = eth_type_trans(skb, jme->dev);
1092
93f698ca 1093 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
8c198884 1094 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1095 else
614c0bfd 1096#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
29bdd921 1097 skb->ip_summed = CHECKSUM_NONE;
08f5fcfa
ED		 1098#else
1099 skb_checksum_none_assert(skb);
1100#endif
8c198884 1101
5141719b 1102#ifndef __UNIFY_VLAN_RX_PATH__
3b70a6fa 1103 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 1104 if (jme->vlgrp) {
cdcdc9eb 1105 jme->jme_vlan_rx(skb, jme->vlgrp,
3b70a6fa 1106 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 1107 NET_STAT(jme).rx_bytes += 4;
7ca9ebee 1108 } else {
7ca9ebee 1109 dev_kfree_skb(skb);
b3821cc5 1110 }
cd0ff491 1111 } else {
cdcdc9eb 1112 jme->jme_rx(skb);
b3821cc5 1113 }
5141719b
JP		 1114#else
1115 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1116 u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1117
1118 __vlan_hwaccel_put_tag(skb, vid);
1119 NET_STAT(jme).rx_bytes += 4;
1120 }
1121 jme->jme_rx(skb);
1122#endif
3bf61c55 1123
3b70a6fa
GFT		 1124 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1125 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 1126 ++(NET_STAT(jme).multicast);
1127
3bf61c55
GFT		 1128 NET_STAT(jme).rx_bytes += framesize;
1129 ++(NET_STAT(jme).rx_packets);
1130 }
1131
1132 jme_set_clean_rxdesc(jme, idx);
1133
1134}
1135
1136static int
1137jme_process_receive(struct jme_adapter *jme, int limit)
1138{
1139 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1140 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1141 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1142
cd0ff491 1143 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 1144 goto out_inc;
1145
cd0ff491 1146 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 1147 goto out_inc;
1148
cd0ff491 1149 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 1150 goto out_inc;
1151
cdcdc9eb 1152 i = atomic_read(&rxring->next_to_clean);
0ede469c 1153 while (limit > 0) {
3bf61c55
GFT		 1154 rxdesc = rxring->desc;
1155 rxdesc += i;
1156
3b70a6fa 1157 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 1158 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1159 goto out;
0ede469c 1160 --limit;
d7699f87 1161
9134abda 1162 rmb();
4330c2f2
GFT		 1163 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1164
cd0ff491 1165 if (unlikely(desccnt > 1 ||
192570e0 1166 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1167
cd0ff491 1168 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1169 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1170 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1171 ++(NET_STAT(jme).rx_fifo_errors);
1172 else
1173 ++(NET_STAT(jme).rx_errors);
4330c2f2 1174
cd0ff491 1175 if (desccnt > 1)
3bf61c55 1176 limit -= desccnt - 1;
4330c2f2 1177
cd0ff491 1178 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1179 jme_set_clean_rxdesc(jme, j);
b3821cc5 1180 j = (j + 1) & (mask);
4330c2f2 1181 }
3bf61c55 1182
cd0ff491 1183 } else {
42b1055e 1184 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1185 }
4330c2f2 1186
b3821cc5 1187 i = (i + desccnt) & (mask);
3bf61c55 1188 }
4330c2f2 1189
3bf61c55 1190out:
cdcdc9eb 1191 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1192
192570e0
GFT		 1193out_inc:
1194 atomic_inc(&jme->rx_cleaning);
1195
3bf61c55 1196 return limit > 0 ? limit : 0;
4330c2f2 1197
3bf61c55 1198}
d7699f87 1199
79ce639c
GFT		 1200static void
1201jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1202{
cd0ff491 1203 if (likely(atmp == dpi->cur)) {
192570e0 1204 dpi->cnt = 0;
79ce639c 1205 return;
192570e0 1206 }
79ce639c 1207
cd0ff491 1208 if (dpi->attempt == atmp) {
79ce639c 1209 ++(dpi->cnt);
cd0ff491 1210 } else {
79ce639c
GFT		 1211 dpi->attempt = atmp;
1212 dpi->cnt = 0;
1213 }
1214
1215}
1216
1217static void
1218jme_dynamic_pcc(struct jme_adapter *jme)
1219{
1220 register struct dynpcc_info *dpi = &(jme->dpi);
1221
cd0ff491 1222 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1223 jme_attempt_pcc(dpi, PCC_P3);
7ca9ebee
GFT		 1224 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1225 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT		 1226 jme_attempt_pcc(dpi, PCC_P2);
1227 else
1228 jme_attempt_pcc(dpi, PCC_P1);
1229
cd0ff491
GFT		 1230 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1231 if (dpi->attempt < dpi->cur)
1232 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1233 jme_set_rx_pcc(jme, dpi->attempt);
1234 dpi->cur = dpi->attempt;
1235 dpi->cnt = 0;
1236 }
1237}
1238
1239static void
1240jme_start_pcc_timer(struct jme_adapter *jme)
1241{
1242 struct dynpcc_info *dpi = &(jme->dpi);
1243 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1244 dpi->last_pkts = NET_STAT(jme).rx_packets;
1245 dpi->intr_cnt = 0;
1246 jwrite32(jme, JME_TMCSR,
1247 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1248}
1249
cd0ff491 1250static inline void
29bdd921
GFT		 1251jme_stop_pcc_timer(struct jme_adapter *jme)
1252{
1253 jwrite32(jme, JME_TMCSR, 0);
1254}
1255
cd0ff491
GFT		 1256static void
1257jme_shutdown_nic(struct jme_adapter *jme)
1258{
1259 u32 phylink;
1260
1261 phylink = jme_linkstat_from_phy(jme);
1262
1263 if (!(phylink & PHY_LINK_UP)) {
1264 /*
1265 * Disable all interrupt before issue timer
1266 */
1267 jme_stop_irq(jme);
1268 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1269 }
1270}
1271
79ce639c
GFT		 1272static void
1273jme_pcc_tasklet(unsigned long arg)
1274{
cd0ff491 1275 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1276 struct net_device *netdev = jme->dev;
1277
cd0ff491
GFT		 1278 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1279 jme_shutdown_nic(jme);
1280 return;
1281 }
29bdd921 1282
cd0ff491 1283 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1284 (atomic_read(&jme->link_changing) != 1)
1285 )) {
1286 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1287 return;
1288 }
29bdd921 1289
cd0ff491 1290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1291 jme_dynamic_pcc(jme);
1292
79ce639c
GFT		 1293 jme_start_pcc_timer(jme);
1294}
1295
cd0ff491 1296static inline void
192570e0
GFT		 1297jme_polling_mode(struct jme_adapter *jme)
1298{
1299 jme_set_rx_pcc(jme, PCC_OFF);
1300}
1301
cd0ff491 1302static inline void
192570e0
GFT		 1303jme_interrupt_mode(struct jme_adapter *jme)
1304{
1305 jme_set_rx_pcc(jme, PCC_P1);
1306}
1307
cd0ff491
GFT		 1308static inline int
1309jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1310{
1311 u32 apmc;
1312 apmc = jread32(jme, JME_APMC);
1313 return apmc & JME_APMC_PSEUDO_HP_EN;
1314}
1315
1316static void
1317jme_start_shutdown_timer(struct jme_adapter *jme)
1318{
1319 u32 apmc;
1320
1321 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1322 apmc &= ~JME_APMC_EPIEN_CTRL;
1323 if (!no_extplug) {
1324 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1325 wmb();
1326 }
1327 jwrite32f(jme, JME_APMC, apmc);
1328
1329 jwrite32f(jme, JME_TIMER2, 0);
1330 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1331 jwrite32(jme, JME_TMCSR,
1332 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1333}
1334
1335static void
1336jme_stop_shutdown_timer(struct jme_adapter *jme)
1337{
1338 u32 apmc;
1339
1340 jwrite32f(jme, JME_TMCSR, 0);
1341 jwrite32f(jme, JME_TIMER2, 0);
1342 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1343
1344 apmc = jread32(jme, JME_APMC);
1345 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1346 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1347 wmb();
1348 jwrite32f(jme, JME_APMC, apmc);
1349}
1350
3bf61c55
GFT		 1351static void
1352jme_link_change_tasklet(unsigned long arg)
1353{
cd0ff491 1354 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1355 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1356 int rc;
1357
cd0ff491
GFT		 1358 while (!atomic_dec_and_test(&jme->link_changing)) {
1359 atomic_inc(&jme->link_changing);
937ef75a 1360 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
58c92f28 1361 while (atomic_read(&jme->link_changing) != 1)
937ef75a 1362 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1363 }
fcf45b4c 1364
cd0ff491 1365 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1366 goto out;
1367
29bdd921 1368 jme->old_mtu = netdev->mtu;
fcf45b4c 1369 netif_stop_queue(netdev);
cd0ff491
GFT		 1370 if (jme_pseudo_hotplug_enabled(jme))
1371 jme_stop_shutdown_timer(jme);
1372
1373 jme_stop_pcc_timer(jme);
1374 tasklet_disable(&jme->txclean_task);
1375 tasklet_disable(&jme->rxclean_task);
1376 tasklet_disable(&jme->rxempty_task);
1377
1378 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT		 1379 jme_disable_rx_engine(jme);
1380 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1381 jme_reset_mac_processor(jme);
1382 jme_free_rx_resources(jme);
1383 jme_free_tx_resources(jme);
192570e0 1384
cd0ff491 1385 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1386 jme_polling_mode(jme);
cd0ff491
GFT		 1387
1388 netif_carrier_off(netdev);
fcf45b4c
GFT		 1389 }
1390
1391 jme_check_link(netdev, 0);
cd0ff491 1392 if (netif_carrier_ok(netdev)) {
fcf45b4c 1393 rc = jme_setup_rx_resources(jme);
cd0ff491 1394 if (rc) {
937ef75a 1395 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1396 goto out_enable_tasklet;
fcf45b4c
GFT		 1397 }
1398
fcf45b4c 1399 rc = jme_setup_tx_resources(jme);
cd0ff491 1400 if (rc) {
937ef75a 1401 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT		 1402 goto err_out_free_rx_resources;
1403 }
1404
1405 jme_enable_rx_engine(jme);
1406 jme_enable_tx_engine(jme);
1407
1408 netif_start_queue(netdev);
192570e0 1409
cd0ff491 1410 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1411 jme_interrupt_mode(jme);
192570e0 1412
79ce639c 1413 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1414 } else if (jme_pseudo_hotplug_enabled(jme)) {
1415 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1416 }
1417
cd0ff491 1418 goto out_enable_tasklet;
fcf45b4c
GFT		 1419
1420err_out_free_rx_resources:
1421 jme_free_rx_resources(jme);
cd0ff491
GFT		 1422out_enable_tasklet:
1423 tasklet_enable(&jme->txclean_task);
1424 tasklet_hi_enable(&jme->rxclean_task);
1425 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1426out:
1427 atomic_inc(&jme->link_changing);
3bf61c55 1428}
d7699f87 1429
3bf61c55
GFT		 1430static void
1431jme_rx_clean_tasklet(unsigned long arg)
1432{
cd0ff491 1433 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1434 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1435
192570e0
GFT		 1436 jme_process_receive(jme, jme->rx_ring_size);
1437 ++(dpi->intr_cnt);
42b1055e 1438
192570e0 1439}
fcf45b4c 1440
192570e0 1441static int
cdcdc9eb 1442jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1443{
cdcdc9eb 1444 struct jme_adapter *jme = jme_napi_priv(holder);
3b70a6fa 1445 DECLARE_NETDEV
192570e0 1446 int rest;
fcf45b4c 1447
cdcdc9eb 1448 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1449
cd0ff491 1450 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1451 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1452 ++(NET_STAT(jme).rx_dropped);
1453 jme_restart_rx_engine(jme);
1454 }
1455 atomic_inc(&jme->rx_empty);
1456
cd0ff491 1457 if (rest) {
cdcdc9eb 1458 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1459 jme_interrupt_mode(jme);
1460 }
1461
cdcdc9eb
GFT		 1462 JME_NAPI_WEIGHT_SET(budget, rest);
1463 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1464}
1465
1466static void
1467jme_rx_empty_tasklet(unsigned long arg)
1468{
cd0ff491 1469 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1470
cd0ff491 1471 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1472 return;
1473
cd0ff491 1474 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1475 return;
1476
7ca9ebee 1477 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1478
fcf45b4c 1479 jme_rx_clean_tasklet(arg);
cdcdc9eb 1480
cd0ff491 1481 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1482 atomic_dec(&jme->rx_empty);
1483 ++(NET_STAT(jme).rx_dropped);
1484 jme_restart_rx_engine(jme);
1485 }
1486 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1487}
1488
b3821cc5
GFT		 1489static void
1490jme_wake_queue_if_stopped(struct jme_adapter *jme)
1491{
0ede469c 1492 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1493
1494 smp_wmb();
cd0ff491 1495 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1496 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
937ef75a 1497 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1498 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1499 }
1500
1501}
1502
3bf61c55
GFT		 1503static void
1504jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1505{
cd0ff491 1506 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1507 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1508 struct txdesc *txdesc = txring->desc;
3bf61c55 1509 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1510 int i, j, cnt = 0, max, err, mask;
3bf61c55 1511
937ef75a 1512 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT		 1513
1514 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1515 goto out;
1516
cd0ff491 1517 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1518 goto out;
1519
cd0ff491 1520 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1521 goto out;
1522
b3821cc5
GFT		 1523 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1524 mask = jme->tx_ring_mask;
3bf61c55 1525
cd0ff491 1526 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1527
1528 ctxbi = txbi + i;
1529
cd0ff491 1530 if (likely(ctxbi->skb &&
b3821cc5 1531 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1532
cd0ff491 1533 tx_dbg(jme, "txclean: %d+%d@%lu\n",
937ef75a 1534 i, ctxbi->nr_desc, jiffies);
3bf61c55 1535
cd0ff491 1536 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1537
cd0ff491 1538 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1539 ttxbi = txbi + ((i + j) & (mask));
1540 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1541
b3821cc5 1542 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1543 ttxbi->mapping,
1544 ttxbi->len,
1545 PCI_DMA_TODEVICE);
1546
3bf61c55
GFT		 1547 ttxbi->mapping = 0;
1548 ttxbi->len = 0;
1549 }
1550
1551 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1552
1553 cnt += ctxbi->nr_desc;
1554
cd0ff491 1555 if (unlikely(err)) {
8c198884 1556 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1557 } else {
8c198884 1558 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1559 NET_STAT(jme).tx_bytes += ctxbi->len;
1560 }
1561
1562 ctxbi->skb = NULL;
1563 ctxbi->len = 0;
cdcdc9eb 1564 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1565
1566 } else {
3bf61c55
GFT		 1567 break;
1568 }
1569
b3821cc5 1570 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1571
1572 ctxbi->nr_desc = 0;
d7699f87
GFT		 1573 }
1574
937ef75a 1575 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1576 atomic_set(&txring->next_to_clean, i);
79ce639c 1577 atomic_add(cnt, &txring->nr_free);
3bf61c55 1578
b3821cc5
GFT		 1579 jme_wake_queue_if_stopped(jme);
1580
fcf45b4c
GFT		 1581out:
1582 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1583}
1584
79ce639c 1585static void
cd0ff491 1586jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1587{
3bf61c55
GFT		 1588 /*
1589 * Disable interrupt
1590 */
1591 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1592
cd0ff491 1593 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1594 /*
1595 * Link change event is critical
1596 * all other events are ignored
1597 */
1598 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1599 tasklet_schedule(&jme->linkch_task);
29bdd921 1600 goto out_reenable;
fcf45b4c 1601 }
d7699f87 1602
cd0ff491 1603 if (intrstat & INTR_TMINTR) {
47220951 1604 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1605 tasklet_schedule(&jme->pcc_task);
47220951 1606 }
79ce639c 1607
cd0ff491 1608 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1609 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1610 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1611 }
1612
cd0ff491 1613 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1614 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1615 INTR_PCCRX0 |
1616 INTR_RX0EMP)) |
1617 INTR_RX0);
1618 }
d7699f87 1619
cd0ff491
GFT		 1620 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1621 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1622 atomic_inc(&jme->rx_empty);
1623
cd0ff491
GFT		 1624 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1625 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1626 jme_polling_mode(jme);
cdcdc9eb 1627 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1628 }
1629 }
cd0ff491
GFT		 1630 } else {
1631 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1632 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1633 tasklet_hi_schedule(&jme->rxempty_task);
1634 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1635 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1636 }
4330c2f2 1637 }
d7699f87 1638
29bdd921 1639out_reenable:
3bf61c55 1640 /*
fcf45b4c 1641 * Re-enable interrupt
3bf61c55 1642 */
fcf45b4c 1643 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1644}
1645
3b70a6fa
GFT		 1646#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1647static irqreturn_t
1648jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1649#else
79ce639c
GFT		 1650static irqreturn_t
1651jme_intr(int irq, void *dev_id)
3b70a6fa 1652#endif
79ce639c 1653{
cd0ff491
GFT		 1654 struct net_device *netdev = dev_id;
1655 struct jme_adapter *jme = netdev_priv(netdev);
1656 u32 intrstat;
79ce639c
GFT		 1657
1658 intrstat = jread32(jme, JME_IEVE);
1659
1660 /*
1661 * Check if it's really an interrupt for us
1662 */
7ee473a3 1663 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1664 return IRQ_NONE;
79ce639c
GFT		 1665
1666 /*
1667 * Check if the device still exist
1668 */
cd0ff491
GFT		 1669 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1670 return IRQ_NONE;
79ce639c
GFT		 1671
1672 jme_intr_msi(jme, intrstat);
1673
cd0ff491 1674 return IRQ_HANDLED;
d7699f87
GFT		 1675}
1676
3b70a6fa
GFT		 1677#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1678static irqreturn_t
1679jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1680#else
79ce639c
GFT		 1681static irqreturn_t
1682jme_msi(int irq, void *dev_id)
3b70a6fa 1683#endif
79ce639c 1684{
cd0ff491
GFT		 1685 struct net_device *netdev = dev_id;
1686 struct jme_adapter *jme = netdev_priv(netdev);
1687 u32 intrstat;
79ce639c 1688
0ede469c 1689 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1690
1691 jme_intr_msi(jme, intrstat);
1692
cd0ff491 1693 return IRQ_HANDLED;
79ce639c
GFT		 1694}
1695
79ce639c
GFT		 1696static void
1697jme_reset_link(struct jme_adapter *jme)
1698{
1699 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1700}
1701
fcf45b4c
GFT		 1702static void
1703jme_restart_an(struct jme_adapter *jme)
1704{
cd0ff491 1705 u32 bmcr;
fcf45b4c 1706
cd0ff491 1707 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1708 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1709 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1710 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1711 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1712}
1713
1714static int
1715jme_request_irq(struct jme_adapter *jme)
1716{
1717 int rc;
cd0ff491 1718 struct net_device *netdev = jme->dev;
3b70a6fa
GFT		 1719#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1720 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1721 int irq_flags = SA_SHIRQ;
1722#else
cd0ff491
GFT		 1723 irq_handler_t handler = jme_intr;
1724 int irq_flags = IRQF_SHARED;
3b70a6fa 1725#endif
cd0ff491
GFT		 1726
1727 if (!pci_enable_msi(jme->pdev)) {
1728 set_bit(JME_FLAG_MSI, &jme->flags);
1729 handler = jme_msi;
1730 irq_flags = 0;
1731 }
1732
1733 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1734 netdev);
1735 if (rc) {
937ef75a
JP		 1736 netdev_err(netdev,
1737 "Unable to request %s interrupt (return: %d)\n",
1738 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1739 rc);
79ce639c 1740
cd0ff491
GFT		 1741 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1742 pci_disable_msi(jme->pdev);
1743 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1744 }
cd0ff491 1745 } else {
79ce639c
GFT		 1746 netdev->irq = jme->pdev->irq;
1747 }
1748
cd0ff491 1749 return rc;
79ce639c
GFT		 1750}
1751
1752static void
1753jme_free_irq(struct jme_adapter *jme)
1754{
cd0ff491
GFT		 1755 free_irq(jme->pdev->irq, jme->dev);
1756 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1757 pci_disable_msi(jme->pdev);
1758 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1759 jme->dev->irq = jme->pdev->irq;
cd0ff491 1760 }
fcf45b4c
GFT		 1761}
1762
ed457bcc
GFT		 1763static inline void
1764jme_new_phy_on(struct jme_adapter *jme)
1765{
1766 u32 reg;
1767
1768 reg = jread32(jme, JME_PHY_PWR);
1769 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1770 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1771 jwrite32(jme, JME_PHY_PWR, reg);
1772
1773 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1774 reg &= ~PE1_GPREG0_PBG;
1775 reg |= PE1_GPREG0_ENBG;
1776 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1777}
1778
1779static inline void
1780jme_new_phy_off(struct jme_adapter *jme)
1781{
1782 u32 reg;
1783
1784 reg = jread32(jme, JME_PHY_PWR);
1785 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1786 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1787 jwrite32(jme, JME_PHY_PWR, reg);
1788
1789 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1790 reg &= ~PE1_GPREG0_PBG;
1791 reg |= PE1_GPREG0_PDD3COLD;
1792 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1793}
1794
e58b908e
GFT		 1795static inline void
1796jme_phy_on(struct jme_adapter *jme)
1797{
1798 u32 bmcr;
1799
1800 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1801 bmcr &= ~BMCR_PDOWN;
1802 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
ed457bcc
GFT		 1803
1804 if (new_phy_power_ctrl(jme->chip_main_rev))
1805 jme_new_phy_on(jme);
1806}
1807
1808static inline void
1809jme_phy_off(struct jme_adapter *jme)
1810{
1811 u32 bmcr;
1812
1813 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1814 bmcr |= BMCR_PDOWN;
1815 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1816
1817 if (new_phy_power_ctrl(jme->chip_main_rev))
1818 jme_new_phy_off(jme);
e58b908e
GFT		 1819}
1820
3bf61c55
GFT		 1821static int
1822jme_open(struct net_device *netdev)
d7699f87
GFT		 1823{
1824 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1825 int rc;
79ce639c 1826
42b1055e 1827 jme_clear_pm(jme);
cdcdc9eb 1828 JME_NAPI_ENABLE(jme);
d7699f87 1829
0ede469c 1830 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1831 tasklet_enable(&jme->txclean_task);
1832 tasklet_hi_enable(&jme->rxclean_task);
1833 tasklet_hi_enable(&jme->rxempty_task);
1834
79ce639c 1835 rc = jme_request_irq(jme);
cd0ff491 1836 if (rc)
4330c2f2 1837 goto err_out;
79ce639c 1838
d7699f87 1839 jme_start_irq(jme);
42b1055e 1840
ed457bcc
GFT		 1841 jme_phy_on(jme);
1842 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1843 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 1844 else
42b1055e
GFT		 1845 jme_reset_phy_processor(jme);
1846
29bdd921 1847 jme_reset_link(jme);
d7699f87
GFT		 1848
1849 return 0;
1850
d7699f87
GFT		 1851err_out:
1852 netif_stop_queue(netdev);
1853 netif_carrier_off(netdev);
4330c2f2 1854 return rc;
d7699f87
GFT		 1855}
1856
42b1055e
GFT		 1857static void
1858jme_set_100m_half(struct jme_adapter *jme)
1859{
cd0ff491 1860 u32 bmcr, tmp;
42b1055e 1861
a82e368c 1862 jme_phy_on(jme);
42b1055e
GFT		 1863 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1864 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1865 BMCR_SPEED1000 | BMCR_FULLDPLX);
1866 tmp |= BMCR_SPEED100;
1867
1868 if (bmcr != tmp)
1869 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1870
cd0ff491 1871 if (jme->fpgaver)
cdcdc9eb
GFT		 1872 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1873 else
1874 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1875}
1876
47220951
GFT		 1877#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1878static void
1879jme_wait_link(struct jme_adapter *jme)
1880{
cd0ff491 1881 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1882
1883 mdelay(1000);
1884 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1885 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1886 mdelay(10);
1887 phylink = jme_linkstat_from_phy(jme);
1888 }
1889}
1890
a82e368c
GFT		 1891static void
1892jme_powersave_phy(struct jme_adapter *jme)
1893{
1894 if (jme->reg_pmcs) {
1895 jme_set_100m_half(jme);
a82e368c
GFT		 1896 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1897 jme_wait_link(jme);
61891ee4 1898 jme_clear_pm(jme);
a82e368c
GFT		 1899 } else {
1900 jme_phy_off(jme);
1901 }
1902}
1903
3bf61c55
GFT		 1904static int
1905jme_close(struct net_device *netdev)
d7699f87
GFT		 1906{
1907 struct jme_adapter *jme = netdev_priv(netdev);
1908
1909 netif_stop_queue(netdev);
1910 netif_carrier_off(netdev);
1911
1912 jme_stop_irq(jme);
79ce639c 1913 jme_free_irq(jme);
d7699f87 1914
cdcdc9eb 1915 JME_NAPI_DISABLE(jme);
192570e0 1916
0ede469c
GFT		 1917 tasklet_disable(&jme->linkch_task);
1918 tasklet_disable(&jme->txclean_task);
1919 tasklet_disable(&jme->rxclean_task);
1920 tasklet_disable(&jme->rxempty_task);
8c198884 1921
cd0ff491
GFT		 1922 jme_disable_rx_engine(jme);
1923 jme_disable_tx_engine(jme);
8c198884 1924 jme_reset_mac_processor(jme);
d7699f87
GFT		 1925 jme_free_rx_resources(jme);
1926 jme_free_tx_resources(jme);
42b1055e 1927 jme->phylink = 0;
b3821cc5
GFT		 1928 jme_phy_off(jme);
1929
1930 return 0;
1931}
1932
1933static int
1934jme_alloc_txdesc(struct jme_adapter *jme,
1935 struct sk_buff *skb)
1936{
0ede469c 1937 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1938 int idx, nr_alloc, mask = jme->tx_ring_mask;
1939
1940 idx = txring->next_to_use;
1941 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1942
cd0ff491 1943 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 1944 return -1;
1945
1946 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1947
b3821cc5
GFT		 1948 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1949
1950 return idx;
1951}
1952
1953static void
1954jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1955 struct txdesc *txdesc,
b3821cc5
GFT		 1956 struct jme_buffer_info *txbi,
1957 struct page *page,
cd0ff491
GFT		 1958 u32 page_offset,
1959 u32 len,
1960 u8 hidma)
b3821cc5
GFT		 1961{
1962 dma_addr_t dmaaddr;
1963
1964 dmaaddr = pci_map_page(pdev,
1965 page,
1966 page_offset,
1967 len,
1968 PCI_DMA_TODEVICE);
1969
1970 pci_dma_sync_single_for_device(pdev,
1971 dmaaddr,
1972 len,
1973 PCI_DMA_TODEVICE);
1974
1975 txdesc->dw[0] = 0;
1976 txdesc->dw[1] = 0;
1977 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1978 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 1979 txdesc->desc2.datalen = cpu_to_le16(len);
1980 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1981 txdesc->desc2.bufaddrl = cpu_to_le32(
1982 (__u64)dmaaddr & 0xFFFFFFFFUL);
1983
1984 txbi->mapping = dmaaddr;
1985 txbi->len = len;
1986}
1987
1988static void
1989jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1990{
0ede469c 1991 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1992 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1993 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
e0ae0351 1994 u8 hidma = !!(jme->dev->features & NETIF_F_HIGHDMA);
b3821cc5
GFT		 1995 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1996 int mask = jme->tx_ring_mask;
a2f95d81 1997 const struct skb_frag_struct *frag;
cd0ff491 1998 u32 len;
b3821cc5 1999
cd0ff491
GFT		 2000 for (i = 0 ; i < nr_frags ; ++i) {
2001 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 2002 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2003 ctxbi = txbi + ((idx + i + 2) & (mask));
2004
c6324444 2005#ifndef __USE_SKB_FRAG_API__
b3821cc5
GFT		 2006 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
2007 frag->page_offset, frag->size, hidma);
c6324444
IC		 2008#else
2009 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2010 skb_frag_page(frag),
a2f95d81 2011 frag->page_offset, skb_frag_size(frag), hidma);
c6324444 2012#endif
42b1055e 2013 }
b3821cc5 2014
cd0ff491 2015 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 2016 ctxdesc = txdesc + ((idx + 1) & (mask));
2017 ctxbi = txbi + ((idx + 1) & (mask));
2018 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2019 offset_in_page(skb->data), len, hidma);
2020
2021}
2022
2023static int
2024jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2025{
3b70a6fa 2026 if (unlikely(
0ede469c 2027#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 2028 skb_shinfo(skb)->tso_size
2029#else
2030 skb_shinfo(skb)->gso_size
2031#endif
2032 && skb_header_cloned(skb) &&
b3821cc5
GFT		 2033 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2034 dev_kfree_skb(skb);
2035 return -1;
2036 }
2037
2038 return 0;
2039}
2040
2041static int
3b70a6fa 2042jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 2043{
0ede469c 2044#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 2045 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2046#else
2047 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2048#endif
cd0ff491 2049 if (*mss) {
b3821cc5
GFT		 2050 *flags |= TXFLAG_LSEN;
2051
cd0ff491 2052 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 2053 struct iphdr *iph = ip_hdr(skb);
2054
2055 iph->check = 0;
cd0ff491 2056 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 2057 iph->daddr, 0,
2058 IPPROTO_TCP,
2059 0);
cd0ff491 2060 } else {
b3821cc5
GFT		 2061 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2062
cd0ff491 2063 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 2064 &ip6h->daddr, 0,
2065 IPPROTO_TCP,
2066 0);
2067 }
2068
2069 return 0;
2070 }
2071
2072 return 1;
2073}
2074
2075static void
cd0ff491 2076jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 2077{
3b70a6fa
GFT		 2078#ifdef CHECKSUM_PARTIAL
2079 if (skb->ip_summed == CHECKSUM_PARTIAL)
2080#else
2081 if (skb->ip_summed == CHECKSUM_HW)
2082#endif
2083 {
cd0ff491 2084 u8 ip_proto;
b3821cc5 2085
3b70a6fa
GFT		 2086#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2087 if (skb->protocol == htons(ETH_P_IP))
2088 ip_proto = ip_hdr(skb)->protocol;
2089 else if (skb->protocol == htons(ETH_P_IPV6))
2090 ip_proto = ipv6_hdr(skb)->nexthdr;
2091 else
2092 ip_proto = 0;
2093#else
b3821cc5 2094 switch (skb->protocol) {
cd0ff491 2095 case htons(ETH_P_IP):
b3821cc5
GFT		 2096 ip_proto = ip_hdr(skb)->protocol;
2097 break;
cd0ff491 2098 case htons(ETH_P_IPV6):
b3821cc5
GFT		 2099 ip_proto = ipv6_hdr(skb)->nexthdr;
2100 break;
2101 default:
2102 ip_proto = 0;
2103 break;
2104 }
3b70a6fa 2105#endif
b3821cc5 2106
cd0ff491 2107 switch (ip_proto) {
b3821cc5
GFT		 2108 case IPPROTO_TCP:
2109 *flags |= TXFLAG_TCPCS;
2110 break;
2111 case IPPROTO_UDP:
2112 *flags |= TXFLAG_UDPCS;
2113 break;
2114 default:
937ef75a 2115 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT		 2116 break;
2117 }
2118 }
2119}
2120
cd0ff491 2121static inline void
3b70a6fa 2122jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2123{
cd0ff491 2124 if (vlan_tx_tag_present(skb)) {
b3821cc5 2125 *flags |= TXFLAG_TAGON;
3b70a6fa 2126 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2127 }
b3821cc5
GFT		 2128}
2129
2130static int
3b70a6fa 2131jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2132{
0ede469c 2133 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2134 struct txdesc *txdesc;
b3821cc5 2135 struct jme_buffer_info *txbi;
cd0ff491 2136 u8 flags;
b3821cc5 2137
cd0ff491 2138 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 2139 txbi = txring->bufinf + idx;
2140
2141 txdesc->dw[0] = 0;
2142 txdesc->dw[1] = 0;
2143 txdesc->dw[2] = 0;
2144 txdesc->dw[3] = 0;
2145 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2146 /*
2147 * Set OWN bit at final.
2148 * When kernel transmit faster than NIC.
2149 * And NIC trying to send this descriptor before we tell
2150 * it to start sending this TX queue.
2151 * Other fields are already filled correctly.
2152 */
2153 wmb();
2154 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 2155 /*
2156 * Set checksum flags while not tso
2157 */
2158 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2159 jme_tx_csum(jme, skb, &flags);
b3821cc5 2160 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
3b70a6fa 2161 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 2162 txdesc->desc1.flags = flags;
2163 /*
2164 * Set tx buffer info after telling NIC to send
2165 * For better tx_clean timing
2166 */
2167 wmb();
2168 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2169 txbi->skb = skb;
2170 txbi->len = skb->len;
cd0ff491
GFT		 2171 txbi->start_xmit = jiffies;
2172 if (!txbi->start_xmit)
8d27293f 2173 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 2174
2175 return 0;
2176}
2177
b3821cc5
GFT		 2178static void
2179jme_stop_queue_if_full(struct jme_adapter *jme)
2180{
0ede469c 2181 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 2182 struct jme_buffer_info *txbi = txring->bufinf;
2183 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2184
cd0ff491 2185 txbi += idx;
b3821cc5
GFT		 2186
2187 smp_wmb();
cd0ff491 2188 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2189 netif_stop_queue(jme->dev);
937ef75a 2190 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2191 smp_wmb();
cd0ff491
GFT		 2192 if (atomic_read(&txring->nr_free)
2193 >= (jme->tx_wake_threshold)) {
b3821cc5 2194 netif_wake_queue(jme->dev);
937ef75a 2195 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT		 2196 }
2197 }
2198
cd0ff491 2199 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 2200 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2201 txbi->skb)) {
2202 netif_stop_queue(jme->dev);
e3b96dc9
GFT		 2203 netif_info(jme, tx_queued, jme->dev,
2204 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2205 }
b3821cc5
GFT		 2206}
2207
3bf61c55
GFT		 2208/*
2209 * This function is already protected by netif_tx_lock()
2210 */
cd0ff491 2211
7ca9ebee 2212#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
3bf61c55 2213static int
7ca9ebee
GFT		 2214#else
2215static netdev_tx_t
2216#endif
3bf61c55 2217jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2218{
cd0ff491 2219 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2220 int idx;
d7699f87 2221
cd0ff491 2222 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 2223 ++(NET_STAT(jme).tx_dropped);
2224 return NETDEV_TX_OK;
2225 }
2226
2227 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2228
cd0ff491 2229 if (unlikely(idx < 0)) {
b3821cc5 2230 netif_stop_queue(netdev);
937ef75a
JP		 2231 netif_err(jme, tx_err, jme->dev,
2232 "BUG! Tx ring full when queue awake!\n");
d7699f87 2233
cd0ff491 2234 return NETDEV_TX_BUSY;
b3821cc5
GFT		 2235 }
2236
3b70a6fa 2237 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2238
4330c2f2
GFT		 2239 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2240 TXCS_SELECT_QUEUE0 |
2241 TXCS_QUEUE0S |
2242 TXCS_ENABLE);
0ede469c 2243#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
d7699f87 2244 netdev->trans_start = jiffies;
0ede469c 2245#endif
d7699f87 2246
937ef75a
JP		 2247 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2248 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT		 2249 jme_stop_queue_if_full(jme);
2250
cd0ff491 2251 return NETDEV_TX_OK;
d7699f87
GFT		 2252}
2253
e523cd89
GFT		 2254static void
2255jme_set_unicastaddr(struct net_device *netdev)
2256{
2257 struct jme_adapter *jme = netdev_priv(netdev);
2258 u32 val;
2259
2260 val = (netdev->dev_addr[3] & 0xff) << 24 |
2261 (netdev->dev_addr[2] & 0xff) << 16 |
2262 (netdev->dev_addr[1] & 0xff) << 8 |
2263 (netdev->dev_addr[0] & 0xff);
2264 jwrite32(jme, JME_RXUMA_LO, val);
2265 val = (netdev->dev_addr[5] & 0xff) << 8 |
2266 (netdev->dev_addr[4] & 0xff);
2267 jwrite32(jme, JME_RXUMA_HI, val);
2268}
2269
3bf61c55
GFT		 2270static int
2271jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2272{
cd0ff491 2273 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2274 struct sockaddr *addr = p;
d7699f87 2275
cd0ff491 2276 if (netif_running(netdev))
d7699f87
GFT		 2277 return -EBUSY;
2278
cd0ff491 2279 spin_lock_bh(&jme->macaddr_lock);
d7699f87 2280 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
e523cd89 2281 jme_set_unicastaddr(netdev);
cd0ff491 2282 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 2283
2284 return 0;
2285}
2286
3bf61c55
GFT		 2287static void
2288jme_set_multi(struct net_device *netdev)
d7699f87 2289{
3bf61c55 2290 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2291 u32 mc_hash[2] = {};
7ca9ebee 2292#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
d7699f87 2293 int i;
7ca9ebee 2294#endif
d7699f87 2295
cd0ff491 2296 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2297
2298 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2299
cd0ff491 2300 if (netdev->flags & IFF_PROMISC) {
8c198884 2301 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2302 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2303 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2304 } else if (netdev->flags & IFF_MULTICAST) {
8e14c278 2305#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
3bf61c55 2306 struct dev_mc_list *mclist;
8e14c278
JP		 2307#else
2308 struct netdev_hw_addr *ha;
2309#endif
3bf61c55 2310 int bit_nr;
d7699f87 2311
8c198884 2312 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
7ca9ebee 2313#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
3bf61c55
GFT		 2314 for (i = 0, mclist = netdev->mc_list;
2315 mclist && i < netdev->mc_count;
2316 ++i, mclist = mclist->next) {
8e14c278 2317#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
7ca9ebee 2318 netdev_for_each_mc_addr(mclist, netdev) {
8e14c278
JP		 2319#else
2320 netdev_for_each_mc_addr(ha, netdev) {
7ca9ebee 2321#endif
8e14c278 2322#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
cd0ff491 2323 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
8e14c278
JP		 2324#else
2325 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2326#endif
cd0ff491
GFT		 2327 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2328 }
d7699f87 2329
4330c2f2
GFT		 2330 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2331 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2332 }
2333
d7699f87 2334 wmb();
8c198884
GFT		 2335 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2336
cd0ff491 2337 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2338}
2339
3bf61c55 2340static int
8c198884 2341jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2342{
cd0ff491 2343 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2344
cd0ff491 2345 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2346 return 0;
2347
cd0ff491
GFT		 2348 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2349 ((new_mtu) < IPV6_MIN_MTU))
2350 return -EINVAL;
79ce639c 2351
cd0ff491 2352 if (new_mtu > 4000) {
79ce639c
GFT		 2353 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2354 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2355 jme_restart_rx_engine(jme);
cd0ff491 2356 } else {
79ce639c
GFT		 2357 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2358 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2359 jme_restart_rx_engine(jme);
2360 }
2361
767e5b98 2362#ifndef __USE_NDO_FIX_FEATURES__
cd0ff491 2363 if (new_mtu > 1900) {
1a0b42f4
MM		 2364 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2365 NETIF_F_TSO | NETIF_F_TSO6);
cd0ff491
GFT		 2366 } else {
2367 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
1a0b42f4 2368 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491 2369 if (test_bit(JME_FLAG_TSO, &jme->flags))
1a0b42f4 2370 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c 2371 }
767e5b98 2372#endif
79ce639c 2373
cd0ff491 2374 netdev->mtu = new_mtu;
767e5b98
MM		 2375#ifdef __USE_NDO_FIX_FEATURES__
2376 netdev_update_features(netdev);
2377#endif
cd0ff491 2378 jme_reset_link(jme);
79ce639c
GFT		 2379
2380 return 0;
d7699f87
GFT		 2381}
2382
8c198884
GFT		 2383static void
2384jme_tx_timeout(struct net_device *netdev)
2385{
cd0ff491 2386 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2387
cdcdc9eb
GFT		 2388 jme->phylink = 0;
2389 jme_reset_phy_processor(jme);
cd0ff491 2390 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2391 jme_set_settings(netdev, &jme->old_ecmd);
2392
8c198884 2393 /*
cdcdc9eb 2394 * Force to Reset the link again
8c198884 2395 */
29bdd921 2396 jme_reset_link(jme);
8c198884
GFT		 2397}
2398
1e5ebebc
GFT		 2399static inline void jme_pause_rx(struct jme_adapter *jme)
2400{
2401 atomic_dec(&jme->link_changing);
2402
2403 jme_set_rx_pcc(jme, PCC_OFF);
2404 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2405 JME_NAPI_DISABLE(jme);
2406 } else {
2407 tasklet_disable(&jme->rxclean_task);
2408 tasklet_disable(&jme->rxempty_task);
2409 }
2410}
2411
2412static inline void jme_resume_rx(struct jme_adapter *jme)
2413{
2414 struct dynpcc_info *dpi = &(jme->dpi);
2415
2416 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2417 JME_NAPI_ENABLE(jme);
2418 } else {
2419 tasklet_hi_enable(&jme->rxclean_task);
2420 tasklet_hi_enable(&jme->rxempty_task);
2421 }
2422 dpi->cur = PCC_P1;
2423 dpi->attempt = PCC_P1;
2424 dpi->cnt = 0;
2425 jme_set_rx_pcc(jme, PCC_P1);
2426
2427 atomic_inc(&jme->link_changing);
2428}
2429
5141719b 2430#ifndef __UNIFY_VLAN_RX_PATH__
42b1055e
GFT		 2431static void
2432jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2433{
2434 struct jme_adapter *jme = netdev_priv(netdev);
2435
1e5ebebc 2436 jme_pause_rx(jme);
42b1055e 2437 jme->vlgrp = grp;
1e5ebebc 2438 jme_resume_rx(jme);
42b1055e 2439}
5141719b 2440#endif
42b1055e 2441
7ca9ebee
GFT		 2442#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2443static void
2444jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2445{
2446 struct jme_adapter *jme = netdev_priv(netdev);
2447
7ca9ebee 2448 if(jme->vlgrp) {
1e5ebebc 2449 jme_pause_rx(jme);
7ca9ebee
GFT		 2450#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2451 jme->vlgrp->vlan_devices[vid] = NULL;
2452#else
2453 vlan_group_set_device(jme->vlgrp, vid, NULL);
2454#endif
1e5ebebc 2455 jme_resume_rx(jme);
7ca9ebee 2456 }
7ca9ebee
GFT		 2457}
2458#endif
2459
3bf61c55
GFT		 2460static void
2461jme_get_drvinfo(struct net_device *netdev,
2462 struct ethtool_drvinfo *info)
d7699f87 2463{
cd0ff491 2464 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2465
c0e78193
RJ		 2466 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2467 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2468 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
d7699f87
GFT		 2469}
2470
8c198884
GFT		 2471static int
2472jme_get_regs_len(struct net_device *netdev)
2473{
cd0ff491 2474 return JME_REG_LEN;
8c198884
GFT		 2475}
2476
2477static void
cd0ff491 2478mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2479{
2480 int i;
2481
cd0ff491 2482 for (i = 0 ; i < len ; i += 4)
79ce639c 2483 p[i >> 2] = jread32(jme, reg + i);
186fc259 2484}
8c198884 2485
186fc259 2486static void
cd0ff491 2487mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2488{
2489 int i;
cd0ff491 2490 u16 *p16 = (u16 *)p;
186fc259 2491
cd0ff491 2492 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2493 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2494}
2495
2496static void
2497jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2498{
cd0ff491
GFT		 2499 struct jme_adapter *jme = netdev_priv(netdev);
2500 u32 *p32 = (u32 *)p;
8c198884 2501
186fc259 2502 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2503
2504 regs->version = 1;
2505 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2506
2507 p32 += 0x100 >> 2;
2508 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2509
2510 p32 += 0x100 >> 2;
2511 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2512
2513 p32 += 0x100 >> 2;
2514 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2515
186fc259
GFT		 2516 p32 += 0x100 >> 2;
2517 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2518}
2519
2520static int
2521jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2522{
2523 struct jme_adapter *jme = netdev_priv(netdev);
2524
8c198884
GFT		 2525 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2526 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2527
cd0ff491 2528 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2529 ecmd->use_adaptive_rx_coalesce = false;
2530 ecmd->rx_coalesce_usecs = 0;
2531 ecmd->rx_max_coalesced_frames = 0;
2532 return 0;
2533 }
2534
2535 ecmd->use_adaptive_rx_coalesce = true;
2536
cd0ff491 2537 switch (jme->dpi.cur) {
8c198884
GFT		 2538 case PCC_P1:
2539 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2540 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2541 break;
2542 case PCC_P2:
2543 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2544 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2545 break;
2546 case PCC_P3:
2547 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2548 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2549 break;
2550 default:
2551 break;
2552 }
2553
2554 return 0;
2555}
2556
192570e0
GFT		 2557static int
2558jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2559{
2560 struct jme_adapter *jme = netdev_priv(netdev);
2561 struct dynpcc_info *dpi = &(jme->dpi);
2562
cd0ff491 2563 if (netif_running(netdev))
cdcdc9eb
GFT		 2564 return -EBUSY;
2565
7ca9ebee
GFT		 2566 if (ecmd->use_adaptive_rx_coalesce &&
2567 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2568 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb 2569 jme->jme_rx = netif_rx;
5141719b 2570#ifndef __UNIFY_VLAN_RX_PATH__
cdcdc9eb 2571 jme->jme_vlan_rx = vlan_hwaccel_rx;
5141719b 2572#endif
192570e0
GFT		 2573 dpi->cur = PCC_P1;
2574 dpi->attempt = PCC_P1;
2575 dpi->cnt = 0;
2576 jme_set_rx_pcc(jme, PCC_P1);
2577 jme_interrupt_mode(jme);
7ca9ebee
GFT		 2578 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2579 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2580 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb 2581 jme->jme_rx = netif_receive_skb;
5141719b 2582#ifndef __UNIFY_VLAN_RX_PATH__
cdcdc9eb 2583 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
5141719b 2584#endif
192570e0
GFT		 2585 jme_interrupt_mode(jme);
2586 }
2587
2588 return 0;
2589}
2590
8c198884
GFT		 2591static void
2592jme_get_pauseparam(struct net_device *netdev,
2593 struct ethtool_pauseparam *ecmd)
2594{
2595 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2596 u32 val;
8c198884
GFT		 2597
2598 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2599 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2600
cd0ff491
GFT		 2601 spin_lock_bh(&jme->phy_lock);
2602 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2603 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2604
2605 ecmd->autoneg =
2606 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2607}
2608
2609static int
2610jme_set_pauseparam(struct net_device *netdev,
2611 struct ethtool_pauseparam *ecmd)
2612{
2613 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2614 u32 val;
8c198884 2615
cd0ff491 2616 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2617 (ecmd->tx_pause != 0)) {
2618
cd0ff491 2619 if (ecmd->tx_pause)
8c198884
GFT		 2620 jme->reg_txpfc |= TXPFC_PF_EN;
2621 else
2622 jme->reg_txpfc &= ~TXPFC_PF_EN;
2623
2624 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2625 }
2626
cd0ff491
GFT		 2627 spin_lock_bh(&jme->rxmcs_lock);
2628 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2629 (ecmd->rx_pause != 0)) {
2630
cd0ff491 2631 if (ecmd->rx_pause)
8c198884
GFT		 2632 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2633 else
2634 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2635
2636 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2637 }
cd0ff491 2638 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2639
cd0ff491
GFT		 2640 spin_lock_bh(&jme->phy_lock);
2641 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2642 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2643 (ecmd->autoneg != 0)) {
2644
cd0ff491 2645 if (ecmd->autoneg)
8c198884
GFT		 2646 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2647 else
2648 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2649
b3821cc5
GFT		 2650 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2651 MII_ADVERTISE, val);
8c198884 2652 }
cd0ff491 2653 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2654
2655 return 0;
2656}
2657
29bdd921
GFT		 2658static void
2659jme_get_wol(struct net_device *netdev,
2660 struct ethtool_wolinfo *wol)
2661{
2662 struct jme_adapter *jme = netdev_priv(netdev);
2663
2664 wol->supported = WAKE_MAGIC | WAKE_PHY;
2665
2666 wol->wolopts = 0;
2667
cd0ff491 2668 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2669 wol->wolopts |= WAKE_PHY;
2670
cd0ff491 2671 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2672 wol->wolopts |= WAKE_MAGIC;
2673
2674}
2675
2676static int
2677jme_set_wol(struct net_device *netdev,
2678 struct ethtool_wolinfo *wol)
2679{
2680 struct jme_adapter *jme = netdev_priv(netdev);
2681
cd0ff491 2682 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2683 WAKE_UCAST |
2684 WAKE_MCAST |
2685 WAKE_BCAST |
2686 WAKE_ARP))
2687 return -EOPNOTSUPP;
2688
2689 jme->reg_pmcs = 0;
2690
cd0ff491 2691 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2692 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2693
cd0ff491 2694 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2695 jme->reg_pmcs |= PMCS_MFEN;
2696
cd0ff491 2697 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3d12cc1b
GFT		 2698#ifndef JME_NEW_PM_API
2699 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2700#endif
7370b85a 2701#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3d12cc1b 2702 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
7370b85a 2703#endif
e3b96dc9 2704
29bdd921
GFT		 2705 return 0;
2706}
b3821cc5 2707
3bf61c55
GFT		 2708static int
2709jme_get_settings(struct net_device *netdev,
2710 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2711{
2712 struct jme_adapter *jme = netdev_priv(netdev);
2713 int rc;
8c198884 2714
cd0ff491 2715 spin_lock_bh(&jme->phy_lock);
d7699f87 2716 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2717 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2718 return rc;
2719}
2720
3bf61c55
GFT		 2721static int
2722jme_set_settings(struct net_device *netdev,
2723 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2724{
2725 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2726 int rc, fdc = 0;
fcf45b4c 2727
8588b84b
DD		 2728 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2729 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2730 return -EINVAL;
2731
e6b41b51
GFT		 2732 /*
2733 * Check If user changed duplex only while force_media.
2734 * Hardware would not generate link change interrupt.
2735 */
cd0ff491 2736 if (jme->mii_if.force_media &&
79ce639c
GFT		 2737 ecmd->autoneg != AUTONEG_ENABLE &&
2738 (jme->mii_if.full_duplex != ecmd->duplex))
2739 fdc = 1;
2740
cd0ff491 2741 spin_lock_bh(&jme->phy_lock);
d7699f87 2742 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2743 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2744
cd0ff491 2745 if (!rc) {
e6b41b51
GFT		 2746 if (fdc)
2747 jme_reset_link(jme);
29bdd921 2748 jme->old_ecmd = *ecmd;
aa1e7189
GFT		 2749 set_bit(JME_FLAG_SSET, &jme->flags);
2750 }
2751
2752 return rc;
2753}
2754
2755static int
2756jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2757{
2758 int rc;
2759 struct jme_adapter *jme = netdev_priv(netdev);
2760 struct mii_ioctl_data *mii_data = if_mii(rq);
2761 unsigned int duplex_chg;
2762
2763 if (cmd == SIOCSMIIREG) {
2764 u16 val = mii_data->val_in;
2765 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2766 (val & BMCR_SPEED1000))
2767 return -EINVAL;
2768 }
2769
2770 spin_lock_bh(&jme->phy_lock);
2771 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2772 spin_unlock_bh(&jme->phy_lock);
2773
2774 if (!rc && (cmd == SIOCSMIIREG)) {
2775 if (duplex_chg)
2776 jme_reset_link(jme);
2777 jme_get_settings(netdev, &jme->old_ecmd);
2778 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2779 }
2780
d7699f87
GFT		 2781 return rc;
2782}
2783
cd0ff491 2784static u32
3bf61c55
GFT		 2785jme_get_link(struct net_device *netdev)
2786{
d7699f87
GFT		 2787 struct jme_adapter *jme = netdev_priv(netdev);
2788 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2789}
2790
8c198884 2791static u32
cd0ff491
GFT		 2792jme_get_msglevel(struct net_device *netdev)
2793{
2794 struct jme_adapter *jme = netdev_priv(netdev);
2795 return jme->msg_enable;
2796}
2797
2798static void
2799jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2800{
cd0ff491
GFT		 2801 struct jme_adapter *jme = netdev_priv(netdev);
2802 jme->msg_enable = value;
2803}
8c198884 2804
767e5b98 2805#ifndef __USE_NDO_FIX_FEATURES__
cd0ff491
GFT		 2806static u32
2807jme_get_rx_csum(struct net_device *netdev)
2808{
2809 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2810 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2811}
2812
2813static int
2814jme_set_rx_csum(struct net_device *netdev, u32 on)
2815{
cd0ff491 2816 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2817
cd0ff491
GFT		 2818 spin_lock_bh(&jme->rxmcs_lock);
2819 if (on)
8c198884
GFT		 2820 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2821 else
2822 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2823 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2824 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2825
2826 return 0;
2827}
2828
2829static int
2830jme_set_tx_csum(struct net_device *netdev, u32 on)
2831{
cd0ff491 2832 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2833
cd0ff491
GFT		 2834 if (on) {
2835 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2836 if (netdev->mtu <= 1900)
1a0b42f4
MM		 2837 netdev->features |=
2838 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491
GFT		 2839 } else {
2840 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
1a0b42f4
MM		 2841 netdev->features &=
2842 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
b3821cc5 2843 }
8c198884
GFT		 2844
2845 return 0;
2846}
2847
b3821cc5
GFT		 2848static int
2849jme_set_tso(struct net_device *netdev, u32 on)
2850{
cd0ff491 2851 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2852
cd0ff491
GFT		 2853 if (on) {
2854 set_bit(JME_FLAG_TSO, &jme->flags);
2855 if (netdev->mtu <= 1900)
1a0b42f4 2856 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT		 2857 } else {
2858 clear_bit(JME_FLAG_TSO, &jme->flags);
1a0b42f4 2859 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT		 2860 }
2861
cd0ff491 2862 return 0;
b3821cc5 2863}
767e5b98 2864#else
e0ae0351 2865#ifndef __NEW_FIX_FEATURES_TYPE__
767e5b98
MM		 2866static u32
2867jme_fix_features(struct net_device *netdev, u32 features)
e0ae0351
MM		 2868#else
2869static netdev_features_t
2870jme_fix_features(struct net_device *netdev, netdev_features_t features)
2871#endif
767e5b98
MM		 2872{
2873 if (netdev->mtu > 1900)
2874 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2875 return features;
2876}
2877
2878static int
e0ae0351 2879#ifndef __NEW_FIX_FEATURES_TYPE__
767e5b98 2880jme_set_features(struct net_device *netdev, u32 features)
e0ae0351
MM		 2881#else
2882jme_set_features(struct net_device *netdev, netdev_features_t features)
2883#endif
767e5b98
MM		 2884{
2885 struct jme_adapter *jme = netdev_priv(netdev);
2886
2887 spin_lock_bh(&jme->rxmcs_lock);
2888 if (features & NETIF_F_RXCSUM)
2889 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2890 else
2891 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2892 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2893 spin_unlock_bh(&jme->rxmcs_lock);
2894
2895 return 0;
2896}
2897#endif
b3821cc5 2898
8c198884
GFT		 2899static int
2900jme_nway_reset(struct net_device *netdev)
2901{
cd0ff491 2902 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2903 jme_restart_an(jme);
2904 return 0;
2905}
2906
cd0ff491 2907static u8
186fc259
GFT		 2908jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2909{
cd0ff491 2910 u32 val;
186fc259
GFT		 2911 int to;
2912
2913 val = jread32(jme, JME_SMBCSR);
2914 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2915 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2916 msleep(1);
2917 val = jread32(jme, JME_SMBCSR);
2918 }
cd0ff491 2919 if (!to) {
937ef75a 2920 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2921 return 0xFF;
2922 }
2923
2924 jwrite32(jme, JME_SMBINTF,
2925 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2926 SMBINTF_HWRWN_READ |
2927 SMBINTF_HWCMD);
2928
2929 val = jread32(jme, JME_SMBINTF);
2930 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2931 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2932 msleep(1);
2933 val = jread32(jme, JME_SMBINTF);
2934 }
cd0ff491 2935 if (!to) {
937ef75a 2936 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2937 return 0xFF;
2938 }
2939
2940 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2941}
2942
2943static void
cd0ff491 2944jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2945{
cd0ff491 2946 u32 val;
186fc259
GFT		 2947 int to;
2948
2949 val = jread32(jme, JME_SMBCSR);
2950 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2951 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2952 msleep(1);
2953 val = jread32(jme, JME_SMBCSR);
2954 }
cd0ff491 2955 if (!to) {
937ef75a 2956 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2957 return;
2958 }
2959
2960 jwrite32(jme, JME_SMBINTF,
2961 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2962 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2963 SMBINTF_HWRWN_WRITE |
2964 SMBINTF_HWCMD);
2965
2966 val = jread32(jme, JME_SMBINTF);
2967 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2968 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2969 msleep(1);
2970 val = jread32(jme, JME_SMBINTF);
2971 }
cd0ff491 2972 if (!to) {
937ef75a 2973 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2974 return;
2975 }
2976
2977 mdelay(2);
2978}
2979
2980static int
2981jme_get_eeprom_len(struct net_device *netdev)
2982{
cd0ff491
GFT		 2983 struct jme_adapter *jme = netdev_priv(netdev);
2984 u32 val;
186fc259 2985 val = jread32(jme, JME_SMBCSR);
cd0ff491 2986 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 2987}
2988
2989static int
2990jme_get_eeprom(struct net_device *netdev,
2991 struct ethtool_eeprom *eeprom, u8 *data)
2992{
cd0ff491 2993 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2994 int i, offset = eeprom->offset, len = eeprom->len;
2995
2996 /*
8d27293f 2997 * ethtool will check the boundary for us
186fc259
GFT		 2998 */
2999 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 3000 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 3001 data[i] = jme_smb_read(jme, i + offset);
3002
3003 return 0;
3004}
3005
3006static int
3007jme_set_eeprom(struct net_device *netdev,
3008 struct ethtool_eeprom *eeprom, u8 *data)
3009{
cd0ff491 3010 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 3011 int i, offset = eeprom->offset, len = eeprom->len;
3012
3013 if (eeprom->magic != JME_EEPROM_MAGIC)
3014 return -EINVAL;
3015
3016 /*
8d27293f 3017 * ethtool will check the boundary for us
186fc259 3018 */
cd0ff491 3019 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 3020 jme_smb_write(jme, i + offset, data[i]);
3021
3022 return 0;
3023}
3024
3b70a6fa
GFT		 3025#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
3026static struct ethtool_ops jme_ethtool_ops = {
3027#else
d7699f87 3028static const struct ethtool_ops jme_ethtool_ops = {
3b70a6fa 3029#endif
cd0ff491 3030 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 3031 .get_regs_len = jme_get_regs_len,
3032 .get_regs = jme_get_regs,
3033 .get_coalesce = jme_get_coalesce,
192570e0 3034 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 3035 .get_pauseparam = jme_get_pauseparam,
3036 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 3037 .get_wol = jme_get_wol,
3038 .set_wol = jme_set_wol,
d7699f87
GFT		 3039 .get_settings = jme_get_settings,
3040 .set_settings = jme_set_settings,
3041 .get_link = jme_get_link,
cd0ff491
GFT		 3042 .get_msglevel = jme_get_msglevel,
3043 .set_msglevel = jme_set_msglevel,
767e5b98 3044#ifndef __USE_NDO_FIX_FEATURES__
8c198884
GFT		 3045 .get_rx_csum = jme_get_rx_csum,
3046 .set_rx_csum = jme_set_rx_csum,
3047 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT		 3048 .set_tso = jme_set_tso,
3049 .set_sg = ethtool_op_set_sg,
767e5b98 3050#endif
8c198884 3051 .nway_reset = jme_nway_reset,
186fc259
GFT		 3052 .get_eeprom_len = jme_get_eeprom_len,
3053 .get_eeprom = jme_get_eeprom,
3054 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 3055};
3056
3bf61c55
GFT		 3057static int
3058jme_pci_dma64(struct pci_dev *pdev)
d7699f87 3059{
3b70a6fa 3060 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 3061#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3062 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
3063#else
3064 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
3065#endif
3066 )
3067#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3068 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3069#else
cd0ff491 3070 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
0ede469c 3071#endif
3bf61c55
GFT		 3072 return 1;
3073
3b70a6fa 3074 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 3075#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3076 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
3077#else
3078 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
3079#endif
3080 )
3081#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3082 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
3083#else
cd0ff491 3084 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
0ede469c 3085#endif
8c198884
GFT		 3086 return 1;
3087
0ede469c
GFT		 3088#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3089 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
3090 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3091#else
cd0ff491
GFT		 3092 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3093 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
0ede469c 3094#endif
3bf61c55
GFT		 3095 return 0;
3096
3097 return -1;
3098}
3099
cd0ff491 3100static inline void
cdcdc9eb
GFT		 3101jme_phy_init(struct jme_adapter *jme)
3102{
cd0ff491 3103 u16 reg26;
cdcdc9eb
GFT		 3104
3105 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3106 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3107}
3108
cd0ff491 3109static inline void
cdcdc9eb 3110jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 3111{
cd0ff491 3112 u32 chipmode;
cdcdc9eb
GFT		 3113
3114 chipmode = jread32(jme, JME_CHIPMODE);
3115
3116 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 3117 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
98ef18f1
GFT		 3118 jme->chip_main_rev = jme->chiprev & 0xF;
3119 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT		 3120}
3121
3b70a6fa
GFT		 3122#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3123static const struct net_device_ops jme_netdev_ops = {
3124 .ndo_open = jme_open,
3125 .ndo_stop = jme_close,
3126 .ndo_validate_addr = eth_validate_addr,
aa1e7189 3127 .ndo_do_ioctl = jme_ioctl,
3b70a6fa
GFT		 3128 .ndo_start_xmit = jme_start_xmit,
3129 .ndo_set_mac_address = jme_set_macaddr,
1ec30a25 3130#ifndef __USE_NDO_SET_RX_MODE__
3b70a6fa 3131 .ndo_set_multicast_list = jme_set_multi,
1ec30a25
JP		 3132#else
3133 .ndo_set_rx_mode = jme_set_multi,
3134#endif
3b70a6fa
GFT		 3135 .ndo_change_mtu = jme_change_mtu,
3136 .ndo_tx_timeout = jme_tx_timeout,
5141719b 3137#ifndef __UNIFY_VLAN_RX_PATH__
3b70a6fa 3138 .ndo_vlan_rx_register = jme_vlan_rx_register,
5141719b 3139#endif
767e5b98
MM		 3140#ifdef __USE_NDO_FIX_FEATURES__
3141 .ndo_fix_features = jme_fix_features,
3142 .ndo_set_features = jme_set_features,
3143#endif
3b70a6fa
GFT		 3144};
3145#endif
3146
3bf61c55
GFT		 3147static int __devinit
3148jme_init_one(struct pci_dev *pdev,
3149 const struct pci_device_id *ent)
3150{
cdcdc9eb 3151 int rc = 0, using_dac, i;
d7699f87
GFT		 3152 struct net_device *netdev;
3153 struct jme_adapter *jme;
cd0ff491
GFT		 3154 u16 bmcr, bmsr;
3155 u32 apmc;
d7699f87
GFT		 3156
3157 /*
3158 * set up PCI device basics
3159 */
4330c2f2 3160 rc = pci_enable_device(pdev);
cd0ff491 3161 if (rc) {
937ef75a 3162 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT		 3163 goto err_out;
3164 }
d7699f87 3165
3bf61c55 3166 using_dac = jme_pci_dma64(pdev);
cd0ff491 3167 if (using_dac < 0) {
937ef75a 3168 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT		 3169 rc = -EIO;
3170 goto err_out_disable_pdev;
3171 }
3172
cd0ff491 3173 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
937ef75a 3174 pr_err("No PCI resource region found\n");
4330c2f2
GFT		 3175 rc = -ENOMEM;
3176 goto err_out_disable_pdev;
3177 }
d7699f87 3178
4330c2f2 3179 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 3180 if (rc) {
937ef75a 3181 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT		 3182 goto err_out_disable_pdev;
3183 }
d7699f87
GFT		 3184
3185 pci_set_master(pdev);
3186
3187 /*
3188 * alloc and init net device
3189 */
3bf61c55 3190 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 3191 if (!netdev) {
937ef75a 3192 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT		 3193 rc = -ENOMEM;
3194 goto err_out_release_regions;
d7699f87 3195 }
3b70a6fa
GFT		 3196#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3197 netdev->netdev_ops = &jme_netdev_ops;
3198#else
d7699f87
GFT		 3199 netdev->open = jme_open;
3200 netdev->stop = jme_close;
aa1e7189 3201 netdev->do_ioctl = jme_ioctl;
d7699f87 3202 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT		 3203 netdev->set_mac_address = jme_set_macaddr;
3204 netdev->set_multicast_list = jme_set_multi;
3205 netdev->change_mtu = jme_change_mtu;
8c198884 3206 netdev->tx_timeout = jme_tx_timeout;
42b1055e 3207 netdev->vlan_rx_register = jme_vlan_rx_register;
7ca9ebee
GFT		 3208#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3209 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3210#endif
3bf61c55 3211 NETDEV_GET_STATS(netdev, &jme_get_stats);
3b70a6fa
GFT		 3212#endif
3213 netdev->ethtool_ops = &jme_ethtool_ops;
3214 netdev->watchdog_timeo = TX_TIMEOUT;
767e5b98
MM		 3215#ifdef __USE_NDO_FIX_FEATURES__
3216 netdev->hw_features = NETIF_F_IP_CSUM |
3217 NETIF_F_IPV6_CSUM |
3218 NETIF_F_SG |
3219 NETIF_F_TSO |
3220 NETIF_F_TSO6 |
3221 NETIF_F_RXCSUM;
3222#endif
1a0b42f4
MM		 3223 netdev->features = NETIF_F_IP_CSUM |
3224 NETIF_F_IPV6_CSUM |
b3821cc5
GFT		 3225 NETIF_F_SG |
3226 NETIF_F_TSO |
3227 NETIF_F_TSO6 |
42b1055e
GFT		 3228 NETIF_F_HW_VLAN_TX |
3229 NETIF_F_HW_VLAN_RX;
cd0ff491 3230 if (using_dac)
8c198884 3231 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 3232
3233 SET_NETDEV_DEV(netdev, &pdev->dev);
3234 pci_set_drvdata(pdev, netdev);
3235
3236 /*
3237 * init adapter info
3238 */
3239 jme = netdev_priv(netdev);
3240 jme->pdev = pdev;
3241 jme->dev = netdev;
cdcdc9eb 3242 jme->jme_rx = netif_rx;
5141719b 3243#ifndef __UNIFY_VLAN_RX_PATH__
cdcdc9eb 3244 jme->jme_vlan_rx = vlan_hwaccel_rx;
5141719b 3245#endif
29bdd921 3246 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 3247 jme->phylink = 0;
b3821cc5 3248 jme->tx_ring_size = 1 << 10;
0ede469c 3249 jme->tx_ring_mask = jme->tx_ring_size - 1;
b3821cc5
GFT		 3250 jme->tx_wake_threshold = 1 << 9;
3251 jme->rx_ring_size = 1 << 9;
3252 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 3253 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 3254 jme->regs = ioremap(pci_resource_start(pdev, 0),
3255 pci_resource_len(pdev, 0));
4330c2f2 3256 if (!(jme->regs)) {
937ef75a 3257 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT		 3258 rc = -ENOMEM;
3259 goto err_out_free_netdev;
3260 }
4330c2f2 3261
cd0ff491
GFT		 3262 if (no_pseudohp) {
3263 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3264 jwrite32(jme, JME_APMC, apmc);
3265 } else if (force_pseudohp) {
3266 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3267 jwrite32(jme, JME_APMC, apmc);
3268 }
3269
cdcdc9eb 3270 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 3271
d7699f87 3272 spin_lock_init(&jme->phy_lock);
fcf45b4c 3273 spin_lock_init(&jme->macaddr_lock);
8c198884 3274 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 3275
fcf45b4c
GFT		 3276 atomic_set(&jme->link_changing, 1);
3277 atomic_set(&jme->rx_cleaning, 1);
3278 atomic_set(&jme->tx_cleaning, 1);
192570e0 3279 atomic_set(&jme->rx_empty, 1);
fcf45b4c 3280
79ce639c 3281 tasklet_init(&jme->pcc_task,
7ca9ebee 3282 jme_pcc_tasklet,
79ce639c 3283 (unsigned long) jme);
4330c2f2 3284 tasklet_init(&jme->linkch_task,
7ca9ebee 3285 jme_link_change_tasklet,
4330c2f2
GFT		 3286 (unsigned long) jme);
3287 tasklet_init(&jme->txclean_task,
7ca9ebee 3288 jme_tx_clean_tasklet,
4330c2f2
GFT		 3289 (unsigned long) jme);
3290 tasklet_init(&jme->rxclean_task,
7ca9ebee 3291 jme_rx_clean_tasklet,
4330c2f2 3292 (unsigned long) jme);
fcf45b4c 3293 tasklet_init(&jme->rxempty_task,
7ca9ebee 3294 jme_rx_empty_tasklet,
fcf45b4c 3295 (unsigned long) jme);
0ede469c 3296 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 3297 tasklet_disable_nosync(&jme->txclean_task);
3298 tasklet_disable_nosync(&jme->rxclean_task);
3299 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 3300 jme->dpi.cur = PCC_P1;
3301
cd0ff491 3302 jme->reg_ghc = 0;
79ce639c 3303 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 3304 jme->reg_rxmcs = RXMCS_DEFAULT;
3305 jme->reg_txpfc = 0;
47220951 3306 jme->reg_pmcs = PMCS_MFEN;
dc4185bd 3307 jme->reg_gpreg1 = GPREG1_DEFAULT;
767e5b98 3308#ifndef __USE_NDO_FIX_FEATURES__
cd0ff491
GFT		 3309 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3310 set_bit(JME_FLAG_TSO, &jme->flags);
767e5b98
MM		 3311#else
3312
3313 if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3314 netdev->features |= NETIF_F_RXCSUM;
3315#endif
192570e0 3316
fcf45b4c
GFT		 3317 /*
3318 * Get Max Read Req Size from PCI Config Space
3319 */
cd0ff491
GFT		 3320 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3321 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3322 switch (jme->mrrs) {
3323 case MRRS_128B:
3324 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3325 break;
3326 case MRRS_256B:
3327 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3328 break;
3329 default:
3330 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3331 break;
cd54cf32 3332 }
fcf45b4c 3333
d7699f87 3334 /*
cdcdc9eb 3335 * Must check before reset_mac_processor
d7699f87 3336 */
cdcdc9eb
GFT		 3337 jme_check_hw_ver(jme);
3338 jme->mii_if.dev = netdev;
cd0ff491 3339 if (jme->fpgaver) {
cdcdc9eb 3340 jme->mii_if.phy_id = 0;
cd0ff491 3341 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 3342 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3343 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3344 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 3345 jme->mii_if.phy_id = i;
3346 break;
3347 }
3348 }
3349
cd0ff491 3350 if (!jme->mii_if.phy_id) {
cdcdc9eb 3351 rc = -EIO;
937ef75a
JP		 3352 pr_err("Can not find phy_id\n");
3353 goto err_out_unmap;
cdcdc9eb
GFT		 3354 }
3355
3356 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3357 } else {
cdcdc9eb
GFT		 3358 jme->mii_if.phy_id = 1;
3359 }
cd0ff491 3360 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 3361 jme->mii_if.supports_gmii = true;
3362 else
3363 jme->mii_if.supports_gmii = false;
aa1e7189
GFT		 3364 jme->mii_if.phy_id_mask = 0x1F;
3365 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT		 3366 jme->mii_if.mdio_read = jme_mdio_read;
3367 jme->mii_if.mdio_write = jme_mdio_write;
3368
61891ee4
GFT		 3369 jme_clear_pm(jme);
3370 pci_set_power_state(jme->pdev, PCI_D0);
3371#ifndef JME_NEW_PM_API
3372 jme_pci_wakeup_enable(jme, true);
3373#endif
3374#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
e3b96dc9 3375 device_set_wakeup_enable(&pdev->dev, true);
61891ee4
GFT		 3376#endif
3377
55d19799 3378 jme_set_phyfifo_5level(jme);
711edd99 3379#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
98ef18f1 3380 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
711edd99
SS		 3381#else
3382 jme->pcirev = pdev->revision;
3383#endif
cd0ff491 3384 if (!jme->fpgaver)
cdcdc9eb 3385 jme_phy_init(jme);
42b1055e 3386 jme_phy_off(jme);
cdcdc9eb
GFT		 3387
3388 /*
3389 * Reset MAC processor and reload EEPROM for MAC Address
3390 */
d7699f87 3391 jme_reset_mac_processor(jme);
4330c2f2 3392 rc = jme_reload_eeprom(jme);
cd0ff491 3393 if (rc) {
937ef75a 3394 pr_err("Reload eeprom for reading MAC Address error\n");
0ede469c 3395 goto err_out_unmap;
4330c2f2 3396 }
d7699f87
GFT		 3397 jme_load_macaddr(netdev);
3398
d7699f87
GFT		 3399 /*
3400 * Tell stack that we are not ready to work until open()
3401 */
3402 netif_carrier_off(netdev);
d7699f87 3403
4330c2f2 3404 rc = register_netdev(netdev);
cd0ff491 3405 if (rc) {
937ef75a 3406 pr_err("Cannot register net device\n");
0ede469c 3407 goto err_out_unmap;
4330c2f2 3408 }
d7699f87 3409
98ef18f1 3410 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
937ef75a 3411 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
7ca9ebee
GFT		 3412 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3413 "JMC250 Gigabit Ethernet" :
3414 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3415 "JMC260 Fast Ethernet" : "Unknown",
3416 (jme->fpgaver != 0) ? " (FPGA)" : "",
3417 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
98ef18f1 3418 jme->pcirev,
937ef75a
JP		 3419 netdev->dev_addr[0],
3420 netdev->dev_addr[1],
3421 netdev->dev_addr[2],
3422 netdev->dev_addr[3],
3423 netdev->dev_addr[4],
3424 netdev->dev_addr[5]);
d7699f87
GFT		 3425
3426 return 0;
3427
3428err_out_unmap:
3429 iounmap(jme->regs);
3430err_out_free_netdev:
3431 pci_set_drvdata(pdev, NULL);
3432 free_netdev(netdev);
4330c2f2
GFT		 3433err_out_release_regions:
3434 pci_release_regions(pdev);
d7699f87 3435err_out_disable_pdev:
cd0ff491 3436 pci_disable_device(pdev);
d7699f87 3437err_out:
4330c2f2 3438 return rc;
d7699f87
GFT		 3439}
3440
3bf61c55
GFT		 3441static void __devexit
3442jme_remove_one(struct pci_dev *pdev)
3443{
d7699f87
GFT		 3444 struct net_device *netdev = pci_get_drvdata(pdev);
3445 struct jme_adapter *jme = netdev_priv(netdev);
3446
3447 unregister_netdev(netdev);
3448 iounmap(jme->regs);
3449 pci_set_drvdata(pdev, NULL);
3450 free_netdev(netdev);
3451 pci_release_regions(pdev);
3452 pci_disable_device(pdev);
3453
3454}
3455
a82e368c
GFT		 3456static void
3457jme_shutdown(struct pci_dev *pdev)
3458{
3459 struct net_device *netdev = pci_get_drvdata(pdev);
3460 struct jme_adapter *jme = netdev_priv(netdev);
3461
61891ee4
GFT		 3462 jme_powersave_phy(jme);
3463#ifndef JME_NEW_PM_API
3464 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3465#endif
3d12cc1b 3466#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
61891ee4 3467 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
a82e368c
GFT		 3468#endif
3469}
3470
fda5634a
GFT		 3471#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3472 #ifdef CONFIG_PM
3473 #define JME_HAVE_PM
3474 #endif
3475#else
3476 #ifdef CONFIG_PM_SLEEP
3477 #define JME_HAVE_PM
3478 #endif
3479#endif
3480
3481#ifdef JME_HAVE_PM
29bdd921 3482static int
3d12cc1b 3483#ifdef JME_NEW_PM_API
7370b85a 3484jme_suspend(struct device *dev)
3d12cc1b
GFT		 3485#else
3486jme_suspend(struct pci_dev *pdev, pm_message_t state)
7370b85a 3487#endif
29bdd921 3488{
3d12cc1b 3489#ifdef JME_NEW_PM_API
7370b85a
RW		 3490 struct pci_dev *pdev = to_pci_dev(dev);
3491#endif
29bdd921
GFT		 3492 struct net_device *netdev = pci_get_drvdata(pdev);
3493 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 3494
3495 atomic_dec(&jme->link_changing);
3496
3497 netif_device_detach(netdev);
3498 netif_stop_queue(netdev);
3499 jme_stop_irq(jme);
29bdd921 3500
cd0ff491
GFT		 3501 tasklet_disable(&jme->txclean_task);
3502 tasklet_disable(&jme->rxclean_task);
3503 tasklet_disable(&jme->rxempty_task);
3504
cd0ff491
GFT		 3505 if (netif_carrier_ok(netdev)) {
3506 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 3507 jme_polling_mode(jme);
3508
29bdd921 3509 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 3510 jme_disable_rx_engine(jme);
3511 jme_disable_tx_engine(jme);
29bdd921
GFT		 3512 jme_reset_mac_processor(jme);
3513 jme_free_rx_resources(jme);
3514 jme_free_tx_resources(jme);
3515 netif_carrier_off(netdev);
3516 jme->phylink = 0;
3517 }
3518
cd0ff491
GFT		 3519 tasklet_enable(&jme->txclean_task);
3520 tasklet_hi_enable(&jme->rxclean_task);
3521 tasklet_hi_enable(&jme->rxempty_task);
29bdd921 3522
a82e368c 3523 jme_powersave_phy(jme);
3d12cc1b 3524#ifndef JME_NEW_PM_API
7370b85a 3525 pci_save_state(pdev);
61891ee4 3526 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
a82e368c 3527 pci_set_power_state(pdev, PCI_D3hot);
7370b85a 3528#endif
29bdd921
GFT		 3529
3530 return 0;
3531}
3532
3533static int
3d12cc1b 3534#ifdef JME_NEW_PM_API
7370b85a 3535jme_resume(struct device *dev)
3d12cc1b
GFT		 3536#else
3537jme_resume(struct pci_dev *pdev)
7370b85a 3538#endif
29bdd921 3539{
3d12cc1b 3540#ifdef JME_NEW_PM_API
7370b85a
RW		 3541 struct pci_dev *pdev = to_pci_dev(dev);
3542#endif
29bdd921
GFT		 3543 struct net_device *netdev = pci_get_drvdata(pdev);
3544 struct jme_adapter *jme = netdev_priv(netdev);
3545
3546 jme_clear_pm(jme);
3d12cc1b
GFT		 3547#ifndef JME_NEW_PM_API
3548 pci_set_power_state(pdev, PCI_D0);
29bdd921 3549 pci_restore_state(pdev);
7370b85a 3550#endif
29bdd921 3551
ed457bcc
GFT		 3552 jme_phy_on(jme);
3553 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3554 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 3555 else
29bdd921
GFT		 3556 jme_reset_phy_processor(jme);
3557
29bdd921
GFT		 3558 jme_start_irq(jme);
3559 netif_device_attach(netdev);
3560
3561 atomic_inc(&jme->link_changing);
3562
3563 jme_reset_link(jme);
3564
3565 return 0;
3566}
7370b85a 3567
e3b96dc9 3568#ifdef JME_NEW_PM_API
7370b85a
RW		 3569static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3570#define JME_PM_OPS (&jme_pm_ops)
3571#endif
3572
3573#else
3574
e3b96dc9 3575#ifdef JME_NEW_PM_API
7370b85a
RW		 3576#define JME_PM_OPS NULL
3577#endif
7ee473a3 3578#endif
29bdd921 3579
7ca9ebee 3580#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
d7699f87 3581static struct pci_device_id jme_pci_tbl[] = {
7ca9ebee
GFT		 3582#else
3583static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3584#endif
cd0ff491
GFT		 3585 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3586 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3587 { }
3588};
3589
3590static struct pci_driver jme_driver = {
cd0ff491
GFT		 3591 .name = DRV_NAME,
3592 .id_table = jme_pci_tbl,
3593 .probe = jme_init_one,
3594 .remove = __devexit_p(jme_remove_one),
a82e368c 3595 .shutdown = jme_shutdown,
e3b96dc9 3596#ifndef JME_NEW_PM_API
7370b85a
RW		 3597 .suspend = jme_suspend,
3598 .resume = jme_resume
3599#else
3600 .driver.pm = JME_PM_OPS,
3601#endif
d7699f87
GFT		 3602};
3603
3bf61c55
GFT		 3604static int __init
3605jme_init_module(void)
d7699f87 3606{
937ef75a 3607 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3608 return pci_register_driver(&jme_driver);
3609}
3610
3bf61c55
GFT		 3611static void __exit
3612jme_cleanup_module(void)
d7699f87
GFT		 3613{
3614 pci_unregister_driver(&jme_driver);
3615}
3616
3617module_init(jme_init_module);
3618module_exit(jme_cleanup_module);
3619
3bf61c55 3620MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3621MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3622MODULE_LICENSE("GPL");
3623MODULE_VERSION(DRV_VERSION);
3624MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3625
JMicron Ethernet Linux driver