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Add fedora compile test
[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT		 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
2e582300 25#include <linux/version.h>
937ef75a
JP		 26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
d7699f87
GFT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
4330c2f2 38#include <linux/delay.h>
29bdd921 39#include <linux/spinlock.h>
8c198884
GFT		 40#include <linux/in.h>
41#include <linux/ip.h>
79ce639c
GFT		 42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
42b1055e 45#include <linux/if_vlan.h>
38d1bc09 46#include <linux/slab.h>
3b70a6fa 47#include <net/ip6_checksum.h>
d7699f87
GFT		 48#include "jme.h"
49
cd0ff491
GFT		 50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 61
6d06d88c 62#ifndef JME_NEW_PM_API
3d12cc1b
GFT		 63static void
64jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
65{
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
67 pci_enable_wake(jme->pdev, PCI_D1, enable);
68 pci_enable_wake(jme->pdev, PCI_D2, enable);
69 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
70 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
71#else
72 pci_pme_active(jme->pdev, enable);
73#endif
74}
6d06d88c 75#endif
3d12cc1b 76
3bf61c55
GFT		 77static int
78jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 79{
80 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 81 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 82
186fc259 83read_again:
cd0ff491 84 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 85 smi_phy_addr(phy) |
86 smi_reg_addr(reg));
d7699f87
GFT		 87
88 wmb();
cd0ff491 89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 90 udelay(20);
b3821cc5
GFT		 91 val = jread32(jme, JME_SMI);
92 if ((val & SMI_OP_REQ) == 0)
3bf61c55 93 break;
cd0ff491 94 }
d7699f87 95
cd0ff491 96 if (i == 0) {
937ef75a 97 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 98 return 0;
cd0ff491 99 }
d7699f87 100
cd0ff491 101 if (again--)
186fc259
GFT		 102 goto read_again;
103
cd0ff491 104 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 105}
106
3bf61c55
GFT		 107static void
108jme_mdio_write(struct net_device *netdev,
109 int phy, int reg, int val)
d7699f87
GFT		 110{
111 struct jme_adapter *jme = netdev_priv(netdev);
112 int i;
113
3bf61c55
GFT		 114 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
115 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
116 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 117
118 wmb();
cdcdc9eb
GFT		 119 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
120 udelay(20);
8d27293f 121 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 122 break;
123 }
d7699f87 124
3bf61c55 125 if (i == 0)
937ef75a 126 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT		 127}
128
cd0ff491 129static inline void
3bf61c55 130jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 131{
cd0ff491 132 u32 val;
3bf61c55
GFT		 133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
8c198884
GFT		 136 MII_ADVERTISE, ADVERTISE_ALL |
137 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 138
cd0ff491 139 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 140 jme_mdio_write(jme->dev,
141 jme->mii_if.phy_id,
142 MII_CTRL1000,
143 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 144
fcf45b4c
GFT		 145 val = jme_mdio_read(jme->dev,
146 jme->mii_if.phy_id,
147 MII_BMCR);
148
149 jme_mdio_write(jme->dev,
150 jme->mii_if.phy_id,
151 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT		 152}
153
b3821cc5
GFT		 154static void
155jme_setup_wakeup_frame(struct jme_adapter *jme,
a4181cd4 156 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 157{
158 int i;
159
160 /*
161 * Setup CRC pattern
162 */
163 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
164 wmb();
165 jwrite32(jme, JME_WFODP, crc);
166 wmb();
167
168 /*
169 * Setup Mask
170 */
cd0ff491 171 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 172 jwrite32(jme, JME_WFOI,
173 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
174 (fnr & WFOI_FRAME_SEL));
175 wmb();
176 jwrite32(jme, JME_WFODP, mask[i]);
177 wmb();
178 }
179}
3bf61c55 180
dc4185bd
GFT		 181static inline void
182jme_mac_rxclk_off(struct jme_adapter *jme)
183{
184 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
185 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
186}
187
188static inline void
189jme_mac_rxclk_on(struct jme_adapter *jme)
190{
191 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
192 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
193}
194
195static inline void
196jme_mac_txclk_off(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_mac_txclk_on(struct jme_adapter *jme)
204{
205 u32 speed = jme->reg_ghc & GHC_SPEED;
206 if (speed == GHC_SPEED_1000M)
207 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
208 else
209 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
210 jwrite32f(jme, JME_GHC, jme->reg_ghc);
211}
212
213static inline void
214jme_reset_ghc_speed(struct jme_adapter *jme)
215{
216 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_reset_250A2_workaround(struct jme_adapter *jme)
222{
223 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
224 GPREG1_RSSPATCH);
225 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
226}
227
228static inline void
229jme_assert_ghc_reset(struct jme_adapter *jme)
230{
231 jme->reg_ghc |= GHC_SWRST;
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
233}
234
235static inline void
236jme_clear_ghc_reset(struct jme_adapter *jme)
237{
238 jme->reg_ghc &= ~GHC_SWRST;
239 jwrite32f(jme, JME_GHC, jme->reg_ghc);
240}
241
cd0ff491 242static inline void
3bf61c55
GFT		 243jme_reset_mac_processor(struct jme_adapter *jme)
244{
a4181cd4 245 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT		 246 u32 crc = 0xCDCDCDCD;
247 u32 gpreg0;
b3821cc5
GFT		 248 int i;
249
dc4185bd
GFT		 250 jme_reset_ghc_speed(jme);
251 jme_reset_250A2_workaround(jme);
252
253 jme_mac_rxclk_on(jme);
254 jme_mac_txclk_on(jme);
255 udelay(1);
256 jme_assert_ghc_reset(jme);
257 udelay(1);
258 jme_mac_rxclk_off(jme);
259 jme_mac_txclk_off(jme);
260 udelay(1);
261 jme_clear_ghc_reset(jme);
262 udelay(1);
263 jme_mac_rxclk_on(jme);
264 jme_mac_txclk_on(jme);
265 udelay(1);
266 jme_mac_rxclk_off(jme);
267 jme_mac_txclk_off(jme);
cd0ff491
GFT		 268
269 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
270 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
271 jwrite32(jme, JME_RXQDC, 0x00000000);
272 jwrite32(jme, JME_RXNDA, 0x00000000);
273 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
274 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
275 jwrite32(jme, JME_TXQDC, 0x00000000);
276 jwrite32(jme, JME_TXNDA, 0x00000000);
277
4330c2f2
GFT		 278 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
279 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 280 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 281 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 282 if (jme->fpgaver)
cdcdc9eb
GFT		 283 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
284 else
285 gpreg0 = GPREG0_DEFAULT;
286 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT		 287}
288
289static inline void
3bf61c55 290jme_clear_pm(struct jme_adapter *jme)
d7699f87 291{
3d12cc1b 292 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
d7699f87
GFT		 293}
294
3bf61c55
GFT		 295static int
296jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 297{
cd0ff491 298 u32 val;
d7699f87
GFT		 299 int i;
300
301 val = jread32(jme, JME_SMBCSR);
302
cd0ff491 303 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 304 val |= SMBCSR_CNACK;
305 jwrite32(jme, JME_SMBCSR, val);
306 val |= SMBCSR_RELOAD;
307 jwrite32(jme, JME_SMBCSR, val);
308 mdelay(12);
309
cd0ff491 310 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 311 mdelay(1);
312 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
313 break;
314 }
315
cd0ff491 316 if (i == 0) {
937ef75a 317 pr_err("eeprom reload timeout\n");
d7699f87
GFT		 318 return -EIO;
319 }
320 }
3bf61c55 321
d7699f87
GFT		 322 return 0;
323}
324
3bf61c55
GFT		 325static void
326jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 327{
328 struct jme_adapter *jme = netdev_priv(netdev);
329 unsigned char macaddr[6];
cd0ff491 330 u32 val;
d7699f87 331
cd0ff491 332 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 333 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 334 macaddr[0] = (val >> 0) & 0xFF;
335 macaddr[1] = (val >> 8) & 0xFF;
336 macaddr[2] = (val >> 16) & 0xFF;
337 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 338 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 339 macaddr[4] = (val >> 0) & 0xFF;
340 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 341 memcpy(netdev->dev_addr, macaddr, 6);
342 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 343}
344
cd0ff491 345static inline void
3bf61c55
GFT		 346jme_set_rx_pcc(struct jme_adapter *jme, int p)
347{
cd0ff491 348 switch (p) {
192570e0
GFT		 349 case PCC_OFF:
350 jwrite32(jme, JME_PCCRX0,
351 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
352 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
353 break;
3bf61c55
GFT		 354 case PCC_P1:
355 jwrite32(jme, JME_PCCRX0,
356 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
357 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
358 break;
359 case PCC_P2:
360 jwrite32(jme, JME_PCCRX0,
361 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
362 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
363 break;
364 case PCC_P3:
365 jwrite32(jme, JME_PCCRX0,
366 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
367 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
368 break;
369 default:
370 break;
371 }
192570e0 372 wmb();
3bf61c55 373
cd0ff491 374 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
7ca9ebee 375 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 376}
377
fcf45b4c 378static void
3bf61c55 379jme_start_irq(struct jme_adapter *jme)
d7699f87 380{
3bf61c55
GFT		 381 register struct dynpcc_info *dpi = &(jme->dpi);
382
383 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 384 dpi->cur = PCC_P1;
385 dpi->attempt = PCC_P1;
386 dpi->cnt = 0;
387
388 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 389 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
390 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 391 PCCTXQ0_EN
392 );
393
d7699f87
GFT		 394 /*
395 * Enable Interrupts
396 */
397 jwrite32(jme, JME_IENS, INTR_ENABLE);
398}
399
cd0ff491 400static inline void
3bf61c55 401jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 402{
403 /*
404 * Disable Interrupts
405 */
cd0ff491 406 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 407}
408
cd0ff491 409static u32
cdcdc9eb
GFT		 410jme_linkstat_from_phy(struct jme_adapter *jme)
411{
cd0ff491 412 u32 phylink, bmsr;
cdcdc9eb
GFT		 413
414 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
415 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 416 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 417 phylink |= PHY_LINK_AUTONEG_COMPLETE;
418
419 return phylink;
420}
421
cd0ff491 422static inline void
55d19799 423jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT		 424{
425 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
426}
427
428static inline void
55d19799 429jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT		 430{
431 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
432}
433
fcf45b4c
GFT		 434static int
435jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 436{
437 struct jme_adapter *jme = netdev_priv(netdev);
dc4185bd 438 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 439 char linkmsg[64];
fcf45b4c 440 int rc = 0;
d7699f87 441
b3821cc5 442 linkmsg[0] = '\0';
cdcdc9eb 443
cd0ff491 444 if (jme->fpgaver)
cdcdc9eb
GFT		 445 phylink = jme_linkstat_from_phy(jme);
446 else
447 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 448
cd0ff491
GFT		 449 if (phylink & PHY_LINK_UP) {
450 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 451 /*
452 * If we did not enable AN
453 * Speed/Duplex Info should be obtained from SMI
454 */
455 phylink = PHY_LINK_UP;
456
457 bmcr = jme_mdio_read(jme->dev,
458 jme->mii_if.phy_id,
459 MII_BMCR);
460
461 phylink |= ((bmcr & BMCR_SPEED1000) &&
462 (bmcr & BMCR_SPEED100) == 0) ?
463 PHY_LINK_SPEED_1000M :
464 (bmcr & BMCR_SPEED100) ?
465 PHY_LINK_SPEED_100M :
466 PHY_LINK_SPEED_10M;
467
468 phylink |= (bmcr & BMCR_FULLDPLX) ?
469 PHY_LINK_DUPLEX : 0;
79ce639c 470
b3821cc5 471 strcat(linkmsg, "Forced: ");
cd0ff491 472 } else {
8c198884
GFT		 473 /*
474 * Keep polling for speed/duplex resolve complete
475 */
cd0ff491 476 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 477 --cnt) {
478
479 udelay(1);
8c198884 480
cd0ff491 481 if (jme->fpgaver)
cdcdc9eb
GFT		 482 phylink = jme_linkstat_from_phy(jme);
483 else
484 phylink = jread32(jme, JME_PHY_LINK);
8c198884 485 }
cd0ff491 486 if (!cnt)
937ef75a 487 pr_err("Waiting speed resolve timeout\n");
79ce639c 488
b3821cc5 489 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 490 }
491
cd0ff491 492 if (jme->phylink == phylink) {
fcf45b4c
GFT		 493 rc = 1;
494 goto out;
495 }
cd0ff491 496 if (testonly)
fcf45b4c
GFT		 497 goto out;
498
499 jme->phylink = phylink;
500
dc4185bd
GFT		 501 /*
502 * The speed/duplex setting of jme->reg_ghc already cleared
503 * by jme_reset_mac_processor()
504 */
cd0ff491
GFT		 505 switch (phylink & PHY_LINK_SPEED_MASK) {
506 case PHY_LINK_SPEED_10M:
dc4185bd 507 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 508 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 509 break;
510 case PHY_LINK_SPEED_100M:
dc4185bd 511 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 512 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 513 break;
514 case PHY_LINK_SPEED_1000M:
dc4185bd 515 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 516 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 517 break;
518 default:
519 break;
d7699f87 520 }
d7699f87 521
cd0ff491 522 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 523 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
809b2798 524 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
dc4185bd 525 jme->reg_ghc |= GHC_DPX;
cd0ff491 526 } else {
d7699f87 527 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 528 TXMCS_BACKOFF |
529 TXMCS_CARRIERSENSE |
530 TXMCS_COLLISION);
809b2798 531 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 532 }
7ee473a3 533
dc4185bd
GFT		 534 jwrite32(jme, JME_GHC, jme->reg_ghc);
535
7ee473a3 536 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
dc4185bd
GFT		 537 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
538 GPREG1_RSSPATCH);
7ee473a3 539 if (!(phylink & PHY_LINK_DUPLEX))
dc4185bd 540 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
7ee473a3
GFT		 541 switch (phylink & PHY_LINK_SPEED_MASK) {
542 case PHY_LINK_SPEED_10M:
55d19799 543 jme_set_phyfifo_8level(jme);
dc4185bd 544 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 545 break;
546 case PHY_LINK_SPEED_100M:
55d19799 547 jme_set_phyfifo_5level(jme);
dc4185bd 548 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 549 break;
550 case PHY_LINK_SPEED_1000M:
55d19799 551 jme_set_phyfifo_8level(jme);
7ee473a3
GFT		 552 break;
553 default:
554 break;
555 }
556 }
dc4185bd 557 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 558
3b70a6fa
GFT		 559 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
560 "Full-Duplex, " :
561 "Half-Duplex, ");
562 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
563 "MDI-X" :
564 "MDI");
937ef75a 565 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT		 566 netif_carrier_on(netdev);
567 } else {
568 if (testonly)
fcf45b4c
GFT		 569 goto out;
570
937ef75a 571 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 572 jme->phylink = 0;
cd0ff491 573 netif_carrier_off(netdev);
d7699f87 574 }
fcf45b4c
GFT		 575
576out:
577 return rc;
d7699f87
GFT		 578}
579
3bf61c55
GFT		 580static int
581jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 582{
d7699f87
GFT		 583 struct jme_ring *txring = &(jme->txring[0]);
584
585 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 586 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
587 &(txring->dmaalloc),
588 GFP_ATOMIC);
fcf45b4c 589
0ede469c
GFT		 590 if (!txring->alloc)
591 goto err_set_null;
d7699f87
GFT		 592
593 /*
594 * 16 Bytes align
595 */
cd0ff491 596 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 597 RING_DESC_ALIGN);
4330c2f2 598 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 599 txring->next_to_use = 0;
cdcdc9eb 600 atomic_set(&txring->next_to_clean, 0);
b3821cc5 601 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 602
0ede469c
GFT		 603 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
604 jme->tx_ring_size, GFP_ATOMIC);
605 if (unlikely(!(txring->bufinf)))
606 goto err_free_txring;
607
d7699f87 608 /*
b3821cc5 609 * Initialize Transmit Descriptors
d7699f87 610 */
b3821cc5 611 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 612 memset(txring->bufinf, 0,
b3821cc5 613 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 614
615 return 0;
0ede469c
GFT		 616
617err_free_txring:
618 dma_free_coherent(&(jme->pdev->dev),
619 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
620 txring->alloc,
621 txring->dmaalloc);
622
623err_set_null:
624 txring->desc = NULL;
625 txring->dmaalloc = 0;
626 txring->dma = 0;
627 txring->bufinf = NULL;
628
629 return -ENOMEM;
d7699f87
GFT		 630}
631
3bf61c55
GFT		 632static void
633jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 634{
635 int i;
636 struct jme_ring *txring = &(jme->txring[0]);
0ede469c 637 struct jme_buffer_info *txbi;
d7699f87 638
cd0ff491 639 if (txring->alloc) {
0ede469c
GFT		 640 if (txring->bufinf) {
641 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
642 txbi = txring->bufinf + i;
643 if (txbi->skb) {
644 dev_kfree_skb(txbi->skb);
645 txbi->skb = NULL;
646 }
647 txbi->mapping = 0;
648 txbi->len = 0;
649 txbi->nr_desc = 0;
650 txbi->start_xmit = 0;
d7699f87 651 }
0ede469c 652 kfree(txring->bufinf);
d7699f87
GFT		 653 }
654
655 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 656 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 657 txring->alloc,
658 txring->dmaalloc);
3bf61c55
GFT		 659
660 txring->alloc = NULL;
661 txring->desc = NULL;
662 txring->dmaalloc = 0;
663 txring->dma = 0;
0ede469c 664 txring->bufinf = NULL;
d7699f87 665 }
3bf61c55 666 txring->next_to_use = 0;
cdcdc9eb 667 atomic_set(&txring->next_to_clean, 0);
79ce639c 668 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 669}
670
cd0ff491 671static inline void
3bf61c55 672jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 673{
674 /*
675 * Select Queue 0
676 */
677 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 678 wmb();
d7699f87
GFT		 679
680 /*
681 * Setup TX Queue 0 DMA Bass Address
682 */
fcf45b4c 683 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 684 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 685 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 686
687 /*
688 * Setup TX Descptor Count
689 */
b3821cc5 690 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 691
692 /*
693 * Enable TX Engine
694 */
695 wmb();
dc4185bd 696 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT		 697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
d7699f87 699
dc4185bd
GFT		 700 /*
701 * Start clock for TX MAC Processor
702 */
703 jme_mac_txclk_on(jme);
d7699f87
GFT		 704}
705
cd0ff491 706static inline void
29bdd921
GFT		 707jme_restart_tx_engine(struct jme_adapter *jme)
708{
709 /*
710 * Restart TX Engine
711 */
712 jwrite32(jme, JME_TXCS, jme->reg_txcs |
713 TXCS_SELECT_QUEUE0 |
714 TXCS_ENABLE);
715}
716
cd0ff491 717static inline void
3bf61c55 718jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 719{
720 int i;
cd0ff491 721 u32 val;
d7699f87
GFT		 722
723 /*
724 * Disable TX Engine
725 */
fcf45b4c 726 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 727 wmb();
d7699f87
GFT		 728
729 val = jread32(jme, JME_TXCS);
cd0ff491 730 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 731 mdelay(1);
d7699f87 732 val = jread32(jme, JME_TXCS);
cd0ff491 733 rmb();
d7699f87
GFT		 734 }
735
cd0ff491 736 if (!i)
937ef75a 737 pr_err("Disable TX engine timeout\n");
dc4185bd
GFT		 738
739 /*
740 * Stop clock for TX MAC Processor
741 */
742 jme_mac_txclk_off(jme);
d7699f87
GFT		 743}
744
3bf61c55
GFT		 745static void
746jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 747{
0ede469c 748 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 749 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 750 struct jme_buffer_info *rxbi = rxring->bufinf;
751 rxdesc += i;
752 rxbi += i;
753
754 rxdesc->dw[0] = 0;
755 rxdesc->dw[1] = 0;
3bf61c55 756 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 757 rxdesc->desc1.bufaddrl = cpu_to_le32(
758 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 759 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 760 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 761 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 762 wmb();
3bf61c55 763 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 764}
765
3bf61c55
GFT		 766static int
767jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 768{
769 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 770 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 771 struct sk_buff *skb;
4330c2f2 772
79ce639c
GFT		 773 skb = netdev_alloc_skb(jme->dev,
774 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 775 if (unlikely(!skb))
4330c2f2 776 return -ENOMEM;
3b70a6fa
GFT		 777#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
778 skb->dev = jme->dev;
779#endif
3bf61c55 780
4330c2f2 781 rxbi->skb = skb;
3bf61c55 782 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT		 783 rxbi->mapping = pci_map_page(jme->pdev,
784 virt_to_page(skb->data),
785 offset_in_page(skb->data),
786 rxbi->len,
787 PCI_DMA_FROMDEVICE);
4330c2f2
GFT		 788
789 return 0;
790}
791
3bf61c55
GFT		 792static void
793jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 794{
795 struct jme_ring *rxring = &(jme->rxring[0]);
796 struct jme_buffer_info *rxbi = rxring->bufinf;
797 rxbi += i;
798
cd0ff491 799 if (rxbi->skb) {
b3821cc5 800 pci_unmap_page(jme->pdev,
4330c2f2 801 rxbi->mapping,
3bf61c55 802 rxbi->len,
4330c2f2
GFT		 803 PCI_DMA_FROMDEVICE);
804 dev_kfree_skb(rxbi->skb);
805 rxbi->skb = NULL;
806 rxbi->mapping = 0;
3bf61c55 807 rxbi->len = 0;
4330c2f2
GFT		 808 }
809}
810
3bf61c55
GFT		 811static void
812jme_free_rx_resources(struct jme_adapter *jme)
813{
814 int i;
815 struct jme_ring *rxring = &(jme->rxring[0]);
816
cd0ff491 817 if (rxring->alloc) {
0ede469c
GFT		 818 if (rxring->bufinf) {
819 for (i = 0 ; i < jme->rx_ring_size ; ++i)
820 jme_free_rx_buf(jme, i);
821 kfree(rxring->bufinf);
822 }
3bf61c55
GFT		 823
824 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 825 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 826 rxring->alloc,
827 rxring->dmaalloc);
828 rxring->alloc = NULL;
829 rxring->desc = NULL;
830 rxring->dmaalloc = 0;
831 rxring->dma = 0;
0ede469c 832 rxring->bufinf = NULL;
3bf61c55
GFT		 833 }
834 rxring->next_to_use = 0;
cdcdc9eb 835 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 836}
837
838static int
839jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 840{
841 int i;
842 struct jme_ring *rxring = &(jme->rxring[0]);
843
844 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 845 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
846 &(rxring->dmaalloc),
847 GFP_ATOMIC);
0ede469c
GFT		 848 if (!rxring->alloc)
849 goto err_set_null;
d7699f87
GFT		 850
851 /*
852 * 16 Bytes align
853 */
cd0ff491 854 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 855 RING_DESC_ALIGN);
4330c2f2 856 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 857 rxring->next_to_use = 0;
cdcdc9eb 858 atomic_set(&rxring->next_to_clean, 0);
d7699f87 859
0ede469c
GFT		 860 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
861 jme->rx_ring_size, GFP_ATOMIC);
862 if (unlikely(!(rxring->bufinf)))
863 goto err_free_rxring;
864
d7699f87
GFT		 865 /*
866 * Initiallize Receive Descriptors
867 */
0ede469c
GFT		 868 memset(rxring->bufinf, 0,
869 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 870 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
871 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 872 jme_free_rx_resources(jme);
873 return -ENOMEM;
874 }
d7699f87
GFT		 875
876 jme_set_clean_rxdesc(jme, i);
877 }
878
d7699f87 879 return 0;
0ede469c
GFT		 880
881err_free_rxring:
882 dma_free_coherent(&(jme->pdev->dev),
883 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
884 rxring->alloc,
885 rxring->dmaalloc);
886err_set_null:
887 rxring->desc = NULL;
888 rxring->dmaalloc = 0;
889 rxring->dma = 0;
890 rxring->bufinf = NULL;
891
892 return -ENOMEM;
d7699f87
GFT		 893}
894
cd0ff491 895static inline void
3bf61c55 896jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 897{
cd0ff491
GFT		 898 /*
899 * Select Queue 0
900 */
901 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
902 RXCS_QUEUESEL_Q0);
903 wmb();
904
d7699f87
GFT		 905 /*
906 * Setup RX DMA Bass Address
907 */
0ede469c 908 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 909 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
0ede469c 910 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 911
912 /*
b3821cc5 913 * Setup RX Descriptor Count
d7699f87 914 */
b3821cc5 915 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 916
3bf61c55 917 /*
d7699f87
GFT		 918 * Setup Unicast Filter
919 */
e523cd89 920 jme_set_unicastaddr(jme->dev);
d7699f87
GFT		 921 jme_set_multi(jme->dev);
922
923 /*
924 * Enable RX Engine
925 */
926 wmb();
dc4185bd 927 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 928 RXCS_QUEUESEL_Q0 |
929 RXCS_ENABLE |
930 RXCS_QST);
dc4185bd
GFT		 931
932 /*
933 * Start clock for RX MAC Processor
934 */
935 jme_mac_rxclk_on(jme);
d7699f87
GFT		 936}
937
cd0ff491 938static inline void
3bf61c55 939jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 940{
941 /*
3bf61c55 942 * Start RX Engine
4330c2f2 943 */
79ce639c 944 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 945 RXCS_QUEUESEL_Q0 |
946 RXCS_ENABLE |
947 RXCS_QST);
948}
949
cd0ff491 950static inline void
3bf61c55 951jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 952{
953 int i;
cd0ff491 954 u32 val;
d7699f87
GFT		 955
956 /*
957 * Disable RX Engine
958 */
29bdd921 959 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 960 wmb();
d7699f87
GFT		 961
962 val = jread32(jme, JME_RXCS);
cd0ff491 963 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 964 mdelay(1);
d7699f87 965 val = jread32(jme, JME_RXCS);
cd0ff491 966 rmb();
d7699f87
GFT		 967 }
968
cd0ff491 969 if (!i)
937ef75a 970 pr_err("Disable RX engine timeout\n");
d7699f87 971
dc4185bd
GFT		 972 /*
973 * Stop clock for RX MAC Processor
974 */
975 jme_mac_rxclk_off(jme);
d7699f87
GFT		 976}
977
93f698ca
GFT		 978static u16
979jme_udpsum(struct sk_buff *skb)
980{
981 u16 csum = 0xFFFFu;
65ff9ddf
GFT		 982#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
983 struct iphdr *iph;
984 int iphlen;
985 struct udphdr *udph;
986#endif
93f698ca
GFT		 987
988 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
989 return csum;
990 if (skb->protocol != htons(ETH_P_IP))
991 return csum;
65ff9ddf
GFT		 992#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
993 iph = (struct iphdr *)skb_pull(skb, ETH_HLEN);
994 iphlen = (iph->ihl << 2);
995 if ((iph->protocol != IPPROTO_UDP) ||
996 (skb->len < (iphlen + sizeof(struct udphdr)))) {
997 skb_push(skb, ETH_HLEN);
998 return csum;
999 }
1000 udph = (struct udphdr *)skb_pull(skb, iphlen);
1001 csum = udph->check;
1002 skb_push(skb, iphlen);
1003 skb_push(skb, ETH_HLEN);
1004#else
93f698ca
GFT		 1005 skb_set_network_header(skb, ETH_HLEN);
1006 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
1007 (skb->len < (ETH_HLEN +
1008 (ip_hdr(skb)->ihl << 2) +
1009 sizeof(struct udphdr)))) {
1010 skb_reset_network_header(skb);
1011 return csum;
1012 }
1013 skb_set_transport_header(skb,
1014 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
1015 csum = udp_hdr(skb)->check;
1016 skb_reset_transport_header(skb);
1017 skb_reset_network_header(skb);
65ff9ddf 1018#endif
93f698ca
GFT		 1019
1020 return csum;
1021}
1022
192570e0 1023static int
93f698ca 1024jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
192570e0 1025{
cd0ff491 1026 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 1027 return false;
1028
0ede469c
GFT		 1029 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1030 == RXWBFLAG_TCPON)) {
1031 if (flags & RXWBFLAG_IPV4)
7ca9ebee 1032 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
0ede469c 1033 return false;
192570e0
GFT		 1034 }
1035
0ede469c 1036 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
93f698ca 1037 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
0ede469c 1038 if (flags & RXWBFLAG_IPV4)
937ef75a 1039 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
0ede469c 1040 return false;
192570e0
GFT		 1041 }
1042
0ede469c
GFT		 1043 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1044 == RXWBFLAG_IPV4)) {
937ef75a 1045 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
0ede469c 1046 return false;
192570e0
GFT		 1047 }
1048
1049 return true;
1050}
1051
3bf61c55 1052static void
42b1055e 1053jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 1054{
d7699f87 1055 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1056 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 1057 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 1058 struct sk_buff *skb;
3bf61c55 1059 int framesize;
d7699f87 1060
3bf61c55
GFT		 1061 rxdesc += idx;
1062 rxbi += idx;
d7699f87 1063
3bf61c55
GFT		 1064 skb = rxbi->skb;
1065 pci_dma_sync_single_for_cpu(jme->pdev,
1066 rxbi->mapping,
1067 rxbi->len,
1068 PCI_DMA_FROMDEVICE);
1069
cd0ff491 1070 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 1071 pci_dma_sync_single_for_device(jme->pdev,
1072 rxbi->mapping,
1073 rxbi->len,
1074 PCI_DMA_FROMDEVICE);
1075
1076 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1077 } else {
3bf61c55
GFT		 1078 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1079 - RX_PREPAD_SIZE;
1080
1081 skb_reserve(skb, RX_PREPAD_SIZE);
1082 skb_put(skb, framesize);
1083 skb->protocol = eth_type_trans(skb, jme->dev);
1084
93f698ca 1085 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
8c198884 1086 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1087 else
614c0bfd 1088#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
29bdd921 1089 skb->ip_summed = CHECKSUM_NONE;
08f5fcfa
ED		 1090#else
1091 skb_checksum_none_assert(skb);
1092#endif
8c198884 1093
3b70a6fa 1094 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 1095 if (jme->vlgrp) {
cdcdc9eb 1096 jme->jme_vlan_rx(skb, jme->vlgrp,
3b70a6fa 1097 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 1098 NET_STAT(jme).rx_bytes += 4;
7ca9ebee 1099 } else {
7ca9ebee 1100 dev_kfree_skb(skb);
b3821cc5 1101 }
cd0ff491 1102 } else {
cdcdc9eb 1103 jme->jme_rx(skb);
b3821cc5 1104 }
3bf61c55 1105
3b70a6fa
GFT		 1106 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1107 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 1108 ++(NET_STAT(jme).multicast);
1109
3bf61c55
GFT		 1110 NET_STAT(jme).rx_bytes += framesize;
1111 ++(NET_STAT(jme).rx_packets);
1112 }
1113
1114 jme_set_clean_rxdesc(jme, idx);
1115
1116}
1117
1118static int
1119jme_process_receive(struct jme_adapter *jme, int limit)
1120{
1121 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1122 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1123 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1124
cd0ff491 1125 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 1126 goto out_inc;
1127
cd0ff491 1128 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 1129 goto out_inc;
1130
cd0ff491 1131 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 1132 goto out_inc;
1133
cdcdc9eb 1134 i = atomic_read(&rxring->next_to_clean);
0ede469c 1135 while (limit > 0) {
3bf61c55
GFT		 1136 rxdesc = rxring->desc;
1137 rxdesc += i;
1138
3b70a6fa 1139 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 1140 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1141 goto out;
0ede469c 1142 --limit;
d7699f87 1143
9134abda 1144 rmb();
4330c2f2
GFT		 1145 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1146
cd0ff491 1147 if (unlikely(desccnt > 1 ||
192570e0 1148 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1149
cd0ff491 1150 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1151 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1152 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1153 ++(NET_STAT(jme).rx_fifo_errors);
1154 else
1155 ++(NET_STAT(jme).rx_errors);
4330c2f2 1156
cd0ff491 1157 if (desccnt > 1)
3bf61c55 1158 limit -= desccnt - 1;
4330c2f2 1159
cd0ff491 1160 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1161 jme_set_clean_rxdesc(jme, j);
b3821cc5 1162 j = (j + 1) & (mask);
4330c2f2 1163 }
3bf61c55 1164
cd0ff491 1165 } else {
42b1055e 1166 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1167 }
4330c2f2 1168
b3821cc5 1169 i = (i + desccnt) & (mask);
3bf61c55 1170 }
4330c2f2 1171
3bf61c55 1172out:
cdcdc9eb 1173 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1174
192570e0
GFT		 1175out_inc:
1176 atomic_inc(&jme->rx_cleaning);
1177
3bf61c55 1178 return limit > 0 ? limit : 0;
4330c2f2 1179
3bf61c55 1180}
d7699f87 1181
79ce639c
GFT		 1182static void
1183jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1184{
cd0ff491 1185 if (likely(atmp == dpi->cur)) {
192570e0 1186 dpi->cnt = 0;
79ce639c 1187 return;
192570e0 1188 }
79ce639c 1189
cd0ff491 1190 if (dpi->attempt == atmp) {
79ce639c 1191 ++(dpi->cnt);
cd0ff491 1192 } else {
79ce639c
GFT		 1193 dpi->attempt = atmp;
1194 dpi->cnt = 0;
1195 }
1196
1197}
1198
1199static void
1200jme_dynamic_pcc(struct jme_adapter *jme)
1201{
1202 register struct dynpcc_info *dpi = &(jme->dpi);
1203
cd0ff491 1204 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1205 jme_attempt_pcc(dpi, PCC_P3);
7ca9ebee
GFT		 1206 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1207 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT		 1208 jme_attempt_pcc(dpi, PCC_P2);
1209 else
1210 jme_attempt_pcc(dpi, PCC_P1);
1211
cd0ff491
GFT		 1212 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1213 if (dpi->attempt < dpi->cur)
1214 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1215 jme_set_rx_pcc(jme, dpi->attempt);
1216 dpi->cur = dpi->attempt;
1217 dpi->cnt = 0;
1218 }
1219}
1220
1221static void
1222jme_start_pcc_timer(struct jme_adapter *jme)
1223{
1224 struct dynpcc_info *dpi = &(jme->dpi);
1225 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1226 dpi->last_pkts = NET_STAT(jme).rx_packets;
1227 dpi->intr_cnt = 0;
1228 jwrite32(jme, JME_TMCSR,
1229 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1230}
1231
cd0ff491 1232static inline void
29bdd921
GFT		 1233jme_stop_pcc_timer(struct jme_adapter *jme)
1234{
1235 jwrite32(jme, JME_TMCSR, 0);
1236}
1237
cd0ff491
GFT		 1238static void
1239jme_shutdown_nic(struct jme_adapter *jme)
1240{
1241 u32 phylink;
1242
1243 phylink = jme_linkstat_from_phy(jme);
1244
1245 if (!(phylink & PHY_LINK_UP)) {
1246 /*
1247 * Disable all interrupt before issue timer
1248 */
1249 jme_stop_irq(jme);
1250 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1251 }
1252}
1253
79ce639c
GFT		 1254static void
1255jme_pcc_tasklet(unsigned long arg)
1256{
cd0ff491 1257 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1258 struct net_device *netdev = jme->dev;
1259
cd0ff491
GFT		 1260 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1261 jme_shutdown_nic(jme);
1262 return;
1263 }
29bdd921 1264
cd0ff491 1265 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1266 (atomic_read(&jme->link_changing) != 1)
1267 )) {
1268 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1269 return;
1270 }
29bdd921 1271
cd0ff491 1272 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1273 jme_dynamic_pcc(jme);
1274
79ce639c
GFT		 1275 jme_start_pcc_timer(jme);
1276}
1277
cd0ff491 1278static inline void
192570e0
GFT		 1279jme_polling_mode(struct jme_adapter *jme)
1280{
1281 jme_set_rx_pcc(jme, PCC_OFF);
1282}
1283
cd0ff491 1284static inline void
192570e0
GFT		 1285jme_interrupt_mode(struct jme_adapter *jme)
1286{
1287 jme_set_rx_pcc(jme, PCC_P1);
1288}
1289
cd0ff491
GFT		 1290static inline int
1291jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1292{
1293 u32 apmc;
1294 apmc = jread32(jme, JME_APMC);
1295 return apmc & JME_APMC_PSEUDO_HP_EN;
1296}
1297
1298static void
1299jme_start_shutdown_timer(struct jme_adapter *jme)
1300{
1301 u32 apmc;
1302
1303 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1304 apmc &= ~JME_APMC_EPIEN_CTRL;
1305 if (!no_extplug) {
1306 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1307 wmb();
1308 }
1309 jwrite32f(jme, JME_APMC, apmc);
1310
1311 jwrite32f(jme, JME_TIMER2, 0);
1312 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1313 jwrite32(jme, JME_TMCSR,
1314 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1315}
1316
1317static void
1318jme_stop_shutdown_timer(struct jme_adapter *jme)
1319{
1320 u32 apmc;
1321
1322 jwrite32f(jme, JME_TMCSR, 0);
1323 jwrite32f(jme, JME_TIMER2, 0);
1324 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1325
1326 apmc = jread32(jme, JME_APMC);
1327 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1328 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1329 wmb();
1330 jwrite32f(jme, JME_APMC, apmc);
1331}
1332
3bf61c55
GFT		 1333static void
1334jme_link_change_tasklet(unsigned long arg)
1335{
cd0ff491 1336 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1337 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1338 int rc;
1339
cd0ff491
GFT		 1340 while (!atomic_dec_and_test(&jme->link_changing)) {
1341 atomic_inc(&jme->link_changing);
937ef75a 1342 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
58c92f28 1343 while (atomic_read(&jme->link_changing) != 1)
937ef75a 1344 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1345 }
fcf45b4c 1346
cd0ff491 1347 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1348 goto out;
1349
29bdd921 1350 jme->old_mtu = netdev->mtu;
fcf45b4c 1351 netif_stop_queue(netdev);
cd0ff491
GFT		 1352 if (jme_pseudo_hotplug_enabled(jme))
1353 jme_stop_shutdown_timer(jme);
1354
1355 jme_stop_pcc_timer(jme);
1356 tasklet_disable(&jme->txclean_task);
1357 tasklet_disable(&jme->rxclean_task);
1358 tasklet_disable(&jme->rxempty_task);
1359
1360 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT		 1361 jme_disable_rx_engine(jme);
1362 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1363 jme_reset_mac_processor(jme);
1364 jme_free_rx_resources(jme);
1365 jme_free_tx_resources(jme);
192570e0 1366
cd0ff491 1367 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1368 jme_polling_mode(jme);
cd0ff491
GFT		 1369
1370 netif_carrier_off(netdev);
fcf45b4c
GFT		 1371 }
1372
1373 jme_check_link(netdev, 0);
cd0ff491 1374 if (netif_carrier_ok(netdev)) {
fcf45b4c 1375 rc = jme_setup_rx_resources(jme);
cd0ff491 1376 if (rc) {
937ef75a 1377 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1378 goto out_enable_tasklet;
fcf45b4c
GFT		 1379 }
1380
fcf45b4c 1381 rc = jme_setup_tx_resources(jme);
cd0ff491 1382 if (rc) {
937ef75a 1383 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT		 1384 goto err_out_free_rx_resources;
1385 }
1386
1387 jme_enable_rx_engine(jme);
1388 jme_enable_tx_engine(jme);
1389
1390 netif_start_queue(netdev);
192570e0 1391
cd0ff491 1392 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1393 jme_interrupt_mode(jme);
192570e0 1394
79ce639c 1395 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1396 } else if (jme_pseudo_hotplug_enabled(jme)) {
1397 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1398 }
1399
cd0ff491 1400 goto out_enable_tasklet;
fcf45b4c
GFT		 1401
1402err_out_free_rx_resources:
1403 jme_free_rx_resources(jme);
cd0ff491
GFT		 1404out_enable_tasklet:
1405 tasklet_enable(&jme->txclean_task);
1406 tasklet_hi_enable(&jme->rxclean_task);
1407 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1408out:
1409 atomic_inc(&jme->link_changing);
3bf61c55 1410}
d7699f87 1411
3bf61c55
GFT		 1412static void
1413jme_rx_clean_tasklet(unsigned long arg)
1414{
cd0ff491 1415 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1416 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1417
192570e0
GFT		 1418 jme_process_receive(jme, jme->rx_ring_size);
1419 ++(dpi->intr_cnt);
42b1055e 1420
192570e0 1421}
fcf45b4c 1422
192570e0 1423static int
cdcdc9eb 1424jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1425{
cdcdc9eb 1426 struct jme_adapter *jme = jme_napi_priv(holder);
3b70a6fa 1427 DECLARE_NETDEV
192570e0 1428 int rest;
fcf45b4c 1429
cdcdc9eb 1430 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1431
cd0ff491 1432 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1433 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1434 ++(NET_STAT(jme).rx_dropped);
1435 jme_restart_rx_engine(jme);
1436 }
1437 atomic_inc(&jme->rx_empty);
1438
cd0ff491 1439 if (rest) {
cdcdc9eb 1440 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1441 jme_interrupt_mode(jme);
1442 }
1443
cdcdc9eb
GFT		 1444 JME_NAPI_WEIGHT_SET(budget, rest);
1445 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1446}
1447
1448static void
1449jme_rx_empty_tasklet(unsigned long arg)
1450{
cd0ff491 1451 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1452
cd0ff491 1453 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1454 return;
1455
cd0ff491 1456 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1457 return;
1458
7ca9ebee 1459 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1460
fcf45b4c 1461 jme_rx_clean_tasklet(arg);
cdcdc9eb 1462
cd0ff491 1463 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1464 atomic_dec(&jme->rx_empty);
1465 ++(NET_STAT(jme).rx_dropped);
1466 jme_restart_rx_engine(jme);
1467 }
1468 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1469}
1470
b3821cc5
GFT		 1471static void
1472jme_wake_queue_if_stopped(struct jme_adapter *jme)
1473{
0ede469c 1474 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1475
1476 smp_wmb();
cd0ff491 1477 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1478 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
937ef75a 1479 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1480 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1481 }
1482
1483}
1484
3bf61c55
GFT		 1485static void
1486jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1487{
cd0ff491 1488 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1489 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1490 struct txdesc *txdesc = txring->desc;
3bf61c55 1491 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1492 int i, j, cnt = 0, max, err, mask;
3bf61c55 1493
937ef75a 1494 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT		 1495
1496 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1497 goto out;
1498
cd0ff491 1499 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1500 goto out;
1501
cd0ff491 1502 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1503 goto out;
1504
b3821cc5
GFT		 1505 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1506 mask = jme->tx_ring_mask;
3bf61c55 1507
cd0ff491 1508 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1509
1510 ctxbi = txbi + i;
1511
cd0ff491 1512 if (likely(ctxbi->skb &&
b3821cc5 1513 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1514
cd0ff491 1515 tx_dbg(jme, "txclean: %d+%d@%lu\n",
937ef75a 1516 i, ctxbi->nr_desc, jiffies);
3bf61c55 1517
cd0ff491 1518 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1519
cd0ff491 1520 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1521 ttxbi = txbi + ((i + j) & (mask));
1522 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1523
b3821cc5 1524 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1525 ttxbi->mapping,
1526 ttxbi->len,
1527 PCI_DMA_TODEVICE);
1528
3bf61c55
GFT		 1529 ttxbi->mapping = 0;
1530 ttxbi->len = 0;
1531 }
1532
1533 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1534
1535 cnt += ctxbi->nr_desc;
1536
cd0ff491 1537 if (unlikely(err)) {
8c198884 1538 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1539 } else {
8c198884 1540 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1541 NET_STAT(jme).tx_bytes += ctxbi->len;
1542 }
1543
1544 ctxbi->skb = NULL;
1545 ctxbi->len = 0;
cdcdc9eb 1546 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1547
1548 } else {
3bf61c55
GFT		 1549 break;
1550 }
1551
b3821cc5 1552 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1553
1554 ctxbi->nr_desc = 0;
d7699f87
GFT		 1555 }
1556
937ef75a 1557 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1558 atomic_set(&txring->next_to_clean, i);
79ce639c 1559 atomic_add(cnt, &txring->nr_free);
3bf61c55 1560
b3821cc5
GFT		 1561 jme_wake_queue_if_stopped(jme);
1562
fcf45b4c
GFT		 1563out:
1564 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1565}
1566
79ce639c 1567static void
cd0ff491 1568jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1569{
3bf61c55
GFT		 1570 /*
1571 * Disable interrupt
1572 */
1573 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1574
cd0ff491 1575 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1576 /*
1577 * Link change event is critical
1578 * all other events are ignored
1579 */
1580 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1581 tasklet_schedule(&jme->linkch_task);
29bdd921 1582 goto out_reenable;
fcf45b4c 1583 }
d7699f87 1584
cd0ff491 1585 if (intrstat & INTR_TMINTR) {
47220951 1586 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1587 tasklet_schedule(&jme->pcc_task);
47220951 1588 }
79ce639c 1589
cd0ff491 1590 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1591 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1592 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1593 }
1594
cd0ff491 1595 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1596 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1597 INTR_PCCRX0 |
1598 INTR_RX0EMP)) |
1599 INTR_RX0);
1600 }
d7699f87 1601
cd0ff491
GFT		 1602 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1603 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1604 atomic_inc(&jme->rx_empty);
1605
cd0ff491
GFT		 1606 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1607 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1608 jme_polling_mode(jme);
cdcdc9eb 1609 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1610 }
1611 }
cd0ff491
GFT		 1612 } else {
1613 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1614 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1615 tasklet_hi_schedule(&jme->rxempty_task);
1616 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1617 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1618 }
4330c2f2 1619 }
d7699f87 1620
29bdd921 1621out_reenable:
3bf61c55 1622 /*
fcf45b4c 1623 * Re-enable interrupt
3bf61c55 1624 */
fcf45b4c 1625 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1626}
1627
3b70a6fa
GFT		 1628#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1629static irqreturn_t
1630jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1631#else
79ce639c
GFT		 1632static irqreturn_t
1633jme_intr(int irq, void *dev_id)
3b70a6fa 1634#endif
79ce639c 1635{
cd0ff491
GFT		 1636 struct net_device *netdev = dev_id;
1637 struct jme_adapter *jme = netdev_priv(netdev);
1638 u32 intrstat;
79ce639c
GFT		 1639
1640 intrstat = jread32(jme, JME_IEVE);
1641
1642 /*
1643 * Check if it's really an interrupt for us
1644 */
7ee473a3 1645 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1646 return IRQ_NONE;
79ce639c
GFT		 1647
1648 /*
1649 * Check if the device still exist
1650 */
cd0ff491
GFT		 1651 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1652 return IRQ_NONE;
79ce639c
GFT		 1653
1654 jme_intr_msi(jme, intrstat);
1655
cd0ff491 1656 return IRQ_HANDLED;
d7699f87
GFT		 1657}
1658
3b70a6fa
GFT		 1659#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1660static irqreturn_t
1661jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1662#else
79ce639c
GFT		 1663static irqreturn_t
1664jme_msi(int irq, void *dev_id)
3b70a6fa 1665#endif
79ce639c 1666{
cd0ff491
GFT		 1667 struct net_device *netdev = dev_id;
1668 struct jme_adapter *jme = netdev_priv(netdev);
1669 u32 intrstat;
79ce639c 1670
0ede469c 1671 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1672
1673 jme_intr_msi(jme, intrstat);
1674
cd0ff491 1675 return IRQ_HANDLED;
79ce639c
GFT		 1676}
1677
79ce639c
GFT		 1678static void
1679jme_reset_link(struct jme_adapter *jme)
1680{
1681 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1682}
1683
fcf45b4c
GFT		 1684static void
1685jme_restart_an(struct jme_adapter *jme)
1686{
cd0ff491 1687 u32 bmcr;
fcf45b4c 1688
cd0ff491 1689 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1690 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1691 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1692 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1693 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1694}
1695
1696static int
1697jme_request_irq(struct jme_adapter *jme)
1698{
1699 int rc;
cd0ff491 1700 struct net_device *netdev = jme->dev;
3b70a6fa
GFT		 1701#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1702 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1703 int irq_flags = SA_SHIRQ;
1704#else
cd0ff491
GFT		 1705 irq_handler_t handler = jme_intr;
1706 int irq_flags = IRQF_SHARED;
3b70a6fa 1707#endif
cd0ff491
GFT		 1708
1709 if (!pci_enable_msi(jme->pdev)) {
1710 set_bit(JME_FLAG_MSI, &jme->flags);
1711 handler = jme_msi;
1712 irq_flags = 0;
1713 }
1714
1715 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1716 netdev);
1717 if (rc) {
937ef75a
JP		 1718 netdev_err(netdev,
1719 "Unable to request %s interrupt (return: %d)\n",
1720 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1721 rc);
79ce639c 1722
cd0ff491
GFT		 1723 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1724 pci_disable_msi(jme->pdev);
1725 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1726 }
cd0ff491 1727 } else {
79ce639c
GFT		 1728 netdev->irq = jme->pdev->irq;
1729 }
1730
cd0ff491 1731 return rc;
79ce639c
GFT		 1732}
1733
1734static void
1735jme_free_irq(struct jme_adapter *jme)
1736{
cd0ff491
GFT		 1737 free_irq(jme->pdev->irq, jme->dev);
1738 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1739 pci_disable_msi(jme->pdev);
1740 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1741 jme->dev->irq = jme->pdev->irq;
cd0ff491 1742 }
fcf45b4c
GFT		 1743}
1744
ed457bcc
GFT		 1745static inline void
1746jme_new_phy_on(struct jme_adapter *jme)
1747{
1748 u32 reg;
1749
1750 reg = jread32(jme, JME_PHY_PWR);
1751 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1752 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1753 jwrite32(jme, JME_PHY_PWR, reg);
1754
1755 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1756 reg &= ~PE1_GPREG0_PBG;
1757 reg |= PE1_GPREG0_ENBG;
1758 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1759}
1760
1761static inline void
1762jme_new_phy_off(struct jme_adapter *jme)
1763{
1764 u32 reg;
1765
1766 reg = jread32(jme, JME_PHY_PWR);
1767 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1768 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1769 jwrite32(jme, JME_PHY_PWR, reg);
1770
1771 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1772 reg &= ~PE1_GPREG0_PBG;
1773 reg |= PE1_GPREG0_PDD3COLD;
1774 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1775}
1776
e58b908e
GFT		 1777static inline void
1778jme_phy_on(struct jme_adapter *jme)
1779{
1780 u32 bmcr;
1781
1782 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1783 bmcr &= ~BMCR_PDOWN;
1784 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
ed457bcc
GFT		 1785
1786 if (new_phy_power_ctrl(jme->chip_main_rev))
1787 jme_new_phy_on(jme);
1788}
1789
1790static inline void
1791jme_phy_off(struct jme_adapter *jme)
1792{
1793 u32 bmcr;
1794
1795 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1796 bmcr |= BMCR_PDOWN;
1797 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1798
1799 if (new_phy_power_ctrl(jme->chip_main_rev))
1800 jme_new_phy_off(jme);
e58b908e
GFT		 1801}
1802
3bf61c55
GFT		 1803static int
1804jme_open(struct net_device *netdev)
d7699f87
GFT		 1805{
1806 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1807 int rc;
79ce639c 1808
42b1055e 1809 jme_clear_pm(jme);
cdcdc9eb 1810 JME_NAPI_ENABLE(jme);
d7699f87 1811
0ede469c 1812 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1813 tasklet_enable(&jme->txclean_task);
1814 tasklet_hi_enable(&jme->rxclean_task);
1815 tasklet_hi_enable(&jme->rxempty_task);
1816
79ce639c 1817 rc = jme_request_irq(jme);
cd0ff491 1818 if (rc)
4330c2f2 1819 goto err_out;
79ce639c 1820
d7699f87 1821 jme_start_irq(jme);
42b1055e 1822
ed457bcc
GFT		 1823 jme_phy_on(jme);
1824 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1825 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 1826 else
42b1055e
GFT		 1827 jme_reset_phy_processor(jme);
1828
29bdd921 1829 jme_reset_link(jme);
d7699f87
GFT		 1830
1831 return 0;
1832
d7699f87
GFT		 1833err_out:
1834 netif_stop_queue(netdev);
1835 netif_carrier_off(netdev);
4330c2f2 1836 return rc;
d7699f87
GFT		 1837}
1838
42b1055e
GFT		 1839static void
1840jme_set_100m_half(struct jme_adapter *jme)
1841{
cd0ff491 1842 u32 bmcr, tmp;
42b1055e 1843
a82e368c 1844 jme_phy_on(jme);
42b1055e
GFT		 1845 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1846 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1847 BMCR_SPEED1000 | BMCR_FULLDPLX);
1848 tmp |= BMCR_SPEED100;
1849
1850 if (bmcr != tmp)
1851 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1852
cd0ff491 1853 if (jme->fpgaver)
cdcdc9eb
GFT		 1854 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1855 else
1856 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1857}
1858
47220951
GFT		 1859#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1860static void
1861jme_wait_link(struct jme_adapter *jme)
1862{
cd0ff491 1863 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1864
1865 mdelay(1000);
1866 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1867 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1868 mdelay(10);
1869 phylink = jme_linkstat_from_phy(jme);
1870 }
1871}
1872
a82e368c
GFT		 1873static void
1874jme_powersave_phy(struct jme_adapter *jme)
1875{
1876 if (jme->reg_pmcs) {
1877 jme_set_100m_half(jme);
a82e368c
GFT		 1878 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1879 jme_wait_link(jme);
61891ee4 1880 jme_clear_pm(jme);
a82e368c
GFT		 1881 } else {
1882 jme_phy_off(jme);
1883 }
1884}
1885
3bf61c55
GFT		 1886static int
1887jme_close(struct net_device *netdev)
d7699f87
GFT		 1888{
1889 struct jme_adapter *jme = netdev_priv(netdev);
1890
1891 netif_stop_queue(netdev);
1892 netif_carrier_off(netdev);
1893
1894 jme_stop_irq(jme);
79ce639c 1895 jme_free_irq(jme);
d7699f87 1896
cdcdc9eb 1897 JME_NAPI_DISABLE(jme);
192570e0 1898
0ede469c
GFT		 1899 tasklet_disable(&jme->linkch_task);
1900 tasklet_disable(&jme->txclean_task);
1901 tasklet_disable(&jme->rxclean_task);
1902 tasklet_disable(&jme->rxempty_task);
8c198884 1903
cd0ff491
GFT		 1904 jme_disable_rx_engine(jme);
1905 jme_disable_tx_engine(jme);
8c198884 1906 jme_reset_mac_processor(jme);
d7699f87
GFT		 1907 jme_free_rx_resources(jme);
1908 jme_free_tx_resources(jme);
42b1055e 1909 jme->phylink = 0;
b3821cc5
GFT		 1910 jme_phy_off(jme);
1911
1912 return 0;
1913}
1914
1915static int
1916jme_alloc_txdesc(struct jme_adapter *jme,
1917 struct sk_buff *skb)
1918{
0ede469c 1919 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1920 int idx, nr_alloc, mask = jme->tx_ring_mask;
1921
1922 idx = txring->next_to_use;
1923 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1924
cd0ff491 1925 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 1926 return -1;
1927
1928 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1929
b3821cc5
GFT		 1930 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1931
1932 return idx;
1933}
1934
1935static void
1936jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1937 struct txdesc *txdesc,
b3821cc5
GFT		 1938 struct jme_buffer_info *txbi,
1939 struct page *page,
cd0ff491
GFT		 1940 u32 page_offset,
1941 u32 len,
1942 u8 hidma)
b3821cc5
GFT		 1943{
1944 dma_addr_t dmaaddr;
1945
1946 dmaaddr = pci_map_page(pdev,
1947 page,
1948 page_offset,
1949 len,
1950 PCI_DMA_TODEVICE);
1951
1952 pci_dma_sync_single_for_device(pdev,
1953 dmaaddr,
1954 len,
1955 PCI_DMA_TODEVICE);
1956
1957 txdesc->dw[0] = 0;
1958 txdesc->dw[1] = 0;
1959 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1960 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 1961 txdesc->desc2.datalen = cpu_to_le16(len);
1962 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1963 txdesc->desc2.bufaddrl = cpu_to_le32(
1964 (__u64)dmaaddr & 0xFFFFFFFFUL);
1965
1966 txbi->mapping = dmaaddr;
1967 txbi->len = len;
1968}
1969
1970static void
1971jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1972{
0ede469c 1973 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1974 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1975 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1976 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT		 1977 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1978 int mask = jme->tx_ring_mask;
1979 struct skb_frag_struct *frag;
cd0ff491 1980 u32 len;
b3821cc5 1981
cd0ff491
GFT		 1982 for (i = 0 ; i < nr_frags ; ++i) {
1983 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 1984 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1985 ctxbi = txbi + ((idx + i + 2) & (mask));
1986
1987 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1988 frag->page_offset, frag->size, hidma);
42b1055e 1989 }
b3821cc5 1990
cd0ff491 1991 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 1992 ctxdesc = txdesc + ((idx + 1) & (mask));
1993 ctxbi = txbi + ((idx + 1) & (mask));
1994 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1995 offset_in_page(skb->data), len, hidma);
1996
1997}
1998
1999static int
2000jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2001{
3b70a6fa 2002 if (unlikely(
0ede469c 2003#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 2004 skb_shinfo(skb)->tso_size
2005#else
2006 skb_shinfo(skb)->gso_size
2007#endif
2008 && skb_header_cloned(skb) &&
b3821cc5
GFT		 2009 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2010 dev_kfree_skb(skb);
2011 return -1;
2012 }
2013
2014 return 0;
2015}
2016
2017static int
3b70a6fa 2018jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 2019{
0ede469c 2020#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 2021 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2022#else
2023 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2024#endif
cd0ff491 2025 if (*mss) {
b3821cc5
GFT		 2026 *flags |= TXFLAG_LSEN;
2027
cd0ff491 2028 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 2029 struct iphdr *iph = ip_hdr(skb);
2030
2031 iph->check = 0;
cd0ff491 2032 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 2033 iph->daddr, 0,
2034 IPPROTO_TCP,
2035 0);
cd0ff491 2036 } else {
b3821cc5
GFT		 2037 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2038
cd0ff491 2039 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 2040 &ip6h->daddr, 0,
2041 IPPROTO_TCP,
2042 0);
2043 }
2044
2045 return 0;
2046 }
2047
2048 return 1;
2049}
2050
2051static void
cd0ff491 2052jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 2053{
3b70a6fa
GFT		 2054#ifdef CHECKSUM_PARTIAL
2055 if (skb->ip_summed == CHECKSUM_PARTIAL)
2056#else
2057 if (skb->ip_summed == CHECKSUM_HW)
2058#endif
2059 {
cd0ff491 2060 u8 ip_proto;
b3821cc5 2061
3b70a6fa
GFT		 2062#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2063 if (skb->protocol == htons(ETH_P_IP))
2064 ip_proto = ip_hdr(skb)->protocol;
2065 else if (skb->protocol == htons(ETH_P_IPV6))
2066 ip_proto = ipv6_hdr(skb)->nexthdr;
2067 else
2068 ip_proto = 0;
2069#else
b3821cc5 2070 switch (skb->protocol) {
cd0ff491 2071 case htons(ETH_P_IP):
b3821cc5
GFT		 2072 ip_proto = ip_hdr(skb)->protocol;
2073 break;
cd0ff491 2074 case htons(ETH_P_IPV6):
b3821cc5
GFT		 2075 ip_proto = ipv6_hdr(skb)->nexthdr;
2076 break;
2077 default:
2078 ip_proto = 0;
2079 break;
2080 }
3b70a6fa 2081#endif
b3821cc5 2082
cd0ff491 2083 switch (ip_proto) {
b3821cc5
GFT		 2084 case IPPROTO_TCP:
2085 *flags |= TXFLAG_TCPCS;
2086 break;
2087 case IPPROTO_UDP:
2088 *flags |= TXFLAG_UDPCS;
2089 break;
2090 default:
937ef75a 2091 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT		 2092 break;
2093 }
2094 }
2095}
2096
cd0ff491 2097static inline void
3b70a6fa 2098jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2099{
cd0ff491 2100 if (vlan_tx_tag_present(skb)) {
b3821cc5 2101 *flags |= TXFLAG_TAGON;
3b70a6fa 2102 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2103 }
b3821cc5
GFT		 2104}
2105
2106static int
3b70a6fa 2107jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2108{
0ede469c 2109 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2110 struct txdesc *txdesc;
b3821cc5 2111 struct jme_buffer_info *txbi;
cd0ff491 2112 u8 flags;
b3821cc5 2113
cd0ff491 2114 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 2115 txbi = txring->bufinf + idx;
2116
2117 txdesc->dw[0] = 0;
2118 txdesc->dw[1] = 0;
2119 txdesc->dw[2] = 0;
2120 txdesc->dw[3] = 0;
2121 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2122 /*
2123 * Set OWN bit at final.
2124 * When kernel transmit faster than NIC.
2125 * And NIC trying to send this descriptor before we tell
2126 * it to start sending this TX queue.
2127 * Other fields are already filled correctly.
2128 */
2129 wmb();
2130 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 2131 /*
2132 * Set checksum flags while not tso
2133 */
2134 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2135 jme_tx_csum(jme, skb, &flags);
b3821cc5 2136 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
3b70a6fa 2137 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 2138 txdesc->desc1.flags = flags;
2139 /*
2140 * Set tx buffer info after telling NIC to send
2141 * For better tx_clean timing
2142 */
2143 wmb();
2144 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2145 txbi->skb = skb;
2146 txbi->len = skb->len;
cd0ff491
GFT		 2147 txbi->start_xmit = jiffies;
2148 if (!txbi->start_xmit)
8d27293f 2149 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 2150
2151 return 0;
2152}
2153
b3821cc5
GFT		 2154static void
2155jme_stop_queue_if_full(struct jme_adapter *jme)
2156{
0ede469c 2157 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 2158 struct jme_buffer_info *txbi = txring->bufinf;
2159 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2160
cd0ff491 2161 txbi += idx;
b3821cc5
GFT		 2162
2163 smp_wmb();
cd0ff491 2164 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2165 netif_stop_queue(jme->dev);
937ef75a 2166 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2167 smp_wmb();
cd0ff491
GFT		 2168 if (atomic_read(&txring->nr_free)
2169 >= (jme->tx_wake_threshold)) {
b3821cc5 2170 netif_wake_queue(jme->dev);
937ef75a 2171 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT		 2172 }
2173 }
2174
cd0ff491 2175 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 2176 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2177 txbi->skb)) {
2178 netif_stop_queue(jme->dev);
e3b96dc9
GFT		 2179 netif_info(jme, tx_queued, jme->dev,
2180 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2181 }
b3821cc5
GFT		 2182}
2183
3bf61c55
GFT		 2184/*
2185 * This function is already protected by netif_tx_lock()
2186 */
cd0ff491 2187
7ca9ebee 2188#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
3bf61c55 2189static int
7ca9ebee
GFT		 2190#else
2191static netdev_tx_t
2192#endif
3bf61c55 2193jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2194{
cd0ff491 2195 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2196 int idx;
d7699f87 2197
cd0ff491 2198 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 2199 ++(NET_STAT(jme).tx_dropped);
2200 return NETDEV_TX_OK;
2201 }
2202
2203 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2204
cd0ff491 2205 if (unlikely(idx < 0)) {
b3821cc5 2206 netif_stop_queue(netdev);
937ef75a
JP		 2207 netif_err(jme, tx_err, jme->dev,
2208 "BUG! Tx ring full when queue awake!\n");
d7699f87 2209
cd0ff491 2210 return NETDEV_TX_BUSY;
b3821cc5
GFT		 2211 }
2212
3b70a6fa 2213 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2214
4330c2f2
GFT		 2215 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2216 TXCS_SELECT_QUEUE0 |
2217 TXCS_QUEUE0S |
2218 TXCS_ENABLE);
0ede469c 2219#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
d7699f87 2220 netdev->trans_start = jiffies;
0ede469c 2221#endif
d7699f87 2222
937ef75a
JP		 2223 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2224 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT		 2225 jme_stop_queue_if_full(jme);
2226
cd0ff491 2227 return NETDEV_TX_OK;
d7699f87
GFT		 2228}
2229
e523cd89
GFT		 2230static void
2231jme_set_unicastaddr(struct net_device *netdev)
2232{
2233 struct jme_adapter *jme = netdev_priv(netdev);
2234 u32 val;
2235
2236 val = (netdev->dev_addr[3] & 0xff) << 24 |
2237 (netdev->dev_addr[2] & 0xff) << 16 |
2238 (netdev->dev_addr[1] & 0xff) << 8 |
2239 (netdev->dev_addr[0] & 0xff);
2240 jwrite32(jme, JME_RXUMA_LO, val);
2241 val = (netdev->dev_addr[5] & 0xff) << 8 |
2242 (netdev->dev_addr[4] & 0xff);
2243 jwrite32(jme, JME_RXUMA_HI, val);
2244}
2245
3bf61c55
GFT		 2246static int
2247jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2248{
cd0ff491 2249 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2250 struct sockaddr *addr = p;
d7699f87 2251
cd0ff491 2252 if (netif_running(netdev))
d7699f87
GFT		 2253 return -EBUSY;
2254
cd0ff491 2255 spin_lock_bh(&jme->macaddr_lock);
d7699f87 2256 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
e523cd89 2257 jme_set_unicastaddr(netdev);
cd0ff491 2258 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 2259
2260 return 0;
2261}
2262
3bf61c55
GFT		 2263static void
2264jme_set_multi(struct net_device *netdev)
d7699f87 2265{
3bf61c55 2266 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2267 u32 mc_hash[2] = {};
7ca9ebee 2268#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
d7699f87 2269 int i;
7ca9ebee 2270#endif
d7699f87 2271
cd0ff491 2272 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2273
2274 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2275
cd0ff491 2276 if (netdev->flags & IFF_PROMISC) {
8c198884 2277 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2278 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2279 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2280 } else if (netdev->flags & IFF_MULTICAST) {
8e14c278 2281#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
3bf61c55 2282 struct dev_mc_list *mclist;
8e14c278
JP		 2283#else
2284 struct netdev_hw_addr *ha;
2285#endif
3bf61c55 2286 int bit_nr;
d7699f87 2287
8c198884 2288 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
7ca9ebee 2289#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
3bf61c55
GFT		 2290 for (i = 0, mclist = netdev->mc_list;
2291 mclist && i < netdev->mc_count;
2292 ++i, mclist = mclist->next) {
8e14c278 2293#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
7ca9ebee 2294 netdev_for_each_mc_addr(mclist, netdev) {
8e14c278
JP		 2295#else
2296 netdev_for_each_mc_addr(ha, netdev) {
7ca9ebee 2297#endif
8e14c278 2298#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
cd0ff491 2299 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
8e14c278
JP		 2300#else
2301 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2302#endif
cd0ff491
GFT		 2303 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2304 }
d7699f87 2305
4330c2f2
GFT		 2306 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2307 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2308 }
2309
d7699f87 2310 wmb();
8c198884
GFT		 2311 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2312
cd0ff491 2313 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2314}
2315
3bf61c55 2316static int
8c198884 2317jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2318{
cd0ff491 2319 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2320
cd0ff491 2321 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2322 return 0;
2323
cd0ff491
GFT		 2324 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2325 ((new_mtu) < IPV6_MIN_MTU))
2326 return -EINVAL;
79ce639c 2327
cd0ff491 2328 if (new_mtu > 4000) {
79ce639c
GFT		 2329 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2330 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2331 jme_restart_rx_engine(jme);
cd0ff491 2332 } else {
79ce639c
GFT		 2333 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2334 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2335 jme_restart_rx_engine(jme);
2336 }
2337
cd0ff491 2338 if (new_mtu > 1900) {
1a0b42f4
MM		 2339 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2340 NETIF_F_TSO | NETIF_F_TSO6);
cd0ff491
GFT		 2341 } else {
2342 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
1a0b42f4 2343 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491 2344 if (test_bit(JME_FLAG_TSO, &jme->flags))
1a0b42f4 2345 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT		 2346 }
2347
cd0ff491
GFT		 2348 netdev->mtu = new_mtu;
2349 jme_reset_link(jme);
79ce639c
GFT		 2350
2351 return 0;
d7699f87
GFT		 2352}
2353
8c198884
GFT		 2354static void
2355jme_tx_timeout(struct net_device *netdev)
2356{
cd0ff491 2357 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2358
cdcdc9eb
GFT		 2359 jme->phylink = 0;
2360 jme_reset_phy_processor(jme);
cd0ff491 2361 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2362 jme_set_settings(netdev, &jme->old_ecmd);
2363
8c198884 2364 /*
cdcdc9eb 2365 * Force to Reset the link again
8c198884 2366 */
29bdd921 2367 jme_reset_link(jme);
8c198884
GFT		 2368}
2369
1e5ebebc
GFT		 2370static inline void jme_pause_rx(struct jme_adapter *jme)
2371{
2372 atomic_dec(&jme->link_changing);
2373
2374 jme_set_rx_pcc(jme, PCC_OFF);
2375 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2376 JME_NAPI_DISABLE(jme);
2377 } else {
2378 tasklet_disable(&jme->rxclean_task);
2379 tasklet_disable(&jme->rxempty_task);
2380 }
2381}
2382
2383static inline void jme_resume_rx(struct jme_adapter *jme)
2384{
2385 struct dynpcc_info *dpi = &(jme->dpi);
2386
2387 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2388 JME_NAPI_ENABLE(jme);
2389 } else {
2390 tasklet_hi_enable(&jme->rxclean_task);
2391 tasklet_hi_enable(&jme->rxempty_task);
2392 }
2393 dpi->cur = PCC_P1;
2394 dpi->attempt = PCC_P1;
2395 dpi->cnt = 0;
2396 jme_set_rx_pcc(jme, PCC_P1);
2397
2398 atomic_inc(&jme->link_changing);
2399}
2400
42b1055e
GFT		 2401static void
2402jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2403{
2404 struct jme_adapter *jme = netdev_priv(netdev);
2405
1e5ebebc 2406 jme_pause_rx(jme);
42b1055e 2407 jme->vlgrp = grp;
1e5ebebc 2408 jme_resume_rx(jme);
42b1055e
GFT		 2409}
2410
7ca9ebee
GFT		 2411#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2412static void
2413jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2414{
2415 struct jme_adapter *jme = netdev_priv(netdev);
2416
7ca9ebee 2417 if(jme->vlgrp) {
1e5ebebc 2418 jme_pause_rx(jme);
7ca9ebee
GFT		 2419#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2420 jme->vlgrp->vlan_devices[vid] = NULL;
2421#else
2422 vlan_group_set_device(jme->vlgrp, vid, NULL);
2423#endif
1e5ebebc 2424 jme_resume_rx(jme);
7ca9ebee 2425 }
7ca9ebee
GFT		 2426}
2427#endif
2428
3bf61c55
GFT		 2429static void
2430jme_get_drvinfo(struct net_device *netdev,
2431 struct ethtool_drvinfo *info)
d7699f87 2432{
cd0ff491 2433 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2434
cd0ff491
GFT		 2435 strcpy(info->driver, DRV_NAME);
2436 strcpy(info->version, DRV_VERSION);
2437 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT		 2438}
2439
8c198884
GFT		 2440static int
2441jme_get_regs_len(struct net_device *netdev)
2442{
cd0ff491 2443 return JME_REG_LEN;
8c198884
GFT		 2444}
2445
2446static void
cd0ff491 2447mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2448{
2449 int i;
2450
cd0ff491 2451 for (i = 0 ; i < len ; i += 4)
79ce639c 2452 p[i >> 2] = jread32(jme, reg + i);
186fc259 2453}
8c198884 2454
186fc259 2455static void
cd0ff491 2456mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2457{
2458 int i;
cd0ff491 2459 u16 *p16 = (u16 *)p;
186fc259 2460
cd0ff491 2461 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2462 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2463}
2464
2465static void
2466jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2467{
cd0ff491
GFT		 2468 struct jme_adapter *jme = netdev_priv(netdev);
2469 u32 *p32 = (u32 *)p;
8c198884 2470
186fc259 2471 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2472
2473 regs->version = 1;
2474 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2475
2476 p32 += 0x100 >> 2;
2477 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2478
2479 p32 += 0x100 >> 2;
2480 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2481
2482 p32 += 0x100 >> 2;
2483 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2484
186fc259
GFT		 2485 p32 += 0x100 >> 2;
2486 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2487}
2488
2489static int
2490jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2491{
2492 struct jme_adapter *jme = netdev_priv(netdev);
2493
8c198884
GFT		 2494 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2495 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2496
cd0ff491 2497 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2498 ecmd->use_adaptive_rx_coalesce = false;
2499 ecmd->rx_coalesce_usecs = 0;
2500 ecmd->rx_max_coalesced_frames = 0;
2501 return 0;
2502 }
2503
2504 ecmd->use_adaptive_rx_coalesce = true;
2505
cd0ff491 2506 switch (jme->dpi.cur) {
8c198884
GFT		 2507 case PCC_P1:
2508 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2509 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2510 break;
2511 case PCC_P2:
2512 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2513 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2514 break;
2515 case PCC_P3:
2516 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2517 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2518 break;
2519 default:
2520 break;
2521 }
2522
2523 return 0;
2524}
2525
192570e0
GFT		 2526static int
2527jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2528{
2529 struct jme_adapter *jme = netdev_priv(netdev);
2530 struct dynpcc_info *dpi = &(jme->dpi);
2531
cd0ff491 2532 if (netif_running(netdev))
cdcdc9eb
GFT		 2533 return -EBUSY;
2534
7ca9ebee
GFT		 2535 if (ecmd->use_adaptive_rx_coalesce &&
2536 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2537 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2538 jme->jme_rx = netif_rx;
2539 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT		 2540 dpi->cur = PCC_P1;
2541 dpi->attempt = PCC_P1;
2542 dpi->cnt = 0;
2543 jme_set_rx_pcc(jme, PCC_P1);
2544 jme_interrupt_mode(jme);
7ca9ebee
GFT		 2545 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2546 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2547 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2548 jme->jme_rx = netif_receive_skb;
2549 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT		 2550 jme_interrupt_mode(jme);
2551 }
2552
2553 return 0;
2554}
2555
8c198884
GFT		 2556static void
2557jme_get_pauseparam(struct net_device *netdev,
2558 struct ethtool_pauseparam *ecmd)
2559{
2560 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2561 u32 val;
8c198884
GFT		 2562
2563 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2564 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2565
cd0ff491
GFT		 2566 spin_lock_bh(&jme->phy_lock);
2567 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2568 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2569
2570 ecmd->autoneg =
2571 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2572}
2573
2574static int
2575jme_set_pauseparam(struct net_device *netdev,
2576 struct ethtool_pauseparam *ecmd)
2577{
2578 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2579 u32 val;
8c198884 2580
cd0ff491 2581 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2582 (ecmd->tx_pause != 0)) {
2583
cd0ff491 2584 if (ecmd->tx_pause)
8c198884
GFT		 2585 jme->reg_txpfc |= TXPFC_PF_EN;
2586 else
2587 jme->reg_txpfc &= ~TXPFC_PF_EN;
2588
2589 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2590 }
2591
cd0ff491
GFT		 2592 spin_lock_bh(&jme->rxmcs_lock);
2593 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2594 (ecmd->rx_pause != 0)) {
2595
cd0ff491 2596 if (ecmd->rx_pause)
8c198884
GFT		 2597 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2598 else
2599 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2600
2601 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2602 }
cd0ff491 2603 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2604
cd0ff491
GFT		 2605 spin_lock_bh(&jme->phy_lock);
2606 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2607 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2608 (ecmd->autoneg != 0)) {
2609
cd0ff491 2610 if (ecmd->autoneg)
8c198884
GFT		 2611 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2612 else
2613 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2614
b3821cc5
GFT		 2615 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2616 MII_ADVERTISE, val);
8c198884 2617 }
cd0ff491 2618 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2619
2620 return 0;
2621}
2622
29bdd921
GFT		 2623static void
2624jme_get_wol(struct net_device *netdev,
2625 struct ethtool_wolinfo *wol)
2626{
2627 struct jme_adapter *jme = netdev_priv(netdev);
2628
2629 wol->supported = WAKE_MAGIC | WAKE_PHY;
2630
2631 wol->wolopts = 0;
2632
cd0ff491 2633 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2634 wol->wolopts |= WAKE_PHY;
2635
cd0ff491 2636 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2637 wol->wolopts |= WAKE_MAGIC;
2638
2639}
2640
2641static int
2642jme_set_wol(struct net_device *netdev,
2643 struct ethtool_wolinfo *wol)
2644{
2645 struct jme_adapter *jme = netdev_priv(netdev);
2646
cd0ff491 2647 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2648 WAKE_UCAST |
2649 WAKE_MCAST |
2650 WAKE_BCAST |
2651 WAKE_ARP))
2652 return -EOPNOTSUPP;
2653
2654 jme->reg_pmcs = 0;
2655
cd0ff491 2656 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2657 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2658
cd0ff491 2659 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2660 jme->reg_pmcs |= PMCS_MFEN;
2661
cd0ff491 2662 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3d12cc1b
GFT		 2663#ifndef JME_NEW_PM_API
2664 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2665#endif
7370b85a 2666#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3d12cc1b 2667 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
7370b85a 2668#endif
e3b96dc9 2669
29bdd921
GFT		 2670 return 0;
2671}
b3821cc5 2672
3bf61c55
GFT		 2673static int
2674jme_get_settings(struct net_device *netdev,
2675 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2676{
2677 struct jme_adapter *jme = netdev_priv(netdev);
2678 int rc;
8c198884 2679
cd0ff491 2680 spin_lock_bh(&jme->phy_lock);
d7699f87 2681 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2682 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2683 return rc;
2684}
2685
3bf61c55
GFT		 2686static int
2687jme_set_settings(struct net_device *netdev,
2688 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2689{
2690 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2691 int rc, fdc = 0;
fcf45b4c 2692
8588b84b
DD		 2693 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2694 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2695 return -EINVAL;
2696
e6b41b51
GFT		 2697 /*
2698 * Check If user changed duplex only while force_media.
2699 * Hardware would not generate link change interrupt.
2700 */
cd0ff491 2701 if (jme->mii_if.force_media &&
79ce639c
GFT		 2702 ecmd->autoneg != AUTONEG_ENABLE &&
2703 (jme->mii_if.full_duplex != ecmd->duplex))
2704 fdc = 1;
2705
cd0ff491 2706 spin_lock_bh(&jme->phy_lock);
d7699f87 2707 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2708 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2709
cd0ff491 2710 if (!rc) {
e6b41b51
GFT		 2711 if (fdc)
2712 jme_reset_link(jme);
29bdd921 2713 jme->old_ecmd = *ecmd;
aa1e7189
GFT		 2714 set_bit(JME_FLAG_SSET, &jme->flags);
2715 }
2716
2717 return rc;
2718}
2719
2720static int
2721jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2722{
2723 int rc;
2724 struct jme_adapter *jme = netdev_priv(netdev);
2725 struct mii_ioctl_data *mii_data = if_mii(rq);
2726 unsigned int duplex_chg;
2727
2728 if (cmd == SIOCSMIIREG) {
2729 u16 val = mii_data->val_in;
2730 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2731 (val & BMCR_SPEED1000))
2732 return -EINVAL;
2733 }
2734
2735 spin_lock_bh(&jme->phy_lock);
2736 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2737 spin_unlock_bh(&jme->phy_lock);
2738
2739 if (!rc && (cmd == SIOCSMIIREG)) {
2740 if (duplex_chg)
2741 jme_reset_link(jme);
2742 jme_get_settings(netdev, &jme->old_ecmd);
2743 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2744 }
2745
d7699f87
GFT		 2746 return rc;
2747}
2748
cd0ff491 2749static u32
3bf61c55
GFT		 2750jme_get_link(struct net_device *netdev)
2751{
d7699f87
GFT		 2752 struct jme_adapter *jme = netdev_priv(netdev);
2753 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2754}
2755
8c198884 2756static u32
cd0ff491
GFT		 2757jme_get_msglevel(struct net_device *netdev)
2758{
2759 struct jme_adapter *jme = netdev_priv(netdev);
2760 return jme->msg_enable;
2761}
2762
2763static void
2764jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2765{
cd0ff491
GFT		 2766 struct jme_adapter *jme = netdev_priv(netdev);
2767 jme->msg_enable = value;
2768}
8c198884 2769
cd0ff491
GFT		 2770static u32
2771jme_get_rx_csum(struct net_device *netdev)
2772{
2773 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2774 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2775}
2776
2777static int
2778jme_set_rx_csum(struct net_device *netdev, u32 on)
2779{
cd0ff491 2780 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2781
cd0ff491
GFT		 2782 spin_lock_bh(&jme->rxmcs_lock);
2783 if (on)
8c198884
GFT		 2784 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2785 else
2786 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2787 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2788 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2789
2790 return 0;
2791}
2792
2793static int
2794jme_set_tx_csum(struct net_device *netdev, u32 on)
2795{
cd0ff491 2796 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2797
cd0ff491
GFT		 2798 if (on) {
2799 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2800 if (netdev->mtu <= 1900)
1a0b42f4
MM		 2801 netdev->features |=
2802 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491
GFT		 2803 } else {
2804 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
1a0b42f4
MM		 2805 netdev->features &=
2806 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
b3821cc5 2807 }
8c198884
GFT		 2808
2809 return 0;
2810}
2811
b3821cc5
GFT		 2812static int
2813jme_set_tso(struct net_device *netdev, u32 on)
2814{
cd0ff491 2815 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2816
cd0ff491
GFT		 2817 if (on) {
2818 set_bit(JME_FLAG_TSO, &jme->flags);
2819 if (netdev->mtu <= 1900)
1a0b42f4 2820 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT		 2821 } else {
2822 clear_bit(JME_FLAG_TSO, &jme->flags);
1a0b42f4 2823 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT		 2824 }
2825
cd0ff491 2826 return 0;
b3821cc5
GFT		 2827}
2828
8c198884
GFT		 2829static int
2830jme_nway_reset(struct net_device *netdev)
2831{
cd0ff491 2832 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2833 jme_restart_an(jme);
2834 return 0;
2835}
2836
cd0ff491 2837static u8
186fc259
GFT		 2838jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2839{
cd0ff491 2840 u32 val;
186fc259
GFT		 2841 int to;
2842
2843 val = jread32(jme, JME_SMBCSR);
2844 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2845 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2846 msleep(1);
2847 val = jread32(jme, JME_SMBCSR);
2848 }
cd0ff491 2849 if (!to) {
937ef75a 2850 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2851 return 0xFF;
2852 }
2853
2854 jwrite32(jme, JME_SMBINTF,
2855 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2856 SMBINTF_HWRWN_READ |
2857 SMBINTF_HWCMD);
2858
2859 val = jread32(jme, JME_SMBINTF);
2860 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2861 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2862 msleep(1);
2863 val = jread32(jme, JME_SMBINTF);
2864 }
cd0ff491 2865 if (!to) {
937ef75a 2866 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2867 return 0xFF;
2868 }
2869
2870 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2871}
2872
2873static void
cd0ff491 2874jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2875{
cd0ff491 2876 u32 val;
186fc259
GFT		 2877 int to;
2878
2879 val = jread32(jme, JME_SMBCSR);
2880 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2881 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2882 msleep(1);
2883 val = jread32(jme, JME_SMBCSR);
2884 }
cd0ff491 2885 if (!to) {
937ef75a 2886 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2887 return;
2888 }
2889
2890 jwrite32(jme, JME_SMBINTF,
2891 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2892 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2893 SMBINTF_HWRWN_WRITE |
2894 SMBINTF_HWCMD);
2895
2896 val = jread32(jme, JME_SMBINTF);
2897 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2898 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2899 msleep(1);
2900 val = jread32(jme, JME_SMBINTF);
2901 }
cd0ff491 2902 if (!to) {
937ef75a 2903 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2904 return;
2905 }
2906
2907 mdelay(2);
2908}
2909
2910static int
2911jme_get_eeprom_len(struct net_device *netdev)
2912{
cd0ff491
GFT		 2913 struct jme_adapter *jme = netdev_priv(netdev);
2914 u32 val;
186fc259 2915 val = jread32(jme, JME_SMBCSR);
cd0ff491 2916 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 2917}
2918
2919static int
2920jme_get_eeprom(struct net_device *netdev,
2921 struct ethtool_eeprom *eeprom, u8 *data)
2922{
cd0ff491 2923 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2924 int i, offset = eeprom->offset, len = eeprom->len;
2925
2926 /*
8d27293f 2927 * ethtool will check the boundary for us
186fc259
GFT		 2928 */
2929 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2930 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2931 data[i] = jme_smb_read(jme, i + offset);
2932
2933 return 0;
2934}
2935
2936static int
2937jme_set_eeprom(struct net_device *netdev,
2938 struct ethtool_eeprom *eeprom, u8 *data)
2939{
cd0ff491 2940 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2941 int i, offset = eeprom->offset, len = eeprom->len;
2942
2943 if (eeprom->magic != JME_EEPROM_MAGIC)
2944 return -EINVAL;
2945
2946 /*
8d27293f 2947 * ethtool will check the boundary for us
186fc259 2948 */
cd0ff491 2949 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2950 jme_smb_write(jme, i + offset, data[i]);
2951
2952 return 0;
2953}
2954
3b70a6fa
GFT		 2955#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2956static struct ethtool_ops jme_ethtool_ops = {
2957#else
d7699f87 2958static const struct ethtool_ops jme_ethtool_ops = {
3b70a6fa 2959#endif
cd0ff491 2960 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 2961 .get_regs_len = jme_get_regs_len,
2962 .get_regs = jme_get_regs,
2963 .get_coalesce = jme_get_coalesce,
192570e0 2964 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 2965 .get_pauseparam = jme_get_pauseparam,
2966 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 2967 .get_wol = jme_get_wol,
2968 .set_wol = jme_set_wol,
d7699f87
GFT		 2969 .get_settings = jme_get_settings,
2970 .set_settings = jme_set_settings,
2971 .get_link = jme_get_link,
cd0ff491
GFT		 2972 .get_msglevel = jme_get_msglevel,
2973 .set_msglevel = jme_set_msglevel,
8c198884
GFT		 2974 .get_rx_csum = jme_get_rx_csum,
2975 .set_rx_csum = jme_set_rx_csum,
2976 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT		 2977 .set_tso = jme_set_tso,
2978 .set_sg = ethtool_op_set_sg,
8c198884 2979 .nway_reset = jme_nway_reset,
186fc259
GFT		 2980 .get_eeprom_len = jme_get_eeprom_len,
2981 .get_eeprom = jme_get_eeprom,
2982 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 2983};
2984
3bf61c55
GFT		 2985static int
2986jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2987{
3b70a6fa 2988 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 2989#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2990 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2991#else
2992 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2993#endif
2994 )
2995#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2996 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2997#else
cd0ff491 2998 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
0ede469c 2999#endif
3bf61c55
GFT		 3000 return 1;
3001
3b70a6fa 3002 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 3003#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3004 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
3005#else
3006 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
3007#endif
3008 )
3009#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3010 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
3011#else
cd0ff491 3012 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
0ede469c 3013#endif
8c198884
GFT		 3014 return 1;
3015
0ede469c
GFT		 3016#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3017 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
3018 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3019#else
cd0ff491
GFT		 3020 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3021 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
0ede469c 3022#endif
3bf61c55
GFT		 3023 return 0;
3024
3025 return -1;
3026}
3027
cd0ff491 3028static inline void
cdcdc9eb
GFT		 3029jme_phy_init(struct jme_adapter *jme)
3030{
cd0ff491 3031 u16 reg26;
cdcdc9eb
GFT		 3032
3033 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3034 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3035}
3036
cd0ff491 3037static inline void
cdcdc9eb 3038jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 3039{
cd0ff491 3040 u32 chipmode;
cdcdc9eb
GFT		 3041
3042 chipmode = jread32(jme, JME_CHIPMODE);
3043
3044 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 3045 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
98ef18f1
GFT		 3046 jme->chip_main_rev = jme->chiprev & 0xF;
3047 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT		 3048}
3049
3b70a6fa
GFT		 3050#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3051static const struct net_device_ops jme_netdev_ops = {
3052 .ndo_open = jme_open,
3053 .ndo_stop = jme_close,
3054 .ndo_validate_addr = eth_validate_addr,
aa1e7189 3055 .ndo_do_ioctl = jme_ioctl,
3b70a6fa
GFT		 3056 .ndo_start_xmit = jme_start_xmit,
3057 .ndo_set_mac_address = jme_set_macaddr,
3058 .ndo_set_multicast_list = jme_set_multi,
3059 .ndo_change_mtu = jme_change_mtu,
3060 .ndo_tx_timeout = jme_tx_timeout,
3061 .ndo_vlan_rx_register = jme_vlan_rx_register,
3062};
3063#endif
3064
3bf61c55
GFT		 3065static int __devinit
3066jme_init_one(struct pci_dev *pdev,
3067 const struct pci_device_id *ent)
3068{
cdcdc9eb 3069 int rc = 0, using_dac, i;
d7699f87
GFT		 3070 struct net_device *netdev;
3071 struct jme_adapter *jme;
cd0ff491
GFT		 3072 u16 bmcr, bmsr;
3073 u32 apmc;
d7699f87
GFT		 3074
3075 /*
3076 * set up PCI device basics
3077 */
4330c2f2 3078 rc = pci_enable_device(pdev);
cd0ff491 3079 if (rc) {
937ef75a 3080 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT		 3081 goto err_out;
3082 }
d7699f87 3083
3bf61c55 3084 using_dac = jme_pci_dma64(pdev);
cd0ff491 3085 if (using_dac < 0) {
937ef75a 3086 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT		 3087 rc = -EIO;
3088 goto err_out_disable_pdev;
3089 }
3090
cd0ff491 3091 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
937ef75a 3092 pr_err("No PCI resource region found\n");
4330c2f2
GFT		 3093 rc = -ENOMEM;
3094 goto err_out_disable_pdev;
3095 }
d7699f87 3096
4330c2f2 3097 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 3098 if (rc) {
937ef75a 3099 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT		 3100 goto err_out_disable_pdev;
3101 }
d7699f87
GFT		 3102
3103 pci_set_master(pdev);
3104
3105 /*
3106 * alloc and init net device
3107 */
3bf61c55 3108 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 3109 if (!netdev) {
937ef75a 3110 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT		 3111 rc = -ENOMEM;
3112 goto err_out_release_regions;
d7699f87 3113 }
3b70a6fa
GFT		 3114#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3115 netdev->netdev_ops = &jme_netdev_ops;
3116#else
d7699f87
GFT		 3117 netdev->open = jme_open;
3118 netdev->stop = jme_close;
aa1e7189 3119 netdev->do_ioctl = jme_ioctl;
d7699f87 3120 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT		 3121 netdev->set_mac_address = jme_set_macaddr;
3122 netdev->set_multicast_list = jme_set_multi;
3123 netdev->change_mtu = jme_change_mtu;
8c198884 3124 netdev->tx_timeout = jme_tx_timeout;
42b1055e 3125 netdev->vlan_rx_register = jme_vlan_rx_register;
7ca9ebee
GFT		 3126#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3127 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3128#endif
3bf61c55 3129 NETDEV_GET_STATS(netdev, &jme_get_stats);
3b70a6fa
GFT		 3130#endif
3131 netdev->ethtool_ops = &jme_ethtool_ops;
3132 netdev->watchdog_timeo = TX_TIMEOUT;
1a0b42f4
MM		 3133 netdev->features = NETIF_F_IP_CSUM |
3134 NETIF_F_IPV6_CSUM |
b3821cc5
GFT		 3135 NETIF_F_SG |
3136 NETIF_F_TSO |
3137 NETIF_F_TSO6 |
42b1055e
GFT		 3138 NETIF_F_HW_VLAN_TX |
3139 NETIF_F_HW_VLAN_RX;
cd0ff491 3140 if (using_dac)
8c198884 3141 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 3142
3143 SET_NETDEV_DEV(netdev, &pdev->dev);
3144 pci_set_drvdata(pdev, netdev);
3145
3146 /*
3147 * init adapter info
3148 */
3149 jme = netdev_priv(netdev);
3150 jme->pdev = pdev;
3151 jme->dev = netdev;
cdcdc9eb
GFT		 3152 jme->jme_rx = netif_rx;
3153 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 3154 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 3155 jme->phylink = 0;
b3821cc5 3156 jme->tx_ring_size = 1 << 10;
0ede469c 3157 jme->tx_ring_mask = jme->tx_ring_size - 1;
b3821cc5
GFT		 3158 jme->tx_wake_threshold = 1 << 9;
3159 jme->rx_ring_size = 1 << 9;
3160 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 3161 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 3162 jme->regs = ioremap(pci_resource_start(pdev, 0),
3163 pci_resource_len(pdev, 0));
4330c2f2 3164 if (!(jme->regs)) {
937ef75a 3165 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT		 3166 rc = -ENOMEM;
3167 goto err_out_free_netdev;
3168 }
4330c2f2 3169
cd0ff491
GFT		 3170 if (no_pseudohp) {
3171 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3172 jwrite32(jme, JME_APMC, apmc);
3173 } else if (force_pseudohp) {
3174 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3175 jwrite32(jme, JME_APMC, apmc);
3176 }
3177
cdcdc9eb 3178 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 3179
d7699f87 3180 spin_lock_init(&jme->phy_lock);
fcf45b4c 3181 spin_lock_init(&jme->macaddr_lock);
8c198884 3182 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 3183
fcf45b4c
GFT		 3184 atomic_set(&jme->link_changing, 1);
3185 atomic_set(&jme->rx_cleaning, 1);
3186 atomic_set(&jme->tx_cleaning, 1);
192570e0 3187 atomic_set(&jme->rx_empty, 1);
fcf45b4c 3188
79ce639c 3189 tasklet_init(&jme->pcc_task,
7ca9ebee 3190 jme_pcc_tasklet,
79ce639c 3191 (unsigned long) jme);
4330c2f2 3192 tasklet_init(&jme->linkch_task,
7ca9ebee 3193 jme_link_change_tasklet,
4330c2f2
GFT		 3194 (unsigned long) jme);
3195 tasklet_init(&jme->txclean_task,
7ca9ebee 3196 jme_tx_clean_tasklet,
4330c2f2
GFT		 3197 (unsigned long) jme);
3198 tasklet_init(&jme->rxclean_task,
7ca9ebee 3199 jme_rx_clean_tasklet,
4330c2f2 3200 (unsigned long) jme);
fcf45b4c 3201 tasklet_init(&jme->rxempty_task,
7ca9ebee 3202 jme_rx_empty_tasklet,
fcf45b4c 3203 (unsigned long) jme);
0ede469c 3204 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 3205 tasklet_disable_nosync(&jme->txclean_task);
3206 tasklet_disable_nosync(&jme->rxclean_task);
3207 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 3208 jme->dpi.cur = PCC_P1;
3209
cd0ff491 3210 jme->reg_ghc = 0;
79ce639c 3211 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 3212 jme->reg_rxmcs = RXMCS_DEFAULT;
3213 jme->reg_txpfc = 0;
47220951 3214 jme->reg_pmcs = PMCS_MFEN;
dc4185bd 3215 jme->reg_gpreg1 = GPREG1_DEFAULT;
cd0ff491
GFT		 3216 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3217 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 3218
fcf45b4c
GFT		 3219 /*
3220 * Get Max Read Req Size from PCI Config Space
3221 */
cd0ff491
GFT		 3222 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3223 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3224 switch (jme->mrrs) {
3225 case MRRS_128B:
3226 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3227 break;
3228 case MRRS_256B:
3229 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3230 break;
3231 default:
3232 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3233 break;
cd54cf32 3234 }
fcf45b4c 3235
d7699f87 3236 /*
cdcdc9eb 3237 * Must check before reset_mac_processor
d7699f87 3238 */
cdcdc9eb
GFT		 3239 jme_check_hw_ver(jme);
3240 jme->mii_if.dev = netdev;
cd0ff491 3241 if (jme->fpgaver) {
cdcdc9eb 3242 jme->mii_if.phy_id = 0;
cd0ff491 3243 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 3244 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3245 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3246 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 3247 jme->mii_if.phy_id = i;
3248 break;
3249 }
3250 }
3251
cd0ff491 3252 if (!jme->mii_if.phy_id) {
cdcdc9eb 3253 rc = -EIO;
937ef75a
JP		 3254 pr_err("Can not find phy_id\n");
3255 goto err_out_unmap;
cdcdc9eb
GFT		 3256 }
3257
3258 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3259 } else {
cdcdc9eb
GFT		 3260 jme->mii_if.phy_id = 1;
3261 }
cd0ff491 3262 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 3263 jme->mii_if.supports_gmii = true;
3264 else
3265 jme->mii_if.supports_gmii = false;
aa1e7189
GFT		 3266 jme->mii_if.phy_id_mask = 0x1F;
3267 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT		 3268 jme->mii_if.mdio_read = jme_mdio_read;
3269 jme->mii_if.mdio_write = jme_mdio_write;
3270
61891ee4
GFT		 3271 jme_clear_pm(jme);
3272 pci_set_power_state(jme->pdev, PCI_D0);
3273#ifndef JME_NEW_PM_API
3274 jme_pci_wakeup_enable(jme, true);
3275#endif
3276#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
e3b96dc9 3277 device_set_wakeup_enable(&pdev->dev, true);
61891ee4
GFT		 3278#endif
3279
55d19799 3280 jme_set_phyfifo_5level(jme);
711edd99 3281#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
98ef18f1 3282 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
711edd99
SS		 3283#else
3284 jme->pcirev = pdev->revision;
3285#endif
cd0ff491 3286 if (!jme->fpgaver)
cdcdc9eb 3287 jme_phy_init(jme);
42b1055e 3288 jme_phy_off(jme);
cdcdc9eb
GFT		 3289
3290 /*
3291 * Reset MAC processor and reload EEPROM for MAC Address
3292 */
d7699f87 3293 jme_reset_mac_processor(jme);
4330c2f2 3294 rc = jme_reload_eeprom(jme);
cd0ff491 3295 if (rc) {
937ef75a 3296 pr_err("Reload eeprom for reading MAC Address error\n");
0ede469c 3297 goto err_out_unmap;
4330c2f2 3298 }
d7699f87
GFT		 3299 jme_load_macaddr(netdev);
3300
d7699f87
GFT		 3301 /*
3302 * Tell stack that we are not ready to work until open()
3303 */
3304 netif_carrier_off(netdev);
d7699f87 3305
4330c2f2 3306 rc = register_netdev(netdev);
cd0ff491 3307 if (rc) {
937ef75a 3308 pr_err("Cannot register net device\n");
0ede469c 3309 goto err_out_unmap;
4330c2f2 3310 }
d7699f87 3311
98ef18f1 3312 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
937ef75a 3313 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
7ca9ebee
GFT		 3314 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3315 "JMC250 Gigabit Ethernet" :
3316 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3317 "JMC260 Fast Ethernet" : "Unknown",
3318 (jme->fpgaver != 0) ? " (FPGA)" : "",
3319 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
98ef18f1 3320 jme->pcirev,
937ef75a
JP		 3321 netdev->dev_addr[0],
3322 netdev->dev_addr[1],
3323 netdev->dev_addr[2],
3324 netdev->dev_addr[3],
3325 netdev->dev_addr[4],
3326 netdev->dev_addr[5]);
d7699f87
GFT		 3327
3328 return 0;
3329
3330err_out_unmap:
3331 iounmap(jme->regs);
3332err_out_free_netdev:
3333 pci_set_drvdata(pdev, NULL);
3334 free_netdev(netdev);
4330c2f2
GFT		 3335err_out_release_regions:
3336 pci_release_regions(pdev);
d7699f87 3337err_out_disable_pdev:
cd0ff491 3338 pci_disable_device(pdev);
d7699f87 3339err_out:
4330c2f2 3340 return rc;
d7699f87
GFT		 3341}
3342
3bf61c55
GFT		 3343static void __devexit
3344jme_remove_one(struct pci_dev *pdev)
3345{
d7699f87
GFT		 3346 struct net_device *netdev = pci_get_drvdata(pdev);
3347 struct jme_adapter *jme = netdev_priv(netdev);
3348
3349 unregister_netdev(netdev);
3350 iounmap(jme->regs);
3351 pci_set_drvdata(pdev, NULL);
3352 free_netdev(netdev);
3353 pci_release_regions(pdev);
3354 pci_disable_device(pdev);
3355
3356}
3357
a82e368c
GFT		 3358static void
3359jme_shutdown(struct pci_dev *pdev)
3360{
3361 struct net_device *netdev = pci_get_drvdata(pdev);
3362 struct jme_adapter *jme = netdev_priv(netdev);
3363
61891ee4
GFT		 3364 jme_powersave_phy(jme);
3365#ifndef JME_NEW_PM_API
3366 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3367#endif
3d12cc1b 3368#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
61891ee4 3369 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
a82e368c
GFT		 3370#endif
3371}
3372
fda5634a
GFT		 3373#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3374 #ifdef CONFIG_PM
3375 #define JME_HAVE_PM
3376 #endif
3377#else
3378 #ifdef CONFIG_PM_SLEEP
3379 #define JME_HAVE_PM
3380 #endif
3381#endif
3382
3383#ifdef JME_HAVE_PM
29bdd921 3384static int
3d12cc1b 3385#ifdef JME_NEW_PM_API
7370b85a 3386jme_suspend(struct device *dev)
3d12cc1b
GFT		 3387#else
3388jme_suspend(struct pci_dev *pdev, pm_message_t state)
7370b85a 3389#endif
29bdd921 3390{
3d12cc1b 3391#ifdef JME_NEW_PM_API
7370b85a
RW		 3392 struct pci_dev *pdev = to_pci_dev(dev);
3393#endif
29bdd921
GFT		 3394 struct net_device *netdev = pci_get_drvdata(pdev);
3395 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 3396
3397 atomic_dec(&jme->link_changing);
3398
3399 netif_device_detach(netdev);
3400 netif_stop_queue(netdev);
3401 jme_stop_irq(jme);
29bdd921 3402
cd0ff491
GFT		 3403 tasklet_disable(&jme->txclean_task);
3404 tasklet_disable(&jme->rxclean_task);
3405 tasklet_disable(&jme->rxempty_task);
3406
cd0ff491
GFT		 3407 if (netif_carrier_ok(netdev)) {
3408 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 3409 jme_polling_mode(jme);
3410
29bdd921 3411 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 3412 jme_disable_rx_engine(jme);
3413 jme_disable_tx_engine(jme);
29bdd921
GFT		 3414 jme_reset_mac_processor(jme);
3415 jme_free_rx_resources(jme);
3416 jme_free_tx_resources(jme);
3417 netif_carrier_off(netdev);
3418 jme->phylink = 0;
3419 }
3420
cd0ff491
GFT		 3421 tasklet_enable(&jme->txclean_task);
3422 tasklet_hi_enable(&jme->rxclean_task);
3423 tasklet_hi_enable(&jme->rxempty_task);
29bdd921 3424
a82e368c 3425 jme_powersave_phy(jme);
3d12cc1b 3426#ifndef JME_NEW_PM_API
7370b85a 3427 pci_save_state(pdev);
61891ee4 3428 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
a82e368c 3429 pci_set_power_state(pdev, PCI_D3hot);
7370b85a 3430#endif
29bdd921
GFT		 3431
3432 return 0;
3433}
3434
3435static int
3d12cc1b 3436#ifdef JME_NEW_PM_API
7370b85a 3437jme_resume(struct device *dev)
3d12cc1b
GFT		 3438#else
3439jme_resume(struct pci_dev *pdev)
7370b85a 3440#endif
29bdd921 3441{
3d12cc1b 3442#ifdef JME_NEW_PM_API
7370b85a
RW		 3443 struct pci_dev *pdev = to_pci_dev(dev);
3444#endif
29bdd921
GFT		 3445 struct net_device *netdev = pci_get_drvdata(pdev);
3446 struct jme_adapter *jme = netdev_priv(netdev);
3447
3448 jme_clear_pm(jme);
3d12cc1b
GFT		 3449#ifndef JME_NEW_PM_API
3450 pci_set_power_state(pdev, PCI_D0);
29bdd921 3451 pci_restore_state(pdev);
7370b85a 3452#endif
29bdd921 3453
ed457bcc
GFT		 3454 jme_phy_on(jme);
3455 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3456 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 3457 else
29bdd921
GFT		 3458 jme_reset_phy_processor(jme);
3459
29bdd921
GFT		 3460 jme_start_irq(jme);
3461 netif_device_attach(netdev);
3462
3463 atomic_inc(&jme->link_changing);
3464
3465 jme_reset_link(jme);
3466
3467 return 0;
3468}
7370b85a 3469
e3b96dc9 3470#ifdef JME_NEW_PM_API
7370b85a
RW		 3471static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3472#define JME_PM_OPS (&jme_pm_ops)
3473#endif
3474
3475#else
3476
e3b96dc9 3477#ifdef JME_NEW_PM_API
7370b85a
RW		 3478#define JME_PM_OPS NULL
3479#endif
7ee473a3 3480#endif
29bdd921 3481
7ca9ebee 3482#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
d7699f87 3483static struct pci_device_id jme_pci_tbl[] = {
7ca9ebee
GFT		 3484#else
3485static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3486#endif
cd0ff491
GFT		 3487 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3488 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3489 { }
3490};
3491
3492static struct pci_driver jme_driver = {
cd0ff491
GFT		 3493 .name = DRV_NAME,
3494 .id_table = jme_pci_tbl,
3495 .probe = jme_init_one,
3496 .remove = __devexit_p(jme_remove_one),
a82e368c 3497 .shutdown = jme_shutdown,
e3b96dc9 3498#ifndef JME_NEW_PM_API
7370b85a
RW		 3499 .suspend = jme_suspend,
3500 .resume = jme_resume
3501#else
3502 .driver.pm = JME_PM_OPS,
3503#endif
d7699f87
GFT		 3504};
3505
3bf61c55
GFT		 3506static int __init
3507jme_init_module(void)
d7699f87 3508{
937ef75a 3509 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3510 return pci_register_driver(&jme_driver);
3511}
3512
3bf61c55
GFT		 3513static void __exit
3514jme_cleanup_module(void)
d7699f87
GFT		 3515{
3516 pci_unregister_driver(&jme_driver);
3517}
3518
3519module_init(jme_init_module);
3520module_exit(jme_cleanup_module);
3521
3bf61c55 3522MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3523MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3524MODULE_LICENSE("GPL");
3525MODULE_VERSION(DRV_VERSION);
3526MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3527
JMicron Ethernet Linux driver