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ixgbe: combine accesses to FCTRL register into ixgbe_set_rx_mode
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
b4617240 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
134MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
135 "per physical function");
136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
172 if (adapter->vfinfo)
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
285 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 printk(KERN_ERR "%-15s ", rname);
293 for (j = 0; j < 8; j++)
294 printk(KERN_CONT "%08x ", regs[i*8+j]);
295 printk(KERN_CONT "\n");
296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 printk(KERN_INFO "Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 printk(KERN_INFO " Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
351 tx_buffer_info =
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
353 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
359 }
360
361 /* Print TX Rings */
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
364
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
366
367 /* Transmit Descriptor Formats
368 *
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
376 */
377
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 printk(KERN_INFO "------------------------------------\n");
383 printk(KERN_INFO "T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
386
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
388 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
391 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i,
393 le64_to_cpu(u0->a),
394 le64_to_cpu(u0->b),
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
402 printk(KERN_CONT " NTC/U\n");
403 else if (i == tx_ring->next_to_use)
404 printk(KERN_CONT " NTU\n");
405 else if (i == tx_ring->next_to_clean)
406 printk(KERN_CONT " NTC\n");
407 else
408 printk(KERN_CONT "\n");
409
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
416 }
417 }
418
419 /* Print RX Rings Summary */
420rx_ring_summary:
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
422 printk(KERN_INFO "Queue [NTU] [NTC]\n");
423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
425 printk(KERN_INFO "%5d %5X %5X\n", n,
426 rx_ring->next_to_use, rx_ring->next_to_clean);
427 }
428
429 /* Print RX Rings */
430 if (!netif_msg_rx_status(adapter))
431 goto exit;
432
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
434
435 /* Advanced Receive Descriptor (Read) Format
436 * 63 1 0
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
442 *
443 *
444 * Advanced Receive Descriptor (Write-Back) Format
445 *
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
454 */
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 printk(KERN_INFO "------------------------------------\n");
460 printk(KERN_INFO "R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
466
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
474 printk(KERN_INFO "RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i,
476 le64_to_cpu(u0->a),
477 le64_to_cpu(u0->b),
478 rx_buffer_info->skb);
479 } else {
480 printk(KERN_INFO "R [0x%03X] %016llX "
481 "%016llX %016llX %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
486
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
492
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
500 ),
501 PAGE_SIZE/2, true);
502 }
503 }
504
505 if (i == rx_ring->next_to_use)
506 printk(KERN_CONT " NTU\n");
507 else if (i == rx_ring->next_to_clean)
508 printk(KERN_CONT " NTC\n");
509 else
510 printk(KERN_CONT "\n");
511
512 }
513 }
514
515exit:
516 return;
517}
518
5eba3699
AV		 519static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
520{
521 u32 ctrl_ext;
522
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 527}
528
529static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
530{
531 u32 ctrl_ext;
532
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 537}
9a799d71 538
e8e26350
PW		 539/*
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
545 *
546 */
547static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
548 u8 queue, u8 msix_vector)
9a799d71
AK		 549{
550 u32 ivar, index;
e8e26350
PW		 551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
555 if (direction == -1)
556 direction = 0;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
562 break;
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
565 /* other causes */
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
572 break;
573 } else {
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
581 break;
582 }
583 default:
584 break;
585 }
9a799d71
AK		 586}
587
fe49f04a
AD		 588static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
589 u64 qmask)
590{
591 u32 mask;
592
593 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
596 } else {
597 mask = (qmask & 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
599 mask = (qmask >> 32);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
601 }
602}
603
9a799d71 604static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 605 struct ixgbe_tx_buffer
606 *tx_buffer_info)
9a799d71 607{
e5a43549
AD		 608 if (tx_buffer_info->dma) {
609 if (tx_buffer_info->mapped_as_page)
1b507730 610 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 611 tx_buffer_info->dma,
612 tx_buffer_info->length,
1b507730 613 DMA_TO_DEVICE);
e5a43549 614 else
1b507730 615 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 616 tx_buffer_info->dma,
617 tx_buffer_info->length,
1b507730 618 DMA_TO_DEVICE);
e5a43549
AD		 619 tx_buffer_info->dma = 0;
620 }
9a799d71
AK		 621 if (tx_buffer_info->skb) {
622 dev_kfree_skb_any(tx_buffer_info->skb);
623 tx_buffer_info->skb = NULL;
624 }
44df32c5 625 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 626 /* tx_buffer_info must be completely set up in the transmit path */
627}
628
26f23d82 629/**
7483d9dd 630 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
633 *
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
636 *
7483d9dd 637 * Returns : true if in xon state (currently not paused)
26f23d82 638 */
7483d9dd 639static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
26f23d82
YZ		 640 struct ixgbe_ring *tx_ring)
641{
26f23d82
YZ		 642 u32 txoff = IXGBE_TFCS_TXOFF;
643
644#ifdef CONFIG_IXGBE_DCB
ca739481 645 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 646 int tc;
26f23d82
YZ		 647 int reg_idx = tx_ring->reg_idx;
648 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
649
6837e895
PW		 650 switch (adapter->hw.mac.type) {
651 case ixgbe_mac_82598EB:
26f23d82
YZ		 652 tc = reg_idx >> 2;
653 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 654 break;
655 case ixgbe_mac_82599EB:
26f23d82
YZ		 656 tc = 0;
657 txoff = IXGBE_TFCS_TXOFF;
658 if (dcb_i == 8) {
659 /* TC0, TC1 */
660 tc = reg_idx >> 5;
661 if (tc == 2) /* TC2, TC3 */
662 tc += (reg_idx - 64) >> 4;
663 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
664 tc += 1 + ((reg_idx - 96) >> 3);
665 } else if (dcb_i == 4) {
666 /* TC0, TC1 */
667 tc = reg_idx >> 6;
668 if (tc == 1) {
669 tc += (reg_idx - 64) >> 5;
670 if (tc == 2) /* TC2, TC3 */
671 tc += (reg_idx - 96) >> 4;
672 }
673 }
6837e895
PW		 674 break;
675 default:
676 tc = 0;
26f23d82
YZ		 677 }
678 txoff <<= tc;
679 }
680#endif
681 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
682}
683
9a799d71 684static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 685 struct ixgbe_ring *tx_ring,
686 unsigned int eop)
9a799d71 687{
e01c31a5 688 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 689
9a799d71 690 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 691 * check with the clearing of time_stamp and movement of eop */
9a799d71 692 adapter->detect_tx_hung = false;
44df32c5 693 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 694 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 695 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 696 /* detected Tx unit hang */
e01c31a5
JB		 697 union ixgbe_adv_tx_desc *tx_desc;
698 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
396e799c 699 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 700 " Tx Queue <%d>\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
706 " jiffies <%lx>\n",
707 tx_ring->queue_index,
708 IXGBE_READ_REG(hw, tx_ring->head),
709 IXGBE_READ_REG(hw, tx_ring->tail),
710 tx_ring->next_to_use, eop,
711 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 712 return true;
713 }
714
715 return false;
716}
717
b4617240
PW		 718#define IXGBE_MAX_TXD_PWR 14
719#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 720
721/* Tx Descriptors needed, worst case */
722#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 726
e01c31a5
JB		 727static void ixgbe_tx_timeout(struct net_device *netdev);
728
9a799d71
AK		 729/**
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 731 * @q_vector: structure containing interrupt and ring information
e01c31a5 732 * @tx_ring: tx ring to clean
9a799d71 733 **/
fe49f04a 734static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 735 struct ixgbe_ring *tx_ring)
9a799d71 736{
fe49f04a 737 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 738 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 739 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
740 struct ixgbe_tx_buffer *tx_buffer_info;
741 unsigned int i, eop, count = 0;
e01c31a5 742 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 743
744 i = tx_ring->next_to_clean;
12207e49
PWJ		 745 eop = tx_ring->tx_buffer_info[i].next_to_watch;
746 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
747
748 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 749 (count < tx_ring->work_limit)) {
12207e49 750 bool cleaned = false;
2d0bb1c1 751 rmb(); /* read buffer_info after eop_desc */
12207e49
PWJ		 752 for ( ; !cleaned; count++) {
753 struct sk_buff *skb;
9a799d71
AK		 754 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
755 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 756 cleaned = (i == eop);
e01c31a5 757 skb = tx_buffer_info->skb;
9a799d71 758
12207e49 759 if (cleaned && skb) {
e092be60 760 unsigned int segs, bytecount;
3d8fd385 761 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 762
763 /* gso_segs is currently only valid for tcp */
e092be60 764 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 765#ifdef IXGBE_FCOE
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
768 && (skb->protocol == htons(ETH_P_FCOE)) &&
769 skb_is_gso(skb)) {
770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
775 }
776#endif /* IXGBE_FCOE */
e092be60 777 /* multiply data chunks by size of headers */
3d8fd385 778 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 779 total_packets += segs;
780 total_bytes += bytecount;
e092be60 781 }
e01c31a5 782
9a799d71 783 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 784 tx_buffer_info);
9a799d71 785
12207e49
PWJ		 786 tx_desc->wb.status = 0;
787
9a799d71
AK		 788 i++;
789 if (i == tx_ring->count)
790 i = 0;
e01c31a5 791 }
12207e49
PWJ		 792
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
794 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
795 }
796
9a799d71
AK		 797 tx_ring->next_to_clean = i;
798
e092be60 799#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 800 if (unlikely(count && netif_carrier_ok(netdev) &&
801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
804 */
805 smp_mb();
30eba97a
AV		 806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 809 ++tx_ring->restart_queue;
30eba97a 810 }
e092be60 811 }
9a799d71 812
e01c31a5
JB		 813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
396e799c
ET		 816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
e01c31a5
JB		 818 ixgbe_tx_timeout(adapter->netdev);
819 }
820 }
9a799d71 821
e01c31a5 822 /* re-arm the interrupt */
fe49f04a
AD		 823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 825
e01c31a5
JB		 826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
e01c31a5 828 tx_ring->stats.packets += total_packets;
12207e49 829 tx_ring->stats.bytes += total_bytes;
9a1a69ad 830 return (count < tx_ring->work_limit);
9a799d71
AK		 831}
832
5dd2d332 833#ifdef CONFIG_IXGBE_DCA
bd0362dd 834static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 835 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 836{
837 u32 rxctrl;
838 int cpu = get_cpu();
4a0b9ca0 839 int q = rx_ring->reg_idx;
bd0362dd 840
3a581073 841 if (rx_ring->cpu != cpu) {
bd0362dd 842 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
844 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
845 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
846 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
847 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
848 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
850 }
bd0362dd
JC		 851 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
852 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 857 rx_ring->cpu = cpu;
bd0362dd
JC		 858 }
859 put_cpu();
860}
861
862static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 863 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 864{
865 u32 txctrl;
866 int cpu = get_cpu();
4a0b9ca0 867 int q = tx_ring->reg_idx;
ee5f784a 868 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 869
3a581073 870 if (tx_ring->cpu != cpu) {
e8e26350 871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 872 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 873 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
874 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 875 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 877 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 878 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 879 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
880 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
882 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 884 }
3a581073 885 tx_ring->cpu = cpu;
bd0362dd
JC		 886 }
887 put_cpu();
888}
889
890static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
891{
892 int i;
893
894 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
895 return;
896
e35ec126
AD		 897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
899
bd0362dd 900 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 901 adapter->tx_ring[i]->cpu = -1;
902 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 903 }
904 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 905 adapter->rx_ring[i]->cpu = -1;
906 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 907 }
908}
909
910static int __ixgbe_notify_dca(struct device *dev, void *data)
911{
912 struct net_device *netdev = dev_get_drvdata(dev);
913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
914 unsigned long event = *(unsigned long *)data;
915
916 switch (event) {
917 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 918 /* if we're already enabled, don't do it again */
919 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
920 break;
652f093f 921 if (dca_add_requester(dev) == 0) {
96b0e0f6 922 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 923 ixgbe_setup_dca(adapter);
924 break;
925 }
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE:
928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
929 dca_remove_requester(dev);
930 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
932 }
933 break;
934 }
935
652f093f 936 return 0;
bd0362dd
JC		 937}
938
5dd2d332 939#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 940/**
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
177db6ff
MC		 944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
9a799d71 947 **/
78b6f4ce 948static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 949 struct sk_buff *skb, u8 status,
fdaff1ce 950 struct ixgbe_ring *ring,
177db6ff 951 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 952{
78b6f4ce
HX		 953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 955 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
956 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 957
182ff8df 958 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 959 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 960 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 961 else
78b6f4ce 962 napi_gro_receive(napi, skb);
177db6ff 963 } else {
8a62babf 964 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 965 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
966 else
967 netif_rx(skb);
9a799d71
AK		 968 }
969}
970
e59bd25d
AV		 971/**
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
976 **/
9a799d71 977static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 978 union ixgbe_adv_rx_desc *rx_desc,
979 struct sk_buff *skb)
9a799d71 980{
8bae1b2b
DS		 981 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
982
9a799d71
AK		 983 skb->ip_summed = CHECKSUM_NONE;
984
712744be
JB		 985 /* Rx csum disabled */
986 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 987 return;
e59bd25d
AV		 988
989 /* if IP and error */
990 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
991 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 992 adapter->hw_csum_rx_error++;
993 return;
994 }
e59bd25d
AV		 995
996 if (!(status_err & IXGBE_RXD_STAT_L4CS))
997 return;
998
999 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1000 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002 /*
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1004 * checksum errors.
1005 */
1006 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008 return;
1009
e59bd25d
AV		 1010 adapter->hw_csum_rx_error++;
1011 return;
1012 }
1013
9a799d71 1014 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1015 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1016}
1017
e8e26350
PW		 1018static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019 struct ixgbe_ring *rx_ring, u32 val)
1020{
1021 /*
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1025 * such as IA-64).
1026 */
1027 wmb();
1028 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029}
1030
9a799d71
AK		 1031/**
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1034 **/
1035static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 1036 struct ixgbe_ring *rx_ring,
1037 int cleaned_count)
9a799d71 1038{
d716a7d8 1039 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1040 struct pci_dev *pdev = adapter->pdev;
1041 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1042 struct ixgbe_rx_buffer *bi;
9a799d71 1043 unsigned int i;
d716a7d8 1044 unsigned int bufsz = rx_ring->rx_buf_len;
9a799d71
AK		 1045
1046 i = rx_ring->next_to_use;
3a581073 1047 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1048
1049 while (cleaned_count--) {
1050 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1051
762f4c57 1052 if (!bi->page_dma &&
6e455b89 1053 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1054 if (!bi->page) {
d716a7d8 1055 bi->page = netdev_alloc_page(netdev);
762f4c57
JB		 1056 if (!bi->page) {
1057 adapter->alloc_rx_page_failed++;
1058 goto no_buffers;
1059 }
1060 bi->page_offset = 0;
1061 } else {
1062 /* use a half page if we're re-using */
1063 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1064 }
762f4c57 1065
1b507730 1066 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
762f4c57
JB		 1067 bi->page_offset,
1068 (PAGE_SIZE / 2),
1b507730 1069 DMA_FROM_DEVICE);
9a799d71
AK		 1070 }
1071
3a581073 1072 if (!bi->skb) {
d716a7d8
AD		 1073 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1074 bufsz);
1075 bi->skb = skb;
9a799d71
AK		 1076
1077 if (!skb) {
1078 adapter->alloc_rx_buff_failed++;
1079 goto no_buffers;
1080 }
d716a7d8
AD		 1081 /* initialize queue mapping */
1082 skb_record_rx_queue(skb, rx_ring->queue_index);
1083 }
9a799d71 1084
d716a7d8
AD		 1085 if (!bi->dma) {
1086 bi->dma = dma_map_single(&pdev->dev,
1087 bi->skb->data,
4f57ca6e 1088 rx_ring->rx_buf_len,
1b507730 1089 DMA_FROM_DEVICE);
9a799d71
AK		 1090 }
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
6e455b89 1093 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1096 } else {
3a581073 1097 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1098 }
1099
1100 i++;
1101 if (i == rx_ring->count)
1102 i = 0;
3a581073 1103 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1104 }
7c6e0a43 1105
9a799d71
AK		 1106no_buffers:
1107 if (rx_ring->next_to_use != i) {
1108 rx_ring->next_to_use = i;
1109 if (i-- == 0)
1110 i = (rx_ring->count - 1);
1111
e8e26350 1112 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1113 }
1114}
1115
7c6e0a43
JB		 1116static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117{
1118 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119}
1120
1121static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122{
1123 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124}
1125
f8212f97
AD		 1126static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127{
1128 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129 IXGBE_RXDADV_RSCCNT_MASK) >>
1130 IXGBE_RXDADV_RSCCNT_SHIFT;
1131}
1132
1133/**
1134 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135 * @skb: pointer to the last skb in the rsc queue
94b982b2 1136 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1137 *
1138 * This function changes a queue full of hw rsc buffers into a completed
1139 * packet. It uses the ->prev pointers to find the first packet and then
1140 * turns it into the frag list owner.
1141 **/
94b982b2
MC		 1142static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143 u64 *count)
f8212f97
AD		 1144{
1145 unsigned int frag_list_size = 0;
1146
1147 while (skb->prev) {
1148 struct sk_buff *prev = skb->prev;
1149 frag_list_size += skb->len;
1150 skb->prev = NULL;
1151 skb = prev;
94b982b2 1152 *count += 1;
f8212f97
AD		 1153 }
1154
1155 skb_shinfo(skb)->frag_list = skb->next;
1156 skb->next = NULL;
1157 skb->len += frag_list_size;
1158 skb->data_len += frag_list_size;
1159 skb->truesize += frag_list_size;
1160 return skb;
1161}
1162
43634e82
MC		 1163struct ixgbe_rsc_cb {
1164 dma_addr_t dma;
e8171aaa 1165 bool delay_unmap;
43634e82
MC		 1166};
1167
1168#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
78b6f4ce 1170static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 1171 struct ixgbe_ring *rx_ring,
1172 int *work_done, int work_to_do)
9a799d71 1173{
78b6f4ce 1174 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 1175 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1176 struct pci_dev *pdev = adapter->pdev;
1177 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179 struct sk_buff *skb;
f8212f97 1180 unsigned int i, rsc_count = 0;
7c6e0a43 1181 u32 len, staterr;
177db6ff
MC		 1182 u16 hdr_info;
1183 bool cleaned = false;
9a799d71 1184 int cleaned_count = 0;
d2f4fbe2 1185 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1186#ifdef IXGBE_FCOE
1187 int ddp_bytes = 0;
1188#endif /* IXGBE_FCOE */
9a799d71
AK		 1189
1190 i = rx_ring->next_to_clean;
9a799d71
AK		 1191 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1194
1195 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1196 u32 upper_len = 0;
9a799d71
AK		 1197 if (*work_done >= work_to_do)
1198 break;
1199 (*work_done)++;
1200
3c945e5b 1201 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1202 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1203 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1206 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1207 if ((len > IXGBE_RX_HDR_SIZE) ||
1208 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1210 } else {
9a799d71 1211 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1212 }
9a799d71
AK		 1213
1214 cleaned = true;
1215 skb = rx_buffer_info->skb;
7ca3bc58 1216 prefetch(skb->data);
9a799d71
AK		 1217 rx_buffer_info->skb = NULL;
1218
21fa4e66 1219 if (rx_buffer_info->dma) {
43634e82
MC		 1220 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1222 (!(skb->prev))) {
43634e82
MC		 1223 /*
1224 * When HWRSC is enabled, delay unmapping
1225 * of the first packet. It carries the
1226 * header information, HW may still
1227 * access the header after the writeback.
1228 * Only unmap it when EOP is reached
1229 */
e8171aaa 1230 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1231 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1232 } else {
1b507730 1233 dma_unmap_single(&pdev->dev,
e8171aaa 1234 rx_buffer_info->dma,
43634e82 1235 rx_ring->rx_buf_len,
e8171aaa
MC		 1236 DMA_FROM_DEVICE);
1237 }
4f57ca6e 1238 rx_buffer_info->dma = 0;
9a799d71
AK		 1239 skb_put(skb, len);
1240 }
1241
1242 if (upper_len) {
1b507730
NN		 1243 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1245 rx_buffer_info->page_dma = 0;
1246 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 1247 rx_buffer_info->page,
1248 rx_buffer_info->page_offset,
1249 upper_len);
1250
1251 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252 (page_count(rx_buffer_info->page) != 1))
1253 rx_buffer_info->page = NULL;
1254 else
1255 get_page(rx_buffer_info->page);
9a799d71
AK		 1256
1257 skb->len += upper_len;
1258 skb->data_len += upper_len;
1259 skb->truesize += upper_len;
1260 }
1261
1262 i++;
1263 if (i == rx_ring->count)
1264 i = 0;
9a799d71
AK		 1265
1266 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267 prefetch(next_rxd);
9a799d71 1268 cleaned_count++;
f8212f97 1269
0c19d6af 1270 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1271 rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273 if (rsc_count) {
1274 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275 IXGBE_RXDADV_NEXTP_SHIFT;
1276 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1277 } else {
1278 next_buffer = &rx_ring->rx_buffer_info[i];
1279 }
1280
9a799d71 1281 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1282 if (skb->prev)
94b982b2
MC		 1283 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1285 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1286 dma_unmap_single(&pdev->dev,
1287 IXGBE_RSC_CB(skb)->dma,
43634e82 1288 rx_ring->rx_buf_len,
1b507730 1289 DMA_FROM_DEVICE);
fd3686a8 1290 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1291 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1292 }
94b982b2
MC		 1293 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295 else
1296 rx_ring->rsc_count++;
1297 rx_ring->rsc_flush++;
1298 }
9a799d71
AK		 1299 rx_ring->stats.packets++;
1300 rx_ring->stats.bytes += skb->len;
1301 } else {
6e455b89 1302 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1303 rx_buffer_info->skb = next_buffer->skb;
1304 rx_buffer_info->dma = next_buffer->dma;
1305 next_buffer->skb = skb;
1306 next_buffer->dma = 0;
1307 } else {
1308 skb->next = next_buffer->skb;
1309 skb->next->prev = skb;
1310 }
7ca3bc58 1311 rx_ring->non_eop_descs++;
9a799d71
AK		 1312 goto next_desc;
1313 }
1314
1315 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316 dev_kfree_skb_irq(skb);
1317 goto next_desc;
1318 }
1319
8bae1b2b 1320 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1321
1322 /* probably a little skewed due to removing CRC */
1323 total_rx_bytes += skb->len;
1324 total_rx_packets++;
1325
74ce8dd2 1326 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1327#ifdef IXGBE_FCOE
1328 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1329 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331 if (!ddp_bytes)
332d4a7d 1332 goto next_desc;
3d8fd385 1333 }
332d4a7d 1334#endif /* IXGBE_FCOE */
fdaff1ce 1335 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1336
1337next_desc:
1338 rx_desc->wb.upper.status_error = 0;
1339
1340 /* return some buffers to hardware, one at a time is too slow */
1341 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343 cleaned_count = 0;
1344 }
1345
1346 /* use prefetched values */
1347 rx_desc = next_rxd;
f8212f97 1348 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1349
1350 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1351 }
1352
9a799d71
AK		 1353 rx_ring->next_to_clean = i;
1354 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356 if (cleaned_count)
1357 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
3d8fd385
YZ		 1359#ifdef IXGBE_FCOE
1360 /* include DDPed FCoE data */
1361 if (ddp_bytes > 0) {
1362 unsigned int mss;
1363
1364 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365 sizeof(struct fc_frame_header) -
1366 sizeof(struct fcoe_crc_eof);
1367 if (mss > 512)
1368 mss &= ~511;
1369 total_rx_bytes += ddp_bytes;
1370 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371 }
1372#endif /* IXGBE_FCOE */
1373
f494e8fa
AV		 1374 rx_ring->total_packets += total_rx_packets;
1375 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1376 netdev->stats.rx_bytes += total_rx_bytes;
1377 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1378
9a799d71
AK		 1379 return cleaned;
1380}
1381
021230d4 1382static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1383/**
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1386 *
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388 * interrupts.
1389 **/
1390static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391{
021230d4
AV		 1392 struct ixgbe_q_vector *q_vector;
1393 int i, j, q_vectors, v_idx, r_idx;
1394 u32 mask;
9a799d71 1395
021230d4 1396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1397
4df10466
JB		 1398 /*
1399 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1400 * corresponding register.
1401 */
1402 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1403 q_vector = adapter->q_vector[v_idx];
984b3f57 1404 /* XXX for_each_set_bit(...) */
021230d4 1405 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1406 adapter->num_rx_queues);
021230d4
AV		 1407
1408 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1409 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1410 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1411 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1412 adapter->num_rx_queues,
1413 r_idx + 1);
021230d4
AV		 1414 }
1415 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1416 adapter->num_tx_queues);
021230d4
AV		 1417
1418 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1419 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1420 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1421 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1422 adapter->num_tx_queues,
1423 r_idx + 1);
021230d4
AV		 1424 }
1425
021230d4 1426 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1427 /* tx only */
1428 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1429 else if (q_vector->rxr_count)
f7554a2b
NS		 1430 /* rx or mixed */
1431 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1432
fe49f04a 1433 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1434 }
1435
e8e26350
PW		 1436 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438 v_idx);
1439 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
41fb9248 1443 /* set up to autoclear timer, and the vectors */
021230d4 1444 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1445 if (adapter->num_vfs)
1446 mask &= ~(IXGBE_EIMS_OTHER |
1447 IXGBE_EIMS_MAILBOX |
1448 IXGBE_EIMS_LSC);
1449 else
1450 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1452}
1453
f494e8fa
AV		 1454enum latency_range {
1455 lowest_latency = 0,
1456 low_latency = 1,
1457 bulk_latency = 2,
1458 latency_invalid = 255
1459};
1460
1461/**
1462 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463 * @adapter: pointer to adapter
1464 * @eitr: eitr setting (ints per sec) to give last timeslice
1465 * @itr_setting: current throttle rate in ints/second
1466 * @packets: the number of packets during this measurement interval
1467 * @bytes: the number of bytes during this measurement interval
1468 *
1469 * Stores a new ITR value based on packets and byte
1470 * counts during the last interrupt. The advantage of per interrupt
1471 * computation is faster updates and more accurate ITR for the current
1472 * traffic pattern. Constants in this function were computed
1473 * based on theoretical maximum wire speed and thresholds were set based
1474 * on testing data as well as attempting to minimize response time
1475 * while increasing bulk throughput.
1476 * this functionality is controlled by the InterruptThrottleRate module
1477 * parameter (see ixgbe_param.c)
1478 **/
1479static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1480 u32 eitr, u8 itr_setting,
1481 int packets, int bytes)
f494e8fa
AV		 1482{
1483 unsigned int retval = itr_setting;
1484 u32 timepassed_us;
1485 u64 bytes_perint;
1486
1487 if (packets == 0)
1488 goto update_itr_done;
1489
1490
1491 /* simple throttlerate management
1492 * 0-20MB/s lowest (100000 ints/s)
1493 * 20-100MB/s low (20000 ints/s)
1494 * 100-1249MB/s bulk (8000 ints/s)
1495 */
1496 /* what was last interrupt timeslice? */
1497 timepassed_us = 1000000/eitr;
1498 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500 switch (itr_setting) {
1501 case lowest_latency:
1502 if (bytes_perint > adapter->eitr_low)
1503 retval = low_latency;
1504 break;
1505 case low_latency:
1506 if (bytes_perint > adapter->eitr_high)
1507 retval = bulk_latency;
1508 else if (bytes_perint <= adapter->eitr_low)
1509 retval = lowest_latency;
1510 break;
1511 case bulk_latency:
1512 if (bytes_perint <= adapter->eitr_high)
1513 retval = low_latency;
1514 break;
1515 }
1516
1517update_itr_done:
1518 return retval;
1519}
1520
509ee935
JB		 1521/**
1522 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1523 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1524 *
1525 * This function is made to be called by ethtool and by the driver
1526 * when it needs to update EITR registers at runtime. Hardware
1527 * specific quirks/differences are taken care of here.
1528 */
fe49f04a 1529void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1530{
fe49f04a 1531 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1532 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1533 int v_idx = q_vector->v_idx;
1534 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
509ee935
JB		 1536 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537 /* must write high and low 16 bits to reset counter */
1538 itr_reg |= (itr_reg << 16);
1539 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1540 /*
1541 * 82599 can support a value of zero, so allow it for
1542 * max interrupt rate, but there is an errata where it can
1543 * not be zero with RSC
1544 */
1545 if (itr_reg == 8 &&
1546 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547 itr_reg = 0;
1548
509ee935
JB		 1549 /*
1550 * set the WDIS bit to not clear the timer bits and cause an
1551 * immediate assertion of the interrupt
1552 */
1553 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554 }
1555 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556}
1557
f494e8fa
AV		 1558static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559{
1560 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1561 u32 new_itr;
1562 u8 current_itr, ret_itr;
fe49f04a 1563 int i, r_idx;
f494e8fa
AV		 1564 struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1568 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1569 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1570 q_vector->tx_itr,
1571 tx_ring->total_packets,
1572 tx_ring->total_bytes);
f494e8fa
AV		 1573 /* if the result for this queue would decrease interrupt
1574 * rate for this vector then use that result */
30efa5a3 1575 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1576 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1577 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1578 r_idx + 1);
f494e8fa
AV		 1579 }
1580
1581 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1583 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1584 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1585 q_vector->rx_itr,
1586 rx_ring->total_packets,
1587 rx_ring->total_bytes);
f494e8fa
AV		 1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
30efa5a3 1590 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1591 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1592 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1593 r_idx + 1);
f494e8fa
AV		 1594 }
1595
30efa5a3 1596 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1597
1598 switch (current_itr) {
1599 /* counts and packets in update_itr are dependent on these numbers */
1600 case lowest_latency:
1601 new_itr = 100000;
1602 break;
1603 case low_latency:
1604 new_itr = 20000; /* aka hwitr = ~200 */
1605 break;
1606 case bulk_latency:
1607 default:
1608 new_itr = 8000;
1609 break;
1610 }
1611
1612 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1613 /* do an exponential smoothing */
1614 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1615
1616 /* save the algorithm value here, not the smoothed one */
1617 q_vector->eitr = new_itr;
fe49f04a
AD		 1618
1619 ixgbe_write_eitr(q_vector);
f494e8fa 1620 }
f494e8fa
AV		 1621}
1622
119fc60a
MC		 1623/**
1624 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625 * @work: pointer to work_struct containing our data
1626 **/
1627static void ixgbe_check_overtemp_task(struct work_struct *work)
1628{
1629 struct ixgbe_adapter *adapter = container_of(work,
1630 struct ixgbe_adapter,
1631 check_overtemp_task);
1632 struct ixgbe_hw *hw = &adapter->hw;
1633 u32 eicr = adapter->interrupt_event;
1634
1635 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636 switch (hw->device_id) {
1637 case IXGBE_DEV_ID_82599_T3_LOM: {
1638 u32 autoneg;
1639 bool link_up = false;
1640
1641 if (hw->mac.ops.check_link)
1642 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645 (eicr & IXGBE_EICR_LSC))
1646 /* Check if this is due to overtemp */
1647 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648 break;
1649 }
1650 return;
1651 default:
1652 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653 return;
1654 break;
1655 }
396e799c
ET		 1656 e_crit(drv, "Network adapter has been stopped because it has "
1657 "over heated. Restart the computer. If the problem "
849c4542
ET		 1658 "persists, power off the system and replace the "
1659 "adapter\n");
119fc60a
MC		 1660 /* write to clear the interrupt */
1661 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662 }
1663}
1664
0befdb3e
JB		 1665static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666{
1667 struct ixgbe_hw *hw = &adapter->hw;
1668
1669 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1671 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1672 /* write to clear the interrupt */
1673 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674 }
1675}
cf8280ee 1676
e8e26350
PW		 1677static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678{
1679 struct ixgbe_hw *hw = &adapter->hw;
1680
1681 if (eicr & IXGBE_EICR_GPI_SDP1) {
1682 /* Clear the interrupt */
1683 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684 schedule_work(&adapter->multispeed_fiber_task);
1685 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686 /* Clear the interrupt */
1687 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688 schedule_work(&adapter->sfp_config_module_task);
1689 } else {
1690 /* Interrupt isn't for us... */
1691 return;
1692 }
1693}
1694
cf8280ee
JB		 1695static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696{
1697 struct ixgbe_hw *hw = &adapter->hw;
1698
1699 adapter->lsc_int++;
1700 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701 adapter->link_check_timeout = jiffies;
1702 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1704 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1705 schedule_work(&adapter->watchdog_task);
1706 }
1707}
1708
9a799d71
AK		 1709static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710{
1711 struct net_device *netdev = data;
1712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1714 u32 eicr;
1715
1716 /*
1717 * Workaround for Silicon errata. Use clear-by-write instead
1718 * of clear-by-read. Reading with EICS will return the
1719 * interrupt causes without clearing, which later be done
1720 * with the write to EICR.
1721 */
1722 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1724
cf8280ee
JB		 1725 if (eicr & IXGBE_EICR_LSC)
1726 ixgbe_check_lsc(adapter);
d4f80882 1727
1cdd1ec8
GR		 1728 if (eicr & IXGBE_EICR_MAILBOX)
1729 ixgbe_msg_task(adapter);
1730
e8e26350
PW		 1731 if (hw->mac.type == ixgbe_mac_82598EB)
1732 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1733
c4cf55e5 1734 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1735 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1736 adapter->interrupt_event = eicr;
1737 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1740
1741 /* Handle Flow Director Full threshold interrupt */
1742 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743 int i;
1744 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745 /* Disable transmits before FDIR Re-initialization */
1746 netif_tx_stop_all_queues(netdev);
1747 for (i = 0; i < adapter->num_tx_queues; i++) {
1748 struct ixgbe_ring *tx_ring =
4a0b9ca0 1749 adapter->tx_ring[i];
c4cf55e5
PWJ		 1750 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751 &tx_ring->reinit_state))
1752 schedule_work(&adapter->fdir_reinit_task);
1753 }
1754 }
1755 }
d4f80882
AV		 1756 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1758
1759 return IRQ_HANDLED;
1760}
1761
fe49f04a
AD		 1762static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763 u64 qmask)
1764{
1765 u32 mask;
1766
1767 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770 } else {
1771 mask = (qmask & 0xFFFFFFFF);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773 mask = (qmask >> 32);
1774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775 }
1776 /* skip the flush */
1777}
1778
1779static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780 u64 qmask)
1781{
1782 u32 mask;
1783
1784 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787 } else {
1788 mask = (qmask & 0xFFFFFFFF);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790 mask = (qmask >> 32);
1791 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792 }
1793 /* skip the flush */
1794}
1795
9a799d71
AK		 1796static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797{
021230d4
AV		 1798 struct ixgbe_q_vector *q_vector = data;
1799 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1800 struct ixgbe_ring *tx_ring;
021230d4
AV		 1801 int i, r_idx;
1802
1803 if (!q_vector->txr_count)
1804 return IRQ_HANDLED;
1805
1806 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1808 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1809 tx_ring->total_bytes = 0;
1810 tx_ring->total_packets = 0;
021230d4 1811 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1812 r_idx + 1);
021230d4 1813 }
9a799d71 1814
9b471446 1815 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1816 napi_schedule(&q_vector->napi);
1817
9a799d71
AK		 1818 return IRQ_HANDLED;
1819}
1820
021230d4
AV		 1821/**
1822 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823 * @irq: unused
1824 * @data: pointer to our q_vector struct for this interrupt vector
1825 **/
9a799d71
AK		 1826static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827{
021230d4
AV		 1828 struct ixgbe_q_vector *q_vector = data;
1829 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1830 struct ixgbe_ring *rx_ring;
021230d4 1831 int r_idx;
30efa5a3 1832 int i;
021230d4
AV		 1833
1834 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1835 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1836 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1837 rx_ring->total_bytes = 0;
1838 rx_ring->total_packets = 0;
1839 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840 r_idx + 1);
1841 }
1842
021230d4
AV		 1843 if (!q_vector->rxr_count)
1844 return IRQ_HANDLED;
1845
021230d4 1846 /* disable interrupts on this vector only */
9b471446 1847 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1848 napi_schedule(&q_vector->napi);
021230d4
AV		 1849
1850 return IRQ_HANDLED;
1851}
1852
1853static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854{
91281fd3
AD		 1855 struct ixgbe_q_vector *q_vector = data;
1856 struct ixgbe_adapter *adapter = q_vector->adapter;
1857 struct ixgbe_ring *ring;
1858 int r_idx;
1859 int i;
1860
1861 if (!q_vector->txr_count && !q_vector->rxr_count)
1862 return IRQ_HANDLED;
1863
1864 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1866 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1867 ring->total_bytes = 0;
1868 ring->total_packets = 0;
1869 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870 r_idx + 1);
1871 }
1872
1873 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1875 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1876 ring->total_bytes = 0;
1877 ring->total_packets = 0;
1878 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879 r_idx + 1);
1880 }
1881
9b471446 1882 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1883 napi_schedule(&q_vector->napi);
9a799d71 1884
9a799d71
AK		 1885 return IRQ_HANDLED;
1886}
1887
021230d4
AV		 1888/**
1889 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890 * @napi: napi struct with our devices info in it
1891 * @budget: amount of work driver is allowed to do this pass, in packets
1892 *
f0848276
JB		 1893 * This function is optimized for cleaning one queue only on a single
1894 * q_vector!!!
021230d4 1895 **/
9a799d71
AK		 1896static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897{
021230d4 1898 struct ixgbe_q_vector *q_vector =
b4617240 1899 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1900 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1901 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1902 int work_done = 0;
021230d4 1903 long r_idx;
9a799d71 1904
021230d4 1905 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1906 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1907#ifdef CONFIG_IXGBE_DCA
bd0362dd 1908 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1909 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1910#endif
9a799d71 1911
78b6f4ce 1912 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1913
021230d4
AV		 1914 /* If all Rx work done, exit the polling mode */
1915 if (work_done < budget) {
288379f0 1916 napi_complete(napi);
f7554a2b 1917 if (adapter->rx_itr_setting & 1)
f494e8fa 1918 ixgbe_set_itr_msix(q_vector);
9a799d71 1919 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1920 ixgbe_irq_enable_queues(adapter,
1921 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1922 }
1923
1924 return work_done;
1925}
1926
f0848276 1927/**
91281fd3 1928 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1929 * @napi: napi struct with our devices info in it
1930 * @budget: amount of work driver is allowed to do this pass, in packets
1931 *
1932 * This function will clean more than one rx queue associated with a
1933 * q_vector.
1934 **/
91281fd3 1935static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1936{
1937 struct ixgbe_q_vector *q_vector =
1938 container_of(napi, struct ixgbe_q_vector, napi);
1939 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1940 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1941 int work_done = 0, i;
1942 long r_idx;
91281fd3
AD		 1943 bool tx_clean_complete = true;
1944
1945 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1947 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1948#ifdef CONFIG_IXGBE_DCA
1949 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950 ixgbe_update_tx_dca(adapter, ring);
1951#endif
1952 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954 r_idx + 1);
1955 }
f0848276
JB		 1956
1957 /* attempt to distribute budget to each queue fairly, but don't allow
1958 * the budget to go below 1 because we'll exit polling */
1959 budget /= (q_vector->rxr_count ?: 1);
1960 budget = max(budget, 1);
1961 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1963 ring = adapter->rx_ring[r_idx];
5dd2d332 1964#ifdef CONFIG_IXGBE_DCA
f0848276 1965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1966 ixgbe_update_rx_dca(adapter, ring);
f0848276 1967#endif
91281fd3 1968 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1969 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970 r_idx + 1);
1971 }
1972
1973 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1974 ring = adapter->rx_ring[r_idx];
f0848276 1975 /* If all Rx work done, exit the polling mode */
7f821875 1976 if (work_done < budget) {
288379f0 1977 napi_complete(napi);
f7554a2b 1978 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1979 ixgbe_set_itr_msix(q_vector);
1980 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1981 ixgbe_irq_enable_queues(adapter,
1982 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1983 return 0;
1984 }
1985
1986 return work_done;
1987}
91281fd3
AD		 1988
1989/**
1990 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991 * @napi: napi struct with our devices info in it
1992 * @budget: amount of work driver is allowed to do this pass, in packets
1993 *
1994 * This function is optimized for cleaning one queue only on a single
1995 * q_vector!!!
1996 **/
1997static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998{
1999 struct ixgbe_q_vector *q_vector =
2000 container_of(napi, struct ixgbe_q_vector, napi);
2001 struct ixgbe_adapter *adapter = q_vector->adapter;
2002 struct ixgbe_ring *tx_ring = NULL;
2003 int work_done = 0;
2004 long r_idx;
2005
2006 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 2007 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2008#ifdef CONFIG_IXGBE_DCA
2009 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010 ixgbe_update_tx_dca(adapter, tx_ring);
2011#endif
2012
2013 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014 work_done = budget;
2015
f7554a2b 2016 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2017 if (work_done < budget) {
2018 napi_complete(napi);
f7554a2b 2019 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2020 ixgbe_set_itr_msix(q_vector);
2021 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023 }
2024
2025 return work_done;
2026}
2027
021230d4 2028static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 2029 int r_idx)
021230d4 2030{
7a921c93
AD		 2031 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033 set_bit(r_idx, q_vector->rxr_idx);
2034 q_vector->rxr_count++;
021230d4
AV		 2035}
2036
2037static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 2038 int t_idx)
021230d4 2039{
7a921c93
AD		 2040 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042 set_bit(t_idx, q_vector->txr_idx);
2043 q_vector->txr_count++;
021230d4
AV		 2044}
2045
9a799d71 2046/**
021230d4
AV		 2047 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048 * @adapter: board private structure to initialize
2049 * @vectors: allotted vector count for descriptor rings
9a799d71 2050 *
021230d4
AV		 2051 * This function maps descriptor rings to the queue-specific vectors
2052 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2053 * one vector per ring/queue, but on a constrained vector budget, we
2054 * group the rings as "efficiently" as possible. You would add new
2055 * mapping configurations in here.
9a799d71 2056 **/
021230d4 2057static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 2058 int vectors)
021230d4
AV		 2059{
2060 int v_start = 0;
2061 int rxr_idx = 0, txr_idx = 0;
2062 int rxr_remaining = adapter->num_rx_queues;
2063 int txr_remaining = adapter->num_tx_queues;
2064 int i, j;
2065 int rqpv, tqpv;
2066 int err = 0;
2067
2068 /* No mapping required if MSI-X is disabled. */
2069 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070 goto out;
9a799d71 2071
021230d4
AV		 2072 /*
2073 * The ideal configuration...
2074 * We have enough vectors to map one per queue.
2075 */
2076 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2079
021230d4
AV		 2080 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2082
9a799d71 2083 goto out;
021230d4 2084 }
9a799d71 2085
021230d4
AV		 2086 /*
2087 * If we don't have enough vectors for a 1-to-1
2088 * mapping, we'll have to group them so there are
2089 * multiple queues per vector.
2090 */
2091 /* Re-adjusting *qpv takes care of the remainder. */
2092 for (i = v_start; i < vectors; i++) {
2093 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094 for (j = 0; j < rqpv; j++) {
2095 map_vector_to_rxq(adapter, i, rxr_idx);
2096 rxr_idx++;
2097 rxr_remaining--;
2098 }
2099 }
2100 for (i = v_start; i < vectors; i++) {
2101 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102 for (j = 0; j < tqpv; j++) {
2103 map_vector_to_txq(adapter, i, txr_idx);
2104 txr_idx++;
2105 txr_remaining--;
9a799d71 2106 }
9a799d71
AK		 2107 }
2108
021230d4
AV		 2109out:
2110 return err;
2111}
2112
2113/**
2114 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115 * @adapter: board private structure
2116 *
2117 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118 * interrupts from the kernel.
2119 **/
2120static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121{
2122 struct net_device *netdev = adapter->netdev;
2123 irqreturn_t (*handler)(int, void *);
2124 int i, vector, q_vectors, err;
cb13fc20 2125 int ri=0, ti=0;
021230d4
AV		 2126
2127 /* Decrement for Other and TCP Timer vectors */
2128 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130 /* Map the Tx/Rx rings to the vectors we were allotted. */
2131 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132 if (err)
2133 goto out;
2134
2135#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 2136 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137 &ixgbe_msix_clean_many)
021230d4 2138 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2139 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 2140
2141 if(handler == &ixgbe_msix_clean_rx) {
2142 sprintf(adapter->name[vector], "%s-%s-%d",
2143 netdev->name, "rx", ri++);
2144 }
2145 else if(handler == &ixgbe_msix_clean_tx) {
2146 sprintf(adapter->name[vector], "%s-%s-%d",
2147 netdev->name, "tx", ti++);
2148 }
2149 else
2150 sprintf(adapter->name[vector], "%s-%s-%d",
2151 netdev->name, "TxRx", vector);
2152
021230d4 2153 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 2154 handler, 0, adapter->name[vector],
7a921c93 2155 adapter->q_vector[vector]);
9a799d71 2156 if (err) {
396e799c 2157 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2158 "Error: %d\n", err);
021230d4 2159 goto free_queue_irqs;
9a799d71 2160 }
9a799d71
AK		 2161 }
2162
021230d4
AV		 2163 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2165 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2166 if (err) {
396e799c 2167 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2168 goto free_queue_irqs;
9a799d71
AK		 2169 }
2170
9a799d71
AK		 2171 return 0;
2172
021230d4
AV		 2173free_queue_irqs:
2174 for (i = vector - 1; i >= 0; i--)
2175 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 2176 adapter->q_vector[i]);
021230d4
AV		 2177 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2179 kfree(adapter->msix_entries);
2180 adapter->msix_entries = NULL;
021230d4 2181out:
9a799d71
AK		 2182 return err;
2183}
2184
f494e8fa
AV		 2185static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2186{
7a921c93 2187 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2188 u8 current_itr;
2189 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2190 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2192
30efa5a3 2193 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2194 q_vector->tx_itr,
2195 tx_ring->total_packets,
2196 tx_ring->total_bytes);
30efa5a3 2197 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 2198 q_vector->rx_itr,
2199 rx_ring->total_packets,
2200 rx_ring->total_bytes);
f494e8fa 2201
30efa5a3 2202 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2203
2204 switch (current_itr) {
2205 /* counts and packets in update_itr are dependent on these numbers */
2206 case lowest_latency:
2207 new_itr = 100000;
2208 break;
2209 case low_latency:
2210 new_itr = 20000; /* aka hwitr = ~200 */
2211 break;
2212 case bulk_latency:
2213 new_itr = 8000;
2214 break;
2215 default:
2216 break;
2217 }
2218
2219 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2220 /* do an exponential smoothing */
2221 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2222
2223 /* save the algorithm value here, not the smoothed one */
2224 q_vector->eitr = new_itr;
fe49f04a
AD		 2225
2226 ixgbe_write_eitr(q_vector);
f494e8fa 2227 }
f494e8fa
AV		 2228}
2229
79aefa45
AD		 2230/**
2231 * ixgbe_irq_enable - Enable default interrupt generation settings
2232 * @adapter: board private structure
2233 **/
2234static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2235{
2236 u32 mask;
835462fc
NS		 2237
2238 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2239 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2241 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2243 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2244 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2245 mask |= IXGBE_EIMS_GPI_SDP1;
2246 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2247 if (adapter->num_vfs)
2248 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2249 }
c4cf55e5
PWJ		 2250 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2253
79aefa45 2254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 2255 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 2256 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2257
2258 if (adapter->num_vfs > 32) {
2259 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2261 }
79aefa45 2262}
021230d4 2263
9a799d71 2264/**
021230d4 2265 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2266 * @irq: interrupt number
2267 * @data: pointer to a network interface device structure
9a799d71
AK		 2268 **/
2269static irqreturn_t ixgbe_intr(int irq, void *data)
2270{
2271 struct net_device *netdev = data;
2272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2274 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2275 u32 eicr;
2276
54037505
DS		 2277 /*
2278 * Workaround for silicon errata. Mask the interrupts
2279 * before the read of EICR.
2280 */
2281 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2282
021230d4
AV		 2283 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284 * therefore no explict interrupt disable is necessary */
2285 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 2286 if (!eicr) {
2287 /* shared interrupt alert!
2288 * make sure interrupts are enabled because the read will
2289 * have disabled interrupts due to EIAM */
2290 ixgbe_irq_enable(adapter);
9a799d71 2291 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2292 }
9a799d71 2293
cf8280ee
JB		 2294 if (eicr & IXGBE_EICR_LSC)
2295 ixgbe_check_lsc(adapter);
021230d4 2296
e8e26350
PW		 2297 if (hw->mac.type == ixgbe_mac_82599EB)
2298 ixgbe_check_sfp_event(adapter, eicr);
2299
0befdb3e 2300 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2301 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2304
7a921c93 2305 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2306 adapter->tx_ring[0]->total_packets = 0;
2307 adapter->tx_ring[0]->total_bytes = 0;
2308 adapter->rx_ring[0]->total_packets = 0;
2309 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2310 /* would disable interrupts here but EIAM disabled it */
7a921c93 2311 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2312 }
2313
2314 return IRQ_HANDLED;
2315}
2316
021230d4
AV		 2317static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2318{
2319 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
2321 for (i = 0; i < q_vectors; i++) {
7a921c93 2322 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2323 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325 q_vector->rxr_count = 0;
2326 q_vector->txr_count = 0;
2327 }
2328}
2329
9a799d71
AK		 2330/**
2331 * ixgbe_request_irq - initialize interrupts
2332 * @adapter: board private structure
2333 *
2334 * Attempts to configure interrupts using the best available
2335 * capabilities of the hardware and kernel.
2336 **/
021230d4 2337static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2338{
2339 struct net_device *netdev = adapter->netdev;
021230d4 2340 int err;
9a799d71 2341
021230d4
AV		 2342 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343 err = ixgbe_request_msix_irqs(adapter);
2344 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2345 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 2346 netdev->name, netdev);
021230d4 2347 } else {
a0607fd3 2348 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 2349 netdev->name, netdev);
9a799d71
AK		 2350 }
2351
9a799d71 2352 if (err)
396e799c 2353 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2354
9a799d71
AK		 2355 return err;
2356}
2357
2358static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2359{
2360 struct net_device *netdev = adapter->netdev;
2361
2362 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2363 int i, q_vectors;
9a799d71 2364
021230d4
AV		 2365 q_vectors = adapter->num_msix_vectors;
2366
2367 i = q_vectors - 1;
9a799d71 2368 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2369
021230d4
AV		 2370 i--;
2371 for (; i >= 0; i--) {
2372 free_irq(adapter->msix_entries[i].vector,
7a921c93 2373 adapter->q_vector[i]);
021230d4
AV		 2374 }
2375
2376 ixgbe_reset_q_vectors(adapter);
2377 } else {
2378 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2379 }
2380}
2381
22d5a71b
JB		 2382/**
2383 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384 * @adapter: board private structure
2385 **/
2386static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2387{
835462fc
NS		 2388 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2390 } else {
2391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2394 if (adapter->num_vfs > 32)
2395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2396 }
2397 IXGBE_WRITE_FLUSH(&adapter->hw);
2398 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2399 int i;
2400 for (i = 0; i < adapter->num_msix_vectors; i++)
2401 synchronize_irq(adapter->msix_entries[i].vector);
2402 } else {
2403 synchronize_irq(adapter->pdev->irq);
2404 }
2405}
2406
9a799d71
AK		 2407/**
2408 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2409 *
2410 **/
2411static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2412{
9a799d71
AK		 2413 struct ixgbe_hw *hw = &adapter->hw;
2414
021230d4 2415 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2416 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2417
e8e26350
PW		 2418 ixgbe_set_ivar(adapter, 0, 0, 0);
2419 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2420
2421 map_vector_to_rxq(adapter, 0, 0);
2422 map_vector_to_txq(adapter, 0, 0);
2423
396e799c 2424 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2425}
2426
43e69bf0
AD		 2427/**
2428 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2429 * @adapter: board private structure
2430 * @ring: structure containing ring specific data
2431 *
2432 * Configure the Tx descriptor ring after a reset.
2433 **/
2434 static void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2435 struct ixgbe_ring *ring)
2436{
2437 struct ixgbe_hw *hw = &adapter->hw;
2438 u64 tdba = ring->dma;
2439 u16 reg_idx = ring->reg_idx;
2440
2441 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2442 (tdba & DMA_BIT_MASK(32)));
2443 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2444 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2445 ring->count * sizeof(union ixgbe_adv_tx_desc));
2446 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2447 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2448 ring->head = IXGBE_TDH(reg_idx);
2449 ring->tail = IXGBE_TDT(reg_idx);
2450
2451}
2452
120ff942
AD		 2453static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2454{
2455 struct ixgbe_hw *hw = &adapter->hw;
2456 u32 rttdcs;
2457 u32 mask;
2458
2459 if (hw->mac.type == ixgbe_mac_82598EB)
2460 return;
2461
2462 /* disable the arbiter while setting MTQC */
2463 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2464 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2465 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2466
2467 /* set transmit pool layout */
2468 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2469 switch (adapter->flags & mask) {
2470
2471 case (IXGBE_FLAG_SRIOV_ENABLED):
2472 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2473 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2474 break;
2475
2476 case (IXGBE_FLAG_DCB_ENABLED):
2477 /* We enable 8 traffic classes, DCB only */
2478 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2479 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2480 break;
2481
2482 default:
2483 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2484 break;
2485 }
2486
2487 /* re-enable the arbiter */
2488 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2489 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2490}
2491
9a799d71 2492/**
3a581073 2493 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2494 * @adapter: board private structure
2495 *
2496 * Configure the Tx unit of the MAC after a reset.
2497 **/
2498static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2499{
43e69bf0 2500 u32 i;
9a799d71
AK		 2501
2502 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2503 for (i = 0; i < adapter->num_tx_queues; i++)
2504 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
ee5f784a 2505
120ff942 2506 ixgbe_setup_mtqc(adapter);
9a799d71
AK		 2507}
2508
e8e26350 2509#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2510
a6616b42
YZ		 2511static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2512 struct ixgbe_ring *rx_ring)
cc41ac7c 2513{
cc41ac7c 2514 u32 srrctl;
a6616b42 2515 int index;
0cefafad 2516 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2517
a6616b42
YZ		 2518 index = rx_ring->reg_idx;
2519 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2520 unsigned long mask;
0cefafad 2521 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2522 index = index & mask;
cc41ac7c 2523 }
cc41ac7c
JB		 2524 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2525
2526 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2527 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2528
afafd5b0
AD		 2529 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2530 IXGBE_SRRCTL_BSIZEHDR_MASK;
2531
6e455b89 2532 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2533#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2534 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2535#else
2536 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2537#endif
cc41ac7c 2538 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2539 } else {
afafd5b0
AD		 2540 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2541 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2542 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2543 }
e8e26350 2544
cc41ac7c
JB		 2545 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2546}
9a799d71 2547
05abb126 2548static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2549{
05abb126
AD		 2550 struct ixgbe_hw *hw = &adapter->hw;
2551 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2552 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2553 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2554 u32 mrqc = 0, reta = 0;
2555 u32 rxcsum;
2556 int i, j;
0cefafad
JB		 2557 int mask;
2558
05abb126
AD		 2559 /* Fill out hash function seeds */
2560 for (i = 0; i < 10; i++)
2561 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563 /* Fill out redirection table */
2564 for (i = 0, j = 0; i < 128; i++, j++) {
2565 if (j == adapter->ring_feature[RING_F_RSS].indices)
2566 j = 0;
2567 /* reta = 4-byte sliding window of
2568 * 0x00..(indices-1)(indices-1)00..etc. */
2569 reta = (reta << 8) | (j * 0x11);
2570 if ((i & 3) == 3)
2571 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572 }
0cefafad 2573
05abb126
AD		 2574 /* Disable indicating checksum in descriptor, enables RSS hash */
2575 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576 rxcsum |= IXGBE_RXCSUM_PCSD;
2577 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
2579 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2580 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2581 else
2582 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2583#ifdef CONFIG_IXGBE_DCB
05abb126 2584 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2585#endif
05abb126
AD		 2586 | IXGBE_FLAG_SRIOV_ENABLED
2587 );
0cefafad
JB		 2588
2589 switch (mask) {
2590 case (IXGBE_FLAG_RSS_ENABLED):
2591 mrqc = IXGBE_MRQC_RSSEN;
2592 break;
1cdd1ec8
GR		 2593 case (IXGBE_FLAG_SRIOV_ENABLED):
2594 mrqc = IXGBE_MRQC_VMDQEN;
2595 break;
0cefafad
JB		 2596#ifdef CONFIG_IXGBE_DCB
2597 case (IXGBE_FLAG_DCB_ENABLED):
2598 mrqc = IXGBE_MRQC_RT8TCEN;
2599 break;
2600#endif /* CONFIG_IXGBE_DCB */
2601 default:
2602 break;
2603 }
2604
05abb126
AD		 2605 /* Perform hash on these packet types */
2606 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2607 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2608 | IXGBE_MRQC_RSS_FIELD_IPV6
2609 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2610
2611 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2612}
2613
bb5a9ad2
NS		 2614/**
2615 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2616 * @adapter: address of board private structure
2617 * @index: index of ring to set
bb5a9ad2 2618 **/
edd2ea55 2619static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2620{
2621 struct ixgbe_ring *rx_ring;
2622 struct ixgbe_hw *hw = &adapter->hw;
2623 int j;
2624 u32 rscctrl;
edd2ea55 2625 int rx_buf_len;
bb5a9ad2 2626
4a0b9ca0 2627 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2628 j = rx_ring->reg_idx;
edd2ea55 2629 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2630 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2631 rscctrl |= IXGBE_RSCCTL_RSCEN;
2632 /*
2633 * we must limit the number of descriptors so that the
2634 * total size of max desc * buf_len is not greater
2635 * than 65535
2636 */
2637 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2638#if (MAX_SKB_FRAGS > 16)
2639 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2640#elif (MAX_SKB_FRAGS > 8)
2641 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2642#elif (MAX_SKB_FRAGS > 4)
2643 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2644#else
2645 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2646#endif
2647 } else {
2648 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2649 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2650 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2651 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2652 else
2653 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2654 }
2655 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2656}
2657
acd37177
AD		 2658static void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2659 struct ixgbe_ring *ring)
2660{
2661 struct ixgbe_hw *hw = &adapter->hw;
2662 u64 rdba = ring->dma;
2663 u16 reg_idx = ring->reg_idx;
2664
2665 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2666 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2667 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2668 ring->count * sizeof(union ixgbe_adv_rx_desc));
2669 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2670 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2671 ring->head = IXGBE_RDH(reg_idx);
2672 ring->tail = IXGBE_RDT(reg_idx);
2673}
2674
48654521
AD		 2675static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2676{
2677 struct ixgbe_hw *hw = &adapter->hw;
2678 int p;
2679
2680 /* PSRTYPE must be initialized in non 82598 adapters */
2681 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2682 IXGBE_PSRTYPE_UDPHDR |
2683 IXGBE_PSRTYPE_IPV4HDR |
2684 IXGBE_PSRTYPE_L2HDR |
2685 IXGBE_PSRTYPE_IPV6HDR;
2686
2687 if (hw->mac.type == ixgbe_mac_82598EB)
2688 return;
2689
2690 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2691 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2692
2693 for (p = 0; p < adapter->num_rx_pools; p++)
2694 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2695 psrtype);
2696}
2697
9a799d71 2698/**
3a581073 2699 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2700 * @adapter: board private structure
2701 *
2702 * Configure the Rx unit of the MAC after a reset.
2703 **/
2704static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2705{
9a799d71 2706 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2707 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2708 struct net_device *netdev = adapter->netdev;
2709 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
acd37177
AD		 2710 int i;
2711 u32 rxctrl;
f5dc442b 2712 u32 hlreg0;
cc41ac7c 2713 u32 rdrxctl;
7c6e0a43 2714 int rx_buf_len;
9a799d71 2715
48654521
AD		 2716 ixgbe_setup_psrtype(adapter);
2717
9a799d71 2718 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2719 /* Do not use packet split if we're in SR-IOV Mode */
2720 if (!adapter->num_vfs)
2721 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2722
2723 /* Set the RX buffer length according to the mode */
2724 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2725 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2726 } else {
0c19d6af 2727 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2728 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2729 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2730 else
7c6e0a43 2731 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2732 }
2733
9a799d71
AK		 2734 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2735 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2736 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2737 else
2738 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2739#ifdef IXGBE_FCOE
f34c5c82 2740 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2741 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2742#endif
9a799d71
AK		 2743 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2744
9a799d71
AK		 2745 /* disable receives while setting up the descriptors */
2746 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2747 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2748
0cefafad
JB		 2749 /*
2750 * Setup the HW Rx Head and Tail Descriptor Pointers and
2751 * the Base and Length of the Rx Descriptor Ring
2752 */
9a799d71 2753 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2754 rx_ring = adapter->rx_ring[i];
a6616b42 2755 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2756
6e455b89
YZ		 2757 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2758 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2759 else
2760 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2761
63f39bd1 2762#ifdef IXGBE_FCOE
f34c5c82 2763 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2764 struct ixgbe_ring_feature *f;
2765 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2766 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2767 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2768 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2769 rx_ring->rx_buf_len =
2770 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2771 }
63f39bd1
YZ		 2772 }
2773
2774#endif /* IXGBE_FCOE */
acd37177 2775 ixgbe_configure_rx_ring(adapter, rx_ring);
a6616b42 2776 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2777 }
2778
e8e26350
PW		 2779 if (hw->mac.type == ixgbe_mac_82598EB) {
2780 /*
2781 * For VMDq support of different descriptor types or
2782 * buffer sizes through the use of multiple SRRCTL
2783 * registers, RDRXCTL.MVMEN must be set to 1
2784 *
2785 * also, the manual doesn't mention it clearly but DCA hints
2786 * will only use queue 0's tags unless this bit is set. Side
2787 * effects of setting this bit are only that SRRCTL must be
2788 * fully programmed [0..15]
2789 */
2a41ff81
JB		 2790 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2791 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2792 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2793 }
177db6ff 2794
1cdd1ec8
GR		 2795 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2796 u32 vt_reg_bits;
2797 u32 reg_offset, vf_shift;
2798 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2799 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2800 | IXGBE_VT_CTL_REPLEN;
2801 vt_reg_bits |= (adapter->num_vfs <<
2802 IXGBE_VT_CTL_POOL_SHIFT);
2803 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2804 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2805
2806 vf_shift = adapter->num_vfs % 32;
2807 reg_offset = adapter->num_vfs / 32;
2808 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2809 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2810 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2811 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2812 /* Enable only the PF's pool for Tx/Rx */
2813 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2814 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2815 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f0412776 2816 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
1cdd1ec8
GR		 2817 }
2818
e8e26350 2819 /* Program MRQC for the distribution of queues */
05abb126 2820 ixgbe_setup_mrqc(adapter);
9a799d71 2821
1cdd1ec8
GR		 2822 if (adapter->num_vfs) {
2823 u32 reg;
2824
2825 /* Map PF MAC address in RAR Entry 0 to first pool
2826 * following VFs */
2827 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2828
2829 /* Set up VF register offsets for selected VT Mode, i.e.
2830 * 64 VFs for SR-IOV */
2831 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2832 reg |= IXGBE_GCR_EXT_SRIOV;
2833 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2834 }
2835
e8e26350
PW		 2836 if (hw->mac.type == ixgbe_mac_82599EB) {
2837 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2838 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2839 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2840 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2841 }
f8212f97 2842
0c19d6af 2843 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2844 /* Enable 82599 HW-RSC */
bb5a9ad2 2845 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2846 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2847
f8212f97
AD		 2848 /* Disable RSC for ACK packets */
2849 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2850 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2851 }
9a799d71
AK		 2852}
2853
068c89b0
DS		 2854static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2855{
2856 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2857 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2858 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2859
2860 /* add VID to filter table */
1ada1b1b 2861 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2862}
2863
2864static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2865{
2866 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2867 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2868 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2869
2870 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2871 ixgbe_irq_disable(adapter);
2872
2873 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2874
2875 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2876 ixgbe_irq_enable(adapter);
2877
2878 /* remove VID from filter table */
1ada1b1b 2879 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2880}
2881
5f6c0181
JB		 2882/**
2883 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2884 * @adapter: driver data
2885 */
2886static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2887{
2888 struct ixgbe_hw *hw = &adapter->hw;
2889 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2890 int i, j;
2891
2892 switch (hw->mac.type) {
2893 case ixgbe_mac_82598EB:
38e0bd98
YZ		 2894 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2895#ifdef CONFIG_IXGBE_DCB
2896 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2897 vlnctrl &= ~IXGBE_VLNCTRL_VME;
2898#endif
5f6c0181
JB		 2899 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2900 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2901 break;
2902 case ixgbe_mac_82599EB:
2903 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2904 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2905 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
38e0bd98
YZ		 2906#ifdef CONFIG_IXGBE_DCB
2907 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2908 break;
2909#endif
5f6c0181
JB		 2910 for (i = 0; i < adapter->num_rx_queues; i++) {
2911 j = adapter->rx_ring[i]->reg_idx;
2912 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2913 vlnctrl &= ~IXGBE_RXDCTL_VME;
2914 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2915 }
2916 break;
2917 default:
2918 break;
2919 }
2920}
2921
2922/**
2923 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2924 * @adapter: driver data
2925 */
2926static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2927{
2928 struct ixgbe_hw *hw = &adapter->hw;
2929 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2930 int i, j;
2931
2932 switch (hw->mac.type) {
2933 case ixgbe_mac_82598EB:
2934 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2935 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2936 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2937 break;
2938 case ixgbe_mac_82599EB:
2939 vlnctrl |= IXGBE_VLNCTRL_VFE;
2940 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2941 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2942 for (i = 0; i < adapter->num_rx_queues; i++) {
2943 j = adapter->rx_ring[i]->reg_idx;
2944 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2945 vlnctrl |= IXGBE_RXDCTL_VME;
2946 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2947 }
2948 break;
2949 default:
2950 break;
2951 }
2952}
2953
9a799d71 2954static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2955 struct vlan_group *grp)
9a799d71
AK		 2956{
2957 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 2958
d4f80882
AV		 2959 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2960 ixgbe_irq_disable(adapter);
9a799d71
AK		 2961 adapter->vlgrp = grp;
2962
2f90b865
AD		 2963 /*
2964 * For a DCB driver, always enable VLAN tag stripping so we can
2965 * still receive traffic from a DCB-enabled host even if we're
2966 * not in DCB mode.
2967 */
5f6c0181 2968 ixgbe_vlan_filter_enable(adapter);
dc63d377 2969
e8e26350 2970 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2971
d4f80882
AV		 2972 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2973 ixgbe_irq_enable(adapter);
9a799d71
AK		 2974}
2975
9a799d71
AK		 2976static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2977{
2978 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2979
2980 if (adapter->vlgrp) {
2981 u16 vid;
2982 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2983 if (!vlan_group_get_device(adapter->vlgrp, vid))
2984 continue;
2985 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2986 }
2987 }
2988}
2989
2850062a
AD		 2990/**
2991 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
2992 * @netdev: network interface device structure
2993 *
2994 * Writes unicast address list to the RAR table.
2995 * Returns: -ENOMEM on failure/insufficient address space
2996 * 0 on no addresses written
2997 * X on writing X addresses to the RAR table
2998 **/
2999static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3000{
3001 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3002 struct ixgbe_hw *hw = &adapter->hw;
3003 unsigned int vfn = adapter->num_vfs;
3004 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3005 int count = 0;
3006
3007 /* return ENOMEM indicating insufficient memory for addresses */
3008 if (netdev_uc_count(netdev) > rar_entries)
3009 return -ENOMEM;
3010
3011 if (!netdev_uc_empty(netdev) && rar_entries) {
3012 struct netdev_hw_addr *ha;
3013 /* return error if we do not support writing to RAR table */
3014 if (!hw->mac.ops.set_rar)
3015 return -ENOMEM;
3016
3017 netdev_for_each_uc_addr(ha, netdev) {
3018 if (!rar_entries)
3019 break;
3020 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3021 vfn, IXGBE_RAH_AV);
3022 count++;
3023 }
3024 }
3025 /* write the addresses in reverse order to avoid write combining */
3026 for (; rar_entries > 0 ; rar_entries--)
3027 hw->mac.ops.clear_rar(hw, rar_entries);
3028
3029 return count;
3030}
3031
9a799d71 3032/**
2c5645cf 3033 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3034 * @netdev: network interface device structure
3035 *
2c5645cf
CL		 3036 * The set_rx_method entry point is called whenever the unicast/multicast
3037 * address list or the network interface flags are updated. This routine is
3038 * responsible for configuring the hardware for proper unicast, multicast and
3039 * promiscuous mode.
9a799d71 3040 **/
7f870475 3041void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3042{
3043 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3044 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3045 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3046 int count;
9a799d71
AK		 3047
3048 /* Check for Promiscuous and All Multicast modes */
3049
3050 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3051
f5dc442b
AD		 3052 /* set all bits that we expect to always be set */
3053 fctrl |= IXGBE_FCTRL_BAM;
3054 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3055 fctrl |= IXGBE_FCTRL_PMCF;
3056
2850062a
AD		 3057 /* clear the bits we are changing the status of */
3058 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3059
9a799d71 3060 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3061 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3062 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3063 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3064 /* don't hardware filter vlans in promisc mode */
3065 ixgbe_vlan_filter_disable(adapter);
9a799d71 3066 } else {
746b9f02
PM		 3067 if (netdev->flags & IFF_ALLMULTI) {
3068 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3069 vmolr |= IXGBE_VMOLR_MPE;
3070 } else {
3071 /*
3072 * Write addresses to the MTA, if the attempt fails
3073 * then we should just turn on promiscous mode so
3074 * that we can at least receive multicast traffic
3075 */
3076 hw->mac.ops.update_mc_addr_list(hw, netdev);
3077 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3078 }
5f6c0181 3079 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3080 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3081 /*
3082 * Write addresses to available RAR registers, if there is not
3083 * sufficient space to store all the addresses then enable
3084 * unicast promiscous mode
3085 */
3086 count = ixgbe_write_uc_addr_list(netdev);
3087 if (count < 0) {
3088 fctrl |= IXGBE_FCTRL_UPE;
3089 vmolr |= IXGBE_VMOLR_ROPE;
3090 }
9a799d71
AK		 3091 }
3092
2850062a 3093 if (adapter->num_vfs) {
1cdd1ec8 3094 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3095 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3096 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3097 IXGBE_VMOLR_ROPE);
3098 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3099 }
3100
3101 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
9a799d71
AK		 3102}
3103
021230d4
AV		 3104static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3105{
3106 int q_idx;
3107 struct ixgbe_q_vector *q_vector;
3108 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3109
3110 /* legacy and MSI only use one vector */
3111 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3112 q_vectors = 1;
3113
3114 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3115 struct napi_struct *napi;
7a921c93 3116 q_vector = adapter->q_vector[q_idx];
f0848276 3117 napi = &q_vector->napi;
91281fd3
AD		 3118 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3119 if (!q_vector->rxr_count || !q_vector->txr_count) {
3120 if (q_vector->txr_count == 1)
3121 napi->poll = &ixgbe_clean_txonly;
3122 else if (q_vector->rxr_count == 1)
3123 napi->poll = &ixgbe_clean_rxonly;
3124 }
3125 }
f0848276
JB		 3126
3127 napi_enable(napi);
021230d4
AV		 3128 }
3129}
3130
3131static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3132{
3133 int q_idx;
3134 struct ixgbe_q_vector *q_vector;
3135 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3136
3137 /* legacy and MSI only use one vector */
3138 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3139 q_vectors = 1;
3140
3141 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3142 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3143 napi_disable(&q_vector->napi);
3144 }
3145}
3146
7a6b6f51 3147#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3148/*
3149 * ixgbe_configure_dcb - Configure DCB hardware
3150 * @adapter: ixgbe adapter struct
3151 *
3152 * This is called by the driver on open to configure the DCB hardware.
3153 * This is also called by the gennetlink interface when reconfiguring
3154 * the DCB state.
3155 */
3156static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3157{
3158 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 3159 u32 txdctl;
2f90b865
AD		 3160 int i, j;
3161
67ebd791
AD		 3162 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3163 if (hw->mac.type == ixgbe_mac_82598EB)
3164 netif_set_gso_max_size(adapter->netdev, 65536);
3165 return;
3166 }
3167
3168 if (hw->mac.type == ixgbe_mac_82598EB)
3169 netif_set_gso_max_size(adapter->netdev, 32768);
3170
2f90b865
AD		 3171 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3172 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3173 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3174
3175 /* reconfigure the hardware */
3176 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3177
3178 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3179 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3180 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3181 /* PThresh workaround for Tx hang with DFP enabled. */
3182 txdctl |= 32;
3183 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3184 }
3185 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 3186 ixgbe_vlan_filter_enable(adapter);
3187
2f90b865
AD		 3188 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3189}
3190
3191#endif
9a799d71
AK		 3192static void ixgbe_configure(struct ixgbe_adapter *adapter)
3193{
3194 struct net_device *netdev = adapter->netdev;
c4cf55e5 3195 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3196 int i;
3197
2c5645cf 3198 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 3199
3200 ixgbe_restore_vlan(adapter);
7a6b6f51 3201#ifdef CONFIG_IXGBE_DCB
67ebd791 3202 ixgbe_configure_dcb(adapter);
2f90b865 3203#endif
9a799d71 3204
eacd73f7
YZ		 3205#ifdef IXGBE_FCOE
3206 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3207 ixgbe_configure_fcoe(adapter);
3208
3209#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3210 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3211 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3212 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 3213 adapter->atr_sample_rate;
3214 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3215 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3216 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3217 }
3218
9a799d71
AK		 3219 ixgbe_configure_tx(adapter);
3220 ixgbe_configure_rx(adapter);
3221 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 3222 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3223 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 3224}
3225
e8e26350
PW		 3226static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3227{
3228 switch (hw->phy.type) {
3229 case ixgbe_phy_sfp_avago:
3230 case ixgbe_phy_sfp_ftl:
3231 case ixgbe_phy_sfp_intel:
3232 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3233 case ixgbe_phy_sfp_passive_tyco:
3234 case ixgbe_phy_sfp_passive_unknown:
3235 case ixgbe_phy_sfp_active_unknown:
3236 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3237 return true;
3238 default:
3239 return false;
3240 }
3241}
3242
0ecc061d 3243/**
e8e26350
PW		 3244 * ixgbe_sfp_link_config - set up SFP+ link
3245 * @adapter: pointer to private adapter struct
3246 **/
3247static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3248{
3249 struct ixgbe_hw *hw = &adapter->hw;
3250
3251 if (hw->phy.multispeed_fiber) {
3252 /*
3253 * In multispeed fiber setups, the device may not have
3254 * had a physical connection when the driver loaded.
3255 * If that's the case, the initial link configuration
3256 * couldn't get the MAC into 10G or 1G mode, so we'll
3257 * never have a link status change interrupt fire.
3258 * We need to try and force an autonegotiation
3259 * session, then bring up link.
3260 */
3261 hw->mac.ops.setup_sfp(hw);
3262 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3263 schedule_work(&adapter->multispeed_fiber_task);
3264 } else {
3265 /*
3266 * Direct Attach Cu and non-multispeed fiber modules
3267 * still need to be configured properly prior to
3268 * attempting link.
3269 */
3270 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3271 schedule_work(&adapter->sfp_config_module_task);
3272 }
3273}
3274
3275/**
3276 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3277 * @hw: pointer to private hardware struct
3278 *
3279 * Returns 0 on success, negative on failure
3280 **/
e8e26350 3281static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3282{
3283 u32 autoneg;
8620a103 3284 bool negotiation, link_up = false;
0ecc061d
PWJ		 3285 u32 ret = IXGBE_ERR_LINK_SETUP;
3286
3287 if (hw->mac.ops.check_link)
3288 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3289
3290 if (ret)
3291 goto link_cfg_out;
3292
3293 if (hw->mac.ops.get_link_capabilities)
8620a103 3294 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 3295 if (ret)
3296 goto link_cfg_out;
3297
8620a103
MC		 3298 if (hw->mac.ops.setup_link)
3299 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3300link_cfg_out:
3301 return ret;
3302}
3303
e8e26350
PW		 3304#define IXGBE_MAX_RX_DESC_POLL 10
3305static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3306 int rxr)
3307{
4a0b9ca0 3308 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 3309 int k;
3310
3311 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3312 if (IXGBE_READ_REG(&adapter->hw,
3313 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3314 break;
3315 else
3316 msleep(1);
3317 }
3318 if (k >= IXGBE_MAX_RX_DESC_POLL) {
396e799c 3319 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
849c4542 3320 "the polling period\n", rxr);
e8e26350 3321 }
4a0b9ca0
PW		 3322 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3323 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 3324}
3325
9a799d71
AK		 3326static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3327{
3328 struct net_device *netdev = adapter->netdev;
9a799d71 3329 struct ixgbe_hw *hw = &adapter->hw;
021230d4 3330 int i, j = 0;
e8e26350 3331 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 3332 int err;
9a799d71 3333 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 3334 u32 txdctl, rxdctl, mhadd;
e8e26350 3335 u32 dmatxctl;
021230d4 3336 u32 gpie;
c9205697 3337 u32 ctrl_ext;
9a799d71 3338
5eba3699
AV		 3339 ixgbe_get_hw_control(adapter);
3340
021230d4
AV		 3341 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3342 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 3343 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3344 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 3345 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 3346 } else {
3347 /* MSI only */
021230d4 3348 gpie = 0;
9a799d71 3349 }
1cdd1ec8
GR		 3350 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3351 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3352 gpie |= IXGBE_GPIE_VTMODE_64;
3353 }
021230d4
AV		 3354 /* XXX: to interrupt immediately for EICS writes, enable this */
3355 /* gpie |= IXGBE_GPIE_EIMEN; */
3356 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 3357 }
3358
9b471446
JB		 3359 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3360 /*
3361 * use EIAM to auto-mask when MSI-X interrupt is asserted
3362 * this saves a register write for every interrupt
3363 */
3364 switch (hw->mac.type) {
3365 case ixgbe_mac_82598EB:
3366 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3367 break;
3368 default:
3369 case ixgbe_mac_82599EB:
3370 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3371 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3372 break;
3373 }
3374 } else {
021230d4
AV		 3375 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3376 * specifically only auto mask tx and rx interrupts */
3377 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3378 }
9a799d71 3379
119fc60a
MC		 3380 /* Enable Thermal over heat sensor interrupt */
3381 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3382 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3383 gpie |= IXGBE_SDP0_GPIEN;
3384 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3385 }
3386
0befdb3e
JB		 3387 /* Enable fan failure interrupt if media type is copper */
3388 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3389 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3390 gpie |= IXGBE_SDP1_GPIEN;
3391 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3392 }
3393
e8e26350
PW		 3394 if (hw->mac.type == ixgbe_mac_82599EB) {
3395 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3396 gpie |= IXGBE_SDP1_GPIEN;
3397 gpie |= IXGBE_SDP2_GPIEN;
3398 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3399 }
3400
63f39bd1
YZ		 3401#ifdef IXGBE_FCOE
3402 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 3403 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 3404 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3405 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3406
3407#endif /* IXGBE_FCOE */
021230d4 3408 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 3409 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3410 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3411 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3412
3413 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3414 }
3415
179b4096
AD		 3416 if (hw->mac.type == ixgbe_mac_82599EB) {
3417 /* DMATXCTL.EN must be set after all Tx queue config is done */
3418 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3419 dmatxctl |= IXGBE_DMATXCTL_TE;
3420 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3421 }
9a799d71 3422 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3423 j = adapter->tx_ring[i]->reg_idx;
021230d4 3424 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
ef021194
JB		 3425 if (adapter->rx_itr_setting == 0) {
3426 /* cannot set wthresh when itr==0 */
3427 txdctl &= ~0x007F0000;
3428 } else {
3429 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3430 txdctl |= (8 << 16);
3431 }
9a799d71 3432 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 3433 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 3434 if (hw->mac.type == ixgbe_mac_82599EB) {
3435 int wait_loop = 10;
3436 /* poll for Tx Enable ready */
3437 do {
3438 msleep(1);
3439 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3440 } while (--wait_loop &&
3441 !(txdctl & IXGBE_TXDCTL_ENABLE));
3442 if (!wait_loop)
396e799c 3443 e_err(drv, "Could not enable Tx Queue %d\n", j);
1cdd1ec8 3444 }
9a799d71
AK		 3445 }
3446
e8e26350 3447 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 3448 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 3449 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3450 /* enable PTHRESH=32 descriptors (half the internal cache)
3451 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3452 * this also removes a pesky rx_no_buffer_count increment */
3453 rxdctl |= 0x0020;
9a799d71 3454 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 3455 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 3456 if (hw->mac.type == ixgbe_mac_82599EB)
3457 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 3458 }
3459 /* enable all receives */
3460 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 3461 if (hw->mac.type == ixgbe_mac_82598EB)
3462 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3463 else
3464 rxdctl |= IXGBE_RXCTRL_RXEN;
3465 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 3466
3467 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3468 ixgbe_configure_msix(adapter);
3469 else
3470 ixgbe_configure_msi_and_legacy(adapter);
3471
61fac744
PW		 3472 /* enable the optics */
3473 if (hw->phy.multispeed_fiber)
3474 hw->mac.ops.enable_tx_laser(hw);
3475
9a799d71 3476 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3477 ixgbe_napi_enable_all(adapter);
3478
3479 /* clear any pending interrupts, may auto mask */
3480 IXGBE_READ_REG(hw, IXGBE_EICR);
3481
9a799d71
AK		 3482 ixgbe_irq_enable(adapter);
3483
bf069c97
DS		 3484 /*
3485 * If this adapter has a fan, check to see if we had a failure
3486 * before we enabled the interrupt.
3487 */
3488 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3489 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3490 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3491 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3492 }
3493
e8e26350
PW		 3494 /*
3495 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3496 * arrived before interrupts were enabled but after probe. Such
3497 * devices wouldn't have their type identified yet. We need to
3498 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3499 * If we're not hot-pluggable SFP+, we just need to configure link
3500 * and bring it up.
3501 */
19343de2
DS		 3502 if (hw->phy.type == ixgbe_phy_unknown) {
3503 err = hw->phy.ops.identify(hw);
3504 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3505 /*
3506 * Take the device down and schedule the sfp tasklet
3507 * which will unregister_netdev and log it.
3508 */
19343de2 3509 ixgbe_down(adapter);
5da43c1a 3510 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3511 return err;
3512 }
e8e26350
PW		 3513 }
3514
3515 if (ixgbe_is_sfp(hw)) {
3516 ixgbe_sfp_link_config(adapter);
3517 } else {
3518 err = ixgbe_non_sfp_link_config(hw);
3519 if (err)
396e799c 3520 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3521 }
0ecc061d 3522
c4cf55e5
PWJ		 3523 for (i = 0; i < adapter->num_tx_queues; i++)
3524 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3525 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3526
1da100bb
PWJ		 3527 /* enable transmits */
3528 netif_tx_start_all_queues(netdev);
3529
9a799d71
AK		 3530 /* bring the link up in the watchdog, this could race with our first
3531 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3532 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3533 adapter->link_check_timeout = jiffies;
9a799d71 3534 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3535
3536 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3537 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3538 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3539 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3540
9a799d71
AK		 3541 return 0;
3542}
3543
d4f80882
AV		 3544void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3545{
3546 WARN_ON(in_interrupt());
3547 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3548 msleep(1);
3549 ixgbe_down(adapter);
5809a1ae
GR		 3550 /*
3551 * If SR-IOV enabled then wait a bit before bringing the adapter
3552 * back up to give the VFs time to respond to the reset. The
3553 * two second wait is based upon the watchdog timer cycle in
3554 * the VF driver.
3555 */
3556 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3557 msleep(2000);
d4f80882
AV		 3558 ixgbe_up(adapter);
3559 clear_bit(__IXGBE_RESETTING, &adapter->state);
3560}
3561
9a799d71
AK		 3562int ixgbe_up(struct ixgbe_adapter *adapter)
3563{
3564 /* hardware has been reset, we need to reload some things */
3565 ixgbe_configure(adapter);
3566
3567 return ixgbe_up_complete(adapter);
3568}
3569
3570void ixgbe_reset(struct ixgbe_adapter *adapter)
3571{
c44ade9e 3572 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3573 int err;
3574
3575 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3576 switch (err) {
3577 case 0:
3578 case IXGBE_ERR_SFP_NOT_PRESENT:
3579 break;
3580 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3581 e_dev_err("master disable timed out\n");
da4dd0f7 3582 break;
794caeb2
PWJ		 3583 case IXGBE_ERR_EEPROM_VERSION:
3584 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3585 e_dev_warn("This device is a pre-production adapter/LOM. "
3586 "Please be aware there may be issuesassociated with "
3587 "your hardware. If you are experiencing problems "
3588 "please contact your Intel or hardware "
3589 "representative who provided you with this "
3590 "hardware.\n");
794caeb2 3591 break;
da4dd0f7 3592 default:
849c4542 3593 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3594 }
9a799d71
AK		 3595
3596 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3597 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3598 IXGBE_RAH_AV);
9a799d71
AK		 3599}
3600
9a799d71
AK		 3601/**
3602 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3603 * @adapter: board private structure
3604 * @rx_ring: ring to free buffers from
3605 **/
3606static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3607 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3608{
3609 struct pci_dev *pdev = adapter->pdev;
3610 unsigned long size;
3611 unsigned int i;
3612
3613 /* Free all the Rx ring sk_buffs */
3614
3615 for (i = 0; i < rx_ring->count; i++) {
3616 struct ixgbe_rx_buffer *rx_buffer_info;
3617
3618 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3619 if (rx_buffer_info->dma) {
1b507730 3620 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
b4617240 3621 rx_ring->rx_buf_len,
1b507730 3622 DMA_FROM_DEVICE);
9a799d71
AK		 3623 rx_buffer_info->dma = 0;
3624 }
3625 if (rx_buffer_info->skb) {
f8212f97 3626 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3627 rx_buffer_info->skb = NULL;
f8212f97
AD		 3628 do {
3629 struct sk_buff *this = skb;
e8171aaa 3630 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3631 dma_unmap_single(&pdev->dev,
3632 IXGBE_RSC_CB(this)->dma,
43634e82 3633 rx_ring->rx_buf_len,
1b507730 3634 DMA_FROM_DEVICE);
fd3686a8 3635 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3636 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3637 }
f8212f97
AD		 3638 skb = skb->prev;
3639 dev_kfree_skb(this);
3640 } while (skb);
9a799d71
AK		 3641 }
3642 if (!rx_buffer_info->page)
3643 continue;
4f57ca6e 3644 if (rx_buffer_info->page_dma) {
1b507730
NN		 3645 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3646 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3647 rx_buffer_info->page_dma = 0;
3648 }
9a799d71
AK		 3649 put_page(rx_buffer_info->page);
3650 rx_buffer_info->page = NULL;
762f4c57 3651 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3652 }
3653
3654 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3655 memset(rx_ring->rx_buffer_info, 0, size);
3656
3657 /* Zero out the descriptor ring */
3658 memset(rx_ring->desc, 0, rx_ring->size);
3659
3660 rx_ring->next_to_clean = 0;
3661 rx_ring->next_to_use = 0;
3662
9891ca7c
JB		 3663 if (rx_ring->head)
3664 writel(0, adapter->hw.hw_addr + rx_ring->head);
3665 if (rx_ring->tail)
3666 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3667}
3668
3669/**
3670 * ixgbe_clean_tx_ring - Free Tx Buffers
3671 * @adapter: board private structure
3672 * @tx_ring: ring to be cleaned
3673 **/
3674static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3675 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3676{
3677 struct ixgbe_tx_buffer *tx_buffer_info;
3678 unsigned long size;
3679 unsigned int i;
3680
3681 /* Free all the Tx ring sk_buffs */
3682
3683 for (i = 0; i < tx_ring->count; i++) {
3684 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3685 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3686 }
3687
3688 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3689 memset(tx_ring->tx_buffer_info, 0, size);
3690
3691 /* Zero out the descriptor ring */
3692 memset(tx_ring->desc, 0, tx_ring->size);
3693
3694 tx_ring->next_to_use = 0;
3695 tx_ring->next_to_clean = 0;
3696
9891ca7c
JB		 3697 if (tx_ring->head)
3698 writel(0, adapter->hw.hw_addr + tx_ring->head);
3699 if (tx_ring->tail)
3700 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3701}
3702
3703/**
021230d4 3704 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3705 * @adapter: board private structure
3706 **/
021230d4 3707static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3708{
3709 int i;
3710
021230d4 3711 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3712 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3713}
3714
3715/**
021230d4 3716 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3717 * @adapter: board private structure
3718 **/
021230d4 3719static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3720{
3721 int i;
3722
021230d4 3723 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3724 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3725}
3726
3727void ixgbe_down(struct ixgbe_adapter *adapter)
3728{
3729 struct net_device *netdev = adapter->netdev;
7f821875 3730 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3731 u32 rxctrl;
7f821875
JB		 3732 u32 txdctl;
3733 int i, j;
9a799d71
AK		 3734
3735 /* signal that we are down to the interrupt handler */
3736 set_bit(__IXGBE_DOWN, &adapter->state);
3737
767081ad
GR		 3738 /* disable receive for all VFs and wait one second */
3739 if (adapter->num_vfs) {
767081ad
GR		 3740 /* ping all the active vfs to let them know we are going down */
3741 ixgbe_ping_all_vfs(adapter);
581d1aa7 3742
767081ad
GR		 3743 /* Disable all VFTE/VFRE TX/RX */
3744 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3745
3746 /* Mark all the VFs as inactive */
3747 for (i = 0 ; i < adapter->num_vfs; i++)
3748 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3749 }
3750
9a799d71 3751 /* disable receives */
7f821875
JB		 3752 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3753 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3754
7f821875 3755 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3756 msleep(10);
3757
7f821875
JB		 3758 netif_tx_stop_all_queues(netdev);
3759
0a1f87cb
DS		 3760 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3761 del_timer_sync(&adapter->sfp_timer);
9a799d71 3762 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3763 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3764
c0dfb90e
JF		 3765 netif_carrier_off(netdev);
3766 netif_tx_disable(netdev);
3767
3768 ixgbe_irq_disable(adapter);
3769
3770 ixgbe_napi_disable_all(adapter);
3771
c4cf55e5
PWJ		 3772 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3773 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3774 cancel_work_sync(&adapter->fdir_reinit_task);
3775
119fc60a
MC		 3776 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3777 cancel_work_sync(&adapter->check_overtemp_task);
3778
7f821875
JB		 3779 /* disable transmits in the hardware now that interrupts are off */
3780 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3781 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3782 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3783 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3784 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3785 }
88512539
PW		 3786 /* Disable the Tx DMA engine on 82599 */
3787 if (hw->mac.type == ixgbe_mac_82599EB)
3788 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3789 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3790 ~IXGBE_DMATXCTL_TE));
7f821875 3791
9f756f01
JF		 3792 /* power down the optics */
3793 if (hw->phy.multispeed_fiber)
3794 hw->mac.ops.disable_tx_laser(hw);
3795
9a713e7c
PW		 3796 /* clear n-tuple filters that are cached */
3797 ethtool_ntuple_flush(netdev);
3798
6f4a0e45
PL		 3799 if (!pci_channel_offline(adapter->pdev))
3800 ixgbe_reset(adapter);
9a799d71
AK		 3801 ixgbe_clean_all_tx_rings(adapter);
3802 ixgbe_clean_all_rx_rings(adapter);
3803
5dd2d332 3804#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3805 /* since we reset the hardware DCA settings were cleared */
e35ec126 3806 ixgbe_setup_dca(adapter);
96b0e0f6 3807#endif
9a799d71
AK		 3808}
3809
9a799d71 3810/**
021230d4
AV		 3811 * ixgbe_poll - NAPI Rx polling callback
3812 * @napi: structure for representing this polling device
3813 * @budget: how many packets driver is allowed to clean
3814 *
3815 * This function is used for legacy and MSI, NAPI mode
9a799d71 3816 **/
021230d4 3817static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3818{
9a1a69ad
JB		 3819 struct ixgbe_q_vector *q_vector =
3820 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3821 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3822 int tx_clean_complete, work_done = 0;
9a799d71 3823
5dd2d332 3824#ifdef CONFIG_IXGBE_DCA
bd0362dd 3825 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3826 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3827 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3828 }
3829#endif
3830
4a0b9ca0
PW		 3831 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3832 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3833
9a1a69ad 3834 if (!tx_clean_complete)
d2c7ddd6
DM		 3835 work_done = budget;
3836
53e52c72
DM		 3837 /* If budget not fully consumed, exit the polling mode */
3838 if (work_done < budget) {
288379f0 3839 napi_complete(napi);
f7554a2b 3840 if (adapter->rx_itr_setting & 1)
f494e8fa 3841 ixgbe_set_itr(adapter);
d4f80882 3842 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3843 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3844 }
9a799d71
AK		 3845 return work_done;
3846}
3847
3848/**
3849 * ixgbe_tx_timeout - Respond to a Tx Hang
3850 * @netdev: network interface device structure
3851 **/
3852static void ixgbe_tx_timeout(struct net_device *netdev)
3853{
3854 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3855
3856 /* Do the reset outside of interrupt context */
3857 schedule_work(&adapter->reset_task);
3858}
3859
3860static void ixgbe_reset_task(struct work_struct *work)
3861{
3862 struct ixgbe_adapter *adapter;
3863 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3864
2f90b865
AD		 3865 /* If we're already down or resetting, just bail */
3866 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3867 test_bit(__IXGBE_RESETTING, &adapter->state))
3868 return;
3869
9a799d71
AK		 3870 adapter->tx_timeout_count++;
3871
dcd79aeb
TI		 3872 ixgbe_dump(adapter);
3873 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3874 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3875}
3876
bc97114d
PWJ		 3877#ifdef CONFIG_IXGBE_DCB
3878static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3879{
bc97114d 3880 bool ret = false;
0cefafad 3881 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3882
0cefafad
JB		 3883 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3884 return ret;
3885
3886 f->mask = 0x7 << 3;
3887 adapter->num_rx_queues = f->indices;
3888 adapter->num_tx_queues = f->indices;
3889 ret = true;
2f90b865 3890
bc97114d
PWJ		 3891 return ret;
3892}
3893#endif
3894
4df10466
JB		 3895/**
3896 * ixgbe_set_rss_queues: Allocate queues for RSS
3897 * @adapter: board private structure to initialize
3898 *
3899 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3900 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3901 *
3902 **/
bc97114d
PWJ		 3903static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3904{
3905 bool ret = false;
0cefafad 3906 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3907
3908 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3909 f->mask = 0xF;
3910 adapter->num_rx_queues = f->indices;
3911 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3912 ret = true;
3913 } else {
bc97114d 3914 ret = false;
b9804972
JB		 3915 }
3916
bc97114d
PWJ		 3917 return ret;
3918}
3919
c4cf55e5
PWJ		 3920/**
3921 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3922 * @adapter: board private structure to initialize
3923 *
3924 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3925 * to the original CPU that initiated the Tx session. This runs in addition
3926 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3927 * Rx load across CPUs using RSS.
3928 *
3929 **/
3930static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3931{
3932 bool ret = false;
3933 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3934
3935 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3936 f_fdir->mask = 0;
3937
3938 /* Flow Director must have RSS enabled */
3939 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3940 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3941 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3942 adapter->num_tx_queues = f_fdir->indices;
3943 adapter->num_rx_queues = f_fdir->indices;
3944 ret = true;
3945 } else {
3946 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3947 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3948 }
3949 return ret;
3950}
3951
0331a832
YZ		 3952#ifdef IXGBE_FCOE
3953/**
3954 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3955 * @adapter: board private structure to initialize
3956 *
3957 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3958 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3959 * rx queues out of the max number of rx queues, instead, it is used as the
3960 * index of the first rx queue used by FCoE.
3961 *
3962 **/
3963static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3964{
3965 bool ret = false;
3966 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3967
3968 f->indices = min((int)num_online_cpus(), f->indices);
3969 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3970 adapter->num_rx_queues = 1;
3971 adapter->num_tx_queues = 1;
0331a832
YZ		 3972#ifdef CONFIG_IXGBE_DCB
3973 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 3974 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 3975 ixgbe_set_dcb_queues(adapter);
3976 }
3977#endif
3978 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 3979 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 3980 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3981 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3982 ixgbe_set_fdir_queues(adapter);
3983 else
3984 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3985 }
3986 /* adding FCoE rx rings to the end */
3987 f->mask = adapter->num_rx_queues;
3988 adapter->num_rx_queues += f->indices;
8de8b2e6 3989 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3990
3991 ret = true;
3992 }
3993
3994 return ret;
3995}
3996
3997#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3998/**
3999 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4000 * @adapter: board private structure to initialize
4001 *
4002 * IOV doesn't actually use anything, so just NAK the
4003 * request for now and let the other queue routines
4004 * figure out what to do.
4005 */
4006static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4007{
4008 return false;
4009}
4010
4df10466
JB		 4011/*
4012 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4013 * @adapter: board private structure to initialize
4014 *
4015 * This is the top level queue allocation routine. The order here is very
4016 * important, starting with the "most" number of features turned on at once,
4017 * and ending with the smallest set of features. This way large combinations
4018 * can be allocated if they're turned on, and smaller combinations are the
4019 * fallthrough conditions.
4020 *
4021 **/
bc97114d
PWJ		 4022static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4023{
1cdd1ec8
GR		 4024 /* Start with base case */
4025 adapter->num_rx_queues = 1;
4026 adapter->num_tx_queues = 1;
4027 adapter->num_rx_pools = adapter->num_rx_queues;
4028 adapter->num_rx_queues_per_pool = 1;
4029
4030 if (ixgbe_set_sriov_queues(adapter))
4031 return;
4032
0331a832
YZ		 4033#ifdef IXGBE_FCOE
4034 if (ixgbe_set_fcoe_queues(adapter))
4035 goto done;
4036
4037#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4038#ifdef CONFIG_IXGBE_DCB
4039 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4040 goto done;
bc97114d
PWJ		 4041
4042#endif
c4cf55e5
PWJ		 4043 if (ixgbe_set_fdir_queues(adapter))
4044 goto done;
4045
bc97114d 4046 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4047 goto done;
4048
4049 /* fallback to base case */
4050 adapter->num_rx_queues = 1;
4051 adapter->num_tx_queues = 1;
4052
4053done:
4054 /* Notify the stack of the (possibly) reduced Tx Queue count. */
f0796d5c 4055 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
b9804972
JB		 4056}
4057
021230d4 4058static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 4059 int vectors)
021230d4
AV		 4060{
4061 int err, vector_threshold;
4062
4063 /* We'll want at least 3 (vector_threshold):
4064 * 1) TxQ[0] Cleanup
4065 * 2) RxQ[0] Cleanup
4066 * 3) Other (Link Status Change, etc.)
4067 * 4) TCP Timer (optional)
4068 */
4069 vector_threshold = MIN_MSIX_COUNT;
4070
4071 /* The more we get, the more we will assign to Tx/Rx Cleanup
4072 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4073 * Right now, we simply care about how many we'll get; we'll
4074 * set them up later while requesting irq's.
4075 */
4076 while (vectors >= vector_threshold) {
4077 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 4078 vectors);
021230d4
AV		 4079 if (!err) /* Success in acquiring all requested vectors. */
4080 break;
4081 else if (err < 0)
4082 vectors = 0; /* Nasty failure, quit now */
4083 else /* err == number of vectors we should try again with */
4084 vectors = err;
4085 }
4086
4087 if (vectors < vector_threshold) {
4088 /* Can't allocate enough MSI-X interrupts? Oh well.
4089 * This just means we'll go with either a single MSI
4090 * vector or fall back to legacy interrupts.
4091 */
849c4542
ET		 4092 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4093 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4094 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4095 kfree(adapter->msix_entries);
4096 adapter->msix_entries = NULL;
021230d4
AV		 4097 } else {
4098 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4099 /*
4100 * Adjust for only the vectors we'll use, which is minimum
4101 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4102 * vectors we were allocated.
4103 */
4104 adapter->num_msix_vectors = min(vectors,
4105 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4106 }
4107}
4108
021230d4 4109/**
bc97114d 4110 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4111 * @adapter: board private structure to initialize
4112 *
bc97114d
PWJ		 4113 * Cache the descriptor ring offsets for RSS to the assigned rings.
4114 *
021230d4 4115 **/
bc97114d 4116static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4117{
bc97114d
PWJ		 4118 int i;
4119 bool ret = false;
4120
4121 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4122 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4123 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4124 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4125 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4126 ret = true;
4127 } else {
4128 ret = false;
4129 }
4130
4131 return ret;
4132}
4133
4134#ifdef CONFIG_IXGBE_DCB
4135/**
4136 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4137 * @adapter: board private structure to initialize
4138 *
4139 * Cache the descriptor ring offsets for DCB to the assigned rings.
4140 *
4141 **/
4142static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4143{
4144 int i;
4145 bool ret = false;
4146 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4147
4148 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4149 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4150 /* the number of queues is assumed to be symmetric */
4151 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4152 adapter->rx_ring[i]->reg_idx = i << 3;
4153 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4154 }
bc97114d 4155 ret = true;
e8e26350 4156 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4157 if (dcb_i == 8) {
4158 /*
4159 * Tx TC0 starts at: descriptor queue 0
4160 * Tx TC1 starts at: descriptor queue 32
4161 * Tx TC2 starts at: descriptor queue 64
4162 * Tx TC3 starts at: descriptor queue 80
4163 * Tx TC4 starts at: descriptor queue 96
4164 * Tx TC5 starts at: descriptor queue 104
4165 * Tx TC6 starts at: descriptor queue 112
4166 * Tx TC7 starts at: descriptor queue 120
4167 *
4168 * Rx TC0-TC7 are offset by 16 queues each
4169 */
4170 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4171 adapter->tx_ring[i]->reg_idx = i << 5;
4172 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4173 }
4174 for ( ; i < 5; i++) {
4a0b9ca0 4175 adapter->tx_ring[i]->reg_idx =
f92ef202 4176 ((i + 2) << 4);
4a0b9ca0 4177 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4178 }
4179 for ( ; i < dcb_i; i++) {
4a0b9ca0 4180 adapter->tx_ring[i]->reg_idx =
f92ef202 4181 ((i + 8) << 3);
4a0b9ca0 4182 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4183 }
4184
4185 ret = true;
4186 } else if (dcb_i == 4) {
4187 /*
4188 * Tx TC0 starts at: descriptor queue 0
4189 * Tx TC1 starts at: descriptor queue 64
4190 * Tx TC2 starts at: descriptor queue 96
4191 * Tx TC3 starts at: descriptor queue 112
4192 *
4193 * Rx TC0-TC3 are offset by 32 queues each
4194 */
4a0b9ca0
PW		 4195 adapter->tx_ring[0]->reg_idx = 0;
4196 adapter->tx_ring[1]->reg_idx = 64;
4197 adapter->tx_ring[2]->reg_idx = 96;
4198 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4199 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4200 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4201
4202 ret = true;
4203 } else {
4204 ret = false;
e8e26350 4205 }
bc97114d
PWJ		 4206 } else {
4207 ret = false;
021230d4 4208 }
bc97114d
PWJ		 4209 } else {
4210 ret = false;
021230d4 4211 }
bc97114d
PWJ		 4212
4213 return ret;
4214}
4215#endif
4216
c4cf55e5
PWJ		 4217/**
4218 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4219 * @adapter: board private structure to initialize
4220 *
4221 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4222 *
4223 **/
4224static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4225{
4226 int i;
4227 bool ret = false;
4228
4229 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4230 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4231 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4232 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4233 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4234 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4235 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4236 ret = true;
4237 }
4238
4239 return ret;
4240}
4241
0331a832
YZ		 4242#ifdef IXGBE_FCOE
4243/**
4244 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4245 * @adapter: board private structure to initialize
4246 *
4247 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4248 *
4249 */
4250static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4251{
8de8b2e6 4252 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4253 bool ret = false;
4254 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4255
4256 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4257#ifdef CONFIG_IXGBE_DCB
4258 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4259 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4260
0331a832 4261 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4262 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4263 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4264 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4265 /*
4266 * In 82599, the number of Tx queues for each traffic
4267 * class for both 8-TC and 4-TC modes are:
4268 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4269 * 8 TCs: 32 32 16 16 8 8 8 8
4270 * 4 TCs: 64 64 32 32
4271 * We have max 8 queues for FCoE, where 8 the is
4272 * FCoE redirection table size. If TC for FCoE is
4273 * less than or equal to TC3, we have enough queues
4274 * to add max of 8 queues for FCoE, so we start FCoE
4275 * tx descriptor from the next one, i.e., reg_idx + 1.
4276 * If TC for FCoE is above TC3, implying 8 TC mode,
4277 * and we need 8 for FCoE, we have to take all queues
4278 * in that traffic class for FCoE.
4279 */
4280 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4281 fcoe_tx_i--;
0331a832
YZ		 4282 }
4283#endif /* CONFIG_IXGBE_DCB */
4284 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4285 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4286 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4287 ixgbe_cache_ring_fdir(adapter);
4288 else
4289 ixgbe_cache_ring_rss(adapter);
4290
8de8b2e6
YZ		 4291 fcoe_rx_i = f->mask;
4292 fcoe_tx_i = f->mask;
4293 }
4294 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4295 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4296 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4297 }
0331a832
YZ		 4298 ret = true;
4299 }
4300 return ret;
4301}
4302
4303#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4304/**
4305 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4306 * @adapter: board private structure to initialize
4307 *
4308 * SR-IOV doesn't use any descriptor rings but changes the default if
4309 * no other mapping is used.
4310 *
4311 */
4312static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4313{
4a0b9ca0
PW		 4314 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4315 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4316 if (adapter->num_vfs)
4317 return true;
4318 else
4319 return false;
4320}
4321
bc97114d
PWJ		 4322/**
4323 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4324 * @adapter: board private structure to initialize
4325 *
4326 * Once we know the feature-set enabled for the device, we'll cache
4327 * the register offset the descriptor ring is assigned to.
4328 *
4329 * Note, the order the various feature calls is important. It must start with
4330 * the "most" features enabled at the same time, then trickle down to the
4331 * least amount of features turned on at once.
4332 **/
4333static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4334{
4335 /* start with default case */
4a0b9ca0
PW		 4336 adapter->rx_ring[0]->reg_idx = 0;
4337 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4338
1cdd1ec8
GR		 4339 if (ixgbe_cache_ring_sriov(adapter))
4340 return;
4341
0331a832
YZ		 4342#ifdef IXGBE_FCOE
4343 if (ixgbe_cache_ring_fcoe(adapter))
4344 return;
4345
4346#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4347#ifdef CONFIG_IXGBE_DCB
4348 if (ixgbe_cache_ring_dcb(adapter))
4349 return;
4350
4351#endif
c4cf55e5
PWJ		 4352 if (ixgbe_cache_ring_fdir(adapter))
4353 return;
4354
bc97114d
PWJ		 4355 if (ixgbe_cache_ring_rss(adapter))
4356 return;
021230d4
AV		 4357}
4358
9a799d71
AK		 4359/**
4360 * ixgbe_alloc_queues - Allocate memory for all rings
4361 * @adapter: board private structure to initialize
4362 *
4363 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4364 * number of queues at compile-time. The polling_netdev array is
4365 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4366 **/
2f90b865 4367static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4368{
4369 int i;
4a0b9ca0 4370 int orig_node = adapter->node;
9a799d71 4371
021230d4 4372 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4373 struct ixgbe_ring *ring = adapter->tx_ring[i];
4374 if (orig_node == -1) {
4375 int cur_node = next_online_node(adapter->node);
4376 if (cur_node == MAX_NUMNODES)
4377 cur_node = first_online_node;
4378 adapter->node = cur_node;
4379 }
4380 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4381 adapter->node);
4382 if (!ring)
4383 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4384 if (!ring)
4385 goto err_tx_ring_allocation;
4386 ring->count = adapter->tx_ring_count;
4387 ring->queue_index = i;
4388 ring->numa_node = adapter->node;
4389
4390 adapter->tx_ring[i] = ring;
021230d4 4391 }
b9804972 4392
4a0b9ca0
PW		 4393 /* Restore the adapter's original node */
4394 adapter->node = orig_node;
4395
9a799d71 4396 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4397 struct ixgbe_ring *ring = adapter->rx_ring[i];
4398 if (orig_node == -1) {
4399 int cur_node = next_online_node(adapter->node);
4400 if (cur_node == MAX_NUMNODES)
4401 cur_node = first_online_node;
4402 adapter->node = cur_node;
4403 }
4404 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4405 adapter->node);
4406 if (!ring)
4407 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4408 if (!ring)
4409 goto err_rx_ring_allocation;
4410 ring->count = adapter->rx_ring_count;
4411 ring->queue_index = i;
4412 ring->numa_node = adapter->node;
4413
4414 adapter->rx_ring[i] = ring;
021230d4
AV		 4415 }
4416
4a0b9ca0
PW		 4417 /* Restore the adapter's original node */
4418 adapter->node = orig_node;
4419
021230d4
AV		 4420 ixgbe_cache_ring_register(adapter);
4421
4422 return 0;
4423
4424err_rx_ring_allocation:
4a0b9ca0
PW		 4425 for (i = 0; i < adapter->num_tx_queues; i++)
4426 kfree(adapter->tx_ring[i]);
021230d4
AV		 4427err_tx_ring_allocation:
4428 return -ENOMEM;
4429}
4430
4431/**
4432 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4433 * @adapter: board private structure to initialize
4434 *
4435 * Attempt to configure the interrupts using the best available
4436 * capabilities of the hardware and the kernel.
4437 **/
feea6a57 4438static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4439{
8be0e467 4440 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4441 int err = 0;
4442 int vector, v_budget;
4443
4444 /*
4445 * It's easy to be greedy for MSI-X vectors, but it really
4446 * doesn't do us much good if we have a lot more vectors
4447 * than CPU's. So let's be conservative and only ask for
342bde1b 4448 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4449 */
4450 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 4451 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4452
4453 /*
4454 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4455 * hw.mac->max_msix_vectors vectors. With features
4456 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4457 * descriptor queues supported by our device. Thus, we cap it off in
4458 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4459 */
8be0e467 4460 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4461
4462 /* A failure in MSI-X entry allocation isn't fatal, but it does
4463 * mean we disable MSI-X capabilities of the adapter. */
4464 adapter->msix_entries = kcalloc(v_budget,
b4617240 4465 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4466 if (adapter->msix_entries) {
4467 for (vector = 0; vector < v_budget; vector++)
4468 adapter->msix_entries[vector].entry = vector;
021230d4 4469
7a921c93 4470 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4471
7a921c93
AD		 4472 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4473 goto out;
4474 }
26d27844 4475
7a921c93
AD		 4476 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4477 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4478 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4479 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4480 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4481 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4482 ixgbe_disable_sriov(adapter);
4483
7a921c93 4484 ixgbe_set_num_queues(adapter);
021230d4 4485
021230d4
AV		 4486 err = pci_enable_msi(adapter->pdev);
4487 if (!err) {
4488 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4489 } else {
849c4542
ET		 4490 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4491 "Unable to allocate MSI interrupt, "
4492 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4493 /* reset err */
4494 err = 0;
4495 }
4496
4497out:
021230d4
AV		 4498 return err;
4499}
4500
7a921c93
AD		 4501/**
4502 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4503 * @adapter: board private structure to initialize
4504 *
4505 * We allocate one q_vector per queue interrupt. If allocation fails we
4506 * return -ENOMEM.
4507 **/
4508static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4509{
4510 int q_idx, num_q_vectors;
4511 struct ixgbe_q_vector *q_vector;
4512 int napi_vectors;
4513 int (*poll)(struct napi_struct *, int);
4514
4515 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4516 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4517 napi_vectors = adapter->num_rx_queues;
91281fd3 4518 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4519 } else {
4520 num_q_vectors = 1;
4521 napi_vectors = 1;
4522 poll = &ixgbe_poll;
4523 }
4524
4525 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4526 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4527 GFP_KERNEL, adapter->node);
4528 if (!q_vector)
4529 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4530 GFP_KERNEL);
7a921c93
AD		 4531 if (!q_vector)
4532 goto err_out;
4533 q_vector->adapter = adapter;
f7554a2b
NS		 4534 if (q_vector->txr_count && !q_vector->rxr_count)
4535 q_vector->eitr = adapter->tx_eitr_param;
4536 else
4537 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4538 q_vector->v_idx = q_idx;
91281fd3 4539 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4540 adapter->q_vector[q_idx] = q_vector;
4541 }
4542
4543 return 0;
4544
4545err_out:
4546 while (q_idx) {
4547 q_idx--;
4548 q_vector = adapter->q_vector[q_idx];
4549 netif_napi_del(&q_vector->napi);
4550 kfree(q_vector);
4551 adapter->q_vector[q_idx] = NULL;
4552 }
4553 return -ENOMEM;
4554}
4555
4556/**
4557 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4558 * @adapter: board private structure to initialize
4559 *
4560 * This function frees the memory allocated to the q_vectors. In addition if
4561 * NAPI is enabled it will delete any references to the NAPI struct prior
4562 * to freeing the q_vector.
4563 **/
4564static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4565{
4566 int q_idx, num_q_vectors;
7a921c93 4567
91281fd3 4568 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4569 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4570 else
7a921c93 4571 num_q_vectors = 1;
7a921c93
AD		 4572
4573 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4574 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4575 adapter->q_vector[q_idx] = NULL;
91281fd3 4576 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4577 kfree(q_vector);
4578 }
4579}
4580
7b25cdba 4581static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4582{
4583 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4584 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4585 pci_disable_msix(adapter->pdev);
4586 kfree(adapter->msix_entries);
4587 adapter->msix_entries = NULL;
4588 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4589 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4590 pci_disable_msi(adapter->pdev);
4591 }
021230d4
AV		 4592}
4593
4594/**
4595 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4596 * @adapter: board private structure to initialize
4597 *
4598 * We determine which interrupt scheme to use based on...
4599 * - Kernel support (MSI, MSI-X)
4600 * - which can be user-defined (via MODULE_PARAM)
4601 * - Hardware queue count (num_*_queues)
4602 * - defined by miscellaneous hardware support/features (RSS, etc.)
4603 **/
2f90b865 4604int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4605{
4606 int err;
4607
4608 /* Number of supported queues */
4609 ixgbe_set_num_queues(adapter);
4610
021230d4
AV		 4611 err = ixgbe_set_interrupt_capability(adapter);
4612 if (err) {
849c4542 4613 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4614 goto err_set_interrupt;
9a799d71
AK		 4615 }
4616
7a921c93
AD		 4617 err = ixgbe_alloc_q_vectors(adapter);
4618 if (err) {
849c4542 4619 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4620 goto err_alloc_q_vectors;
4621 }
4622
4623 err = ixgbe_alloc_queues(adapter);
4624 if (err) {
849c4542 4625 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4626 goto err_alloc_queues;
4627 }
4628
849c4542 4629 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4630 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4631 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4632
4633 set_bit(__IXGBE_DOWN, &adapter->state);
4634
9a799d71 4635 return 0;
021230d4 4636
7a921c93
AD		 4637err_alloc_queues:
4638 ixgbe_free_q_vectors(adapter);
4639err_alloc_q_vectors:
4640 ixgbe_reset_interrupt_capability(adapter);
021230d4 4641err_set_interrupt:
7a921c93
AD		 4642 return err;
4643}
4644
4645/**
4646 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4647 * @adapter: board private structure to clear interrupt scheme on
4648 *
4649 * We go through and clear interrupt specific resources and reset the structure
4650 * to pre-load conditions
4651 **/
4652void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4653{
4a0b9ca0
PW		 4654 int i;
4655
4656 for (i = 0; i < adapter->num_tx_queues; i++) {
4657 kfree(adapter->tx_ring[i]);
4658 adapter->tx_ring[i] = NULL;
4659 }
4660 for (i = 0; i < adapter->num_rx_queues; i++) {
4661 kfree(adapter->rx_ring[i]);
4662 adapter->rx_ring[i] = NULL;
4663 }
7a921c93
AD		 4664
4665 ixgbe_free_q_vectors(adapter);
4666 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4667}
4668
c4900be0
DS		 4669/**
4670 * ixgbe_sfp_timer - worker thread to find a missing module
4671 * @data: pointer to our adapter struct
4672 **/
4673static void ixgbe_sfp_timer(unsigned long data)
4674{
4675 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4676
4df10466
JB		 4677 /*
4678 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4679 * delays that sfp+ detection requires
4680 */
4681 schedule_work(&adapter->sfp_task);
4682}
4683
4684/**
4685 * ixgbe_sfp_task - worker thread to find a missing module
4686 * @work: pointer to work_struct containing our data
4687 **/
4688static void ixgbe_sfp_task(struct work_struct *work)
4689{
4690 struct ixgbe_adapter *adapter = container_of(work,
4691 struct ixgbe_adapter,
4692 sfp_task);
4693 struct ixgbe_hw *hw = &adapter->hw;
4694
4695 if ((hw->phy.type == ixgbe_phy_nl) &&
4696 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4697 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4698 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4699 goto reschedule;
4700 ret = hw->phy.ops.reset(hw);
4701 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4702 e_dev_err("failed to initialize because an unsupported "
4703 "SFP+ module type was detected.\n");
4704 e_dev_err("Reload the driver after installing a "
4705 "supported module.\n");
c4900be0
DS		 4706 unregister_netdev(adapter->netdev);
4707 } else {
396e799c 4708 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4709 }
4710 /* don't need this routine any more */
4711 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4712 }
4713 return;
4714reschedule:
4715 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4716 mod_timer(&adapter->sfp_timer,
4717 round_jiffies(jiffies + (2 * HZ)));
4718}
4719
9a799d71
AK		 4720/**
4721 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4722 * @adapter: board private structure to initialize
4723 *
4724 * ixgbe_sw_init initializes the Adapter private data structure.
4725 * Fields are initialized based on PCI device information and
4726 * OS network device settings (MTU size).
4727 **/
4728static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4729{
4730 struct ixgbe_hw *hw = &adapter->hw;
4731 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4732 struct net_device *dev = adapter->netdev;
021230d4 4733 unsigned int rss;
7a6b6f51 4734#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4735 int j;
4736 struct tc_configuration *tc;
4737#endif
021230d4 4738
c44ade9e
JB		 4739 /* PCI config space info */
4740
4741 hw->vendor_id = pdev->vendor;
4742 hw->device_id = pdev->device;
4743 hw->revision_id = pdev->revision;
4744 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4745 hw->subsystem_device_id = pdev->subsystem_device;
4746
021230d4
AV		 4747 /* Set capability flags */
4748 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4749 adapter->ring_feature[RING_F_RSS].indices = rss;
4750 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4751 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4752 if (hw->mac.type == ixgbe_mac_82598EB) {
4753 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4754 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4755 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4756 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4757 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4758 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4759 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4760 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4761 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4762 if (dev->features & NETIF_F_NTUPLE) {
4763 /* Flow Director perfect filter enabled */
4764 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4765 adapter->atr_sample_rate = 0;
4766 spin_lock_init(&adapter->fdir_perfect_lock);
4767 } else {
4768 /* Flow Director hash filters enabled */
4769 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4770 adapter->atr_sample_rate = 20;
4771 }
c4cf55e5
PWJ		 4772 adapter->ring_feature[RING_F_FDIR].indices =
4773 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4774 adapter->fdir_pballoc = 0;
eacd73f7 4775#ifdef IXGBE_FCOE
0d551589
YZ		 4776 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4777 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4778 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4779#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4780 /* Default traffic class to use for FCoE */
4781 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4782 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4783#endif
eacd73f7 4784#endif /* IXGBE_FCOE */
f8212f97 4785 }
2f90b865 4786
7a6b6f51 4787#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4788 /* Configure DCB traffic classes */
4789 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4790 tc = &adapter->dcb_cfg.tc_config[j];
4791 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4792 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4793 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4794 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4795 tc->dcb_pfc = pfc_disabled;
4796 }
4797 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4798 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4799 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4800 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4801 adapter->dcb_cfg.round_robin_enable = false;
4802 adapter->dcb_set_bitmap = 0x00;
4803 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4804 adapter->ring_feature[RING_F_DCB].indices);
4805
4806#endif
9a799d71
AK		 4807
4808 /* default flow control settings */
cd7664f6 4809 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4810 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4811#ifdef CONFIG_DCB
4812 adapter->last_lfc_mode = hw->fc.current_mode;
4813#endif
2b9ade93
JB		 4814 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4815 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4816 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4817 hw->fc.send_xon = true;
71fd570b 4818 hw->fc.disable_fc_autoneg = false;
9a799d71 4819
30efa5a3 4820 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4821 adapter->rx_itr_setting = 1;
4822 adapter->rx_eitr_param = 20000;
4823 adapter->tx_itr_setting = 1;
4824 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4825
4826 /* set defaults for eitr in MegaBytes */
4827 adapter->eitr_low = 10;
4828 adapter->eitr_high = 20;
4829
4830 /* set default ring sizes */
4831 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4832 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4833
9a799d71 4834 /* initialize eeprom parameters */
c44ade9e 4835 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4836 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4837 return -EIO;
4838 }
4839
021230d4 4840 /* enable rx csum by default */
9a799d71
AK		 4841 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4842
1a6c14a2
JB		 4843 /* get assigned NUMA node */
4844 adapter->node = dev_to_node(&pdev->dev);
4845
9a799d71
AK		 4846 set_bit(__IXGBE_DOWN, &adapter->state);
4847
4848 return 0;
4849}
4850
4851/**
4852 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4853 * @adapter: board private structure
3a581073 4854 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4855 *
4856 * Return 0 on success, negative on failure
4857 **/
4858int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4859 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4860{
4861 struct pci_dev *pdev = adapter->pdev;
4862 int size;
4863
3a581073 4864 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4865 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4866 if (!tx_ring->tx_buffer_info)
4867 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4868 if (!tx_ring->tx_buffer_info)
4869 goto err;
3a581073 4870 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4871
4872 /* round up to nearest 4K */
12207e49 4873 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4874 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4875
1b507730
NN		 4876 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4877 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4878 if (!tx_ring->desc)
4879 goto err;
9a799d71 4880
3a581073
JB		 4881 tx_ring->next_to_use = 0;
4882 tx_ring->next_to_clean = 0;
4883 tx_ring->work_limit = tx_ring->count;
9a799d71 4884 return 0;
e01c31a5
JB		 4885
4886err:
4887 vfree(tx_ring->tx_buffer_info);
4888 tx_ring->tx_buffer_info = NULL;
396e799c 4889 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4890 return -ENOMEM;
9a799d71
AK		 4891}
4892
69888674
AD		 4893/**
4894 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4895 * @adapter: board private structure
4896 *
4897 * If this function returns with an error, then it's possible one or
4898 * more of the rings is populated (while the rest are not). It is the
4899 * callers duty to clean those orphaned rings.
4900 *
4901 * Return 0 on success, negative on failure
4902 **/
4903static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4904{
4905 int i, err = 0;
4906
4907 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4908 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4909 if (!err)
4910 continue;
396e799c 4911 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 4912 break;
4913 }
4914
4915 return err;
4916}
4917
9a799d71
AK		 4918/**
4919 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4920 * @adapter: board private structure
3a581073 4921 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4922 *
4923 * Returns 0 on success, negative on failure
4924 **/
4925int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4926 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4927{
4928 struct pci_dev *pdev = adapter->pdev;
021230d4 4929 int size;
9a799d71 4930
3a581073 4931 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4932 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4933 if (!rx_ring->rx_buffer_info)
4934 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4935 if (!rx_ring->rx_buffer_info) {
396e799c
ET		 4936 e_err(probe, "vmalloc allocation failed for the Rx "
4937 "descriptor ring\n");
177db6ff 4938 goto alloc_failed;
9a799d71 4939 }
3a581073 4940 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4941
9a799d71 4942 /* Round up to nearest 4K */
3a581073
JB		 4943 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4944 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4945
1b507730
NN		 4946 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4947 &rx_ring->dma, GFP_KERNEL);
9a799d71 4948
3a581073 4949 if (!rx_ring->desc) {
396e799c
ET		 4950 e_err(probe, "Memory allocation failed for the Rx "
4951 "descriptor ring\n");
3a581073 4952 vfree(rx_ring->rx_buffer_info);
177db6ff 4953 goto alloc_failed;
9a799d71
AK		 4954 }
4955
3a581073
JB		 4956 rx_ring->next_to_clean = 0;
4957 rx_ring->next_to_use = 0;
9a799d71
AK		 4958
4959 return 0;
177db6ff
MC		 4960
4961alloc_failed:
177db6ff 4962 return -ENOMEM;
9a799d71
AK		 4963}
4964
69888674
AD		 4965/**
4966 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4967 * @adapter: board private structure
4968 *
4969 * If this function returns with an error, then it's possible one or
4970 * more of the rings is populated (while the rest are not). It is the
4971 * callers duty to clean those orphaned rings.
4972 *
4973 * Return 0 on success, negative on failure
4974 **/
4975
4976static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4977{
4978 int i, err = 0;
4979
4980 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4981 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4982 if (!err)
4983 continue;
396e799c 4984 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 4985 break;
4986 }
4987
4988 return err;
4989}
4990
9a799d71
AK		 4991/**
4992 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4993 * @adapter: board private structure
4994 * @tx_ring: Tx descriptor ring for a specific queue
4995 *
4996 * Free all transmit software resources
4997 **/
c431f97e
JB		 4998void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4999 struct ixgbe_ring *tx_ring)
9a799d71
AK		 5000{
5001 struct pci_dev *pdev = adapter->pdev;
5002
5003 ixgbe_clean_tx_ring(adapter, tx_ring);
5004
5005 vfree(tx_ring->tx_buffer_info);
5006 tx_ring->tx_buffer_info = NULL;
5007
1b507730
NN		 5008 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5009 tx_ring->dma);
9a799d71
AK		 5010
5011 tx_ring->desc = NULL;
5012}
5013
5014/**
5015 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5016 * @adapter: board private structure
5017 *
5018 * Free all transmit software resources
5019 **/
5020static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5021{
5022 int i;
5023
5024 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 5025 if (adapter->tx_ring[i]->desc)
5026 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 5027}
5028
5029/**
b4617240 5030 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5031 * @adapter: board private structure
5032 * @rx_ring: ring to clean the resources from
5033 *
5034 * Free all receive software resources
5035 **/
c431f97e
JB		 5036void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5037 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5038{
5039 struct pci_dev *pdev = adapter->pdev;
5040
5041 ixgbe_clean_rx_ring(adapter, rx_ring);
5042
5043 vfree(rx_ring->rx_buffer_info);
5044 rx_ring->rx_buffer_info = NULL;
5045
1b507730
NN		 5046 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5047 rx_ring->dma);
9a799d71
AK		 5048
5049 rx_ring->desc = NULL;
5050}
5051
5052/**
5053 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5054 * @adapter: board private structure
5055 *
5056 * Free all receive software resources
5057 **/
5058static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5059{
5060 int i;
5061
5062 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 5063 if (adapter->rx_ring[i]->desc)
5064 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 5065}
5066
9a799d71
AK		 5067/**
5068 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5069 * @netdev: network interface device structure
5070 * @new_mtu: new value for maximum frame size
5071 *
5072 * Returns 0 on success, negative on failure
5073 **/
5074static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5075{
5076 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5077 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5078
42c783c5
JB		 5079 /* MTU < 68 is an error and causes problems on some kernels */
5080 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5081 return -EINVAL;
5082
396e799c 5083 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5084 /* must set new MTU before calling down or up */
9a799d71
AK		 5085 netdev->mtu = new_mtu;
5086
d4f80882
AV		 5087 if (netif_running(netdev))
5088 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5089
5090 return 0;
5091}
5092
5093/**
5094 * ixgbe_open - Called when a network interface is made active
5095 * @netdev: network interface device structure
5096 *
5097 * Returns 0 on success, negative value on failure
5098 *
5099 * The open entry point is called when a network interface is made
5100 * active by the system (IFF_UP). At this point all resources needed
5101 * for transmit and receive operations are allocated, the interrupt
5102 * handler is registered with the OS, the watchdog timer is started,
5103 * and the stack is notified that the interface is ready.
5104 **/
5105static int ixgbe_open(struct net_device *netdev)
5106{
5107 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5108 int err;
4bebfaa5
AK		 5109
5110 /* disallow open during test */
5111 if (test_bit(__IXGBE_TESTING, &adapter->state))
5112 return -EBUSY;
9a799d71 5113
54386467
JB		 5114 netif_carrier_off(netdev);
5115
9a799d71
AK		 5116 /* allocate transmit descriptors */
5117 err = ixgbe_setup_all_tx_resources(adapter);
5118 if (err)
5119 goto err_setup_tx;
5120
9a799d71
AK		 5121 /* allocate receive descriptors */
5122 err = ixgbe_setup_all_rx_resources(adapter);
5123 if (err)
5124 goto err_setup_rx;
5125
5126 ixgbe_configure(adapter);
5127
021230d4 5128 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5129 if (err)
5130 goto err_req_irq;
5131
9a799d71
AK		 5132 err = ixgbe_up_complete(adapter);
5133 if (err)
5134 goto err_up;
5135
d55b53ff
JK		 5136 netif_tx_start_all_queues(netdev);
5137
9a799d71
AK		 5138 return 0;
5139
5140err_up:
5eba3699 5141 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5142 ixgbe_free_irq(adapter);
5143err_req_irq:
9a799d71 5144err_setup_rx:
a20a1199 5145 ixgbe_free_all_rx_resources(adapter);
9a799d71 5146err_setup_tx:
a20a1199 5147 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5148 ixgbe_reset(adapter);
5149
5150 return err;
5151}
5152
5153/**
5154 * ixgbe_close - Disables a network interface
5155 * @netdev: network interface device structure
5156 *
5157 * Returns 0, this is not allowed to fail
5158 *
5159 * The close entry point is called when an interface is de-activated
5160 * by the OS. The hardware is still under the drivers control, but
5161 * needs to be disabled. A global MAC reset is issued to stop the
5162 * hardware, and all transmit and receive resources are freed.
5163 **/
5164static int ixgbe_close(struct net_device *netdev)
5165{
5166 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5167
5168 ixgbe_down(adapter);
5169 ixgbe_free_irq(adapter);
5170
5171 ixgbe_free_all_tx_resources(adapter);
5172 ixgbe_free_all_rx_resources(adapter);
5173
5eba3699 5174 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5175
5176 return 0;
5177}
5178
b3c8b4ba
AD		 5179#ifdef CONFIG_PM
5180static int ixgbe_resume(struct pci_dev *pdev)
5181{
5182 struct net_device *netdev = pci_get_drvdata(pdev);
5183 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5184 u32 err;
5185
5186 pci_set_power_state(pdev, PCI_D0);
5187 pci_restore_state(pdev);
656ab817
DS		 5188 /*
5189 * pci_restore_state clears dev->state_saved so call
5190 * pci_save_state to restore it.
5191 */
5192 pci_save_state(pdev);
9ce77666 5193
5194 err = pci_enable_device_mem(pdev);
b3c8b4ba 5195 if (err) {
849c4542 5196 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5197 return err;
5198 }
5199 pci_set_master(pdev);
5200
dd4d8ca6 5201 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5202
5203 err = ixgbe_init_interrupt_scheme(adapter);
5204 if (err) {
849c4542 5205 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5206 return err;
5207 }
5208
b3c8b4ba
AD		 5209 ixgbe_reset(adapter);
5210
495dce12
WJP		 5211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5212
b3c8b4ba
AD		 5213 if (netif_running(netdev)) {
5214 err = ixgbe_open(adapter->netdev);
5215 if (err)
5216 return err;
5217 }
5218
5219 netif_device_attach(netdev);
5220
5221 return 0;
5222}
b3c8b4ba 5223#endif /* CONFIG_PM */
9d8d05ae
RW		 5224
5225static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5226{
5227 struct net_device *netdev = pci_get_drvdata(pdev);
5228 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5229 struct ixgbe_hw *hw = &adapter->hw;
5230 u32 ctrl, fctrl;
5231 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5232#ifdef CONFIG_PM
5233 int retval = 0;
5234#endif
5235
5236 netif_device_detach(netdev);
5237
5238 if (netif_running(netdev)) {
5239 ixgbe_down(adapter);
5240 ixgbe_free_irq(adapter);
5241 ixgbe_free_all_tx_resources(adapter);
5242 ixgbe_free_all_rx_resources(adapter);
5243 }
b3c8b4ba
AD		 5244
5245#ifdef CONFIG_PM
5246 retval = pci_save_state(pdev);
5247 if (retval)
5248 return retval;
4df10466 5249
b3c8b4ba 5250#endif
e8e26350
PW		 5251 if (wufc) {
5252 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5253
e8e26350
PW		 5254 /* turn on all-multi mode if wake on multicast is enabled */
5255 if (wufc & IXGBE_WUFC_MC) {
5256 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5257 fctrl |= IXGBE_FCTRL_MPE;
5258 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5259 }
5260
5261 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5262 ctrl |= IXGBE_CTRL_GIO_DIS;
5263 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5264
5265 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5266 } else {
5267 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5268 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5269 }
5270
dd4d8ca6
DS		 5271 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5272 pci_wake_from_d3(pdev, true);
5273 else
5274 pci_wake_from_d3(pdev, false);
b3c8b4ba 5275
9d8d05ae
RW		 5276 *enable_wake = !!wufc;
5277
fa378134
AG		 5278 ixgbe_clear_interrupt_scheme(adapter);
5279
b3c8b4ba
AD		 5280 ixgbe_release_hw_control(adapter);
5281
5282 pci_disable_device(pdev);
5283
9d8d05ae
RW		 5284 return 0;
5285}
5286
5287#ifdef CONFIG_PM
5288static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5289{
5290 int retval;
5291 bool wake;
5292
5293 retval = __ixgbe_shutdown(pdev, &wake);
5294 if (retval)
5295 return retval;
5296
5297 if (wake) {
5298 pci_prepare_to_sleep(pdev);
5299 } else {
5300 pci_wake_from_d3(pdev, false);
5301 pci_set_power_state(pdev, PCI_D3hot);
5302 }
b3c8b4ba
AD		 5303
5304 return 0;
5305}
9d8d05ae 5306#endif /* CONFIG_PM */
b3c8b4ba
AD		 5307
5308static void ixgbe_shutdown(struct pci_dev *pdev)
5309{
9d8d05ae
RW		 5310 bool wake;
5311
5312 __ixgbe_shutdown(pdev, &wake);
5313
5314 if (system_state == SYSTEM_POWER_OFF) {
5315 pci_wake_from_d3(pdev, wake);
5316 pci_set_power_state(pdev, PCI_D3hot);
5317 }
b3c8b4ba
AD		 5318}
5319
9a799d71
AK		 5320/**
5321 * ixgbe_update_stats - Update the board statistics counters.
5322 * @adapter: board private structure
5323 **/
5324void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5325{
2d86f139 5326 struct net_device *netdev = adapter->netdev;
9a799d71 5327 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5328 u64 total_mpc = 0;
5329 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5330 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 5331
d08935c2
DS		 5332 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5333 test_bit(__IXGBE_RESETTING, &adapter->state))
5334 return;
5335
94b982b2 5336 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5337 u64 rsc_count = 0;
94b982b2 5338 u64 rsc_flush = 0;
d51019a4
PW		 5339 for (i = 0; i < 16; i++)
5340 adapter->hw_rx_no_dma_resources +=
5341 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5342 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5343 rsc_count += adapter->rx_ring[i]->rsc_count;
5344 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5345 }
5346 adapter->rsc_total_count = rsc_count;
5347 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5348 }
5349
7ca3bc58
JB		 5350 /* gather some stats to the adapter struct that are per queue */
5351 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5352 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5353 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5354
5355 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5356 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5357 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5358
9a799d71 5359 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5360 for (i = 0; i < 8; i++) {
5361 /* for packet buffers not used, the register should read 0 */
5362 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5363 missed_rx += mpc;
5364 adapter->stats.mpc[i] += mpc;
5365 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 5366 if (hw->mac.type == ixgbe_mac_82598EB)
5367 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 5368 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5369 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5370 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5371 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 5372 if (hw->mac.type == ixgbe_mac_82599EB) {
5373 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5374 IXGBE_PXONRXCNT(i));
5375 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5376 IXGBE_PXOFFRXCNT(i));
5377 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 5378 } else {
5379 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5380 IXGBE_PXONRXC(i));
5381 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5382 IXGBE_PXOFFRXC(i));
5383 }
2f90b865
AD		 5384 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5385 IXGBE_PXONTXC(i));
2f90b865 5386 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 5387 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 5388 }
5389 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5390 /* work around hardware counting issue */
5391 adapter->stats.gprc -= missed_rx;
5392
5393 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5394 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5395 u64 tmp;
e8e26350 5396 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 5397 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5398 adapter->stats.gorc += (tmp << 32);
e8e26350 5399 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 5400 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5401 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 5402 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5403 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5404 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5405 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 5406 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5407 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 5408#ifdef IXGBE_FCOE
5409 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5410 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5411 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5412 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5413 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5414 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5415#endif /* IXGBE_FCOE */
e8e26350
PW		 5416 } else {
5417 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5418 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5419 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5420 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5421 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5422 }
9a799d71
AK		 5423 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5424 adapter->stats.bprc += bprc;
5425 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 5426 if (hw->mac.type == ixgbe_mac_82598EB)
5427 adapter->stats.mprc -= bprc;
9a799d71
AK		 5428 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5429 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5430 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5431 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5432 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5433 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5434 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 5435 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 5436 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5437 adapter->stats.lxontxc += lxon;
5438 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5439 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 5440 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5441 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 5442 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5443 /*
5444 * 82598 errata - tx of flow control packets is included in tx counters
5445 */
5446 xon_off_tot = lxon + lxoff;
5447 adapter->stats.gptc -= xon_off_tot;
5448 adapter->stats.mptc -= xon_off_tot;
5449 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 5450 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5451 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5452 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 5453 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5454 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 5455 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 5456 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5457 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5458 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5459 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5460 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 5461 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5462
5463 /* Fill out the OS statistics structure */
2d86f139 5464 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 5465
5466 /* Rx Errors */
2d86f139 5467 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 5468 adapter->stats.rlec;
2d86f139
AK		 5469 netdev->stats.rx_dropped = 0;
5470 netdev->stats.rx_length_errors = adapter->stats.rlec;
5471 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5472 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5473}
5474
5475/**
5476 * ixgbe_watchdog - Timer Call-back
5477 * @data: pointer to adapter cast into an unsigned long
5478 **/
5479static void ixgbe_watchdog(unsigned long data)
5480{
5481 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5482 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5483 u64 eics = 0;
5484 int i;
cf8280ee 5485
fe49f04a
AD		 5486 /*
5487 * Do the watchdog outside of interrupt context due to the lovely
5488 * delays that some of the newer hardware requires
5489 */
22d5a71b 5490
fe49f04a
AD		 5491 if (test_bit(__IXGBE_DOWN, &adapter->state))
5492 goto watchdog_short_circuit;
22d5a71b 5493
fe49f04a
AD		 5494 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5495 /*
5496 * for legacy and MSI interrupts don't set any bits
5497 * that are enabled for EIAM, because this operation
5498 * would set *both* EIMS and EICS for any bit in EIAM
5499 */
5500 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5501 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5502 goto watchdog_reschedule;
5503 }
5504
5505 /* get one bit for every active tx/rx interrupt vector */
5506 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5507 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5508 if (qv->rxr_count || qv->txr_count)
5509 eics |= ((u64)1 << i);
cf8280ee 5510 }
9a799d71 5511
fe49f04a
AD		 5512 /* Cause software interrupt to ensure rx rings are cleaned */
5513 ixgbe_irq_rearm_queues(adapter, eics);
5514
5515watchdog_reschedule:
5516 /* Reset the timer */
5517 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5518
5519watchdog_short_circuit:
cf8280ee
JB		 5520 schedule_work(&adapter->watchdog_task);
5521}
5522
e8e26350
PW		 5523/**
5524 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5525 * @work: pointer to work_struct containing our data
5526 **/
5527static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5528{
5529 struct ixgbe_adapter *adapter = container_of(work,
5530 struct ixgbe_adapter,
5531 multispeed_fiber_task);
5532 struct ixgbe_hw *hw = &adapter->hw;
5533 u32 autoneg;
8620a103 5534 bool negotiation;
e8e26350
PW		 5535
5536 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5537 autoneg = hw->phy.autoneg_advertised;
5538 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5539 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5540 hw->mac.autotry_restart = false;
8620a103
MC		 5541 if (hw->mac.ops.setup_link)
5542 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5543 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5544 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5545}
5546
5547/**
5548 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5549 * @work: pointer to work_struct containing our data
5550 **/
5551static void ixgbe_sfp_config_module_task(struct work_struct *work)
5552{
5553 struct ixgbe_adapter *adapter = container_of(work,
5554 struct ixgbe_adapter,
5555 sfp_config_module_task);
5556 struct ixgbe_hw *hw = &adapter->hw;
5557 u32 err;
5558
5559 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5560
5561 /* Time for electrical oscillations to settle down */
5562 msleep(100);
e8e26350 5563 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5564
e8e26350 5565 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5566 e_dev_err("failed to initialize because an unsupported SFP+ "
5567 "module type was detected.\n");
5568 e_dev_err("Reload the driver after installing a supported "
5569 "module.\n");
63d6e1d8 5570 unregister_netdev(adapter->netdev);
e8e26350
PW		 5571 return;
5572 }
5573 hw->mac.ops.setup_sfp(hw);
5574
8d1c3c07 5575 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5576 /* This will also work for DA Twinax connections */
5577 schedule_work(&adapter->multispeed_fiber_task);
5578 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5579}
5580
c4cf55e5
PWJ		 5581/**
5582 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5583 * @work: pointer to work_struct containing our data
5584 **/
5585static void ixgbe_fdir_reinit_task(struct work_struct *work)
5586{
5587 struct ixgbe_adapter *adapter = container_of(work,
5588 struct ixgbe_adapter,
5589 fdir_reinit_task);
5590 struct ixgbe_hw *hw = &adapter->hw;
5591 int i;
5592
5593 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5594 for (i = 0; i < adapter->num_tx_queues; i++)
5595 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5596 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 5597 } else {
396e799c 5598 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5599 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5600 }
5601 /* Done FDIR Re-initialization, enable transmits */
5602 netif_tx_start_all_queues(adapter->netdev);
5603}
5604
10eec955
JF		 5605static DEFINE_MUTEX(ixgbe_watchdog_lock);
5606
cf8280ee 5607/**
69888674
AD		 5608 * ixgbe_watchdog_task - worker thread to bring link up
5609 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5610 **/
5611static void ixgbe_watchdog_task(struct work_struct *work)
5612{
5613 struct ixgbe_adapter *adapter = container_of(work,
5614 struct ixgbe_adapter,
5615 watchdog_task);
5616 struct net_device *netdev = adapter->netdev;
5617 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5618 u32 link_speed;
5619 bool link_up;
bc59fcda
NS		 5620 int i;
5621 struct ixgbe_ring *tx_ring;
5622 int some_tx_pending = 0;
cf8280ee 5623
10eec955
JF		 5624 mutex_lock(&ixgbe_watchdog_lock);
5625
5626 link_up = adapter->link_up;
5627 link_speed = adapter->link_speed;
cf8280ee
JB		 5628
5629 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5630 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5631 if (link_up) {
5632#ifdef CONFIG_DCB
5633 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5634 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5635 hw->mac.ops.fc_enable(hw, i);
264857b8 5636 } else {
620fa036 5637 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5638 }
5639#else
620fa036 5640 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5641#endif
5642 }
5643
cf8280ee
JB		 5644 if (link_up ||
5645 time_after(jiffies, (adapter->link_check_timeout +
5646 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5647 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5648 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5649 }
5650 adapter->link_up = link_up;
5651 adapter->link_speed = link_speed;
5652 }
9a799d71
AK		 5653
5654 if (link_up) {
5655 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5656 bool flow_rx, flow_tx;
5657
5658 if (hw->mac.type == ixgbe_mac_82599EB) {
5659 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5660 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5661 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5662 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5663 } else {
5664 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5665 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5666 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5667 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5668 }
5669
396e799c 5670 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5671 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5672 "10 Gbps" :
5673 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5674 "1 Gbps" : "unknown speed")),
e8e26350 5675 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5676 (flow_rx ? "RX" :
5677 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5678
5679 netif_carrier_on(netdev);
9a799d71
AK		 5680 } else {
5681 /* Force detection of hung controller */
5682 adapter->detect_tx_hung = true;
5683 }
5684 } else {
cf8280ee
JB		 5685 adapter->link_up = false;
5686 adapter->link_speed = 0;
9a799d71 5687 if (netif_carrier_ok(netdev)) {
396e799c 5688 e_info(drv, "NIC Link is Down\n");
9a799d71 5689 netif_carrier_off(netdev);
9a799d71
AK		 5690 }
5691 }
5692
bc59fcda
NS		 5693 if (!netif_carrier_ok(netdev)) {
5694 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5695 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5696 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5697 some_tx_pending = 1;
5698 break;
5699 }
5700 }
5701
5702 if (some_tx_pending) {
5703 /* We've lost link, so the controller stops DMA,
5704 * but we've got queued Tx work that's never going
5705 * to get done, so reset controller to flush Tx.
5706 * (Do the reset outside of interrupt context).
5707 */
5708 schedule_work(&adapter->reset_task);
5709 }
5710 }
5711
9a799d71 5712 ixgbe_update_stats(adapter);
10eec955 5713 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5714}
5715
9a799d71 5716static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5717 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5718 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5719{
5720 struct ixgbe_adv_tx_context_desc *context_desc;
5721 unsigned int i;
5722 int err;
5723 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5724 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5725 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5726
5727 if (skb_is_gso(skb)) {
5728 if (skb_header_cloned(skb)) {
5729 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5730 if (err)
5731 return err;
5732 }
5733 l4len = tcp_hdrlen(skb);
5734 *hdr_len += l4len;
5735
8327d000 5736 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5737 struct iphdr *iph = ip_hdr(skb);
5738 iph->tot_len = 0;
5739 iph->check = 0;
5740 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5741 iph->daddr, 0,
5742 IPPROTO_TCP,
5743 0);
8e1e8a47 5744 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5745 ipv6_hdr(skb)->payload_len = 0;
5746 tcp_hdr(skb)->check =
5747 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5748 &ipv6_hdr(skb)->daddr,
5749 0, IPPROTO_TCP, 0);
9a799d71
AK		 5750 }
5751
5752 i = tx_ring->next_to_use;
5753
5754 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5755 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5756
5757 /* VLAN MACLEN IPLEN */
5758 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5759 vlan_macip_lens |=
5760 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5761 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5762 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5763 *hdr_len += skb_network_offset(skb);
5764 vlan_macip_lens |=
5765 (skb_transport_header(skb) - skb_network_header(skb));
5766 *hdr_len +=
5767 (skb_transport_header(skb) - skb_network_header(skb));
5768 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5769 context_desc->seqnum_seed = 0;
5770
5771 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5772 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5773 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5774
8327d000 5775 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5776 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5777 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5778 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5779
5780 /* MSS L4LEN IDX */
9f8cdf4f 5781 mss_l4len_idx =
9a799d71
AK		 5782 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5783 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5784 /* use index 1 for TSO */
5785 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5786 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5787
5788 tx_buffer_info->time_stamp = jiffies;
5789 tx_buffer_info->next_to_watch = i;
5790
5791 i++;
5792 if (i == tx_ring->count)
5793 i = 0;
5794 tx_ring->next_to_use = i;
5795
5796 return true;
5797 }
5798 return false;
5799}
5800
5801static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5802 struct ixgbe_ring *tx_ring,
5803 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5804{
5805 struct ixgbe_adv_tx_context_desc *context_desc;
5806 unsigned int i;
5807 struct ixgbe_tx_buffer *tx_buffer_info;
5808 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5809
5810 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5811 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5812 i = tx_ring->next_to_use;
5813 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5814 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5815
5816 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5817 vlan_macip_lens |=
5818 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5819 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5820 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5821 if (skb->ip_summed == CHECKSUM_PARTIAL)
5822 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5823 skb_network_header(skb));
9a799d71
AK		 5824
5825 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5826 context_desc->seqnum_seed = 0;
5827
5828 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5829 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5830
5831 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5832 __be16 protocol;
5833
5834 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5835 const struct vlan_ethhdr *vhdr =
5836 (const struct vlan_ethhdr *)skb->data;
5837
5838 protocol = vhdr->h_vlan_encapsulated_proto;
5839 } else {
5840 protocol = skb->protocol;
5841 }
5842
5843 switch (protocol) {
09640e63 5844 case cpu_to_be16(ETH_P_IP):
9a799d71 5845 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5846 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5847 type_tucmd_mlhl |=
b4617240 5848 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5849 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5850 type_tucmd_mlhl |=
5851 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5852 break;
09640e63 5853 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5854 /* XXX what about other V6 headers?? */
5855 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5856 type_tucmd_mlhl |=
b4617240 5857 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5858 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5859 type_tucmd_mlhl |=
5860 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5861 break;
41825d71
AK		 5862 default:
5863 if (unlikely(net_ratelimit())) {
396e799c
ET		 5864 e_warn(probe, "partial checksum "
5865 "but proto=%x!\n",
5866 skb->protocol);
41825d71
AK		 5867 }
5868 break;
5869 }
9a799d71
AK		 5870 }
5871
5872 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5873 /* use index zero for tx checksum offload */
9a799d71
AK		 5874 context_desc->mss_l4len_idx = 0;
5875
5876 tx_buffer_info->time_stamp = jiffies;
5877 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5878
9a799d71
AK		 5879 i++;
5880 if (i == tx_ring->count)
5881 i = 0;
5882 tx_ring->next_to_use = i;
5883
5884 return true;
5885 }
9f8cdf4f 5886
9a799d71
AK		 5887 return false;
5888}
5889
5890static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5891 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5892 struct sk_buff *skb, u32 tx_flags,
5893 unsigned int first)
9a799d71 5894{
e5a43549 5895 struct pci_dev *pdev = adapter->pdev;
9a799d71 5896 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5897 unsigned int len;
5898 unsigned int total = skb->len;
9a799d71
AK		 5899 unsigned int offset = 0, size, count = 0, i;
5900 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5901 unsigned int f;
9a799d71
AK		 5902
5903 i = tx_ring->next_to_use;
5904
eacd73f7
YZ		 5905 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5906 /* excluding fcoe_crc_eof for FCoE */
5907 total -= sizeof(struct fcoe_crc_eof);
5908
5909 len = min(skb_headlen(skb), total);
9a799d71
AK		 5910 while (len) {
5911 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5912 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5913
5914 tx_buffer_info->length = size;
e5a43549 5915 tx_buffer_info->mapped_as_page = false;
1b507730 5916 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 5917 skb->data + offset,
1b507730
NN		 5918 size, DMA_TO_DEVICE);
5919 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5920 goto dma_error;
9a799d71
AK		 5921 tx_buffer_info->time_stamp = jiffies;
5922 tx_buffer_info->next_to_watch = i;
5923
5924 len -= size;
eacd73f7 5925 total -= size;
9a799d71
AK		 5926 offset += size;
5927 count++;
44df32c5
AD		 5928
5929 if (len) {
5930 i++;
5931 if (i == tx_ring->count)
5932 i = 0;
5933 }
9a799d71
AK		 5934 }
5935
5936 for (f = 0; f < nr_frags; f++) {
5937 struct skb_frag_struct *frag;
5938
5939 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5940 len = min((unsigned int)frag->size, total);
e5a43549 5941 offset = frag->page_offset;
9a799d71
AK		 5942
5943 while (len) {
44df32c5
AD		 5944 i++;
5945 if (i == tx_ring->count)
5946 i = 0;
5947
9a799d71
AK		 5948 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5949 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5950
5951 tx_buffer_info->length = size;
1b507730 5952 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 5953 frag->page,
5954 offset, size,
1b507730 5955 DMA_TO_DEVICE);
e5a43549 5956 tx_buffer_info->mapped_as_page = true;
1b507730 5957 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5958 goto dma_error;
9a799d71
AK		 5959 tx_buffer_info->time_stamp = jiffies;
5960 tx_buffer_info->next_to_watch = i;
5961
5962 len -= size;
eacd73f7 5963 total -= size;
9a799d71
AK		 5964 offset += size;
5965 count++;
9a799d71 5966 }
eacd73f7
YZ		 5967 if (total == 0)
5968 break;
9a799d71 5969 }
44df32c5 5970
9a799d71
AK		 5971 tx_ring->tx_buffer_info[i].skb = skb;
5972 tx_ring->tx_buffer_info[first].next_to_watch = i;
5973
e5a43549
AD		 5974 return count;
5975
5976dma_error:
849c4542 5977 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 5978
5979 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5980 tx_buffer_info->dma = 0;
5981 tx_buffer_info->time_stamp = 0;
5982 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5983 if (count)
5984 count--;
e5a43549
AD		 5985
5986 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5987 while (count--) {
5988 if (i==0)
e5a43549 5989 i += tx_ring->count;
c1fa347f 5990 i--;
e5a43549
AD		 5991 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5992 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5993 }
5994
e44d38e1 5995 return 0;
9a799d71
AK		 5996}
5997
5998static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5999 struct ixgbe_ring *tx_ring,
6000 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6001{
6002 union ixgbe_adv_tx_desc *tx_desc = NULL;
6003 struct ixgbe_tx_buffer *tx_buffer_info;
6004 u32 olinfo_status = 0, cmd_type_len = 0;
6005 unsigned int i;
6006 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6007
6008 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6009
6010 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6011
6012 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6013 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6014
6015 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6016 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6017
6018 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 6019 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6020
4eeae6fd
PW		 6021 /* use index 1 context for tso */
6022 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6023 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6024 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 6025 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6026
6027 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6028 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 6029 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6030
eacd73f7
YZ		 6031 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6032 olinfo_status |= IXGBE_ADVTXD_CC;
6033 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6034 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6035 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6036 }
6037
9a799d71
AK		 6038 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6039
6040 i = tx_ring->next_to_use;
6041 while (count--) {
6042 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6043 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6044 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6045 tx_desc->read.cmd_type_len =
b4617240 6046 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6047 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6048 i++;
6049 if (i == tx_ring->count)
6050 i = 0;
6051 }
6052
6053 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6054
6055 /*
6056 * Force memory writes to complete before letting h/w
6057 * know there are new descriptors to fetch. (Only
6058 * applicable for weak-ordered memory model archs,
6059 * such as IA-64).
6060 */
6061 wmb();
6062
6063 tx_ring->next_to_use = i;
6064 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6065}
6066
c4cf55e5
PWJ		 6067static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6068 int queue, u32 tx_flags)
6069{
c4cf55e5
PWJ		 6070 struct ixgbe_atr_input atr_input;
6071 struct tcphdr *th;
c4cf55e5
PWJ		 6072 struct iphdr *iph = ip_hdr(skb);
6073 struct ethhdr *eth = (struct ethhdr *)skb->data;
6074 u16 vlan_id, src_port, dst_port, flex_bytes;
6075 u32 src_ipv4_addr, dst_ipv4_addr;
6076 u8 l4type = 0;
6077
d3ead241
GG		 6078 /* Right now, we support IPv4 only */
6079 if (skb->protocol != htons(ETH_P_IP))
6080 return;
c4cf55e5
PWJ		 6081 /* check if we're UDP or TCP */
6082 if (iph->protocol == IPPROTO_TCP) {
6083 th = tcp_hdr(skb);
6084 src_port = th->source;
6085 dst_port = th->dest;
6086 l4type |= IXGBE_ATR_L4TYPE_TCP;
6087 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6088 } else {
6089 /* Unsupported L4 header, just bail here */
6090 return;
6091 }
6092
6093 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6094
6095 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6096 IXGBE_TX_FLAGS_VLAN_SHIFT;
6097 src_ipv4_addr = iph->saddr;
6098 dst_ipv4_addr = iph->daddr;
6099 flex_bytes = eth->h_proto;
6100
6101 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6102 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6103 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6104 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6105 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6106 /* src and dst are inverted, think how the receiver sees them */
6107 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6108 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6109
6110 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6111 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6112}
6113
e092be60 6114static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 6115 struct ixgbe_ring *tx_ring, int size)
e092be60 6116{
30eba97a 6117 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6118 /* Herbert's original patch had:
6119 * smp_mb__after_netif_stop_queue();
6120 * but since that doesn't exist yet, just open code it. */
6121 smp_mb();
6122
6123 /* We need to check again in a case another CPU has just
6124 * made room available. */
6125 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6126 return -EBUSY;
6127
6128 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6129 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6130 ++tx_ring->restart_queue;
e092be60
AV		 6131 return 0;
6132}
6133
6134static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 6135 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6136{
6137 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6138 return 0;
6139 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6140}
6141
09a3b1f8
SH		 6142static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6143{
6144 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6145 int txq = smp_processor_id();
09a3b1f8 6146
56075a98
JF		 6147#ifdef IXGBE_FCOE
6148 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6149 (skb->protocol == htons(ETH_P_FIP))) {
6150 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6151 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6152 txq += adapter->ring_feature[RING_F_FCOE].mask;
6153 return txq;
4bc091d8 6154#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6155 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6156 txq = adapter->fcoe.up;
6157 return txq;
4bc091d8 6158#endif
56075a98
JF		 6159 }
6160 }
6161#endif
6162
fdd3d631
KK		 6163 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6164 while (unlikely(txq >= dev->real_num_tx_queues))
6165 txq -= dev->real_num_tx_queues;
5f715823 6166 return txq;
fdd3d631 6167 }
c4cf55e5 6168
2ea186ae
JF		 6169 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6170 if (skb->priority == TC_PRIO_CONTROL)
6171 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6172 else
6173 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6174 >> 13;
6175 return txq;
6176 }
09a3b1f8
SH		 6177
6178 return skb_tx_hash(dev, skb);
6179}
6180
3b29a56d
SH		 6181static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6182 struct net_device *netdev)
9a799d71
AK		 6183{
6184 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6185 struct ixgbe_ring *tx_ring;
60d51134 6186 struct netdev_queue *txq;
9a799d71
AK		 6187 unsigned int first;
6188 unsigned int tx_flags = 0;
30eba97a 6189 u8 hdr_len = 0;
5f715823 6190 int tso;
9a799d71
AK		 6191 int count = 0;
6192 unsigned int f;
9f8cdf4f 6193
9f8cdf4f
JB		 6194 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6195 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6196 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6197 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6198 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6199 }
6200 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6201 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6202 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6203 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6204 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6205 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6206 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6207 }
eacd73f7 6208
4a0b9ca0 6209 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 6210
09ad1cc0 6211#ifdef IXGBE_FCOE
56075a98
JF		 6212 /* for FCoE with DCB, we force the priority to what
6213 * was specified by the switch */
6214 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6215 (skb->protocol == htons(ETH_P_FCOE) ||
6216 skb->protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6217#ifdef CONFIG_IXGBE_DCB
6218 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6219 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6220 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6221 tx_flags |= ((adapter->fcoe.up << 13)
6222 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6223 }
6224#endif
ca77cd59
RL		 6225 /* flag for FCoE offloads */
6226 if (skb->protocol == htons(ETH_P_FCOE))
6227 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6228 }
ca77cd59
RL		 6229#endif
6230
eacd73f7 6231 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6232 if (skb_is_gso(skb) ||
6233 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6234 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6235 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6236 count++;
6237
9f8cdf4f
JB		 6238 count += TXD_USE_COUNT(skb_headlen(skb));
6239 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6240 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6241
e092be60 6242 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6243 adapter->tx_busy++;
9a799d71
AK		 6244 return NETDEV_TX_BUSY;
6245 }
9a799d71 6246
9a799d71 6247 first = tx_ring->next_to_use;
eacd73f7
YZ		 6248 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6249#ifdef IXGBE_FCOE
6250 /* setup tx offload for FCoE */
6251 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6252 if (tso < 0) {
6253 dev_kfree_skb_any(skb);
6254 return NETDEV_TX_OK;
6255 }
6256 if (tso)
6257 tx_flags |= IXGBE_TX_FLAGS_FSO;
6258#endif /* IXGBE_FCOE */
6259 } else {
6260 if (skb->protocol == htons(ETH_P_IP))
6261 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6262 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6263 if (tso < 0) {
6264 dev_kfree_skb_any(skb);
6265 return NETDEV_TX_OK;
6266 }
9a799d71 6267
eacd73f7
YZ		 6268 if (tso)
6269 tx_flags |= IXGBE_TX_FLAGS_TSO;
6270 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6271 (skb->ip_summed == CHECKSUM_PARTIAL))
6272 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6273 }
9a799d71 6274
eacd73f7 6275 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 6276 if (count) {
c4cf55e5
PWJ		 6277 /* add the ATR filter if ATR is on */
6278 if (tx_ring->atr_sample_rate) {
6279 ++tx_ring->atr_count;
6280 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6281 test_bit(__IXGBE_FDIR_INIT_DONE,
6282 &tx_ring->reinit_state)) {
6283 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6284 tx_flags);
6285 tx_ring->atr_count = 0;
6286 }
6287 }
60d51134
ED		 6288 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6289 txq->tx_bytes += skb->len;
6290 txq->tx_packets++;
44df32c5
AD		 6291 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6292 hdr_len);
44df32c5 6293 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6294
44df32c5
AD		 6295 } else {
6296 dev_kfree_skb_any(skb);
6297 tx_ring->tx_buffer_info[first].time_stamp = 0;
6298 tx_ring->next_to_use = first;
6299 }
9a799d71
AK		 6300
6301 return NETDEV_TX_OK;
6302}
6303
9a799d71
AK		 6304/**
6305 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6306 * @netdev: network interface device structure
6307 * @p: pointer to an address structure
6308 *
6309 * Returns 0 on success, negative on failure
6310 **/
6311static int ixgbe_set_mac(struct net_device *netdev, void *p)
6312{
6313 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6314 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6315 struct sockaddr *addr = p;
6316
6317 if (!is_valid_ether_addr(addr->sa_data))
6318 return -EADDRNOTAVAIL;
6319
6320 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6321 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6322
1cdd1ec8
GR		 6323 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6324 IXGBE_RAH_AV);
9a799d71
AK		 6325
6326 return 0;
6327}
6328
6b73e10d
BH		 6329static int
6330ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6331{
6332 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6333 struct ixgbe_hw *hw = &adapter->hw;
6334 u16 value;
6335 int rc;
6336
6337 if (prtad != hw->phy.mdio.prtad)
6338 return -EINVAL;
6339 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6340 if (!rc)
6341 rc = value;
6342 return rc;
6343}
6344
6345static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6346 u16 addr, u16 value)
6347{
6348 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6349 struct ixgbe_hw *hw = &adapter->hw;
6350
6351 if (prtad != hw->phy.mdio.prtad)
6352 return -EINVAL;
6353 return hw->phy.ops.write_reg(hw, addr, devad, value);
6354}
6355
6356static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6357{
6358 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6359
6360 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6361}
6362
0365e6e4
PW		 6363/**
6364 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6365 * netdev->dev_addrs
0365e6e4
PW		 6366 * @netdev: network interface device structure
6367 *
6368 * Returns non-zero on failure
6369 **/
6370static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6371{
6372 int err = 0;
6373 struct ixgbe_adapter *adapter = netdev_priv(dev);
6374 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6375
6376 if (is_valid_ether_addr(mac->san_addr)) {
6377 rtnl_lock();
6378 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6379 rtnl_unlock();
6380 }
6381 return err;
6382}
6383
6384/**
6385 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6386 * netdev->dev_addrs
0365e6e4
PW		 6387 * @netdev: network interface device structure
6388 *
6389 * Returns non-zero on failure
6390 **/
6391static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6392{
6393 int err = 0;
6394 struct ixgbe_adapter *adapter = netdev_priv(dev);
6395 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6396
6397 if (is_valid_ether_addr(mac->san_addr)) {
6398 rtnl_lock();
6399 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6400 rtnl_unlock();
6401 }
6402 return err;
6403}
6404
9a799d71
AK		 6405#ifdef CONFIG_NET_POLL_CONTROLLER
6406/*
6407 * Polling 'interrupt' - used by things like netconsole to send skbs
6408 * without having to re-enable interrupts. It's not called while
6409 * the interrupt routine is executing.
6410 */
6411static void ixgbe_netpoll(struct net_device *netdev)
6412{
6413 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6414 int i;
9a799d71 6415
1a647bd2
AD		 6416 /* if interface is down do nothing */
6417 if (test_bit(__IXGBE_DOWN, &adapter->state))
6418 return;
6419
9a799d71 6420 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6421 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6422 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6423 for (i = 0; i < num_q_vectors; i++) {
6424 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6425 ixgbe_msix_clean_many(0, q_vector);
6426 }
6427 } else {
6428 ixgbe_intr(adapter->pdev->irq, netdev);
6429 }
9a799d71 6430 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6431}
6432#endif
6433
0edc3527
SH		 6434static const struct net_device_ops ixgbe_netdev_ops = {
6435 .ndo_open = ixgbe_open,
6436 .ndo_stop = ixgbe_close,
00829823 6437 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6438 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6439 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6440 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6441 .ndo_validate_addr = eth_validate_addr,
6442 .ndo_set_mac_address = ixgbe_set_mac,
6443 .ndo_change_mtu = ixgbe_change_mtu,
6444 .ndo_tx_timeout = ixgbe_tx_timeout,
6445 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6446 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6447 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6448 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6449 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6450 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6451 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6452 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
0edc3527
SH		 6453#ifdef CONFIG_NET_POLL_CONTROLLER
6454 .ndo_poll_controller = ixgbe_netpoll,
6455#endif
332d4a7d
YZ		 6456#ifdef IXGBE_FCOE
6457 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6458 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6459 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6460 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6461 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6462#endif /* IXGBE_FCOE */
0edc3527
SH		 6463};
6464
1cdd1ec8
GR		 6465static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6466 const struct ixgbe_info *ii)
6467{
6468#ifdef CONFIG_PCI_IOV
6469 struct ixgbe_hw *hw = &adapter->hw;
6470 int err;
6471
6472 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6473 return;
6474
6475 /* The 82599 supports up to 64 VFs per physical function
6476 * but this implementation limits allocation to 63 so that
6477 * basic networking resources are still available to the
6478 * physical function
6479 */
6480 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6481 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6482 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6483 if (err) {
396e799c 6484 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6485 goto err_novfs;
6486 }
6487 /* If call to enable VFs succeeded then allocate memory
6488 * for per VF control structures.
6489 */
6490 adapter->vfinfo =
6491 kcalloc(adapter->num_vfs,
6492 sizeof(struct vf_data_storage), GFP_KERNEL);
6493 if (adapter->vfinfo) {
6494 /* Now that we're sure SR-IOV is enabled
6495 * and memory allocated set up the mailbox parameters
6496 */
6497 ixgbe_init_mbx_params_pf(hw);
6498 memcpy(&hw->mbx.ops, ii->mbx_ops,
6499 sizeof(hw->mbx.ops));
6500
6501 /* Disable RSC when in SR-IOV mode */
6502 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6503 IXGBE_FLAG2_RSC_ENABLED);
6504 return;
6505 }
6506
6507 /* Oh oh */
396e799c
ET		 6508 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6509 "SRIOV disabled\n");
1cdd1ec8
GR		 6510 pci_disable_sriov(adapter->pdev);
6511
6512err_novfs:
6513 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6514 adapter->num_vfs = 0;
6515#endif /* CONFIG_PCI_IOV */
6516}
6517
9a799d71
AK		 6518/**
6519 * ixgbe_probe - Device Initialization Routine
6520 * @pdev: PCI device information struct
6521 * @ent: entry in ixgbe_pci_tbl
6522 *
6523 * Returns 0 on success, negative on failure
6524 *
6525 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6526 * The OS initialization, configuring of the adapter private structure,
6527 * and a hardware reset occur.
6528 **/
6529static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6530 const struct pci_device_id *ent)
9a799d71
AK		 6531{
6532 struct net_device *netdev;
6533 struct ixgbe_adapter *adapter = NULL;
6534 struct ixgbe_hw *hw;
6535 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6536 static int cards_found;
6537 int i, err, pci_using_dac;
c85a2618 6538 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6539#ifdef IXGBE_FCOE
6540 u16 device_caps;
6541#endif
c44ade9e 6542 u32 part_num, eec;
9a799d71 6543
bded64a7
AG		 6544 /* Catch broken hardware that put the wrong VF device ID in
6545 * the PCIe SR-IOV capability.
6546 */
6547 if (pdev->is_virtfn) {
6548 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6549 pci_name(pdev), pdev->vendor, pdev->device);
6550 return -EINVAL;
6551 }
6552
9ce77666 6553 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6554 if (err)
6555 return err;
6556
1b507730
NN		 6557 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6558 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6559 pci_using_dac = 1;
6560 } else {
1b507730 6561 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6562 if (err) {
1b507730
NN		 6563 err = dma_set_coherent_mask(&pdev->dev,
6564 DMA_BIT_MASK(32));
9a799d71 6565 if (err) {
b8bc0421
DC		 6566 dev_err(&pdev->dev,
6567 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6568 goto err_dma;
6569 }
6570 }
6571 pci_using_dac = 0;
6572 }
6573
9ce77666 6574 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6575 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6576 if (err) {
b8bc0421
DC		 6577 dev_err(&pdev->dev,
6578 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6579 goto err_pci_reg;
6580 }
6581
19d5afd4 6582 pci_enable_pcie_error_reporting(pdev);
6fabd715 6583
9a799d71 6584 pci_set_master(pdev);
fb3b27bc 6585 pci_save_state(pdev);
9a799d71 6586
c85a2618
JF		 6587 if (ii->mac == ixgbe_mac_82598EB)
6588 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6589 else
6590 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6591
6592 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6593#ifdef IXGBE_FCOE
6594 indices += min_t(unsigned int, num_possible_cpus(),
6595 IXGBE_MAX_FCOE_INDICES);
6596#endif
c85a2618 6597 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6598 if (!netdev) {
6599 err = -ENOMEM;
6600 goto err_alloc_etherdev;
6601 }
6602
9a799d71
AK		 6603 SET_NETDEV_DEV(netdev, &pdev->dev);
6604
6605 pci_set_drvdata(pdev, netdev);
6606 adapter = netdev_priv(netdev);
6607
6608 adapter->netdev = netdev;
6609 adapter->pdev = pdev;
6610 hw = &adapter->hw;
6611 hw->back = adapter;
6612 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6613
05857980
JK		 6614 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6615 pci_resource_len(pdev, 0));
9a799d71
AK		 6616 if (!hw->hw_addr) {
6617 err = -EIO;
6618 goto err_ioremap;
6619 }
6620
6621 for (i = 1; i <= 5; i++) {
6622 if (pci_resource_len(pdev, i) == 0)
6623 continue;
6624 }
6625
0edc3527 6626 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6627 ixgbe_set_ethtool_ops(netdev);
9a799d71 6628 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6629 strcpy(netdev->name, pci_name(pdev));
6630
9a799d71
AK		 6631 adapter->bd_number = cards_found;
6632
9a799d71
AK		 6633 /* Setup hw api */
6634 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6635 hw->mac.type = ii->mac;
9a799d71 6636
c44ade9e
JB		 6637 /* EEPROM */
6638 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6639 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6640 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6641 if (!(eec & (1 << 8)))
6642 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6643
6644 /* PHY */
6645 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6646 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6647 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6648 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6649 hw->phy.mdio.mmds = 0;
6650 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6651 hw->phy.mdio.dev = netdev;
6652 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6653 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6654
6655 /* set up this timer and work struct before calling get_invariants
6656 * which might start the timer
6657 */
6658 init_timer(&adapter->sfp_timer);
6659 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6660 adapter->sfp_timer.data = (unsigned long) adapter;
6661
6662 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6663
e8e26350
PW		 6664 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6665 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6666
6667 /* a new SFP+ module arrival, called from GPI SDP2 context */
6668 INIT_WORK(&adapter->sfp_config_module_task,
6669 ixgbe_sfp_config_module_task);
6670
8ca783ab 6671 ii->get_invariants(hw);
9a799d71
AK		 6672
6673 /* setup the private structure */
6674 err = ixgbe_sw_init(adapter);
6675 if (err)
6676 goto err_sw_init;
6677
e86bff0e
DS		 6678 /* Make it possible the adapter to be woken up via WOL */
6679 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6680 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6681
bf069c97
DS		 6682 /*
6683 * If there is a fan on this device and it has failed log the
6684 * failure.
6685 */
6686 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6687 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6688 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6689 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6690 }
6691
c44ade9e 6692 /* reset_hw fills in the perm_addr as well */
119fc60a 6693 hw->phy.reset_if_overtemp = true;
c44ade9e 6694 err = hw->mac.ops.reset_hw(hw);
119fc60a 6695 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6696 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6697 hw->mac.type == ixgbe_mac_82598EB) {
6698 /*
6699 * Start a kernel thread to watch for a module to arrive.
6700 * Only do this for 82598, since 82599 will generate
6701 * interrupts on module arrival.
6702 */
6703 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6704 mod_timer(&adapter->sfp_timer,
6705 round_jiffies(jiffies + (2 * HZ)));
6706 err = 0;
6707 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6708 e_dev_err("failed to initialize because an unsupported SFP+ "
6709 "module type was detected.\n");
6710 e_dev_err("Reload the driver after installing a supported "
6711 "module.\n");
04f165ef
PW		 6712 goto err_sw_init;
6713 } else if (err) {
849c4542 6714 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6715 goto err_sw_init;
6716 }
6717
1cdd1ec8
GR		 6718 ixgbe_probe_vf(adapter, ii);
6719
396e799c 6720 netdev->features = NETIF_F_SG |
b4617240
PW		 6721 NETIF_F_IP_CSUM |
6722 NETIF_F_HW_VLAN_TX |
6723 NETIF_F_HW_VLAN_RX |
6724 NETIF_F_HW_VLAN_FILTER;
9a799d71 6725
e9990a9c 6726 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6727 netdev->features |= NETIF_F_TSO;
9a799d71 6728 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6729 netdev->features |= NETIF_F_GRO;
ad31c402 6730
45a5ead0
JB		 6731 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6732 netdev->features |= NETIF_F_SCTP_CSUM;
6733
ad31c402
JK		 6734 netdev->vlan_features |= NETIF_F_TSO;
6735 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6736 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6737 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6738 netdev->vlan_features |= NETIF_F_SG;
6739
1cdd1ec8
GR		 6740 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6741 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6742 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6743 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6744 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6745
7a6b6f51 6746#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6747 netdev->dcbnl_ops = &dcbnl_ops;
6748#endif
6749
eacd73f7 6750#ifdef IXGBE_FCOE
0d551589 6751 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6752 if (hw->mac.ops.get_device_caps) {
6753 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6754 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6755 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6756 }
6757 }
5e09d7f6
YZ		 6758 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6759 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6760 netdev->vlan_features |= NETIF_F_FSO;
6761 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6762 }
eacd73f7 6763#endif /* IXGBE_FCOE */
9a799d71
AK		 6764 if (pci_using_dac)
6765 netdev->features |= NETIF_F_HIGHDMA;
6766
0c19d6af 6767 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6768 netdev->features |= NETIF_F_LRO;
6769
9a799d71 6770 /* make sure the EEPROM is good */
c44ade9e 6771 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6772 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6773 err = -EIO;
6774 goto err_eeprom;
6775 }
6776
6777 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6778 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6779
c44ade9e 6780 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6781 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6782 err = -EIO;
6783 goto err_eeprom;
6784 }
6785
61fac744
PW		 6786 /* power down the optics */
6787 if (hw->phy.multispeed_fiber)
6788 hw->mac.ops.disable_tx_laser(hw);
6789
9a799d71
AK		 6790 init_timer(&adapter->watchdog_timer);
6791 adapter->watchdog_timer.function = &ixgbe_watchdog;
6792 adapter->watchdog_timer.data = (unsigned long)adapter;
6793
6794 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6795 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6796
021230d4
AV		 6797 err = ixgbe_init_interrupt_scheme(adapter);
6798 if (err)
6799 goto err_sw_init;
9a799d71 6800
e8e26350
PW		 6801 switch (pdev->device) {
6802 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6803 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6804 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6805 break;
6806 default:
6807 adapter->wol = 0;
6808 break;
6809 }
e8e26350
PW		 6810 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6811
04f165ef
PW		 6812 /* pick up the PCI bus settings for reporting later */
6813 hw->mac.ops.get_bus_info(hw);
6814
9a799d71 6815 /* print bus type/speed/width info */
849c4542 6816 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6817 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6818 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6819 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6820 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6821 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6822 "Unknown"),
7c510e4b 6823 netdev->dev_addr);
c44ade9e 6824 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 6825 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 6826 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6827 "PBA No: %06x-%03x\n",
6828 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6829 (part_num >> 8), (part_num & 0xff));
e8e26350 6830 else
849c4542
ET		 6831 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6832 hw->mac.type, hw->phy.type,
6833 (part_num >> 8), (part_num & 0xff));
9a799d71 6834
e8e26350 6835 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 6836 e_dev_warn("PCI-Express bandwidth available for this card is "
6837 "not sufficient for optimal performance.\n");
6838 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6839 "is required.\n");
0c254d86
AK		 6840 }
6841
34b0368c
PWJ		 6842 /* save off EEPROM version number */
6843 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6844
9a799d71 6845 /* reset the hardware with the new settings */
794caeb2 6846 err = hw->mac.ops.start_hw(hw);
c44ade9e 6847
794caeb2
PWJ		 6848 if (err == IXGBE_ERR_EEPROM_VERSION) {
6849 /* We are running on a pre-production device, log a warning */
849c4542
ET		 6850 e_dev_warn("This device is a pre-production adapter/LOM. "
6851 "Please be aware there may be issues associated "
6852 "with your hardware. If you are experiencing "
6853 "problems please contact your Intel or hardware "
6854 "representative who provided you with this "
6855 "hardware.\n");
794caeb2 6856 }
9a799d71
AK		 6857 strcpy(netdev->name, "eth%d");
6858 err = register_netdev(netdev);
6859 if (err)
6860 goto err_register;
6861
54386467
JB		 6862 /* carrier off reporting is important to ethtool even BEFORE open */
6863 netif_carrier_off(netdev);
6864
c4cf55e5
PWJ		 6865 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6866 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6867 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6868
119fc60a
MC		 6869 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6870 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
5dd2d332 6871#ifdef CONFIG_IXGBE_DCA
652f093f 6872 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6873 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6874 ixgbe_setup_dca(adapter);
6875 }
6876#endif
1cdd1ec8 6877 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 6878 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 6879 for (i = 0; i < adapter->num_vfs; i++)
6880 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6881 }
6882
0365e6e4
PW		 6883 /* add san mac addr to netdev */
6884 ixgbe_add_sanmac_netdev(netdev);
9a799d71 6885
849c4542 6886 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 6887 cards_found++;
6888 return 0;
6889
6890err_register:
5eba3699 6891 ixgbe_release_hw_control(adapter);
7a921c93 6892 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6893err_sw_init:
6894err_eeprom:
1cdd1ec8
GR		 6895 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6896 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6897 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6898 del_timer_sync(&adapter->sfp_timer);
6899 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6900 cancel_work_sync(&adapter->multispeed_fiber_task);
6901 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6902 iounmap(hw->hw_addr);
6903err_ioremap:
6904 free_netdev(netdev);
6905err_alloc_etherdev:
9ce77666 6906 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6907 IORESOURCE_MEM));
9a799d71
AK		 6908err_pci_reg:
6909err_dma:
6910 pci_disable_device(pdev);
6911 return err;
6912}
6913
6914/**
6915 * ixgbe_remove - Device Removal Routine
6916 * @pdev: PCI device information struct
6917 *
6918 * ixgbe_remove is called by the PCI subsystem to alert the driver
6919 * that it should release a PCI device. The could be caused by a
6920 * Hot-Plug event, or because the driver is going to be removed from
6921 * memory.
6922 **/
6923static void __devexit ixgbe_remove(struct pci_dev *pdev)
6924{
6925 struct net_device *netdev = pci_get_drvdata(pdev);
6926 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6927
6928 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6929 /* clear the module not found bit to make sure the worker won't
6930 * reschedule
6931 */
6932 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6933 del_timer_sync(&adapter->watchdog_timer);
6934
c4900be0
DS		 6935 del_timer_sync(&adapter->sfp_timer);
6936 cancel_work_sync(&adapter->watchdog_task);
6937 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6938 cancel_work_sync(&adapter->multispeed_fiber_task);
6939 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6940 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6941 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6942 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6943 flush_scheduled_work();
6944
5dd2d332 6945#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6946 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6947 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6948 dca_remove_requester(&pdev->dev);
6949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6950 }
6951
6952#endif
332d4a7d
YZ		 6953#ifdef IXGBE_FCOE
6954 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6955 ixgbe_cleanup_fcoe(adapter);
6956
6957#endif /* IXGBE_FCOE */
0365e6e4
PW		 6958
6959 /* remove the added san mac */
6960 ixgbe_del_sanmac_netdev(netdev);
6961
c4900be0
DS		 6962 if (netdev->reg_state == NETREG_REGISTERED)
6963 unregister_netdev(netdev);
9a799d71 6964
1cdd1ec8
GR		 6965 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6966 ixgbe_disable_sriov(adapter);
6967
7a921c93 6968 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6969
021230d4 6970 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6971
6972 iounmap(adapter->hw.hw_addr);
9ce77666 6973 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6974 IORESOURCE_MEM));
9a799d71 6975
849c4542 6976 e_dev_info("complete\n");
021230d4 6977
9a799d71
AK		 6978 free_netdev(netdev);
6979
19d5afd4 6980 pci_disable_pcie_error_reporting(pdev);
6fabd715 6981
9a799d71
AK		 6982 pci_disable_device(pdev);
6983}
6984
6985/**
6986 * ixgbe_io_error_detected - called when PCI error is detected
6987 * @pdev: Pointer to PCI device
6988 * @state: The current pci connection state
6989 *
6990 * This function is called after a PCI bus error affecting
6991 * this device has been detected.
6992 */
6993static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6994 pci_channel_state_t state)
9a799d71
AK		 6995{
6996 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6997 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6998
6999 netif_device_detach(netdev);
7000
3044b8d1
BL		 7001 if (state == pci_channel_io_perm_failure)
7002 return PCI_ERS_RESULT_DISCONNECT;
7003
9a799d71
AK		 7004 if (netif_running(netdev))
7005 ixgbe_down(adapter);
7006 pci_disable_device(pdev);
7007
b4617240 7008 /* Request a slot reset. */
9a799d71
AK		 7009 return PCI_ERS_RESULT_NEED_RESET;
7010}
7011
7012/**
7013 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7014 * @pdev: Pointer to PCI device
7015 *
7016 * Restart the card from scratch, as if from a cold-boot.
7017 */
7018static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7019{
7020 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7021 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 7022 pci_ers_result_t result;
7023 int err;
9a799d71 7024
9ce77666 7025 if (pci_enable_device_mem(pdev)) {
396e799c 7026 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7027 result = PCI_ERS_RESULT_DISCONNECT;
7028 } else {
7029 pci_set_master(pdev);
7030 pci_restore_state(pdev);
c0e1f68b 7031 pci_save_state(pdev);
9a799d71 7032
dd4d8ca6 7033 pci_wake_from_d3(pdev, false);
9a799d71 7034
6fabd715 7035 ixgbe_reset(adapter);
88512539 7036 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7037 result = PCI_ERS_RESULT_RECOVERED;
7038 }
7039
7040 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7041 if (err) {
849c4542
ET		 7042 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7043 "failed 0x%0x\n", err);
6fabd715
PWJ		 7044 /* non-fatal, continue */
7045 }
9a799d71 7046
6fabd715 7047 return result;
9a799d71
AK		 7048}
7049
7050/**
7051 * ixgbe_io_resume - called when traffic can start flowing again.
7052 * @pdev: Pointer to PCI device
7053 *
7054 * This callback is called when the error recovery driver tells us that
7055 * its OK to resume normal operation.
7056 */
7057static void ixgbe_io_resume(struct pci_dev *pdev)
7058{
7059 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7060 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7061
7062 if (netif_running(netdev)) {
7063 if (ixgbe_up(adapter)) {
396e799c 7064 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7065 return;
7066 }
7067 }
7068
7069 netif_device_attach(netdev);
9a799d71
AK		 7070}
7071
7072static struct pci_error_handlers ixgbe_err_handler = {
7073 .error_detected = ixgbe_io_error_detected,
7074 .slot_reset = ixgbe_io_slot_reset,
7075 .resume = ixgbe_io_resume,
7076};
7077
7078static struct pci_driver ixgbe_driver = {
7079 .name = ixgbe_driver_name,
7080 .id_table = ixgbe_pci_tbl,
7081 .probe = ixgbe_probe,
7082 .remove = __devexit_p(ixgbe_remove),
7083#ifdef CONFIG_PM
7084 .suspend = ixgbe_suspend,
7085 .resume = ixgbe_resume,
7086#endif
7087 .shutdown = ixgbe_shutdown,
7088 .err_handler = &ixgbe_err_handler
7089};
7090
7091/**
7092 * ixgbe_init_module - Driver Registration Routine
7093 *
7094 * ixgbe_init_module is the first routine called when the driver is
7095 * loaded. All it does is register with the PCI subsystem.
7096 **/
7097static int __init ixgbe_init_module(void)
7098{
7099 int ret;
849c4542
ET		 7100 pr_info("%s - version %s\n", ixgbe_driver_string,
7101 ixgbe_driver_version);
7102 pr_info("%s\n", ixgbe_copyright);
9a799d71 7103
5dd2d332 7104#ifdef CONFIG_IXGBE_DCA
bd0362dd 7105 dca_register_notify(&dca_notifier);
bd0362dd 7106#endif
5dd2d332 7107
9a799d71
AK		 7108 ret = pci_register_driver(&ixgbe_driver);
7109 return ret;
7110}
b4617240 7111
9a799d71
AK		 7112module_init(ixgbe_init_module);
7113
7114/**
7115 * ixgbe_exit_module - Driver Exit Cleanup Routine
7116 *
7117 * ixgbe_exit_module is called just before the driver is removed
7118 * from memory.
7119 **/
7120static void __exit ixgbe_exit_module(void)
7121{
5dd2d332 7122#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7123 dca_unregister_notify(&dca_notifier);
7124#endif
9a799d71
AK		 7125 pci_unregister_driver(&ixgbe_driver);
7126}
bd0362dd 7127
5dd2d332 7128#ifdef CONFIG_IXGBE_DCA
bd0362dd 7129static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 7130 void *p)
bd0362dd
JC		 7131{
7132 int ret_val;
7133
7134 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 7135 __ixgbe_notify_dca);
bd0362dd
JC		 7136
7137 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7138}
b453368d 7139
5dd2d332 7140#endif /* CONFIG_IXGBE_DCA */
849c4542 7141
b453368d 7142/**
849c4542 7143 * ixgbe_get_hw_dev return device
b453368d
AD		 7144 * used by hardware layer to print debugging information
7145 **/
849c4542 7146struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7147{
7148 struct ixgbe_adapter *adapter = hw->back;
849c4542 7149 return adapter->netdev;
b453368d 7150}
bd0362dd 7151
9a799d71
AK		 7152module_exit(ixgbe_exit_module);
7153
7154/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree