]>
Commit | Line | Data |
---|---|---|
4330c2f2 GFT |
1 | /* |
2 | * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver | |
3 | * | |
4 | * Copyright 2008 JMicron Technology Corporation | |
5 | * http://www.jmicron.com/ | |
d3d584f5 | 6 | * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org> |
4330c2f2 | 7 | * |
3bf61c55 GFT |
8 | * Author: Guo-Fu Tseng <cooldavid@cooldavid.org> |
9 | * | |
4330c2f2 GFT |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | * | |
23 | */ | |
24 | ||
cd0ff491 | 25 | #ifndef __JME_H_INCLUDED__ |
3b70a6fa | 26 | #define __JME_H_INCLUDED__ |
678e26f9 | 27 | #include <linux/interrupt.h> |
d7699f87 GFT |
28 | |
29 | #define DRV_NAME "jme" | |
f6d5c552 | 30 | #define DRV_VERSION "1.0.8.2-jmmod" |
cd0ff491 | 31 | #define PFX DRV_NAME ": " |
d7699f87 | 32 | |
cd0ff491 GFT |
33 | #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250 |
34 | #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260 | |
8d27293f | 35 | |
cd0ff491 GFT |
36 | /* |
37 | * Message related definitions | |
38 | */ | |
39 | #define JME_DEF_MSG_ENABLE \ | |
40 | (NETIF_MSG_PROBE | \ | |
41 | NETIF_MSG_LINK | \ | |
42 | NETIF_MSG_RX_ERR | \ | |
43 | NETIF_MSG_TX_ERR | \ | |
44 | NETIF_MSG_HW) | |
45 | ||
aee7a9f5 | 46 | #ifndef pr_err |
937ef75a JP |
47 | #define pr_err(fmt, arg...) \ |
48 | printk(KERN_ERR fmt, ##arg) | |
49 | #endif | |
aee7a9f5 | 50 | #ifndef netdev_err |
937ef75a JP |
51 | #define netdev_err(netdev, fmt, arg...) \ |
52 | pr_err(fmt, ##arg) | |
53 | #endif | |
d7699f87 | 54 | |
3bf61c55 | 55 | #ifdef TX_DEBUG |
7ca9ebee GFT |
56 | #define tx_dbg(priv, fmt, args...) \ |
57 | printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args) | |
3bf61c55 | 58 | #else |
7ca9ebee GFT |
59 | #define tx_dbg(priv, fmt, args...) \ |
60 | do { \ | |
61 | if (0) \ | |
62 | printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \ | |
63 | } while (0) | |
3bf61c55 GFT |
64 | #endif |
65 | ||
7ca9ebee | 66 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33) |
cd0ff491 GFT |
67 | #define jme_msg(msglvl, type, priv, fmt, args...) \ |
68 | if (netif_msg_##type(priv)) \ | |
69 | printk(msglvl "%s: " fmt, (priv)->dev->name, ## args) | |
3bf61c55 | 70 | |
cd0ff491 GFT |
71 | #define msg_probe(priv, fmt, args...) \ |
72 | jme_msg(KERN_INFO, probe, priv, fmt, ## args) | |
29bdd921 | 73 | |
cd0ff491 GFT |
74 | #define msg_link(priv, fmt, args...) \ |
75 | jme_msg(KERN_INFO, link, priv, fmt, ## args) | |
79ce639c | 76 | |
cd0ff491 GFT |
77 | #define msg_intr(priv, fmt, args...) \ |
78 | jme_msg(KERN_INFO, intr, priv, fmt, ## args) | |
79 | ||
80 | #define msg_rx_err(priv, fmt, args...) \ | |
81 | jme_msg(KERN_ERR, rx_err, priv, fmt, ## args) | |
b3821cc5 | 82 | |
cd0ff491 GFT |
83 | #define msg_rx_status(priv, fmt, args...) \ |
84 | jme_msg(KERN_INFO, rx_status, priv, fmt, ## args) | |
4330c2f2 | 85 | |
cd0ff491 GFT |
86 | #define msg_tx_err(priv, fmt, args...) \ |
87 | jme_msg(KERN_ERR, tx_err, priv, fmt, ## args) | |
4330c2f2 | 88 | |
cd0ff491 GFT |
89 | #define msg_tx_done(priv, fmt, args...) \ |
90 | jme_msg(KERN_INFO, tx_done, priv, fmt, ## args) | |
d7699f87 | 91 | |
cd0ff491 GFT |
92 | #define msg_tx_queued(priv, fmt, args...) \ |
93 | jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args) | |
94 | ||
95 | #define msg_hw(priv, fmt, args...) \ | |
96 | jme_msg(KERN_ERR, hw, priv, fmt, ## args) | |
937ef75a | 97 | |
aee7a9f5 | 98 | #ifndef netif_info |
937ef75a JP |
99 | #define netif_info(priv, type, dev, fmt, args...) \ |
100 | msg_ ## type(priv, fmt, ## args) | |
aee7a9f5 GFT |
101 | #endif |
102 | #ifndef netif_err | |
937ef75a JP |
103 | #define netif_err(priv, type, dev, fmt, args...) \ |
104 | msg_ ## type(priv, fmt, ## args) | |
7ca9ebee | 105 | #endif |
aee7a9f5 | 106 | #endif |
cd0ff491 | 107 | |
1a0b42f4 MM |
108 | #ifndef NETIF_F_TSO6 |
109 | #define NETIF_F_TSO6 0 | |
110 | #endif | |
111 | #ifndef NETIF_F_IPV6_CSUM | |
112 | #define NETIF_F_IPV6_CSUM 0 | |
113 | #endif | |
114 | ||
767e5b98 MM |
115 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) |
116 | #define __USE_NDO_FIX_FEATURES__ | |
117 | #endif | |
118 | ||
5141719b JP |
119 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,1,0) |
120 | #define __UNIFY_VLAN_RX_PATH__ | |
1ec30a25 | 121 | #define __USE_NDO_SET_RX_MODE__ |
5141719b JP |
122 | #endif |
123 | ||
cd0ff491 GFT |
124 | /* |
125 | * Extra PCI Configuration space interface | |
126 | */ | |
127 | #define PCI_DCSR_MRRS 0x59 | |
128 | #define PCI_DCSR_MRRS_MASK 0x70 | |
129 | ||
130 | enum pci_dcsr_mrrs_vals { | |
4330c2f2 GFT |
131 | MRRS_128B = 0x00, |
132 | MRRS_256B = 0x10, | |
133 | MRRS_512B = 0x20, | |
134 | MRRS_1024B = 0x30, | |
135 | MRRS_2048B = 0x40, | |
136 | MRRS_4096B = 0x50, | |
137 | }; | |
d7699f87 | 138 | |
cd0ff491 GFT |
139 | #define PCI_SPI 0xB0 |
140 | ||
141 | enum pci_spi_bits { | |
142 | SPI_EN = 0x10, | |
143 | SPI_MISO = 0x08, | |
144 | SPI_MOSI = 0x04, | |
145 | SPI_SCLK = 0x02, | |
146 | SPI_CS = 0x01, | |
147 | }; | |
148 | ||
149 | struct jme_spi_op { | |
150 | void __user *uwbuf; | |
151 | void __user *urbuf; | |
152 | __u8 wn; /* Number of write actions */ | |
153 | __u8 rn; /* Number of read actions */ | |
154 | __u8 bitn; /* Number of bits per action */ | |
155 | __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/ | |
156 | __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */ | |
157 | ||
158 | /* Internal use only */ | |
159 | u8 *kwbuf; | |
160 | u8 *krbuf; | |
161 | u8 sr; | |
162 | u16 halfclk; /* Half of clock cycle calculated from spd, in ns */ | |
163 | }; | |
79ce639c | 164 | |
cd0ff491 GFT |
165 | enum jme_spi_op_bits { |
166 | SPI_MODE_CPHA = 0x01, | |
167 | SPI_MODE_CPOL = 0x02, | |
168 | SPI_MODE_DUP = 0x80, | |
169 | }; | |
170 | ||
171 | #define HALF_US 500 /* 500 ns */ | |
172 | #define JMESPIIOCTL SIOCDEVPRIVATE | |
173 | ||
ed457bcc GFT |
174 | #define PCI_PRIV_PE1 0xE4 |
175 | ||
176 | enum pci_priv_pe1_bit_masks { | |
177 | PE1_ASPMSUPRT = 0x00000003, /* | |
178 | * RW: | |
179 | * Aspm_support[1:0] | |
180 | * (R/W Port of 5C[11:10]) | |
181 | */ | |
182 | PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */ | |
183 | PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */ | |
184 | PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */ | |
185 | PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */ | |
186 | PE1_GPREG0 = 0x0000FF00, /* | |
187 | * SRW: | |
188 | * Cfg_gp_reg0 | |
189 | * [7:6] phy_giga BG control | |
190 | * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#) | |
191 | * [4:0] Reserved | |
192 | */ | |
193 | PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */ | |
194 | PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */ | |
195 | PE1_REVID = 0xFF000000, /* RO: Rev ID */ | |
196 | }; | |
197 | ||
198 | enum pci_priv_pe1_values { | |
199 | PE1_GPREG0_ENBG = 0x00000000, /* en BG */ | |
200 | PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */ | |
201 | PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */ | |
202 | PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */ | |
203 | }; | |
204 | ||
cd0ff491 GFT |
205 | /* |
206 | * Dynamic(adaptive)/Static PCC values | |
207 | */ | |
3bf61c55 | 208 | enum dynamic_pcc_values { |
192570e0 | 209 | PCC_OFF = 0, |
3bf61c55 GFT |
210 | PCC_P1 = 1, |
211 | PCC_P2 = 2, | |
212 | PCC_P3 = 3, | |
213 | ||
192570e0 | 214 | PCC_OFF_TO = 0, |
3bf61c55 | 215 | PCC_P1_TO = 1, |
192570e0 GFT |
216 | PCC_P2_TO = 64, |
217 | PCC_P3_TO = 128, | |
3bf61c55 | 218 | |
192570e0 | 219 | PCC_OFF_CNT = 0, |
3bf61c55 | 220 | PCC_P1_CNT = 1, |
192570e0 GFT |
221 | PCC_P2_CNT = 16, |
222 | PCC_P3_CNT = 32, | |
3bf61c55 GFT |
223 | }; |
224 | struct dynpcc_info { | |
3bf61c55 GFT |
225 | unsigned long last_bytes; |
226 | unsigned long last_pkts; | |
79ce639c | 227 | unsigned long intr_cnt; |
3bf61c55 GFT |
228 | unsigned char cur; |
229 | unsigned char attempt; | |
230 | unsigned char cnt; | |
231 | }; | |
79ce639c | 232 | #define PCC_INTERVAL_US 100000 |
cd0ff491 GFT |
233 | #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US)) |
234 | #define PCC_P3_THRESHOLD (2 * 1024 * 1024) | |
79ce639c GFT |
235 | #define PCC_P2_THRESHOLD 800 |
236 | #define PCC_INTR_THRESHOLD 800 | |
47220951 | 237 | #define PCC_TX_TO 1000 |
b3821cc5 | 238 | #define PCC_TX_CNT 8 |
3bf61c55 | 239 | |
d7699f87 GFT |
240 | /* |
241 | * TX/RX Descriptors | |
4330c2f2 | 242 | * |
cd0ff491 | 243 | * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024 |
d7699f87 | 244 | */ |
4330c2f2 | 245 | #define RING_DESC_ALIGN 16 /* Descriptor alignment */ |
d7699f87 GFT |
246 | #define TX_DESC_SIZE 16 |
247 | #define TX_RING_NR 8 | |
cd0ff491 | 248 | #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN) |
d7699f87 | 249 | |
3bf61c55 | 250 | struct txdesc { |
d7699f87 | 251 | union { |
cd0ff491 GFT |
252 | __u8 all[16]; |
253 | __le32 dw[4]; | |
d7699f87 GFT |
254 | struct { |
255 | /* DW0 */ | |
cd0ff491 GFT |
256 | __le16 vlan; |
257 | __u8 rsv1; | |
258 | __u8 flags; | |
d7699f87 GFT |
259 | |
260 | /* DW1 */ | |
cd0ff491 GFT |
261 | __le16 datalen; |
262 | __le16 mss; | |
d7699f87 GFT |
263 | |
264 | /* DW2 */ | |
cd0ff491 GFT |
265 | __le16 pktsize; |
266 | __le16 rsv2; | |
d7699f87 GFT |
267 | |
268 | /* DW3 */ | |
cd0ff491 | 269 | __le32 bufaddr; |
d7699f87 | 270 | } desc1; |
3bf61c55 GFT |
271 | struct { |
272 | /* DW0 */ | |
cd0ff491 GFT |
273 | __le16 rsv1; |
274 | __u8 rsv2; | |
275 | __u8 flags; | |
3bf61c55 GFT |
276 | |
277 | /* DW1 */ | |
cd0ff491 GFT |
278 | __le16 datalen; |
279 | __le16 rsv3; | |
3bf61c55 GFT |
280 | |
281 | /* DW2 */ | |
cd0ff491 | 282 | __le32 bufaddrh; |
3bf61c55 GFT |
283 | |
284 | /* DW3 */ | |
cd0ff491 | 285 | __le32 bufaddrl; |
3bf61c55 | 286 | } desc2; |
8c198884 GFT |
287 | struct { |
288 | /* DW0 */ | |
cd0ff491 GFT |
289 | __u8 ehdrsz; |
290 | __u8 rsv1; | |
291 | __u8 rsv2; | |
292 | __u8 flags; | |
8c198884 GFT |
293 | |
294 | /* DW1 */ | |
cd0ff491 GFT |
295 | __le16 trycnt; |
296 | __le16 segcnt; | |
8c198884 GFT |
297 | |
298 | /* DW2 */ | |
cd0ff491 GFT |
299 | __le16 pktsz; |
300 | __le16 rsv3; | |
8c198884 GFT |
301 | |
302 | /* DW3 */ | |
cd0ff491 | 303 | __le32 bufaddrl; |
8c198884 | 304 | } descwb; |
d7699f87 GFT |
305 | }; |
306 | }; | |
cd0ff491 | 307 | |
8c198884 | 308 | enum jme_txdesc_flags_bits { |
d7699f87 GFT |
309 | TXFLAG_OWN = 0x80, |
310 | TXFLAG_INT = 0x40, | |
3bf61c55 | 311 | TXFLAG_64BIT = 0x20, |
d7699f87 GFT |
312 | TXFLAG_TCPCS = 0x10, |
313 | TXFLAG_UDPCS = 0x08, | |
314 | TXFLAG_IPCS = 0x04, | |
315 | TXFLAG_LSEN = 0x02, | |
316 | TXFLAG_TAGON = 0x01, | |
317 | }; | |
cd0ff491 | 318 | |
b3821cc5 | 319 | #define TXDESC_MSS_SHIFT 2 |
0ede469c | 320 | enum jme_txwbdesc_flags_bits { |
8c198884 GFT |
321 | TXWBFLAG_OWN = 0x80, |
322 | TXWBFLAG_INT = 0x40, | |
323 | TXWBFLAG_TMOUT = 0x20, | |
324 | TXWBFLAG_TRYOUT = 0x10, | |
325 | TXWBFLAG_COL = 0x08, | |
326 | ||
327 | TXWBFLAG_ALLERR = TXWBFLAG_TMOUT | | |
328 | TXWBFLAG_TRYOUT | | |
329 | TXWBFLAG_COL, | |
330 | }; | |
d7699f87 | 331 | |
d7699f87 GFT |
332 | #define RX_DESC_SIZE 16 |
333 | #define RX_RING_NR 4 | |
cd0ff491 | 334 | #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN) |
d7699f87 | 335 | #define RX_BUF_DMA_ALIGN 8 |
3bf61c55 | 336 | #define RX_PREPAD_SIZE 10 |
79ce639c GFT |
337 | #define ETH_CRC_LEN 2 |
338 | #define RX_VLANHDR_LEN 2 | |
339 | #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \ | |
340 | ETH_HLEN + \ | |
341 | ETH_CRC_LEN + \ | |
342 | RX_VLANHDR_LEN + \ | |
343 | RX_BUF_DMA_ALIGN) | |
d7699f87 | 344 | |
3bf61c55 | 345 | struct rxdesc { |
d7699f87 | 346 | union { |
cd0ff491 GFT |
347 | __u8 all[16]; |
348 | __le32 dw[4]; | |
d7699f87 GFT |
349 | struct { |
350 | /* DW0 */ | |
cd0ff491 GFT |
351 | __le16 rsv2; |
352 | __u8 rsv1; | |
353 | __u8 flags; | |
d7699f87 GFT |
354 | |
355 | /* DW1 */ | |
cd0ff491 GFT |
356 | __le16 datalen; |
357 | __le16 wbcpl; | |
d7699f87 GFT |
358 | |
359 | /* DW2 */ | |
cd0ff491 | 360 | __le32 bufaddrh; |
d7699f87 GFT |
361 | |
362 | /* DW3 */ | |
cd0ff491 | 363 | __le32 bufaddrl; |
d7699f87 GFT |
364 | } desc1; |
365 | struct { | |
366 | /* DW0 */ | |
cd0ff491 GFT |
367 | __le16 vlan; |
368 | __le16 flags; | |
d7699f87 GFT |
369 | |
370 | /* DW1 */ | |
cd0ff491 GFT |
371 | __le16 framesize; |
372 | __u8 errstat; | |
373 | __u8 desccnt; | |
d7699f87 GFT |
374 | |
375 | /* DW2 */ | |
cd0ff491 | 376 | __le32 rsshash; |
d7699f87 GFT |
377 | |
378 | /* DW3 */ | |
cd0ff491 GFT |
379 | __u8 hashfun; |
380 | __u8 hashtype; | |
381 | __le16 resrv; | |
d7699f87 GFT |
382 | } descwb; |
383 | }; | |
384 | }; | |
cd0ff491 | 385 | |
d7699f87 GFT |
386 | enum jme_rxdesc_flags_bits { |
387 | RXFLAG_OWN = 0x80, | |
388 | RXFLAG_INT = 0x40, | |
389 | RXFLAG_64BIT = 0x20, | |
390 | }; | |
cd0ff491 | 391 | |
d7699f87 | 392 | enum jme_rxwbdesc_flags_bits { |
4330c2f2 GFT |
393 | RXWBFLAG_OWN = 0x8000, |
394 | RXWBFLAG_INT = 0x4000, | |
395 | RXWBFLAG_MF = 0x2000, | |
396 | RXWBFLAG_64BIT = 0x2000, | |
397 | RXWBFLAG_TCPON = 0x1000, | |
398 | RXWBFLAG_UDPON = 0x0800, | |
399 | RXWBFLAG_IPCS = 0x0400, | |
400 | RXWBFLAG_TCPCS = 0x0200, | |
401 | RXWBFLAG_UDPCS = 0x0100, | |
402 | RXWBFLAG_TAGON = 0x0080, | |
403 | RXWBFLAG_IPV4 = 0x0040, | |
404 | RXWBFLAG_IPV6 = 0x0020, | |
405 | RXWBFLAG_PAUSE = 0x0010, | |
406 | RXWBFLAG_MAGIC = 0x0008, | |
407 | RXWBFLAG_WAKEUP = 0x0004, | |
408 | RXWBFLAG_DEST = 0x0003, | |
409 | RXWBFLAG_DEST_UNI = 0x0001, | |
410 | RXWBFLAG_DEST_MUL = 0x0002, | |
411 | RXWBFLAG_DEST_BRO = 0x0003, | |
d7699f87 | 412 | }; |
cd0ff491 | 413 | |
d7699f87 GFT |
414 | enum jme_rxwbdesc_desccnt_mask { |
415 | RXWBDCNT_WBCPL = 0x80, | |
416 | RXWBDCNT_DCNT = 0x7F, | |
417 | }; | |
cd0ff491 | 418 | |
4330c2f2 GFT |
419 | enum jme_rxwbdesc_errstat_bits { |
420 | RXWBERR_LIMIT = 0x80, | |
421 | RXWBERR_MIIER = 0x40, | |
422 | RXWBERR_NIBON = 0x20, | |
423 | RXWBERR_COLON = 0x10, | |
424 | RXWBERR_ABORT = 0x08, | |
425 | RXWBERR_SHORT = 0x04, | |
426 | RXWBERR_OVERUN = 0x02, | |
427 | RXWBERR_CRCERR = 0x01, | |
428 | RXWBERR_ALLERR = 0xFF, | |
429 | }; | |
430 | ||
cd0ff491 GFT |
431 | /* |
432 | * Buffer information corresponding to ring descriptors. | |
433 | */ | |
4330c2f2 GFT |
434 | struct jme_buffer_info { |
435 | struct sk_buff *skb; | |
436 | dma_addr_t mapping; | |
437 | int len; | |
3bf61c55 | 438 | int nr_desc; |
cdcdc9eb | 439 | unsigned long start_xmit; |
4330c2f2 | 440 | }; |
d7699f87 | 441 | |
cd0ff491 GFT |
442 | /* |
443 | * The structure holding buffer information and ring descriptors all together. | |
444 | */ | |
d7699f87 | 445 | struct jme_ring { |
cd0ff491 GFT |
446 | void *alloc; /* pointer to allocated memory */ |
447 | void *desc; /* pointer to ring memory */ | |
448 | dma_addr_t dmaalloc; /* phys address of ring alloc */ | |
449 | dma_addr_t dma; /* phys address for ring dma */ | |
d7699f87 | 450 | |
4330c2f2 | 451 | /* Buffer information corresponding to each descriptor */ |
0ede469c | 452 | struct jme_buffer_info *bufinf; |
d7699f87 | 453 | |
cd0ff491 GFT |
454 | int next_to_use; |
455 | atomic_t next_to_clean; | |
79ce639c | 456 | atomic_t nr_free; |
d7699f87 GFT |
457 | }; |
458 | ||
3b70a6fa GFT |
459 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18) |
460 | #define false 0 | |
461 | #define true 0 | |
462 | #define netdev_alloc_skb(dev, len) dev_alloc_skb(len) | |
463 | #define PCI_VENDOR_ID_JMICRON 0x197B | |
464 | #endif | |
465 | ||
466 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19) | |
467 | #define PCI_VDEVICE(vendor, device) \ | |
468 | PCI_VENDOR_ID_##vendor, (device), \ | |
469 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
470 | #endif | |
471 | ||
85776f33 GFT |
472 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) |
473 | #define NET_STAT(priv) priv->stats | |
474 | #define NETDEV_GET_STATS(netdev, fun_ptr) \ | |
475 | netdev->get_stats = fun_ptr | |
476 | #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats; | |
e5169728 | 477 | /* |
d1d139de | 478 | * CentOS 5.2 have *_hdr helpers back-ported |
e5169728 GFT |
479 | */ |
480 | #ifdef RHEL_RELEASE_CODE | |
d1d139de | 481 | #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,2) |
e5169728 GFT |
482 | #define __DEFINE_IPHDR_HELPERS__ |
483 | #endif | |
484 | #else | |
485 | #define __DEFINE_IPHDR_HELPERS__ | |
486 | #endif | |
487 | #else | |
488 | #define NET_STAT(priv) (priv->dev->stats) | |
489 | #define NETDEV_GET_STATS(netdev, fun_ptr) | |
490 | #define DECLARE_NET_DEVICE_STATS | |
491 | #endif | |
492 | ||
493 | #ifdef __DEFINE_IPHDR_HELPERS__ | |
3b70a6fa GFT |
494 | static inline struct iphdr *ip_hdr(const struct sk_buff *skb) |
495 | { | |
496 | return skb->nh.iph; | |
497 | } | |
498 | ||
499 | static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb) | |
500 | { | |
501 | return skb->nh.ipv6h; | |
502 | } | |
503 | ||
504 | static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb) | |
505 | { | |
506 | return skb->h.th; | |
507 | } | |
85776f33 | 508 | #endif |
3bf61c55 | 509 | |
85776f33 GFT |
510 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) |
511 | #define DECLARE_NAPI_STRUCT | |
512 | #define NETIF_NAPI_SET(dev, napis, pollfn, q) \ | |
513 | dev->poll = pollfn; \ | |
514 | dev->weight = q; | |
515 | #define JME_NAPI_HOLDER(holder) struct net_device *holder | |
516 | #define JME_NAPI_WEIGHT(w) int *w | |
517 | #define JME_NAPI_WEIGHT_VAL(w) *w | |
518 | #define JME_NAPI_WEIGHT_SET(w, r) *w = r | |
3b70a6fa | 519 | #define DECLARE_NETDEV struct net_device *netdev = jme->dev; |
85776f33 GFT |
520 | #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev) |
521 | #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev); | |
522 | #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev); | |
523 | #define JME_RX_SCHEDULE_PREP(priv) \ | |
524 | netif_rx_schedule_prep(priv->dev) | |
525 | #define JME_RX_SCHEDULE(priv) \ | |
526 | __netif_rx_schedule(priv->dev); | |
0ede469c | 527 | #else |
3b70a6fa GFT |
528 | #define DECLARE_NAPI_STRUCT struct napi_struct napi; |
529 | #define NETIF_NAPI_SET(dev, napis, pollfn, q) \ | |
530 | netif_napi_add(dev, napis, pollfn, q); | |
531 | #define JME_NAPI_HOLDER(holder) struct napi_struct *holder | |
532 | #define JME_NAPI_WEIGHT(w) int w | |
533 | #define JME_NAPI_WEIGHT_VAL(w) w | |
534 | #define JME_NAPI_WEIGHT_SET(w, r) | |
535 | #define DECLARE_NETDEV | |
536 | #define JME_RX_COMPLETE(dev, napis) napi_complete(napis) | |
537 | #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); | |
538 | #define JME_NAPI_DISABLE(priv) \ | |
539 | if (!napi_disable_pending(&priv->napi)) \ | |
540 | napi_disable(&priv->napi); | |
541 | #define JME_RX_SCHEDULE_PREP(priv) \ | |
542 | napi_schedule_prep(&priv->napi) | |
543 | #define JME_RX_SCHEDULE(priv) \ | |
544 | __napi_schedule(&priv->napi); | |
85776f33 | 545 | #endif |
cdcdc9eb | 546 | |
3d12cc1b GFT |
547 | #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38) |
548 | #define JME_NEW_PM_API | |
549 | #endif | |
550 | ||
8588b84b DD |
551 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26) |
552 | static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep) | |
553 | { | |
554 | return ep->speed; | |
555 | } | |
556 | #endif | |
557 | ||
d7699f87 GFT |
558 | /* |
559 | * Jmac Adapter Private data | |
560 | */ | |
561 | struct jme_adapter { | |
cd0ff491 GFT |
562 | struct pci_dev *pdev; |
563 | struct net_device *dev; | |
564 | void __iomem *regs; | |
d7699f87 GFT |
565 | struct mii_if_info mii_if; |
566 | struct jme_ring rxring[RX_RING_NR]; | |
567 | struct jme_ring txring[TX_RING_NR]; | |
d7699f87 | 568 | spinlock_t phy_lock; |
fcf45b4c | 569 | spinlock_t macaddr_lock; |
8c198884 | 570 | spinlock_t rxmcs_lock; |
fcf45b4c | 571 | struct tasklet_struct rxempty_task; |
4330c2f2 GFT |
572 | struct tasklet_struct rxclean_task; |
573 | struct tasklet_struct txclean_task; | |
574 | struct tasklet_struct linkch_task; | |
79ce639c | 575 | struct tasklet_struct pcc_task; |
cd0ff491 GFT |
576 | unsigned long flags; |
577 | u32 reg_txcs; | |
578 | u32 reg_txpfc; | |
579 | u32 reg_rxcs; | |
580 | u32 reg_rxmcs; | |
581 | u32 reg_ghc; | |
582 | u32 reg_pmcs; | |
dc4185bd | 583 | u32 reg_gpreg1; |
cd0ff491 GFT |
584 | u32 phylink; |
585 | u32 tx_ring_size; | |
586 | u32 tx_ring_mask; | |
587 | u32 tx_wake_threshold; | |
588 | u32 rx_ring_size; | |
589 | u32 rx_ring_mask; | |
590 | u8 mrrs; | |
591 | unsigned int fpgaver; | |
98ef18f1 GFT |
592 | u8 chiprev; |
593 | u8 chip_main_rev; | |
594 | u8 chip_sub_rev; | |
595 | u8 pcirev; | |
cd0ff491 | 596 | u32 msg_enable; |
29bdd921 GFT |
597 | struct ethtool_cmd old_ecmd; |
598 | unsigned int old_mtu; | |
5141719b | 599 | #ifndef __UNIFY_VLAN_RX_PATH__ |
cd0ff491 | 600 | struct vlan_group *vlgrp; |
5141719b | 601 | #endif |
3bf61c55 GFT |
602 | struct dynpcc_info dpi; |
603 | atomic_t intr_sem; | |
fcf45b4c GFT |
604 | atomic_t link_changing; |
605 | atomic_t tx_cleaning; | |
606 | atomic_t rx_cleaning; | |
192570e0 | 607 | atomic_t rx_empty; |
cdcdc9eb | 608 | int (*jme_rx)(struct sk_buff *skb); |
5141719b | 609 | #ifndef __UNIFY_VLAN_RX_PATH__ |
cdcdc9eb GFT |
610 | int (*jme_vlan_rx)(struct sk_buff *skb, |
611 | struct vlan_group *grp, | |
612 | unsigned short vlan_tag); | |
5141719b | 613 | #endif |
cdcdc9eb | 614 | DECLARE_NAPI_STRUCT |
3bf61c55 | 615 | DECLARE_NET_DEVICE_STATS |
d7699f87 | 616 | }; |
cd0ff491 | 617 | |
3b70a6fa GFT |
618 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) |
619 | static struct net_device_stats * | |
620 | jme_get_stats(struct net_device *netdev) | |
621 | { | |
622 | struct jme_adapter *jme = netdev_priv(netdev); | |
623 | return &jme->stats; | |
624 | } | |
625 | #endif | |
626 | ||
79ce639c | 627 | enum jme_flags_bits { |
cd0ff491 GFT |
628 | JME_FLAG_MSI = 1, |
629 | JME_FLAG_SSET = 2, | |
767e5b98 | 630 | #ifndef __USE_NDO_FIX_FEATURES__ |
cd0ff491 GFT |
631 | JME_FLAG_TXCSUM = 3, |
632 | JME_FLAG_TSO = 4, | |
767e5b98 | 633 | #endif |
cd0ff491 GFT |
634 | JME_FLAG_POLL = 5, |
635 | JME_FLAG_SHUTDOWN = 6, | |
8c198884 | 636 | }; |
cd0ff491 GFT |
637 | |
638 | #define TX_TIMEOUT (5 * HZ) | |
186fc259 | 639 | #define JME_REG_LEN 0x500 |
cd0ff491 | 640 | #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 |
8c198884 | 641 | |
85776f33 | 642 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) |
7ee473a3 | 643 | static inline struct jme_adapter* |
85776f33 GFT |
644 | jme_napi_priv(struct net_device *holder) |
645 | { | |
7ee473a3 | 646 | struct jme_adapter *jme; |
85776f33 GFT |
647 | jme = netdev_priv(holder); |
648 | return jme; | |
649 | } | |
650 | #else | |
7ee473a3 | 651 | static inline struct jme_adapter* |
cdcdc9eb GFT |
652 | jme_napi_priv(struct napi_struct *napi) |
653 | { | |
7ee473a3 | 654 | struct jme_adapter *jme; |
cdcdc9eb GFT |
655 | jme = container_of(napi, struct jme_adapter, napi); |
656 | return jme; | |
657 | } | |
85776f33 | 658 | #endif |
d7699f87 GFT |
659 | |
660 | /* | |
661 | * MMaped I/O Resters | |
662 | */ | |
663 | enum jme_iomap_offsets { | |
4330c2f2 GFT |
664 | JME_MAC = 0x0000, |
665 | JME_PHY = 0x0400, | |
d7699f87 | 666 | JME_MISC = 0x0800, |
4330c2f2 | 667 | JME_RSS = 0x0C00, |
d7699f87 GFT |
668 | }; |
669 | ||
8c198884 GFT |
670 | enum jme_iomap_lens { |
671 | JME_MAC_LEN = 0x80, | |
672 | JME_PHY_LEN = 0x58, | |
673 | JME_MISC_LEN = 0x98, | |
674 | JME_RSS_LEN = 0xFF, | |
675 | }; | |
676 | ||
d7699f87 GFT |
677 | enum jme_iomap_regs { |
678 | JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */ | |
3bf61c55 GFT |
679 | JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */ |
680 | JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */ | |
d7699f87 GFT |
681 | JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */ |
682 | JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */ | |
683 | JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */ | |
684 | JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */ | |
685 | JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */ | |
686 | ||
687 | JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */ | |
3bf61c55 GFT |
688 | JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */ |
689 | JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */ | |
d7699f87 GFT |
690 | JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */ |
691 | JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */ | |
692 | JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */ | |
4330c2f2 GFT |
693 | JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */ |
694 | JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */ | |
3bf61c55 GFT |
695 | JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */ |
696 | JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */ | |
d7699f87 GFT |
697 | JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */ |
698 | JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */ | |
699 | ||
700 | JME_SMI = JME_MAC | 0x50, /* Station Management Interface */ | |
701 | JME_GHC = JME_MAC | 0x54, /* Global Host Control */ | |
702 | JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */ | |
703 | ||
704 | ||
ed457bcc | 705 | JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */ |
3bf61c55 | 706 | JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */ |
d7699f87 GFT |
707 | JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */ |
708 | JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ | |
186fc259 | 709 | JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */ |
d7699f87 GFT |
710 | |
711 | ||
cd0ff491 GFT |
712 | JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */ |
713 | JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */ | |
714 | JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */ | |
715 | JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */ | |
716 | JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */ | |
717 | JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */ | |
718 | JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */ | |
719 | JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */ | |
720 | JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */ | |
721 | JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */ | |
722 | JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */ | |
723 | JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */ | |
724 | JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */ | |
725 | JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */ | |
726 | JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */ | |
727 | JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */ | |
d7699f87 GFT |
728 | }; |
729 | ||
730 | /* | |
731 | * TX Control/Status Bits | |
732 | */ | |
733 | enum jme_txcs_bits { | |
734 | TXCS_QUEUE7S = 0x00008000, | |
735 | TXCS_QUEUE6S = 0x00004000, | |
736 | TXCS_QUEUE5S = 0x00002000, | |
737 | TXCS_QUEUE4S = 0x00001000, | |
738 | TXCS_QUEUE3S = 0x00000800, | |
739 | TXCS_QUEUE2S = 0x00000400, | |
740 | TXCS_QUEUE1S = 0x00000200, | |
741 | TXCS_QUEUE0S = 0x00000100, | |
742 | TXCS_FIFOTH = 0x000000C0, | |
743 | TXCS_DMASIZE = 0x00000030, | |
744 | TXCS_BURST = 0x00000004, | |
745 | TXCS_ENABLE = 0x00000001, | |
746 | }; | |
cd0ff491 | 747 | |
d7699f87 GFT |
748 | enum jme_txcs_value { |
749 | TXCS_FIFOTH_16QW = 0x000000C0, | |
750 | TXCS_FIFOTH_12QW = 0x00000080, | |
751 | TXCS_FIFOTH_8QW = 0x00000040, | |
752 | TXCS_FIFOTH_4QW = 0x00000000, | |
753 | ||
754 | TXCS_DMASIZE_64B = 0x00000000, | |
755 | TXCS_DMASIZE_128B = 0x00000010, | |
756 | TXCS_DMASIZE_256B = 0x00000020, | |
757 | TXCS_DMASIZE_512B = 0x00000030, | |
758 | ||
759 | TXCS_SELECT_QUEUE0 = 0x00000000, | |
760 | TXCS_SELECT_QUEUE1 = 0x00010000, | |
761 | TXCS_SELECT_QUEUE2 = 0x00020000, | |
762 | TXCS_SELECT_QUEUE3 = 0x00030000, | |
763 | TXCS_SELECT_QUEUE4 = 0x00040000, | |
764 | TXCS_SELECT_QUEUE5 = 0x00050000, | |
765 | TXCS_SELECT_QUEUE6 = 0x00060000, | |
766 | TXCS_SELECT_QUEUE7 = 0x00070000, | |
767 | ||
768 | TXCS_DEFAULT = TXCS_FIFOTH_4QW | | |
d7699f87 GFT |
769 | TXCS_BURST, |
770 | }; | |
cd0ff491 | 771 | |
29bdd921 | 772 | #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */ |
d7699f87 GFT |
773 | |
774 | /* | |
775 | * TX MAC Control/Status Bits | |
776 | */ | |
777 | enum jme_txmcs_bit_masks { | |
778 | TXMCS_IFG2 = 0xC0000000, | |
779 | TXMCS_IFG1 = 0x30000000, | |
780 | TXMCS_TTHOLD = 0x00000300, | |
781 | TXMCS_FBURST = 0x00000080, | |
782 | TXMCS_CARRIEREXT = 0x00000040, | |
783 | TXMCS_DEFER = 0x00000020, | |
784 | TXMCS_BACKOFF = 0x00000010, | |
785 | TXMCS_CARRIERSENSE = 0x00000008, | |
786 | TXMCS_COLLISION = 0x00000004, | |
787 | TXMCS_CRC = 0x00000002, | |
788 | TXMCS_PADDING = 0x00000001, | |
789 | }; | |
cd0ff491 | 790 | |
d7699f87 GFT |
791 | enum jme_txmcs_values { |
792 | TXMCS_IFG2_6_4 = 0x00000000, | |
793 | TXMCS_IFG2_8_5 = 0x40000000, | |
794 | TXMCS_IFG2_10_6 = 0x80000000, | |
795 | TXMCS_IFG2_12_7 = 0xC0000000, | |
796 | ||
797 | TXMCS_IFG1_8_4 = 0x00000000, | |
798 | TXMCS_IFG1_12_6 = 0x10000000, | |
799 | TXMCS_IFG1_16_8 = 0x20000000, | |
800 | TXMCS_IFG1_20_10 = 0x30000000, | |
801 | ||
802 | TXMCS_TTHOLD_1_8 = 0x00000000, | |
803 | TXMCS_TTHOLD_1_4 = 0x00000100, | |
804 | TXMCS_TTHOLD_1_2 = 0x00000200, | |
805 | TXMCS_TTHOLD_FULL = 0x00000300, | |
806 | ||
807 | TXMCS_DEFAULT = TXMCS_IFG2_8_5 | | |
808 | TXMCS_IFG1_16_8 | | |
809 | TXMCS_TTHOLD_FULL | | |
810 | TXMCS_DEFER | | |
811 | TXMCS_CRC | | |
812 | TXMCS_PADDING, | |
813 | }; | |
814 | ||
8c198884 GFT |
815 | enum jme_txpfc_bits_masks { |
816 | TXPFC_VLAN_TAG = 0xFFFF0000, | |
817 | TXPFC_VLAN_EN = 0x00008000, | |
818 | TXPFC_PF_EN = 0x00000001, | |
819 | }; | |
820 | ||
821 | enum jme_txtrhd_bits_masks { | |
822 | TXTRHD_TXPEN = 0x80000000, | |
823 | TXTRHD_TXP = 0x7FFFFF00, | |
824 | TXTRHD_TXREN = 0x00000080, | |
825 | TXTRHD_TXRL = 0x0000007F, | |
826 | }; | |
cd0ff491 | 827 | |
8c198884 GFT |
828 | enum jme_txtrhd_shifts { |
829 | TXTRHD_TXP_SHIFT = 8, | |
830 | TXTRHD_TXRL_SHIFT = 0, | |
831 | }; | |
832 | ||
809b2798 GFT |
833 | enum jme_txtrhd_values { |
834 | TXTRHD_FULLDUPLEX = 0x00000000, | |
835 | TXTRHD_HALFDUPLEX = TXTRHD_TXPEN | | |
836 | ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) | | |
837 | TXTRHD_TXREN | | |
838 | ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL), | |
839 | }; | |
840 | ||
d7699f87 GFT |
841 | /* |
842 | * RX Control/Status Bits | |
843 | */ | |
4330c2f2 | 844 | enum jme_rxcs_bit_masks { |
3bf61c55 GFT |
845 | /* FIFO full threshold for transmitting Tx Pause Packet */ |
846 | RXCS_FIFOTHTP = 0x30000000, | |
847 | /* FIFO threshold for processing next packet */ | |
848 | RXCS_FIFOTHNP = 0x0C000000, | |
4330c2f2 GFT |
849 | RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */ |
850 | RXCS_QUEUESEL = 0x00030000, /* Queue selection */ | |
851 | RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */ | |
852 | RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */ | |
853 | RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */ | |
854 | RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */ | |
855 | RXCS_SHORT = 0x00000010, /* Enable receive short packet */ | |
856 | RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */ | |
857 | RXCS_QST = 0x00000004, /* Receive queue start */ | |
858 | RXCS_SUSPEND = 0x00000002, | |
d7699f87 GFT |
859 | RXCS_ENABLE = 0x00000001, |
860 | }; | |
cd0ff491 | 861 | |
4330c2f2 GFT |
862 | enum jme_rxcs_values { |
863 | RXCS_FIFOTHTP_16T = 0x00000000, | |
864 | RXCS_FIFOTHTP_32T = 0x10000000, | |
865 | RXCS_FIFOTHTP_64T = 0x20000000, | |
866 | RXCS_FIFOTHTP_128T = 0x30000000, | |
867 | ||
868 | RXCS_FIFOTHNP_16QW = 0x00000000, | |
869 | RXCS_FIFOTHNP_32QW = 0x04000000, | |
870 | RXCS_FIFOTHNP_64QW = 0x08000000, | |
871 | RXCS_FIFOTHNP_128QW = 0x0C000000, | |
872 | ||
873 | RXCS_DMAREQSZ_16B = 0x00000000, | |
874 | RXCS_DMAREQSZ_32B = 0x01000000, | |
875 | RXCS_DMAREQSZ_64B = 0x02000000, | |
876 | RXCS_DMAREQSZ_128B = 0x03000000, | |
877 | ||
878 | RXCS_QUEUESEL_Q0 = 0x00000000, | |
879 | RXCS_QUEUESEL_Q1 = 0x00010000, | |
880 | RXCS_QUEUESEL_Q2 = 0x00020000, | |
881 | RXCS_QUEUESEL_Q3 = 0x00030000, | |
882 | ||
883 | RXCS_RETRYGAP_256ns = 0x00000000, | |
884 | RXCS_RETRYGAP_512ns = 0x00001000, | |
885 | RXCS_RETRYGAP_1024ns = 0x00002000, | |
886 | RXCS_RETRYGAP_2048ns = 0x00003000, | |
887 | RXCS_RETRYGAP_4096ns = 0x00004000, | |
888 | RXCS_RETRYGAP_8192ns = 0x00005000, | |
889 | RXCS_RETRYGAP_16384ns = 0x00006000, | |
890 | RXCS_RETRYGAP_32768ns = 0x00007000, | |
891 | ||
892 | RXCS_RETRYCNT_0 = 0x00000000, | |
893 | RXCS_RETRYCNT_4 = 0x00000100, | |
894 | RXCS_RETRYCNT_8 = 0x00000200, | |
895 | RXCS_RETRYCNT_12 = 0x00000300, | |
896 | RXCS_RETRYCNT_16 = 0x00000400, | |
897 | RXCS_RETRYCNT_20 = 0x00000500, | |
898 | RXCS_RETRYCNT_24 = 0x00000600, | |
899 | RXCS_RETRYCNT_28 = 0x00000700, | |
900 | RXCS_RETRYCNT_32 = 0x00000800, | |
901 | RXCS_RETRYCNT_36 = 0x00000900, | |
902 | RXCS_RETRYCNT_40 = 0x00000A00, | |
903 | RXCS_RETRYCNT_44 = 0x00000B00, | |
904 | RXCS_RETRYCNT_48 = 0x00000C00, | |
905 | RXCS_RETRYCNT_52 = 0x00000D00, | |
906 | RXCS_RETRYCNT_56 = 0x00000E00, | |
907 | RXCS_RETRYCNT_60 = 0x00000F00, | |
908 | ||
909 | RXCS_DEFAULT = RXCS_FIFOTHTP_128T | | |
79ce639c | 910 | RXCS_FIFOTHNP_128QW | |
4330c2f2 GFT |
911 | RXCS_DMAREQSZ_128B | |
912 | RXCS_RETRYGAP_256ns | | |
913 | RXCS_RETRYCNT_32, | |
914 | }; | |
cd0ff491 | 915 | |
29bdd921 | 916 | #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */ |
d7699f87 GFT |
917 | |
918 | /* | |
919 | * RX MAC Control/Status Bits | |
920 | */ | |
921 | enum jme_rxmcs_bits { | |
922 | RXMCS_ALLFRAME = 0x00000800, | |
923 | RXMCS_BRDFRAME = 0x00000400, | |
924 | RXMCS_MULFRAME = 0x00000200, | |
925 | RXMCS_UNIFRAME = 0x00000100, | |
926 | RXMCS_ALLMULFRAME = 0x00000080, | |
927 | RXMCS_MULFILTERED = 0x00000040, | |
3bf61c55 GFT |
928 | RXMCS_RXCOLLDEC = 0x00000020, |
929 | RXMCS_FLOWCTRL = 0x00000008, | |
930 | RXMCS_VTAGRM = 0x00000004, | |
931 | RXMCS_PREPAD = 0x00000002, | |
932 | RXMCS_CHECKSUM = 0x00000001, | |
b3821cc5 | 933 | |
8c198884 GFT |
934 | RXMCS_DEFAULT = RXMCS_VTAGRM | |
935 | RXMCS_PREPAD | | |
936 | RXMCS_FLOWCTRL | | |
937 | RXMCS_CHECKSUM, | |
d7699f87 GFT |
938 | }; |
939 | ||
b3821cc5 GFT |
940 | /* |
941 | * Wakeup Frame setup interface registers | |
942 | */ | |
943 | #define WAKEUP_FRAME_NR 8 | |
944 | #define WAKEUP_FRAME_MASK_DWNR 4 | |
cd0ff491 | 945 | |
b3821cc5 GFT |
946 | enum jme_wfoi_bit_masks { |
947 | WFOI_MASK_SEL = 0x00000070, | |
948 | WFOI_CRC_SEL = 0x00000008, | |
949 | WFOI_FRAME_SEL = 0x00000007, | |
950 | }; | |
cd0ff491 | 951 | |
b3821cc5 GFT |
952 | enum jme_wfoi_shifts { |
953 | WFOI_MASK_SHIFT = 4, | |
954 | }; | |
955 | ||
d7699f87 GFT |
956 | /* |
957 | * SMI Related definitions | |
958 | */ | |
cd0ff491 | 959 | enum jme_smi_bit_mask { |
d7699f87 GFT |
960 | SMI_DATA_MASK = 0xFFFF0000, |
961 | SMI_REG_ADDR_MASK = 0x0000F800, | |
962 | SMI_PHY_ADDR_MASK = 0x000007C0, | |
963 | SMI_OP_WRITE = 0x00000020, | |
3bf61c55 GFT |
964 | /* Set to 1, after req done it'll be cleared to 0 */ |
965 | SMI_OP_REQ = 0x00000010, | |
d7699f87 GFT |
966 | SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */ |
967 | SMI_OP_MDOE = 0x00000004, /* Software Output Enable */ | |
968 | SMI_OP_MDC = 0x00000002, /* Software CLK Control */ | |
969 | SMI_OP_MDEN = 0x00000001, /* Software access Enable */ | |
970 | }; | |
cd0ff491 GFT |
971 | |
972 | enum jme_smi_bit_shift { | |
d7699f87 GFT |
973 | SMI_DATA_SHIFT = 16, |
974 | SMI_REG_ADDR_SHIFT = 11, | |
975 | SMI_PHY_ADDR_SHIFT = 6, | |
976 | }; | |
cd0ff491 GFT |
977 | |
978 | static inline u32 smi_reg_addr(int x) | |
d7699f87 | 979 | { |
cd0ff491 | 980 | return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK; |
d7699f87 | 981 | } |
cd0ff491 GFT |
982 | |
983 | static inline u32 smi_phy_addr(int x) | |
d7699f87 | 984 | { |
cd0ff491 | 985 | return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK; |
d7699f87 | 986 | } |
cd0ff491 | 987 | |
8d27293f | 988 | #define JME_PHY_TIMEOUT 100 /* 100 msec */ |
186fc259 | 989 | #define JME_PHY_REG_NR 32 |
d7699f87 GFT |
990 | |
991 | /* | |
992 | * Global Host Control | |
993 | */ | |
994 | enum jme_ghc_bit_mask { | |
3b70a6fa | 995 | GHC_SWRST = 0x40000000, |
dc4185bd GFT |
996 | GHC_TO_CLK_SRC = 0x00C00000, |
997 | GHC_TXMAC_CLK_SRC = 0x00300000, | |
3b70a6fa GFT |
998 | GHC_DPX = 0x00000040, |
999 | GHC_SPEED = 0x00000030, | |
1000 | GHC_LINK_POLL = 0x00000001, | |
d7699f87 | 1001 | }; |
cd0ff491 | 1002 | |
d7699f87 | 1003 | enum jme_ghc_speed_val { |
3b70a6fa GFT |
1004 | GHC_SPEED_10M = 0x00000010, |
1005 | GHC_SPEED_100M = 0x00000020, | |
1006 | GHC_SPEED_1000M = 0x00000030, | |
1007 | }; | |
1008 | ||
1009 | enum jme_ghc_to_clk { | |
1010 | GHC_TO_CLK_OFF = 0x00000000, | |
1011 | GHC_TO_CLK_GPHY = 0x00400000, | |
1012 | GHC_TO_CLK_PCIE = 0x00800000, | |
1013 | GHC_TO_CLK_INVALID = 0x00C00000, | |
1014 | }; | |
1015 | ||
1016 | enum jme_ghc_txmac_clk { | |
1017 | GHC_TXMAC_CLK_OFF = 0x00000000, | |
1018 | GHC_TXMAC_CLK_GPHY = 0x00100000, | |
1019 | GHC_TXMAC_CLK_PCIE = 0x00200000, | |
1020 | GHC_TXMAC_CLK_INVALID = 0x00300000, | |
d7699f87 GFT |
1021 | }; |
1022 | ||
29bdd921 GFT |
1023 | /* |
1024 | * Power management control and status register | |
1025 | */ | |
1026 | enum jme_pmcs_bit_masks { | |
3d12cc1b | 1027 | PMCS_STMASK = 0xFFFF0000, |
29bdd921 GFT |
1028 | PMCS_WF7DET = 0x80000000, |
1029 | PMCS_WF6DET = 0x40000000, | |
1030 | PMCS_WF5DET = 0x20000000, | |
1031 | PMCS_WF4DET = 0x10000000, | |
1032 | PMCS_WF3DET = 0x08000000, | |
1033 | PMCS_WF2DET = 0x04000000, | |
1034 | PMCS_WF1DET = 0x02000000, | |
1035 | PMCS_WF0DET = 0x01000000, | |
1036 | PMCS_LFDET = 0x00040000, | |
1037 | PMCS_LRDET = 0x00020000, | |
1038 | PMCS_MFDET = 0x00010000, | |
3d12cc1b | 1039 | PMCS_ENMASK = 0x0000FFFF, |
29bdd921 GFT |
1040 | PMCS_WF7EN = 0x00008000, |
1041 | PMCS_WF6EN = 0x00004000, | |
1042 | PMCS_WF5EN = 0x00002000, | |
1043 | PMCS_WF4EN = 0x00001000, | |
1044 | PMCS_WF3EN = 0x00000800, | |
1045 | PMCS_WF2EN = 0x00000400, | |
1046 | PMCS_WF1EN = 0x00000200, | |
1047 | PMCS_WF0EN = 0x00000100, | |
1048 | PMCS_LFEN = 0x00000004, | |
1049 | PMCS_LREN = 0x00000002, | |
1050 | PMCS_MFEN = 0x00000001, | |
1051 | }; | |
1052 | ||
ed457bcc GFT |
1053 | /* |
1054 | * New PHY Power Control Register | |
1055 | */ | |
1056 | enum jme_phy_pwr_bit_masks { | |
1057 | PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */ | |
1058 | PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */ | |
1059 | PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */ | |
1060 | PHY_PWR_CLKSEL = 0x08000000, /* | |
1061 | * XTL_OUT Clock select | |
1062 | * (an internal free-running clock) | |
1063 | * 0: xtl_out = phy_giga.A_XTL25_O | |
1064 | * 1: xtl_out = phy_giga.PD_OSC | |
1065 | */ | |
1066 | }; | |
1067 | ||
d7699f87 | 1068 | /* |
3bf61c55 | 1069 | * Giga PHY Status Registers |
d7699f87 GFT |
1070 | */ |
1071 | enum jme_phy_link_bit_mask { | |
1072 | PHY_LINK_SPEED_MASK = 0x0000C000, | |
1073 | PHY_LINK_DUPLEX = 0x00002000, | |
1074 | PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800, | |
1075 | PHY_LINK_UP = 0x00000400, | |
1076 | PHY_LINK_AUTONEG_COMPLETE = 0x00000200, | |
fcf45b4c | 1077 | PHY_LINK_MDI_STAT = 0x00000040, |
d7699f87 | 1078 | }; |
cd0ff491 | 1079 | |
d7699f87 GFT |
1080 | enum jme_phy_link_speed_val { |
1081 | PHY_LINK_SPEED_10M = 0x00000000, | |
1082 | PHY_LINK_SPEED_100M = 0x00004000, | |
1083 | PHY_LINK_SPEED_1000M = 0x00008000, | |
1084 | }; | |
cd0ff491 | 1085 | |
fcf45b4c | 1086 | #define JME_SPDRSV_TIMEOUT 500 /* 500 us */ |
d7699f87 GFT |
1087 | |
1088 | /* | |
1089 | * SMB Control and Status | |
1090 | */ | |
79ce639c | 1091 | enum jme_smbcsr_bit_mask { |
d7699f87 GFT |
1092 | SMBCSR_CNACK = 0x00020000, |
1093 | SMBCSR_RELOAD = 0x00010000, | |
1094 | SMBCSR_EEPROMD = 0x00000020, | |
186fc259 GFT |
1095 | SMBCSR_INITDONE = 0x00000010, |
1096 | SMBCSR_BUSY = 0x0000000F, | |
1097 | }; | |
cd0ff491 | 1098 | |
186fc259 GFT |
1099 | enum jme_smbintf_bit_mask { |
1100 | SMBINTF_HWDATR = 0xFF000000, | |
1101 | SMBINTF_HWDATW = 0x00FF0000, | |
1102 | SMBINTF_HWADDR = 0x0000FF00, | |
1103 | SMBINTF_HWRWN = 0x00000020, | |
1104 | SMBINTF_HWCMD = 0x00000010, | |
1105 | SMBINTF_FASTM = 0x00000008, | |
1106 | SMBINTF_GPIOSCL = 0x00000004, | |
1107 | SMBINTF_GPIOSDA = 0x00000002, | |
1108 | SMBINTF_GPIOEN = 0x00000001, | |
1109 | }; | |
cd0ff491 | 1110 | |
186fc259 GFT |
1111 | enum jme_smbintf_vals { |
1112 | SMBINTF_HWRWN_READ = 0x00000020, | |
1113 | SMBINTF_HWRWN_WRITE = 0x00000000, | |
1114 | }; | |
cd0ff491 | 1115 | |
186fc259 GFT |
1116 | enum jme_smbintf_shifts { |
1117 | SMBINTF_HWDATR_SHIFT = 24, | |
1118 | SMBINTF_HWDATW_SHIFT = 16, | |
1119 | SMBINTF_HWADDR_SHIFT = 8, | |
1120 | }; | |
cd0ff491 | 1121 | |
186fc259 GFT |
1122 | #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */ |
1123 | #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */ | |
1124 | #define JME_SMB_LEN 256 | |
1125 | #define JME_EEPROM_MAGIC 0x250 | |
d7699f87 | 1126 | |
79ce639c GFT |
1127 | /* |
1128 | * Timer Control/Status Register | |
1129 | */ | |
1130 | enum jme_tmcsr_bit_masks { | |
1131 | TMCSR_SWIT = 0x80000000, | |
1132 | TMCSR_EN = 0x01000000, | |
1133 | TMCSR_CNT = 0x00FFFFFF, | |
1134 | }; | |
1135 | ||
4330c2f2 | 1136 | /* |
cd0ff491 | 1137 | * General Purpose REG-0 |
4330c2f2 GFT |
1138 | */ |
1139 | enum jme_gpreg0_masks { | |
3bf61c55 GFT |
1140 | GPREG0_DISSH = 0xFF000000, |
1141 | GPREG0_PCIRLMT = 0x00300000, | |
1142 | GPREG0_PCCNOMUTCLR = 0x00040000, | |
cdcdc9eb | 1143 | GPREG0_LNKINTPOLL = 0x00001000, |
3bf61c55 GFT |
1144 | GPREG0_PCCTMR = 0x00000300, |
1145 | GPREG0_PHYADDR = 0x0000001F, | |
4330c2f2 | 1146 | }; |
cd0ff491 | 1147 | |
4330c2f2 GFT |
1148 | enum jme_gpreg0_vals { |
1149 | GPREG0_DISSH_DW7 = 0x80000000, | |
1150 | GPREG0_DISSH_DW6 = 0x40000000, | |
1151 | GPREG0_DISSH_DW5 = 0x20000000, | |
1152 | GPREG0_DISSH_DW4 = 0x10000000, | |
1153 | GPREG0_DISSH_DW3 = 0x08000000, | |
1154 | GPREG0_DISSH_DW2 = 0x04000000, | |
1155 | GPREG0_DISSH_DW1 = 0x02000000, | |
1156 | GPREG0_DISSH_DW0 = 0x01000000, | |
1157 | GPREG0_DISSH_ALL = 0xFF000000, | |
1158 | ||
1159 | GPREG0_PCIRLMT_8 = 0x00000000, | |
1160 | GPREG0_PCIRLMT_6 = 0x00100000, | |
1161 | GPREG0_PCIRLMT_5 = 0x00200000, | |
1162 | GPREG0_PCIRLMT_4 = 0x00300000, | |
1163 | ||
1164 | GPREG0_PCCTMR_16ns = 0x00000000, | |
3bf61c55 GFT |
1165 | GPREG0_PCCTMR_256ns = 0x00000100, |
1166 | GPREG0_PCCTMR_1us = 0x00000200, | |
1167 | GPREG0_PCCTMR_1ms = 0x00000300, | |
4330c2f2 GFT |
1168 | |
1169 | GPREG0_PHYADDR_1 = 0x00000001, | |
1170 | ||
1171 | GPREG0_DEFAULT = GPREG0_PCIRLMT_4 | | |
3bf61c55 GFT |
1172 | GPREG0_PCCTMR_1us | |
1173 | GPREG0_PHYADDR_1, | |
4330c2f2 GFT |
1174 | }; |
1175 | ||
7ee473a3 GFT |
1176 | /* |
1177 | * General Purpose REG-1 | |
7ee473a3 | 1178 | */ |
dc4185bd GFT |
1179 | enum jme_gpreg1_bit_masks { |
1180 | GPREG1_RXCLKOFF = 0x04000000, | |
1181 | GPREG1_PCREQN = 0x00020000, | |
1182 | GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */ | |
1183 | GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */ | |
7ee473a3 GFT |
1184 | GPREG1_INTRDELAYUNIT = 0x00000018, |
1185 | GPREG1_INTRDELAYENABLE = 0x00000007, | |
1186 | }; | |
1187 | ||
1188 | enum jme_gpreg1_vals { | |
7ee473a3 GFT |
1189 | GPREG1_INTDLYUNIT_16NS = 0x00000000, |
1190 | GPREG1_INTDLYUNIT_256NS = 0x00000008, | |
1191 | GPREG1_INTDLYUNIT_1US = 0x00000010, | |
1192 | GPREG1_INTDLYUNIT_16US = 0x00000018, | |
1193 | ||
1194 | GPREG1_INTDLYEN_1U = 0x00000001, | |
1195 | GPREG1_INTDLYEN_2U = 0x00000002, | |
1196 | GPREG1_INTDLYEN_3U = 0x00000003, | |
1197 | GPREG1_INTDLYEN_4U = 0x00000004, | |
1198 | GPREG1_INTDLYEN_5U = 0x00000005, | |
1199 | GPREG1_INTDLYEN_6U = 0x00000006, | |
1200 | GPREG1_INTDLYEN_7U = 0x00000007, | |
1201 | ||
dc4185bd | 1202 | GPREG1_DEFAULT = GPREG1_PCREQN, |
7ee473a3 GFT |
1203 | }; |
1204 | ||
d7699f87 GFT |
1205 | /* |
1206 | * Interrupt Status Bits | |
1207 | */ | |
cd0ff491 | 1208 | enum jme_interrupt_bits { |
d7699f87 GFT |
1209 | INTR_SWINTR = 0x80000000, |
1210 | INTR_TMINTR = 0x40000000, | |
1211 | INTR_LINKCH = 0x20000000, | |
1212 | INTR_PAUSERCV = 0x10000000, | |
1213 | INTR_MAGICRCV = 0x08000000, | |
1214 | INTR_WAKERCV = 0x04000000, | |
1215 | INTR_PCCRX0TO = 0x02000000, | |
1216 | INTR_PCCRX1TO = 0x01000000, | |
1217 | INTR_PCCRX2TO = 0x00800000, | |
1218 | INTR_PCCRX3TO = 0x00400000, | |
1219 | INTR_PCCTXTO = 0x00200000, | |
1220 | INTR_PCCRX0 = 0x00100000, | |
1221 | INTR_PCCRX1 = 0x00080000, | |
1222 | INTR_PCCRX2 = 0x00040000, | |
1223 | INTR_PCCRX3 = 0x00020000, | |
1224 | INTR_PCCTX = 0x00010000, | |
1225 | INTR_RX3EMP = 0x00008000, | |
1226 | INTR_RX2EMP = 0x00004000, | |
1227 | INTR_RX1EMP = 0x00002000, | |
1228 | INTR_RX0EMP = 0x00001000, | |
1229 | INTR_RX3 = 0x00000800, | |
1230 | INTR_RX2 = 0x00000400, | |
1231 | INTR_RX1 = 0x00000200, | |
1232 | INTR_RX0 = 0x00000100, | |
1233 | INTR_TX7 = 0x00000080, | |
1234 | INTR_TX6 = 0x00000040, | |
1235 | INTR_TX5 = 0x00000020, | |
1236 | INTR_TX4 = 0x00000010, | |
1237 | INTR_TX3 = 0x00000008, | |
1238 | INTR_TX2 = 0x00000004, | |
1239 | INTR_TX1 = 0x00000002, | |
1240 | INTR_TX0 = 0x00000001, | |
1241 | }; | |
cd0ff491 GFT |
1242 | |
1243 | static const u32 INTR_ENABLE = INTR_SWINTR | | |
79ce639c GFT |
1244 | INTR_TMINTR | |
1245 | INTR_LINKCH | | |
3bf61c55 GFT |
1246 | INTR_PCCRX0TO | |
1247 | INTR_PCCRX0 | | |
1248 | INTR_PCCTXTO | | |
cdcdc9eb GFT |
1249 | INTR_PCCTX | |
1250 | INTR_RX0EMP; | |
3bf61c55 GFT |
1251 | |
1252 | /* | |
1253 | * PCC Control Registers | |
1254 | */ | |
1255 | enum jme_pccrx_masks { | |
1256 | PCCRXTO_MASK = 0xFFFF0000, | |
1257 | PCCRX_MASK = 0x0000FF00, | |
1258 | }; | |
cd0ff491 | 1259 | |
3bf61c55 GFT |
1260 | enum jme_pcctx_masks { |
1261 | PCCTXTO_MASK = 0xFFFF0000, | |
1262 | PCCTX_MASK = 0x0000FF00, | |
1263 | PCCTX_QS_MASK = 0x000000FF, | |
1264 | }; | |
cd0ff491 | 1265 | |
3bf61c55 GFT |
1266 | enum jme_pccrx_shifts { |
1267 | PCCRXTO_SHIFT = 16, | |
1268 | PCCRX_SHIFT = 8, | |
1269 | }; | |
cd0ff491 | 1270 | |
3bf61c55 GFT |
1271 | enum jme_pcctx_shifts { |
1272 | PCCTXTO_SHIFT = 16, | |
1273 | PCCTX_SHIFT = 8, | |
1274 | }; | |
cd0ff491 | 1275 | |
3bf61c55 GFT |
1276 | enum jme_pcctx_bits { |
1277 | PCCTXQ0_EN = 0x00000001, | |
1278 | PCCTXQ1_EN = 0x00000002, | |
1279 | PCCTXQ2_EN = 0x00000004, | |
1280 | PCCTXQ3_EN = 0x00000008, | |
1281 | PCCTXQ4_EN = 0x00000010, | |
1282 | PCCTXQ5_EN = 0x00000020, | |
1283 | PCCTXQ6_EN = 0x00000040, | |
1284 | PCCTXQ7_EN = 0x00000080, | |
1285 | }; | |
1286 | ||
cdcdc9eb GFT |
1287 | /* |
1288 | * Chip Mode Register | |
1289 | */ | |
1290 | enum jme_chipmode_bit_masks { | |
1291 | CM_FPGAVER_MASK = 0xFFFF0000, | |
58c92f28 | 1292 | CM_CHIPREV_MASK = 0x0000FF00, |
cdcdc9eb GFT |
1293 | CM_CHIPMODE_MASK = 0x0000000F, |
1294 | }; | |
cd0ff491 | 1295 | |
cdcdc9eb GFT |
1296 | enum jme_chipmode_shifts { |
1297 | CM_FPGAVER_SHIFT = 16, | |
58c92f28 | 1298 | CM_CHIPREV_SHIFT = 8, |
cdcdc9eb | 1299 | }; |
d7699f87 | 1300 | |
cd0ff491 GFT |
1301 | /* |
1302 | * Aggressive Power Mode Control | |
1303 | */ | |
1304 | enum jme_apmc_bits { | |
1305 | JME_APMC_PCIE_SD_EN = 0x40000000, | |
1306 | JME_APMC_PSEUDO_HP_EN = 0x20000000, | |
1307 | JME_APMC_EPIEN = 0x04000000, | |
1308 | JME_APMC_EPIEN_CTRL = 0x03000000, | |
1309 | }; | |
1310 | ||
1311 | enum jme_apmc_values { | |
1312 | JME_APMC_EPIEN_CTRL_EN = 0x02000000, | |
1313 | JME_APMC_EPIEN_CTRL_DIS = 0x01000000, | |
1314 | }; | |
1315 | ||
1316 | #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000) | |
1317 | ||
1318 | #ifdef REG_DEBUG | |
1319 | static char *MAC_REG_NAME[] = { | |
1320 | "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC", | |
1321 | "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD", | |
1322 | "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC", | |
1323 | "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI", | |
1324 | "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI", | |
1325 | "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN", | |
1326 | "JME_PMCS"}; | |
7ee473a3 | 1327 | |
cd0ff491 GFT |
1328 | static char *PE_REG_NAME[] = { |
1329 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1330 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1331 | "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN", | |
1332 | "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1333 | "JME_SMBCSR", "JME_SMBINTF"}; | |
7ee473a3 | 1334 | |
cd0ff491 GFT |
1335 | static char *MISC_REG_NAME[] = { |
1336 | "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1", | |
1337 | "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC", | |
1338 | "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3", | |
1339 | "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO", | |
1340 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1341 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1342 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1343 | "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC", | |
1344 | "JME_PCCSRX0"}; | |
7ee473a3 | 1345 | |
cd0ff491 GFT |
1346 | static inline void reg_dbg(const struct jme_adapter *jme, |
1347 | const char *msg, u32 val, u32 reg) | |
1348 | { | |
1349 | const char *regname; | |
58c92f28 | 1350 | switch (reg & 0xF00) { |
cd0ff491 GFT |
1351 | case 0x000: |
1352 | regname = MAC_REG_NAME[(reg & 0xFF) >> 2]; | |
1353 | break; | |
1354 | case 0x400: | |
1355 | regname = PE_REG_NAME[(reg & 0xFF) >> 2]; | |
1356 | break; | |
1357 | case 0x800: | |
58c92f28 | 1358 | regname = MISC_REG_NAME[(reg & 0xFF) >> 2]; |
cd0ff491 GFT |
1359 | break; |
1360 | default: | |
1361 | regname = PE_REG_NAME[0]; | |
1362 | } | |
1363 | printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name, | |
1364 | msg, val, regname); | |
1365 | } | |
1366 | #else | |
1367 | static inline void reg_dbg(const struct jme_adapter *jme, | |
1368 | const char *msg, u32 val, u32 reg) {} | |
1369 | #endif | |
1370 | ||
d7699f87 GFT |
1371 | /* |
1372 | * Read/Write MMaped I/O Registers | |
1373 | */ | |
cd0ff491 | 1374 | static inline u32 jread32(struct jme_adapter *jme, u32 reg) |
d7699f87 | 1375 | { |
cd0ff491 | 1376 | return readl(jme->regs + reg); |
d7699f87 | 1377 | } |
cd0ff491 GFT |
1378 | |
1379 | static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val) | |
d7699f87 | 1380 | { |
cd0ff491 GFT |
1381 | reg_dbg(jme, "REG WRITE", val, reg); |
1382 | writel(val, jme->regs + reg); | |
1383 | reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); | |
d7699f87 | 1384 | } |
cd0ff491 GFT |
1385 | |
1386 | static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val) | |
d7699f87 GFT |
1387 | { |
1388 | /* | |
1389 | * Read after write should cause flush | |
1390 | */ | |
cd0ff491 GFT |
1391 | reg_dbg(jme, "REG WRITE FLUSH", val, reg); |
1392 | writel(val, jme->regs + reg); | |
1393 | readl(jme->regs + reg); | |
1394 | reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); | |
d7699f87 GFT |
1395 | } |
1396 | ||
cdcdc9eb GFT |
1397 | /* |
1398 | * PHY Regs | |
1399 | */ | |
1400 | enum jme_phy_reg17_bit_masks { | |
1401 | PREG17_SPEED = 0xC000, | |
1402 | PREG17_DUPLEX = 0x2000, | |
1403 | PREG17_SPDRSV = 0x0800, | |
1404 | PREG17_LNKUP = 0x0400, | |
1405 | PREG17_MDI = 0x0040, | |
1406 | }; | |
cd0ff491 | 1407 | |
cdcdc9eb GFT |
1408 | enum jme_phy_reg17_vals { |
1409 | PREG17_SPEED_10M = 0x0000, | |
1410 | PREG17_SPEED_100M = 0x4000, | |
1411 | PREG17_SPEED_1000M = 0x8000, | |
1412 | }; | |
cd0ff491 | 1413 | |
8d27293f | 1414 | #define BMSR_ANCOMP 0x0020 |
cdcdc9eb | 1415 | |
58c92f28 GFT |
1416 | /* |
1417 | * Workaround | |
1418 | */ | |
98ef18f1 | 1419 | static inline int is_buggy250(unsigned short device, u8 chiprev) |
58c92f28 GFT |
1420 | { |
1421 | return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11; | |
1422 | } | |
1423 | ||
ed457bcc GFT |
1424 | static inline int new_phy_power_ctrl(u8 chip_main_rev) |
1425 | { | |
1426 | return chip_main_rev >= 5; | |
1427 | } | |
1428 | ||
d7699f87 | 1429 | /* |
cd0ff491 | 1430 | * Function prototypes |
d7699f87 | 1431 | */ |
d7699f87 | 1432 | static int jme_set_settings(struct net_device *netdev, |
cd0ff491 | 1433 | struct ethtool_cmd *ecmd); |
e523cd89 | 1434 | static void jme_set_unicastaddr(struct net_device *netdev); |
d7699f87 GFT |
1435 | static void jme_set_multi(struct net_device *netdev); |
1436 | ||
cd0ff491 | 1437 | #endif |
e5169728 | 1438 |