Import jme 0.1 source
[jme.git] / jme.h
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d7699f87
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1
2#define DRV_NAME "jme"
3#define DRV_VERSION "0.1"
4#define PFX DRV_NAME ": "
5
6#ifdef DEBUG
7#define dprintk(fmt, args...) \
8 printk(KERN_DEBUG PFX "%s: " fmt, jme->dev->name, ## args);
9#else
10#define dprintk(fmt, args...)
11#endif
12
13#define jprintk(fmt, args...) \
14 printk(KERN_INFO PFX "%s: " fmt, jme->dev->name, ## args);
15
16#undef RX_QUEUE_DEBUG
17
18#define DEFAULT_MSG_ENABLE \
19 (NETIF_MSG_DRV | \
20 NETIF_MSG_PROBE | \
21 NETIF_MSG_LINK | \
22 NETIF_MSG_TIMER | \
23 NETIF_MSG_RX_ERR | \
24 NETIF_MSG_TX_ERR)
25
26#define CHECK_VAR rc
27#define CHECK_AND_GOTO(fun, label, msg) \
28 CHECK_VAR = fun; \
29 if(CHECK_VAR) \
30 { \
31 printk(KERN_ERR PFX msg "\n"); \
32 goto label; \
33 }
34
35/*
36 * TX/RX Descriptors
37 */
38#define RING_DESC_NR 512 /* Must be power of 2 */
39#define TX_DESC_SIZE 16
40#define TX_RING_NR 8
41#define TX_RING_ALLOC_SIZE (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE
42#define TX_RING_SIZE (RING_DESC_NR * TX_DESC_SIZE)
43
44#define TX_BUF_DMA_ALIGN 8
45#define TX_BUF_SIZE 1600
46#define TX_BUF_ALLOC_SIZE TX_BUF_SIZE + TX_BUF_DMA_ALIGN
47
48struct TxDesc {
49 union {
50 __u8 all[16];
51 __u32 dw[4];
52 struct {
53 /* DW0 */
54 __u16 vlan;
55 __u8 rsv1;
56 __u8 flags;
57
58 /* DW1 */
59 __u16 datalen;
60 __u16 mss;
61
62 /* DW2 */
63 __u16 pktsize;
64 __u16 rsv2;
65
66 /* DW3 */
67 __u32 bufaddr;
68 } desc1;
69 };
70};
71enum jme_txdesc_flag_bits {
72 TXFLAG_OWN = 0x80,
73 TXFLAG_INT = 0x40,
74 TXFLAG_TCPCS = 0x10,
75 TXFLAG_UDPCS = 0x08,
76 TXFLAG_IPCS = 0x04,
77 TXFLAG_LSEN = 0x02,
78 TXFLAG_TAGON = 0x01,
79};
80
81
82#define RX_DESC_SIZE 16
83#define RX_RING_NR 4
84#define RX_RING_ALLOC_SIZE (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE
85#define RX_RING_SIZE (RING_DESC_NR * RX_DESC_SIZE)
86
87#define RX_BUF_DMA_ALIGN 8
88#define RX_BUF_SIZE 1600
89#define RX_BUF_ALLOC_SIZE RX_BUF_SIZE + RX_BUF_DMA_ALIGN
90
91struct RxDesc {
92 union {
93 __u8 all[16];
94 __le32 dw[4];
95 struct {
96 /* DW0 */
97 __le16 rsv2;
98 __u8 rsv1;
99 __u8 flags;
100
101 /* DW1 */
102 __le16 datalen;
103 __le16 wbcpl;
104
105 /* DW2 */
106 __le32 bufaddrh;
107
108 /* DW3 */
109 __le32 bufaddrl;
110 } desc1;
111 struct {
112 /* DW0 */
113 __le16 vlan;
114 __le16 flags;
115
116 /* DW1 */
117 __le16 framesize;
118 __u8 stat;
119 __u8 desccnt;
120
121 /* DW2 */
122 __le32 rsshash;
123
124 /* DW3 */
125 __u8 hashfun;
126 __u8 hashtype;
127 __le16 resrv;
128 } descwb;
129 };
130};
131enum jme_rxdesc_flags_bits {
132 RXFLAG_OWN = 0x80,
133 RXFLAG_INT = 0x40,
134 RXFLAG_64BIT = 0x20,
135};
136enum jme_rxwbdesc_flags_bits {
137 RXWBFLAG_OWN = 0x8000,
138 RXWBFLAG_INT = 0x4000,
139 RXWBFLAG_MF = 0x2000,
140 RXWBFLAG_64BIT = 0x2000,
141 RXWBFLAG_TCPON = 0x1000,
142 RXWBFLAG_UDPON = 0x0800,
143 RXWBFLAG_IPCS = 0x0400,
144 RXWBFLAG_TCPCS = 0x0200,
145 RXWBFLAG_UDPCS = 0x0100,
146 RXWBFLAG_TAGON = 0x0080,
147 RXWBFLAG_IPV4 = 0x0040,
148 RXWBFLAG_IPV6 = 0x0020,
149 RXWBFLAG_PAUSE = 0x0010,
150 RXWBFLAG_MAGIC = 0x0008,
151 RXWBFLAG_WAKEUP = 0x0004,
152 RXWBFLAG_DEST = 0x0003,
153};
154enum jme_rxwbdesc_desccnt_mask {
155 RXWBDCNT_WBCPL = 0x80,
156 RXWBDCNT_DCNT = 0x7F,
157};
158
159struct jme_ring {
160 void *alloc; /* pointer to allocated memory */
161 void *desc; /* pointer to ring memory */
162 dma_addr_t dmaalloc; /* phys address of ring alloc */
163 dma_addr_t dma; /* phys address for ring dma */
164
165 /* Virtual addresses for each buffer of Desc */
166 void* buf_virt[RING_DESC_NR];
167 /* Physical addresses for each buffer of Desc */
168 dma_addr_t buf_dma[RING_DESC_NR];
169
170 u16 next_to_use;
171 u16 next_to_clean;
172
173 /*
174 * Kernel requested TX sk_buffs
175 * should be cleared after tx complete
176 */
177 struct sk_buff *tx_skb[RING_DESC_NR];
178};
179
180/*
181 * Jmac Adapter Private data
182 */
183struct jme_adapter {
184 struct pci_dev *pdev;
185 struct net_device *dev;
186 void __iomem *regs;
187 struct mii_if_info mii_if;
188 struct jme_ring rxring[RX_RING_NR];
189 struct jme_ring txring[TX_RING_NR];
190 spinlock_t xmit_lock;
191 spinlock_t recv_lock;
192 spinlock_t macaddr_lock;
193 spinlock_t phy_lock;
194};
195
196/*
197 * MMaped I/O Resters
198 */
199enum jme_iomap_offsets {
200 JME_MAC = 0x0000,
201 JME_PHY = 0x0400,
202 JME_MISC = 0x0800,
203 JME_RSS = 0x0C00,
204};
205
206enum jme_iomap_regs {
207 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
208 JME_TXDBA = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
209 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
210 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
211 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
212 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
213 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
214
215 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
216 JME_RXDBA = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
217 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
218 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
219 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
220 JME_RXUMA = JME_MAC | 0x38, /* Receive Unicast MAC Address */
221 JME_RXMCHT = JME_MAC | 0x40, /* Receive Multicast Addr HashTable */
222 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
223 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
224
225 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
226 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
227 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
228
229
230 JME_PHY_CS = JME_PHY | 0x28, /* PHY Control and Status Register */
231 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
232 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
233
234
235 JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */
236 JME_IREQ = JME_MISC| 0x24, /* Interrupt Req Status (For Debug) */
237 JME_IENS = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
238 JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clearing Port */
239};
240
241/*
242 * TX Control/Status Bits
243 */
244enum jme_txcs_bits {
245 TXCS_QUEUE7S = 0x00008000,
246 TXCS_QUEUE6S = 0x00004000,
247 TXCS_QUEUE5S = 0x00002000,
248 TXCS_QUEUE4S = 0x00001000,
249 TXCS_QUEUE3S = 0x00000800,
250 TXCS_QUEUE2S = 0x00000400,
251 TXCS_QUEUE1S = 0x00000200,
252 TXCS_QUEUE0S = 0x00000100,
253 TXCS_FIFOTH = 0x000000C0,
254 TXCS_DMASIZE = 0x00000030,
255 TXCS_BURST = 0x00000004,
256 TXCS_ENABLE = 0x00000001,
257};
258enum jme_txcs_value {
259 TXCS_FIFOTH_16QW = 0x000000C0,
260 TXCS_FIFOTH_12QW = 0x00000080,
261 TXCS_FIFOTH_8QW = 0x00000040,
262 TXCS_FIFOTH_4QW = 0x00000000,
263
264 TXCS_DMASIZE_64B = 0x00000000,
265 TXCS_DMASIZE_128B = 0x00000010,
266 TXCS_DMASIZE_256B = 0x00000020,
267 TXCS_DMASIZE_512B = 0x00000030,
268
269 TXCS_SELECT_QUEUE0 = 0x00000000,
270 TXCS_SELECT_QUEUE1 = 0x00010000,
271 TXCS_SELECT_QUEUE2 = 0x00020000,
272 TXCS_SELECT_QUEUE3 = 0x00030000,
273 TXCS_SELECT_QUEUE4 = 0x00040000,
274 TXCS_SELECT_QUEUE5 = 0x00050000,
275 TXCS_SELECT_QUEUE6 = 0x00060000,
276 TXCS_SELECT_QUEUE7 = 0x00070000,
277
278 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
279 TXCS_DMASIZE_512B |
280 TXCS_BURST,
281};
282#define JME_TX_DISABLE_TIMEOUT 200 /* 200 usec */
283
284/*
285 * TX MAC Control/Status Bits
286 */
287enum jme_txmcs_bit_masks {
288 TXMCS_IFG2 = 0xC0000000,
289 TXMCS_IFG1 = 0x30000000,
290 TXMCS_TTHOLD = 0x00000300,
291 TXMCS_FBURST = 0x00000080,
292 TXMCS_CARRIEREXT = 0x00000040,
293 TXMCS_DEFER = 0x00000020,
294 TXMCS_BACKOFF = 0x00000010,
295 TXMCS_CARRIERSENSE = 0x00000008,
296 TXMCS_COLLISION = 0x00000004,
297 TXMCS_CRC = 0x00000002,
298 TXMCS_PADDING = 0x00000001,
299};
300enum jme_txmcs_values {
301 TXMCS_IFG2_6_4 = 0x00000000,
302 TXMCS_IFG2_8_5 = 0x40000000,
303 TXMCS_IFG2_10_6 = 0x80000000,
304 TXMCS_IFG2_12_7 = 0xC0000000,
305
306 TXMCS_IFG1_8_4 = 0x00000000,
307 TXMCS_IFG1_12_6 = 0x10000000,
308 TXMCS_IFG1_16_8 = 0x20000000,
309 TXMCS_IFG1_20_10 = 0x30000000,
310
311 TXMCS_TTHOLD_1_8 = 0x00000000,
312 TXMCS_TTHOLD_1_4 = 0x00000100,
313 TXMCS_TTHOLD_1_2 = 0x00000200,
314 TXMCS_TTHOLD_FULL = 0x00000300,
315
316 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
317 TXMCS_IFG1_16_8 |
318 TXMCS_TTHOLD_FULL |
319 TXMCS_DEFER |
320 TXMCS_CRC |
321 TXMCS_PADDING,
322};
323
324
325/*
326 * RX Control/Status Bits
327 */
328enum jme_rxcs_bits {
329 RXCS_QST = 0x00000004,
330 RXCS_ENABLE = 0x00000001,
331};
332#define JME_RX_DISABLE_TIMEOUT 200 /* 200 usec */
333
334/*
335 * RX MAC Control/Status Bits
336 */
337enum jme_rxmcs_bits {
338 RXMCS_ALLFRAME = 0x00000800,
339 RXMCS_BRDFRAME = 0x00000400,
340 RXMCS_MULFRAME = 0x00000200,
341 RXMCS_UNIFRAME = 0x00000100,
342 RXMCS_ALLMULFRAME = 0x00000080,
343 RXMCS_MULFILTERED = 0x00000040,
344};
345
346/*
347 * SMI Related definitions
348 */
349enum jme_smi_bit_mask
350{
351 SMI_DATA_MASK = 0xFFFF0000,
352 SMI_REG_ADDR_MASK = 0x0000F800,
353 SMI_PHY_ADDR_MASK = 0x000007C0,
354 SMI_OP_WRITE = 0x00000020,
355 SMI_OP_REQ = 0x00000010, /* Set to 1, after req done it'll be cleared to 0 */
356 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
357 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
358 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
359 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
360};
361enum jme_smi_bit_shift
362{
363 SMI_DATA_SHIFT = 16,
364 SMI_REG_ADDR_SHIFT = 11,
365 SMI_PHY_ADDR_SHIFT = 6,
366};
367__always_inline __u32 smi_reg_addr(int x)
368{
369 return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
370}
371__always_inline __u32 smi_phy_addr(int x)
372{
373 return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
374}
375#define JME_PHY_TIMEOUT 1000 /* 1000 usec */
376
377/*
378 * Global Host Control
379 */
380enum jme_ghc_bit_mask {
381 GHC_SWRST = 0x40000000,
382 GHC_DPX = 0x00000040,
383 GHC_SPEED = 0x00000030,
384 GHC_LINK_POLL = 0x00000001,
385};
386enum jme_ghc_speed_val {
387 GHC_SPEED_10M = 0x00000010,
388 GHC_SPEED_100M = 0x00000020,
389 GHC_SPEED_1000M = 0x00000030,
390};
391
392/*
393 * Giga PHY Status Registers
394 */
395enum jme_phy_link_bit_mask {
396 PHY_LINK_SPEED_MASK = 0x0000C000,
397 PHY_LINK_DUPLEX = 0x00002000,
398 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
399 PHY_LINK_UP = 0x00000400,
400 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
401};
402enum jme_phy_link_speed_val {
403 PHY_LINK_SPEED_10M = 0x00000000,
404 PHY_LINK_SPEED_100M = 0x00004000,
405 PHY_LINK_SPEED_1000M = 0x00008000,
406};
407#define JME_AUTONEG_TIMEOUT 500 /* 500 ms */
408
409/*
410 * SMB Control and Status
411 */
412enum jme_smbcsr_bit_mask
413{
414 SMBCSR_CNACK = 0x00020000,
415 SMBCSR_RELOAD = 0x00010000,
416 SMBCSR_EEPROMD = 0x00000020,
417};
418#define JME_SMB_TIMEOUT 10 /* 10 msec */
419
420
421/*
422 * Interrupt Status Bits
423 */
424enum jme_interrupt_bits
425{
426 INTR_SWINTR = 0x80000000,
427 INTR_TMINTR = 0x40000000,
428 INTR_LINKCH = 0x20000000,
429 INTR_PAUSERCV = 0x10000000,
430 INTR_MAGICRCV = 0x08000000,
431 INTR_WAKERCV = 0x04000000,
432 INTR_PCCRX0TO = 0x02000000,
433 INTR_PCCRX1TO = 0x01000000,
434 INTR_PCCRX2TO = 0x00800000,
435 INTR_PCCRX3TO = 0x00400000,
436 INTR_PCCTXTO = 0x00200000,
437 INTR_PCCRX0 = 0x00100000,
438 INTR_PCCRX1 = 0x00080000,
439 INTR_PCCRX2 = 0x00040000,
440 INTR_PCCRX3 = 0x00020000,
441 INTR_PCCTX = 0x00010000,
442 INTR_RX3EMP = 0x00008000,
443 INTR_RX2EMP = 0x00004000,
444 INTR_RX1EMP = 0x00002000,
445 INTR_RX0EMP = 0x00001000,
446 INTR_RX3 = 0x00000800,
447 INTR_RX2 = 0x00000400,
448 INTR_RX1 = 0x00000200,
449 INTR_RX0 = 0x00000100,
450 INTR_TX7 = 0x00000080,
451 INTR_TX6 = 0x00000040,
452 INTR_TX5 = 0x00000020,
453 INTR_TX4 = 0x00000010,
454 INTR_TX3 = 0x00000008,
455 INTR_TX2 = 0x00000004,
456 INTR_TX1 = 0x00000002,
457 INTR_TX0 = 0x00000001,
458};
459static const __u32 INTR_ENABLE = INTR_LINKCH |
460 INTR_RX0EMP |
461 INTR_RX0 |
462 INTR_TX0;
463
464/*
465 * Read/Write MMaped I/O Registers
466 */
467__always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
468{
469 return le32_to_cpu(readl(jme->regs + reg));
470}
471__always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
472{
473 writel(cpu_to_le32(val), jme->regs + reg);
474}
475__always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
476{
477 /*
478 * Read after write should cause flush
479 */
480 writel(cpu_to_le32(val), jme->regs + reg);
481 readl(jme->regs + reg);
482}
483
484/*
485 * Function prototypes for ethtool
486 */
487static void jme_get_drvinfo(struct net_device *netdev,
488 struct ethtool_drvinfo *info);
489static int jme_get_settings(struct net_device *netdev,
490 struct ethtool_cmd *ecmd);
491static int jme_set_settings(struct net_device *netdev,
492 struct ethtool_cmd *ecmd);
493static u32 jme_get_link(struct net_device *netdev);
494
495
496/*
497 * Function prototypes for netdev
498 */
499static int jme_open(struct net_device *netdev);
500static int jme_close(struct net_device *netdev);
501static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
502static int jme_set_macaddr(struct net_device *netdev, void *p);
503static void jme_set_multi(struct net_device *netdev);
504