Fix version.h include order
[jme.git] / jme.h
CommitLineData
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
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7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
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9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
cd0ff491 24#ifndef __JME_H_INCLUDED__
3b70a6fa 25#define __JME_H_INCLUDED__
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26
27#define DRV_NAME "jme"
1e5ebebc 28#define DRV_VERSION "1.0.6.1-jmmod"
cd0ff491 29#define PFX DRV_NAME ": "
d7699f87 30
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31#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
32#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
8d27293f 33
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34/*
35 * Message related definitions
36 */
37#define JME_DEF_MSG_ENABLE \
38 (NETIF_MSG_PROBE | \
39 NETIF_MSG_LINK | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR | \
42 NETIF_MSG_HW)
43
44#define jeprintk(pdev, fmt, args...) \
45 printk(KERN_ERR PFX fmt, ## args)
d7699f87 46
3bf61c55 47#ifdef TX_DEBUG
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48#define tx_dbg(priv, fmt, args...) \
49 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
3bf61c55 50#else
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51#define tx_dbg(priv, fmt, args...) \
52do { \
53 if (0) \
54 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
55} while (0)
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56#endif
57
7ca9ebee 58#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
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59#define jme_msg(msglvl, type, priv, fmt, args...) \
60 if (netif_msg_##type(priv)) \
61 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
3bf61c55 62
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63#define msg_probe(priv, fmt, args...) \
64 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
29bdd921 65
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66#define msg_link(priv, fmt, args...) \
67 jme_msg(KERN_INFO, link, priv, fmt, ## args)
79ce639c 68
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69#define msg_intr(priv, fmt, args...) \
70 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
71
72#define msg_rx_err(priv, fmt, args...) \
73 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
b3821cc5 74
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75#define msg_rx_status(priv, fmt, args...) \
76 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
4330c2f2 77
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78#define msg_tx_err(priv, fmt, args...) \
79 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
4330c2f2 80
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81#define msg_tx_done(priv, fmt, args...) \
82 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
d7699f87 83
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84#define msg_tx_queued(priv, fmt, args...) \
85 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
86
87#define msg_hw(priv, fmt, args...) \
88 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
7ca9ebee 89#endif
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90
91/*
92 * Extra PCI Configuration space interface
93 */
94#define PCI_DCSR_MRRS 0x59
95#define PCI_DCSR_MRRS_MASK 0x70
96
97enum pci_dcsr_mrrs_vals {
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98 MRRS_128B = 0x00,
99 MRRS_256B = 0x10,
100 MRRS_512B = 0x20,
101 MRRS_1024B = 0x30,
102 MRRS_2048B = 0x40,
103 MRRS_4096B = 0x50,
104};
d7699f87 105
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106#define PCI_SPI 0xB0
107
108enum pci_spi_bits {
109 SPI_EN = 0x10,
110 SPI_MISO = 0x08,
111 SPI_MOSI = 0x04,
112 SPI_SCLK = 0x02,
113 SPI_CS = 0x01,
114};
115
116struct jme_spi_op {
117 void __user *uwbuf;
118 void __user *urbuf;
119 __u8 wn; /* Number of write actions */
120 __u8 rn; /* Number of read actions */
121 __u8 bitn; /* Number of bits per action */
122 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
123 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
124
125 /* Internal use only */
126 u8 *kwbuf;
127 u8 *krbuf;
128 u8 sr;
129 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
130};
79ce639c 131
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132enum jme_spi_op_bits {
133 SPI_MODE_CPHA = 0x01,
134 SPI_MODE_CPOL = 0x02,
135 SPI_MODE_DUP = 0x80,
136};
137
138#define HALF_US 500 /* 500 ns */
139#define JMESPIIOCTL SIOCDEVPRIVATE
140
141/*
142 * Dynamic(adaptive)/Static PCC values
143 */
3bf61c55 144enum dynamic_pcc_values {
192570e0 145 PCC_OFF = 0,
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146 PCC_P1 = 1,
147 PCC_P2 = 2,
148 PCC_P3 = 3,
149
192570e0 150 PCC_OFF_TO = 0,
3bf61c55 151 PCC_P1_TO = 1,
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152 PCC_P2_TO = 64,
153 PCC_P3_TO = 128,
3bf61c55 154
192570e0 155 PCC_OFF_CNT = 0,
3bf61c55 156 PCC_P1_CNT = 1,
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157 PCC_P2_CNT = 16,
158 PCC_P3_CNT = 32,
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159};
160struct dynpcc_info {
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161 unsigned long last_bytes;
162 unsigned long last_pkts;
79ce639c 163 unsigned long intr_cnt;
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164 unsigned char cur;
165 unsigned char attempt;
166 unsigned char cnt;
167};
79ce639c 168#define PCC_INTERVAL_US 100000
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169#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
170#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
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171#define PCC_P2_THRESHOLD 800
172#define PCC_INTR_THRESHOLD 800
47220951 173#define PCC_TX_TO 1000
b3821cc5 174#define PCC_TX_CNT 8
3bf61c55 175
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176/*
177 * TX/RX Descriptors
4330c2f2 178 *
cd0ff491 179 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
d7699f87 180 */
4330c2f2 181#define RING_DESC_ALIGN 16 /* Descriptor alignment */
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182#define TX_DESC_SIZE 16
183#define TX_RING_NR 8
cd0ff491 184#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 185
3bf61c55 186struct txdesc {
d7699f87 187 union {
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188 __u8 all[16];
189 __le32 dw[4];
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190 struct {
191 /* DW0 */
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192 __le16 vlan;
193 __u8 rsv1;
194 __u8 flags;
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195
196 /* DW1 */
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197 __le16 datalen;
198 __le16 mss;
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199
200 /* DW2 */
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201 __le16 pktsize;
202 __le16 rsv2;
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203
204 /* DW3 */
cd0ff491 205 __le32 bufaddr;
d7699f87 206 } desc1;
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207 struct {
208 /* DW0 */
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209 __le16 rsv1;
210 __u8 rsv2;
211 __u8 flags;
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212
213 /* DW1 */
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214 __le16 datalen;
215 __le16 rsv3;
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216
217 /* DW2 */
cd0ff491 218 __le32 bufaddrh;
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219
220 /* DW3 */
cd0ff491 221 __le32 bufaddrl;
3bf61c55 222 } desc2;
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223 struct {
224 /* DW0 */
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225 __u8 ehdrsz;
226 __u8 rsv1;
227 __u8 rsv2;
228 __u8 flags;
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229
230 /* DW1 */
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231 __le16 trycnt;
232 __le16 segcnt;
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233
234 /* DW2 */
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235 __le16 pktsz;
236 __le16 rsv3;
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237
238 /* DW3 */
cd0ff491 239 __le32 bufaddrl;
8c198884 240 } descwb;
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241 };
242};
cd0ff491 243
8c198884 244enum jme_txdesc_flags_bits {
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245 TXFLAG_OWN = 0x80,
246 TXFLAG_INT = 0x40,
3bf61c55 247 TXFLAG_64BIT = 0x20,
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248 TXFLAG_TCPCS = 0x10,
249 TXFLAG_UDPCS = 0x08,
250 TXFLAG_IPCS = 0x04,
251 TXFLAG_LSEN = 0x02,
252 TXFLAG_TAGON = 0x01,
253};
cd0ff491 254
b3821cc5 255#define TXDESC_MSS_SHIFT 2
0ede469c 256enum jme_txwbdesc_flags_bits {
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257 TXWBFLAG_OWN = 0x80,
258 TXWBFLAG_INT = 0x40,
259 TXWBFLAG_TMOUT = 0x20,
260 TXWBFLAG_TRYOUT = 0x10,
261 TXWBFLAG_COL = 0x08,
262
263 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
264 TXWBFLAG_TRYOUT |
265 TXWBFLAG_COL,
266};
d7699f87 267
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268#define RX_DESC_SIZE 16
269#define RX_RING_NR 4
cd0ff491 270#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 271#define RX_BUF_DMA_ALIGN 8
3bf61c55 272#define RX_PREPAD_SIZE 10
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273#define ETH_CRC_LEN 2
274#define RX_VLANHDR_LEN 2
275#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
276 ETH_HLEN + \
277 ETH_CRC_LEN + \
278 RX_VLANHDR_LEN + \
279 RX_BUF_DMA_ALIGN)
d7699f87 280
3bf61c55 281struct rxdesc {
d7699f87 282 union {
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283 __u8 all[16];
284 __le32 dw[4];
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285 struct {
286 /* DW0 */
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287 __le16 rsv2;
288 __u8 rsv1;
289 __u8 flags;
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290
291 /* DW1 */
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292 __le16 datalen;
293 __le16 wbcpl;
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294
295 /* DW2 */
cd0ff491 296 __le32 bufaddrh;
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297
298 /* DW3 */
cd0ff491 299 __le32 bufaddrl;
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300 } desc1;
301 struct {
302 /* DW0 */
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303 __le16 vlan;
304 __le16 flags;
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305
306 /* DW1 */
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307 __le16 framesize;
308 __u8 errstat;
309 __u8 desccnt;
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310
311 /* DW2 */
cd0ff491 312 __le32 rsshash;
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313
314 /* DW3 */
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315 __u8 hashfun;
316 __u8 hashtype;
317 __le16 resrv;
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318 } descwb;
319 };
320};
cd0ff491 321
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322enum jme_rxdesc_flags_bits {
323 RXFLAG_OWN = 0x80,
324 RXFLAG_INT = 0x40,
325 RXFLAG_64BIT = 0x20,
326};
cd0ff491 327
d7699f87 328enum jme_rxwbdesc_flags_bits {
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329 RXWBFLAG_OWN = 0x8000,
330 RXWBFLAG_INT = 0x4000,
331 RXWBFLAG_MF = 0x2000,
332 RXWBFLAG_64BIT = 0x2000,
333 RXWBFLAG_TCPON = 0x1000,
334 RXWBFLAG_UDPON = 0x0800,
335 RXWBFLAG_IPCS = 0x0400,
336 RXWBFLAG_TCPCS = 0x0200,
337 RXWBFLAG_UDPCS = 0x0100,
338 RXWBFLAG_TAGON = 0x0080,
339 RXWBFLAG_IPV4 = 0x0040,
340 RXWBFLAG_IPV6 = 0x0020,
341 RXWBFLAG_PAUSE = 0x0010,
342 RXWBFLAG_MAGIC = 0x0008,
343 RXWBFLAG_WAKEUP = 0x0004,
344 RXWBFLAG_DEST = 0x0003,
345 RXWBFLAG_DEST_UNI = 0x0001,
346 RXWBFLAG_DEST_MUL = 0x0002,
347 RXWBFLAG_DEST_BRO = 0x0003,
d7699f87 348};
cd0ff491 349
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350enum jme_rxwbdesc_desccnt_mask {
351 RXWBDCNT_WBCPL = 0x80,
352 RXWBDCNT_DCNT = 0x7F,
353};
cd0ff491 354
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355enum jme_rxwbdesc_errstat_bits {
356 RXWBERR_LIMIT = 0x80,
357 RXWBERR_MIIER = 0x40,
358 RXWBERR_NIBON = 0x20,
359 RXWBERR_COLON = 0x10,
360 RXWBERR_ABORT = 0x08,
361 RXWBERR_SHORT = 0x04,
362 RXWBERR_OVERUN = 0x02,
363 RXWBERR_CRCERR = 0x01,
364 RXWBERR_ALLERR = 0xFF,
365};
366
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367/*
368 * Buffer information corresponding to ring descriptors.
369 */
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370struct jme_buffer_info {
371 struct sk_buff *skb;
372 dma_addr_t mapping;
373 int len;
3bf61c55 374 int nr_desc;
cdcdc9eb 375 unsigned long start_xmit;
4330c2f2 376};
d7699f87 377
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378/*
379 * The structure holding buffer information and ring descriptors all together.
380 */
d7699f87 381struct jme_ring {
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382 void *alloc; /* pointer to allocated memory */
383 void *desc; /* pointer to ring memory */
384 dma_addr_t dmaalloc; /* phys address of ring alloc */
385 dma_addr_t dma; /* phys address for ring dma */
d7699f87 386
4330c2f2 387 /* Buffer information corresponding to each descriptor */
0ede469c 388 struct jme_buffer_info *bufinf;
d7699f87 389
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390 int next_to_use;
391 atomic_t next_to_clean;
79ce639c 392 atomic_t nr_free;
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393};
394
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395#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
396#define false 0
397#define true 0
398#define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
399#define PCI_VENDOR_ID_JMICRON 0x197B
400#endif
401
402#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
403#define PCI_VDEVICE(vendor, device) \
404 PCI_VENDOR_ID_##vendor, (device), \
405 PCI_ANY_ID, PCI_ANY_ID, 0, 0
406#endif
407
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408#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
409#define NET_STAT(priv) priv->stats
410#define NETDEV_GET_STATS(netdev, fun_ptr) \
411 netdev->get_stats = fun_ptr
412#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
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413/*
414 * CentOS 5.5 have *_hdr helpers back-ported
415 */
416#ifdef RHEL_RELEASE_CODE
417#if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,5)
418#define __DEFINE_IPHDR_HELPERS__
419#endif
420#else
421#define __DEFINE_IPHDR_HELPERS__
422#endif
423#else
424#define NET_STAT(priv) (priv->dev->stats)
425#define NETDEV_GET_STATS(netdev, fun_ptr)
426#define DECLARE_NET_DEVICE_STATS
427#endif
428
429#ifdef __DEFINE_IPHDR_HELPERS__
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430static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
431{
432 return skb->nh.iph;
433}
434
435static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
436{
437 return skb->nh.ipv6h;
438}
439
440static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
441{
442 return skb->h.th;
443}
85776f33 444#endif
3bf61c55 445
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446#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
447#define DECLARE_NAPI_STRUCT
448#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
449 dev->poll = pollfn; \
450 dev->weight = q;
451#define JME_NAPI_HOLDER(holder) struct net_device *holder
452#define JME_NAPI_WEIGHT(w) int *w
453#define JME_NAPI_WEIGHT_VAL(w) *w
454#define JME_NAPI_WEIGHT_SET(w, r) *w = r
3b70a6fa 455#define DECLARE_NETDEV struct net_device *netdev = jme->dev;
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456#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
457#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
458#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
459#define JME_RX_SCHEDULE_PREP(priv) \
460 netif_rx_schedule_prep(priv->dev)
461#define JME_RX_SCHEDULE(priv) \
462 __netif_rx_schedule(priv->dev);
0ede469c 463#else
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464#define DECLARE_NAPI_STRUCT struct napi_struct napi;
465#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
466 netif_napi_add(dev, napis, pollfn, q);
467#define JME_NAPI_HOLDER(holder) struct napi_struct *holder
468#define JME_NAPI_WEIGHT(w) int w
469#define JME_NAPI_WEIGHT_VAL(w) w
470#define JME_NAPI_WEIGHT_SET(w, r)
471#define DECLARE_NETDEV
472#define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
473#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
474#define JME_NAPI_DISABLE(priv) \
475 if (!napi_disable_pending(&priv->napi)) \
476 napi_disable(&priv->napi);
477#define JME_RX_SCHEDULE_PREP(priv) \
478 napi_schedule_prep(&priv->napi)
479#define JME_RX_SCHEDULE(priv) \
480 __napi_schedule(&priv->napi);
85776f33 481#endif
cdcdc9eb 482
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483/*
484 * Jmac Adapter Private data
485 */
486struct jme_adapter {
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487 struct pci_dev *pdev;
488 struct net_device *dev;
489 void __iomem *regs;
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490 struct mii_if_info mii_if;
491 struct jme_ring rxring[RX_RING_NR];
492 struct jme_ring txring[TX_RING_NR];
d7699f87 493 spinlock_t phy_lock;
fcf45b4c 494 spinlock_t macaddr_lock;
8c198884 495 spinlock_t rxmcs_lock;
fcf45b4c 496 struct tasklet_struct rxempty_task;
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497 struct tasklet_struct rxclean_task;
498 struct tasklet_struct txclean_task;
499 struct tasklet_struct linkch_task;
79ce639c 500 struct tasklet_struct pcc_task;
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501 unsigned long flags;
502 u32 reg_txcs;
503 u32 reg_txpfc;
504 u32 reg_rxcs;
505 u32 reg_rxmcs;
506 u32 reg_ghc;
507 u32 reg_pmcs;
508 u32 phylink;
509 u32 tx_ring_size;
510 u32 tx_ring_mask;
511 u32 tx_wake_threshold;
512 u32 rx_ring_size;
513 u32 rx_ring_mask;
514 u8 mrrs;
515 unsigned int fpgaver;
58c92f28 516 unsigned int chiprev;
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517 u8 rev;
518 u32 msg_enable;
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519 struct ethtool_cmd old_ecmd;
520 unsigned int old_mtu;
cd0ff491 521 struct vlan_group *vlgrp;
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522 struct dynpcc_info dpi;
523 atomic_t intr_sem;
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524 atomic_t link_changing;
525 atomic_t tx_cleaning;
526 atomic_t rx_cleaning;
192570e0 527 atomic_t rx_empty;
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528 int (*jme_rx)(struct sk_buff *skb);
529 int (*jme_vlan_rx)(struct sk_buff *skb,
530 struct vlan_group *grp,
531 unsigned short vlan_tag);
532 DECLARE_NAPI_STRUCT
3bf61c55 533 DECLARE_NET_DEVICE_STATS
d7699f87 534};
cd0ff491 535
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536#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
537static struct net_device_stats *
538jme_get_stats(struct net_device *netdev)
539{
540 struct jme_adapter *jme = netdev_priv(netdev);
541 return &jme->stats;
542}
543#endif
544
79ce639c 545enum jme_flags_bits {
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546 JME_FLAG_MSI = 1,
547 JME_FLAG_SSET = 2,
548 JME_FLAG_TXCSUM = 3,
549 JME_FLAG_TSO = 4,
550 JME_FLAG_POLL = 5,
551 JME_FLAG_SHUTDOWN = 6,
8c198884 552};
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553
554#define TX_TIMEOUT (5 * HZ)
186fc259 555#define JME_REG_LEN 0x500
cd0ff491 556#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
8c198884 557
85776f33 558#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
7ee473a3 559static inline struct jme_adapter*
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560jme_napi_priv(struct net_device *holder)
561{
7ee473a3 562 struct jme_adapter *jme;
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563 jme = netdev_priv(holder);
564 return jme;
565}
566#else
7ee473a3 567static inline struct jme_adapter*
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568jme_napi_priv(struct napi_struct *napi)
569{
7ee473a3 570 struct jme_adapter *jme;
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571 jme = container_of(napi, struct jme_adapter, napi);
572 return jme;
573}
85776f33 574#endif
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575
576/*
577 * MMaped I/O Resters
578 */
579enum jme_iomap_offsets {
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580 JME_MAC = 0x0000,
581 JME_PHY = 0x0400,
d7699f87 582 JME_MISC = 0x0800,
4330c2f2 583 JME_RSS = 0x0C00,
d7699f87
GFT
584};
585
8c198884
GFT
586enum jme_iomap_lens {
587 JME_MAC_LEN = 0x80,
588 JME_PHY_LEN = 0x58,
589 JME_MISC_LEN = 0x98,
590 JME_RSS_LEN = 0xFF,
591};
592
d7699f87
GFT
593enum jme_iomap_regs {
594 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
3bf61c55
GFT
595 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
596 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
d7699f87
GFT
597 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
598 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
599 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
600 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
601 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
602
603 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
3bf61c55
GFT
604 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
605 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
d7699f87
GFT
606 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
607 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
608 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
4330c2f2
GFT
609 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
610 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
3bf61c55
GFT
611 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
612 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
d7699f87
GFT
613 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
614 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
615
616 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
617 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
618 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
619
620
3bf61c55 621 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
d7699f87
GFT
622 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
623 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
186fc259 624 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
d7699f87
GFT
625
626
cd0ff491
GFT
627 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
628 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
629 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
630 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
631 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
632 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
633 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
634 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
635 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
636 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
637 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
638 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
639 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
640 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
641 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
642 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
d7699f87
GFT
643};
644
645/*
646 * TX Control/Status Bits
647 */
648enum jme_txcs_bits {
649 TXCS_QUEUE7S = 0x00008000,
650 TXCS_QUEUE6S = 0x00004000,
651 TXCS_QUEUE5S = 0x00002000,
652 TXCS_QUEUE4S = 0x00001000,
653 TXCS_QUEUE3S = 0x00000800,
654 TXCS_QUEUE2S = 0x00000400,
655 TXCS_QUEUE1S = 0x00000200,
656 TXCS_QUEUE0S = 0x00000100,
657 TXCS_FIFOTH = 0x000000C0,
658 TXCS_DMASIZE = 0x00000030,
659 TXCS_BURST = 0x00000004,
660 TXCS_ENABLE = 0x00000001,
661};
cd0ff491 662
d7699f87
GFT
663enum jme_txcs_value {
664 TXCS_FIFOTH_16QW = 0x000000C0,
665 TXCS_FIFOTH_12QW = 0x00000080,
666 TXCS_FIFOTH_8QW = 0x00000040,
667 TXCS_FIFOTH_4QW = 0x00000000,
668
669 TXCS_DMASIZE_64B = 0x00000000,
670 TXCS_DMASIZE_128B = 0x00000010,
671 TXCS_DMASIZE_256B = 0x00000020,
672 TXCS_DMASIZE_512B = 0x00000030,
673
674 TXCS_SELECT_QUEUE0 = 0x00000000,
675 TXCS_SELECT_QUEUE1 = 0x00010000,
676 TXCS_SELECT_QUEUE2 = 0x00020000,
677 TXCS_SELECT_QUEUE3 = 0x00030000,
678 TXCS_SELECT_QUEUE4 = 0x00040000,
679 TXCS_SELECT_QUEUE5 = 0x00050000,
680 TXCS_SELECT_QUEUE6 = 0x00060000,
681 TXCS_SELECT_QUEUE7 = 0x00070000,
682
683 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
d7699f87
GFT
684 TXCS_BURST,
685};
cd0ff491 686
29bdd921 687#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
688
689/*
690 * TX MAC Control/Status Bits
691 */
692enum jme_txmcs_bit_masks {
693 TXMCS_IFG2 = 0xC0000000,
694 TXMCS_IFG1 = 0x30000000,
695 TXMCS_TTHOLD = 0x00000300,
696 TXMCS_FBURST = 0x00000080,
697 TXMCS_CARRIEREXT = 0x00000040,
698 TXMCS_DEFER = 0x00000020,
699 TXMCS_BACKOFF = 0x00000010,
700 TXMCS_CARRIERSENSE = 0x00000008,
701 TXMCS_COLLISION = 0x00000004,
702 TXMCS_CRC = 0x00000002,
703 TXMCS_PADDING = 0x00000001,
704};
cd0ff491 705
d7699f87
GFT
706enum jme_txmcs_values {
707 TXMCS_IFG2_6_4 = 0x00000000,
708 TXMCS_IFG2_8_5 = 0x40000000,
709 TXMCS_IFG2_10_6 = 0x80000000,
710 TXMCS_IFG2_12_7 = 0xC0000000,
711
712 TXMCS_IFG1_8_4 = 0x00000000,
713 TXMCS_IFG1_12_6 = 0x10000000,
714 TXMCS_IFG1_16_8 = 0x20000000,
715 TXMCS_IFG1_20_10 = 0x30000000,
716
717 TXMCS_TTHOLD_1_8 = 0x00000000,
718 TXMCS_TTHOLD_1_4 = 0x00000100,
719 TXMCS_TTHOLD_1_2 = 0x00000200,
720 TXMCS_TTHOLD_FULL = 0x00000300,
721
722 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
723 TXMCS_IFG1_16_8 |
724 TXMCS_TTHOLD_FULL |
725 TXMCS_DEFER |
726 TXMCS_CRC |
727 TXMCS_PADDING,
728};
729
8c198884
GFT
730enum jme_txpfc_bits_masks {
731 TXPFC_VLAN_TAG = 0xFFFF0000,
732 TXPFC_VLAN_EN = 0x00008000,
733 TXPFC_PF_EN = 0x00000001,
734};
735
736enum jme_txtrhd_bits_masks {
737 TXTRHD_TXPEN = 0x80000000,
738 TXTRHD_TXP = 0x7FFFFF00,
739 TXTRHD_TXREN = 0x00000080,
740 TXTRHD_TXRL = 0x0000007F,
741};
cd0ff491 742
8c198884
GFT
743enum jme_txtrhd_shifts {
744 TXTRHD_TXP_SHIFT = 8,
745 TXTRHD_TXRL_SHIFT = 0,
746};
747
d7699f87
GFT
748/*
749 * RX Control/Status Bits
750 */
4330c2f2 751enum jme_rxcs_bit_masks {
3bf61c55
GFT
752 /* FIFO full threshold for transmitting Tx Pause Packet */
753 RXCS_FIFOTHTP = 0x30000000,
754 /* FIFO threshold for processing next packet */
755 RXCS_FIFOTHNP = 0x0C000000,
4330c2f2
GFT
756 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
757 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
758 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
759 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
760 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
761 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
762 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
763 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
764 RXCS_QST = 0x00000004, /* Receive queue start */
765 RXCS_SUSPEND = 0x00000002,
d7699f87
GFT
766 RXCS_ENABLE = 0x00000001,
767};
cd0ff491 768
4330c2f2
GFT
769enum jme_rxcs_values {
770 RXCS_FIFOTHTP_16T = 0x00000000,
771 RXCS_FIFOTHTP_32T = 0x10000000,
772 RXCS_FIFOTHTP_64T = 0x20000000,
773 RXCS_FIFOTHTP_128T = 0x30000000,
774
775 RXCS_FIFOTHNP_16QW = 0x00000000,
776 RXCS_FIFOTHNP_32QW = 0x04000000,
777 RXCS_FIFOTHNP_64QW = 0x08000000,
778 RXCS_FIFOTHNP_128QW = 0x0C000000,
779
780 RXCS_DMAREQSZ_16B = 0x00000000,
781 RXCS_DMAREQSZ_32B = 0x01000000,
782 RXCS_DMAREQSZ_64B = 0x02000000,
783 RXCS_DMAREQSZ_128B = 0x03000000,
784
785 RXCS_QUEUESEL_Q0 = 0x00000000,
786 RXCS_QUEUESEL_Q1 = 0x00010000,
787 RXCS_QUEUESEL_Q2 = 0x00020000,
788 RXCS_QUEUESEL_Q3 = 0x00030000,
789
790 RXCS_RETRYGAP_256ns = 0x00000000,
791 RXCS_RETRYGAP_512ns = 0x00001000,
792 RXCS_RETRYGAP_1024ns = 0x00002000,
793 RXCS_RETRYGAP_2048ns = 0x00003000,
794 RXCS_RETRYGAP_4096ns = 0x00004000,
795 RXCS_RETRYGAP_8192ns = 0x00005000,
796 RXCS_RETRYGAP_16384ns = 0x00006000,
797 RXCS_RETRYGAP_32768ns = 0x00007000,
798
799 RXCS_RETRYCNT_0 = 0x00000000,
800 RXCS_RETRYCNT_4 = 0x00000100,
801 RXCS_RETRYCNT_8 = 0x00000200,
802 RXCS_RETRYCNT_12 = 0x00000300,
803 RXCS_RETRYCNT_16 = 0x00000400,
804 RXCS_RETRYCNT_20 = 0x00000500,
805 RXCS_RETRYCNT_24 = 0x00000600,
806 RXCS_RETRYCNT_28 = 0x00000700,
807 RXCS_RETRYCNT_32 = 0x00000800,
808 RXCS_RETRYCNT_36 = 0x00000900,
809 RXCS_RETRYCNT_40 = 0x00000A00,
810 RXCS_RETRYCNT_44 = 0x00000B00,
811 RXCS_RETRYCNT_48 = 0x00000C00,
812 RXCS_RETRYCNT_52 = 0x00000D00,
813 RXCS_RETRYCNT_56 = 0x00000E00,
814 RXCS_RETRYCNT_60 = 0x00000F00,
815
816 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
79ce639c 817 RXCS_FIFOTHNP_128QW |
4330c2f2
GFT
818 RXCS_DMAREQSZ_128B |
819 RXCS_RETRYGAP_256ns |
820 RXCS_RETRYCNT_32,
821};
cd0ff491 822
29bdd921 823#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
824
825/*
826 * RX MAC Control/Status Bits
827 */
828enum jme_rxmcs_bits {
829 RXMCS_ALLFRAME = 0x00000800,
830 RXMCS_BRDFRAME = 0x00000400,
831 RXMCS_MULFRAME = 0x00000200,
832 RXMCS_UNIFRAME = 0x00000100,
833 RXMCS_ALLMULFRAME = 0x00000080,
834 RXMCS_MULFILTERED = 0x00000040,
3bf61c55
GFT
835 RXMCS_RXCOLLDEC = 0x00000020,
836 RXMCS_FLOWCTRL = 0x00000008,
837 RXMCS_VTAGRM = 0x00000004,
838 RXMCS_PREPAD = 0x00000002,
839 RXMCS_CHECKSUM = 0x00000001,
b3821cc5 840
8c198884
GFT
841 RXMCS_DEFAULT = RXMCS_VTAGRM |
842 RXMCS_PREPAD |
843 RXMCS_FLOWCTRL |
844 RXMCS_CHECKSUM,
d7699f87
GFT
845};
846
847/*
b3821cc5
GFT
848 * Wakeup Frame setup interface registers
849 */
850#define WAKEUP_FRAME_NR 8
851#define WAKEUP_FRAME_MASK_DWNR 4
cd0ff491 852
b3821cc5
GFT
853enum jme_wfoi_bit_masks {
854 WFOI_MASK_SEL = 0x00000070,
855 WFOI_CRC_SEL = 0x00000008,
856 WFOI_FRAME_SEL = 0x00000007,
857};
cd0ff491 858
b3821cc5
GFT
859enum jme_wfoi_shifts {
860 WFOI_MASK_SHIFT = 4,
861};
862
863/*
d7699f87
GFT
864 * SMI Related definitions
865 */
cd0ff491 866enum jme_smi_bit_mask {
d7699f87
GFT
867 SMI_DATA_MASK = 0xFFFF0000,
868 SMI_REG_ADDR_MASK = 0x0000F800,
869 SMI_PHY_ADDR_MASK = 0x000007C0,
870 SMI_OP_WRITE = 0x00000020,
3bf61c55
GFT
871 /* Set to 1, after req done it'll be cleared to 0 */
872 SMI_OP_REQ = 0x00000010,
d7699f87
GFT
873 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
874 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
875 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
876 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
877};
cd0ff491
GFT
878
879enum jme_smi_bit_shift {
d7699f87
GFT
880 SMI_DATA_SHIFT = 16,
881 SMI_REG_ADDR_SHIFT = 11,
882 SMI_PHY_ADDR_SHIFT = 6,
883};
cd0ff491
GFT
884
885static inline u32 smi_reg_addr(int x)
d7699f87 886{
cd0ff491 887 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
d7699f87 888}
cd0ff491
GFT
889
890static inline u32 smi_phy_addr(int x)
d7699f87 891{
cd0ff491 892 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
d7699f87 893}
cd0ff491 894
8d27293f 895#define JME_PHY_TIMEOUT 100 /* 100 msec */
186fc259 896#define JME_PHY_REG_NR 32
d7699f87
GFT
897
898/*
899 * Global Host Control
900 */
901enum jme_ghc_bit_mask {
3b70a6fa
GFT
902 GHC_SWRST = 0x40000000,
903 GHC_DPX = 0x00000040,
904 GHC_SPEED = 0x00000030,
905 GHC_LINK_POLL = 0x00000001,
d7699f87 906};
cd0ff491 907
d7699f87 908enum jme_ghc_speed_val {
3b70a6fa
GFT
909 GHC_SPEED_10M = 0x00000010,
910 GHC_SPEED_100M = 0x00000020,
911 GHC_SPEED_1000M = 0x00000030,
912};
913
914enum jme_ghc_to_clk {
915 GHC_TO_CLK_OFF = 0x00000000,
916 GHC_TO_CLK_GPHY = 0x00400000,
917 GHC_TO_CLK_PCIE = 0x00800000,
918 GHC_TO_CLK_INVALID = 0x00C00000,
919};
920
921enum jme_ghc_txmac_clk {
922 GHC_TXMAC_CLK_OFF = 0x00000000,
923 GHC_TXMAC_CLK_GPHY = 0x00100000,
924 GHC_TXMAC_CLK_PCIE = 0x00200000,
925 GHC_TXMAC_CLK_INVALID = 0x00300000,
d7699f87
GFT
926};
927
928/*
29bdd921
GFT
929 * Power management control and status register
930 */
931enum jme_pmcs_bit_masks {
932 PMCS_WF7DET = 0x80000000,
933 PMCS_WF6DET = 0x40000000,
934 PMCS_WF5DET = 0x20000000,
935 PMCS_WF4DET = 0x10000000,
936 PMCS_WF3DET = 0x08000000,
937 PMCS_WF2DET = 0x04000000,
938 PMCS_WF1DET = 0x02000000,
939 PMCS_WF0DET = 0x01000000,
940 PMCS_LFDET = 0x00040000,
941 PMCS_LRDET = 0x00020000,
942 PMCS_MFDET = 0x00010000,
943 PMCS_WF7EN = 0x00008000,
944 PMCS_WF6EN = 0x00004000,
945 PMCS_WF5EN = 0x00002000,
946 PMCS_WF4EN = 0x00001000,
947 PMCS_WF3EN = 0x00000800,
948 PMCS_WF2EN = 0x00000400,
949 PMCS_WF1EN = 0x00000200,
950 PMCS_WF0EN = 0x00000100,
951 PMCS_LFEN = 0x00000004,
952 PMCS_LREN = 0x00000002,
953 PMCS_MFEN = 0x00000001,
954};
955
956/*
3bf61c55 957 * Giga PHY Status Registers
d7699f87
GFT
958 */
959enum jme_phy_link_bit_mask {
960 PHY_LINK_SPEED_MASK = 0x0000C000,
961 PHY_LINK_DUPLEX = 0x00002000,
962 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
963 PHY_LINK_UP = 0x00000400,
964 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
fcf45b4c 965 PHY_LINK_MDI_STAT = 0x00000040,
d7699f87 966};
cd0ff491 967
d7699f87
GFT
968enum jme_phy_link_speed_val {
969 PHY_LINK_SPEED_10M = 0x00000000,
970 PHY_LINK_SPEED_100M = 0x00004000,
971 PHY_LINK_SPEED_1000M = 0x00008000,
972};
cd0ff491 973
fcf45b4c 974#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
d7699f87
GFT
975
976/*
977 * SMB Control and Status
978 */
79ce639c 979enum jme_smbcsr_bit_mask {
d7699f87
GFT
980 SMBCSR_CNACK = 0x00020000,
981 SMBCSR_RELOAD = 0x00010000,
982 SMBCSR_EEPROMD = 0x00000020,
186fc259
GFT
983 SMBCSR_INITDONE = 0x00000010,
984 SMBCSR_BUSY = 0x0000000F,
985};
cd0ff491 986
186fc259
GFT
987enum jme_smbintf_bit_mask {
988 SMBINTF_HWDATR = 0xFF000000,
989 SMBINTF_HWDATW = 0x00FF0000,
990 SMBINTF_HWADDR = 0x0000FF00,
991 SMBINTF_HWRWN = 0x00000020,
992 SMBINTF_HWCMD = 0x00000010,
993 SMBINTF_FASTM = 0x00000008,
994 SMBINTF_GPIOSCL = 0x00000004,
995 SMBINTF_GPIOSDA = 0x00000002,
996 SMBINTF_GPIOEN = 0x00000001,
997};
cd0ff491 998
186fc259
GFT
999enum jme_smbintf_vals {
1000 SMBINTF_HWRWN_READ = 0x00000020,
1001 SMBINTF_HWRWN_WRITE = 0x00000000,
1002};
cd0ff491 1003
186fc259
GFT
1004enum jme_smbintf_shifts {
1005 SMBINTF_HWDATR_SHIFT = 24,
1006 SMBINTF_HWDATW_SHIFT = 16,
1007 SMBINTF_HWADDR_SHIFT = 8,
1008};
cd0ff491 1009
186fc259
GFT
1010#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1011#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1012#define JME_SMB_LEN 256
1013#define JME_EEPROM_MAGIC 0x250
d7699f87 1014
79ce639c
GFT
1015/*
1016 * Timer Control/Status Register
1017 */
1018enum jme_tmcsr_bit_masks {
1019 TMCSR_SWIT = 0x80000000,
1020 TMCSR_EN = 0x01000000,
1021 TMCSR_CNT = 0x00FFFFFF,
1022};
1023
d7699f87 1024/*
cd0ff491 1025 * General Purpose REG-0
4330c2f2
GFT
1026 */
1027enum jme_gpreg0_masks {
3bf61c55
GFT
1028 GPREG0_DISSH = 0xFF000000,
1029 GPREG0_PCIRLMT = 0x00300000,
1030 GPREG0_PCCNOMUTCLR = 0x00040000,
cdcdc9eb 1031 GPREG0_LNKINTPOLL = 0x00001000,
3bf61c55
GFT
1032 GPREG0_PCCTMR = 0x00000300,
1033 GPREG0_PHYADDR = 0x0000001F,
4330c2f2 1034};
cd0ff491 1035
4330c2f2
GFT
1036enum jme_gpreg0_vals {
1037 GPREG0_DISSH_DW7 = 0x80000000,
1038 GPREG0_DISSH_DW6 = 0x40000000,
1039 GPREG0_DISSH_DW5 = 0x20000000,
1040 GPREG0_DISSH_DW4 = 0x10000000,
1041 GPREG0_DISSH_DW3 = 0x08000000,
1042 GPREG0_DISSH_DW2 = 0x04000000,
1043 GPREG0_DISSH_DW1 = 0x02000000,
1044 GPREG0_DISSH_DW0 = 0x01000000,
1045 GPREG0_DISSH_ALL = 0xFF000000,
1046
1047 GPREG0_PCIRLMT_8 = 0x00000000,
1048 GPREG0_PCIRLMT_6 = 0x00100000,
1049 GPREG0_PCIRLMT_5 = 0x00200000,
1050 GPREG0_PCIRLMT_4 = 0x00300000,
1051
1052 GPREG0_PCCTMR_16ns = 0x00000000,
3bf61c55
GFT
1053 GPREG0_PCCTMR_256ns = 0x00000100,
1054 GPREG0_PCCTMR_1us = 0x00000200,
1055 GPREG0_PCCTMR_1ms = 0x00000300,
4330c2f2
GFT
1056
1057 GPREG0_PHYADDR_1 = 0x00000001,
1058
1059 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
3bf61c55
GFT
1060 GPREG0_PCCTMR_1us |
1061 GPREG0_PHYADDR_1,
4330c2f2
GFT
1062};
1063
1064/*
7ee473a3
GFT
1065 * General Purpose REG-1
1066 * Note: All theses bits defined here are for
1067 * Chip mode revision 0x11 only
1068 */
1069enum jme_gpreg1_masks {
1070 GPREG1_INTRDELAYUNIT = 0x00000018,
1071 GPREG1_INTRDELAYENABLE = 0x00000007,
1072};
1073
1074enum jme_gpreg1_vals {
1075 GPREG1_RSSPATCH = 0x00000040,
1076 GPREG1_HALFMODEPATCH = 0x00000020,
1077
1078 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1079 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1080 GPREG1_INTDLYUNIT_1US = 0x00000010,
1081 GPREG1_INTDLYUNIT_16US = 0x00000018,
1082
1083 GPREG1_INTDLYEN_1U = 0x00000001,
1084 GPREG1_INTDLYEN_2U = 0x00000002,
1085 GPREG1_INTDLYEN_3U = 0x00000003,
1086 GPREG1_INTDLYEN_4U = 0x00000004,
1087 GPREG1_INTDLYEN_5U = 0x00000005,
1088 GPREG1_INTDLYEN_6U = 0x00000006,
1089 GPREG1_INTDLYEN_7U = 0x00000007,
1090
1091 GPREG1_DEFAULT = 0x00000000,
1092};
1093
1094/*
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GFT
1095 * Interrupt Status Bits
1096 */
cd0ff491 1097enum jme_interrupt_bits {
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1098 INTR_SWINTR = 0x80000000,
1099 INTR_TMINTR = 0x40000000,
1100 INTR_LINKCH = 0x20000000,
1101 INTR_PAUSERCV = 0x10000000,
1102 INTR_MAGICRCV = 0x08000000,
1103 INTR_WAKERCV = 0x04000000,
1104 INTR_PCCRX0TO = 0x02000000,
1105 INTR_PCCRX1TO = 0x01000000,
1106 INTR_PCCRX2TO = 0x00800000,
1107 INTR_PCCRX3TO = 0x00400000,
1108 INTR_PCCTXTO = 0x00200000,
1109 INTR_PCCRX0 = 0x00100000,
1110 INTR_PCCRX1 = 0x00080000,
1111 INTR_PCCRX2 = 0x00040000,
1112 INTR_PCCRX3 = 0x00020000,
1113 INTR_PCCTX = 0x00010000,
1114 INTR_RX3EMP = 0x00008000,
1115 INTR_RX2EMP = 0x00004000,
1116 INTR_RX1EMP = 0x00002000,
1117 INTR_RX0EMP = 0x00001000,
1118 INTR_RX3 = 0x00000800,
1119 INTR_RX2 = 0x00000400,
1120 INTR_RX1 = 0x00000200,
1121 INTR_RX0 = 0x00000100,
1122 INTR_TX7 = 0x00000080,
1123 INTR_TX6 = 0x00000040,
1124 INTR_TX5 = 0x00000020,
1125 INTR_TX4 = 0x00000010,
1126 INTR_TX3 = 0x00000008,
1127 INTR_TX2 = 0x00000004,
1128 INTR_TX1 = 0x00000002,
1129 INTR_TX0 = 0x00000001,
1130};
cd0ff491
GFT
1131
1132static const u32 INTR_ENABLE = INTR_SWINTR |
79ce639c
GFT
1133 INTR_TMINTR |
1134 INTR_LINKCH |
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GFT
1135 INTR_PCCRX0TO |
1136 INTR_PCCRX0 |
1137 INTR_PCCTXTO |
cdcdc9eb
GFT
1138 INTR_PCCTX |
1139 INTR_RX0EMP;
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GFT
1140
1141/*
1142 * PCC Control Registers
1143 */
1144enum jme_pccrx_masks {
1145 PCCRXTO_MASK = 0xFFFF0000,
1146 PCCRX_MASK = 0x0000FF00,
1147};
cd0ff491 1148
3bf61c55
GFT
1149enum jme_pcctx_masks {
1150 PCCTXTO_MASK = 0xFFFF0000,
1151 PCCTX_MASK = 0x0000FF00,
1152 PCCTX_QS_MASK = 0x000000FF,
1153};
cd0ff491 1154
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GFT
1155enum jme_pccrx_shifts {
1156 PCCRXTO_SHIFT = 16,
1157 PCCRX_SHIFT = 8,
1158};
cd0ff491 1159
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GFT
1160enum jme_pcctx_shifts {
1161 PCCTXTO_SHIFT = 16,
1162 PCCTX_SHIFT = 8,
1163};
cd0ff491 1164
3bf61c55
GFT
1165enum jme_pcctx_bits {
1166 PCCTXQ0_EN = 0x00000001,
1167 PCCTXQ1_EN = 0x00000002,
1168 PCCTXQ2_EN = 0x00000004,
1169 PCCTXQ3_EN = 0x00000008,
1170 PCCTXQ4_EN = 0x00000010,
1171 PCCTXQ5_EN = 0x00000020,
1172 PCCTXQ6_EN = 0x00000040,
1173 PCCTXQ7_EN = 0x00000080,
1174};
1175
cdcdc9eb
GFT
1176/*
1177 * Chip Mode Register
1178 */
1179enum jme_chipmode_bit_masks {
1180 CM_FPGAVER_MASK = 0xFFFF0000,
58c92f28 1181 CM_CHIPREV_MASK = 0x0000FF00,
cdcdc9eb
GFT
1182 CM_CHIPMODE_MASK = 0x0000000F,
1183};
cd0ff491 1184
cdcdc9eb
GFT
1185enum jme_chipmode_shifts {
1186 CM_FPGAVER_SHIFT = 16,
58c92f28 1187 CM_CHIPREV_SHIFT = 8,
cdcdc9eb 1188};
d7699f87
GFT
1189
1190/*
cd0ff491
GFT
1191 * Aggressive Power Mode Control
1192 */
1193enum jme_apmc_bits {
1194 JME_APMC_PCIE_SD_EN = 0x40000000,
1195 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1196 JME_APMC_EPIEN = 0x04000000,
1197 JME_APMC_EPIEN_CTRL = 0x03000000,
1198};
1199
1200enum jme_apmc_values {
1201 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1202 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1203};
1204
1205#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1206
1207#ifdef REG_DEBUG
1208static char *MAC_REG_NAME[] = {
1209 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1210 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1211 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1212 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1213 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1214 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1215 "JME_PMCS"};
7ee473a3 1216
cd0ff491
GFT
1217static char *PE_REG_NAME[] = {
1218 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1219 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1220 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1221 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1222 "JME_SMBCSR", "JME_SMBINTF"};
7ee473a3 1223
cd0ff491
GFT
1224static char *MISC_REG_NAME[] = {
1225 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1226 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1227 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1228 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1229 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1230 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1231 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1232 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1233 "JME_PCCSRX0"};
7ee473a3 1234
cd0ff491
GFT
1235static inline void reg_dbg(const struct jme_adapter *jme,
1236 const char *msg, u32 val, u32 reg)
1237{
1238 const char *regname;
58c92f28 1239 switch (reg & 0xF00) {
cd0ff491
GFT
1240 case 0x000:
1241 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1242 break;
1243 case 0x400:
1244 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1245 break;
1246 case 0x800:
58c92f28 1247 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
cd0ff491
GFT
1248 break;
1249 default:
1250 regname = PE_REG_NAME[0];
1251 }
1252 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1253 msg, val, regname);
1254}
1255#else
1256static inline void reg_dbg(const struct jme_adapter *jme,
1257 const char *msg, u32 val, u32 reg) {}
1258#endif
1259
1260/*
d7699f87
GFT
1261 * Read/Write MMaped I/O Registers
1262 */
cd0ff491 1263static inline u32 jread32(struct jme_adapter *jme, u32 reg)
d7699f87 1264{
cd0ff491 1265 return readl(jme->regs + reg);
d7699f87 1266}
cd0ff491
GFT
1267
1268static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
d7699f87 1269{
cd0ff491
GFT
1270 reg_dbg(jme, "REG WRITE", val, reg);
1271 writel(val, jme->regs + reg);
1272 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
d7699f87 1273}
cd0ff491
GFT
1274
1275static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
d7699f87
GFT
1276{
1277 /*
1278 * Read after write should cause flush
1279 */
cd0ff491
GFT
1280 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1281 writel(val, jme->regs + reg);
1282 readl(jme->regs + reg);
1283 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
d7699f87
GFT
1284}
1285
1286/*
cdcdc9eb
GFT
1287 * PHY Regs
1288 */
1289enum jme_phy_reg17_bit_masks {
1290 PREG17_SPEED = 0xC000,
1291 PREG17_DUPLEX = 0x2000,
1292 PREG17_SPDRSV = 0x0800,
1293 PREG17_LNKUP = 0x0400,
1294 PREG17_MDI = 0x0040,
1295};
cd0ff491 1296
cdcdc9eb
GFT
1297enum jme_phy_reg17_vals {
1298 PREG17_SPEED_10M = 0x0000,
1299 PREG17_SPEED_100M = 0x4000,
1300 PREG17_SPEED_1000M = 0x8000,
1301};
cd0ff491 1302
8d27293f 1303#define BMSR_ANCOMP 0x0020
cdcdc9eb
GFT
1304
1305/*
58c92f28
GFT
1306 * Workaround
1307 */
1308static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1309{
1310 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1311}
1312
1313/*
cd0ff491 1314 * Function prototypes
d7699f87 1315 */
d7699f87 1316static int jme_set_settings(struct net_device *netdev,
cd0ff491 1317 struct ethtool_cmd *ecmd);
d7699f87
GFT
1318static void jme_set_multi(struct net_device *netdev);
1319
cd0ff491 1320#endif
e5169728 1321