Import jme 1.0.5-backport source
[jme.git] / jme.h
CommitLineData
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
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7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
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9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
cd0ff491 24#ifndef __JME_H_INCLUDED__
3b70a6fa 25#define __JME_H_INCLUDED__
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26
27#define DRV_NAME "jme"
0ede469c 28#define DRV_VERSION "1.0.5"
cd0ff491 29#define PFX DRV_NAME ": "
d7699f87 30
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31#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
32#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
8d27293f 33
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34/*
35 * Message related definitions
36 */
37#define JME_DEF_MSG_ENABLE \
38 (NETIF_MSG_PROBE | \
39 NETIF_MSG_LINK | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR | \
42 NETIF_MSG_HW)
43
44#define jeprintk(pdev, fmt, args...) \
45 printk(KERN_ERR PFX fmt, ## args)
d7699f87 46
3bf61c55 47#ifdef TX_DEBUG
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48#define tx_dbg(priv, fmt, args...) \
49 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ## args)
3bf61c55 50#else
cd0ff491 51#define tx_dbg(priv, fmt, args...)
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52#endif
53
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54#define jme_msg(msglvl, type, priv, fmt, args...) \
55 if (netif_msg_##type(priv)) \
56 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
3bf61c55 57
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58#define msg_probe(priv, fmt, args...) \
59 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
29bdd921 60
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61#define msg_link(priv, fmt, args...) \
62 jme_msg(KERN_INFO, link, priv, fmt, ## args)
79ce639c 63
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64#define msg_intr(priv, fmt, args...) \
65 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
66
67#define msg_rx_err(priv, fmt, args...) \
68 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
b3821cc5 69
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70#define msg_rx_status(priv, fmt, args...) \
71 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
4330c2f2 72
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73#define msg_tx_err(priv, fmt, args...) \
74 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
4330c2f2 75
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76#define msg_tx_done(priv, fmt, args...) \
77 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
d7699f87 78
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79#define msg_tx_queued(priv, fmt, args...) \
80 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
81
82#define msg_hw(priv, fmt, args...) \
83 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
84
85/*
86 * Extra PCI Configuration space interface
87 */
88#define PCI_DCSR_MRRS 0x59
89#define PCI_DCSR_MRRS_MASK 0x70
90
91enum pci_dcsr_mrrs_vals {
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92 MRRS_128B = 0x00,
93 MRRS_256B = 0x10,
94 MRRS_512B = 0x20,
95 MRRS_1024B = 0x30,
96 MRRS_2048B = 0x40,
97 MRRS_4096B = 0x50,
98};
d7699f87 99
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100#define PCI_SPI 0xB0
101
102enum pci_spi_bits {
103 SPI_EN = 0x10,
104 SPI_MISO = 0x08,
105 SPI_MOSI = 0x04,
106 SPI_SCLK = 0x02,
107 SPI_CS = 0x01,
108};
109
110struct jme_spi_op {
111 void __user *uwbuf;
112 void __user *urbuf;
113 __u8 wn; /* Number of write actions */
114 __u8 rn; /* Number of read actions */
115 __u8 bitn; /* Number of bits per action */
116 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
117 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
118
119 /* Internal use only */
120 u8 *kwbuf;
121 u8 *krbuf;
122 u8 sr;
123 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
124};
79ce639c 125
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126enum jme_spi_op_bits {
127 SPI_MODE_CPHA = 0x01,
128 SPI_MODE_CPOL = 0x02,
129 SPI_MODE_DUP = 0x80,
130};
131
132#define HALF_US 500 /* 500 ns */
133#define JMESPIIOCTL SIOCDEVPRIVATE
134
135/*
136 * Dynamic(adaptive)/Static PCC values
137 */
3bf61c55 138enum dynamic_pcc_values {
192570e0 139 PCC_OFF = 0,
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140 PCC_P1 = 1,
141 PCC_P2 = 2,
142 PCC_P3 = 3,
143
192570e0 144 PCC_OFF_TO = 0,
3bf61c55 145 PCC_P1_TO = 1,
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146 PCC_P2_TO = 64,
147 PCC_P3_TO = 128,
3bf61c55 148
192570e0 149 PCC_OFF_CNT = 0,
3bf61c55 150 PCC_P1_CNT = 1,
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151 PCC_P2_CNT = 16,
152 PCC_P3_CNT = 32,
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153};
154struct dynpcc_info {
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155 unsigned long last_bytes;
156 unsigned long last_pkts;
79ce639c 157 unsigned long intr_cnt;
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158 unsigned char cur;
159 unsigned char attempt;
160 unsigned char cnt;
161};
79ce639c 162#define PCC_INTERVAL_US 100000
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163#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
164#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
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165#define PCC_P2_THRESHOLD 800
166#define PCC_INTR_THRESHOLD 800
47220951 167#define PCC_TX_TO 1000
b3821cc5 168#define PCC_TX_CNT 8
3bf61c55 169
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170/*
171 * TX/RX Descriptors
4330c2f2 172 *
cd0ff491 173 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
d7699f87 174 */
4330c2f2 175#define RING_DESC_ALIGN 16 /* Descriptor alignment */
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176#define TX_DESC_SIZE 16
177#define TX_RING_NR 8
cd0ff491 178#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 179
3bf61c55 180struct txdesc {
d7699f87 181 union {
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182 __u8 all[16];
183 __le32 dw[4];
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184 struct {
185 /* DW0 */
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186 __le16 vlan;
187 __u8 rsv1;
188 __u8 flags;
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189
190 /* DW1 */
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191 __le16 datalen;
192 __le16 mss;
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193
194 /* DW2 */
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195 __le16 pktsize;
196 __le16 rsv2;
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197
198 /* DW3 */
cd0ff491 199 __le32 bufaddr;
d7699f87 200 } desc1;
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201 struct {
202 /* DW0 */
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203 __le16 rsv1;
204 __u8 rsv2;
205 __u8 flags;
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206
207 /* DW1 */
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208 __le16 datalen;
209 __le16 rsv3;
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210
211 /* DW2 */
cd0ff491 212 __le32 bufaddrh;
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213
214 /* DW3 */
cd0ff491 215 __le32 bufaddrl;
3bf61c55 216 } desc2;
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217 struct {
218 /* DW0 */
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219 __u8 ehdrsz;
220 __u8 rsv1;
221 __u8 rsv2;
222 __u8 flags;
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223
224 /* DW1 */
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225 __le16 trycnt;
226 __le16 segcnt;
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227
228 /* DW2 */
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229 __le16 pktsz;
230 __le16 rsv3;
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231
232 /* DW3 */
cd0ff491 233 __le32 bufaddrl;
8c198884 234 } descwb;
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235 };
236};
cd0ff491 237
8c198884 238enum jme_txdesc_flags_bits {
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239 TXFLAG_OWN = 0x80,
240 TXFLAG_INT = 0x40,
3bf61c55 241 TXFLAG_64BIT = 0x20,
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242 TXFLAG_TCPCS = 0x10,
243 TXFLAG_UDPCS = 0x08,
244 TXFLAG_IPCS = 0x04,
245 TXFLAG_LSEN = 0x02,
246 TXFLAG_TAGON = 0x01,
247};
cd0ff491 248
b3821cc5 249#define TXDESC_MSS_SHIFT 2
0ede469c 250enum jme_txwbdesc_flags_bits {
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251 TXWBFLAG_OWN = 0x80,
252 TXWBFLAG_INT = 0x40,
253 TXWBFLAG_TMOUT = 0x20,
254 TXWBFLAG_TRYOUT = 0x10,
255 TXWBFLAG_COL = 0x08,
256
257 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
258 TXWBFLAG_TRYOUT |
259 TXWBFLAG_COL,
260};
d7699f87 261
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262#define RX_DESC_SIZE 16
263#define RX_RING_NR 4
cd0ff491 264#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 265#define RX_BUF_DMA_ALIGN 8
3bf61c55 266#define RX_PREPAD_SIZE 10
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267#define ETH_CRC_LEN 2
268#define RX_VLANHDR_LEN 2
269#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
270 ETH_HLEN + \
271 ETH_CRC_LEN + \
272 RX_VLANHDR_LEN + \
273 RX_BUF_DMA_ALIGN)
d7699f87 274
3bf61c55 275struct rxdesc {
d7699f87 276 union {
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277 __u8 all[16];
278 __le32 dw[4];
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279 struct {
280 /* DW0 */
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281 __le16 rsv2;
282 __u8 rsv1;
283 __u8 flags;
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284
285 /* DW1 */
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286 __le16 datalen;
287 __le16 wbcpl;
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288
289 /* DW2 */
cd0ff491 290 __le32 bufaddrh;
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291
292 /* DW3 */
cd0ff491 293 __le32 bufaddrl;
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294 } desc1;
295 struct {
296 /* DW0 */
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297 __le16 vlan;
298 __le16 flags;
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299
300 /* DW1 */
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301 __le16 framesize;
302 __u8 errstat;
303 __u8 desccnt;
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304
305 /* DW2 */
cd0ff491 306 __le32 rsshash;
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307
308 /* DW3 */
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309 __u8 hashfun;
310 __u8 hashtype;
311 __le16 resrv;
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312 } descwb;
313 };
314};
cd0ff491 315
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316enum jme_rxdesc_flags_bits {
317 RXFLAG_OWN = 0x80,
318 RXFLAG_INT = 0x40,
319 RXFLAG_64BIT = 0x20,
320};
cd0ff491 321
d7699f87 322enum jme_rxwbdesc_flags_bits {
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323 RXWBFLAG_OWN = 0x8000,
324 RXWBFLAG_INT = 0x4000,
325 RXWBFLAG_MF = 0x2000,
326 RXWBFLAG_64BIT = 0x2000,
327 RXWBFLAG_TCPON = 0x1000,
328 RXWBFLAG_UDPON = 0x0800,
329 RXWBFLAG_IPCS = 0x0400,
330 RXWBFLAG_TCPCS = 0x0200,
331 RXWBFLAG_UDPCS = 0x0100,
332 RXWBFLAG_TAGON = 0x0080,
333 RXWBFLAG_IPV4 = 0x0040,
334 RXWBFLAG_IPV6 = 0x0020,
335 RXWBFLAG_PAUSE = 0x0010,
336 RXWBFLAG_MAGIC = 0x0008,
337 RXWBFLAG_WAKEUP = 0x0004,
338 RXWBFLAG_DEST = 0x0003,
339 RXWBFLAG_DEST_UNI = 0x0001,
340 RXWBFLAG_DEST_MUL = 0x0002,
341 RXWBFLAG_DEST_BRO = 0x0003,
d7699f87 342};
cd0ff491 343
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344enum jme_rxwbdesc_desccnt_mask {
345 RXWBDCNT_WBCPL = 0x80,
346 RXWBDCNT_DCNT = 0x7F,
347};
cd0ff491 348
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349enum jme_rxwbdesc_errstat_bits {
350 RXWBERR_LIMIT = 0x80,
351 RXWBERR_MIIER = 0x40,
352 RXWBERR_NIBON = 0x20,
353 RXWBERR_COLON = 0x10,
354 RXWBERR_ABORT = 0x08,
355 RXWBERR_SHORT = 0x04,
356 RXWBERR_OVERUN = 0x02,
357 RXWBERR_CRCERR = 0x01,
358 RXWBERR_ALLERR = 0xFF,
359};
360
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361/*
362 * Buffer information corresponding to ring descriptors.
363 */
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364struct jme_buffer_info {
365 struct sk_buff *skb;
366 dma_addr_t mapping;
367 int len;
3bf61c55 368 int nr_desc;
cdcdc9eb 369 unsigned long start_xmit;
4330c2f2 370};
d7699f87 371
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372/*
373 * The structure holding buffer information and ring descriptors all together.
374 */
d7699f87 375struct jme_ring {
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376 void *alloc; /* pointer to allocated memory */
377 void *desc; /* pointer to ring memory */
378 dma_addr_t dmaalloc; /* phys address of ring alloc */
379 dma_addr_t dma; /* phys address for ring dma */
d7699f87 380
4330c2f2 381 /* Buffer information corresponding to each descriptor */
0ede469c 382 struct jme_buffer_info *bufinf;
d7699f87 383
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384 int next_to_use;
385 atomic_t next_to_clean;
79ce639c 386 atomic_t nr_free;
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387};
388
0ede469c 389#include <linux/version.h>
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390#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
391#define false 0
392#define true 0
393#define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
394#define PCI_VENDOR_ID_JMICRON 0x197B
395#endif
396
397#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
398#define PCI_VDEVICE(vendor, device) \
399 PCI_VENDOR_ID_##vendor, (device), \
400 PCI_ANY_ID, PCI_ANY_ID, 0, 0
401#endif
402
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403#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
404#define NET_STAT(priv) priv->stats
405#define NETDEV_GET_STATS(netdev, fun_ptr) \
406 netdev->get_stats = fun_ptr
407#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
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408static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
409{
410 return skb->nh.iph;
411}
412
413static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
414{
415 return skb->nh.ipv6h;
416}
417
418static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
419{
420 return skb->h.th;
421}
85776f33 422#else
0ede469c 423#define NET_STAT(priv) (priv->dev->stats)
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424#define NETDEV_GET_STATS(netdev, fun_ptr)
425#define DECLARE_NET_DEVICE_STATS
85776f33 426#endif
3bf61c55 427
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428#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
429#define DECLARE_NAPI_STRUCT
430#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
431 dev->poll = pollfn; \
432 dev->weight = q;
433#define JME_NAPI_HOLDER(holder) struct net_device *holder
434#define JME_NAPI_WEIGHT(w) int *w
435#define JME_NAPI_WEIGHT_VAL(w) *w
436#define JME_NAPI_WEIGHT_SET(w, r) *w = r
3b70a6fa 437#define DECLARE_NETDEV struct net_device *netdev = jme->dev;
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438#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
439#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
440#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
441#define JME_RX_SCHEDULE_PREP(priv) \
442 netif_rx_schedule_prep(priv->dev)
443#define JME_RX_SCHEDULE(priv) \
444 __netif_rx_schedule(priv->dev);
0ede469c 445#else
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446#define DECLARE_NAPI_STRUCT struct napi_struct napi;
447#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
448 netif_napi_add(dev, napis, pollfn, q);
449#define JME_NAPI_HOLDER(holder) struct napi_struct *holder
450#define JME_NAPI_WEIGHT(w) int w
451#define JME_NAPI_WEIGHT_VAL(w) w
452#define JME_NAPI_WEIGHT_SET(w, r)
453#define DECLARE_NETDEV
454#define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
455#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
456#define JME_NAPI_DISABLE(priv) \
457 if (!napi_disable_pending(&priv->napi)) \
458 napi_disable(&priv->napi);
459#define JME_RX_SCHEDULE_PREP(priv) \
460 napi_schedule_prep(&priv->napi)
461#define JME_RX_SCHEDULE(priv) \
462 __napi_schedule(&priv->napi);
85776f33 463#endif
cdcdc9eb 464
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465/*
466 * Jmac Adapter Private data
467 */
468struct jme_adapter {
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469 struct pci_dev *pdev;
470 struct net_device *dev;
471 void __iomem *regs;
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472 struct mii_if_info mii_if;
473 struct jme_ring rxring[RX_RING_NR];
474 struct jme_ring txring[TX_RING_NR];
d7699f87 475 spinlock_t phy_lock;
fcf45b4c 476 spinlock_t macaddr_lock;
8c198884 477 spinlock_t rxmcs_lock;
fcf45b4c 478 struct tasklet_struct rxempty_task;
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479 struct tasklet_struct rxclean_task;
480 struct tasklet_struct txclean_task;
481 struct tasklet_struct linkch_task;
79ce639c 482 struct tasklet_struct pcc_task;
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483 unsigned long flags;
484 u32 reg_txcs;
485 u32 reg_txpfc;
486 u32 reg_rxcs;
487 u32 reg_rxmcs;
488 u32 reg_ghc;
489 u32 reg_pmcs;
490 u32 phylink;
491 u32 tx_ring_size;
492 u32 tx_ring_mask;
493 u32 tx_wake_threshold;
494 u32 rx_ring_size;
495 u32 rx_ring_mask;
496 u8 mrrs;
497 unsigned int fpgaver;
58c92f28 498 unsigned int chiprev;
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499 u8 rev;
500 u32 msg_enable;
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501 struct ethtool_cmd old_ecmd;
502 unsigned int old_mtu;
cd0ff491 503 struct vlan_group *vlgrp;
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504 struct dynpcc_info dpi;
505 atomic_t intr_sem;
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506 atomic_t link_changing;
507 atomic_t tx_cleaning;
508 atomic_t rx_cleaning;
192570e0 509 atomic_t rx_empty;
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510 int (*jme_rx)(struct sk_buff *skb);
511 int (*jme_vlan_rx)(struct sk_buff *skb,
512 struct vlan_group *grp,
513 unsigned short vlan_tag);
514 DECLARE_NAPI_STRUCT
3bf61c55 515 DECLARE_NET_DEVICE_STATS
d7699f87 516};
cd0ff491 517
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518#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
519static struct net_device_stats *
520jme_get_stats(struct net_device *netdev)
521{
522 struct jme_adapter *jme = netdev_priv(netdev);
523 return &jme->stats;
524}
525#endif
526
79ce639c 527enum jme_flags_bits {
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528 JME_FLAG_MSI = 1,
529 JME_FLAG_SSET = 2,
530 JME_FLAG_TXCSUM = 3,
531 JME_FLAG_TSO = 4,
532 JME_FLAG_POLL = 5,
533 JME_FLAG_SHUTDOWN = 6,
8c198884 534};
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535
536#define TX_TIMEOUT (5 * HZ)
186fc259 537#define JME_REG_LEN 0x500
cd0ff491 538#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
8c198884 539
85776f33 540#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
7ee473a3 541static inline struct jme_adapter*
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542jme_napi_priv(struct net_device *holder)
543{
7ee473a3 544 struct jme_adapter *jme;
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545 jme = netdev_priv(holder);
546 return jme;
547}
548#else
7ee473a3 549static inline struct jme_adapter*
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550jme_napi_priv(struct napi_struct *napi)
551{
7ee473a3 552 struct jme_adapter *jme;
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553 jme = container_of(napi, struct jme_adapter, napi);
554 return jme;
555}
85776f33 556#endif
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557
558/*
559 * MMaped I/O Resters
560 */
561enum jme_iomap_offsets {
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562 JME_MAC = 0x0000,
563 JME_PHY = 0x0400,
d7699f87 564 JME_MISC = 0x0800,
4330c2f2 565 JME_RSS = 0x0C00,
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566};
567
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568enum jme_iomap_lens {
569 JME_MAC_LEN = 0x80,
570 JME_PHY_LEN = 0x58,
571 JME_MISC_LEN = 0x98,
572 JME_RSS_LEN = 0xFF,
573};
574
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575enum jme_iomap_regs {
576 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
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GFT
577 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
578 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
d7699f87
GFT
579 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
580 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
581 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
582 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
583 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
584
585 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
3bf61c55
GFT
586 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
587 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
d7699f87
GFT
588 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
589 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
590 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
4330c2f2
GFT
591 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
592 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
3bf61c55
GFT
593 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
594 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
d7699f87
GFT
595 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
596 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
597
598 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
599 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
600 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
601
602
3bf61c55 603 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
d7699f87
GFT
604 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
605 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
186fc259 606 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
d7699f87
GFT
607
608
cd0ff491
GFT
609 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
610 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
611 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
612 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
613 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
614 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
615 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
616 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
617 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
618 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
619 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
620 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
621 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
622 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
623 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
624 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
d7699f87
GFT
625};
626
627/*
628 * TX Control/Status Bits
629 */
630enum jme_txcs_bits {
631 TXCS_QUEUE7S = 0x00008000,
632 TXCS_QUEUE6S = 0x00004000,
633 TXCS_QUEUE5S = 0x00002000,
634 TXCS_QUEUE4S = 0x00001000,
635 TXCS_QUEUE3S = 0x00000800,
636 TXCS_QUEUE2S = 0x00000400,
637 TXCS_QUEUE1S = 0x00000200,
638 TXCS_QUEUE0S = 0x00000100,
639 TXCS_FIFOTH = 0x000000C0,
640 TXCS_DMASIZE = 0x00000030,
641 TXCS_BURST = 0x00000004,
642 TXCS_ENABLE = 0x00000001,
643};
cd0ff491 644
d7699f87
GFT
645enum jme_txcs_value {
646 TXCS_FIFOTH_16QW = 0x000000C0,
647 TXCS_FIFOTH_12QW = 0x00000080,
648 TXCS_FIFOTH_8QW = 0x00000040,
649 TXCS_FIFOTH_4QW = 0x00000000,
650
651 TXCS_DMASIZE_64B = 0x00000000,
652 TXCS_DMASIZE_128B = 0x00000010,
653 TXCS_DMASIZE_256B = 0x00000020,
654 TXCS_DMASIZE_512B = 0x00000030,
655
656 TXCS_SELECT_QUEUE0 = 0x00000000,
657 TXCS_SELECT_QUEUE1 = 0x00010000,
658 TXCS_SELECT_QUEUE2 = 0x00020000,
659 TXCS_SELECT_QUEUE3 = 0x00030000,
660 TXCS_SELECT_QUEUE4 = 0x00040000,
661 TXCS_SELECT_QUEUE5 = 0x00050000,
662 TXCS_SELECT_QUEUE6 = 0x00060000,
663 TXCS_SELECT_QUEUE7 = 0x00070000,
664
665 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
d7699f87
GFT
666 TXCS_BURST,
667};
cd0ff491 668
29bdd921 669#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
670
671/*
672 * TX MAC Control/Status Bits
673 */
674enum jme_txmcs_bit_masks {
675 TXMCS_IFG2 = 0xC0000000,
676 TXMCS_IFG1 = 0x30000000,
677 TXMCS_TTHOLD = 0x00000300,
678 TXMCS_FBURST = 0x00000080,
679 TXMCS_CARRIEREXT = 0x00000040,
680 TXMCS_DEFER = 0x00000020,
681 TXMCS_BACKOFF = 0x00000010,
682 TXMCS_CARRIERSENSE = 0x00000008,
683 TXMCS_COLLISION = 0x00000004,
684 TXMCS_CRC = 0x00000002,
685 TXMCS_PADDING = 0x00000001,
686};
cd0ff491 687
d7699f87
GFT
688enum jme_txmcs_values {
689 TXMCS_IFG2_6_4 = 0x00000000,
690 TXMCS_IFG2_8_5 = 0x40000000,
691 TXMCS_IFG2_10_6 = 0x80000000,
692 TXMCS_IFG2_12_7 = 0xC0000000,
693
694 TXMCS_IFG1_8_4 = 0x00000000,
695 TXMCS_IFG1_12_6 = 0x10000000,
696 TXMCS_IFG1_16_8 = 0x20000000,
697 TXMCS_IFG1_20_10 = 0x30000000,
698
699 TXMCS_TTHOLD_1_8 = 0x00000000,
700 TXMCS_TTHOLD_1_4 = 0x00000100,
701 TXMCS_TTHOLD_1_2 = 0x00000200,
702 TXMCS_TTHOLD_FULL = 0x00000300,
703
704 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
705 TXMCS_IFG1_16_8 |
706 TXMCS_TTHOLD_FULL |
707 TXMCS_DEFER |
708 TXMCS_CRC |
709 TXMCS_PADDING,
710};
711
8c198884
GFT
712enum jme_txpfc_bits_masks {
713 TXPFC_VLAN_TAG = 0xFFFF0000,
714 TXPFC_VLAN_EN = 0x00008000,
715 TXPFC_PF_EN = 0x00000001,
716};
717
718enum jme_txtrhd_bits_masks {
719 TXTRHD_TXPEN = 0x80000000,
720 TXTRHD_TXP = 0x7FFFFF00,
721 TXTRHD_TXREN = 0x00000080,
722 TXTRHD_TXRL = 0x0000007F,
723};
cd0ff491 724
8c198884
GFT
725enum jme_txtrhd_shifts {
726 TXTRHD_TXP_SHIFT = 8,
727 TXTRHD_TXRL_SHIFT = 0,
728};
729
d7699f87
GFT
730/*
731 * RX Control/Status Bits
732 */
4330c2f2 733enum jme_rxcs_bit_masks {
3bf61c55
GFT
734 /* FIFO full threshold for transmitting Tx Pause Packet */
735 RXCS_FIFOTHTP = 0x30000000,
736 /* FIFO threshold for processing next packet */
737 RXCS_FIFOTHNP = 0x0C000000,
4330c2f2
GFT
738 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
739 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
740 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
741 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
742 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
743 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
744 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
745 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
746 RXCS_QST = 0x00000004, /* Receive queue start */
747 RXCS_SUSPEND = 0x00000002,
d7699f87
GFT
748 RXCS_ENABLE = 0x00000001,
749};
cd0ff491 750
4330c2f2
GFT
751enum jme_rxcs_values {
752 RXCS_FIFOTHTP_16T = 0x00000000,
753 RXCS_FIFOTHTP_32T = 0x10000000,
754 RXCS_FIFOTHTP_64T = 0x20000000,
755 RXCS_FIFOTHTP_128T = 0x30000000,
756
757 RXCS_FIFOTHNP_16QW = 0x00000000,
758 RXCS_FIFOTHNP_32QW = 0x04000000,
759 RXCS_FIFOTHNP_64QW = 0x08000000,
760 RXCS_FIFOTHNP_128QW = 0x0C000000,
761
762 RXCS_DMAREQSZ_16B = 0x00000000,
763 RXCS_DMAREQSZ_32B = 0x01000000,
764 RXCS_DMAREQSZ_64B = 0x02000000,
765 RXCS_DMAREQSZ_128B = 0x03000000,
766
767 RXCS_QUEUESEL_Q0 = 0x00000000,
768 RXCS_QUEUESEL_Q1 = 0x00010000,
769 RXCS_QUEUESEL_Q2 = 0x00020000,
770 RXCS_QUEUESEL_Q3 = 0x00030000,
771
772 RXCS_RETRYGAP_256ns = 0x00000000,
773 RXCS_RETRYGAP_512ns = 0x00001000,
774 RXCS_RETRYGAP_1024ns = 0x00002000,
775 RXCS_RETRYGAP_2048ns = 0x00003000,
776 RXCS_RETRYGAP_4096ns = 0x00004000,
777 RXCS_RETRYGAP_8192ns = 0x00005000,
778 RXCS_RETRYGAP_16384ns = 0x00006000,
779 RXCS_RETRYGAP_32768ns = 0x00007000,
780
781 RXCS_RETRYCNT_0 = 0x00000000,
782 RXCS_RETRYCNT_4 = 0x00000100,
783 RXCS_RETRYCNT_8 = 0x00000200,
784 RXCS_RETRYCNT_12 = 0x00000300,
785 RXCS_RETRYCNT_16 = 0x00000400,
786 RXCS_RETRYCNT_20 = 0x00000500,
787 RXCS_RETRYCNT_24 = 0x00000600,
788 RXCS_RETRYCNT_28 = 0x00000700,
789 RXCS_RETRYCNT_32 = 0x00000800,
790 RXCS_RETRYCNT_36 = 0x00000900,
791 RXCS_RETRYCNT_40 = 0x00000A00,
792 RXCS_RETRYCNT_44 = 0x00000B00,
793 RXCS_RETRYCNT_48 = 0x00000C00,
794 RXCS_RETRYCNT_52 = 0x00000D00,
795 RXCS_RETRYCNT_56 = 0x00000E00,
796 RXCS_RETRYCNT_60 = 0x00000F00,
797
798 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
79ce639c 799 RXCS_FIFOTHNP_128QW |
4330c2f2
GFT
800 RXCS_DMAREQSZ_128B |
801 RXCS_RETRYGAP_256ns |
802 RXCS_RETRYCNT_32,
803};
cd0ff491 804
29bdd921 805#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
806
807/*
808 * RX MAC Control/Status Bits
809 */
810enum jme_rxmcs_bits {
811 RXMCS_ALLFRAME = 0x00000800,
812 RXMCS_BRDFRAME = 0x00000400,
813 RXMCS_MULFRAME = 0x00000200,
814 RXMCS_UNIFRAME = 0x00000100,
815 RXMCS_ALLMULFRAME = 0x00000080,
816 RXMCS_MULFILTERED = 0x00000040,
3bf61c55
GFT
817 RXMCS_RXCOLLDEC = 0x00000020,
818 RXMCS_FLOWCTRL = 0x00000008,
819 RXMCS_VTAGRM = 0x00000004,
820 RXMCS_PREPAD = 0x00000002,
821 RXMCS_CHECKSUM = 0x00000001,
b3821cc5 822
8c198884
GFT
823 RXMCS_DEFAULT = RXMCS_VTAGRM |
824 RXMCS_PREPAD |
825 RXMCS_FLOWCTRL |
826 RXMCS_CHECKSUM,
d7699f87
GFT
827};
828
829/*
b3821cc5
GFT
830 * Wakeup Frame setup interface registers
831 */
832#define WAKEUP_FRAME_NR 8
833#define WAKEUP_FRAME_MASK_DWNR 4
cd0ff491 834
b3821cc5
GFT
835enum jme_wfoi_bit_masks {
836 WFOI_MASK_SEL = 0x00000070,
837 WFOI_CRC_SEL = 0x00000008,
838 WFOI_FRAME_SEL = 0x00000007,
839};
cd0ff491 840
b3821cc5
GFT
841enum jme_wfoi_shifts {
842 WFOI_MASK_SHIFT = 4,
843};
844
845/*
d7699f87
GFT
846 * SMI Related definitions
847 */
cd0ff491 848enum jme_smi_bit_mask {
d7699f87
GFT
849 SMI_DATA_MASK = 0xFFFF0000,
850 SMI_REG_ADDR_MASK = 0x0000F800,
851 SMI_PHY_ADDR_MASK = 0x000007C0,
852 SMI_OP_WRITE = 0x00000020,
3bf61c55
GFT
853 /* Set to 1, after req done it'll be cleared to 0 */
854 SMI_OP_REQ = 0x00000010,
d7699f87
GFT
855 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
856 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
857 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
858 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
859};
cd0ff491
GFT
860
861enum jme_smi_bit_shift {
d7699f87
GFT
862 SMI_DATA_SHIFT = 16,
863 SMI_REG_ADDR_SHIFT = 11,
864 SMI_PHY_ADDR_SHIFT = 6,
865};
cd0ff491
GFT
866
867static inline u32 smi_reg_addr(int x)
d7699f87 868{
cd0ff491 869 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
d7699f87 870}
cd0ff491
GFT
871
872static inline u32 smi_phy_addr(int x)
d7699f87 873{
cd0ff491 874 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
d7699f87 875}
cd0ff491 876
8d27293f 877#define JME_PHY_TIMEOUT 100 /* 100 msec */
186fc259 878#define JME_PHY_REG_NR 32
d7699f87
GFT
879
880/*
881 * Global Host Control
882 */
883enum jme_ghc_bit_mask {
3b70a6fa
GFT
884 GHC_SWRST = 0x40000000,
885 GHC_DPX = 0x00000040,
886 GHC_SPEED = 0x00000030,
887 GHC_LINK_POLL = 0x00000001,
d7699f87 888};
cd0ff491 889
d7699f87 890enum jme_ghc_speed_val {
3b70a6fa
GFT
891 GHC_SPEED_10M = 0x00000010,
892 GHC_SPEED_100M = 0x00000020,
893 GHC_SPEED_1000M = 0x00000030,
894};
895
896enum jme_ghc_to_clk {
897 GHC_TO_CLK_OFF = 0x00000000,
898 GHC_TO_CLK_GPHY = 0x00400000,
899 GHC_TO_CLK_PCIE = 0x00800000,
900 GHC_TO_CLK_INVALID = 0x00C00000,
901};
902
903enum jme_ghc_txmac_clk {
904 GHC_TXMAC_CLK_OFF = 0x00000000,
905 GHC_TXMAC_CLK_GPHY = 0x00100000,
906 GHC_TXMAC_CLK_PCIE = 0x00200000,
907 GHC_TXMAC_CLK_INVALID = 0x00300000,
d7699f87
GFT
908};
909
910/*
29bdd921
GFT
911 * Power management control and status register
912 */
913enum jme_pmcs_bit_masks {
914 PMCS_WF7DET = 0x80000000,
915 PMCS_WF6DET = 0x40000000,
916 PMCS_WF5DET = 0x20000000,
917 PMCS_WF4DET = 0x10000000,
918 PMCS_WF3DET = 0x08000000,
919 PMCS_WF2DET = 0x04000000,
920 PMCS_WF1DET = 0x02000000,
921 PMCS_WF0DET = 0x01000000,
922 PMCS_LFDET = 0x00040000,
923 PMCS_LRDET = 0x00020000,
924 PMCS_MFDET = 0x00010000,
925 PMCS_WF7EN = 0x00008000,
926 PMCS_WF6EN = 0x00004000,
927 PMCS_WF5EN = 0x00002000,
928 PMCS_WF4EN = 0x00001000,
929 PMCS_WF3EN = 0x00000800,
930 PMCS_WF2EN = 0x00000400,
931 PMCS_WF1EN = 0x00000200,
932 PMCS_WF0EN = 0x00000100,
933 PMCS_LFEN = 0x00000004,
934 PMCS_LREN = 0x00000002,
935 PMCS_MFEN = 0x00000001,
936};
937
938/*
3bf61c55 939 * Giga PHY Status Registers
d7699f87
GFT
940 */
941enum jme_phy_link_bit_mask {
942 PHY_LINK_SPEED_MASK = 0x0000C000,
943 PHY_LINK_DUPLEX = 0x00002000,
944 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
945 PHY_LINK_UP = 0x00000400,
946 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
fcf45b4c 947 PHY_LINK_MDI_STAT = 0x00000040,
d7699f87 948};
cd0ff491 949
d7699f87
GFT
950enum jme_phy_link_speed_val {
951 PHY_LINK_SPEED_10M = 0x00000000,
952 PHY_LINK_SPEED_100M = 0x00004000,
953 PHY_LINK_SPEED_1000M = 0x00008000,
954};
cd0ff491 955
fcf45b4c 956#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
d7699f87
GFT
957
958/*
959 * SMB Control and Status
960 */
79ce639c 961enum jme_smbcsr_bit_mask {
d7699f87
GFT
962 SMBCSR_CNACK = 0x00020000,
963 SMBCSR_RELOAD = 0x00010000,
964 SMBCSR_EEPROMD = 0x00000020,
186fc259
GFT
965 SMBCSR_INITDONE = 0x00000010,
966 SMBCSR_BUSY = 0x0000000F,
967};
cd0ff491 968
186fc259
GFT
969enum jme_smbintf_bit_mask {
970 SMBINTF_HWDATR = 0xFF000000,
971 SMBINTF_HWDATW = 0x00FF0000,
972 SMBINTF_HWADDR = 0x0000FF00,
973 SMBINTF_HWRWN = 0x00000020,
974 SMBINTF_HWCMD = 0x00000010,
975 SMBINTF_FASTM = 0x00000008,
976 SMBINTF_GPIOSCL = 0x00000004,
977 SMBINTF_GPIOSDA = 0x00000002,
978 SMBINTF_GPIOEN = 0x00000001,
979};
cd0ff491 980
186fc259
GFT
981enum jme_smbintf_vals {
982 SMBINTF_HWRWN_READ = 0x00000020,
983 SMBINTF_HWRWN_WRITE = 0x00000000,
984};
cd0ff491 985
186fc259
GFT
986enum jme_smbintf_shifts {
987 SMBINTF_HWDATR_SHIFT = 24,
988 SMBINTF_HWDATW_SHIFT = 16,
989 SMBINTF_HWADDR_SHIFT = 8,
990};
cd0ff491 991
186fc259
GFT
992#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
993#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
994#define JME_SMB_LEN 256
995#define JME_EEPROM_MAGIC 0x250
d7699f87 996
79ce639c
GFT
997/*
998 * Timer Control/Status Register
999 */
1000enum jme_tmcsr_bit_masks {
1001 TMCSR_SWIT = 0x80000000,
1002 TMCSR_EN = 0x01000000,
1003 TMCSR_CNT = 0x00FFFFFF,
1004};
1005
d7699f87 1006/*
cd0ff491 1007 * General Purpose REG-0
4330c2f2
GFT
1008 */
1009enum jme_gpreg0_masks {
3bf61c55
GFT
1010 GPREG0_DISSH = 0xFF000000,
1011 GPREG0_PCIRLMT = 0x00300000,
1012 GPREG0_PCCNOMUTCLR = 0x00040000,
cdcdc9eb 1013 GPREG0_LNKINTPOLL = 0x00001000,
3bf61c55
GFT
1014 GPREG0_PCCTMR = 0x00000300,
1015 GPREG0_PHYADDR = 0x0000001F,
4330c2f2 1016};
cd0ff491 1017
4330c2f2
GFT
1018enum jme_gpreg0_vals {
1019 GPREG0_DISSH_DW7 = 0x80000000,
1020 GPREG0_DISSH_DW6 = 0x40000000,
1021 GPREG0_DISSH_DW5 = 0x20000000,
1022 GPREG0_DISSH_DW4 = 0x10000000,
1023 GPREG0_DISSH_DW3 = 0x08000000,
1024 GPREG0_DISSH_DW2 = 0x04000000,
1025 GPREG0_DISSH_DW1 = 0x02000000,
1026 GPREG0_DISSH_DW0 = 0x01000000,
1027 GPREG0_DISSH_ALL = 0xFF000000,
1028
1029 GPREG0_PCIRLMT_8 = 0x00000000,
1030 GPREG0_PCIRLMT_6 = 0x00100000,
1031 GPREG0_PCIRLMT_5 = 0x00200000,
1032 GPREG0_PCIRLMT_4 = 0x00300000,
1033
1034 GPREG0_PCCTMR_16ns = 0x00000000,
3bf61c55
GFT
1035 GPREG0_PCCTMR_256ns = 0x00000100,
1036 GPREG0_PCCTMR_1us = 0x00000200,
1037 GPREG0_PCCTMR_1ms = 0x00000300,
4330c2f2
GFT
1038
1039 GPREG0_PHYADDR_1 = 0x00000001,
1040
1041 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
3bf61c55
GFT
1042 GPREG0_PCCTMR_1us |
1043 GPREG0_PHYADDR_1,
4330c2f2
GFT
1044};
1045
1046/*
7ee473a3
GFT
1047 * General Purpose REG-1
1048 * Note: All theses bits defined here are for
1049 * Chip mode revision 0x11 only
1050 */
1051enum jme_gpreg1_masks {
1052 GPREG1_INTRDELAYUNIT = 0x00000018,
1053 GPREG1_INTRDELAYENABLE = 0x00000007,
1054};
1055
1056enum jme_gpreg1_vals {
1057 GPREG1_RSSPATCH = 0x00000040,
1058 GPREG1_HALFMODEPATCH = 0x00000020,
1059
1060 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1061 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1062 GPREG1_INTDLYUNIT_1US = 0x00000010,
1063 GPREG1_INTDLYUNIT_16US = 0x00000018,
1064
1065 GPREG1_INTDLYEN_1U = 0x00000001,
1066 GPREG1_INTDLYEN_2U = 0x00000002,
1067 GPREG1_INTDLYEN_3U = 0x00000003,
1068 GPREG1_INTDLYEN_4U = 0x00000004,
1069 GPREG1_INTDLYEN_5U = 0x00000005,
1070 GPREG1_INTDLYEN_6U = 0x00000006,
1071 GPREG1_INTDLYEN_7U = 0x00000007,
1072
1073 GPREG1_DEFAULT = 0x00000000,
1074};
1075
1076/*
d7699f87
GFT
1077 * Interrupt Status Bits
1078 */
cd0ff491 1079enum jme_interrupt_bits {
d7699f87
GFT
1080 INTR_SWINTR = 0x80000000,
1081 INTR_TMINTR = 0x40000000,
1082 INTR_LINKCH = 0x20000000,
1083 INTR_PAUSERCV = 0x10000000,
1084 INTR_MAGICRCV = 0x08000000,
1085 INTR_WAKERCV = 0x04000000,
1086 INTR_PCCRX0TO = 0x02000000,
1087 INTR_PCCRX1TO = 0x01000000,
1088 INTR_PCCRX2TO = 0x00800000,
1089 INTR_PCCRX3TO = 0x00400000,
1090 INTR_PCCTXTO = 0x00200000,
1091 INTR_PCCRX0 = 0x00100000,
1092 INTR_PCCRX1 = 0x00080000,
1093 INTR_PCCRX2 = 0x00040000,
1094 INTR_PCCRX3 = 0x00020000,
1095 INTR_PCCTX = 0x00010000,
1096 INTR_RX3EMP = 0x00008000,
1097 INTR_RX2EMP = 0x00004000,
1098 INTR_RX1EMP = 0x00002000,
1099 INTR_RX0EMP = 0x00001000,
1100 INTR_RX3 = 0x00000800,
1101 INTR_RX2 = 0x00000400,
1102 INTR_RX1 = 0x00000200,
1103 INTR_RX0 = 0x00000100,
1104 INTR_TX7 = 0x00000080,
1105 INTR_TX6 = 0x00000040,
1106 INTR_TX5 = 0x00000020,
1107 INTR_TX4 = 0x00000010,
1108 INTR_TX3 = 0x00000008,
1109 INTR_TX2 = 0x00000004,
1110 INTR_TX1 = 0x00000002,
1111 INTR_TX0 = 0x00000001,
1112};
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1113
1114static const u32 INTR_ENABLE = INTR_SWINTR |
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GFT
1115 INTR_TMINTR |
1116 INTR_LINKCH |
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GFT
1117 INTR_PCCRX0TO |
1118 INTR_PCCRX0 |
1119 INTR_PCCTXTO |
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1120 INTR_PCCTX |
1121 INTR_RX0EMP;
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GFT
1122
1123/*
1124 * PCC Control Registers
1125 */
1126enum jme_pccrx_masks {
1127 PCCRXTO_MASK = 0xFFFF0000,
1128 PCCRX_MASK = 0x0000FF00,
1129};
cd0ff491 1130
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GFT
1131enum jme_pcctx_masks {
1132 PCCTXTO_MASK = 0xFFFF0000,
1133 PCCTX_MASK = 0x0000FF00,
1134 PCCTX_QS_MASK = 0x000000FF,
1135};
cd0ff491 1136
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GFT
1137enum jme_pccrx_shifts {
1138 PCCRXTO_SHIFT = 16,
1139 PCCRX_SHIFT = 8,
1140};
cd0ff491 1141
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GFT
1142enum jme_pcctx_shifts {
1143 PCCTXTO_SHIFT = 16,
1144 PCCTX_SHIFT = 8,
1145};
cd0ff491 1146
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GFT
1147enum jme_pcctx_bits {
1148 PCCTXQ0_EN = 0x00000001,
1149 PCCTXQ1_EN = 0x00000002,
1150 PCCTXQ2_EN = 0x00000004,
1151 PCCTXQ3_EN = 0x00000008,
1152 PCCTXQ4_EN = 0x00000010,
1153 PCCTXQ5_EN = 0x00000020,
1154 PCCTXQ6_EN = 0x00000040,
1155 PCCTXQ7_EN = 0x00000080,
1156};
1157
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GFT
1158/*
1159 * Chip Mode Register
1160 */
1161enum jme_chipmode_bit_masks {
1162 CM_FPGAVER_MASK = 0xFFFF0000,
58c92f28 1163 CM_CHIPREV_MASK = 0x0000FF00,
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GFT
1164 CM_CHIPMODE_MASK = 0x0000000F,
1165};
cd0ff491 1166
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1167enum jme_chipmode_shifts {
1168 CM_FPGAVER_SHIFT = 16,
58c92f28 1169 CM_CHIPREV_SHIFT = 8,
cdcdc9eb 1170};
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GFT
1171
1172/*
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GFT
1173 * Aggressive Power Mode Control
1174 */
1175enum jme_apmc_bits {
1176 JME_APMC_PCIE_SD_EN = 0x40000000,
1177 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1178 JME_APMC_EPIEN = 0x04000000,
1179 JME_APMC_EPIEN_CTRL = 0x03000000,
1180};
1181
1182enum jme_apmc_values {
1183 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1184 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1185};
1186
1187#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1188
1189#ifdef REG_DEBUG
1190static char *MAC_REG_NAME[] = {
1191 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1192 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1193 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1194 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1195 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1196 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1197 "JME_PMCS"};
7ee473a3 1198
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GFT
1199static char *PE_REG_NAME[] = {
1200 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1201 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1202 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1203 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1204 "JME_SMBCSR", "JME_SMBINTF"};
7ee473a3 1205
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GFT
1206static char *MISC_REG_NAME[] = {
1207 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1208 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1209 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1210 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1211 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1212 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1213 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1214 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1215 "JME_PCCSRX0"};
7ee473a3 1216
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GFT
1217static inline void reg_dbg(const struct jme_adapter *jme,
1218 const char *msg, u32 val, u32 reg)
1219{
1220 const char *regname;
58c92f28 1221 switch (reg & 0xF00) {
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GFT
1222 case 0x000:
1223 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1224 break;
1225 case 0x400:
1226 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1227 break;
1228 case 0x800:
58c92f28 1229 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
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GFT
1230 break;
1231 default:
1232 regname = PE_REG_NAME[0];
1233 }
1234 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1235 msg, val, regname);
1236}
1237#else
1238static inline void reg_dbg(const struct jme_adapter *jme,
1239 const char *msg, u32 val, u32 reg) {}
1240#endif
1241
1242/*
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GFT
1243 * Read/Write MMaped I/O Registers
1244 */
cd0ff491 1245static inline u32 jread32(struct jme_adapter *jme, u32 reg)
d7699f87 1246{
cd0ff491 1247 return readl(jme->regs + reg);
d7699f87 1248}
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GFT
1249
1250static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
d7699f87 1251{
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GFT
1252 reg_dbg(jme, "REG WRITE", val, reg);
1253 writel(val, jme->regs + reg);
1254 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
d7699f87 1255}
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GFT
1256
1257static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
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GFT
1258{
1259 /*
1260 * Read after write should cause flush
1261 */
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GFT
1262 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1263 writel(val, jme->regs + reg);
1264 readl(jme->regs + reg);
1265 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
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GFT
1266}
1267
1268/*
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GFT
1269 * PHY Regs
1270 */
1271enum jme_phy_reg17_bit_masks {
1272 PREG17_SPEED = 0xC000,
1273 PREG17_DUPLEX = 0x2000,
1274 PREG17_SPDRSV = 0x0800,
1275 PREG17_LNKUP = 0x0400,
1276 PREG17_MDI = 0x0040,
1277};
cd0ff491 1278
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GFT
1279enum jme_phy_reg17_vals {
1280 PREG17_SPEED_10M = 0x0000,
1281 PREG17_SPEED_100M = 0x4000,
1282 PREG17_SPEED_1000M = 0x8000,
1283};
cd0ff491 1284
8d27293f 1285#define BMSR_ANCOMP 0x0020
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GFT
1286
1287/*
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GFT
1288 * Workaround
1289 */
1290static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1291{
1292 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1293}
1294
1295/*
cd0ff491 1296 * Function prototypes
d7699f87 1297 */
d7699f87 1298static int jme_set_settings(struct net_device *netdev,
cd0ff491 1299 struct ethtool_cmd *ecmd);
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GFT
1300static void jme_set_multi(struct net_device *netdev);
1301
cd0ff491 1302#endif