Import jme 0.6 source
[jme.git] / jme.h
CommitLineData
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
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7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
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9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#include <linux/version.h>
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25
26#define DRV_NAME "jme"
79ce639c 27#define DRV_VERSION "0.6"
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28#define PFX DRV_NAME ": "
29
30#ifdef DEBUG
4330c2f2 31#define dprintk(devname, fmt, args...) \
8c198884 32 printk(KERN_DEBUG "%s: " fmt, devname, ## args)
d7699f87 33#else
4330c2f2 34#define dprintk(devname, fmt, args...)
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35#endif
36
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37#ifdef TX_DEBUG
38#define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
39#else
40#define tx_dbg(args...)
41#endif
42
43#ifdef RX_DEBUG
44#define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
45#else
46#define rx_dbg(args...)
47#endif
48
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49#ifdef CSUM_DEBUG
50#define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
51#else
52#define csum_dbg(args...)
53#endif
54
4330c2f2 55#define jprintk(devname, fmt, args...) \
8c198884 56 printk(KERN_INFO "%s: " fmt, devname, ## args)
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57
58#define jeprintk(devname, fmt, args...) \
8c198884 59 printk(KERN_ERR "%s: " fmt, devname, ## args)
4330c2f2 60
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61#define DEFAULT_MSG_ENABLE \
62 (NETIF_MSG_DRV | \
63 NETIF_MSG_PROBE | \
64 NETIF_MSG_LINK | \
65 NETIF_MSG_TIMER | \
66 NETIF_MSG_RX_ERR | \
67 NETIF_MSG_TX_ERR)
68
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69#define PCI_CONF_DCSR_MRRS 0x59
70#define PCI_CONF_DCSR_MRRS_MASK 0x70
71enum pci_conf_dcsr_mrrs_vals {
72 MRRS_128B = 0x00,
73 MRRS_256B = 0x10,
74 MRRS_512B = 0x20,
75 MRRS_1024B = 0x30,
76 MRRS_2048B = 0x40,
77 MRRS_4096B = 0x50,
78};
d7699f87 79
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80#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
81#define MIN_ETHERNET_PACKET_SIZE 60
82
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83enum dynamic_pcc_values {
84 PCC_P1 = 1,
85 PCC_P2 = 2,
86 PCC_P3 = 3,
87
88 PCC_P1_TO = 1,
89 PCC_P2_TO = 250,
90 PCC_P3_TO = 1000,
91
92 PCC_P1_CNT = 1,
93 PCC_P2_CNT = 64,
94 PCC_P3_CNT = 255,
95};
96struct dynpcc_info {
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97 unsigned long last_bytes;
98 unsigned long last_pkts;
79ce639c 99 unsigned long intr_cnt;
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100 unsigned char cur;
101 unsigned char attempt;
102 unsigned char cnt;
103};
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104#define PCC_INTERVAL_US 100000
105#define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US))
3bf61c55 106#define PCC_P3_THRESHOLD 3*1024*1024
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107#define PCC_P2_THRESHOLD 800
108#define PCC_INTR_THRESHOLD 800
109#define PCC_TX_TO 100
110#define PCC_TX_CNT 16
3bf61c55 111
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112/*
113 * TX/RX Descriptors
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114 *
115 * TX/RX Ring DESC Count Must be multiple of 16
116 * RX Ring DESC Count Must be <= 1024
d7699f87 117 */
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118#define RING_DESC_NR 512 /* Must be power of 2 */
119#define RING_DESC_ALIGN 16 /* Descriptor alignment */
120
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121#define TX_DESC_SIZE 16
122#define TX_RING_NR 8
123#define TX_RING_ALLOC_SIZE (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE
124#define TX_RING_SIZE (RING_DESC_NR * TX_DESC_SIZE)
125
3bf61c55 126struct txdesc {
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127 union {
128 __u8 all[16];
129 __u32 dw[4];
130 struct {
131 /* DW0 */
132 __u16 vlan;
133 __u8 rsv1;
134 __u8 flags;
135
136 /* DW1 */
137 __u16 datalen;
138 __u16 mss;
139
140 /* DW2 */
141 __u16 pktsize;
142 __u16 rsv2;
143
144 /* DW3 */
145 __u32 bufaddr;
146 } desc1;
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147 struct {
148 /* DW0 */
149 __u16 rsv1;
150 __u8 rsv2;
151 __u8 flags;
152
153 /* DW1 */
154 __u16 datalen;
155 __u16 rsv3;
156
157 /* DW2 */
158 __u32 bufaddrh;
159
160 /* DW3 */
161 __u32 bufaddrl;
162 } desc2;
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163 struct {
164 /* DW0 */
165 __u8 ehdrsz;
166 __u8 rsv1;
167 __u8 rsv2;
168 __u8 flags;
169
170 /* DW1 */
171 __u16 trycnt;
172 __u16 segcnt;
173
174 /* DW2 */
175 __u16 pktsz;
176 __u16 rsv3;
177
178 /* DW3 */
179 __u32 bufaddrl;
180 } descwb;
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181 };
182};
8c198884 183enum jme_txdesc_flags_bits {
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184 TXFLAG_OWN = 0x80,
185 TXFLAG_INT = 0x40,
3bf61c55 186 TXFLAG_64BIT = 0x20,
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187 TXFLAG_TCPCS = 0x10,
188 TXFLAG_UDPCS = 0x08,
189 TXFLAG_IPCS = 0x04,
190 TXFLAG_LSEN = 0x02,
191 TXFLAG_TAGON = 0x01,
192};
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193enum jme_rxdescwb_flags_bits {
194 TXWBFLAG_OWN = 0x80,
195 TXWBFLAG_INT = 0x40,
196 TXWBFLAG_TMOUT = 0x20,
197 TXWBFLAG_TRYOUT = 0x10,
198 TXWBFLAG_COL = 0x08,
199
200 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
201 TXWBFLAG_TRYOUT |
202 TXWBFLAG_COL,
203};
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204
205
206#define RX_DESC_SIZE 16
207#define RX_RING_NR 4
208#define RX_RING_ALLOC_SIZE (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE
209#define RX_RING_SIZE (RING_DESC_NR * RX_DESC_SIZE)
210
211#define RX_BUF_DMA_ALIGN 8
3bf61c55 212#define RX_PREPAD_SIZE 10
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213#define ETH_CRC_LEN 2
214#define RX_VLANHDR_LEN 2
215#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
216 ETH_HLEN + \
217 ETH_CRC_LEN + \
218 RX_VLANHDR_LEN + \
219 RX_BUF_DMA_ALIGN)
d7699f87 220
3bf61c55 221struct rxdesc {
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222 union {
223 __u8 all[16];
224 __le32 dw[4];
225 struct {
226 /* DW0 */
227 __le16 rsv2;
228 __u8 rsv1;
229 __u8 flags;
230
231 /* DW1 */
232 __le16 datalen;
233 __le16 wbcpl;
234
235 /* DW2 */
236 __le32 bufaddrh;
237
238 /* DW3 */
239 __le32 bufaddrl;
240 } desc1;
241 struct {
242 /* DW0 */
243 __le16 vlan;
244 __le16 flags;
245
246 /* DW1 */
247 __le16 framesize;
4330c2f2 248 __u8 errstat;
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249 __u8 desccnt;
250
251 /* DW2 */
252 __le32 rsshash;
253
254 /* DW3 */
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255 __u8 hashfun;
256 __u8 hashtype;
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257 __le16 resrv;
258 } descwb;
259 };
260};
261enum jme_rxdesc_flags_bits {
262 RXFLAG_OWN = 0x80,
263 RXFLAG_INT = 0x40,
264 RXFLAG_64BIT = 0x20,
265};
266enum jme_rxwbdesc_flags_bits {
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267 RXWBFLAG_OWN = 0x8000,
268 RXWBFLAG_INT = 0x4000,
269 RXWBFLAG_MF = 0x2000,
270 RXWBFLAG_64BIT = 0x2000,
271 RXWBFLAG_TCPON = 0x1000,
272 RXWBFLAG_UDPON = 0x0800,
273 RXWBFLAG_IPCS = 0x0400,
274 RXWBFLAG_TCPCS = 0x0200,
275 RXWBFLAG_UDPCS = 0x0100,
276 RXWBFLAG_TAGON = 0x0080,
277 RXWBFLAG_IPV4 = 0x0040,
278 RXWBFLAG_IPV6 = 0x0020,
279 RXWBFLAG_PAUSE = 0x0010,
280 RXWBFLAG_MAGIC = 0x0008,
281 RXWBFLAG_WAKEUP = 0x0004,
282 RXWBFLAG_DEST = 0x0003,
283 RXWBFLAG_DEST_UNI = 0x0001,
284 RXWBFLAG_DEST_MUL = 0x0002,
285 RXWBFLAG_DEST_BRO = 0x0003,
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286};
287enum jme_rxwbdesc_desccnt_mask {
288 RXWBDCNT_WBCPL = 0x80,
289 RXWBDCNT_DCNT = 0x7F,
290};
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291enum jme_rxwbdesc_errstat_bits {
292 RXWBERR_LIMIT = 0x80,
293 RXWBERR_MIIER = 0x40,
294 RXWBERR_NIBON = 0x20,
295 RXWBERR_COLON = 0x10,
296 RXWBERR_ABORT = 0x08,
297 RXWBERR_SHORT = 0x04,
298 RXWBERR_OVERUN = 0x02,
299 RXWBERR_CRCERR = 0x01,
300 RXWBERR_ALLERR = 0xFF,
301};
302
303struct jme_buffer_info {
304 struct sk_buff *skb;
305 dma_addr_t mapping;
306 int len;
3bf61c55 307 int nr_desc;
4330c2f2 308};
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309
310struct jme_ring {
4330c2f2 311 void* alloc; /* pointer to allocated memory */
3bf61c55 312 volatile void* desc; /* pointer to ring memory */
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313 dma_addr_t dmaalloc; /* phys address of ring alloc */
314 dma_addr_t dma; /* phys address for ring dma */
315
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316 /* Buffer information corresponding to each descriptor */
317 struct jme_buffer_info bufinf[RING_DESC_NR];
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318
319 u16 next_to_use;
320 u16 next_to_clean;
3bf61c55 321
79ce639c 322 atomic_t nr_free;
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323};
324
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325#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
326#define NET_STAT(priv) priv->stats
327#define NETDEV_GET_STATS(netdev, fun_ptr) \
328 netdev->get_stats = fun_ptr
329#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
330#else
331#define NET_STAT(priv) priv->dev->stats
332#define NETDEV_GET_STATS(netdev, fun_ptr)
333#define DECLARE_NET_DEVICE_STATS
334#endif
335
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336/*
337 * Jmac Adapter Private data
338 */
4330c2f2 339#define SHADOW_REG_NR 8
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340struct jme_adapter {
341 struct pci_dev *pdev;
342 struct net_device *dev;
343 void __iomem *regs;
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344 dma_addr_t shadow_dma;
345 __u32 *shadow_regs;
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346 struct mii_if_info mii_if;
347 struct jme_ring rxring[RX_RING_NR];
348 struct jme_ring txring[TX_RING_NR];
d7699f87 349 spinlock_t phy_lock;
fcf45b4c 350 spinlock_t macaddr_lock;
8c198884 351 spinlock_t rxmcs_lock;
fcf45b4c 352 struct tasklet_struct rxempty_task;
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353 struct tasklet_struct rxclean_task;
354 struct tasklet_struct txclean_task;
355 struct tasklet_struct linkch_task;
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356 struct tasklet_struct pcc_task;
357 __u32 flags;
4330c2f2 358 __u32 reg_txcs;
8c198884 359 __u32 reg_txpfc;
79ce639c 360 __u32 reg_rxcs;
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361 __u32 reg_rxmcs;
362 __u32 reg_ghc;
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363 __u32 phylink;
364 __u8 mrrs;
79ce639c 365 unsigned int oldmtu;
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366 struct dynpcc_info dpi;
367 atomic_t intr_sem;
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368 atomic_t link_changing;
369 atomic_t tx_cleaning;
370 atomic_t rx_cleaning;
3bf61c55 371 DECLARE_NET_DEVICE_STATS
d7699f87 372};
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373enum shadow_reg_val {
374 SHADOW_IEVE = 0,
375};
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376enum jme_flags_bits {
377 JME_FLAG_MSI = 0x00000001,
8c198884 378};
fcf45b4c 379#define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */
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380#define TX_TIMEOUT (5*HZ)
381
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382
383/*
384 * MMaped I/O Resters
385 */
386enum jme_iomap_offsets {
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387 JME_MAC = 0x0000,
388 JME_PHY = 0x0400,
d7699f87 389 JME_MISC = 0x0800,
4330c2f2 390 JME_RSS = 0x0C00,
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391};
392
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393enum jme_iomap_lens {
394 JME_MAC_LEN = 0x80,
395 JME_PHY_LEN = 0x58,
396 JME_MISC_LEN = 0x98,
397 JME_RSS_LEN = 0xFF,
398};
399
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400enum jme_iomap_regs {
401 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
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402 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
403 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
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404 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
405 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
406 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
407 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
408 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
409
410 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
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411 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
412 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
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413 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
414 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
415 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
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416 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
417 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
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418 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
419 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
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420 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
421 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
422
423 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
424 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
425 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
426
427
3bf61c55 428 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
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429 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
430 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
431
432
79ce639c 433 JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */
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434 JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */
435 JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */
d7699f87 436 JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */
3bf61c55 437 JME_IREQ = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
d7699f87 438 JME_IENS = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
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439 JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
440 JME_PCCRX0 = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
441 JME_PCCTX = JME_MISC| 0x40, /* PCC Control for TX Queues */
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442 JME_SHBA_HI = JME_MISC| 0x48, /* Shadow Register Base HI */
443 JME_SHBA_LO = JME_MISC| 0x4C, /* Shadow Register Base LO */
3bf61c55 444 JME_PCCSRX0 = JME_MISC| 0x80, /* PCC Status of RX0 */
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445};
446
447/*
448 * TX Control/Status Bits
449 */
450enum jme_txcs_bits {
451 TXCS_QUEUE7S = 0x00008000,
452 TXCS_QUEUE6S = 0x00004000,
453 TXCS_QUEUE5S = 0x00002000,
454 TXCS_QUEUE4S = 0x00001000,
455 TXCS_QUEUE3S = 0x00000800,
456 TXCS_QUEUE2S = 0x00000400,
457 TXCS_QUEUE1S = 0x00000200,
458 TXCS_QUEUE0S = 0x00000100,
459 TXCS_FIFOTH = 0x000000C0,
460 TXCS_DMASIZE = 0x00000030,
461 TXCS_BURST = 0x00000004,
462 TXCS_ENABLE = 0x00000001,
463};
464enum jme_txcs_value {
465 TXCS_FIFOTH_16QW = 0x000000C0,
466 TXCS_FIFOTH_12QW = 0x00000080,
467 TXCS_FIFOTH_8QW = 0x00000040,
468 TXCS_FIFOTH_4QW = 0x00000000,
469
470 TXCS_DMASIZE_64B = 0x00000000,
471 TXCS_DMASIZE_128B = 0x00000010,
472 TXCS_DMASIZE_256B = 0x00000020,
473 TXCS_DMASIZE_512B = 0x00000030,
474
475 TXCS_SELECT_QUEUE0 = 0x00000000,
476 TXCS_SELECT_QUEUE1 = 0x00010000,
477 TXCS_SELECT_QUEUE2 = 0x00020000,
478 TXCS_SELECT_QUEUE3 = 0x00030000,
479 TXCS_SELECT_QUEUE4 = 0x00040000,
480 TXCS_SELECT_QUEUE5 = 0x00050000,
481 TXCS_SELECT_QUEUE6 = 0x00060000,
482 TXCS_SELECT_QUEUE7 = 0x00070000,
483
484 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
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485 TXCS_BURST,
486};
8c198884 487#define JME_TX_DISABLE_TIMEOUT 5 /* 5 msec */
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488
489/*
490 * TX MAC Control/Status Bits
491 */
492enum jme_txmcs_bit_masks {
493 TXMCS_IFG2 = 0xC0000000,
494 TXMCS_IFG1 = 0x30000000,
495 TXMCS_TTHOLD = 0x00000300,
496 TXMCS_FBURST = 0x00000080,
497 TXMCS_CARRIEREXT = 0x00000040,
498 TXMCS_DEFER = 0x00000020,
499 TXMCS_BACKOFF = 0x00000010,
500 TXMCS_CARRIERSENSE = 0x00000008,
501 TXMCS_COLLISION = 0x00000004,
502 TXMCS_CRC = 0x00000002,
503 TXMCS_PADDING = 0x00000001,
504};
505enum jme_txmcs_values {
506 TXMCS_IFG2_6_4 = 0x00000000,
507 TXMCS_IFG2_8_5 = 0x40000000,
508 TXMCS_IFG2_10_6 = 0x80000000,
509 TXMCS_IFG2_12_7 = 0xC0000000,
510
511 TXMCS_IFG1_8_4 = 0x00000000,
512 TXMCS_IFG1_12_6 = 0x10000000,
513 TXMCS_IFG1_16_8 = 0x20000000,
514 TXMCS_IFG1_20_10 = 0x30000000,
515
516 TXMCS_TTHOLD_1_8 = 0x00000000,
517 TXMCS_TTHOLD_1_4 = 0x00000100,
518 TXMCS_TTHOLD_1_2 = 0x00000200,
519 TXMCS_TTHOLD_FULL = 0x00000300,
520
521 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
522 TXMCS_IFG1_16_8 |
523 TXMCS_TTHOLD_FULL |
524 TXMCS_DEFER |
525 TXMCS_CRC |
526 TXMCS_PADDING,
527};
528
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529enum jme_txpfc_bits_masks {
530 TXPFC_VLAN_TAG = 0xFFFF0000,
531 TXPFC_VLAN_EN = 0x00008000,
532 TXPFC_PF_EN = 0x00000001,
533};
534
535enum jme_txtrhd_bits_masks {
536 TXTRHD_TXPEN = 0x80000000,
537 TXTRHD_TXP = 0x7FFFFF00,
538 TXTRHD_TXREN = 0x00000080,
539 TXTRHD_TXRL = 0x0000007F,
540};
541enum jme_txtrhd_shifts {
542 TXTRHD_TXP_SHIFT = 8,
543 TXTRHD_TXRL_SHIFT = 0,
544};
545
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546
547/*
548 * RX Control/Status Bits
549 */
4330c2f2 550enum jme_rxcs_bit_masks {
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551 /* FIFO full threshold for transmitting Tx Pause Packet */
552 RXCS_FIFOTHTP = 0x30000000,
553 /* FIFO threshold for processing next packet */
554 RXCS_FIFOTHNP = 0x0C000000,
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555 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
556 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
557 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
558 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
559 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
560 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
561 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
562 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
563 RXCS_QST = 0x00000004, /* Receive queue start */
564 RXCS_SUSPEND = 0x00000002,
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565 RXCS_ENABLE = 0x00000001,
566};
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567enum jme_rxcs_values {
568 RXCS_FIFOTHTP_16T = 0x00000000,
569 RXCS_FIFOTHTP_32T = 0x10000000,
570 RXCS_FIFOTHTP_64T = 0x20000000,
571 RXCS_FIFOTHTP_128T = 0x30000000,
572
573 RXCS_FIFOTHNP_16QW = 0x00000000,
574 RXCS_FIFOTHNP_32QW = 0x04000000,
575 RXCS_FIFOTHNP_64QW = 0x08000000,
576 RXCS_FIFOTHNP_128QW = 0x0C000000,
577
578 RXCS_DMAREQSZ_16B = 0x00000000,
579 RXCS_DMAREQSZ_32B = 0x01000000,
580 RXCS_DMAREQSZ_64B = 0x02000000,
581 RXCS_DMAREQSZ_128B = 0x03000000,
582
583 RXCS_QUEUESEL_Q0 = 0x00000000,
584 RXCS_QUEUESEL_Q1 = 0x00010000,
585 RXCS_QUEUESEL_Q2 = 0x00020000,
586 RXCS_QUEUESEL_Q3 = 0x00030000,
587
588 RXCS_RETRYGAP_256ns = 0x00000000,
589 RXCS_RETRYGAP_512ns = 0x00001000,
590 RXCS_RETRYGAP_1024ns = 0x00002000,
591 RXCS_RETRYGAP_2048ns = 0x00003000,
592 RXCS_RETRYGAP_4096ns = 0x00004000,
593 RXCS_RETRYGAP_8192ns = 0x00005000,
594 RXCS_RETRYGAP_16384ns = 0x00006000,
595 RXCS_RETRYGAP_32768ns = 0x00007000,
596
597 RXCS_RETRYCNT_0 = 0x00000000,
598 RXCS_RETRYCNT_4 = 0x00000100,
599 RXCS_RETRYCNT_8 = 0x00000200,
600 RXCS_RETRYCNT_12 = 0x00000300,
601 RXCS_RETRYCNT_16 = 0x00000400,
602 RXCS_RETRYCNT_20 = 0x00000500,
603 RXCS_RETRYCNT_24 = 0x00000600,
604 RXCS_RETRYCNT_28 = 0x00000700,
605 RXCS_RETRYCNT_32 = 0x00000800,
606 RXCS_RETRYCNT_36 = 0x00000900,
607 RXCS_RETRYCNT_40 = 0x00000A00,
608 RXCS_RETRYCNT_44 = 0x00000B00,
609 RXCS_RETRYCNT_48 = 0x00000C00,
610 RXCS_RETRYCNT_52 = 0x00000D00,
611 RXCS_RETRYCNT_56 = 0x00000E00,
612 RXCS_RETRYCNT_60 = 0x00000F00,
613
614 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
79ce639c 615 RXCS_FIFOTHNP_128QW |
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GFT
616 RXCS_DMAREQSZ_128B |
617 RXCS_RETRYGAP_256ns |
618 RXCS_RETRYCNT_32,
619};
8c198884 620#define JME_RX_DISABLE_TIMEOUT 5 /* 5 msec */
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621
622/*
623 * RX MAC Control/Status Bits
624 */
625enum jme_rxmcs_bits {
626 RXMCS_ALLFRAME = 0x00000800,
627 RXMCS_BRDFRAME = 0x00000400,
628 RXMCS_MULFRAME = 0x00000200,
629 RXMCS_UNIFRAME = 0x00000100,
630 RXMCS_ALLMULFRAME = 0x00000080,
631 RXMCS_MULFILTERED = 0x00000040,
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GFT
632 RXMCS_RXCOLLDEC = 0x00000020,
633 RXMCS_FLOWCTRL = 0x00000008,
634 RXMCS_VTAGRM = 0x00000004,
635 RXMCS_PREPAD = 0x00000002,
636 RXMCS_CHECKSUM = 0x00000001,
8c198884
GFT
637
638 RXMCS_DEFAULT = RXMCS_VTAGRM |
639 RXMCS_PREPAD |
640 RXMCS_FLOWCTRL |
641 RXMCS_CHECKSUM,
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642};
643
644/*
645 * SMI Related definitions
646 */
647enum jme_smi_bit_mask
648{
649 SMI_DATA_MASK = 0xFFFF0000,
650 SMI_REG_ADDR_MASK = 0x0000F800,
651 SMI_PHY_ADDR_MASK = 0x000007C0,
652 SMI_OP_WRITE = 0x00000020,
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GFT
653 /* Set to 1, after req done it'll be cleared to 0 */
654 SMI_OP_REQ = 0x00000010,
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655 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
656 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
657 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
658 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
659};
660enum jme_smi_bit_shift
661{
662 SMI_DATA_SHIFT = 16,
663 SMI_REG_ADDR_SHIFT = 11,
664 SMI_PHY_ADDR_SHIFT = 6,
665};
666__always_inline __u32 smi_reg_addr(int x)
667{
668 return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
669}
670__always_inline __u32 smi_phy_addr(int x)
671{
672 return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
673}
674#define JME_PHY_TIMEOUT 1000 /* 1000 usec */
675
676/*
677 * Global Host Control
678 */
679enum jme_ghc_bit_mask {
680 GHC_SWRST = 0x40000000,
681 GHC_DPX = 0x00000040,
682 GHC_SPEED = 0x00000030,
683 GHC_LINK_POLL = 0x00000001,
684};
685enum jme_ghc_speed_val {
686 GHC_SPEED_10M = 0x00000010,
687 GHC_SPEED_100M = 0x00000020,
688 GHC_SPEED_1000M = 0x00000030,
689};
690
691/*
3bf61c55 692 * Giga PHY Status Registers
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693 */
694enum jme_phy_link_bit_mask {
695 PHY_LINK_SPEED_MASK = 0x0000C000,
696 PHY_LINK_DUPLEX = 0x00002000,
697 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
698 PHY_LINK_UP = 0x00000400,
699 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
fcf45b4c 700 PHY_LINK_MDI_STAT = 0x00000040,
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GFT
701};
702enum jme_phy_link_speed_val {
703 PHY_LINK_SPEED_10M = 0x00000000,
704 PHY_LINK_SPEED_100M = 0x00004000,
705 PHY_LINK_SPEED_1000M = 0x00008000,
706};
fcf45b4c 707#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
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708
709/*
710 * SMB Control and Status
711 */
79ce639c 712enum jme_smbcsr_bit_mask {
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GFT
713 SMBCSR_CNACK = 0x00020000,
714 SMBCSR_RELOAD = 0x00010000,
715 SMBCSR_EEPROMD = 0x00000020,
716};
717#define JME_SMB_TIMEOUT 10 /* 10 msec */
718
79ce639c
GFT
719/*
720 * Timer Control/Status Register
721 */
722enum jme_tmcsr_bit_masks {
723 TMCSR_SWIT = 0x80000000,
724 TMCSR_EN = 0x01000000,
725 TMCSR_CNT = 0x00FFFFFF,
726};
727
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GFT
728
729/*
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730 * General Purpost REG-0
731 */
732enum jme_gpreg0_masks {
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GFT
733 GPREG0_DISSH = 0xFF000000,
734 GPREG0_PCIRLMT = 0x00300000,
735 GPREG0_PCCNOMUTCLR = 0x00040000,
736 GPREG0_PCCTMR = 0x00000300,
737 GPREG0_PHYADDR = 0x0000001F,
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GFT
738};
739enum jme_gpreg0_vals {
740 GPREG0_DISSH_DW7 = 0x80000000,
741 GPREG0_DISSH_DW6 = 0x40000000,
742 GPREG0_DISSH_DW5 = 0x20000000,
743 GPREG0_DISSH_DW4 = 0x10000000,
744 GPREG0_DISSH_DW3 = 0x08000000,
745 GPREG0_DISSH_DW2 = 0x04000000,
746 GPREG0_DISSH_DW1 = 0x02000000,
747 GPREG0_DISSH_DW0 = 0x01000000,
748 GPREG0_DISSH_ALL = 0xFF000000,
749
750 GPREG0_PCIRLMT_8 = 0x00000000,
751 GPREG0_PCIRLMT_6 = 0x00100000,
752 GPREG0_PCIRLMT_5 = 0x00200000,
753 GPREG0_PCIRLMT_4 = 0x00300000,
754
755 GPREG0_PCCTMR_16ns = 0x00000000,
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GFT
756 GPREG0_PCCTMR_256ns = 0x00000100,
757 GPREG0_PCCTMR_1us = 0x00000200,
758 GPREG0_PCCTMR_1ms = 0x00000300,
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GFT
759
760 GPREG0_PHYADDR_1 = 0x00000001,
761
762 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
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GFT
763 GPREG0_PCCNOMUTCLR |
764 GPREG0_PCCTMR_1us |
765 GPREG0_PHYADDR_1,
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GFT
766};
767
768/*
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769 * Interrupt Status Bits
770 */
771enum jme_interrupt_bits
772{
773 INTR_SWINTR = 0x80000000,
774 INTR_TMINTR = 0x40000000,
775 INTR_LINKCH = 0x20000000,
776 INTR_PAUSERCV = 0x10000000,
777 INTR_MAGICRCV = 0x08000000,
778 INTR_WAKERCV = 0x04000000,
779 INTR_PCCRX0TO = 0x02000000,
780 INTR_PCCRX1TO = 0x01000000,
781 INTR_PCCRX2TO = 0x00800000,
782 INTR_PCCRX3TO = 0x00400000,
783 INTR_PCCTXTO = 0x00200000,
784 INTR_PCCRX0 = 0x00100000,
785 INTR_PCCRX1 = 0x00080000,
786 INTR_PCCRX2 = 0x00040000,
787 INTR_PCCRX3 = 0x00020000,
788 INTR_PCCTX = 0x00010000,
789 INTR_RX3EMP = 0x00008000,
790 INTR_RX2EMP = 0x00004000,
791 INTR_RX1EMP = 0x00002000,
792 INTR_RX0EMP = 0x00001000,
793 INTR_RX3 = 0x00000800,
794 INTR_RX2 = 0x00000400,
795 INTR_RX1 = 0x00000200,
796 INTR_RX0 = 0x00000100,
797 INTR_TX7 = 0x00000080,
798 INTR_TX6 = 0x00000040,
799 INTR_TX5 = 0x00000020,
800 INTR_TX4 = 0x00000010,
801 INTR_TX3 = 0x00000008,
802 INTR_TX2 = 0x00000004,
803 INTR_TX1 = 0x00000002,
804 INTR_TX0 = 0x00000001,
805};
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GFT
806static const __u32 INTR_ENABLE = INTR_SWINTR |
807 INTR_TMINTR |
808 INTR_LINKCH |
d7699f87 809 INTR_RX0EMP |
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GFT
810 INTR_PCCRX0TO |
811 INTR_PCCRX0 |
812 INTR_PCCTXTO |
813 INTR_PCCTX;
814
815/*
816 * PCC Control Registers
817 */
818enum jme_pccrx_masks {
819 PCCRXTO_MASK = 0xFFFF0000,
820 PCCRX_MASK = 0x0000FF00,
821};
822enum jme_pcctx_masks {
823 PCCTXTO_MASK = 0xFFFF0000,
824 PCCTX_MASK = 0x0000FF00,
825 PCCTX_QS_MASK = 0x000000FF,
826};
827enum jme_pccrx_shifts {
828 PCCRXTO_SHIFT = 16,
829 PCCRX_SHIFT = 8,
830};
831enum jme_pcctx_shifts {
832 PCCTXTO_SHIFT = 16,
833 PCCTX_SHIFT = 8,
834};
835enum jme_pcctx_bits {
836 PCCTXQ0_EN = 0x00000001,
837 PCCTXQ1_EN = 0x00000002,
838 PCCTXQ2_EN = 0x00000004,
839 PCCTXQ3_EN = 0x00000008,
840 PCCTXQ4_EN = 0x00000010,
841 PCCTXQ5_EN = 0x00000020,
842 PCCTXQ6_EN = 0x00000040,
843 PCCTXQ7_EN = 0x00000080,
844};
845
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GFT
846
847/*
4330c2f2
GFT
848 * Shadow base address register bits
849 */
850enum jme_shadow_base_address_bits {
851 SHBA_POSTEN = 0x1,
852};
853
854/*
d7699f87
GFT
855 * Read/Write MMaped I/O Registers
856 */
857__always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
858{
79ce639c 859 return le32_to_cpu(readl((__u8*)jme->regs + reg));
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GFT
860}
861__always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
862{
79ce639c 863 writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
d7699f87
GFT
864}
865__always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
866{
867 /*
868 * Read after write should cause flush
869 */
79ce639c
GFT
870 writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
871 readl((__u8*)jme->regs + reg);
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GFT
872}
873
874/*
875 * Function prototypes for ethtool
876 */
877static void jme_get_drvinfo(struct net_device *netdev,
878 struct ethtool_drvinfo *info);
879static int jme_get_settings(struct net_device *netdev,
880 struct ethtool_cmd *ecmd);
881static int jme_set_settings(struct net_device *netdev,
882 struct ethtool_cmd *ecmd);
883static u32 jme_get_link(struct net_device *netdev);
884
885
886/*
887 * Function prototypes for netdev
888 */
889static int jme_open(struct net_device *netdev);
890static int jme_close(struct net_device *netdev);
891static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
892static int jme_set_macaddr(struct net_device *netdev, void *p);
893static void jme_set_multi(struct net_device *netdev);
894
fcf45b4c 895