jme: Advance driver version
[jme.git] / jme.h
CommitLineData
4330c2f2
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
4330c2f2 7 *
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8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
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10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
cd0ff491 25#ifndef __JME_H_INCLUDED__
3b70a6fa 26#define __JME_H_INCLUDED__
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27
28#define DRV_NAME "jme"
b34adbb0 29#define DRV_VERSION "1.0.8-jmmod"
cd0ff491 30#define PFX DRV_NAME ": "
d7699f87 31
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32#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
33#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
8d27293f 34
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35/*
36 * Message related definitions
37 */
38#define JME_DEF_MSG_ENABLE \
39 (NETIF_MSG_PROBE | \
40 NETIF_MSG_LINK | \
41 NETIF_MSG_RX_ERR | \
42 NETIF_MSG_TX_ERR | \
43 NETIF_MSG_HW)
44
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45#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
46#define pr_err(fmt, arg...) \
47 printk(KERN_ERR fmt, ##arg)
48#endif
49#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
50#define netdev_err(netdev, fmt, arg...) \
51 pr_err(fmt, ##arg)
52#endif
d7699f87 53
3bf61c55 54#ifdef TX_DEBUG
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55#define tx_dbg(priv, fmt, args...) \
56 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
3bf61c55 57#else
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58#define tx_dbg(priv, fmt, args...) \
59do { \
60 if (0) \
61 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
62} while (0)
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63#endif
64
7ca9ebee 65#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
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66#define jme_msg(msglvl, type, priv, fmt, args...) \
67 if (netif_msg_##type(priv)) \
68 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
3bf61c55 69
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70#define msg_probe(priv, fmt, args...) \
71 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
29bdd921 72
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73#define msg_link(priv, fmt, args...) \
74 jme_msg(KERN_INFO, link, priv, fmt, ## args)
79ce639c 75
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76#define msg_intr(priv, fmt, args...) \
77 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
78
79#define msg_rx_err(priv, fmt, args...) \
80 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
b3821cc5 81
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82#define msg_rx_status(priv, fmt, args...) \
83 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
4330c2f2 84
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85#define msg_tx_err(priv, fmt, args...) \
86 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
4330c2f2 87
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88#define msg_tx_done(priv, fmt, args...) \
89 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
d7699f87 90
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91#define msg_tx_queued(priv, fmt, args...) \
92 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
93
94#define msg_hw(priv, fmt, args...) \
95 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
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96
97#define netif_info(priv, type, dev, fmt, args...) \
98 msg_ ## type(priv, fmt, ## args)
99#define netif_err(priv, type, dev, fmt, args...) \
100 msg_ ## type(priv, fmt, ## args)
7ca9ebee 101#endif
cd0ff491 102
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103#ifndef NETIF_F_TSO6
104#define NETIF_F_TSO6 0
105#endif
106#ifndef NETIF_F_IPV6_CSUM
107#define NETIF_F_IPV6_CSUM 0
108#endif
109
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110/*
111 * Extra PCI Configuration space interface
112 */
113#define PCI_DCSR_MRRS 0x59
114#define PCI_DCSR_MRRS_MASK 0x70
115
116enum pci_dcsr_mrrs_vals {
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117 MRRS_128B = 0x00,
118 MRRS_256B = 0x10,
119 MRRS_512B = 0x20,
120 MRRS_1024B = 0x30,
121 MRRS_2048B = 0x40,
122 MRRS_4096B = 0x50,
123};
d7699f87 124
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125#define PCI_SPI 0xB0
126
127enum pci_spi_bits {
128 SPI_EN = 0x10,
129 SPI_MISO = 0x08,
130 SPI_MOSI = 0x04,
131 SPI_SCLK = 0x02,
132 SPI_CS = 0x01,
133};
134
135struct jme_spi_op {
136 void __user *uwbuf;
137 void __user *urbuf;
138 __u8 wn; /* Number of write actions */
139 __u8 rn; /* Number of read actions */
140 __u8 bitn; /* Number of bits per action */
141 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
142 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
143
144 /* Internal use only */
145 u8 *kwbuf;
146 u8 *krbuf;
147 u8 sr;
148 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
149};
79ce639c 150
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151enum jme_spi_op_bits {
152 SPI_MODE_CPHA = 0x01,
153 SPI_MODE_CPOL = 0x02,
154 SPI_MODE_DUP = 0x80,
155};
156
157#define HALF_US 500 /* 500 ns */
158#define JMESPIIOCTL SIOCDEVPRIVATE
159
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160#define PCI_PRIV_PE1 0xE4
161
162enum pci_priv_pe1_bit_masks {
163 PE1_ASPMSUPRT = 0x00000003, /*
164 * RW:
165 * Aspm_support[1:0]
166 * (R/W Port of 5C[11:10])
167 */
168 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
169 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
170 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
171 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
172 PE1_GPREG0 = 0x0000FF00, /*
173 * SRW:
174 * Cfg_gp_reg0
175 * [7:6] phy_giga BG control
176 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
177 * [4:0] Reserved
178 */
179 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
180 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
181 PE1_REVID = 0xFF000000, /* RO: Rev ID */
182};
183
184enum pci_priv_pe1_values {
185 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
186 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
187 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
188 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
189};
190
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191/*
192 * Dynamic(adaptive)/Static PCC values
193 */
3bf61c55 194enum dynamic_pcc_values {
192570e0 195 PCC_OFF = 0,
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196 PCC_P1 = 1,
197 PCC_P2 = 2,
198 PCC_P3 = 3,
199
192570e0 200 PCC_OFF_TO = 0,
3bf61c55 201 PCC_P1_TO = 1,
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202 PCC_P2_TO = 64,
203 PCC_P3_TO = 128,
3bf61c55 204
192570e0 205 PCC_OFF_CNT = 0,
3bf61c55 206 PCC_P1_CNT = 1,
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207 PCC_P2_CNT = 16,
208 PCC_P3_CNT = 32,
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209};
210struct dynpcc_info {
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211 unsigned long last_bytes;
212 unsigned long last_pkts;
79ce639c 213 unsigned long intr_cnt;
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214 unsigned char cur;
215 unsigned char attempt;
216 unsigned char cnt;
217};
79ce639c 218#define PCC_INTERVAL_US 100000
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219#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
220#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
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221#define PCC_P2_THRESHOLD 800
222#define PCC_INTR_THRESHOLD 800
47220951 223#define PCC_TX_TO 1000
b3821cc5 224#define PCC_TX_CNT 8
3bf61c55 225
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226/*
227 * TX/RX Descriptors
4330c2f2 228 *
cd0ff491 229 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
d7699f87 230 */
4330c2f2 231#define RING_DESC_ALIGN 16 /* Descriptor alignment */
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232#define TX_DESC_SIZE 16
233#define TX_RING_NR 8
cd0ff491 234#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 235
3bf61c55 236struct txdesc {
d7699f87 237 union {
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238 __u8 all[16];
239 __le32 dw[4];
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240 struct {
241 /* DW0 */
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242 __le16 vlan;
243 __u8 rsv1;
244 __u8 flags;
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245
246 /* DW1 */
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247 __le16 datalen;
248 __le16 mss;
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249
250 /* DW2 */
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251 __le16 pktsize;
252 __le16 rsv2;
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253
254 /* DW3 */
cd0ff491 255 __le32 bufaddr;
d7699f87 256 } desc1;
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257 struct {
258 /* DW0 */
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259 __le16 rsv1;
260 __u8 rsv2;
261 __u8 flags;
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262
263 /* DW1 */
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264 __le16 datalen;
265 __le16 rsv3;
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266
267 /* DW2 */
cd0ff491 268 __le32 bufaddrh;
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269
270 /* DW3 */
cd0ff491 271 __le32 bufaddrl;
3bf61c55 272 } desc2;
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273 struct {
274 /* DW0 */
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275 __u8 ehdrsz;
276 __u8 rsv1;
277 __u8 rsv2;
278 __u8 flags;
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279
280 /* DW1 */
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281 __le16 trycnt;
282 __le16 segcnt;
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283
284 /* DW2 */
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285 __le16 pktsz;
286 __le16 rsv3;
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287
288 /* DW3 */
cd0ff491 289 __le32 bufaddrl;
8c198884 290 } descwb;
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291 };
292};
cd0ff491 293
8c198884 294enum jme_txdesc_flags_bits {
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295 TXFLAG_OWN = 0x80,
296 TXFLAG_INT = 0x40,
3bf61c55 297 TXFLAG_64BIT = 0x20,
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298 TXFLAG_TCPCS = 0x10,
299 TXFLAG_UDPCS = 0x08,
300 TXFLAG_IPCS = 0x04,
301 TXFLAG_LSEN = 0x02,
302 TXFLAG_TAGON = 0x01,
303};
cd0ff491 304
b3821cc5 305#define TXDESC_MSS_SHIFT 2
0ede469c 306enum jme_txwbdesc_flags_bits {
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307 TXWBFLAG_OWN = 0x80,
308 TXWBFLAG_INT = 0x40,
309 TXWBFLAG_TMOUT = 0x20,
310 TXWBFLAG_TRYOUT = 0x10,
311 TXWBFLAG_COL = 0x08,
312
313 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
314 TXWBFLAG_TRYOUT |
315 TXWBFLAG_COL,
316};
d7699f87 317
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318#define RX_DESC_SIZE 16
319#define RX_RING_NR 4
cd0ff491 320#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 321#define RX_BUF_DMA_ALIGN 8
3bf61c55 322#define RX_PREPAD_SIZE 10
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323#define ETH_CRC_LEN 2
324#define RX_VLANHDR_LEN 2
325#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
326 ETH_HLEN + \
327 ETH_CRC_LEN + \
328 RX_VLANHDR_LEN + \
329 RX_BUF_DMA_ALIGN)
d7699f87 330
3bf61c55 331struct rxdesc {
d7699f87 332 union {
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333 __u8 all[16];
334 __le32 dw[4];
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335 struct {
336 /* DW0 */
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337 __le16 rsv2;
338 __u8 rsv1;
339 __u8 flags;
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340
341 /* DW1 */
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342 __le16 datalen;
343 __le16 wbcpl;
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344
345 /* DW2 */
cd0ff491 346 __le32 bufaddrh;
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347
348 /* DW3 */
cd0ff491 349 __le32 bufaddrl;
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350 } desc1;
351 struct {
352 /* DW0 */
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353 __le16 vlan;
354 __le16 flags;
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355
356 /* DW1 */
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357 __le16 framesize;
358 __u8 errstat;
359 __u8 desccnt;
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360
361 /* DW2 */
cd0ff491 362 __le32 rsshash;
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363
364 /* DW3 */
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365 __u8 hashfun;
366 __u8 hashtype;
367 __le16 resrv;
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368 } descwb;
369 };
370};
cd0ff491 371
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372enum jme_rxdesc_flags_bits {
373 RXFLAG_OWN = 0x80,
374 RXFLAG_INT = 0x40,
375 RXFLAG_64BIT = 0x20,
376};
cd0ff491 377
d7699f87 378enum jme_rxwbdesc_flags_bits {
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379 RXWBFLAG_OWN = 0x8000,
380 RXWBFLAG_INT = 0x4000,
381 RXWBFLAG_MF = 0x2000,
382 RXWBFLAG_64BIT = 0x2000,
383 RXWBFLAG_TCPON = 0x1000,
384 RXWBFLAG_UDPON = 0x0800,
385 RXWBFLAG_IPCS = 0x0400,
386 RXWBFLAG_TCPCS = 0x0200,
387 RXWBFLAG_UDPCS = 0x0100,
388 RXWBFLAG_TAGON = 0x0080,
389 RXWBFLAG_IPV4 = 0x0040,
390 RXWBFLAG_IPV6 = 0x0020,
391 RXWBFLAG_PAUSE = 0x0010,
392 RXWBFLAG_MAGIC = 0x0008,
393 RXWBFLAG_WAKEUP = 0x0004,
394 RXWBFLAG_DEST = 0x0003,
395 RXWBFLAG_DEST_UNI = 0x0001,
396 RXWBFLAG_DEST_MUL = 0x0002,
397 RXWBFLAG_DEST_BRO = 0x0003,
d7699f87 398};
cd0ff491 399
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400enum jme_rxwbdesc_desccnt_mask {
401 RXWBDCNT_WBCPL = 0x80,
402 RXWBDCNT_DCNT = 0x7F,
403};
cd0ff491 404
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405enum jme_rxwbdesc_errstat_bits {
406 RXWBERR_LIMIT = 0x80,
407 RXWBERR_MIIER = 0x40,
408 RXWBERR_NIBON = 0x20,
409 RXWBERR_COLON = 0x10,
410 RXWBERR_ABORT = 0x08,
411 RXWBERR_SHORT = 0x04,
412 RXWBERR_OVERUN = 0x02,
413 RXWBERR_CRCERR = 0x01,
414 RXWBERR_ALLERR = 0xFF,
415};
416
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417/*
418 * Buffer information corresponding to ring descriptors.
419 */
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420struct jme_buffer_info {
421 struct sk_buff *skb;
422 dma_addr_t mapping;
423 int len;
3bf61c55 424 int nr_desc;
cdcdc9eb 425 unsigned long start_xmit;
4330c2f2 426};
d7699f87 427
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428/*
429 * The structure holding buffer information and ring descriptors all together.
430 */
d7699f87 431struct jme_ring {
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432 void *alloc; /* pointer to allocated memory */
433 void *desc; /* pointer to ring memory */
434 dma_addr_t dmaalloc; /* phys address of ring alloc */
435 dma_addr_t dma; /* phys address for ring dma */
d7699f87 436
4330c2f2 437 /* Buffer information corresponding to each descriptor */
0ede469c 438 struct jme_buffer_info *bufinf;
d7699f87 439
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440 int next_to_use;
441 atomic_t next_to_clean;
79ce639c 442 atomic_t nr_free;
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443};
444
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445#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
446#define false 0
447#define true 0
448#define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
449#define PCI_VENDOR_ID_JMICRON 0x197B
450#endif
451
452#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
453#define PCI_VDEVICE(vendor, device) \
454 PCI_VENDOR_ID_##vendor, (device), \
455 PCI_ANY_ID, PCI_ANY_ID, 0, 0
456#endif
457
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458#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
459#define NET_STAT(priv) priv->stats
460#define NETDEV_GET_STATS(netdev, fun_ptr) \
461 netdev->get_stats = fun_ptr
462#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
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463/*
464 * CentOS 5.5 have *_hdr helpers back-ported
465 */
466#ifdef RHEL_RELEASE_CODE
467#if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,5)
468#define __DEFINE_IPHDR_HELPERS__
469#endif
470#else
471#define __DEFINE_IPHDR_HELPERS__
472#endif
473#else
474#define NET_STAT(priv) (priv->dev->stats)
475#define NETDEV_GET_STATS(netdev, fun_ptr)
476#define DECLARE_NET_DEVICE_STATS
477#endif
478
479#ifdef __DEFINE_IPHDR_HELPERS__
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480static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
481{
482 return skb->nh.iph;
483}
484
485static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
486{
487 return skb->nh.ipv6h;
488}
489
490static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
491{
492 return skb->h.th;
493}
85776f33 494#endif
3bf61c55 495
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496#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
497#define DECLARE_NAPI_STRUCT
498#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
499 dev->poll = pollfn; \
500 dev->weight = q;
501#define JME_NAPI_HOLDER(holder) struct net_device *holder
502#define JME_NAPI_WEIGHT(w) int *w
503#define JME_NAPI_WEIGHT_VAL(w) *w
504#define JME_NAPI_WEIGHT_SET(w, r) *w = r
3b70a6fa 505#define DECLARE_NETDEV struct net_device *netdev = jme->dev;
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506#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
507#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
508#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
509#define JME_RX_SCHEDULE_PREP(priv) \
510 netif_rx_schedule_prep(priv->dev)
511#define JME_RX_SCHEDULE(priv) \
512 __netif_rx_schedule(priv->dev);
0ede469c 513#else
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514#define DECLARE_NAPI_STRUCT struct napi_struct napi;
515#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
516 netif_napi_add(dev, napis, pollfn, q);
517#define JME_NAPI_HOLDER(holder) struct napi_struct *holder
518#define JME_NAPI_WEIGHT(w) int w
519#define JME_NAPI_WEIGHT_VAL(w) w
520#define JME_NAPI_WEIGHT_SET(w, r)
521#define DECLARE_NETDEV
522#define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
523#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
524#define JME_NAPI_DISABLE(priv) \
525 if (!napi_disable_pending(&priv->napi)) \
526 napi_disable(&priv->napi);
527#define JME_RX_SCHEDULE_PREP(priv) \
528 napi_schedule_prep(&priv->napi)
529#define JME_RX_SCHEDULE(priv) \
530 __napi_schedule(&priv->napi);
85776f33 531#endif
cdcdc9eb 532
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533/*
534 * Jmac Adapter Private data
535 */
536struct jme_adapter {
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537 struct pci_dev *pdev;
538 struct net_device *dev;
539 void __iomem *regs;
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540 struct mii_if_info mii_if;
541 struct jme_ring rxring[RX_RING_NR];
542 struct jme_ring txring[TX_RING_NR];
d7699f87 543 spinlock_t phy_lock;
fcf45b4c 544 spinlock_t macaddr_lock;
8c198884 545 spinlock_t rxmcs_lock;
fcf45b4c 546 struct tasklet_struct rxempty_task;
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547 struct tasklet_struct rxclean_task;
548 struct tasklet_struct txclean_task;
549 struct tasklet_struct linkch_task;
79ce639c 550 struct tasklet_struct pcc_task;
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551 unsigned long flags;
552 u32 reg_txcs;
553 u32 reg_txpfc;
554 u32 reg_rxcs;
555 u32 reg_rxmcs;
556 u32 reg_ghc;
557 u32 reg_pmcs;
dc4185bd 558 u32 reg_gpreg1;
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GFT
559 u32 phylink;
560 u32 tx_ring_size;
561 u32 tx_ring_mask;
562 u32 tx_wake_threshold;
563 u32 rx_ring_size;
564 u32 rx_ring_mask;
565 u8 mrrs;
566 unsigned int fpgaver;
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GFT
567 u8 chiprev;
568 u8 chip_main_rev;
569 u8 chip_sub_rev;
570 u8 pcirev;
cd0ff491 571 u32 msg_enable;
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GFT
572 struct ethtool_cmd old_ecmd;
573 unsigned int old_mtu;
cd0ff491 574 struct vlan_group *vlgrp;
3bf61c55
GFT
575 struct dynpcc_info dpi;
576 atomic_t intr_sem;
fcf45b4c
GFT
577 atomic_t link_changing;
578 atomic_t tx_cleaning;
579 atomic_t rx_cleaning;
192570e0 580 atomic_t rx_empty;
cdcdc9eb
GFT
581 int (*jme_rx)(struct sk_buff *skb);
582 int (*jme_vlan_rx)(struct sk_buff *skb,
583 struct vlan_group *grp,
584 unsigned short vlan_tag);
585 DECLARE_NAPI_STRUCT
3bf61c55 586 DECLARE_NET_DEVICE_STATS
d7699f87 587};
cd0ff491 588
3b70a6fa
GFT
589#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
590static struct net_device_stats *
591jme_get_stats(struct net_device *netdev)
592{
593 struct jme_adapter *jme = netdev_priv(netdev);
594 return &jme->stats;
595}
596#endif
597
79ce639c 598enum jme_flags_bits {
cd0ff491
GFT
599 JME_FLAG_MSI = 1,
600 JME_FLAG_SSET = 2,
601 JME_FLAG_TXCSUM = 3,
602 JME_FLAG_TSO = 4,
603 JME_FLAG_POLL = 5,
604 JME_FLAG_SHUTDOWN = 6,
8c198884 605};
cd0ff491
GFT
606
607#define TX_TIMEOUT (5 * HZ)
186fc259 608#define JME_REG_LEN 0x500
cd0ff491 609#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
8c198884 610
85776f33 611#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
7ee473a3 612static inline struct jme_adapter*
85776f33
GFT
613jme_napi_priv(struct net_device *holder)
614{
7ee473a3 615 struct jme_adapter *jme;
85776f33
GFT
616 jme = netdev_priv(holder);
617 return jme;
618}
619#else
7ee473a3 620static inline struct jme_adapter*
cdcdc9eb
GFT
621jme_napi_priv(struct napi_struct *napi)
622{
7ee473a3 623 struct jme_adapter *jme;
cdcdc9eb
GFT
624 jme = container_of(napi, struct jme_adapter, napi);
625 return jme;
626}
85776f33 627#endif
d7699f87
GFT
628
629/*
630 * MMaped I/O Resters
631 */
632enum jme_iomap_offsets {
4330c2f2
GFT
633 JME_MAC = 0x0000,
634 JME_PHY = 0x0400,
d7699f87 635 JME_MISC = 0x0800,
4330c2f2 636 JME_RSS = 0x0C00,
d7699f87
GFT
637};
638
8c198884
GFT
639enum jme_iomap_lens {
640 JME_MAC_LEN = 0x80,
641 JME_PHY_LEN = 0x58,
642 JME_MISC_LEN = 0x98,
643 JME_RSS_LEN = 0xFF,
644};
645
d7699f87
GFT
646enum jme_iomap_regs {
647 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
3bf61c55
GFT
648 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
649 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
d7699f87
GFT
650 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
651 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
652 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
653 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
654 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
655
656 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
3bf61c55
GFT
657 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
658 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
d7699f87
GFT
659 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
660 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
661 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
4330c2f2
GFT
662 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
663 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
3bf61c55
GFT
664 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
665 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
d7699f87
GFT
666 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
667 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
668
669 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
670 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
671 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
672
673
ed457bcc 674 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
3bf61c55 675 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
d7699f87
GFT
676 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
677 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
186fc259 678 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
d7699f87
GFT
679
680
cd0ff491
GFT
681 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
682 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
683 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
684 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
685 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
686 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
687 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
688 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
689 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
690 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
691 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
692 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
693 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
694 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
695 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
696 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
d7699f87
GFT
697};
698
699/*
700 * TX Control/Status Bits
701 */
702enum jme_txcs_bits {
703 TXCS_QUEUE7S = 0x00008000,
704 TXCS_QUEUE6S = 0x00004000,
705 TXCS_QUEUE5S = 0x00002000,
706 TXCS_QUEUE4S = 0x00001000,
707 TXCS_QUEUE3S = 0x00000800,
708 TXCS_QUEUE2S = 0x00000400,
709 TXCS_QUEUE1S = 0x00000200,
710 TXCS_QUEUE0S = 0x00000100,
711 TXCS_FIFOTH = 0x000000C0,
712 TXCS_DMASIZE = 0x00000030,
713 TXCS_BURST = 0x00000004,
714 TXCS_ENABLE = 0x00000001,
715};
cd0ff491 716
d7699f87
GFT
717enum jme_txcs_value {
718 TXCS_FIFOTH_16QW = 0x000000C0,
719 TXCS_FIFOTH_12QW = 0x00000080,
720 TXCS_FIFOTH_8QW = 0x00000040,
721 TXCS_FIFOTH_4QW = 0x00000000,
722
723 TXCS_DMASIZE_64B = 0x00000000,
724 TXCS_DMASIZE_128B = 0x00000010,
725 TXCS_DMASIZE_256B = 0x00000020,
726 TXCS_DMASIZE_512B = 0x00000030,
727
728 TXCS_SELECT_QUEUE0 = 0x00000000,
729 TXCS_SELECT_QUEUE1 = 0x00010000,
730 TXCS_SELECT_QUEUE2 = 0x00020000,
731 TXCS_SELECT_QUEUE3 = 0x00030000,
732 TXCS_SELECT_QUEUE4 = 0x00040000,
733 TXCS_SELECT_QUEUE5 = 0x00050000,
734 TXCS_SELECT_QUEUE6 = 0x00060000,
735 TXCS_SELECT_QUEUE7 = 0x00070000,
736
737 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
d7699f87
GFT
738 TXCS_BURST,
739};
cd0ff491 740
29bdd921 741#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
742
743/*
744 * TX MAC Control/Status Bits
745 */
746enum jme_txmcs_bit_masks {
747 TXMCS_IFG2 = 0xC0000000,
748 TXMCS_IFG1 = 0x30000000,
749 TXMCS_TTHOLD = 0x00000300,
750 TXMCS_FBURST = 0x00000080,
751 TXMCS_CARRIEREXT = 0x00000040,
752 TXMCS_DEFER = 0x00000020,
753 TXMCS_BACKOFF = 0x00000010,
754 TXMCS_CARRIERSENSE = 0x00000008,
755 TXMCS_COLLISION = 0x00000004,
756 TXMCS_CRC = 0x00000002,
757 TXMCS_PADDING = 0x00000001,
758};
cd0ff491 759
d7699f87
GFT
760enum jme_txmcs_values {
761 TXMCS_IFG2_6_4 = 0x00000000,
762 TXMCS_IFG2_8_5 = 0x40000000,
763 TXMCS_IFG2_10_6 = 0x80000000,
764 TXMCS_IFG2_12_7 = 0xC0000000,
765
766 TXMCS_IFG1_8_4 = 0x00000000,
767 TXMCS_IFG1_12_6 = 0x10000000,
768 TXMCS_IFG1_16_8 = 0x20000000,
769 TXMCS_IFG1_20_10 = 0x30000000,
770
771 TXMCS_TTHOLD_1_8 = 0x00000000,
772 TXMCS_TTHOLD_1_4 = 0x00000100,
773 TXMCS_TTHOLD_1_2 = 0x00000200,
774 TXMCS_TTHOLD_FULL = 0x00000300,
775
776 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
777 TXMCS_IFG1_16_8 |
778 TXMCS_TTHOLD_FULL |
779 TXMCS_DEFER |
780 TXMCS_CRC |
781 TXMCS_PADDING,
782};
783
8c198884
GFT
784enum jme_txpfc_bits_masks {
785 TXPFC_VLAN_TAG = 0xFFFF0000,
786 TXPFC_VLAN_EN = 0x00008000,
787 TXPFC_PF_EN = 0x00000001,
788};
789
790enum jme_txtrhd_bits_masks {
791 TXTRHD_TXPEN = 0x80000000,
792 TXTRHD_TXP = 0x7FFFFF00,
793 TXTRHD_TXREN = 0x00000080,
794 TXTRHD_TXRL = 0x0000007F,
795};
cd0ff491 796
8c198884
GFT
797enum jme_txtrhd_shifts {
798 TXTRHD_TXP_SHIFT = 8,
799 TXTRHD_TXRL_SHIFT = 0,
800};
801
809b2798
GFT
802enum jme_txtrhd_values {
803 TXTRHD_FULLDUPLEX = 0x00000000,
804 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
805 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
806 TXTRHD_TXREN |
807 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
808};
809
d7699f87
GFT
810/*
811 * RX Control/Status Bits
812 */
4330c2f2 813enum jme_rxcs_bit_masks {
3bf61c55
GFT
814 /* FIFO full threshold for transmitting Tx Pause Packet */
815 RXCS_FIFOTHTP = 0x30000000,
816 /* FIFO threshold for processing next packet */
817 RXCS_FIFOTHNP = 0x0C000000,
4330c2f2
GFT
818 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
819 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
820 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
821 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
822 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
823 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
824 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
825 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
826 RXCS_QST = 0x00000004, /* Receive queue start */
827 RXCS_SUSPEND = 0x00000002,
d7699f87
GFT
828 RXCS_ENABLE = 0x00000001,
829};
cd0ff491 830
4330c2f2
GFT
831enum jme_rxcs_values {
832 RXCS_FIFOTHTP_16T = 0x00000000,
833 RXCS_FIFOTHTP_32T = 0x10000000,
834 RXCS_FIFOTHTP_64T = 0x20000000,
835 RXCS_FIFOTHTP_128T = 0x30000000,
836
837 RXCS_FIFOTHNP_16QW = 0x00000000,
838 RXCS_FIFOTHNP_32QW = 0x04000000,
839 RXCS_FIFOTHNP_64QW = 0x08000000,
840 RXCS_FIFOTHNP_128QW = 0x0C000000,
841
842 RXCS_DMAREQSZ_16B = 0x00000000,
843 RXCS_DMAREQSZ_32B = 0x01000000,
844 RXCS_DMAREQSZ_64B = 0x02000000,
845 RXCS_DMAREQSZ_128B = 0x03000000,
846
847 RXCS_QUEUESEL_Q0 = 0x00000000,
848 RXCS_QUEUESEL_Q1 = 0x00010000,
849 RXCS_QUEUESEL_Q2 = 0x00020000,
850 RXCS_QUEUESEL_Q3 = 0x00030000,
851
852 RXCS_RETRYGAP_256ns = 0x00000000,
853 RXCS_RETRYGAP_512ns = 0x00001000,
854 RXCS_RETRYGAP_1024ns = 0x00002000,
855 RXCS_RETRYGAP_2048ns = 0x00003000,
856 RXCS_RETRYGAP_4096ns = 0x00004000,
857 RXCS_RETRYGAP_8192ns = 0x00005000,
858 RXCS_RETRYGAP_16384ns = 0x00006000,
859 RXCS_RETRYGAP_32768ns = 0x00007000,
860
861 RXCS_RETRYCNT_0 = 0x00000000,
862 RXCS_RETRYCNT_4 = 0x00000100,
863 RXCS_RETRYCNT_8 = 0x00000200,
864 RXCS_RETRYCNT_12 = 0x00000300,
865 RXCS_RETRYCNT_16 = 0x00000400,
866 RXCS_RETRYCNT_20 = 0x00000500,
867 RXCS_RETRYCNT_24 = 0x00000600,
868 RXCS_RETRYCNT_28 = 0x00000700,
869 RXCS_RETRYCNT_32 = 0x00000800,
870 RXCS_RETRYCNT_36 = 0x00000900,
871 RXCS_RETRYCNT_40 = 0x00000A00,
872 RXCS_RETRYCNT_44 = 0x00000B00,
873 RXCS_RETRYCNT_48 = 0x00000C00,
874 RXCS_RETRYCNT_52 = 0x00000D00,
875 RXCS_RETRYCNT_56 = 0x00000E00,
876 RXCS_RETRYCNT_60 = 0x00000F00,
877
878 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
79ce639c 879 RXCS_FIFOTHNP_128QW |
4330c2f2
GFT
880 RXCS_DMAREQSZ_128B |
881 RXCS_RETRYGAP_256ns |
882 RXCS_RETRYCNT_32,
883};
cd0ff491 884
29bdd921 885#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
886
887/*
888 * RX MAC Control/Status Bits
889 */
890enum jme_rxmcs_bits {
891 RXMCS_ALLFRAME = 0x00000800,
892 RXMCS_BRDFRAME = 0x00000400,
893 RXMCS_MULFRAME = 0x00000200,
894 RXMCS_UNIFRAME = 0x00000100,
895 RXMCS_ALLMULFRAME = 0x00000080,
896 RXMCS_MULFILTERED = 0x00000040,
3bf61c55
GFT
897 RXMCS_RXCOLLDEC = 0x00000020,
898 RXMCS_FLOWCTRL = 0x00000008,
899 RXMCS_VTAGRM = 0x00000004,
900 RXMCS_PREPAD = 0x00000002,
901 RXMCS_CHECKSUM = 0x00000001,
b3821cc5 902
8c198884
GFT
903 RXMCS_DEFAULT = RXMCS_VTAGRM |
904 RXMCS_PREPAD |
905 RXMCS_FLOWCTRL |
906 RXMCS_CHECKSUM,
d7699f87
GFT
907};
908
909/*
b3821cc5
GFT
910 * Wakeup Frame setup interface registers
911 */
912#define WAKEUP_FRAME_NR 8
913#define WAKEUP_FRAME_MASK_DWNR 4
cd0ff491 914
b3821cc5
GFT
915enum jme_wfoi_bit_masks {
916 WFOI_MASK_SEL = 0x00000070,
917 WFOI_CRC_SEL = 0x00000008,
918 WFOI_FRAME_SEL = 0x00000007,
919};
cd0ff491 920
b3821cc5
GFT
921enum jme_wfoi_shifts {
922 WFOI_MASK_SHIFT = 4,
923};
924
925/*
d7699f87
GFT
926 * SMI Related definitions
927 */
cd0ff491 928enum jme_smi_bit_mask {
d7699f87
GFT
929 SMI_DATA_MASK = 0xFFFF0000,
930 SMI_REG_ADDR_MASK = 0x0000F800,
931 SMI_PHY_ADDR_MASK = 0x000007C0,
932 SMI_OP_WRITE = 0x00000020,
3bf61c55
GFT
933 /* Set to 1, after req done it'll be cleared to 0 */
934 SMI_OP_REQ = 0x00000010,
d7699f87
GFT
935 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
936 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
937 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
938 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
939};
cd0ff491
GFT
940
941enum jme_smi_bit_shift {
d7699f87
GFT
942 SMI_DATA_SHIFT = 16,
943 SMI_REG_ADDR_SHIFT = 11,
944 SMI_PHY_ADDR_SHIFT = 6,
945};
cd0ff491
GFT
946
947static inline u32 smi_reg_addr(int x)
d7699f87 948{
cd0ff491 949 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
d7699f87 950}
cd0ff491
GFT
951
952static inline u32 smi_phy_addr(int x)
d7699f87 953{
cd0ff491 954 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
d7699f87 955}
cd0ff491 956
8d27293f 957#define JME_PHY_TIMEOUT 100 /* 100 msec */
186fc259 958#define JME_PHY_REG_NR 32
d7699f87
GFT
959
960/*
961 * Global Host Control
962 */
963enum jme_ghc_bit_mask {
3b70a6fa 964 GHC_SWRST = 0x40000000,
dc4185bd
GFT
965 GHC_TO_CLK_SRC = 0x00C00000,
966 GHC_TXMAC_CLK_SRC = 0x00300000,
3b70a6fa
GFT
967 GHC_DPX = 0x00000040,
968 GHC_SPEED = 0x00000030,
969 GHC_LINK_POLL = 0x00000001,
d7699f87 970};
cd0ff491 971
d7699f87 972enum jme_ghc_speed_val {
3b70a6fa
GFT
973 GHC_SPEED_10M = 0x00000010,
974 GHC_SPEED_100M = 0x00000020,
975 GHC_SPEED_1000M = 0x00000030,
976};
977
978enum jme_ghc_to_clk {
979 GHC_TO_CLK_OFF = 0x00000000,
980 GHC_TO_CLK_GPHY = 0x00400000,
981 GHC_TO_CLK_PCIE = 0x00800000,
982 GHC_TO_CLK_INVALID = 0x00C00000,
983};
984
985enum jme_ghc_txmac_clk {
986 GHC_TXMAC_CLK_OFF = 0x00000000,
987 GHC_TXMAC_CLK_GPHY = 0x00100000,
988 GHC_TXMAC_CLK_PCIE = 0x00200000,
989 GHC_TXMAC_CLK_INVALID = 0x00300000,
d7699f87
GFT
990};
991
992/*
29bdd921
GFT
993 * Power management control and status register
994 */
995enum jme_pmcs_bit_masks {
996 PMCS_WF7DET = 0x80000000,
997 PMCS_WF6DET = 0x40000000,
998 PMCS_WF5DET = 0x20000000,
999 PMCS_WF4DET = 0x10000000,
1000 PMCS_WF3DET = 0x08000000,
1001 PMCS_WF2DET = 0x04000000,
1002 PMCS_WF1DET = 0x02000000,
1003 PMCS_WF0DET = 0x01000000,
1004 PMCS_LFDET = 0x00040000,
1005 PMCS_LRDET = 0x00020000,
1006 PMCS_MFDET = 0x00010000,
1007 PMCS_WF7EN = 0x00008000,
1008 PMCS_WF6EN = 0x00004000,
1009 PMCS_WF5EN = 0x00002000,
1010 PMCS_WF4EN = 0x00001000,
1011 PMCS_WF3EN = 0x00000800,
1012 PMCS_WF2EN = 0x00000400,
1013 PMCS_WF1EN = 0x00000200,
1014 PMCS_WF0EN = 0x00000100,
1015 PMCS_LFEN = 0x00000004,
1016 PMCS_LREN = 0x00000002,
1017 PMCS_MFEN = 0x00000001,
1018};
1019
1020/*
ed457bcc
GFT
1021 * New PHY Power Control Register
1022 */
1023enum jme_phy_pwr_bit_masks {
1024 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
1025 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
1026 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
1027 PHY_PWR_CLKSEL = 0x08000000, /*
1028 * XTL_OUT Clock select
1029 * (an internal free-running clock)
1030 * 0: xtl_out = phy_giga.A_XTL25_O
1031 * 1: xtl_out = phy_giga.PD_OSC
1032 */
1033};
1034
1035/*
3bf61c55 1036 * Giga PHY Status Registers
d7699f87
GFT
1037 */
1038enum jme_phy_link_bit_mask {
1039 PHY_LINK_SPEED_MASK = 0x0000C000,
1040 PHY_LINK_DUPLEX = 0x00002000,
1041 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
1042 PHY_LINK_UP = 0x00000400,
1043 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
fcf45b4c 1044 PHY_LINK_MDI_STAT = 0x00000040,
d7699f87 1045};
cd0ff491 1046
d7699f87
GFT
1047enum jme_phy_link_speed_val {
1048 PHY_LINK_SPEED_10M = 0x00000000,
1049 PHY_LINK_SPEED_100M = 0x00004000,
1050 PHY_LINK_SPEED_1000M = 0x00008000,
1051};
cd0ff491 1052
fcf45b4c 1053#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
d7699f87
GFT
1054
1055/*
1056 * SMB Control and Status
1057 */
79ce639c 1058enum jme_smbcsr_bit_mask {
d7699f87
GFT
1059 SMBCSR_CNACK = 0x00020000,
1060 SMBCSR_RELOAD = 0x00010000,
1061 SMBCSR_EEPROMD = 0x00000020,
186fc259
GFT
1062 SMBCSR_INITDONE = 0x00000010,
1063 SMBCSR_BUSY = 0x0000000F,
1064};
cd0ff491 1065
186fc259
GFT
1066enum jme_smbintf_bit_mask {
1067 SMBINTF_HWDATR = 0xFF000000,
1068 SMBINTF_HWDATW = 0x00FF0000,
1069 SMBINTF_HWADDR = 0x0000FF00,
1070 SMBINTF_HWRWN = 0x00000020,
1071 SMBINTF_HWCMD = 0x00000010,
1072 SMBINTF_FASTM = 0x00000008,
1073 SMBINTF_GPIOSCL = 0x00000004,
1074 SMBINTF_GPIOSDA = 0x00000002,
1075 SMBINTF_GPIOEN = 0x00000001,
1076};
cd0ff491 1077
186fc259
GFT
1078enum jme_smbintf_vals {
1079 SMBINTF_HWRWN_READ = 0x00000020,
1080 SMBINTF_HWRWN_WRITE = 0x00000000,
1081};
cd0ff491 1082
186fc259
GFT
1083enum jme_smbintf_shifts {
1084 SMBINTF_HWDATR_SHIFT = 24,
1085 SMBINTF_HWDATW_SHIFT = 16,
1086 SMBINTF_HWADDR_SHIFT = 8,
1087};
cd0ff491 1088
186fc259
GFT
1089#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1090#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1091#define JME_SMB_LEN 256
1092#define JME_EEPROM_MAGIC 0x250
d7699f87 1093
79ce639c
GFT
1094/*
1095 * Timer Control/Status Register
1096 */
1097enum jme_tmcsr_bit_masks {
1098 TMCSR_SWIT = 0x80000000,
1099 TMCSR_EN = 0x01000000,
1100 TMCSR_CNT = 0x00FFFFFF,
1101};
1102
d7699f87 1103/*
cd0ff491 1104 * General Purpose REG-0
4330c2f2
GFT
1105 */
1106enum jme_gpreg0_masks {
3bf61c55
GFT
1107 GPREG0_DISSH = 0xFF000000,
1108 GPREG0_PCIRLMT = 0x00300000,
1109 GPREG0_PCCNOMUTCLR = 0x00040000,
cdcdc9eb 1110 GPREG0_LNKINTPOLL = 0x00001000,
3bf61c55
GFT
1111 GPREG0_PCCTMR = 0x00000300,
1112 GPREG0_PHYADDR = 0x0000001F,
4330c2f2 1113};
cd0ff491 1114
4330c2f2
GFT
1115enum jme_gpreg0_vals {
1116 GPREG0_DISSH_DW7 = 0x80000000,
1117 GPREG0_DISSH_DW6 = 0x40000000,
1118 GPREG0_DISSH_DW5 = 0x20000000,
1119 GPREG0_DISSH_DW4 = 0x10000000,
1120 GPREG0_DISSH_DW3 = 0x08000000,
1121 GPREG0_DISSH_DW2 = 0x04000000,
1122 GPREG0_DISSH_DW1 = 0x02000000,
1123 GPREG0_DISSH_DW0 = 0x01000000,
1124 GPREG0_DISSH_ALL = 0xFF000000,
1125
1126 GPREG0_PCIRLMT_8 = 0x00000000,
1127 GPREG0_PCIRLMT_6 = 0x00100000,
1128 GPREG0_PCIRLMT_5 = 0x00200000,
1129 GPREG0_PCIRLMT_4 = 0x00300000,
1130
1131 GPREG0_PCCTMR_16ns = 0x00000000,
3bf61c55
GFT
1132 GPREG0_PCCTMR_256ns = 0x00000100,
1133 GPREG0_PCCTMR_1us = 0x00000200,
1134 GPREG0_PCCTMR_1ms = 0x00000300,
4330c2f2
GFT
1135
1136 GPREG0_PHYADDR_1 = 0x00000001,
1137
1138 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
3bf61c55
GFT
1139 GPREG0_PCCTMR_1us |
1140 GPREG0_PHYADDR_1,
4330c2f2
GFT
1141};
1142
1143/*
7ee473a3 1144 * General Purpose REG-1
7ee473a3 1145 */
dc4185bd
GFT
1146enum jme_gpreg1_bit_masks {
1147 GPREG1_RXCLKOFF = 0x04000000,
1148 GPREG1_PCREQN = 0x00020000,
1149 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1150 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
7ee473a3
GFT
1151 GPREG1_INTRDELAYUNIT = 0x00000018,
1152 GPREG1_INTRDELAYENABLE = 0x00000007,
1153};
1154
1155enum jme_gpreg1_vals {
7ee473a3
GFT
1156 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1157 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1158 GPREG1_INTDLYUNIT_1US = 0x00000010,
1159 GPREG1_INTDLYUNIT_16US = 0x00000018,
1160
1161 GPREG1_INTDLYEN_1U = 0x00000001,
1162 GPREG1_INTDLYEN_2U = 0x00000002,
1163 GPREG1_INTDLYEN_3U = 0x00000003,
1164 GPREG1_INTDLYEN_4U = 0x00000004,
1165 GPREG1_INTDLYEN_5U = 0x00000005,
1166 GPREG1_INTDLYEN_6U = 0x00000006,
1167 GPREG1_INTDLYEN_7U = 0x00000007,
1168
dc4185bd 1169 GPREG1_DEFAULT = GPREG1_PCREQN,
7ee473a3
GFT
1170};
1171
1172/*
d7699f87
GFT
1173 * Interrupt Status Bits
1174 */
cd0ff491 1175enum jme_interrupt_bits {
d7699f87
GFT
1176 INTR_SWINTR = 0x80000000,
1177 INTR_TMINTR = 0x40000000,
1178 INTR_LINKCH = 0x20000000,
1179 INTR_PAUSERCV = 0x10000000,
1180 INTR_MAGICRCV = 0x08000000,
1181 INTR_WAKERCV = 0x04000000,
1182 INTR_PCCRX0TO = 0x02000000,
1183 INTR_PCCRX1TO = 0x01000000,
1184 INTR_PCCRX2TO = 0x00800000,
1185 INTR_PCCRX3TO = 0x00400000,
1186 INTR_PCCTXTO = 0x00200000,
1187 INTR_PCCRX0 = 0x00100000,
1188 INTR_PCCRX1 = 0x00080000,
1189 INTR_PCCRX2 = 0x00040000,
1190 INTR_PCCRX3 = 0x00020000,
1191 INTR_PCCTX = 0x00010000,
1192 INTR_RX3EMP = 0x00008000,
1193 INTR_RX2EMP = 0x00004000,
1194 INTR_RX1EMP = 0x00002000,
1195 INTR_RX0EMP = 0x00001000,
1196 INTR_RX3 = 0x00000800,
1197 INTR_RX2 = 0x00000400,
1198 INTR_RX1 = 0x00000200,
1199 INTR_RX0 = 0x00000100,
1200 INTR_TX7 = 0x00000080,
1201 INTR_TX6 = 0x00000040,
1202 INTR_TX5 = 0x00000020,
1203 INTR_TX4 = 0x00000010,
1204 INTR_TX3 = 0x00000008,
1205 INTR_TX2 = 0x00000004,
1206 INTR_TX1 = 0x00000002,
1207 INTR_TX0 = 0x00000001,
1208};
cd0ff491
GFT
1209
1210static const u32 INTR_ENABLE = INTR_SWINTR |
79ce639c
GFT
1211 INTR_TMINTR |
1212 INTR_LINKCH |
3bf61c55
GFT
1213 INTR_PCCRX0TO |
1214 INTR_PCCRX0 |
1215 INTR_PCCTXTO |
cdcdc9eb
GFT
1216 INTR_PCCTX |
1217 INTR_RX0EMP;
3bf61c55
GFT
1218
1219/*
1220 * PCC Control Registers
1221 */
1222enum jme_pccrx_masks {
1223 PCCRXTO_MASK = 0xFFFF0000,
1224 PCCRX_MASK = 0x0000FF00,
1225};
cd0ff491 1226
3bf61c55
GFT
1227enum jme_pcctx_masks {
1228 PCCTXTO_MASK = 0xFFFF0000,
1229 PCCTX_MASK = 0x0000FF00,
1230 PCCTX_QS_MASK = 0x000000FF,
1231};
cd0ff491 1232
3bf61c55
GFT
1233enum jme_pccrx_shifts {
1234 PCCRXTO_SHIFT = 16,
1235 PCCRX_SHIFT = 8,
1236};
cd0ff491 1237
3bf61c55
GFT
1238enum jme_pcctx_shifts {
1239 PCCTXTO_SHIFT = 16,
1240 PCCTX_SHIFT = 8,
1241};
cd0ff491 1242
3bf61c55
GFT
1243enum jme_pcctx_bits {
1244 PCCTXQ0_EN = 0x00000001,
1245 PCCTXQ1_EN = 0x00000002,
1246 PCCTXQ2_EN = 0x00000004,
1247 PCCTXQ3_EN = 0x00000008,
1248 PCCTXQ4_EN = 0x00000010,
1249 PCCTXQ5_EN = 0x00000020,
1250 PCCTXQ6_EN = 0x00000040,
1251 PCCTXQ7_EN = 0x00000080,
1252};
1253
cdcdc9eb
GFT
1254/*
1255 * Chip Mode Register
1256 */
1257enum jme_chipmode_bit_masks {
1258 CM_FPGAVER_MASK = 0xFFFF0000,
58c92f28 1259 CM_CHIPREV_MASK = 0x0000FF00,
cdcdc9eb
GFT
1260 CM_CHIPMODE_MASK = 0x0000000F,
1261};
cd0ff491 1262
cdcdc9eb
GFT
1263enum jme_chipmode_shifts {
1264 CM_FPGAVER_SHIFT = 16,
58c92f28 1265 CM_CHIPREV_SHIFT = 8,
cdcdc9eb 1266};
d7699f87
GFT
1267
1268/*
cd0ff491
GFT
1269 * Aggressive Power Mode Control
1270 */
1271enum jme_apmc_bits {
1272 JME_APMC_PCIE_SD_EN = 0x40000000,
1273 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1274 JME_APMC_EPIEN = 0x04000000,
1275 JME_APMC_EPIEN_CTRL = 0x03000000,
1276};
1277
1278enum jme_apmc_values {
1279 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1280 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1281};
1282
1283#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1284
1285#ifdef REG_DEBUG
1286static char *MAC_REG_NAME[] = {
1287 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1288 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1289 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1290 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1291 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1292 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1293 "JME_PMCS"};
7ee473a3 1294
cd0ff491
GFT
1295static char *PE_REG_NAME[] = {
1296 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1297 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1298 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1299 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1300 "JME_SMBCSR", "JME_SMBINTF"};
7ee473a3 1301
cd0ff491
GFT
1302static char *MISC_REG_NAME[] = {
1303 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1304 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1305 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1306 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1307 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1308 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1309 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1310 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1311 "JME_PCCSRX0"};
7ee473a3 1312
cd0ff491
GFT
1313static inline void reg_dbg(const struct jme_adapter *jme,
1314 const char *msg, u32 val, u32 reg)
1315{
1316 const char *regname;
58c92f28 1317 switch (reg & 0xF00) {
cd0ff491
GFT
1318 case 0x000:
1319 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1320 break;
1321 case 0x400:
1322 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1323 break;
1324 case 0x800:
58c92f28 1325 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
cd0ff491
GFT
1326 break;
1327 default:
1328 regname = PE_REG_NAME[0];
1329 }
1330 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1331 msg, val, regname);
1332}
1333#else
1334static inline void reg_dbg(const struct jme_adapter *jme,
1335 const char *msg, u32 val, u32 reg) {}
1336#endif
1337
1338/*
d7699f87
GFT
1339 * Read/Write MMaped I/O Registers
1340 */
cd0ff491 1341static inline u32 jread32(struct jme_adapter *jme, u32 reg)
d7699f87 1342{
cd0ff491 1343 return readl(jme->regs + reg);
d7699f87 1344}
cd0ff491
GFT
1345
1346static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
d7699f87 1347{
cd0ff491
GFT
1348 reg_dbg(jme, "REG WRITE", val, reg);
1349 writel(val, jme->regs + reg);
1350 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
d7699f87 1351}
cd0ff491
GFT
1352
1353static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
d7699f87
GFT
1354{
1355 /*
1356 * Read after write should cause flush
1357 */
cd0ff491
GFT
1358 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1359 writel(val, jme->regs + reg);
1360 readl(jme->regs + reg);
1361 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
d7699f87
GFT
1362}
1363
1364/*
cdcdc9eb
GFT
1365 * PHY Regs
1366 */
1367enum jme_phy_reg17_bit_masks {
1368 PREG17_SPEED = 0xC000,
1369 PREG17_DUPLEX = 0x2000,
1370 PREG17_SPDRSV = 0x0800,
1371 PREG17_LNKUP = 0x0400,
1372 PREG17_MDI = 0x0040,
1373};
cd0ff491 1374
cdcdc9eb
GFT
1375enum jme_phy_reg17_vals {
1376 PREG17_SPEED_10M = 0x0000,
1377 PREG17_SPEED_100M = 0x4000,
1378 PREG17_SPEED_1000M = 0x8000,
1379};
cd0ff491 1380
8d27293f 1381#define BMSR_ANCOMP 0x0020
cdcdc9eb
GFT
1382
1383/*
58c92f28
GFT
1384 * Workaround
1385 */
98ef18f1 1386static inline int is_buggy250(unsigned short device, u8 chiprev)
58c92f28
GFT
1387{
1388 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1389}
1390
ed457bcc
GFT
1391static inline int new_phy_power_ctrl(u8 chip_main_rev)
1392{
1393 return chip_main_rev >= 5;
1394}
1395
58c92f28 1396/*
cd0ff491 1397 * Function prototypes
d7699f87 1398 */
d7699f87 1399static int jme_set_settings(struct net_device *netdev,
cd0ff491 1400 struct ethtool_cmd *ecmd);
e523cd89 1401static void jme_set_unicastaddr(struct net_device *netdev);
d7699f87
GFT
1402static void jme_set_multi(struct net_device *netdev);
1403
cd0ff491 1404#endif
e5169728 1405