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ixgbe: ixgbe_down needs to stop dev_watchdog
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
b4617240 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
92eb879f 55#define DRV_VERSION "2.0.62-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
312eb931
DS		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
112 board_82599 },
9a799d71
AK		 113
114 /* required last entry */
115 {0, }
116};
117MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
118
5dd2d332 119#ifdef CONFIG_IXGBE_DCA
bd0362dd 120static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 121 void *p);
bd0362dd
JC		 122static struct notifier_block dca_notifier = {
123 .notifier_call = ixgbe_notify_dca,
124 .next = NULL,
125 .priority = 0
126};
127#endif
128
1cdd1ec8
GR		 129#ifdef CONFIG_PCI_IOV
130static unsigned int max_vfs;
131module_param(max_vfs, uint, 0);
132MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
133 "per physical function");
134#endif /* CONFIG_PCI_IOV */
135
9a799d71
AK		 136MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
137MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
138MODULE_LICENSE("GPL");
139MODULE_VERSION(DRV_VERSION);
140
141#define DEFAULT_DEBUG_LEVEL_SHIFT 3
142
1cdd1ec8
GR		 143static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
144{
145 struct ixgbe_hw *hw = &adapter->hw;
146 u32 gcr;
147 u32 gpie;
148 u32 vmdctl;
149
150#ifdef CONFIG_PCI_IOV
151 /* disable iov and allow time for transactions to clear */
152 pci_disable_sriov(adapter->pdev);
153#endif
154
155 /* turn off device IOV mode */
156 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
157 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
158 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
159 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
160 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
161 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
162
163 /* set default pool back to 0 */
164 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
165 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
166 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
167
168 /* take a breather then clean up driver data */
169 msleep(100);
170 if (adapter->vfinfo)
171 kfree(adapter->vfinfo);
172 adapter->vfinfo = NULL;
173
174 adapter->num_vfs = 0;
175 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
176}
177
5eba3699
AV		 178static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
179{
180 u32 ctrl_ext;
181
182 /* Let firmware take over control of h/w */
183 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 185 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 186}
187
188static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
189{
190 u32 ctrl_ext;
191
192 /* Let firmware know the driver has taken over */
193 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
194 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 195 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 196}
9a799d71 197
e8e26350
PW		 198/*
199 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
200 * @adapter: pointer to adapter struct
201 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
202 * @queue: queue to map the corresponding interrupt to
203 * @msix_vector: the vector to map to the corresponding queue
204 *
205 */
206static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
207 u8 queue, u8 msix_vector)
9a799d71
AK		 208{
209 u32 ivar, index;
e8e26350
PW		 210 struct ixgbe_hw *hw = &adapter->hw;
211 switch (hw->mac.type) {
212 case ixgbe_mac_82598EB:
213 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
214 if (direction == -1)
215 direction = 0;
216 index = (((direction * 64) + queue) >> 2) & 0x1F;
217 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
218 ivar &= ~(0xFF << (8 * (queue & 0x3)));
219 ivar |= (msix_vector << (8 * (queue & 0x3)));
220 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
221 break;
222 case ixgbe_mac_82599EB:
223 if (direction == -1) {
224 /* other causes */
225 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
226 index = ((queue & 1) * 8);
227 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
228 ivar &= ~(0xFF << index);
229 ivar |= (msix_vector << index);
230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
231 break;
232 } else {
233 /* tx or rx causes */
234 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
235 index = ((16 * (queue & 1)) + (8 * direction));
236 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
237 ivar &= ~(0xFF << index);
238 ivar |= (msix_vector << index);
239 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
240 break;
241 }
242 default:
243 break;
244 }
9a799d71
AK		 245}
246
fe49f04a
AD		 247static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
248 u64 qmask)
249{
250 u32 mask;
251
252 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
253 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
255 } else {
256 mask = (qmask & 0xFFFFFFFF);
257 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
258 mask = (qmask >> 32);
259 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
260 }
261}
262
9a799d71 263static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 264 struct ixgbe_tx_buffer
265 *tx_buffer_info)
9a799d71 266{
e5a43549
AD		 267 if (tx_buffer_info->dma) {
268 if (tx_buffer_info->mapped_as_page)
269 pci_unmap_page(adapter->pdev,
270 tx_buffer_info->dma,
271 tx_buffer_info->length,
272 PCI_DMA_TODEVICE);
273 else
274 pci_unmap_single(adapter->pdev,
275 tx_buffer_info->dma,
276 tx_buffer_info->length,
277 PCI_DMA_TODEVICE);
278 tx_buffer_info->dma = 0;
279 }
9a799d71
AK		 280 if (tx_buffer_info->skb) {
281 dev_kfree_skb_any(tx_buffer_info->skb);
282 tx_buffer_info->skb = NULL;
283 }
44df32c5 284 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 285 /* tx_buffer_info must be completely set up in the transmit path */
286}
287
26f23d82
YZ		 288/**
289 * ixgbe_tx_is_paused - check if the tx ring is paused
290 * @adapter: the ixgbe adapter
291 * @tx_ring: the corresponding tx_ring
292 *
293 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
294 * corresponding TC of this tx_ring when checking TFCS.
295 *
296 * Returns : true if paused
297 */
298static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
299 struct ixgbe_ring *tx_ring)
300{
26f23d82
YZ		 301 u32 txoff = IXGBE_TFCS_TXOFF;
302
303#ifdef CONFIG_IXGBE_DCB
304 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 305 int tc;
26f23d82
YZ		 306 int reg_idx = tx_ring->reg_idx;
307 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
308
6837e895
PW		 309 switch (adapter->hw.mac.type) {
310 case ixgbe_mac_82598EB:
26f23d82
YZ		 311 tc = reg_idx >> 2;
312 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 313 break;
314 case ixgbe_mac_82599EB:
26f23d82
YZ		 315 tc = 0;
316 txoff = IXGBE_TFCS_TXOFF;
317 if (dcb_i == 8) {
318 /* TC0, TC1 */
319 tc = reg_idx >> 5;
320 if (tc == 2) /* TC2, TC3 */
321 tc += (reg_idx - 64) >> 4;
322 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
323 tc += 1 + ((reg_idx - 96) >> 3);
324 } else if (dcb_i == 4) {
325 /* TC0, TC1 */
326 tc = reg_idx >> 6;
327 if (tc == 1) {
328 tc += (reg_idx - 64) >> 5;
329 if (tc == 2) /* TC2, TC3 */
330 tc += (reg_idx - 96) >> 4;
331 }
332 }
6837e895
PW		 333 break;
334 default:
335 tc = 0;
26f23d82
YZ		 336 }
337 txoff <<= tc;
338 }
339#endif
340 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
341}
342
9a799d71 343static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 344 struct ixgbe_ring *tx_ring,
345 unsigned int eop)
9a799d71 346{
e01c31a5 347 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 348
9a799d71 349 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 350 * check with the clearing of time_stamp and movement of eop */
9a799d71 351 adapter->detect_tx_hung = false;
44df32c5 352 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 353 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 354 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 355 /* detected Tx unit hang */
e01c31a5
JB		 356 union ixgbe_adv_tx_desc *tx_desc;
357 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 358 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 359 " Tx Queue <%d>\n"
360 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 361 " next_to_use <%x>\n"
362 " next_to_clean <%x>\n"
363 "tx_buffer_info[next_to_clean]\n"
364 " time_stamp <%lx>\n"
e01c31a5
JB		 365 " jiffies <%lx>\n",
366 tx_ring->queue_index,
44df32c5
AD		 367 IXGBE_READ_REG(hw, tx_ring->head),
368 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 369 tx_ring->next_to_use, eop,
370 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 371 return true;
372 }
373
374 return false;
375}
376
b4617240
PW		 377#define IXGBE_MAX_TXD_PWR 14
378#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 379
380/* Tx Descriptors needed, worst case */
381#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
382 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
383#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 384 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 385
e01c31a5
JB		 386static void ixgbe_tx_timeout(struct net_device *netdev);
387
9a799d71
AK		 388/**
389 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 390 * @q_vector: structure containing interrupt and ring information
e01c31a5 391 * @tx_ring: tx ring to clean
9a799d71 392 **/
fe49f04a 393static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 394 struct ixgbe_ring *tx_ring)
9a799d71 395{
fe49f04a 396 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 397 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 398 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
399 struct ixgbe_tx_buffer *tx_buffer_info;
400 unsigned int i, eop, count = 0;
e01c31a5 401 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 402
403 i = tx_ring->next_to_clean;
12207e49
PWJ		 404 eop = tx_ring->tx_buffer_info[i].next_to_watch;
405 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
406
407 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 408 (count < tx_ring->work_limit)) {
12207e49
PWJ		 409 bool cleaned = false;
410 for ( ; !cleaned; count++) {
411 struct sk_buff *skb;
9a799d71
AK		 412 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
413 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 414 cleaned = (i == eop);
e01c31a5 415 skb = tx_buffer_info->skb;
9a799d71 416
12207e49 417 if (cleaned && skb) {
e092be60 418 unsigned int segs, bytecount;
3d8fd385 419 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 420
421 /* gso_segs is currently only valid for tcp */
e092be60 422 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 423#ifdef IXGBE_FCOE
424 /* adjust for FCoE Sequence Offload */
425 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
426 && (skb->protocol == htons(ETH_P_FCOE)) &&
427 skb_is_gso(skb)) {
428 hlen = skb_transport_offset(skb) +
429 sizeof(struct fc_frame_header) +
430 sizeof(struct fcoe_crc_eof);
431 segs = DIV_ROUND_UP(skb->len - hlen,
432 skb_shinfo(skb)->gso_size);
433 }
434#endif /* IXGBE_FCOE */
e092be60 435 /* multiply data chunks by size of headers */
3d8fd385 436 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 437 total_packets += segs;
438 total_bytes += bytecount;
e092be60 439 }
e01c31a5 440
9a799d71 441 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 442 tx_buffer_info);
9a799d71 443
12207e49
PWJ		 444 tx_desc->wb.status = 0;
445
9a799d71
AK		 446 i++;
447 if (i == tx_ring->count)
448 i = 0;
e01c31a5 449 }
12207e49
PWJ		 450
451 eop = tx_ring->tx_buffer_info[i].next_to_watch;
452 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
453 }
454
9a799d71
AK		 455 tx_ring->next_to_clean = i;
456
e092be60 457#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 458 if (unlikely(count && netif_carrier_ok(netdev) &&
459 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 460 /* Make sure that anybody stopping the queue after this
461 * sees the new next_to_clean.
462 */
463 smp_mb();
30eba97a
AV		 464 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
465 !test_bit(__IXGBE_DOWN, &adapter->state)) {
466 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 467 ++tx_ring->restart_queue;
30eba97a 468 }
e092be60 469 }
9a799d71 470
e01c31a5
JB		 471 if (adapter->detect_tx_hung) {
472 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
473 /* schedule immediate reset if we believe we hung */
474 DPRINTK(PROBE, INFO,
475 "tx hang %d detected, resetting adapter\n",
476 adapter->tx_timeout_count + 1);
477 ixgbe_tx_timeout(adapter->netdev);
478 }
479 }
9a799d71 480
e01c31a5 481 /* re-arm the interrupt */
fe49f04a
AD		 482 if (count >= tx_ring->work_limit)
483 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 484
e01c31a5
JB		 485 tx_ring->total_bytes += total_bytes;
486 tx_ring->total_packets += total_packets;
e01c31a5 487 tx_ring->stats.packets += total_packets;
12207e49 488 tx_ring->stats.bytes += total_bytes;
9a1a69ad 489 return (count < tx_ring->work_limit);
9a799d71
AK		 490}
491
5dd2d332 492#ifdef CONFIG_IXGBE_DCA
bd0362dd 493static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 494 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 495{
496 u32 rxctrl;
497 int cpu = get_cpu();
4a0b9ca0 498 int q = rx_ring->reg_idx;
bd0362dd 499
3a581073 500 if (rx_ring->cpu != cpu) {
bd0362dd 501 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 502 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
503 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
504 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
505 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
506 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
507 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
508 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
509 }
bd0362dd
JC		 510 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
511 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 512 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
513 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 514 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 516 rx_ring->cpu = cpu;
bd0362dd
JC		 517 }
518 put_cpu();
519}
520
521static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 522 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 523{
524 u32 txctrl;
525 int cpu = get_cpu();
4a0b9ca0 526 int q = tx_ring->reg_idx;
ee5f784a 527 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 528
3a581073 529 if (tx_ring->cpu != cpu) {
e8e26350 530 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 531 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 532 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
533 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 534 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
535 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 536 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 537 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 538 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
539 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 540 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
541 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
542 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 543 }
3a581073 544 tx_ring->cpu = cpu;
bd0362dd
JC		 545 }
546 put_cpu();
547}
548
549static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
550{
551 int i;
552
553 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
554 return;
555
e35ec126
AD		 556 /* always use CB2 mode, difference is masked in the CB driver */
557 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
558
bd0362dd 559 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 560 adapter->tx_ring[i]->cpu = -1;
561 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 562 }
563 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 564 adapter->rx_ring[i]->cpu = -1;
565 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 566 }
567}
568
569static int __ixgbe_notify_dca(struct device *dev, void *data)
570{
571 struct net_device *netdev = dev_get_drvdata(dev);
572 struct ixgbe_adapter *adapter = netdev_priv(netdev);
573 unsigned long event = *(unsigned long *)data;
574
575 switch (event) {
576 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 577 /* if we're already enabled, don't do it again */
578 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
579 break;
652f093f 580 if (dca_add_requester(dev) == 0) {
96b0e0f6 581 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 582 ixgbe_setup_dca(adapter);
583 break;
584 }
585 /* Fall Through since DCA is disabled. */
586 case DCA_PROVIDER_REMOVE:
587 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
588 dca_remove_requester(dev);
589 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
591 }
592 break;
593 }
594
652f093f 595 return 0;
bd0362dd
JC		 596}
597
5dd2d332 598#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 599/**
600 * ixgbe_receive_skb - Send a completed packet up the stack
601 * @adapter: board private structure
602 * @skb: packet to send up
177db6ff
MC		 603 * @status: hardware indication of status of receive
604 * @rx_ring: rx descriptor ring (for a specific queue) to setup
605 * @rx_desc: rx descriptor
9a799d71 606 **/
78b6f4ce 607static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 608 struct sk_buff *skb, u8 status,
fdaff1ce 609 struct ixgbe_ring *ring,
177db6ff 610 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 611{
78b6f4ce
HX		 612 struct ixgbe_adapter *adapter = q_vector->adapter;
613 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 614 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
615 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 616
fdaff1ce 617 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 618 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 619 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 620 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 621 else
78b6f4ce 622 napi_gro_receive(napi, skb);
177db6ff 623 } else {
8a62babf 624 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 625 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
626 else
627 netif_rx(skb);
9a799d71
AK		 628 }
629}
630
e59bd25d
AV		 631/**
632 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
633 * @adapter: address of board private structure
634 * @status_err: hardware indication of status of receive
635 * @skb: skb currently being received and modified
636 **/
9a799d71 637static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 638 union ixgbe_adv_rx_desc *rx_desc,
639 struct sk_buff *skb)
9a799d71 640{
8bae1b2b
DS		 641 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
642
9a799d71
AK		 643 skb->ip_summed = CHECKSUM_NONE;
644
712744be
JB		 645 /* Rx csum disabled */
646 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 647 return;
e59bd25d
AV		 648
649 /* if IP and error */
650 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
651 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 652 adapter->hw_csum_rx_error++;
653 return;
654 }
e59bd25d
AV		 655
656 if (!(status_err & IXGBE_RXD_STAT_L4CS))
657 return;
658
659 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 660 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
661
662 /*
663 * 82599 errata, UDP frames with a 0 checksum can be marked as
664 * checksum errors.
665 */
666 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
667 (adapter->hw.mac.type == ixgbe_mac_82599EB))
668 return;
669
e59bd25d
AV		 670 adapter->hw_csum_rx_error++;
671 return;
672 }
673
9a799d71 674 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 675 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 676}
677
e8e26350
PW		 678static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
679 struct ixgbe_ring *rx_ring, u32 val)
680{
681 /*
682 * Force memory writes to complete before letting h/w
683 * know there are new descriptors to fetch. (Only
684 * applicable for weak-ordered memory model archs,
685 * such as IA-64).
686 */
687 wmb();
688 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
689}
690
9a799d71
AK		 691/**
692 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
693 * @adapter: address of board private structure
694 **/
695static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 696 struct ixgbe_ring *rx_ring,
697 int cleaned_count)
9a799d71 698{
9a799d71
AK		 699 struct pci_dev *pdev = adapter->pdev;
700 union ixgbe_adv_rx_desc *rx_desc;
3a581073 701 struct ixgbe_rx_buffer *bi;
9a799d71 702 unsigned int i;
9a799d71
AK		 703
704 i = rx_ring->next_to_use;
3a581073 705 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 706
707 while (cleaned_count--) {
708 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
709
762f4c57 710 if (!bi->page_dma &&
6e455b89 711 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 712 if (!bi->page) {
762f4c57
JB		 713 bi->page = alloc_page(GFP_ATOMIC);
714 if (!bi->page) {
715 adapter->alloc_rx_page_failed++;
716 goto no_buffers;
717 }
718 bi->page_offset = 0;
719 } else {
720 /* use a half page if we're re-using */
721 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 722 }
762f4c57
JB		 723
724 bi->page_dma = pci_map_page(pdev, bi->page,
725 bi->page_offset,
726 (PAGE_SIZE / 2),
727 PCI_DMA_FROMDEVICE);
9a799d71
AK		 728 }
729
3a581073 730 if (!bi->skb) {
5ecc3614 731 struct sk_buff *skb;
7ca3bc58
JB		 732 /* netdev_alloc_skb reserves 32 bytes up front!! */
733 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
734 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 735
736 if (!skb) {
737 adapter->alloc_rx_buff_failed++;
738 goto no_buffers;
739 }
740
7ca3bc58
JB		 741 /* advance the data pointer to the next cache line */
742 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
743 - skb->data));
744
3a581073 745 bi->skb = skb;
4f57ca6e
JB		 746 bi->dma = pci_map_single(pdev, skb->data,
747 rx_ring->rx_buf_len,
3a581073 748 PCI_DMA_FROMDEVICE);
9a799d71
AK		 749 }
750 /* Refresh the desc even if buffer_addrs didn't change because
751 * each write-back erases this info. */
6e455b89 752 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 753 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
754 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 755 } else {
3a581073 756 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 757 }
758
759 i++;
760 if (i == rx_ring->count)
761 i = 0;
3a581073 762 bi = &rx_ring->rx_buffer_info[i];
9a799d71 763 }
7c6e0a43 764
9a799d71
AK		 765no_buffers:
766 if (rx_ring->next_to_use != i) {
767 rx_ring->next_to_use = i;
768 if (i-- == 0)
769 i = (rx_ring->count - 1);
770
e8e26350 771 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 772 }
773}
774
7c6e0a43
JB		 775static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
776{
777 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
778}
779
780static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
781{
782 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
783}
784
f8212f97
AD		 785static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
786{
787 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
788 IXGBE_RXDADV_RSCCNT_MASK) >>
789 IXGBE_RXDADV_RSCCNT_SHIFT;
790}
791
792/**
793 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
794 * @skb: pointer to the last skb in the rsc queue
94b982b2 795 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 796 *
797 * This function changes a queue full of hw rsc buffers into a completed
798 * packet. It uses the ->prev pointers to find the first packet and then
799 * turns it into the frag list owner.
800 **/
94b982b2
MC		 801static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
802 u64 *count)
f8212f97
AD		 803{
804 unsigned int frag_list_size = 0;
805
806 while (skb->prev) {
807 struct sk_buff *prev = skb->prev;
808 frag_list_size += skb->len;
809 skb->prev = NULL;
810 skb = prev;
94b982b2 811 *count += 1;
f8212f97
AD		 812 }
813
814 skb_shinfo(skb)->frag_list = skb->next;
815 skb->next = NULL;
816 skb->len += frag_list_size;
817 skb->data_len += frag_list_size;
818 skb->truesize += frag_list_size;
819 return skb;
820}
821
43634e82
MC		 822struct ixgbe_rsc_cb {
823 dma_addr_t dma;
824};
825
826#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
827
78b6f4ce 828static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 829 struct ixgbe_ring *rx_ring,
830 int *work_done, int work_to_do)
9a799d71 831{
78b6f4ce 832 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 833 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 834 struct pci_dev *pdev = adapter->pdev;
835 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
836 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
837 struct sk_buff *skb;
f8212f97 838 unsigned int i, rsc_count = 0;
7c6e0a43 839 u32 len, staterr;
177db6ff
MC		 840 u16 hdr_info;
841 bool cleaned = false;
9a799d71 842 int cleaned_count = 0;
d2f4fbe2 843 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 844#ifdef IXGBE_FCOE
845 int ddp_bytes = 0;
846#endif /* IXGBE_FCOE */
9a799d71
AK		 847
848 i = rx_ring->next_to_clean;
9a799d71
AK		 849 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
850 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
851 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 852
853 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 854 u32 upper_len = 0;
9a799d71
AK		 855 if (*work_done >= work_to_do)
856 break;
857 (*work_done)++;
858
3c945e5b 859 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 860 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 861 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
862 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 863 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 864 if (len > IXGBE_RX_HDR_SIZE)
865 len = IXGBE_RX_HDR_SIZE;
866 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 867 } else {
9a799d71 868 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 869 }
9a799d71
AK		 870
871 cleaned = true;
872 skb = rx_buffer_info->skb;
7ca3bc58 873 prefetch(skb->data);
9a799d71
AK		 874 rx_buffer_info->skb = NULL;
875
21fa4e66 876 if (rx_buffer_info->dma) {
43634e82
MC		 877 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
878 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
879 (!(skb->prev)))
880 /*
881 * When HWRSC is enabled, delay unmapping
882 * of the first packet. It carries the
883 * header information, HW may still
884 * access the header after the writeback.
885 * Only unmap it when EOP is reached
886 */
887 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
888 else
889 pci_unmap_single(pdev, rx_buffer_info->dma,
890 rx_ring->rx_buf_len,
891 PCI_DMA_FROMDEVICE);
4f57ca6e 892 rx_buffer_info->dma = 0;
9a799d71
AK		 893 skb_put(skb, len);
894 }
895
896 if (upper_len) {
897 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 898 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 899 rx_buffer_info->page_dma = 0;
900 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 901 rx_buffer_info->page,
902 rx_buffer_info->page_offset,
903 upper_len);
904
905 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
906 (page_count(rx_buffer_info->page) != 1))
907 rx_buffer_info->page = NULL;
908 else
909 get_page(rx_buffer_info->page);
9a799d71
AK		 910
911 skb->len += upper_len;
912 skb->data_len += upper_len;
913 skb->truesize += upper_len;
914 }
915
916 i++;
917 if (i == rx_ring->count)
918 i = 0;
9a799d71
AK		 919
920 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
921 prefetch(next_rxd);
9a799d71 922 cleaned_count++;
f8212f97 923
0c19d6af 924 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 925 rsc_count = ixgbe_get_rsc_count(rx_desc);
926
927 if (rsc_count) {
928 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
929 IXGBE_RXDADV_NEXTP_SHIFT;
930 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 931 } else {
932 next_buffer = &rx_ring->rx_buffer_info[i];
933 }
934
9a799d71 935 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 936 if (skb->prev)
94b982b2
MC		 937 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
938 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
fd3686a8 939 if (IXGBE_RSC_CB(skb)->dma) {
43634e82
MC		 940 pci_unmap_single(pdev, IXGBE_RSC_CB(skb)->dma,
941 rx_ring->rx_buf_len,
942 PCI_DMA_FROMDEVICE);
fd3686a8
MC		 943 IXGBE_RSC_CB(skb)->dma = 0;
944 }
94b982b2
MC		 945 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
946 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
947 else
948 rx_ring->rsc_count++;
949 rx_ring->rsc_flush++;
950 }
9a799d71
AK		 951 rx_ring->stats.packets++;
952 rx_ring->stats.bytes += skb->len;
953 } else {
6e455b89 954 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 955 rx_buffer_info->skb = next_buffer->skb;
956 rx_buffer_info->dma = next_buffer->dma;
957 next_buffer->skb = skb;
958 next_buffer->dma = 0;
959 } else {
960 skb->next = next_buffer->skb;
961 skb->next->prev = skb;
962 }
7ca3bc58 963 rx_ring->non_eop_descs++;
9a799d71
AK		 964 goto next_desc;
965 }
966
967 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
968 dev_kfree_skb_irq(skb);
969 goto next_desc;
970 }
971
8bae1b2b 972 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 973
974 /* probably a little skewed due to removing CRC */
975 total_rx_bytes += skb->len;
976 total_rx_packets++;
977
74ce8dd2 978 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 979#ifdef IXGBE_FCOE
980 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 981 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
982 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
983 if (!ddp_bytes)
332d4a7d 984 goto next_desc;
3d8fd385 985 }
332d4a7d 986#endif /* IXGBE_FCOE */
fdaff1ce 987 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 988
989next_desc:
990 rx_desc->wb.upper.status_error = 0;
991
992 /* return some buffers to hardware, one at a time is too slow */
993 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
994 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
995 cleaned_count = 0;
996 }
997
998 /* use prefetched values */
999 rx_desc = next_rxd;
f8212f97 1000 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1001
1002 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1003 }
1004
9a799d71
AK		 1005 rx_ring->next_to_clean = i;
1006 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1007
1008 if (cleaned_count)
1009 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1010
3d8fd385
YZ		 1011#ifdef IXGBE_FCOE
1012 /* include DDPed FCoE data */
1013 if (ddp_bytes > 0) {
1014 unsigned int mss;
1015
1016 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1017 sizeof(struct fc_frame_header) -
1018 sizeof(struct fcoe_crc_eof);
1019 if (mss > 512)
1020 mss &= ~511;
1021 total_rx_bytes += ddp_bytes;
1022 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1023 }
1024#endif /* IXGBE_FCOE */
1025
f494e8fa
AV		 1026 rx_ring->total_packets += total_rx_packets;
1027 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1028 netdev->stats.rx_bytes += total_rx_bytes;
1029 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1030
9a799d71
AK		 1031 return cleaned;
1032}
1033
021230d4 1034static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1035/**
1036 * ixgbe_configure_msix - Configure MSI-X hardware
1037 * @adapter: board private structure
1038 *
1039 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1040 * interrupts.
1041 **/
1042static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1043{
021230d4
AV		 1044 struct ixgbe_q_vector *q_vector;
1045 int i, j, q_vectors, v_idx, r_idx;
1046 u32 mask;
9a799d71 1047
021230d4 1048 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1049
4df10466
JB		 1050 /*
1051 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1052 * corresponding register.
1053 */
1054 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1055 q_vector = adapter->q_vector[v_idx];
984b3f57 1056 /* XXX for_each_set_bit(...) */
021230d4 1057 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1058 adapter->num_rx_queues);
021230d4
AV		 1059
1060 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1061 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1062 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1063 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1064 adapter->num_rx_queues,
1065 r_idx + 1);
021230d4
AV		 1066 }
1067 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1068 adapter->num_tx_queues);
021230d4
AV		 1069
1070 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1071 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1072 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1073 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1074 adapter->num_tx_queues,
1075 r_idx + 1);
021230d4
AV		 1076 }
1077
021230d4 1078 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1079 /* tx only */
1080 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1081 else if (q_vector->rxr_count)
f7554a2b
NS		 1082 /* rx or mixed */
1083 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1084
fe49f04a 1085 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1086 }
1087
e8e26350
PW		 1088 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1089 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1090 v_idx);
1091 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1092 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1093 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1094
41fb9248 1095 /* set up to autoclear timer, and the vectors */
021230d4 1096 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1097 if (adapter->num_vfs)
1098 mask &= ~(IXGBE_EIMS_OTHER |
1099 IXGBE_EIMS_MAILBOX |
1100 IXGBE_EIMS_LSC);
1101 else
1102 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1103 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1104}
1105
f494e8fa
AV		 1106enum latency_range {
1107 lowest_latency = 0,
1108 low_latency = 1,
1109 bulk_latency = 2,
1110 latency_invalid = 255
1111};
1112
1113/**
1114 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1115 * @adapter: pointer to adapter
1116 * @eitr: eitr setting (ints per sec) to give last timeslice
1117 * @itr_setting: current throttle rate in ints/second
1118 * @packets: the number of packets during this measurement interval
1119 * @bytes: the number of bytes during this measurement interval
1120 *
1121 * Stores a new ITR value based on packets and byte
1122 * counts during the last interrupt. The advantage of per interrupt
1123 * computation is faster updates and more accurate ITR for the current
1124 * traffic pattern. Constants in this function were computed
1125 * based on theoretical maximum wire speed and thresholds were set based
1126 * on testing data as well as attempting to minimize response time
1127 * while increasing bulk throughput.
1128 * this functionality is controlled by the InterruptThrottleRate module
1129 * parameter (see ixgbe_param.c)
1130 **/
1131static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1132 u32 eitr, u8 itr_setting,
1133 int packets, int bytes)
f494e8fa
AV		 1134{
1135 unsigned int retval = itr_setting;
1136 u32 timepassed_us;
1137 u64 bytes_perint;
1138
1139 if (packets == 0)
1140 goto update_itr_done;
1141
1142
1143 /* simple throttlerate management
1144 * 0-20MB/s lowest (100000 ints/s)
1145 * 20-100MB/s low (20000 ints/s)
1146 * 100-1249MB/s bulk (8000 ints/s)
1147 */
1148 /* what was last interrupt timeslice? */
1149 timepassed_us = 1000000/eitr;
1150 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1151
1152 switch (itr_setting) {
1153 case lowest_latency:
1154 if (bytes_perint > adapter->eitr_low)
1155 retval = low_latency;
1156 break;
1157 case low_latency:
1158 if (bytes_perint > adapter->eitr_high)
1159 retval = bulk_latency;
1160 else if (bytes_perint <= adapter->eitr_low)
1161 retval = lowest_latency;
1162 break;
1163 case bulk_latency:
1164 if (bytes_perint <= adapter->eitr_high)
1165 retval = low_latency;
1166 break;
1167 }
1168
1169update_itr_done:
1170 return retval;
1171}
1172
509ee935
JB		 1173/**
1174 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1175 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1176 *
1177 * This function is made to be called by ethtool and by the driver
1178 * when it needs to update EITR registers at runtime. Hardware
1179 * specific quirks/differences are taken care of here.
1180 */
fe49f04a 1181void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1182{
fe49f04a 1183 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1184 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1185 int v_idx = q_vector->v_idx;
1186 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1187
509ee935
JB		 1188 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1189 /* must write high and low 16 bits to reset counter */
1190 itr_reg |= (itr_reg << 16);
1191 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1192 /*
1193 * 82599 can support a value of zero, so allow it for
1194 * max interrupt rate, but there is an errata where it can
1195 * not be zero with RSC
1196 */
1197 if (itr_reg == 8 &&
1198 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1199 itr_reg = 0;
1200
509ee935
JB		 1201 /*
1202 * set the WDIS bit to not clear the timer bits and cause an
1203 * immediate assertion of the interrupt
1204 */
1205 itr_reg |= IXGBE_EITR_CNT_WDIS;
1206 }
1207 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1208}
1209
f494e8fa
AV		 1210static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1211{
1212 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1213 u32 new_itr;
1214 u8 current_itr, ret_itr;
fe49f04a 1215 int i, r_idx;
f494e8fa
AV		 1216 struct ixgbe_ring *rx_ring, *tx_ring;
1217
1218 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1219 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1220 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1221 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1222 q_vector->tx_itr,
1223 tx_ring->total_packets,
1224 tx_ring->total_bytes);
f494e8fa
AV		 1225 /* if the result for this queue would decrease interrupt
1226 * rate for this vector then use that result */
30efa5a3 1227 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1228 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1229 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1230 r_idx + 1);
f494e8fa
AV		 1231 }
1232
1233 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1234 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1235 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1236 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1237 q_vector->rx_itr,
1238 rx_ring->total_packets,
1239 rx_ring->total_bytes);
f494e8fa
AV		 1240 /* if the result for this queue would decrease interrupt
1241 * rate for this vector then use that result */
30efa5a3 1242 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1243 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1244 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1245 r_idx + 1);
f494e8fa
AV		 1246 }
1247
30efa5a3 1248 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1249
1250 switch (current_itr) {
1251 /* counts and packets in update_itr are dependent on these numbers */
1252 case lowest_latency:
1253 new_itr = 100000;
1254 break;
1255 case low_latency:
1256 new_itr = 20000; /* aka hwitr = ~200 */
1257 break;
1258 case bulk_latency:
1259 default:
1260 new_itr = 8000;
1261 break;
1262 }
1263
1264 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1265 /* do an exponential smoothing */
1266 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1267
1268 /* save the algorithm value here, not the smoothed one */
1269 q_vector->eitr = new_itr;
fe49f04a
AD		 1270
1271 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1272 }
1273
1274 return;
1275}
1276
0befdb3e
JB		 1277static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1278{
1279 struct ixgbe_hw *hw = &adapter->hw;
1280
1281 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1282 (eicr & IXGBE_EICR_GPI_SDP1)) {
1283 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1284 /* write to clear the interrupt */
1285 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1286 }
1287}
cf8280ee 1288
e8e26350
PW		 1289static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1290{
1291 struct ixgbe_hw *hw = &adapter->hw;
1292
1293 if (eicr & IXGBE_EICR_GPI_SDP1) {
1294 /* Clear the interrupt */
1295 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1296 schedule_work(&adapter->multispeed_fiber_task);
1297 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1298 /* Clear the interrupt */
1299 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1300 schedule_work(&adapter->sfp_config_module_task);
1301 } else {
1302 /* Interrupt isn't for us... */
1303 return;
1304 }
1305}
1306
cf8280ee
JB		 1307static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1308{
1309 struct ixgbe_hw *hw = &adapter->hw;
1310
1311 adapter->lsc_int++;
1312 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1313 adapter->link_check_timeout = jiffies;
1314 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1315 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1316 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1317 schedule_work(&adapter->watchdog_task);
1318 }
1319}
1320
9a799d71
AK		 1321static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1322{
1323 struct net_device *netdev = data;
1324 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1325 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1326 u32 eicr;
1327
1328 /*
1329 * Workaround for Silicon errata. Use clear-by-write instead
1330 * of clear-by-read. Reading with EICS will return the
1331 * interrupt causes without clearing, which later be done
1332 * with the write to EICR.
1333 */
1334 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1335 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1336
cf8280ee
JB		 1337 if (eicr & IXGBE_EICR_LSC)
1338 ixgbe_check_lsc(adapter);
d4f80882 1339
1cdd1ec8
GR		 1340 if (eicr & IXGBE_EICR_MAILBOX)
1341 ixgbe_msg_task(adapter);
1342
e8e26350
PW		 1343 if (hw->mac.type == ixgbe_mac_82598EB)
1344 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1345
c4cf55e5 1346 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1347 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1348
1349 /* Handle Flow Director Full threshold interrupt */
1350 if (eicr & IXGBE_EICR_FLOW_DIR) {
1351 int i;
1352 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1353 /* Disable transmits before FDIR Re-initialization */
1354 netif_tx_stop_all_queues(netdev);
1355 for (i = 0; i < adapter->num_tx_queues; i++) {
1356 struct ixgbe_ring *tx_ring =
4a0b9ca0 1357 adapter->tx_ring[i];
c4cf55e5
PWJ		 1358 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1359 &tx_ring->reinit_state))
1360 schedule_work(&adapter->fdir_reinit_task);
1361 }
1362 }
1363 }
d4f80882
AV		 1364 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1365 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1366
1367 return IRQ_HANDLED;
1368}
1369
fe49f04a
AD		 1370static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1371 u64 qmask)
1372{
1373 u32 mask;
1374
1375 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1376 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1377 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1378 } else {
1379 mask = (qmask & 0xFFFFFFFF);
1380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1381 mask = (qmask >> 32);
1382 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1383 }
1384 /* skip the flush */
1385}
1386
1387static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1388 u64 qmask)
1389{
1390 u32 mask;
1391
1392 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1393 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1395 } else {
1396 mask = (qmask & 0xFFFFFFFF);
1397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1398 mask = (qmask >> 32);
1399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1400 }
1401 /* skip the flush */
1402}
1403
9a799d71
AK		 1404static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1405{
021230d4
AV		 1406 struct ixgbe_q_vector *q_vector = data;
1407 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1408 struct ixgbe_ring *tx_ring;
021230d4
AV		 1409 int i, r_idx;
1410
1411 if (!q_vector->txr_count)
1412 return IRQ_HANDLED;
1413
1414 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1415 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1416 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1417 tx_ring->total_bytes = 0;
1418 tx_ring->total_packets = 0;
021230d4 1419 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1420 r_idx + 1);
021230d4 1421 }
9a799d71 1422
9b471446 1423 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1424 napi_schedule(&q_vector->napi);
1425
9a799d71
AK		 1426 return IRQ_HANDLED;
1427}
1428
021230d4
AV		 1429/**
1430 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1431 * @irq: unused
1432 * @data: pointer to our q_vector struct for this interrupt vector
1433 **/
9a799d71
AK		 1434static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1435{
021230d4
AV		 1436 struct ixgbe_q_vector *q_vector = data;
1437 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1438 struct ixgbe_ring *rx_ring;
021230d4 1439 int r_idx;
30efa5a3 1440 int i;
021230d4
AV		 1441
1442 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1443 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1444 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1445 rx_ring->total_bytes = 0;
1446 rx_ring->total_packets = 0;
1447 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1448 r_idx + 1);
1449 }
1450
021230d4
AV		 1451 if (!q_vector->rxr_count)
1452 return IRQ_HANDLED;
1453
021230d4 1454 /* disable interrupts on this vector only */
9b471446 1455 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1456 napi_schedule(&q_vector->napi);
021230d4
AV		 1457
1458 return IRQ_HANDLED;
1459}
1460
1461static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1462{
91281fd3
AD		 1463 struct ixgbe_q_vector *q_vector = data;
1464 struct ixgbe_adapter *adapter = q_vector->adapter;
1465 struct ixgbe_ring *ring;
1466 int r_idx;
1467 int i;
1468
1469 if (!q_vector->txr_count && !q_vector->rxr_count)
1470 return IRQ_HANDLED;
1471
1472 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1473 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1474 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1475 ring->total_bytes = 0;
1476 ring->total_packets = 0;
1477 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1478 r_idx + 1);
1479 }
1480
1481 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1482 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1483 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1484 ring->total_bytes = 0;
1485 ring->total_packets = 0;
1486 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1487 r_idx + 1);
1488 }
1489
9b471446 1490 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1491 napi_schedule(&q_vector->napi);
9a799d71 1492
9a799d71
AK		 1493 return IRQ_HANDLED;
1494}
1495
021230d4
AV		 1496/**
1497 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1498 * @napi: napi struct with our devices info in it
1499 * @budget: amount of work driver is allowed to do this pass, in packets
1500 *
f0848276
JB		 1501 * This function is optimized for cleaning one queue only on a single
1502 * q_vector!!!
021230d4 1503 **/
9a799d71
AK		 1504static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1505{
021230d4 1506 struct ixgbe_q_vector *q_vector =
b4617240 1507 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1508 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1509 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1510 int work_done = 0;
021230d4 1511 long r_idx;
9a799d71 1512
021230d4 1513 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1514 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1515#ifdef CONFIG_IXGBE_DCA
bd0362dd 1516 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1517 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1518#endif
9a799d71 1519
78b6f4ce 1520 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1521
021230d4
AV		 1522 /* If all Rx work done, exit the polling mode */
1523 if (work_done < budget) {
288379f0 1524 napi_complete(napi);
f7554a2b 1525 if (adapter->rx_itr_setting & 1)
f494e8fa 1526 ixgbe_set_itr_msix(q_vector);
9a799d71 1527 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1528 ixgbe_irq_enable_queues(adapter,
1529 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1530 }
1531
1532 return work_done;
1533}
1534
f0848276 1535/**
91281fd3 1536 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1537 * @napi: napi struct with our devices info in it
1538 * @budget: amount of work driver is allowed to do this pass, in packets
1539 *
1540 * This function will clean more than one rx queue associated with a
1541 * q_vector.
1542 **/
91281fd3 1543static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1544{
1545 struct ixgbe_q_vector *q_vector =
1546 container_of(napi, struct ixgbe_q_vector, napi);
1547 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1548 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1549 int work_done = 0, i;
1550 long r_idx;
91281fd3
AD		 1551 bool tx_clean_complete = true;
1552
1553 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1554 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1555 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1556#ifdef CONFIG_IXGBE_DCA
1557 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1558 ixgbe_update_tx_dca(adapter, ring);
1559#endif
1560 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1561 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1562 r_idx + 1);
1563 }
f0848276
JB		 1564
1565 /* attempt to distribute budget to each queue fairly, but don't allow
1566 * the budget to go below 1 because we'll exit polling */
1567 budget /= (q_vector->rxr_count ?: 1);
1568 budget = max(budget, 1);
1569 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1570 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1571 ring = adapter->rx_ring[r_idx];
5dd2d332 1572#ifdef CONFIG_IXGBE_DCA
f0848276 1573 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1574 ixgbe_update_rx_dca(adapter, ring);
f0848276 1575#endif
91281fd3 1576 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1577 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1578 r_idx + 1);
1579 }
1580
1581 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1582 ring = adapter->rx_ring[r_idx];
f0848276 1583 /* If all Rx work done, exit the polling mode */
7f821875 1584 if (work_done < budget) {
288379f0 1585 napi_complete(napi);
f7554a2b 1586 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1587 ixgbe_set_itr_msix(q_vector);
1588 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1589 ixgbe_irq_enable_queues(adapter,
1590 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1591 return 0;
1592 }
1593
1594 return work_done;
1595}
91281fd3
AD		 1596
1597/**
1598 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1599 * @napi: napi struct with our devices info in it
1600 * @budget: amount of work driver is allowed to do this pass, in packets
1601 *
1602 * This function is optimized for cleaning one queue only on a single
1603 * q_vector!!!
1604 **/
1605static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1606{
1607 struct ixgbe_q_vector *q_vector =
1608 container_of(napi, struct ixgbe_q_vector, napi);
1609 struct ixgbe_adapter *adapter = q_vector->adapter;
1610 struct ixgbe_ring *tx_ring = NULL;
1611 int work_done = 0;
1612 long r_idx;
1613
1614 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 1615 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1616#ifdef CONFIG_IXGBE_DCA
1617 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1618 ixgbe_update_tx_dca(adapter, tx_ring);
1619#endif
1620
1621 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1622 work_done = budget;
1623
f7554a2b 1624 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1625 if (work_done < budget) {
1626 napi_complete(napi);
f7554a2b 1627 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1628 ixgbe_set_itr_msix(q_vector);
1629 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1630 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1631 }
1632
1633 return work_done;
1634}
1635
021230d4 1636static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1637 int r_idx)
021230d4 1638{
7a921c93
AD		 1639 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1640
1641 set_bit(r_idx, q_vector->rxr_idx);
1642 q_vector->rxr_count++;
021230d4
AV		 1643}
1644
1645static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1646 int t_idx)
021230d4 1647{
7a921c93
AD		 1648 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1649
1650 set_bit(t_idx, q_vector->txr_idx);
1651 q_vector->txr_count++;
021230d4
AV		 1652}
1653
9a799d71 1654/**
021230d4
AV		 1655 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1656 * @adapter: board private structure to initialize
1657 * @vectors: allotted vector count for descriptor rings
9a799d71 1658 *
021230d4
AV		 1659 * This function maps descriptor rings to the queue-specific vectors
1660 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1661 * one vector per ring/queue, but on a constrained vector budget, we
1662 * group the rings as "efficiently" as possible. You would add new
1663 * mapping configurations in here.
9a799d71 1664 **/
021230d4 1665static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1666 int vectors)
021230d4
AV		 1667{
1668 int v_start = 0;
1669 int rxr_idx = 0, txr_idx = 0;
1670 int rxr_remaining = adapter->num_rx_queues;
1671 int txr_remaining = adapter->num_tx_queues;
1672 int i, j;
1673 int rqpv, tqpv;
1674 int err = 0;
1675
1676 /* No mapping required if MSI-X is disabled. */
1677 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1678 goto out;
9a799d71 1679
021230d4
AV		 1680 /*
1681 * The ideal configuration...
1682 * We have enough vectors to map one per queue.
1683 */
1684 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1685 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1686 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1687
021230d4
AV		 1688 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1689 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1690
9a799d71 1691 goto out;
021230d4 1692 }
9a799d71 1693
021230d4
AV		 1694 /*
1695 * If we don't have enough vectors for a 1-to-1
1696 * mapping, we'll have to group them so there are
1697 * multiple queues per vector.
1698 */
1699 /* Re-adjusting *qpv takes care of the remainder. */
1700 for (i = v_start; i < vectors; i++) {
1701 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1702 for (j = 0; j < rqpv; j++) {
1703 map_vector_to_rxq(adapter, i, rxr_idx);
1704 rxr_idx++;
1705 rxr_remaining--;
1706 }
1707 }
1708 for (i = v_start; i < vectors; i++) {
1709 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1710 for (j = 0; j < tqpv; j++) {
1711 map_vector_to_txq(adapter, i, txr_idx);
1712 txr_idx++;
1713 txr_remaining--;
9a799d71 1714 }
9a799d71
AK		 1715 }
1716
021230d4
AV		 1717out:
1718 return err;
1719}
1720
1721/**
1722 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1723 * @adapter: board private structure
1724 *
1725 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1726 * interrupts from the kernel.
1727 **/
1728static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1729{
1730 struct net_device *netdev = adapter->netdev;
1731 irqreturn_t (*handler)(int, void *);
1732 int i, vector, q_vectors, err;
cb13fc20 1733 int ri=0, ti=0;
021230d4
AV		 1734
1735 /* Decrement for Other and TCP Timer vectors */
1736 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1737
1738 /* Map the Tx/Rx rings to the vectors we were allotted. */
1739 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1740 if (err)
1741 goto out;
1742
1743#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1744 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1745 &ixgbe_msix_clean_many)
021230d4 1746 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1747 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1748
1749 if(handler == &ixgbe_msix_clean_rx) {
1750 sprintf(adapter->name[vector], "%s-%s-%d",
1751 netdev->name, "rx", ri++);
1752 }
1753 else if(handler == &ixgbe_msix_clean_tx) {
1754 sprintf(adapter->name[vector], "%s-%s-%d",
1755 netdev->name, "tx", ti++);
1756 }
1757 else
1758 sprintf(adapter->name[vector], "%s-%s-%d",
1759 netdev->name, "TxRx", vector);
1760
021230d4 1761 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1762 handler, 0, adapter->name[vector],
7a921c93 1763 adapter->q_vector[vector]);
9a799d71
AK		 1764 if (err) {
1765 DPRINTK(PROBE, ERR,
b4617240
PW		 1766 "request_irq failed for MSIX interrupt "
1767 "Error: %d\n", err);
021230d4 1768 goto free_queue_irqs;
9a799d71 1769 }
9a799d71
AK		 1770 }
1771
021230d4
AV		 1772 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1773 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1774 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1775 if (err) {
1776 DPRINTK(PROBE, ERR,
1777 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1778 goto free_queue_irqs;
9a799d71
AK		 1779 }
1780
9a799d71
AK		 1781 return 0;
1782
021230d4
AV		 1783free_queue_irqs:
1784 for (i = vector - 1; i >= 0; i--)
1785 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1786 adapter->q_vector[i]);
021230d4
AV		 1787 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1788 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1789 kfree(adapter->msix_entries);
1790 adapter->msix_entries = NULL;
021230d4 1791out:
9a799d71
AK		 1792 return err;
1793}
1794
f494e8fa
AV		 1795static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1796{
7a921c93 1797 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1798 u8 current_itr;
1799 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 1800 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1801 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 1802
30efa5a3 1803 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1804 q_vector->tx_itr,
1805 tx_ring->total_packets,
1806 tx_ring->total_bytes);
30efa5a3 1807 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1808 q_vector->rx_itr,
1809 rx_ring->total_packets,
1810 rx_ring->total_bytes);
f494e8fa 1811
30efa5a3 1812 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1813
1814 switch (current_itr) {
1815 /* counts and packets in update_itr are dependent on these numbers */
1816 case lowest_latency:
1817 new_itr = 100000;
1818 break;
1819 case low_latency:
1820 new_itr = 20000; /* aka hwitr = ~200 */
1821 break;
1822 case bulk_latency:
1823 new_itr = 8000;
1824 break;
1825 default:
1826 break;
1827 }
1828
1829 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1830 /* do an exponential smoothing */
1831 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1832
1833 /* save the algorithm value here, not the smoothed one */
1834 q_vector->eitr = new_itr;
fe49f04a
AD		 1835
1836 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1837 }
1838
1839 return;
1840}
1841
79aefa45
AD		 1842/**
1843 * ixgbe_irq_enable - Enable default interrupt generation settings
1844 * @adapter: board private structure
1845 **/
1846static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1847{
1848 u32 mask;
835462fc
NS		 1849
1850 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1851 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1852 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1853 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1854 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1855 mask |= IXGBE_EIMS_GPI_SDP1;
1856 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 1857 if (adapter->num_vfs)
1858 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 1859 }
c4cf55e5
PWJ		 1860 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1861 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1862 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1863
79aefa45 1864 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1865 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 1866 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 1867
1868 if (adapter->num_vfs > 32) {
1869 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1871 }
79aefa45 1872}
021230d4 1873
9a799d71 1874/**
021230d4 1875 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1876 * @irq: interrupt number
1877 * @data: pointer to a network interface device structure
9a799d71
AK		 1878 **/
1879static irqreturn_t ixgbe_intr(int irq, void *data)
1880{
1881 struct net_device *netdev = data;
1882 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1883 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1884 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1885 u32 eicr;
1886
54037505
DS		 1887 /*
1888 * Workaround for silicon errata. Mask the interrupts
1889 * before the read of EICR.
1890 */
1891 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1892
021230d4
AV		 1893 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1894 * therefore no explict interrupt disable is necessary */
1895 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1896 if (!eicr) {
1897 /* shared interrupt alert!
1898 * make sure interrupts are enabled because the read will
1899 * have disabled interrupts due to EIAM */
1900 ixgbe_irq_enable(adapter);
9a799d71 1901 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1902 }
9a799d71 1903
cf8280ee
JB		 1904 if (eicr & IXGBE_EICR_LSC)
1905 ixgbe_check_lsc(adapter);
021230d4 1906
e8e26350
PW		 1907 if (hw->mac.type == ixgbe_mac_82599EB)
1908 ixgbe_check_sfp_event(adapter, eicr);
1909
0befdb3e
JB		 1910 ixgbe_check_fan_failure(adapter, eicr);
1911
7a921c93 1912 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 1913 adapter->tx_ring[0]->total_packets = 0;
1914 adapter->tx_ring[0]->total_bytes = 0;
1915 adapter->rx_ring[0]->total_packets = 0;
1916 adapter->rx_ring[0]->total_bytes = 0;
021230d4 1917 /* would disable interrupts here but EIAM disabled it */
7a921c93 1918 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1919 }
1920
1921 return IRQ_HANDLED;
1922}
1923
021230d4
AV		 1924static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1925{
1926 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1927
1928 for (i = 0; i < q_vectors; i++) {
7a921c93 1929 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1930 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1931 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1932 q_vector->rxr_count = 0;
1933 q_vector->txr_count = 0;
1934 }
1935}
1936
9a799d71
AK		 1937/**
1938 * ixgbe_request_irq - initialize interrupts
1939 * @adapter: board private structure
1940 *
1941 * Attempts to configure interrupts using the best available
1942 * capabilities of the hardware and kernel.
1943 **/
021230d4 1944static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1945{
1946 struct net_device *netdev = adapter->netdev;
021230d4 1947 int err;
9a799d71 1948
021230d4
AV		 1949 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1950 err = ixgbe_request_msix_irqs(adapter);
1951 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 1952 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 1953 netdev->name, netdev);
021230d4 1954 } else {
a0607fd3 1955 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 1956 netdev->name, netdev);
9a799d71
AK		 1957 }
1958
9a799d71
AK		 1959 if (err)
1960 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1961
9a799d71
AK		 1962 return err;
1963}
1964
1965static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1966{
1967 struct net_device *netdev = adapter->netdev;
1968
1969 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1970 int i, q_vectors;
9a799d71 1971
021230d4
AV		 1972 q_vectors = adapter->num_msix_vectors;
1973
1974 i = q_vectors - 1;
9a799d71 1975 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1976
021230d4
AV		 1977 i--;
1978 for (; i >= 0; i--) {
1979 free_irq(adapter->msix_entries[i].vector,
7a921c93 1980 adapter->q_vector[i]);
021230d4
AV		 1981 }
1982
1983 ixgbe_reset_q_vectors(adapter);
1984 } else {
1985 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1986 }
1987}
1988
22d5a71b
JB		 1989/**
1990 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1991 * @adapter: board private structure
1992 **/
1993static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1994{
835462fc
NS		 1995 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1996 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1997 } else {
1998 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1999 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2000 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2001 if (adapter->num_vfs > 32)
2002 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2003 }
2004 IXGBE_WRITE_FLUSH(&adapter->hw);
2005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2006 int i;
2007 for (i = 0; i < adapter->num_msix_vectors; i++)
2008 synchronize_irq(adapter->msix_entries[i].vector);
2009 } else {
2010 synchronize_irq(adapter->pdev->irq);
2011 }
2012}
2013
9a799d71
AK		 2014/**
2015 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2016 *
2017 **/
2018static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2019{
9a799d71
AK		 2020 struct ixgbe_hw *hw = &adapter->hw;
2021
021230d4 2022 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 2023 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2024
e8e26350
PW		 2025 ixgbe_set_ivar(adapter, 0, 0, 0);
2026 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2027
2028 map_vector_to_rxq(adapter, 0, 0);
2029 map_vector_to_txq(adapter, 0, 0);
2030
2031 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2032}
2033
2034/**
3a581073 2035 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2036 * @adapter: board private structure
2037 *
2038 * Configure the Tx unit of the MAC after a reset.
2039 **/
2040static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2041{
12207e49 2042 u64 tdba;
9a799d71 2043 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2044 u32 i, j, tdlen, txctrl;
9a799d71
AK		 2045
2046 /* Setup the HW Tx Head and Tail descriptor pointers */
2047 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2048 struct ixgbe_ring *ring = adapter->tx_ring[i];
e01c31a5
JB		 2049 j = ring->reg_idx;
2050 tdba = ring->dma;
2051 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 2052 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 2053 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 2054 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2055 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2056 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2057 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
4a0b9ca0
PW		 2058 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2059 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
84f62d4b
PWJ		 2060 /*
2061 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 2062 * bookkeeping if things aren't delivered in order.
2063 */
84f62d4b
PWJ		 2064 switch (hw->mac.type) {
2065 case ixgbe_mac_82598EB:
2066 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2067 break;
2068 case ixgbe_mac_82599EB:
2069 default:
2070 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2071 break;
2072 }
021230d4 2073 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 2074 switch (hw->mac.type) {
2075 case ixgbe_mac_82598EB:
2076 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2077 break;
2078 case ixgbe_mac_82599EB:
2079 default:
2080 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2081 break;
2082 }
9a799d71 2083 }
ee5f784a 2084
e8e26350 2085 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a 2086 u32 rttdcs;
1cdd1ec8 2087 u32 mask;
ee5f784a
DS		 2088
2089 /* disable the arbiter while setting MTQC */
2090 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2091 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2092 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2093
1cdd1ec8
GR		 2094 /* set transmit pool layout */
2095 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2096 switch (adapter->flags & mask) {
2097
2098 case (IXGBE_FLAG_SRIOV_ENABLED):
2099 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2100 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2101 break;
2102
2103 case (IXGBE_FLAG_DCB_ENABLED):
2104 /* We enable 8 traffic classes, DCB only */
2105 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2106 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2107 break;
2108
2109 default:
ee5f784a 2110 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1cdd1ec8
GR		 2111 break;
2112 }
ee5f784a
DS		 2113
2114 /* re-eable the arbiter */
2115 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2116 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2117 }
9a799d71
AK		 2118}
2119
e8e26350 2120#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2121
a6616b42
YZ		 2122static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2123 struct ixgbe_ring *rx_ring)
cc41ac7c 2124{
cc41ac7c 2125 u32 srrctl;
a6616b42 2126 int index;
0cefafad 2127 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2128
a6616b42
YZ		 2129 index = rx_ring->reg_idx;
2130 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2131 unsigned long mask;
0cefafad 2132 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2133 index = index & mask;
cc41ac7c 2134 }
cc41ac7c
JB		 2135 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2136
2137 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2138 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2139
afafd5b0
AD		 2140 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2141 IXGBE_SRRCTL_BSIZEHDR_MASK;
2142
6e455b89 2143 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2144#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2145 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2146#else
2147 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2148#endif
cc41ac7c 2149 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2150 } else {
afafd5b0
AD		 2151 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2152 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2153 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2154 }
e8e26350 2155
cc41ac7c
JB		 2156 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2157}
9a799d71 2158
0cefafad
JB		 2159static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2160{
2161 u32 mrqc = 0;
2162 int mask;
2163
2164 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2165 return mrqc;
2166
2167 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2168#ifdef CONFIG_IXGBE_DCB
2169 | IXGBE_FLAG_DCB_ENABLED
2170#endif
1cdd1ec8 2171 | IXGBE_FLAG_SRIOV_ENABLED
0cefafad
JB		 2172 );
2173
2174 switch (mask) {
2175 case (IXGBE_FLAG_RSS_ENABLED):
2176 mrqc = IXGBE_MRQC_RSSEN;
2177 break;
1cdd1ec8
GR		 2178 case (IXGBE_FLAG_SRIOV_ENABLED):
2179 mrqc = IXGBE_MRQC_VMDQEN;
2180 break;
0cefafad
JB		 2181#ifdef CONFIG_IXGBE_DCB
2182 case (IXGBE_FLAG_DCB_ENABLED):
2183 mrqc = IXGBE_MRQC_RT8TCEN;
2184 break;
2185#endif /* CONFIG_IXGBE_DCB */
2186 default:
2187 break;
2188 }
2189
2190 return mrqc;
2191}
2192
bb5a9ad2
NS		 2193/**
2194 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2195 * @adapter: address of board private structure
2196 * @index: index of ring to set
bb5a9ad2 2197 **/
edd2ea55 2198static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2199{
2200 struct ixgbe_ring *rx_ring;
2201 struct ixgbe_hw *hw = &adapter->hw;
2202 int j;
2203 u32 rscctrl;
edd2ea55 2204 int rx_buf_len;
bb5a9ad2 2205
4a0b9ca0 2206 rx_ring = adapter->rx_ring[index];
bb5a9ad2 2207 j = rx_ring->reg_idx;
edd2ea55 2208 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2209 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2210 rscctrl |= IXGBE_RSCCTL_RSCEN;
2211 /*
2212 * we must limit the number of descriptors so that the
2213 * total size of max desc * buf_len is not greater
2214 * than 65535
2215 */
2216 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2217#if (MAX_SKB_FRAGS > 16)
2218 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2219#elif (MAX_SKB_FRAGS > 8)
2220 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2221#elif (MAX_SKB_FRAGS > 4)
2222 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2223#else
2224 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2225#endif
2226 } else {
2227 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2228 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2229 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2230 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2231 else
2232 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2233 }
2234 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2235}
2236
9a799d71 2237/**
3a581073 2238 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2239 * @adapter: board private structure
2240 *
2241 * Configure the Rx unit of the MAC after a reset.
2242 **/
2243static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2244{
2245 u64 rdba;
2246 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2247 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2248 struct net_device *netdev = adapter->netdev;
2249 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2250 int i, j;
9a799d71 2251 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2252 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2253 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2254 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2255 u32 fctrl, hlreg0;
509ee935 2256 u32 reta = 0, mrqc = 0;
cc41ac7c 2257 u32 rdrxctl;
7c6e0a43 2258 int rx_buf_len;
9a799d71
AK		 2259
2260 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2261 /* Do not use packet split if we're in SR-IOV Mode */
2262 if (!adapter->num_vfs)
2263 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2264
2265 /* Set the RX buffer length according to the mode */
2266 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2267 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2268 if (hw->mac.type == ixgbe_mac_82599EB) {
2269 /* PSRTYPE must be initialized in 82599 */
2270 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2271 IXGBE_PSRTYPE_UDPHDR |
2272 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2273 IXGBE_PSRTYPE_IPV6HDR |
2274 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2275 IXGBE_WRITE_REG(hw,
2276 IXGBE_PSRTYPE(adapter->num_vfs),
2277 psrtype);
e8e26350 2278 }
9a799d71 2279 } else {
0c19d6af 2280 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2281 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2282 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2283 else
7c6e0a43 2284 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2285 }
2286
2287 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2288 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2289 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2290 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2291 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2292
2293 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2294 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2295 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2296 else
2297 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2298#ifdef IXGBE_FCOE
f34c5c82 2299 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2300 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2301#endif
9a799d71
AK		 2302 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2303
4a0b9ca0 2304 rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
9a799d71
AK		 2305 /* disable receives while setting up the descriptors */
2306 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2307 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2308
0cefafad
JB		 2309 /*
2310 * Setup the HW Rx Head and Tail Descriptor Pointers and
2311 * the Base and Length of the Rx Descriptor Ring
2312 */
9a799d71 2313 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2314 rx_ring = adapter->rx_ring[i];
a6616b42
YZ		 2315 rdba = rx_ring->dma;
2316 j = rx_ring->reg_idx;
284901a9 2317 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2318 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2319 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2320 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2321 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2322 rx_ring->head = IXGBE_RDH(j);
2323 rx_ring->tail = IXGBE_RDT(j);
2324 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2325
6e455b89
YZ		 2326 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2327 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2328 else
2329 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2330
63f39bd1 2331#ifdef IXGBE_FCOE
f34c5c82 2332 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2333 struct ixgbe_ring_feature *f;
2334 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2335 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2336 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2337 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2338 rx_ring->rx_buf_len =
2339 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2340 }
63f39bd1
YZ		 2341 }
2342
2343#endif /* IXGBE_FCOE */
a6616b42 2344 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2345 }
2346
e8e26350
PW		 2347 if (hw->mac.type == ixgbe_mac_82598EB) {
2348 /*
2349 * For VMDq support of different descriptor types or
2350 * buffer sizes through the use of multiple SRRCTL
2351 * registers, RDRXCTL.MVMEN must be set to 1
2352 *
2353 * also, the manual doesn't mention it clearly but DCA hints
2354 * will only use queue 0's tags unless this bit is set. Side
2355 * effects of setting this bit are only that SRRCTL must be
2356 * fully programmed [0..15]
2357 */
2a41ff81
JB		 2358 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2359 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2360 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2361 }
177db6ff 2362
1cdd1ec8
GR		 2363 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2364 u32 vt_reg_bits;
2365 u32 reg_offset, vf_shift;
2366 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2367 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2368 | IXGBE_VT_CTL_REPLEN;
2369 vt_reg_bits |= (adapter->num_vfs <<
2370 IXGBE_VT_CTL_POOL_SHIFT);
2371 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2372 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2373
2374 vf_shift = adapter->num_vfs % 32;
2375 reg_offset = adapter->num_vfs / 32;
2376 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2377 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2378 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2379 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2380 /* Enable only the PF's pool for Tx/Rx */
2381 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2382 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2383 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2384 ixgbe_set_vmolr(hw, adapter->num_vfs);
2385 }
2386
e8e26350 2387 /* Program MRQC for the distribution of queues */
0cefafad 2388 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2389
021230d4 2390 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2391 /* Fill out redirection table */
021230d4
AV		 2392 for (i = 0, j = 0; i < 128; i++, j++) {
2393 if (j == adapter->ring_feature[RING_F_RSS].indices)
2394 j = 0;
2395 /* reta = 4-byte sliding window of
2396 * 0x00..(indices-1)(indices-1)00..etc. */
2397 reta = (reta << 8) | (j * 0x11);
2398 if ((i & 3) == 3)
2399 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2400 }
2401
2402 /* Fill out hash function seeds */
2403 for (i = 0; i < 10; i++)
7c6e0a43 2404 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2405
2a41ff81
JB		 2406 if (hw->mac.type == ixgbe_mac_82598EB)
2407 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2408 /* Perform hash on these packet types */
2a41ff81
JB		 2409 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2410 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2411 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2412 | IXGBE_MRQC_RSS_FIELD_IPV6
2413 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2414 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2415 }
2a41ff81 2416 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2417
1cdd1ec8
GR		 2418 if (adapter->num_vfs) {
2419 u32 reg;
2420
2421 /* Map PF MAC address in RAR Entry 0 to first pool
2422 * following VFs */
2423 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2424
2425 /* Set up VF register offsets for selected VT Mode, i.e.
2426 * 64 VFs for SR-IOV */
2427 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2428 reg |= IXGBE_GCR_EXT_SRIOV;
2429 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2430 }
2431
021230d4
AV		 2432 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2433
2434 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2435 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2436 /* Disable indicating checksum in descriptor, enables
2437 * RSS hash */
9a799d71 2438 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2439 }
021230d4
AV		 2440 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2441 /* Enable IPv4 payload checksum for UDP fragments
2442 * if PCSD is not set */
2443 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2444 }
2445
2446 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2447
2448 if (hw->mac.type == ixgbe_mac_82599EB) {
2449 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2450 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2451 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2452 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2453 }
f8212f97 2454
0c19d6af 2455 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2456 /* Enable 82599 HW-RSC */
bb5a9ad2 2457 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2458 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2459
f8212f97
AD		 2460 /* Disable RSC for ACK packets */
2461 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2462 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2463 }
9a799d71
AK		 2464}
2465
068c89b0
DS		 2466static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2467{
2468 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2469 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2470 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2471
2472 /* add VID to filter table */
1ada1b1b 2473 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2474}
2475
2476static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2477{
2478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2479 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2480 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2481
2482 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2483 ixgbe_irq_disable(adapter);
2484
2485 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2486
2487 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2488 ixgbe_irq_enable(adapter);
2489
2490 /* remove VID from filter table */
1ada1b1b 2491 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2492}
2493
5f6c0181
JB		 2494/**
2495 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2496 * @adapter: driver data
2497 */
2498static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2499{
2500 struct ixgbe_hw *hw = &adapter->hw;
2501 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2502 int i, j;
2503
2504 switch (hw->mac.type) {
2505 case ixgbe_mac_82598EB:
2506 vlnctrl &= ~(IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE);
2507 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2508 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2509 break;
2510 case ixgbe_mac_82599EB:
2511 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2512 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2513 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2514 for (i = 0; i < adapter->num_rx_queues; i++) {
2515 j = adapter->rx_ring[i]->reg_idx;
2516 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2517 vlnctrl &= ~IXGBE_RXDCTL_VME;
2518 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2519 }
2520 break;
2521 default:
2522 break;
2523 }
2524}
2525
2526/**
2527 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2528 * @adapter: driver data
2529 */
2530static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2531{
2532 struct ixgbe_hw *hw = &adapter->hw;
2533 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2534 int i, j;
2535
2536 switch (hw->mac.type) {
2537 case ixgbe_mac_82598EB:
2538 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2539 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2540 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2541 break;
2542 case ixgbe_mac_82599EB:
2543 vlnctrl |= IXGBE_VLNCTRL_VFE;
2544 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2545 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2546 for (i = 0; i < adapter->num_rx_queues; i++) {
2547 j = adapter->rx_ring[i]->reg_idx;
2548 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2549 vlnctrl |= IXGBE_RXDCTL_VME;
2550 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2551 }
2552 break;
2553 default:
2554 break;
2555 }
2556}
2557
9a799d71 2558static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2559 struct vlan_group *grp)
9a799d71
AK		 2560{
2561 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 2562
d4f80882
AV		 2563 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2564 ixgbe_irq_disable(adapter);
9a799d71
AK		 2565 adapter->vlgrp = grp;
2566
2f90b865
AD		 2567 /*
2568 * For a DCB driver, always enable VLAN tag stripping so we can
2569 * still receive traffic from a DCB-enabled host even if we're
2570 * not in DCB mode.
2571 */
5f6c0181 2572 ixgbe_vlan_filter_enable(adapter);
dc63d377 2573
e8e26350 2574 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2575
d4f80882
AV		 2576 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2577 ixgbe_irq_enable(adapter);
9a799d71
AK		 2578}
2579
9a799d71
AK		 2580static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2581{
2582 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2583
2584 if (adapter->vlgrp) {
2585 u16 vid;
2586 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2587 if (!vlan_group_get_device(adapter->vlgrp, vid))
2588 continue;
2589 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2590 }
2591 }
2592}
2593
2594/**
2c5645cf 2595 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2596 * @netdev: network interface device structure
2597 *
2c5645cf
CL		 2598 * The set_rx_method entry point is called whenever the unicast/multicast
2599 * address list or the network interface flags are updated. This routine is
2600 * responsible for configuring the hardware for proper unicast, multicast and
2601 * promiscuous mode.
9a799d71 2602 **/
7f870475 2603void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2604{
2605 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2606 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 2607 u32 fctrl;
9a799d71
AK		 2608
2609 /* Check for Promiscuous and All Multicast modes */
2610
2611 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2612
2613 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2614 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2615 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
5f6c0181
JB		 2616 /* don't hardware filter vlans in promisc mode */
2617 ixgbe_vlan_filter_disable(adapter);
9a799d71 2618 } else {
746b9f02
PM		 2619 if (netdev->flags & IFF_ALLMULTI) {
2620 fctrl |= IXGBE_FCTRL_MPE;
2621 fctrl &= ~IXGBE_FCTRL_UPE;
2622 } else {
2623 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2624 }
5f6c0181 2625 ixgbe_vlan_filter_enable(adapter);
2c5645cf 2626 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2627 }
2628
2629 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2630
2c5645cf 2631 /* reprogram secondary unicast list */
32e7bfc4 2632 hw->mac.ops.update_uc_addr_list(hw, netdev);
9a799d71 2633
2c5645cf 2634 /* reprogram multicast list */
2853eb89
JP		 2635 hw->mac.ops.update_mc_addr_list(hw, netdev);
2636
1cdd1ec8
GR		 2637 if (adapter->num_vfs)
2638 ixgbe_restore_vf_multicasts(adapter);
9a799d71
AK		 2639}
2640
021230d4
AV		 2641static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2642{
2643 int q_idx;
2644 struct ixgbe_q_vector *q_vector;
2645 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2646
2647 /* legacy and MSI only use one vector */
2648 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2649 q_vectors = 1;
2650
2651 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2652 struct napi_struct *napi;
7a921c93 2653 q_vector = adapter->q_vector[q_idx];
f0848276 2654 napi = &q_vector->napi;
91281fd3
AD		 2655 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2656 if (!q_vector->rxr_count || !q_vector->txr_count) {
2657 if (q_vector->txr_count == 1)
2658 napi->poll = &ixgbe_clean_txonly;
2659 else if (q_vector->rxr_count == 1)
2660 napi->poll = &ixgbe_clean_rxonly;
2661 }
2662 }
f0848276
JB		 2663
2664 napi_enable(napi);
021230d4
AV		 2665 }
2666}
2667
2668static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2669{
2670 int q_idx;
2671 struct ixgbe_q_vector *q_vector;
2672 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2673
2674 /* legacy and MSI only use one vector */
2675 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2676 q_vectors = 1;
2677
2678 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2679 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2680 napi_disable(&q_vector->napi);
2681 }
2682}
2683
7a6b6f51 2684#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2685/*
2686 * ixgbe_configure_dcb - Configure DCB hardware
2687 * @adapter: ixgbe adapter struct
2688 *
2689 * This is called by the driver on open to configure the DCB hardware.
2690 * This is also called by the gennetlink interface when reconfiguring
2691 * the DCB state.
2692 */
2693static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2694{
2695 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 2696 u32 txdctl;
2f90b865
AD		 2697 int i, j;
2698
2699 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2700 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2701 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2702
2703 /* reconfigure the hardware */
2704 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2705
2706 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2707 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 2708 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2709 /* PThresh workaround for Tx hang with DFP enabled. */
2710 txdctl |= 32;
2711 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2712 }
2713 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 2714 ixgbe_vlan_filter_enable(adapter);
2715
2f90b865
AD		 2716 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2717}
2718
2719#endif
9a799d71
AK		 2720static void ixgbe_configure(struct ixgbe_adapter *adapter)
2721{
2722 struct net_device *netdev = adapter->netdev;
c4cf55e5 2723 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2724 int i;
2725
2c5645cf 2726 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2727
2728 ixgbe_restore_vlan(adapter);
7a6b6f51 2729#ifdef CONFIG_IXGBE_DCB
2f90b865 2730 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2731 if (hw->mac.type == ixgbe_mac_82598EB)
2732 netif_set_gso_max_size(netdev, 32768);
2733 else
2734 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2735 ixgbe_configure_dcb(adapter);
2736 } else {
2737 netif_set_gso_max_size(netdev, 65536);
2738 }
2739#else
2740 netif_set_gso_max_size(netdev, 65536);
2741#endif
9a799d71 2742
eacd73f7
YZ		 2743#ifdef IXGBE_FCOE
2744 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2745 ixgbe_configure_fcoe(adapter);
2746
2747#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2748 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2749 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 2750 adapter->tx_ring[i]->atr_sample_rate =
c4cf55e5
PWJ		 2751 adapter->atr_sample_rate;
2752 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2753 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2754 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2755 }
2756
9a799d71
AK		 2757 ixgbe_configure_tx(adapter);
2758 ixgbe_configure_rx(adapter);
2759 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 2760 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
2761 (adapter->rx_ring[i]->count - 1));
9a799d71
AK		 2762}
2763
e8e26350
PW		 2764static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2765{
2766 switch (hw->phy.type) {
2767 case ixgbe_phy_sfp_avago:
2768 case ixgbe_phy_sfp_ftl:
2769 case ixgbe_phy_sfp_intel:
2770 case ixgbe_phy_sfp_unknown:
2771 case ixgbe_phy_tw_tyco:
2772 case ixgbe_phy_tw_unknown:
2773 return true;
2774 default:
2775 return false;
2776 }
2777}
2778
0ecc061d 2779/**
e8e26350
PW		 2780 * ixgbe_sfp_link_config - set up SFP+ link
2781 * @adapter: pointer to private adapter struct
2782 **/
2783static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2784{
2785 struct ixgbe_hw *hw = &adapter->hw;
2786
2787 if (hw->phy.multispeed_fiber) {
2788 /*
2789 * In multispeed fiber setups, the device may not have
2790 * had a physical connection when the driver loaded.
2791 * If that's the case, the initial link configuration
2792 * couldn't get the MAC into 10G or 1G mode, so we'll
2793 * never have a link status change interrupt fire.
2794 * We need to try and force an autonegotiation
2795 * session, then bring up link.
2796 */
2797 hw->mac.ops.setup_sfp(hw);
2798 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2799 schedule_work(&adapter->multispeed_fiber_task);
2800 } else {
2801 /*
2802 * Direct Attach Cu and non-multispeed fiber modules
2803 * still need to be configured properly prior to
2804 * attempting link.
2805 */
2806 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2807 schedule_work(&adapter->sfp_config_module_task);
2808 }
2809}
2810
2811/**
2812 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2813 * @hw: pointer to private hardware struct
2814 *
2815 * Returns 0 on success, negative on failure
2816 **/
e8e26350 2817static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2818{
2819 u32 autoneg;
8620a103 2820 bool negotiation, link_up = false;
0ecc061d
PWJ		 2821 u32 ret = IXGBE_ERR_LINK_SETUP;
2822
2823 if (hw->mac.ops.check_link)
2824 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2825
2826 if (ret)
2827 goto link_cfg_out;
2828
2829 if (hw->mac.ops.get_link_capabilities)
8620a103 2830 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2831 if (ret)
2832 goto link_cfg_out;
2833
8620a103
MC		 2834 if (hw->mac.ops.setup_link)
2835 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2836link_cfg_out:
2837 return ret;
2838}
2839
e8e26350
PW		 2840#define IXGBE_MAX_RX_DESC_POLL 10
2841static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2842 int rxr)
2843{
4a0b9ca0 2844 int j = adapter->rx_ring[rxr]->reg_idx;
e8e26350
PW		 2845 int k;
2846
2847 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2848 if (IXGBE_READ_REG(&adapter->hw,
2849 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2850 break;
2851 else
2852 msleep(1);
2853 }
2854 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2855 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2856 "not set within the polling period\n", rxr);
2857 }
4a0b9ca0
PW		 2858 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
2859 (adapter->rx_ring[rxr]->count - 1));
e8e26350
PW		 2860}
2861
9a799d71
AK		 2862static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2863{
2864 struct net_device *netdev = adapter->netdev;
9a799d71 2865 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2866 int i, j = 0;
e8e26350 2867 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2868 int err;
9a799d71 2869 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2870 u32 txdctl, rxdctl, mhadd;
e8e26350 2871 u32 dmatxctl;
021230d4 2872 u32 gpie;
c9205697 2873 u32 ctrl_ext;
9a799d71 2874
5eba3699
AV		 2875 ixgbe_get_hw_control(adapter);
2876
021230d4
AV		 2877 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2878 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2879 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2880 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2881 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2882 } else {
2883 /* MSI only */
021230d4 2884 gpie = 0;
9a799d71 2885 }
1cdd1ec8
GR		 2886 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2887 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2888 gpie |= IXGBE_GPIE_VTMODE_64;
2889 }
021230d4
AV		 2890 /* XXX: to interrupt immediately for EICS writes, enable this */
2891 /* gpie |= IXGBE_GPIE_EIMEN; */
2892 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2893 }
2894
9b471446
JB		 2895 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2896 /*
2897 * use EIAM to auto-mask when MSI-X interrupt is asserted
2898 * this saves a register write for every interrupt
2899 */
2900 switch (hw->mac.type) {
2901 case ixgbe_mac_82598EB:
2902 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2903 break;
2904 default:
2905 case ixgbe_mac_82599EB:
2906 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2907 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2908 break;
2909 }
2910 } else {
021230d4
AV		 2911 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2912 * specifically only auto mask tx and rx interrupts */
2913 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2914 }
9a799d71 2915
0befdb3e
JB		 2916 /* Enable fan failure interrupt if media type is copper */
2917 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2918 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2919 gpie |= IXGBE_SDP1_GPIEN;
2920 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2921 }
2922
e8e26350
PW		 2923 if (hw->mac.type == ixgbe_mac_82599EB) {
2924 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2925 gpie |= IXGBE_SDP1_GPIEN;
2926 gpie |= IXGBE_SDP2_GPIEN;
2927 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2928 }
2929
63f39bd1
YZ		 2930#ifdef IXGBE_FCOE
2931 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2932 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2933 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2934 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2935
2936#endif /* IXGBE_FCOE */
021230d4 2937 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2938 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2939 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2940 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2941
2942 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2943 }
2944
2945 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2946 j = adapter->tx_ring[i]->reg_idx;
021230d4 2947 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
ef021194
JB		 2948 if (adapter->rx_itr_setting == 0) {
2949 /* cannot set wthresh when itr==0 */
2950 txdctl &= ~0x007F0000;
2951 } else {
2952 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2953 txdctl |= (8 << 16);
2954 }
e8e26350
PW		 2955 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2956 }
2957
2958 if (hw->mac.type == ixgbe_mac_82599EB) {
2959 /* DMATXCTL.EN must be set after all Tx queue config is done */
2960 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2961 dmatxctl |= IXGBE_DMATXCTL_TE;
2962 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2963 }
2964 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 2965 j = adapter->tx_ring[i]->reg_idx;
e8e26350 2966 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2967 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2968 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 2969 if (hw->mac.type == ixgbe_mac_82599EB) {
2970 int wait_loop = 10;
2971 /* poll for Tx Enable ready */
2972 do {
2973 msleep(1);
2974 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2975 } while (--wait_loop &&
2976 !(txdctl & IXGBE_TXDCTL_ENABLE));
2977 if (!wait_loop)
2978 DPRINTK(DRV, ERR, "Could not enable "
2979 "Tx Queue %d\n", j);
2980 }
9a799d71
AK		 2981 }
2982
e8e26350 2983 for (i = 0; i < num_rx_rings; i++) {
4a0b9ca0 2984 j = adapter->rx_ring[i]->reg_idx;
021230d4
AV		 2985 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2986 /* enable PTHRESH=32 descriptors (half the internal cache)
2987 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2988 * this also removes a pesky rx_no_buffer_count increment */
2989 rxdctl |= 0x0020;
9a799d71 2990 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2991 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2992 if (hw->mac.type == ixgbe_mac_82599EB)
2993 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2994 }
2995 /* enable all receives */
2996 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2997 if (hw->mac.type == ixgbe_mac_82598EB)
2998 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2999 else
3000 rxdctl |= IXGBE_RXCTRL_RXEN;
3001 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 3002
3003 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3004 ixgbe_configure_msix(adapter);
3005 else
3006 ixgbe_configure_msi_and_legacy(adapter);
3007
61fac744
PW		 3008 /* enable the optics */
3009 if (hw->phy.multispeed_fiber)
3010 hw->mac.ops.enable_tx_laser(hw);
3011
9a799d71 3012 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3013 ixgbe_napi_enable_all(adapter);
3014
3015 /* clear any pending interrupts, may auto mask */
3016 IXGBE_READ_REG(hw, IXGBE_EICR);
3017
9a799d71
AK		 3018 ixgbe_irq_enable(adapter);
3019
bf069c97
DS		 3020 /*
3021 * If this adapter has a fan, check to see if we had a failure
3022 * before we enabled the interrupt.
3023 */
3024 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3025 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3026 if (esdp & IXGBE_ESDP_SDP1)
3027 DPRINTK(DRV, CRIT,
3028 "Fan has stopped, replace the adapter\n");
3029 }
3030
e8e26350
PW		 3031 /*
3032 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3033 * arrived before interrupts were enabled but after probe. Such
3034 * devices wouldn't have their type identified yet. We need to
3035 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3036 * If we're not hot-pluggable SFP+, we just need to configure link
3037 * and bring it up.
3038 */
19343de2
DS		 3039 if (hw->phy.type == ixgbe_phy_unknown) {
3040 err = hw->phy.ops.identify(hw);
3041 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3042 /*
3043 * Take the device down and schedule the sfp tasklet
3044 * which will unregister_netdev and log it.
3045 */
19343de2 3046 ixgbe_down(adapter);
5da43c1a 3047 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3048 return err;
3049 }
e8e26350
PW		 3050 }
3051
3052 if (ixgbe_is_sfp(hw)) {
3053 ixgbe_sfp_link_config(adapter);
3054 } else {
3055 err = ixgbe_non_sfp_link_config(hw);
3056 if (err)
3057 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3058 }
0ecc061d 3059
c4cf55e5
PWJ		 3060 for (i = 0; i < adapter->num_tx_queues; i++)
3061 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 3062 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 3063
1da100bb
PWJ		 3064 /* enable transmits */
3065 netif_tx_start_all_queues(netdev);
3066
9a799d71
AK		 3067 /* bring the link up in the watchdog, this could race with our first
3068 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3069 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3070 adapter->link_check_timeout = jiffies;
9a799d71 3071 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3072
3073 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3074 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3075 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3076 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3077
9a799d71
AK		 3078 return 0;
3079}
3080
d4f80882
AV		 3081void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3082{
3083 WARN_ON(in_interrupt());
3084 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3085 msleep(1);
3086 ixgbe_down(adapter);
5809a1ae
GR		 3087 /*
3088 * If SR-IOV enabled then wait a bit before bringing the adapter
3089 * back up to give the VFs time to respond to the reset. The
3090 * two second wait is based upon the watchdog timer cycle in
3091 * the VF driver.
3092 */
3093 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3094 msleep(2000);
d4f80882
AV		 3095 ixgbe_up(adapter);
3096 clear_bit(__IXGBE_RESETTING, &adapter->state);
3097}
3098
9a799d71
AK		 3099int ixgbe_up(struct ixgbe_adapter *adapter)
3100{
3101 /* hardware has been reset, we need to reload some things */
3102 ixgbe_configure(adapter);
3103
3104 return ixgbe_up_complete(adapter);
3105}
3106
3107void ixgbe_reset(struct ixgbe_adapter *adapter)
3108{
c44ade9e 3109 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3110 int err;
3111
3112 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3113 switch (err) {
3114 case 0:
3115 case IXGBE_ERR_SFP_NOT_PRESENT:
3116 break;
3117 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3118 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3119 break;
794caeb2
PWJ		 3120 case IXGBE_ERR_EEPROM_VERSION:
3121 /* We are running on a pre-production device, log a warning */
3122 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3123 "adapter/LOM. Please be aware there may be issues "
3124 "associated with your hardware. If you are "
3125 "experiencing problems please contact your Intel or "
3126 "hardware representative who provided you with this "
3127 "hardware.\n");
3128 break;
da4dd0f7
PWJ		 3129 default:
3130 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3131 }
9a799d71
AK		 3132
3133 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3134 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3135 IXGBE_RAH_AV);
9a799d71
AK		 3136}
3137
9a799d71
AK		 3138/**
3139 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3140 * @adapter: board private structure
3141 * @rx_ring: ring to free buffers from
3142 **/
3143static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3144 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3145{
3146 struct pci_dev *pdev = adapter->pdev;
3147 unsigned long size;
3148 unsigned int i;
3149
3150 /* Free all the Rx ring sk_buffs */
3151
3152 for (i = 0; i < rx_ring->count; i++) {
3153 struct ixgbe_rx_buffer *rx_buffer_info;
3154
3155 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3156 if (rx_buffer_info->dma) {
3157 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 3158 rx_ring->rx_buf_len,
3159 PCI_DMA_FROMDEVICE);
9a799d71
AK		 3160 rx_buffer_info->dma = 0;
3161 }
3162 if (rx_buffer_info->skb) {
f8212f97 3163 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3164 rx_buffer_info->skb = NULL;
f8212f97
AD		 3165 do {
3166 struct sk_buff *this = skb;
fd3686a8 3167 if (IXGBE_RSC_CB(this)->dma) {
43634e82
MC		 3168 pci_unmap_single(pdev, IXGBE_RSC_CB(this)->dma,
3169 rx_ring->rx_buf_len,
3170 PCI_DMA_FROMDEVICE);
fd3686a8
MC		 3171 IXGBE_RSC_CB(this)->dma = 0;
3172 }
f8212f97
AD		 3173 skb = skb->prev;
3174 dev_kfree_skb(this);
3175 } while (skb);
9a799d71
AK		 3176 }
3177 if (!rx_buffer_info->page)
3178 continue;
4f57ca6e
JB		 3179 if (rx_buffer_info->page_dma) {
3180 pci_unmap_page(pdev, rx_buffer_info->page_dma,
3181 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3182 rx_buffer_info->page_dma = 0;
3183 }
9a799d71
AK		 3184 put_page(rx_buffer_info->page);
3185 rx_buffer_info->page = NULL;
762f4c57 3186 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3187 }
3188
3189 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3190 memset(rx_ring->rx_buffer_info, 0, size);
3191
3192 /* Zero out the descriptor ring */
3193 memset(rx_ring->desc, 0, rx_ring->size);
3194
3195 rx_ring->next_to_clean = 0;
3196 rx_ring->next_to_use = 0;
3197
9891ca7c
JB		 3198 if (rx_ring->head)
3199 writel(0, adapter->hw.hw_addr + rx_ring->head);
3200 if (rx_ring->tail)
3201 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3202}
3203
3204/**
3205 * ixgbe_clean_tx_ring - Free Tx Buffers
3206 * @adapter: board private structure
3207 * @tx_ring: ring to be cleaned
3208 **/
3209static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3210 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3211{
3212 struct ixgbe_tx_buffer *tx_buffer_info;
3213 unsigned long size;
3214 unsigned int i;
3215
3216 /* Free all the Tx ring sk_buffs */
3217
3218 for (i = 0; i < tx_ring->count; i++) {
3219 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3220 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3221 }
3222
3223 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3224 memset(tx_ring->tx_buffer_info, 0, size);
3225
3226 /* Zero out the descriptor ring */
3227 memset(tx_ring->desc, 0, tx_ring->size);
3228
3229 tx_ring->next_to_use = 0;
3230 tx_ring->next_to_clean = 0;
3231
9891ca7c
JB		 3232 if (tx_ring->head)
3233 writel(0, adapter->hw.hw_addr + tx_ring->head);
3234 if (tx_ring->tail)
3235 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3236}
3237
3238/**
021230d4 3239 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3240 * @adapter: board private structure
3241 **/
021230d4 3242static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3243{
3244 int i;
3245
021230d4 3246 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3247 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3248}
3249
3250/**
021230d4 3251 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3252 * @adapter: board private structure
3253 **/
021230d4 3254static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3255{
3256 int i;
3257
021230d4 3258 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3259 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3260}
3261
3262void ixgbe_down(struct ixgbe_adapter *adapter)
3263{
3264 struct net_device *netdev = adapter->netdev;
7f821875 3265 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3266 u32 rxctrl;
7f821875
JB		 3267 u32 txdctl;
3268 int i, j;
9a799d71
AK		 3269
3270 /* signal that we are down to the interrupt handler */
3271 set_bit(__IXGBE_DOWN, &adapter->state);
3272
61fac744
PW		 3273 /* power down the optics */
3274 if (hw->phy.multispeed_fiber)
3275 hw->mac.ops.disable_tx_laser(hw);
3276
767081ad
GR		 3277 /* disable receive for all VFs and wait one second */
3278 if (adapter->num_vfs) {
767081ad
GR		 3279 /* ping all the active vfs to let them know we are going down */
3280 ixgbe_ping_all_vfs(adapter);
581d1aa7 3281
767081ad
GR		 3282 /* Disable all VFTE/VFRE TX/RX */
3283 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3284
3285 /* Mark all the VFs as inactive */
3286 for (i = 0 ; i < adapter->num_vfs; i++)
3287 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3288 }
3289
9a799d71 3290 /* disable receives */
7f821875
JB		 3291 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3292 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3293
7f821875 3294 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3295 msleep(10);
3296
7f821875
JB		 3297 netif_tx_stop_all_queues(netdev);
3298
0a1f87cb
DS		 3299 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3300 del_timer_sync(&adapter->sfp_timer);
9a799d71 3301 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3302 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3303
c0dfb90e
JF		 3304 netif_carrier_off(netdev);
3305 netif_tx_disable(netdev);
3306
3307 ixgbe_irq_disable(adapter);
3308
3309 ixgbe_napi_disable_all(adapter);
3310
c4cf55e5
PWJ		 3311 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3312 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3313 cancel_work_sync(&adapter->fdir_reinit_task);
3314
7f821875
JB		 3315 /* disable transmits in the hardware now that interrupts are off */
3316 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3317 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3318 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3319 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3320 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3321 }
88512539
PW		 3322 /* Disable the Tx DMA engine on 82599 */
3323 if (hw->mac.type == ixgbe_mac_82599EB)
3324 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3325 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3326 ~IXGBE_DMATXCTL_TE));
7f821875 3327
9a713e7c
PW		 3328 /* clear n-tuple filters that are cached */
3329 ethtool_ntuple_flush(netdev);
3330
6f4a0e45
PL		 3331 if (!pci_channel_offline(adapter->pdev))
3332 ixgbe_reset(adapter);
9a799d71
AK		 3333 ixgbe_clean_all_tx_rings(adapter);
3334 ixgbe_clean_all_rx_rings(adapter);
3335
5dd2d332 3336#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3337 /* since we reset the hardware DCA settings were cleared */
e35ec126 3338 ixgbe_setup_dca(adapter);
96b0e0f6 3339#endif
9a799d71
AK		 3340}
3341
9a799d71 3342/**
021230d4
AV		 3343 * ixgbe_poll - NAPI Rx polling callback
3344 * @napi: structure for representing this polling device
3345 * @budget: how many packets driver is allowed to clean
3346 *
3347 * This function is used for legacy and MSI, NAPI mode
9a799d71 3348 **/
021230d4 3349static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3350{
9a1a69ad
JB		 3351 struct ixgbe_q_vector *q_vector =
3352 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3353 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3354 int tx_clean_complete, work_done = 0;
9a799d71 3355
5dd2d332 3356#ifdef CONFIG_IXGBE_DCA
bd0362dd 3357 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3358 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3359 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3360 }
3361#endif
3362
4a0b9ca0
PW		 3363 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3364 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3365
9a1a69ad 3366 if (!tx_clean_complete)
d2c7ddd6
DM		 3367 work_done = budget;
3368
53e52c72
DM		 3369 /* If budget not fully consumed, exit the polling mode */
3370 if (work_done < budget) {
288379f0 3371 napi_complete(napi);
f7554a2b 3372 if (adapter->rx_itr_setting & 1)
f494e8fa 3373 ixgbe_set_itr(adapter);
d4f80882 3374 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3375 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3376 }
9a799d71
AK		 3377 return work_done;
3378}
3379
3380/**
3381 * ixgbe_tx_timeout - Respond to a Tx Hang
3382 * @netdev: network interface device structure
3383 **/
3384static void ixgbe_tx_timeout(struct net_device *netdev)
3385{
3386 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3387
3388 /* Do the reset outside of interrupt context */
3389 schedule_work(&adapter->reset_task);
3390}
3391
3392static void ixgbe_reset_task(struct work_struct *work)
3393{
3394 struct ixgbe_adapter *adapter;
3395 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3396
2f90b865
AD		 3397 /* If we're already down or resetting, just bail */
3398 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3399 test_bit(__IXGBE_RESETTING, &adapter->state))
3400 return;
3401
9a799d71
AK		 3402 adapter->tx_timeout_count++;
3403
d4f80882 3404 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3405}
3406
bc97114d
PWJ		 3407#ifdef CONFIG_IXGBE_DCB
3408static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3409{
bc97114d 3410 bool ret = false;
0cefafad 3411 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3412
0cefafad
JB		 3413 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3414 return ret;
3415
3416 f->mask = 0x7 << 3;
3417 adapter->num_rx_queues = f->indices;
3418 adapter->num_tx_queues = f->indices;
3419 ret = true;
2f90b865 3420
bc97114d
PWJ		 3421 return ret;
3422}
3423#endif
3424
4df10466
JB		 3425/**
3426 * ixgbe_set_rss_queues: Allocate queues for RSS
3427 * @adapter: board private structure to initialize
3428 *
3429 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3430 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3431 *
3432 **/
bc97114d
PWJ		 3433static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3434{
3435 bool ret = false;
0cefafad 3436 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3437
3438 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3439 f->mask = 0xF;
3440 adapter->num_rx_queues = f->indices;
3441 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3442 ret = true;
3443 } else {
bc97114d 3444 ret = false;
b9804972
JB		 3445 }
3446
bc97114d
PWJ		 3447 return ret;
3448}
3449
c4cf55e5
PWJ		 3450/**
3451 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3452 * @adapter: board private structure to initialize
3453 *
3454 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3455 * to the original CPU that initiated the Tx session. This runs in addition
3456 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3457 * Rx load across CPUs using RSS.
3458 *
3459 **/
3460static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3461{
3462 bool ret = false;
3463 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3464
3465 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3466 f_fdir->mask = 0;
3467
3468 /* Flow Director must have RSS enabled */
3469 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3470 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3471 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3472 adapter->num_tx_queues = f_fdir->indices;
3473 adapter->num_rx_queues = f_fdir->indices;
3474 ret = true;
3475 } else {
3476 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3477 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3478 }
3479 return ret;
3480}
3481
0331a832
YZ		 3482#ifdef IXGBE_FCOE
3483/**
3484 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3485 * @adapter: board private structure to initialize
3486 *
3487 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3488 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3489 * rx queues out of the max number of rx queues, instead, it is used as the
3490 * index of the first rx queue used by FCoE.
3491 *
3492 **/
3493static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3494{
3495 bool ret = false;
3496 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3497
3498 f->indices = min((int)num_online_cpus(), f->indices);
3499 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3500 adapter->num_rx_queues = 1;
3501 adapter->num_tx_queues = 1;
0331a832
YZ		 3502#ifdef CONFIG_IXGBE_DCB
3503 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
d6dbee86 3504 DPRINTK(PROBE, INFO, "FCoE enabled with DCB\n");
0331a832
YZ		 3505 ixgbe_set_dcb_queues(adapter);
3506 }
3507#endif
3508 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
d6dbee86 3509 DPRINTK(PROBE, INFO, "FCoE enabled with RSS\n");
8faa2a78
YZ		 3510 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3511 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3512 ixgbe_set_fdir_queues(adapter);
3513 else
3514 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3515 }
3516 /* adding FCoE rx rings to the end */
3517 f->mask = adapter->num_rx_queues;
3518 adapter->num_rx_queues += f->indices;
8de8b2e6 3519 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3520
3521 ret = true;
3522 }
3523
3524 return ret;
3525}
3526
3527#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3528/**
3529 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3530 * @adapter: board private structure to initialize
3531 *
3532 * IOV doesn't actually use anything, so just NAK the
3533 * request for now and let the other queue routines
3534 * figure out what to do.
3535 */
3536static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3537{
3538 return false;
3539}
3540
4df10466
JB		 3541/*
3542 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3543 * @adapter: board private structure to initialize
3544 *
3545 * This is the top level queue allocation routine. The order here is very
3546 * important, starting with the "most" number of features turned on at once,
3547 * and ending with the smallest set of features. This way large combinations
3548 * can be allocated if they're turned on, and smaller combinations are the
3549 * fallthrough conditions.
3550 *
3551 **/
bc97114d
PWJ		 3552static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3553{
1cdd1ec8
GR		 3554 /* Start with base case */
3555 adapter->num_rx_queues = 1;
3556 adapter->num_tx_queues = 1;
3557 adapter->num_rx_pools = adapter->num_rx_queues;
3558 adapter->num_rx_queues_per_pool = 1;
3559
3560 if (ixgbe_set_sriov_queues(adapter))
3561 return;
3562
0331a832
YZ		 3563#ifdef IXGBE_FCOE
3564 if (ixgbe_set_fcoe_queues(adapter))
3565 goto done;
3566
3567#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3568#ifdef CONFIG_IXGBE_DCB
3569 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3570 goto done;
bc97114d
PWJ		 3571
3572#endif
c4cf55e5
PWJ		 3573 if (ixgbe_set_fdir_queues(adapter))
3574 goto done;
3575
bc97114d 3576 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3577 goto done;
3578
3579 /* fallback to base case */
3580 adapter->num_rx_queues = 1;
3581 adapter->num_tx_queues = 1;
3582
3583done:
3584 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3585 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3586}
3587
021230d4 3588static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3589 int vectors)
021230d4
AV		 3590{
3591 int err, vector_threshold;
3592
3593 /* We'll want at least 3 (vector_threshold):
3594 * 1) TxQ[0] Cleanup
3595 * 2) RxQ[0] Cleanup
3596 * 3) Other (Link Status Change, etc.)
3597 * 4) TCP Timer (optional)
3598 */
3599 vector_threshold = MIN_MSIX_COUNT;
3600
3601 /* The more we get, the more we will assign to Tx/Rx Cleanup
3602 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3603 * Right now, we simply care about how many we'll get; we'll
3604 * set them up later while requesting irq's.
3605 */
3606 while (vectors >= vector_threshold) {
3607 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3608 vectors);
021230d4
AV		 3609 if (!err) /* Success in acquiring all requested vectors. */
3610 break;
3611 else if (err < 0)
3612 vectors = 0; /* Nasty failure, quit now */
3613 else /* err == number of vectors we should try again with */
3614 vectors = err;
3615 }
3616
3617 if (vectors < vector_threshold) {
3618 /* Can't allocate enough MSI-X interrupts? Oh well.
3619 * This just means we'll go with either a single MSI
3620 * vector or fall back to legacy interrupts.
3621 */
3622 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3623 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3624 kfree(adapter->msix_entries);
3625 adapter->msix_entries = NULL;
021230d4
AV		 3626 } else {
3627 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3628 /*
3629 * Adjust for only the vectors we'll use, which is minimum
3630 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3631 * vectors we were allocated.
3632 */
3633 adapter->num_msix_vectors = min(vectors,
3634 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3635 }
3636}
3637
021230d4 3638/**
bc97114d 3639 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3640 * @adapter: board private structure to initialize
3641 *
bc97114d
PWJ		 3642 * Cache the descriptor ring offsets for RSS to the assigned rings.
3643 *
021230d4 3644 **/
bc97114d 3645static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3646{
bc97114d
PWJ		 3647 int i;
3648 bool ret = false;
3649
3650 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3651 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3652 adapter->rx_ring[i]->reg_idx = i;
bc97114d 3653 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3654 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 3655 ret = true;
3656 } else {
3657 ret = false;
3658 }
3659
3660 return ret;
3661}
3662
3663#ifdef CONFIG_IXGBE_DCB
3664/**
3665 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3666 * @adapter: board private structure to initialize
3667 *
3668 * Cache the descriptor ring offsets for DCB to the assigned rings.
3669 *
3670 **/
3671static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3672{
3673 int i;
3674 bool ret = false;
3675 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3676
3677 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3678 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3679 /* the number of queues is assumed to be symmetric */
3680 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 3681 adapter->rx_ring[i]->reg_idx = i << 3;
3682 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 3683 }
bc97114d 3684 ret = true;
e8e26350 3685 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3686 if (dcb_i == 8) {
3687 /*
3688 * Tx TC0 starts at: descriptor queue 0
3689 * Tx TC1 starts at: descriptor queue 32
3690 * Tx TC2 starts at: descriptor queue 64
3691 * Tx TC3 starts at: descriptor queue 80
3692 * Tx TC4 starts at: descriptor queue 96
3693 * Tx TC5 starts at: descriptor queue 104
3694 * Tx TC6 starts at: descriptor queue 112
3695 * Tx TC7 starts at: descriptor queue 120
3696 *
3697 * Rx TC0-TC7 are offset by 16 queues each
3698 */
3699 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 3700 adapter->tx_ring[i]->reg_idx = i << 5;
3701 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3702 }
3703 for ( ; i < 5; i++) {
4a0b9ca0 3704 adapter->tx_ring[i]->reg_idx =
f92ef202 3705 ((i + 2) << 4);
4a0b9ca0 3706 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3707 }
3708 for ( ; i < dcb_i; i++) {
4a0b9ca0 3709 adapter->tx_ring[i]->reg_idx =
f92ef202 3710 ((i + 8) << 3);
4a0b9ca0 3711 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 3712 }
3713
3714 ret = true;
3715 } else if (dcb_i == 4) {
3716 /*
3717 * Tx TC0 starts at: descriptor queue 0
3718 * Tx TC1 starts at: descriptor queue 64
3719 * Tx TC2 starts at: descriptor queue 96
3720 * Tx TC3 starts at: descriptor queue 112
3721 *
3722 * Rx TC0-TC3 are offset by 32 queues each
3723 */
4a0b9ca0
PW		 3724 adapter->tx_ring[0]->reg_idx = 0;
3725 adapter->tx_ring[1]->reg_idx = 64;
3726 adapter->tx_ring[2]->reg_idx = 96;
3727 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 3728 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 3729 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 3730
3731 ret = true;
3732 } else {
3733 ret = false;
e8e26350 3734 }
bc97114d
PWJ		 3735 } else {
3736 ret = false;
021230d4 3737 }
bc97114d
PWJ		 3738 } else {
3739 ret = false;
021230d4 3740 }
bc97114d
PWJ		 3741
3742 return ret;
3743}
3744#endif
3745
c4cf55e5
PWJ		 3746/**
3747 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3748 * @adapter: board private structure to initialize
3749 *
3750 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3751 *
3752 **/
3753static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3754{
3755 int i;
3756 bool ret = false;
3757
3758 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3759 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3760 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3761 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3762 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 3763 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3764 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 3765 ret = true;
3766 }
3767
3768 return ret;
3769}
3770
0331a832
YZ		 3771#ifdef IXGBE_FCOE
3772/**
3773 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3774 * @adapter: board private structure to initialize
3775 *
3776 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3777 *
3778 */
3779static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3780{
8de8b2e6 3781 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3782 bool ret = false;
3783 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3784
3785 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3786#ifdef CONFIG_IXGBE_DCB
3787 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3788 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3789
0331a832 3790 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 3791 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 3792 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
3793 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 3794 /*
3795 * In 82599, the number of Tx queues for each traffic
3796 * class for both 8-TC and 4-TC modes are:
3797 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3798 * 8 TCs: 32 32 16 16 8 8 8 8
3799 * 4 TCs: 64 64 32 32
3800 * We have max 8 queues for FCoE, where 8 the is
3801 * FCoE redirection table size. If TC for FCoE is
3802 * less than or equal to TC3, we have enough queues
3803 * to add max of 8 queues for FCoE, so we start FCoE
3804 * tx descriptor from the next one, i.e., reg_idx + 1.
3805 * If TC for FCoE is above TC3, implying 8 TC mode,
3806 * and we need 8 for FCoE, we have to take all queues
3807 * in that traffic class for FCoE.
3808 */
3809 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3810 fcoe_tx_i--;
0331a832
YZ		 3811 }
3812#endif /* CONFIG_IXGBE_DCB */
3813 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3814 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3815 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3816 ixgbe_cache_ring_fdir(adapter);
3817 else
3818 ixgbe_cache_ring_rss(adapter);
3819
8de8b2e6
YZ		 3820 fcoe_rx_i = f->mask;
3821 fcoe_tx_i = f->mask;
3822 }
3823 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 3824 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
3825 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 3826 }
0331a832
YZ		 3827 ret = true;
3828 }
3829 return ret;
3830}
3831
3832#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3833/**
3834 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3835 * @adapter: board private structure to initialize
3836 *
3837 * SR-IOV doesn't use any descriptor rings but changes the default if
3838 * no other mapping is used.
3839 *
3840 */
3841static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3842{
4a0b9ca0
PW		 3843 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
3844 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 3845 if (adapter->num_vfs)
3846 return true;
3847 else
3848 return false;
3849}
3850
bc97114d
PWJ		 3851/**
3852 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3853 * @adapter: board private structure to initialize
3854 *
3855 * Once we know the feature-set enabled for the device, we'll cache
3856 * the register offset the descriptor ring is assigned to.
3857 *
3858 * Note, the order the various feature calls is important. It must start with
3859 * the "most" features enabled at the same time, then trickle down to the
3860 * least amount of features turned on at once.
3861 **/
3862static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3863{
3864 /* start with default case */
4a0b9ca0
PW		 3865 adapter->rx_ring[0]->reg_idx = 0;
3866 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 3867
1cdd1ec8
GR		 3868 if (ixgbe_cache_ring_sriov(adapter))
3869 return;
3870
0331a832
YZ		 3871#ifdef IXGBE_FCOE
3872 if (ixgbe_cache_ring_fcoe(adapter))
3873 return;
3874
3875#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3876#ifdef CONFIG_IXGBE_DCB
3877 if (ixgbe_cache_ring_dcb(adapter))
3878 return;
3879
3880#endif
c4cf55e5
PWJ		 3881 if (ixgbe_cache_ring_fdir(adapter))
3882 return;
3883
bc97114d
PWJ		 3884 if (ixgbe_cache_ring_rss(adapter))
3885 return;
021230d4
AV		 3886}
3887
9a799d71
AK		 3888/**
3889 * ixgbe_alloc_queues - Allocate memory for all rings
3890 * @adapter: board private structure to initialize
3891 *
3892 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3893 * number of queues at compile-time. The polling_netdev array is
3894 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3895 **/
2f90b865 3896static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3897{
3898 int i;
4a0b9ca0 3899 int orig_node = adapter->node;
9a799d71 3900
021230d4 3901 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 3902 struct ixgbe_ring *ring = adapter->tx_ring[i];
3903 if (orig_node == -1) {
3904 int cur_node = next_online_node(adapter->node);
3905 if (cur_node == MAX_NUMNODES)
3906 cur_node = first_online_node;
3907 adapter->node = cur_node;
3908 }
3909 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3910 adapter->node);
3911 if (!ring)
3912 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3913 if (!ring)
3914 goto err_tx_ring_allocation;
3915 ring->count = adapter->tx_ring_count;
3916 ring->queue_index = i;
3917 ring->numa_node = adapter->node;
3918
3919 adapter->tx_ring[i] = ring;
021230d4 3920 }
b9804972 3921
4a0b9ca0
PW		 3922 /* Restore the adapter's original node */
3923 adapter->node = orig_node;
3924
9a799d71 3925 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 3926 struct ixgbe_ring *ring = adapter->rx_ring[i];
3927 if (orig_node == -1) {
3928 int cur_node = next_online_node(adapter->node);
3929 if (cur_node == MAX_NUMNODES)
3930 cur_node = first_online_node;
3931 adapter->node = cur_node;
3932 }
3933 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
3934 adapter->node);
3935 if (!ring)
3936 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
3937 if (!ring)
3938 goto err_rx_ring_allocation;
3939 ring->count = adapter->rx_ring_count;
3940 ring->queue_index = i;
3941 ring->numa_node = adapter->node;
3942
3943 adapter->rx_ring[i] = ring;
021230d4
AV		 3944 }
3945
4a0b9ca0
PW		 3946 /* Restore the adapter's original node */
3947 adapter->node = orig_node;
3948
021230d4
AV		 3949 ixgbe_cache_ring_register(adapter);
3950
3951 return 0;
3952
3953err_rx_ring_allocation:
4a0b9ca0
PW		 3954 for (i = 0; i < adapter->num_tx_queues; i++)
3955 kfree(adapter->tx_ring[i]);
021230d4
AV		 3956err_tx_ring_allocation:
3957 return -ENOMEM;
3958}
3959
3960/**
3961 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3962 * @adapter: board private structure to initialize
3963 *
3964 * Attempt to configure the interrupts using the best available
3965 * capabilities of the hardware and the kernel.
3966 **/
feea6a57 3967static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3968{
8be0e467 3969 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3970 int err = 0;
3971 int vector, v_budget;
3972
3973 /*
3974 * It's easy to be greedy for MSI-X vectors, but it really
3975 * doesn't do us much good if we have a lot more vectors
3976 * than CPU's. So let's be conservative and only ask for
342bde1b 3977 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3978 */
3979 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3980 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3981
3982 /*
3983 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3984 * hw.mac->max_msix_vectors vectors. With features
3985 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3986 * descriptor queues supported by our device. Thus, we cap it off in
3987 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3988 */
8be0e467 3989 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3990
3991 /* A failure in MSI-X entry allocation isn't fatal, but it does
3992 * mean we disable MSI-X capabilities of the adapter. */
3993 adapter->msix_entries = kcalloc(v_budget,
b4617240 3994 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3995 if (adapter->msix_entries) {
3996 for (vector = 0; vector < v_budget; vector++)
3997 adapter->msix_entries[vector].entry = vector;
021230d4 3998
7a921c93 3999 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4000
7a921c93
AD		 4001 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4002 goto out;
4003 }
021230d4 4004
7a921c93
AD		 4005 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4006 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4007 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4008 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4009 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4010 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4011 ixgbe_disable_sriov(adapter);
4012
7a921c93 4013 ixgbe_set_num_queues(adapter);
021230d4 4014
021230d4
AV		 4015 err = pci_enable_msi(adapter->pdev);
4016 if (!err) {
4017 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4018 } else {
4019 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 4020 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4021 /* reset err */
4022 err = 0;
4023 }
4024
4025out:
021230d4
AV		 4026 return err;
4027}
4028
7a921c93
AD		 4029/**
4030 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4031 * @adapter: board private structure to initialize
4032 *
4033 * We allocate one q_vector per queue interrupt. If allocation fails we
4034 * return -ENOMEM.
4035 **/
4036static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4037{
4038 int q_idx, num_q_vectors;
4039 struct ixgbe_q_vector *q_vector;
4040 int napi_vectors;
4041 int (*poll)(struct napi_struct *, int);
4042
4043 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4044 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4045 napi_vectors = adapter->num_rx_queues;
91281fd3 4046 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4047 } else {
4048 num_q_vectors = 1;
4049 napi_vectors = 1;
4050 poll = &ixgbe_poll;
4051 }
4052
4053 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2
JB		 4054 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4055 GFP_KERNEL, adapter->node);
4056 if (!q_vector)
4057 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4058 GFP_KERNEL);
7a921c93
AD		 4059 if (!q_vector)
4060 goto err_out;
4061 q_vector->adapter = adapter;
f7554a2b
NS		 4062 if (q_vector->txr_count && !q_vector->rxr_count)
4063 q_vector->eitr = adapter->tx_eitr_param;
4064 else
4065 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4066 q_vector->v_idx = q_idx;
91281fd3 4067 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4068 adapter->q_vector[q_idx] = q_vector;
4069 }
4070
4071 return 0;
4072
4073err_out:
4074 while (q_idx) {
4075 q_idx--;
4076 q_vector = adapter->q_vector[q_idx];
4077 netif_napi_del(&q_vector->napi);
4078 kfree(q_vector);
4079 adapter->q_vector[q_idx] = NULL;
4080 }
4081 return -ENOMEM;
4082}
4083
4084/**
4085 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4086 * @adapter: board private structure to initialize
4087 *
4088 * This function frees the memory allocated to the q_vectors. In addition if
4089 * NAPI is enabled it will delete any references to the NAPI struct prior
4090 * to freeing the q_vector.
4091 **/
4092static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4093{
4094 int q_idx, num_q_vectors;
7a921c93 4095
91281fd3 4096 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4097 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4098 else
7a921c93 4099 num_q_vectors = 1;
7a921c93
AD		 4100
4101 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4102 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4103 adapter->q_vector[q_idx] = NULL;
91281fd3 4104 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4105 kfree(q_vector);
4106 }
4107}
4108
7b25cdba 4109static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4110{
4111 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4112 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4113 pci_disable_msix(adapter->pdev);
4114 kfree(adapter->msix_entries);
4115 adapter->msix_entries = NULL;
4116 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4117 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4118 pci_disable_msi(adapter->pdev);
4119 }
4120 return;
4121}
4122
4123/**
4124 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4125 * @adapter: board private structure to initialize
4126 *
4127 * We determine which interrupt scheme to use based on...
4128 * - Kernel support (MSI, MSI-X)
4129 * - which can be user-defined (via MODULE_PARAM)
4130 * - Hardware queue count (num_*_queues)
4131 * - defined by miscellaneous hardware support/features (RSS, etc.)
4132 **/
2f90b865 4133int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4134{
4135 int err;
4136
4137 /* Number of supported queues */
4138 ixgbe_set_num_queues(adapter);
4139
021230d4
AV		 4140 err = ixgbe_set_interrupt_capability(adapter);
4141 if (err) {
4142 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4143 goto err_set_interrupt;
9a799d71
AK		 4144 }
4145
7a921c93
AD		 4146 err = ixgbe_alloc_q_vectors(adapter);
4147 if (err) {
4148 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4149 "vectors\n");
4150 goto err_alloc_q_vectors;
4151 }
4152
4153 err = ixgbe_alloc_queues(adapter);
4154 if (err) {
4155 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4156 goto err_alloc_queues;
4157 }
4158
021230d4 4159 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 4160 "Tx Queue count = %u\n",
4161 (adapter->num_rx_queues > 1) ? "Enabled" :
4162 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4163
4164 set_bit(__IXGBE_DOWN, &adapter->state);
4165
9a799d71 4166 return 0;
021230d4 4167
7a921c93
AD		 4168err_alloc_queues:
4169 ixgbe_free_q_vectors(adapter);
4170err_alloc_q_vectors:
4171 ixgbe_reset_interrupt_capability(adapter);
021230d4 4172err_set_interrupt:
7a921c93
AD		 4173 return err;
4174}
4175
4176/**
4177 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4178 * @adapter: board private structure to clear interrupt scheme on
4179 *
4180 * We go through and clear interrupt specific resources and reset the structure
4181 * to pre-load conditions
4182 **/
4183void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4184{
4a0b9ca0
PW		 4185 int i;
4186
4187 for (i = 0; i < adapter->num_tx_queues; i++) {
4188 kfree(adapter->tx_ring[i]);
4189 adapter->tx_ring[i] = NULL;
4190 }
4191 for (i = 0; i < adapter->num_rx_queues; i++) {
4192 kfree(adapter->rx_ring[i]);
4193 adapter->rx_ring[i] = NULL;
4194 }
7a921c93
AD		 4195
4196 ixgbe_free_q_vectors(adapter);
4197 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4198}
4199
c4900be0
DS		 4200/**
4201 * ixgbe_sfp_timer - worker thread to find a missing module
4202 * @data: pointer to our adapter struct
4203 **/
4204static void ixgbe_sfp_timer(unsigned long data)
4205{
4206 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4207
4df10466
JB		 4208 /*
4209 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4210 * delays that sfp+ detection requires
4211 */
4212 schedule_work(&adapter->sfp_task);
4213}
4214
4215/**
4216 * ixgbe_sfp_task - worker thread to find a missing module
4217 * @work: pointer to work_struct containing our data
4218 **/
4219static void ixgbe_sfp_task(struct work_struct *work)
4220{
4221 struct ixgbe_adapter *adapter = container_of(work,
4222 struct ixgbe_adapter,
4223 sfp_task);
4224 struct ixgbe_hw *hw = &adapter->hw;
4225
4226 if ((hw->phy.type == ixgbe_phy_nl) &&
4227 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4228 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4229 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4230 goto reschedule;
4231 ret = hw->phy.ops.reset(hw);
4232 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4233 dev_err(&adapter->pdev->dev, "failed to initialize "
4234 "because an unsupported SFP+ module type "
4235 "was detected.\n"
4236 "Reload the driver after installing a "
4237 "supported module.\n");
c4900be0
DS		 4238 unregister_netdev(adapter->netdev);
4239 } else {
4240 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4241 hw->phy.sfp_type);
4242 }
4243 /* don't need this routine any more */
4244 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4245 }
4246 return;
4247reschedule:
4248 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4249 mod_timer(&adapter->sfp_timer,
4250 round_jiffies(jiffies + (2 * HZ)));
4251}
4252
9a799d71
AK		 4253/**
4254 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4255 * @adapter: board private structure to initialize
4256 *
4257 * ixgbe_sw_init initializes the Adapter private data structure.
4258 * Fields are initialized based on PCI device information and
4259 * OS network device settings (MTU size).
4260 **/
4261static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4262{
4263 struct ixgbe_hw *hw = &adapter->hw;
4264 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4265 struct net_device *dev = adapter->netdev;
021230d4 4266 unsigned int rss;
7a6b6f51 4267#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4268 int j;
4269 struct tc_configuration *tc;
4270#endif
021230d4 4271
c44ade9e
JB		 4272 /* PCI config space info */
4273
4274 hw->vendor_id = pdev->vendor;
4275 hw->device_id = pdev->device;
4276 hw->revision_id = pdev->revision;
4277 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4278 hw->subsystem_device_id = pdev->subsystem_device;
4279
021230d4
AV		 4280 /* Set capability flags */
4281 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4282 adapter->ring_feature[RING_F_RSS].indices = rss;
4283 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4284 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4285 if (hw->mac.type == ixgbe_mac_82598EB) {
4286 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4287 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4288 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4289 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4290 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4291 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4292 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9a713e7c
PW		 4293 if (dev->features & NETIF_F_NTUPLE) {
4294 /* Flow Director perfect filter enabled */
4295 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4296 adapter->atr_sample_rate = 0;
4297 spin_lock_init(&adapter->fdir_perfect_lock);
4298 } else {
4299 /* Flow Director hash filters enabled */
4300 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4301 adapter->atr_sample_rate = 20;
4302 }
c4cf55e5
PWJ		 4303 adapter->ring_feature[RING_F_FDIR].indices =
4304 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4305 adapter->fdir_pballoc = 0;
eacd73f7 4306#ifdef IXGBE_FCOE
0d551589
YZ		 4307 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4308 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4309 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4310#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4311 /* Default traffic class to use for FCoE */
4312 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 4313#endif
eacd73f7 4314#endif /* IXGBE_FCOE */
f8212f97 4315 }
2f90b865 4316
7a6b6f51 4317#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4318 /* Configure DCB traffic classes */
4319 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4320 tc = &adapter->dcb_cfg.tc_config[j];
4321 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4322 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4323 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4324 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4325 tc->dcb_pfc = pfc_disabled;
4326 }
4327 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4328 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4329 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4330 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4331 adapter->dcb_cfg.round_robin_enable = false;
4332 adapter->dcb_set_bitmap = 0x00;
4333 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4334 adapter->ring_feature[RING_F_DCB].indices);
4335
4336#endif
9a799d71
AK		 4337
4338 /* default flow control settings */
cd7664f6 4339 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4340 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4341#ifdef CONFIG_DCB
4342 adapter->last_lfc_mode = hw->fc.current_mode;
4343#endif
2b9ade93
JB		 4344 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4345 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4346 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4347 hw->fc.send_xon = true;
71fd570b 4348 hw->fc.disable_fc_autoneg = false;
9a799d71 4349
30efa5a3 4350 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4351 adapter->rx_itr_setting = 1;
4352 adapter->rx_eitr_param = 20000;
4353 adapter->tx_itr_setting = 1;
4354 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4355
4356 /* set defaults for eitr in MegaBytes */
4357 adapter->eitr_low = 10;
4358 adapter->eitr_high = 20;
4359
4360 /* set default ring sizes */
4361 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4362 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4363
9a799d71 4364 /* initialize eeprom parameters */
c44ade9e 4365 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4366 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4367 return -EIO;
4368 }
4369
021230d4 4370 /* enable rx csum by default */
9a799d71
AK		 4371 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4372
1a6c14a2
JB		 4373 /* get assigned NUMA node */
4374 adapter->node = dev_to_node(&pdev->dev);
4375
9a799d71
AK		 4376 set_bit(__IXGBE_DOWN, &adapter->state);
4377
4378 return 0;
4379}
4380
4381/**
4382 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4383 * @adapter: board private structure
3a581073 4384 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4385 *
4386 * Return 0 on success, negative on failure
4387 **/
4388int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4389 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4390{
4391 struct pci_dev *pdev = adapter->pdev;
4392 int size;
4393
3a581073 4394 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4395 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4396 if (!tx_ring->tx_buffer_info)
4397 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4398 if (!tx_ring->tx_buffer_info)
4399 goto err;
3a581073 4400 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4401
4402 /* round up to nearest 4K */
12207e49 4403 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4404 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4405
3a581073
JB		 4406 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4407 &tx_ring->dma);
e01c31a5
JB		 4408 if (!tx_ring->desc)
4409 goto err;
9a799d71 4410
3a581073
JB		 4411 tx_ring->next_to_use = 0;
4412 tx_ring->next_to_clean = 0;
4413 tx_ring->work_limit = tx_ring->count;
9a799d71 4414 return 0;
e01c31a5
JB		 4415
4416err:
4417 vfree(tx_ring->tx_buffer_info);
4418 tx_ring->tx_buffer_info = NULL;
4419 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4420 "descriptor ring\n");
4421 return -ENOMEM;
9a799d71
AK		 4422}
4423
69888674
AD		 4424/**
4425 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4426 * @adapter: board private structure
4427 *
4428 * If this function returns with an error, then it's possible one or
4429 * more of the rings is populated (while the rest are not). It is the
4430 * callers duty to clean those orphaned rings.
4431 *
4432 * Return 0 on success, negative on failure
4433 **/
4434static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4435{
4436 int i, err = 0;
4437
4438 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4439 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4440 if (!err)
4441 continue;
4442 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4443 break;
4444 }
4445
4446 return err;
4447}
4448
9a799d71
AK		 4449/**
4450 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4451 * @adapter: board private structure
3a581073 4452 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4453 *
4454 * Returns 0 on success, negative on failure
4455 **/
4456int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4457 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4458{
4459 struct pci_dev *pdev = adapter->pdev;
021230d4 4460 int size;
9a799d71 4461
3a581073 4462 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 4463 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4464 if (!rx_ring->rx_buffer_info)
4465 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 4466 if (!rx_ring->rx_buffer_info) {
9a799d71 4467 DPRINTK(PROBE, ERR,
b4617240 4468 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4469 goto alloc_failed;
9a799d71 4470 }
3a581073 4471 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4472
9a799d71 4473 /* Round up to nearest 4K */
3a581073
JB		 4474 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4475 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4476
3a581073 4477 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4478
3a581073 4479 if (!rx_ring->desc) {
9a799d71 4480 DPRINTK(PROBE, ERR,
b4617240 4481 "Memory allocation failed for the rx desc ring\n");
3a581073 4482 vfree(rx_ring->rx_buffer_info);
177db6ff 4483 goto alloc_failed;
9a799d71
AK		 4484 }
4485
3a581073
JB		 4486 rx_ring->next_to_clean = 0;
4487 rx_ring->next_to_use = 0;
9a799d71
AK		 4488
4489 return 0;
177db6ff
MC		 4490
4491alloc_failed:
177db6ff 4492 return -ENOMEM;
9a799d71
AK		 4493}
4494
69888674
AD		 4495/**
4496 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4497 * @adapter: board private structure
4498 *
4499 * If this function returns with an error, then it's possible one or
4500 * more of the rings is populated (while the rest are not). It is the
4501 * callers duty to clean those orphaned rings.
4502 *
4503 * Return 0 on success, negative on failure
4504 **/
4505
4506static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4507{
4508 int i, err = 0;
4509
4510 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 4511 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 4512 if (!err)
4513 continue;
4514 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4515 break;
4516 }
4517
4518 return err;
4519}
4520
9a799d71
AK		 4521/**
4522 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4523 * @adapter: board private structure
4524 * @tx_ring: Tx descriptor ring for a specific queue
4525 *
4526 * Free all transmit software resources
4527 **/
c431f97e
JB		 4528void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4529 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4530{
4531 struct pci_dev *pdev = adapter->pdev;
4532
4533 ixgbe_clean_tx_ring(adapter, tx_ring);
4534
4535 vfree(tx_ring->tx_buffer_info);
4536 tx_ring->tx_buffer_info = NULL;
4537
4538 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4539
4540 tx_ring->desc = NULL;
4541}
4542
4543/**
4544 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4545 * @adapter: board private structure
4546 *
4547 * Free all transmit software resources
4548 **/
4549static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4550{
4551 int i;
4552
4553 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 4554 if (adapter->tx_ring[i]->desc)
4555 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 4556}
4557
4558/**
b4617240 4559 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4560 * @adapter: board private structure
4561 * @rx_ring: ring to clean the resources from
4562 *
4563 * Free all receive software resources
4564 **/
c431f97e
JB		 4565void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4566 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4567{
4568 struct pci_dev *pdev = adapter->pdev;
4569
4570 ixgbe_clean_rx_ring(adapter, rx_ring);
4571
4572 vfree(rx_ring->rx_buffer_info);
4573 rx_ring->rx_buffer_info = NULL;
4574
4575 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4576
4577 rx_ring->desc = NULL;
4578}
4579
4580/**
4581 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4582 * @adapter: board private structure
4583 *
4584 * Free all receive software resources
4585 **/
4586static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4587{
4588 int i;
4589
4590 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 4591 if (adapter->rx_ring[i]->desc)
4592 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 4593}
4594
9a799d71
AK		 4595/**
4596 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4597 * @netdev: network interface device structure
4598 * @new_mtu: new value for maximum frame size
4599 *
4600 * Returns 0 on success, negative on failure
4601 **/
4602static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4603{
4604 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4605 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4606
42c783c5
JB		 4607 /* MTU < 68 is an error and causes problems on some kernels */
4608 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4609 return -EINVAL;
4610
021230d4 4611 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4612 netdev->mtu, new_mtu);
021230d4 4613 /* must set new MTU before calling down or up */
9a799d71
AK		 4614 netdev->mtu = new_mtu;
4615
d4f80882
AV		 4616 if (netif_running(netdev))
4617 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4618
4619 return 0;
4620}
4621
4622/**
4623 * ixgbe_open - Called when a network interface is made active
4624 * @netdev: network interface device structure
4625 *
4626 * Returns 0 on success, negative value on failure
4627 *
4628 * The open entry point is called when a network interface is made
4629 * active by the system (IFF_UP). At this point all resources needed
4630 * for transmit and receive operations are allocated, the interrupt
4631 * handler is registered with the OS, the watchdog timer is started,
4632 * and the stack is notified that the interface is ready.
4633 **/
4634static int ixgbe_open(struct net_device *netdev)
4635{
4636 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4637 int err;
4bebfaa5
AK		 4638
4639 /* disallow open during test */
4640 if (test_bit(__IXGBE_TESTING, &adapter->state))
4641 return -EBUSY;
9a799d71 4642
54386467
JB		 4643 netif_carrier_off(netdev);
4644
9a799d71
AK		 4645 /* allocate transmit descriptors */
4646 err = ixgbe_setup_all_tx_resources(adapter);
4647 if (err)
4648 goto err_setup_tx;
4649
9a799d71
AK		 4650 /* allocate receive descriptors */
4651 err = ixgbe_setup_all_rx_resources(adapter);
4652 if (err)
4653 goto err_setup_rx;
4654
4655 ixgbe_configure(adapter);
4656
021230d4 4657 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4658 if (err)
4659 goto err_req_irq;
4660
9a799d71
AK		 4661 err = ixgbe_up_complete(adapter);
4662 if (err)
4663 goto err_up;
4664
d55b53ff
JK		 4665 netif_tx_start_all_queues(netdev);
4666
9a799d71
AK		 4667 return 0;
4668
4669err_up:
5eba3699 4670 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4671 ixgbe_free_irq(adapter);
4672err_req_irq:
9a799d71 4673err_setup_rx:
a20a1199 4674 ixgbe_free_all_rx_resources(adapter);
9a799d71 4675err_setup_tx:
a20a1199 4676 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4677 ixgbe_reset(adapter);
4678
4679 return err;
4680}
4681
4682/**
4683 * ixgbe_close - Disables a network interface
4684 * @netdev: network interface device structure
4685 *
4686 * Returns 0, this is not allowed to fail
4687 *
4688 * The close entry point is called when an interface is de-activated
4689 * by the OS. The hardware is still under the drivers control, but
4690 * needs to be disabled. A global MAC reset is issued to stop the
4691 * hardware, and all transmit and receive resources are freed.
4692 **/
4693static int ixgbe_close(struct net_device *netdev)
4694{
4695 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4696
4697 ixgbe_down(adapter);
4698 ixgbe_free_irq(adapter);
4699
4700 ixgbe_free_all_tx_resources(adapter);
4701 ixgbe_free_all_rx_resources(adapter);
4702
5eba3699 4703 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4704
4705 return 0;
4706}
4707
b3c8b4ba
AD		 4708#ifdef CONFIG_PM
4709static int ixgbe_resume(struct pci_dev *pdev)
4710{
4711 struct net_device *netdev = pci_get_drvdata(pdev);
4712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4713 u32 err;
4714
4715 pci_set_power_state(pdev, PCI_D0);
4716 pci_restore_state(pdev);
656ab817
DS		 4717 /*
4718 * pci_restore_state clears dev->state_saved so call
4719 * pci_save_state to restore it.
4720 */
4721 pci_save_state(pdev);
9ce77666 4722
4723 err = pci_enable_device_mem(pdev);
b3c8b4ba 4724 if (err) {
69888674 4725 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4726 "suspend\n");
4727 return err;
4728 }
4729 pci_set_master(pdev);
4730
dd4d8ca6 4731 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4732
4733 err = ixgbe_init_interrupt_scheme(adapter);
4734 if (err) {
4735 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4736 "device\n");
4737 return err;
4738 }
4739
b3c8b4ba
AD		 4740 ixgbe_reset(adapter);
4741
495dce12
WJP		 4742 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4743
b3c8b4ba
AD		 4744 if (netif_running(netdev)) {
4745 err = ixgbe_open(adapter->netdev);
4746 if (err)
4747 return err;
4748 }
4749
4750 netif_device_attach(netdev);
4751
4752 return 0;
4753}
b3c8b4ba 4754#endif /* CONFIG_PM */
9d8d05ae
RW		 4755
4756static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4757{
4758 struct net_device *netdev = pci_get_drvdata(pdev);
4759 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4760 struct ixgbe_hw *hw = &adapter->hw;
4761 u32 ctrl, fctrl;
4762 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4763#ifdef CONFIG_PM
4764 int retval = 0;
4765#endif
4766
4767 netif_device_detach(netdev);
4768
4769 if (netif_running(netdev)) {
4770 ixgbe_down(adapter);
4771 ixgbe_free_irq(adapter);
4772 ixgbe_free_all_tx_resources(adapter);
4773 ixgbe_free_all_rx_resources(adapter);
4774 }
7a921c93 4775 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4776
4777#ifdef CONFIG_PM
4778 retval = pci_save_state(pdev);
4779 if (retval)
4780 return retval;
4df10466 4781
b3c8b4ba 4782#endif
e8e26350
PW		 4783 if (wufc) {
4784 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4785
e8e26350
PW		 4786 /* turn on all-multi mode if wake on multicast is enabled */
4787 if (wufc & IXGBE_WUFC_MC) {
4788 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4789 fctrl |= IXGBE_FCTRL_MPE;
4790 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4791 }
4792
4793 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4794 ctrl |= IXGBE_CTRL_GIO_DIS;
4795 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4796
4797 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4798 } else {
4799 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4800 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4801 }
4802
dd4d8ca6
DS		 4803 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4804 pci_wake_from_d3(pdev, true);
4805 else
4806 pci_wake_from_d3(pdev, false);
b3c8b4ba 4807
9d8d05ae
RW		 4808 *enable_wake = !!wufc;
4809
b3c8b4ba
AD		 4810 ixgbe_release_hw_control(adapter);
4811
4812 pci_disable_device(pdev);
4813
9d8d05ae
RW		 4814 return 0;
4815}
4816
4817#ifdef CONFIG_PM
4818static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4819{
4820 int retval;
4821 bool wake;
4822
4823 retval = __ixgbe_shutdown(pdev, &wake);
4824 if (retval)
4825 return retval;
4826
4827 if (wake) {
4828 pci_prepare_to_sleep(pdev);
4829 } else {
4830 pci_wake_from_d3(pdev, false);
4831 pci_set_power_state(pdev, PCI_D3hot);
4832 }
b3c8b4ba
AD		 4833
4834 return 0;
4835}
9d8d05ae 4836#endif /* CONFIG_PM */
b3c8b4ba
AD		 4837
4838static void ixgbe_shutdown(struct pci_dev *pdev)
4839{
9d8d05ae
RW		 4840 bool wake;
4841
4842 __ixgbe_shutdown(pdev, &wake);
4843
4844 if (system_state == SYSTEM_POWER_OFF) {
4845 pci_wake_from_d3(pdev, wake);
4846 pci_set_power_state(pdev, PCI_D3hot);
4847 }
b3c8b4ba
AD		 4848}
4849
9a799d71
AK		 4850/**
4851 * ixgbe_update_stats - Update the board statistics counters.
4852 * @adapter: board private structure
4853 **/
4854void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4855{
2d86f139 4856 struct net_device *netdev = adapter->netdev;
9a799d71 4857 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4858 u64 total_mpc = 0;
4859 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 4860 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 4861
94b982b2 4862 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 4863 u64 rsc_count = 0;
94b982b2 4864 u64 rsc_flush = 0;
d51019a4
PW		 4865 for (i = 0; i < 16; i++)
4866 adapter->hw_rx_no_dma_resources +=
4867 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 4868 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4869 rsc_count += adapter->rx_ring[i]->rsc_count;
4870 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 4871 }
4872 adapter->rsc_total_count = rsc_count;
4873 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 4874 }
4875
7ca3bc58
JB		 4876 /* gather some stats to the adapter struct that are per queue */
4877 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4878 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 4879 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 4880
4881 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4882 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 4883 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 4884
9a799d71 4885 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4886 for (i = 0; i < 8; i++) {
4887 /* for packet buffers not used, the register should read 0 */
4888 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4889 missed_rx += mpc;
4890 adapter->stats.mpc[i] += mpc;
4891 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4892 if (hw->mac.type == ixgbe_mac_82598EB)
4893 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4894 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4895 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4896 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4897 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4898 if (hw->mac.type == ixgbe_mac_82599EB) {
4899 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4900 IXGBE_PXONRXCNT(i));
4901 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4902 IXGBE_PXOFFRXCNT(i));
4903 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4904 } else {
4905 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4906 IXGBE_PXONRXC(i));
4907 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4908 IXGBE_PXOFFRXC(i));
4909 }
2f90b865
AD		 4910 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4911 IXGBE_PXONTXC(i));
2f90b865 4912 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4913 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4914 }
4915 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4916 /* work around hardware counting issue */
4917 adapter->stats.gprc -= missed_rx;
4918
4919 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4920 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4921 u64 tmp;
e8e26350 4922 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4923 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4924 adapter->stats.gorc += (tmp << 32);
e8e26350 4925 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4926 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4927 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4928 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4929 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4930 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4931 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4932 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4933 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4934#ifdef IXGBE_FCOE
4935 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4936 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4937 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4938 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4939 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4940 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4941#endif /* IXGBE_FCOE */
e8e26350
PW		 4942 } else {
4943 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4944 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4945 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4946 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4947 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4948 }
9a799d71
AK		 4949 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4950 adapter->stats.bprc += bprc;
4951 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4952 if (hw->mac.type == ixgbe_mac_82598EB)
4953 adapter->stats.mprc -= bprc;
9a799d71
AK		 4954 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4955 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4956 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4957 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4958 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4959 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4960 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4961 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4962 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4963 adapter->stats.lxontxc += lxon;
4964 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4965 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4966 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4967 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4968 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4969 /*
4970 * 82598 errata - tx of flow control packets is included in tx counters
4971 */
4972 xon_off_tot = lxon + lxoff;
4973 adapter->stats.gptc -= xon_off_tot;
4974 adapter->stats.mptc -= xon_off_tot;
4975 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4976 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4977 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4978 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4979 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4980 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4981 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4982 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4983 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4984 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4985 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4986 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4987 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4988
4989 /* Fill out the OS statistics structure */
2d86f139 4990 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4991
4992 /* Rx Errors */
2d86f139 4993 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 4994 adapter->stats.rlec;
2d86f139
AK		 4995 netdev->stats.rx_dropped = 0;
4996 netdev->stats.rx_length_errors = adapter->stats.rlec;
4997 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4998 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4999}
5000
5001/**
5002 * ixgbe_watchdog - Timer Call-back
5003 * @data: pointer to adapter cast into an unsigned long
5004 **/
5005static void ixgbe_watchdog(unsigned long data)
5006{
5007 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5008 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5009 u64 eics = 0;
5010 int i;
cf8280ee 5011
fe49f04a
AD		 5012 /*
5013 * Do the watchdog outside of interrupt context due to the lovely
5014 * delays that some of the newer hardware requires
5015 */
22d5a71b 5016
fe49f04a
AD		 5017 if (test_bit(__IXGBE_DOWN, &adapter->state))
5018 goto watchdog_short_circuit;
22d5a71b 5019
fe49f04a
AD		 5020 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5021 /*
5022 * for legacy and MSI interrupts don't set any bits
5023 * that are enabled for EIAM, because this operation
5024 * would set *both* EIMS and EICS for any bit in EIAM
5025 */
5026 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5027 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5028 goto watchdog_reschedule;
5029 }
5030
5031 /* get one bit for every active tx/rx interrupt vector */
5032 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5033 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5034 if (qv->rxr_count || qv->txr_count)
5035 eics |= ((u64)1 << i);
cf8280ee 5036 }
9a799d71 5037
fe49f04a
AD		 5038 /* Cause software interrupt to ensure rx rings are cleaned */
5039 ixgbe_irq_rearm_queues(adapter, eics);
5040
5041watchdog_reschedule:
5042 /* Reset the timer */
5043 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5044
5045watchdog_short_circuit:
cf8280ee
JB		 5046 schedule_work(&adapter->watchdog_task);
5047}
5048
e8e26350
PW		 5049/**
5050 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5051 * @work: pointer to work_struct containing our data
5052 **/
5053static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5054{
5055 struct ixgbe_adapter *adapter = container_of(work,
5056 struct ixgbe_adapter,
5057 multispeed_fiber_task);
5058 struct ixgbe_hw *hw = &adapter->hw;
5059 u32 autoneg;
8620a103 5060 bool negotiation;
e8e26350
PW		 5061
5062 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5063 autoneg = hw->phy.autoneg_advertised;
5064 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5065 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5066 hw->mac.autotry_restart = false;
8620a103
MC		 5067 if (hw->mac.ops.setup_link)
5068 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5069 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5070 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5071}
5072
5073/**
5074 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5075 * @work: pointer to work_struct containing our data
5076 **/
5077static void ixgbe_sfp_config_module_task(struct work_struct *work)
5078{
5079 struct ixgbe_adapter *adapter = container_of(work,
5080 struct ixgbe_adapter,
5081 sfp_config_module_task);
5082 struct ixgbe_hw *hw = &adapter->hw;
5083 u32 err;
5084
5085 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5086
5087 /* Time for electrical oscillations to settle down */
5088 msleep(100);
e8e26350 5089 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5090
e8e26350 5091 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5092 dev_err(&adapter->pdev->dev, "failed to initialize because "
5093 "an unsupported SFP+ module type was detected.\n"
5094 "Reload the driver after installing a supported "
5095 "module.\n");
63d6e1d8 5096 unregister_netdev(adapter->netdev);
e8e26350
PW		 5097 return;
5098 }
5099 hw->mac.ops.setup_sfp(hw);
5100
8d1c3c07 5101 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5102 /* This will also work for DA Twinax connections */
5103 schedule_work(&adapter->multispeed_fiber_task);
5104 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5105}
5106
c4cf55e5
PWJ		 5107/**
5108 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5109 * @work: pointer to work_struct containing our data
5110 **/
5111static void ixgbe_fdir_reinit_task(struct work_struct *work)
5112{
5113 struct ixgbe_adapter *adapter = container_of(work,
5114 struct ixgbe_adapter,
5115 fdir_reinit_task);
5116 struct ixgbe_hw *hw = &adapter->hw;
5117 int i;
5118
5119 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5120 for (i = 0; i < adapter->num_tx_queues; i++)
5121 set_bit(__IXGBE_FDIR_INIT_DONE,
4a0b9ca0 5122 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5
PWJ		 5123 } else {
5124 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
d6dbee86 5125 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5126 }
5127 /* Done FDIR Re-initialization, enable transmits */
5128 netif_tx_start_all_queues(adapter->netdev);
5129}
5130
10eec955
JF		 5131static DEFINE_MUTEX(ixgbe_watchdog_lock);
5132
cf8280ee 5133/**
69888674
AD		 5134 * ixgbe_watchdog_task - worker thread to bring link up
5135 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5136 **/
5137static void ixgbe_watchdog_task(struct work_struct *work)
5138{
5139 struct ixgbe_adapter *adapter = container_of(work,
5140 struct ixgbe_adapter,
5141 watchdog_task);
5142 struct net_device *netdev = adapter->netdev;
5143 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5144 u32 link_speed;
5145 bool link_up;
bc59fcda
NS		 5146 int i;
5147 struct ixgbe_ring *tx_ring;
5148 int some_tx_pending = 0;
cf8280ee 5149
10eec955
JF		 5150 mutex_lock(&ixgbe_watchdog_lock);
5151
5152 link_up = adapter->link_up;
5153 link_speed = adapter->link_speed;
cf8280ee
JB		 5154
5155 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5156 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5157 if (link_up) {
5158#ifdef CONFIG_DCB
5159 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5160 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5161 hw->mac.ops.fc_enable(hw, i);
264857b8 5162 } else {
620fa036 5163 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5164 }
5165#else
620fa036 5166 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5167#endif
5168 }
5169
cf8280ee
JB		 5170 if (link_up ||
5171 time_after(jiffies, (adapter->link_check_timeout +
5172 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5173 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5174 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5175 }
5176 adapter->link_up = link_up;
5177 adapter->link_speed = link_speed;
5178 }
9a799d71
AK		 5179
5180 if (link_up) {
5181 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5182 bool flow_rx, flow_tx;
5183
5184 if (hw->mac.type == ixgbe_mac_82599EB) {
5185 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5186 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5187 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5188 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5189 } else {
5190 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5191 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5192 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5193 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5194 }
5195
a46e534b
JK		 5196 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5197 "Flow Control: %s\n",
5198 netdev->name,
5199 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5200 "10 Gbps" :
5201 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5202 "1 Gbps" : "unknown speed")),
e8e26350
PW		 5203 ((flow_rx && flow_tx) ? "RX/TX" :
5204 (flow_rx ? "RX" :
5205 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5206
5207 netif_carrier_on(netdev);
9a799d71
AK		 5208 } else {
5209 /* Force detection of hung controller */
5210 adapter->detect_tx_hung = true;
5211 }
5212 } else {
cf8280ee
JB		 5213 adapter->link_up = false;
5214 adapter->link_speed = 0;
9a799d71 5215 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 5216 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5217 netdev->name);
9a799d71 5218 netif_carrier_off(netdev);
9a799d71
AK		 5219 }
5220 }
5221
bc59fcda
NS		 5222 if (!netif_carrier_ok(netdev)) {
5223 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5224 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5225 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5226 some_tx_pending = 1;
5227 break;
5228 }
5229 }
5230
5231 if (some_tx_pending) {
5232 /* We've lost link, so the controller stops DMA,
5233 * but we've got queued Tx work that's never going
5234 * to get done, so reset controller to flush Tx.
5235 * (Do the reset outside of interrupt context).
5236 */
5237 schedule_work(&adapter->reset_task);
5238 }
5239 }
5240
9a799d71 5241 ixgbe_update_stats(adapter);
10eec955 5242 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5243}
5244
9a799d71 5245static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5246 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5247 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5248{
5249 struct ixgbe_adv_tx_context_desc *context_desc;
5250 unsigned int i;
5251 int err;
5252 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5253 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5254 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5255
5256 if (skb_is_gso(skb)) {
5257 if (skb_header_cloned(skb)) {
5258 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5259 if (err)
5260 return err;
5261 }
5262 l4len = tcp_hdrlen(skb);
5263 *hdr_len += l4len;
5264
8327d000 5265 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5266 struct iphdr *iph = ip_hdr(skb);
5267 iph->tot_len = 0;
5268 iph->check = 0;
5269 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5270 iph->daddr, 0,
5271 IPPROTO_TCP,
5272 0);
8e1e8a47 5273 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5274 ipv6_hdr(skb)->payload_len = 0;
5275 tcp_hdr(skb)->check =
5276 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5277 &ipv6_hdr(skb)->daddr,
5278 0, IPPROTO_TCP, 0);
9a799d71
AK		 5279 }
5280
5281 i = tx_ring->next_to_use;
5282
5283 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5284 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5285
5286 /* VLAN MACLEN IPLEN */
5287 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5288 vlan_macip_lens |=
5289 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5290 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5291 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5292 *hdr_len += skb_network_offset(skb);
5293 vlan_macip_lens |=
5294 (skb_transport_header(skb) - skb_network_header(skb));
5295 *hdr_len +=
5296 (skb_transport_header(skb) - skb_network_header(skb));
5297 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5298 context_desc->seqnum_seed = 0;
5299
5300 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5301 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5302 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5303
8327d000 5304 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5305 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5306 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5307 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5308
5309 /* MSS L4LEN IDX */
9f8cdf4f 5310 mss_l4len_idx =
9a799d71
AK		 5311 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5312 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5313 /* use index 1 for TSO */
5314 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5315 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5316
5317 tx_buffer_info->time_stamp = jiffies;
5318 tx_buffer_info->next_to_watch = i;
5319
5320 i++;
5321 if (i == tx_ring->count)
5322 i = 0;
5323 tx_ring->next_to_use = i;
5324
5325 return true;
5326 }
5327 return false;
5328}
5329
5330static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5331 struct ixgbe_ring *tx_ring,
5332 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5333{
5334 struct ixgbe_adv_tx_context_desc *context_desc;
5335 unsigned int i;
5336 struct ixgbe_tx_buffer *tx_buffer_info;
5337 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5338
5339 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5340 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5341 i = tx_ring->next_to_use;
5342 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5343 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5344
5345 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5346 vlan_macip_lens |=
5347 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5348 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5349 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5350 if (skb->ip_summed == CHECKSUM_PARTIAL)
5351 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5352 skb_network_header(skb));
9a799d71
AK		 5353
5354 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5355 context_desc->seqnum_seed = 0;
5356
5357 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5358 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5359
5360 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5361 __be16 protocol;
5362
5363 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5364 const struct vlan_ethhdr *vhdr =
5365 (const struct vlan_ethhdr *)skb->data;
5366
5367 protocol = vhdr->h_vlan_encapsulated_proto;
5368 } else {
5369 protocol = skb->protocol;
5370 }
5371
5372 switch (protocol) {
09640e63 5373 case cpu_to_be16(ETH_P_IP):
9a799d71 5374 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5375 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5376 type_tucmd_mlhl |=
b4617240 5377 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5378 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5379 type_tucmd_mlhl |=
5380 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5381 break;
09640e63 5382 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5383 /* XXX what about other V6 headers?? */
5384 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5385 type_tucmd_mlhl |=
b4617240 5386 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5387 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5388 type_tucmd_mlhl |=
5389 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5390 break;
41825d71
AK		 5391 default:
5392 if (unlikely(net_ratelimit())) {
5393 DPRINTK(PROBE, WARNING,
5394 "partial checksum but proto=%x!\n",
5395 skb->protocol);
5396 }
5397 break;
5398 }
9a799d71
AK		 5399 }
5400
5401 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5402 /* use index zero for tx checksum offload */
9a799d71
AK		 5403 context_desc->mss_l4len_idx = 0;
5404
5405 tx_buffer_info->time_stamp = jiffies;
5406 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5407
9a799d71
AK		 5408 i++;
5409 if (i == tx_ring->count)
5410 i = 0;
5411 tx_ring->next_to_use = i;
5412
5413 return true;
5414 }
9f8cdf4f 5415
9a799d71
AK		 5416 return false;
5417}
5418
5419static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5420 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5421 struct sk_buff *skb, u32 tx_flags,
5422 unsigned int first)
9a799d71 5423{
e5a43549 5424 struct pci_dev *pdev = adapter->pdev;
9a799d71 5425 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5426 unsigned int len;
5427 unsigned int total = skb->len;
9a799d71
AK		 5428 unsigned int offset = 0, size, count = 0, i;
5429 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5430 unsigned int f;
9a799d71
AK		 5431
5432 i = tx_ring->next_to_use;
5433
eacd73f7
YZ		 5434 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5435 /* excluding fcoe_crc_eof for FCoE */
5436 total -= sizeof(struct fcoe_crc_eof);
5437
5438 len = min(skb_headlen(skb), total);
9a799d71
AK		 5439 while (len) {
5440 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5441 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5442
5443 tx_buffer_info->length = size;
e5a43549
AD		 5444 tx_buffer_info->mapped_as_page = false;
5445 tx_buffer_info->dma = pci_map_single(pdev,
5446 skb->data + offset,
5447 size, PCI_DMA_TODEVICE);
5448 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5449 goto dma_error;
9a799d71
AK		 5450 tx_buffer_info->time_stamp = jiffies;
5451 tx_buffer_info->next_to_watch = i;
5452
5453 len -= size;
eacd73f7 5454 total -= size;
9a799d71
AK		 5455 offset += size;
5456 count++;
44df32c5
AD		 5457
5458 if (len) {
5459 i++;
5460 if (i == tx_ring->count)
5461 i = 0;
5462 }
9a799d71
AK		 5463 }
5464
5465 for (f = 0; f < nr_frags; f++) {
5466 struct skb_frag_struct *frag;
5467
5468 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5469 len = min((unsigned int)frag->size, total);
e5a43549 5470 offset = frag->page_offset;
9a799d71
AK		 5471
5472 while (len) {
44df32c5
AD		 5473 i++;
5474 if (i == tx_ring->count)
5475 i = 0;
5476
9a799d71
AK		 5477 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5478 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5479
5480 tx_buffer_info->length = size;
e5a43549
AD		 5481 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5482 frag->page,
5483 offset, size,
5484 PCI_DMA_TODEVICE);
5485 tx_buffer_info->mapped_as_page = true;
5486 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5487 goto dma_error;
9a799d71
AK		 5488 tx_buffer_info->time_stamp = jiffies;
5489 tx_buffer_info->next_to_watch = i;
5490
5491 len -= size;
eacd73f7 5492 total -= size;
9a799d71
AK		 5493 offset += size;
5494 count++;
9a799d71 5495 }
eacd73f7
YZ		 5496 if (total == 0)
5497 break;
9a799d71 5498 }
44df32c5 5499
9a799d71
AK		 5500 tx_ring->tx_buffer_info[i].skb = skb;
5501 tx_ring->tx_buffer_info[first].next_to_watch = i;
5502
e5a43549
AD		 5503 return count;
5504
5505dma_error:
5506 dev_err(&pdev->dev, "TX DMA map failed\n");
5507
5508 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5509 tx_buffer_info->dma = 0;
5510 tx_buffer_info->time_stamp = 0;
5511 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5512 if (count)
5513 count--;
e5a43549
AD		 5514
5515 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5516 while (count--) {
5517 if (i==0)
e5a43549 5518 i += tx_ring->count;
c1fa347f 5519 i--;
e5a43549
AD		 5520 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5521 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5522 }
5523
e44d38e1 5524 return 0;
9a799d71
AK		 5525}
5526
5527static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5528 struct ixgbe_ring *tx_ring,
5529 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5530{
5531 union ixgbe_adv_tx_desc *tx_desc = NULL;
5532 struct ixgbe_tx_buffer *tx_buffer_info;
5533 u32 olinfo_status = 0, cmd_type_len = 0;
5534 unsigned int i;
5535 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5536
5537 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5538
5539 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5540
5541 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5542 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5543
5544 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5545 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5546
5547 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5548 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5549
4eeae6fd
PW		 5550 /* use index 1 context for tso */
5551 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5552 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5553 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5554 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5555
5556 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5557 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5558 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5559
eacd73f7
YZ		 5560 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5561 olinfo_status |= IXGBE_ADVTXD_CC;
5562 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5563 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5564 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5565 }
5566
9a799d71
AK		 5567 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5568
5569 i = tx_ring->next_to_use;
5570 while (count--) {
5571 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5572 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5573 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5574 tx_desc->read.cmd_type_len =
b4617240 5575 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5576 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5577 i++;
5578 if (i == tx_ring->count)
5579 i = 0;
5580 }
5581
5582 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5583
5584 /*
5585 * Force memory writes to complete before letting h/w
5586 * know there are new descriptors to fetch. (Only
5587 * applicable for weak-ordered memory model archs,
5588 * such as IA-64).
5589 */
5590 wmb();
5591
5592 tx_ring->next_to_use = i;
5593 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5594}
5595
c4cf55e5
PWJ		 5596static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5597 int queue, u32 tx_flags)
5598{
5599 /* Right now, we support IPv4 only */
5600 struct ixgbe_atr_input atr_input;
5601 struct tcphdr *th;
c4cf55e5
PWJ		 5602 struct iphdr *iph = ip_hdr(skb);
5603 struct ethhdr *eth = (struct ethhdr *)skb->data;
5604 u16 vlan_id, src_port, dst_port, flex_bytes;
5605 u32 src_ipv4_addr, dst_ipv4_addr;
5606 u8 l4type = 0;
5607
5608 /* check if we're UDP or TCP */
5609 if (iph->protocol == IPPROTO_TCP) {
5610 th = tcp_hdr(skb);
5611 src_port = th->source;
5612 dst_port = th->dest;
5613 l4type |= IXGBE_ATR_L4TYPE_TCP;
5614 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5615 } else {
5616 /* Unsupported L4 header, just bail here */
5617 return;
5618 }
5619
5620 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5621
5622 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5623 IXGBE_TX_FLAGS_VLAN_SHIFT;
5624 src_ipv4_addr = iph->saddr;
5625 dst_ipv4_addr = iph->daddr;
5626 flex_bytes = eth->h_proto;
5627
5628 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5629 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5630 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5631 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5632 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5633 /* src and dst are inverted, think how the receiver sees them */
5634 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5635 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5636
5637 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5638 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5639}
5640
e092be60 5641static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5642 struct ixgbe_ring *tx_ring, int size)
e092be60 5643{
30eba97a 5644 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5645 /* Herbert's original patch had:
5646 * smp_mb__after_netif_stop_queue();
5647 * but since that doesn't exist yet, just open code it. */
5648 smp_mb();
5649
5650 /* We need to check again in a case another CPU has just
5651 * made room available. */
5652 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5653 return -EBUSY;
5654
5655 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5656 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 5657 ++tx_ring->restart_queue;
e092be60
AV		 5658 return 0;
5659}
5660
5661static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5662 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5663{
5664 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5665 return 0;
5666 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5667}
5668
09a3b1f8
SH		 5669static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5670{
5671 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 5672 int txq = smp_processor_id();
09a3b1f8 5673
fdd3d631
KK		 5674 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5675 while (unlikely(txq >= dev->real_num_tx_queues))
5676 txq -= dev->real_num_tx_queues;
5f715823 5677 return txq;
fdd3d631 5678 }
c4cf55e5 5679
5f715823
YZ		 5680#ifdef IXGBE_FCOE
5681 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
ca77cd59
RL		 5682 ((skb->protocol == htons(ETH_P_FCOE)) ||
5683 (skb->protocol == htons(ETH_P_FIP)))) {
5f715823
YZ		 5684 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5685 txq += adapter->ring_feature[RING_F_FCOE].mask;
5686 return txq;
5687 }
5688#endif
2ea186ae
JF		 5689 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5690 if (skb->priority == TC_PRIO_CONTROL)
5691 txq = adapter->ring_feature[RING_F_DCB].indices-1;
5692 else
5693 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
5694 >> 13;
5695 return txq;
5696 }
09a3b1f8
SH		 5697
5698 return skb_tx_hash(dev, skb);
5699}
5700
3b29a56d
SH		 5701static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5702 struct net_device *netdev)
9a799d71
AK		 5703{
5704 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5705 struct ixgbe_ring *tx_ring;
60d51134 5706 struct netdev_queue *txq;
9a799d71
AK		 5707 unsigned int first;
5708 unsigned int tx_flags = 0;
30eba97a 5709 u8 hdr_len = 0;
5f715823 5710 int tso;
9a799d71
AK		 5711 int count = 0;
5712 unsigned int f;
9f8cdf4f 5713
9f8cdf4f
JB		 5714 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5715 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5716 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5717 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 5718 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 5719 }
5720 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5721 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5722 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2ea186ae
JF		 5723 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5724 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5725 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 5726 }
eacd73f7 5727
4a0b9ca0 5728 tx_ring = adapter->tx_ring[skb->queue_mapping];
60127865 5729
09ad1cc0 5730#ifdef IXGBE_FCOE
ca77cd59 5731 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
61a0f421 5732#ifdef CONFIG_IXGBE_DCB
ca77cd59
RL		 5733 /* for FCoE with DCB, we force the priority to what
5734 * was specified by the switch */
5735 if ((skb->protocol == htons(ETH_P_FCOE)) ||
5736 (skb->protocol == htons(ETH_P_FIP))) {
5737 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5738 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5739 tx_flags |= ((adapter->fcoe.up << 13)
5740 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5741 }
09ad1cc0 5742#endif
ca77cd59
RL		 5743 /* flag for FCoE offloads */
5744 if (skb->protocol == htons(ETH_P_FCOE))
5745 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 5746 }
ca77cd59
RL		 5747#endif
5748
eacd73f7 5749 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5750 if (skb_is_gso(skb) ||
5751 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5752 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5753 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5754 count++;
5755
9f8cdf4f
JB		 5756 count += TXD_USE_COUNT(skb_headlen(skb));
5757 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5758 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5759
e092be60 5760 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5761 adapter->tx_busy++;
9a799d71
AK		 5762 return NETDEV_TX_BUSY;
5763 }
9a799d71 5764
9a799d71 5765 first = tx_ring->next_to_use;
eacd73f7
YZ		 5766 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5767#ifdef IXGBE_FCOE
5768 /* setup tx offload for FCoE */
5769 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5770 if (tso < 0) {
5771 dev_kfree_skb_any(skb);
5772 return NETDEV_TX_OK;
5773 }
5774 if (tso)
5775 tx_flags |= IXGBE_TX_FLAGS_FSO;
5776#endif /* IXGBE_FCOE */
5777 } else {
5778 if (skb->protocol == htons(ETH_P_IP))
5779 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5780 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5781 if (tso < 0) {
5782 dev_kfree_skb_any(skb);
5783 return NETDEV_TX_OK;
5784 }
9a799d71 5785
eacd73f7
YZ		 5786 if (tso)
5787 tx_flags |= IXGBE_TX_FLAGS_TSO;
5788 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5789 (skb->ip_summed == CHECKSUM_PARTIAL))
5790 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5791 }
9a799d71 5792
eacd73f7 5793 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5794 if (count) {
c4cf55e5
PWJ		 5795 /* add the ATR filter if ATR is on */
5796 if (tx_ring->atr_sample_rate) {
5797 ++tx_ring->atr_count;
5798 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5799 test_bit(__IXGBE_FDIR_INIT_DONE,
5800 &tx_ring->reinit_state)) {
5801 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5802 tx_flags);
5803 tx_ring->atr_count = 0;
5804 }
5805 }
60d51134
ED		 5806 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5807 txq->tx_bytes += skb->len;
5808 txq->tx_packets++;
44df32c5
AD		 5809 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5810 hdr_len);
44df32c5 5811 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5812
44df32c5
AD		 5813 } else {
5814 dev_kfree_skb_any(skb);
5815 tx_ring->tx_buffer_info[first].time_stamp = 0;
5816 tx_ring->next_to_use = first;
5817 }
9a799d71
AK		 5818
5819 return NETDEV_TX_OK;
5820}
5821
9a799d71
AK		 5822/**
5823 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5824 * @netdev: network interface device structure
5825 * @p: pointer to an address structure
5826 *
5827 * Returns 0 on success, negative on failure
5828 **/
5829static int ixgbe_set_mac(struct net_device *netdev, void *p)
5830{
5831 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5832 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5833 struct sockaddr *addr = p;
5834
5835 if (!is_valid_ether_addr(addr->sa_data))
5836 return -EADDRNOTAVAIL;
5837
5838 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5839 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5840
1cdd1ec8
GR		 5841 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5842 IXGBE_RAH_AV);
9a799d71
AK		 5843
5844 return 0;
5845}
5846
6b73e10d
BH		 5847static int
5848ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5849{
5850 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5851 struct ixgbe_hw *hw = &adapter->hw;
5852 u16 value;
5853 int rc;
5854
5855 if (prtad != hw->phy.mdio.prtad)
5856 return -EINVAL;
5857 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5858 if (!rc)
5859 rc = value;
5860 return rc;
5861}
5862
5863static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5864 u16 addr, u16 value)
5865{
5866 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5867 struct ixgbe_hw *hw = &adapter->hw;
5868
5869 if (prtad != hw->phy.mdio.prtad)
5870 return -EINVAL;
5871 return hw->phy.ops.write_reg(hw, addr, devad, value);
5872}
5873
5874static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5875{
5876 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5877
5878 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5879}
5880
0365e6e4
PW		 5881/**
5882 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5883 * netdev->dev_addrs
0365e6e4
PW		 5884 * @netdev: network interface device structure
5885 *
5886 * Returns non-zero on failure
5887 **/
5888static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5889{
5890 int err = 0;
5891 struct ixgbe_adapter *adapter = netdev_priv(dev);
5892 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5893
5894 if (is_valid_ether_addr(mac->san_addr)) {
5895 rtnl_lock();
5896 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5897 rtnl_unlock();
5898 }
5899 return err;
5900}
5901
5902/**
5903 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5904 * netdev->dev_addrs
0365e6e4
PW		 5905 * @netdev: network interface device structure
5906 *
5907 * Returns non-zero on failure
5908 **/
5909static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5910{
5911 int err = 0;
5912 struct ixgbe_adapter *adapter = netdev_priv(dev);
5913 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5914
5915 if (is_valid_ether_addr(mac->san_addr)) {
5916 rtnl_lock();
5917 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5918 rtnl_unlock();
5919 }
5920 return err;
5921}
5922
9a799d71
AK		 5923#ifdef CONFIG_NET_POLL_CONTROLLER
5924/*
5925 * Polling 'interrupt' - used by things like netconsole to send skbs
5926 * without having to re-enable interrupts. It's not called while
5927 * the interrupt routine is executing.
5928 */
5929static void ixgbe_netpoll(struct net_device *netdev)
5930{
5931 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5932 int i;
9a799d71 5933
1a647bd2
AD		 5934 /* if interface is down do nothing */
5935 if (test_bit(__IXGBE_DOWN, &adapter->state))
5936 return;
5937
9a799d71 5938 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5939 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5940 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5941 for (i = 0; i < num_q_vectors; i++) {
5942 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5943 ixgbe_msix_clean_many(0, q_vector);
5944 }
5945 } else {
5946 ixgbe_intr(adapter->pdev->irq, netdev);
5947 }
9a799d71 5948 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5949}
5950#endif
5951
0edc3527
SH		 5952static const struct net_device_ops ixgbe_netdev_ops = {
5953 .ndo_open = ixgbe_open,
5954 .ndo_stop = ixgbe_close,
00829823 5955 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5956 .ndo_select_queue = ixgbe_select_queue,
e90d400c 5957 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5958 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5959 .ndo_validate_addr = eth_validate_addr,
5960 .ndo_set_mac_address = ixgbe_set_mac,
5961 .ndo_change_mtu = ixgbe_change_mtu,
5962 .ndo_tx_timeout = ixgbe_tx_timeout,
5963 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5964 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5965 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5966 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5967#ifdef CONFIG_NET_POLL_CONTROLLER
5968 .ndo_poll_controller = ixgbe_netpoll,
5969#endif
332d4a7d
YZ		 5970#ifdef IXGBE_FCOE
5971 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5972 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5973 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5974 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5975 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5976#endif /* IXGBE_FCOE */
0edc3527
SH		 5977};
5978
1cdd1ec8
GR		 5979static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5980 const struct ixgbe_info *ii)
5981{
5982#ifdef CONFIG_PCI_IOV
5983 struct ixgbe_hw *hw = &adapter->hw;
5984 int err;
5985
5986 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5987 return;
5988
5989 /* The 82599 supports up to 64 VFs per physical function
5990 * but this implementation limits allocation to 63 so that
5991 * basic networking resources are still available to the
5992 * physical function
5993 */
5994 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5995 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5996 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5997 if (err) {
5998 DPRINTK(PROBE, ERR,
5999 "Failed to enable PCI sriov: %d\n", err);
6000 goto err_novfs;
6001 }
6002 /* If call to enable VFs succeeded then allocate memory
6003 * for per VF control structures.
6004 */
6005 adapter->vfinfo =
6006 kcalloc(adapter->num_vfs,
6007 sizeof(struct vf_data_storage), GFP_KERNEL);
6008 if (adapter->vfinfo) {
6009 /* Now that we're sure SR-IOV is enabled
6010 * and memory allocated set up the mailbox parameters
6011 */
6012 ixgbe_init_mbx_params_pf(hw);
6013 memcpy(&hw->mbx.ops, ii->mbx_ops,
6014 sizeof(hw->mbx.ops));
6015
6016 /* Disable RSC when in SR-IOV mode */
6017 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6018 IXGBE_FLAG2_RSC_ENABLED);
6019 return;
6020 }
6021
6022 /* Oh oh */
6023 DPRINTK(PROBE, ERR,
6024 "Unable to allocate memory for VF "
6025 "Data Storage - SRIOV disabled\n");
6026 pci_disable_sriov(adapter->pdev);
6027
6028err_novfs:
6029 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6030 adapter->num_vfs = 0;
6031#endif /* CONFIG_PCI_IOV */
6032}
6033
9a799d71
AK		 6034/**
6035 * ixgbe_probe - Device Initialization Routine
6036 * @pdev: PCI device information struct
6037 * @ent: entry in ixgbe_pci_tbl
6038 *
6039 * Returns 0 on success, negative on failure
6040 *
6041 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6042 * The OS initialization, configuring of the adapter private structure,
6043 * and a hardware reset occur.
6044 **/
6045static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 6046 const struct pci_device_id *ent)
9a799d71
AK		 6047{
6048 struct net_device *netdev;
6049 struct ixgbe_adapter *adapter = NULL;
6050 struct ixgbe_hw *hw;
6051 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6052 static int cards_found;
6053 int i, err, pci_using_dac;
c85a2618 6054 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6055#ifdef IXGBE_FCOE
6056 u16 device_caps;
6057#endif
c44ade9e 6058 u32 part_num, eec;
9a799d71 6059
9ce77666 6060 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6061 if (err)
6062 return err;
6063
6a35528a
YH		 6064 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
6065 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6066 pci_using_dac = 1;
6067 } else {
284901a9 6068 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 6069 if (err) {
284901a9 6070 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 6071 if (err) {
b4617240
PW		 6072 dev_err(&pdev->dev, "No usable DMA "
6073 "configuration, aborting\n");
9a799d71
AK		 6074 goto err_dma;
6075 }
6076 }
6077 pci_using_dac = 0;
6078 }
6079
9ce77666 6080 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6081 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6082 if (err) {
9ce77666 6083 dev_err(&pdev->dev,
6084 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6085 goto err_pci_reg;
6086 }
6087
19d5afd4 6088 pci_enable_pcie_error_reporting(pdev);
6fabd715 6089
9a799d71 6090 pci_set_master(pdev);
fb3b27bc 6091 pci_save_state(pdev);
9a799d71 6092
c85a2618
JF		 6093 if (ii->mac == ixgbe_mac_82598EB)
6094 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6095 else
6096 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6097
6098 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6099#ifdef IXGBE_FCOE
6100 indices += min_t(unsigned int, num_possible_cpus(),
6101 IXGBE_MAX_FCOE_INDICES);
6102#endif
c85a2618 6103 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6104 if (!netdev) {
6105 err = -ENOMEM;
6106 goto err_alloc_etherdev;
6107 }
6108
9a799d71
AK		 6109 SET_NETDEV_DEV(netdev, &pdev->dev);
6110
6111 pci_set_drvdata(pdev, netdev);
6112 adapter = netdev_priv(netdev);
6113
6114 adapter->netdev = netdev;
6115 adapter->pdev = pdev;
6116 hw = &adapter->hw;
6117 hw->back = adapter;
6118 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6119
05857980
JK		 6120 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6121 pci_resource_len(pdev, 0));
9a799d71
AK		 6122 if (!hw->hw_addr) {
6123 err = -EIO;
6124 goto err_ioremap;
6125 }
6126
6127 for (i = 1; i <= 5; i++) {
6128 if (pci_resource_len(pdev, i) == 0)
6129 continue;
6130 }
6131
0edc3527 6132 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6133 ixgbe_set_ethtool_ops(netdev);
9a799d71 6134 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6135 strcpy(netdev->name, pci_name(pdev));
6136
9a799d71
AK		 6137 adapter->bd_number = cards_found;
6138
9a799d71
AK		 6139 /* Setup hw api */
6140 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6141 hw->mac.type = ii->mac;
9a799d71 6142
c44ade9e
JB		 6143 /* EEPROM */
6144 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6145 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6146 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6147 if (!(eec & (1 << 8)))
6148 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6149
6150 /* PHY */
6151 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6152 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6153 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6154 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6155 hw->phy.mdio.mmds = 0;
6156 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6157 hw->phy.mdio.dev = netdev;
6158 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6159 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6160
6161 /* set up this timer and work struct before calling get_invariants
6162 * which might start the timer
6163 */
6164 init_timer(&adapter->sfp_timer);
6165 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6166 adapter->sfp_timer.data = (unsigned long) adapter;
6167
6168 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6169
e8e26350
PW		 6170 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6171 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6172
6173 /* a new SFP+ module arrival, called from GPI SDP2 context */
6174 INIT_WORK(&adapter->sfp_config_module_task,
6175 ixgbe_sfp_config_module_task);
6176
8ca783ab 6177 ii->get_invariants(hw);
9a799d71
AK		 6178
6179 /* setup the private structure */
6180 err = ixgbe_sw_init(adapter);
6181 if (err)
6182 goto err_sw_init;
6183
e86bff0e
DS		 6184 /* Make it possible the adapter to be woken up via WOL */
6185 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6186 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6187
bf069c97
DS		 6188 /*
6189 * If there is a fan on this device and it has failed log the
6190 * failure.
6191 */
6192 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6193 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6194 if (esdp & IXGBE_ESDP_SDP1)
6195 DPRINTK(PROBE, CRIT,
6196 "Fan has stopped, replace the adapter\n");
6197 }
6198
c44ade9e
JB		 6199 /* reset_hw fills in the perm_addr as well */
6200 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 6201 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6202 hw->mac.type == ixgbe_mac_82598EB) {
6203 /*
6204 * Start a kernel thread to watch for a module to arrive.
6205 * Only do this for 82598, since 82599 will generate
6206 * interrupts on module arrival.
6207 */
6208 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6209 mod_timer(&adapter->sfp_timer,
6210 round_jiffies(jiffies + (2 * HZ)));
6211 err = 0;
6212 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 6213 dev_err(&adapter->pdev->dev, "failed to initialize because "
6214 "an unsupported SFP+ module type was detected.\n"
6215 "Reload the driver after installing a supported "
6216 "module.\n");
04f165ef
PW		 6217 goto err_sw_init;
6218 } else if (err) {
c44ade9e
JB		 6219 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6220 goto err_sw_init;
6221 }
6222
1cdd1ec8
GR		 6223 ixgbe_probe_vf(adapter, ii);
6224
9a799d71 6225 netdev->features = NETIF_F_SG |
b4617240
PW		 6226 NETIF_F_IP_CSUM |
6227 NETIF_F_HW_VLAN_TX |
6228 NETIF_F_HW_VLAN_RX |
6229 NETIF_F_HW_VLAN_FILTER;
9a799d71 6230
e9990a9c 6231 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6232 netdev->features |= NETIF_F_TSO;
9a799d71 6233 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6234 netdev->features |= NETIF_F_GRO;
ad31c402 6235
45a5ead0
JB		 6236 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6237 netdev->features |= NETIF_F_SCTP_CSUM;
6238
ad31c402
JK		 6239 netdev->vlan_features |= NETIF_F_TSO;
6240 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6241 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6242 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6243 netdev->vlan_features |= NETIF_F_SG;
6244
1cdd1ec8
GR		 6245 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6246 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6247 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6248 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6249 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6250
7a6b6f51 6251#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6252 netdev->dcbnl_ops = &dcbnl_ops;
6253#endif
6254
eacd73f7 6255#ifdef IXGBE_FCOE
0d551589 6256 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6257 if (hw->mac.ops.get_device_caps) {
6258 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6259 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6260 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6261 }
6262 }
6263#endif /* IXGBE_FCOE */
9a799d71
AK		 6264 if (pci_using_dac)
6265 netdev->features |= NETIF_F_HIGHDMA;
6266
0c19d6af 6267 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6268 netdev->features |= NETIF_F_LRO;
6269
9a799d71 6270 /* make sure the EEPROM is good */
c44ade9e 6271 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 6272 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6273 err = -EIO;
6274 goto err_eeprom;
6275 }
6276
6277 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6278 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6279
c44ade9e
JB		 6280 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6281 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 6282 err = -EIO;
6283 goto err_eeprom;
6284 }
6285
61fac744
PW		 6286 /* power down the optics */
6287 if (hw->phy.multispeed_fiber)
6288 hw->mac.ops.disable_tx_laser(hw);
6289
9a799d71
AK		 6290 init_timer(&adapter->watchdog_timer);
6291 adapter->watchdog_timer.function = &ixgbe_watchdog;
6292 adapter->watchdog_timer.data = (unsigned long)adapter;
6293
6294 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6295 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6296
021230d4
AV		 6297 err = ixgbe_init_interrupt_scheme(adapter);
6298 if (err)
6299 goto err_sw_init;
9a799d71 6300
e8e26350
PW		 6301 switch (pdev->device) {
6302 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6303 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6304 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6305 break;
6306 default:
6307 adapter->wol = 0;
6308 break;
6309 }
e8e26350
PW		 6310 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6311
04f165ef
PW		 6312 /* pick up the PCI bus settings for reporting later */
6313 hw->mac.ops.get_bus_info(hw);
6314
9a799d71 6315 /* print bus type/speed/width info */
7c510e4b 6316 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6317 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6318 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6319 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6320 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6321 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6322 "Unknown"),
7c510e4b 6323 netdev->dev_addr);
c44ade9e 6324 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 6325 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6326 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6327 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6328 (part_num >> 8), (part_num & 0xff));
6329 else
6330 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6331 hw->mac.type, hw->phy.type,
6332 (part_num >> 8), (part_num & 0xff));
9a799d71 6333
e8e26350 6334 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 6335 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 6336 "this card is not sufficient for optimal "
6337 "performance.\n");
0c254d86 6338 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 6339 "PCI-Express slot is required.\n");
0c254d86
AK		 6340 }
6341
34b0368c
PWJ		 6342 /* save off EEPROM version number */
6343 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6344
9a799d71 6345 /* reset the hardware with the new settings */
794caeb2 6346 err = hw->mac.ops.start_hw(hw);
c44ade9e 6347
794caeb2
PWJ		 6348 if (err == IXGBE_ERR_EEPROM_VERSION) {
6349 /* We are running on a pre-production device, log a warning */
6350 dev_warn(&pdev->dev, "This device is a pre-production "
6351 "adapter/LOM. Please be aware there may be issues "
6352 "associated with your hardware. If you are "
6353 "experiencing problems please contact your Intel or "
6354 "hardware representative who provided you with this "
6355 "hardware.\n");
6356 }
9a799d71
AK		 6357 strcpy(netdev->name, "eth%d");
6358 err = register_netdev(netdev);
6359 if (err)
6360 goto err_register;
6361
54386467
JB		 6362 /* carrier off reporting is important to ethtool even BEFORE open */
6363 netif_carrier_off(netdev);
6364
c4cf55e5
PWJ		 6365 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6366 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6367 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6368
5dd2d332 6369#ifdef CONFIG_IXGBE_DCA
652f093f 6370 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6371 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6372 ixgbe_setup_dca(adapter);
6373 }
6374#endif
1cdd1ec8
GR		 6375 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6376 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6377 adapter->num_vfs);
6378 for (i = 0; i < adapter->num_vfs; i++)
6379 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6380 }
6381
0365e6e4
PW		 6382 /* add san mac addr to netdev */
6383 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 6384
6385 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6386 cards_found++;
6387 return 0;
6388
6389err_register:
5eba3699 6390 ixgbe_release_hw_control(adapter);
7a921c93 6391 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6392err_sw_init:
6393err_eeprom:
1cdd1ec8
GR		 6394 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6395 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6396 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6397 del_timer_sync(&adapter->sfp_timer);
6398 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6399 cancel_work_sync(&adapter->multispeed_fiber_task);
6400 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6401 iounmap(hw->hw_addr);
6402err_ioremap:
6403 free_netdev(netdev);
6404err_alloc_etherdev:
9ce77666 6405 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6406 IORESOURCE_MEM));
9a799d71
AK		 6407err_pci_reg:
6408err_dma:
6409 pci_disable_device(pdev);
6410 return err;
6411}
6412
6413/**
6414 * ixgbe_remove - Device Removal Routine
6415 * @pdev: PCI device information struct
6416 *
6417 * ixgbe_remove is called by the PCI subsystem to alert the driver
6418 * that it should release a PCI device. The could be caused by a
6419 * Hot-Plug event, or because the driver is going to be removed from
6420 * memory.
6421 **/
6422static void __devexit ixgbe_remove(struct pci_dev *pdev)
6423{
6424 struct net_device *netdev = pci_get_drvdata(pdev);
6425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6426
6427 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6428 /* clear the module not found bit to make sure the worker won't
6429 * reschedule
6430 */
6431 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6432 del_timer_sync(&adapter->watchdog_timer);
6433
c4900be0
DS		 6434 del_timer_sync(&adapter->sfp_timer);
6435 cancel_work_sync(&adapter->watchdog_task);
6436 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6437 cancel_work_sync(&adapter->multispeed_fiber_task);
6438 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6439 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6440 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6441 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6442 flush_scheduled_work();
6443
5dd2d332 6444#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6445 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6446 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6447 dca_remove_requester(&pdev->dev);
6448 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6449 }
6450
6451#endif
332d4a7d
YZ		 6452#ifdef IXGBE_FCOE
6453 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6454 ixgbe_cleanup_fcoe(adapter);
6455
6456#endif /* IXGBE_FCOE */
0365e6e4
PW		 6457
6458 /* remove the added san mac */
6459 ixgbe_del_sanmac_netdev(netdev);
6460
c4900be0
DS		 6461 if (netdev->reg_state == NETREG_REGISTERED)
6462 unregister_netdev(netdev);
9a799d71 6463
1cdd1ec8
GR		 6464 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6465 ixgbe_disable_sriov(adapter);
6466
7a921c93 6467 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6468
021230d4 6469 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6470
6471 iounmap(adapter->hw.hw_addr);
9ce77666 6472 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6473 IORESOURCE_MEM));
9a799d71 6474
021230d4 6475 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6476
9a799d71
AK		 6477 free_netdev(netdev);
6478
19d5afd4 6479 pci_disable_pcie_error_reporting(pdev);
6fabd715 6480
9a799d71
AK		 6481 pci_disable_device(pdev);
6482}
6483
6484/**
6485 * ixgbe_io_error_detected - called when PCI error is detected
6486 * @pdev: Pointer to PCI device
6487 * @state: The current pci connection state
6488 *
6489 * This function is called after a PCI bus error affecting
6490 * this device has been detected.
6491 */
6492static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6493 pci_channel_state_t state)
9a799d71
AK		 6494{
6495 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6496 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6497
6498 netif_device_detach(netdev);
6499
3044b8d1
BL		 6500 if (state == pci_channel_io_perm_failure)
6501 return PCI_ERS_RESULT_DISCONNECT;
6502
9a799d71
AK		 6503 if (netif_running(netdev))
6504 ixgbe_down(adapter);
6505 pci_disable_device(pdev);
6506
b4617240 6507 /* Request a slot reset. */
9a799d71
AK		 6508 return PCI_ERS_RESULT_NEED_RESET;
6509}
6510
6511/**
6512 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6513 * @pdev: Pointer to PCI device
6514 *
6515 * Restart the card from scratch, as if from a cold-boot.
6516 */
6517static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6518{
6519 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6520 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6521 pci_ers_result_t result;
6522 int err;
9a799d71 6523
9ce77666 6524 if (pci_enable_device_mem(pdev)) {
9a799d71 6525 DPRINTK(PROBE, ERR,
b4617240 6526 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6527 result = PCI_ERS_RESULT_DISCONNECT;
6528 } else {
6529 pci_set_master(pdev);
6530 pci_restore_state(pdev);
c0e1f68b 6531 pci_save_state(pdev);
9a799d71 6532
dd4d8ca6 6533 pci_wake_from_d3(pdev, false);
9a799d71 6534
6fabd715 6535 ixgbe_reset(adapter);
88512539 6536 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6537 result = PCI_ERS_RESULT_RECOVERED;
6538 }
6539
6540 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6541 if (err) {
6542 dev_err(&pdev->dev,
6543 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6544 /* non-fatal, continue */
6545 }
9a799d71 6546
6fabd715 6547 return result;
9a799d71
AK		 6548}
6549
6550/**
6551 * ixgbe_io_resume - called when traffic can start flowing again.
6552 * @pdev: Pointer to PCI device
6553 *
6554 * This callback is called when the error recovery driver tells us that
6555 * its OK to resume normal operation.
6556 */
6557static void ixgbe_io_resume(struct pci_dev *pdev)
6558{
6559 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6560 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6561
6562 if (netif_running(netdev)) {
6563 if (ixgbe_up(adapter)) {
6564 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6565 return;
6566 }
6567 }
6568
6569 netif_device_attach(netdev);
9a799d71
AK		 6570}
6571
6572static struct pci_error_handlers ixgbe_err_handler = {
6573 .error_detected = ixgbe_io_error_detected,
6574 .slot_reset = ixgbe_io_slot_reset,
6575 .resume = ixgbe_io_resume,
6576};
6577
6578static struct pci_driver ixgbe_driver = {
6579 .name = ixgbe_driver_name,
6580 .id_table = ixgbe_pci_tbl,
6581 .probe = ixgbe_probe,
6582 .remove = __devexit_p(ixgbe_remove),
6583#ifdef CONFIG_PM
6584 .suspend = ixgbe_suspend,
6585 .resume = ixgbe_resume,
6586#endif
6587 .shutdown = ixgbe_shutdown,
6588 .err_handler = &ixgbe_err_handler
6589};
6590
6591/**
6592 * ixgbe_init_module - Driver Registration Routine
6593 *
6594 * ixgbe_init_module is the first routine called when the driver is
6595 * loaded. All it does is register with the PCI subsystem.
6596 **/
6597static int __init ixgbe_init_module(void)
6598{
6599 int ret;
6600 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6601 ixgbe_driver_string, ixgbe_driver_version);
6602
6603 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6604
5dd2d332 6605#ifdef CONFIG_IXGBE_DCA
bd0362dd 6606 dca_register_notify(&dca_notifier);
bd0362dd 6607#endif
5dd2d332 6608
9a799d71
AK		 6609 ret = pci_register_driver(&ixgbe_driver);
6610 return ret;
6611}
b4617240 6612
9a799d71
AK		 6613module_init(ixgbe_init_module);
6614
6615/**
6616 * ixgbe_exit_module - Driver Exit Cleanup Routine
6617 *
6618 * ixgbe_exit_module is called just before the driver is removed
6619 * from memory.
6620 **/
6621static void __exit ixgbe_exit_module(void)
6622{
5dd2d332 6623#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6624 dca_unregister_notify(&dca_notifier);
6625#endif
9a799d71
AK		 6626 pci_unregister_driver(&ixgbe_driver);
6627}
bd0362dd 6628
5dd2d332 6629#ifdef CONFIG_IXGBE_DCA
bd0362dd 6630static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6631 void *p)
bd0362dd
JC		 6632{
6633 int ret_val;
6634
6635 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6636 __ixgbe_notify_dca);
bd0362dd
JC		 6637
6638 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6639}
b453368d 6640
5dd2d332 6641#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6642#ifdef DEBUG
6643/**
6644 * ixgbe_get_hw_dev_name - return device name string
6645 * used by hardware layer to print debugging information
6646 **/
6647char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6648{
6649 struct ixgbe_adapter *adapter = hw->back;
6650 return adapter->netdev->name;
6651}
bd0362dd 6652
b453368d 6653#endif
9a799d71
AK		 6654module_exit(ixgbe_exit_module);
6655
6656/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree