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ixgbe: only process one ixgbe_watchdog_task at a time.
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
ee5f784a 47#include "ixgbe_dcb_82599.h"
1cdd1ec8 48#include "ixgbe_sriov.h"
9a799d71
AK		 49
50char ixgbe_driver_name[] = "ixgbe";
9c8eb720 51static const char ixgbe_driver_string[] =
b4617240 52 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 53
e0f4daff 54#define DRV_VERSION "2.0.44-k2"
9c8eb720 55const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 56static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 57
58static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 59 [board_82598] = &ixgbe_82598_info,
e8e26350 60 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 61};
62
63/* ixgbe_pci_tbl - PCI Device ID Table
64 *
65 * Wildcard entries (PCI_ANY_ID) should come last
66 * Last entry must be all 0s
67 *
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
70 */
a3aa1884 71static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
73 board_82598 },
9a799d71 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 77 board_82598 },
0befdb3e
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
79 board_82598 },
3845bec0
PWJ		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
81 board_82598 },
9a799d71 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 83 board_82598 },
8d792cd9
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
87 board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
89 board_82598 },
b95f5fcb
JB		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
91 board_82598 },
c4900be0
DS		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
93 board_82598 },
2f21bdd3
DS		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
95 board_82598 },
e8e26350
PW		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
97 board_82599 },
1fcf03e6
PWJ		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
99 board_82599 },
74757d49
DS		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
101 board_82599 },
e8e26350
PW		 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
103 board_82599 },
38ad1c8e
DS		 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
105 board_82599 },
dbfec662
DS		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
107 board_82599 },
8911184f
PWJ		 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
109 board_82599 },
312eb931
DS		 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
111 board_82599 },
9a799d71
AK		 112
113 /* required last entry */
114 {0, }
115};
116MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
117
5dd2d332 118#ifdef CONFIG_IXGBE_DCA
bd0362dd 119static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 120 void *p);
bd0362dd
JC		 121static struct notifier_block dca_notifier = {
122 .notifier_call = ixgbe_notify_dca,
123 .next = NULL,
124 .priority = 0
125};
126#endif
127
1cdd1ec8
GR		 128#ifdef CONFIG_PCI_IOV
129static unsigned int max_vfs;
130module_param(max_vfs, uint, 0);
131MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
132 "per physical function");
133#endif /* CONFIG_PCI_IOV */
134
9a799d71
AK		 135MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137MODULE_LICENSE("GPL");
138MODULE_VERSION(DRV_VERSION);
139
140#define DEFAULT_DEBUG_LEVEL_SHIFT 3
141
1cdd1ec8
GR		 142static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
143{
144 struct ixgbe_hw *hw = &adapter->hw;
145 u32 gcr;
146 u32 gpie;
147 u32 vmdctl;
148
149#ifdef CONFIG_PCI_IOV
150 /* disable iov and allow time for transactions to clear */
151 pci_disable_sriov(adapter->pdev);
152#endif
153
154 /* turn off device IOV mode */
155 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
156 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
157 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
158 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
159 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
160 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
161
162 /* set default pool back to 0 */
163 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
164 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
165 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
166
167 /* take a breather then clean up driver data */
168 msleep(100);
169 if (adapter->vfinfo)
170 kfree(adapter->vfinfo);
171 adapter->vfinfo = NULL;
172
173 adapter->num_vfs = 0;
174 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
175}
176
5eba3699
AV		 177static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
178{
179 u32 ctrl_ext;
180
181 /* Let firmware take over control of h/w */
182 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 184 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 185}
186
187static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
188{
189 u32 ctrl_ext;
190
191 /* Let firmware know the driver has taken over */
192 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 194 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 195}
9a799d71 196
e8e26350
PW		 197/*
198 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199 * @adapter: pointer to adapter struct
200 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201 * @queue: queue to map the corresponding interrupt to
202 * @msix_vector: the vector to map to the corresponding queue
203 *
204 */
205static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
206 u8 queue, u8 msix_vector)
9a799d71
AK		 207{
208 u32 ivar, index;
e8e26350
PW		 209 struct ixgbe_hw *hw = &adapter->hw;
210 switch (hw->mac.type) {
211 case ixgbe_mac_82598EB:
212 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
213 if (direction == -1)
214 direction = 0;
215 index = (((direction * 64) + queue) >> 2) & 0x1F;
216 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
217 ivar &= ~(0xFF << (8 * (queue & 0x3)));
218 ivar |= (msix_vector << (8 * (queue & 0x3)));
219 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
220 break;
221 case ixgbe_mac_82599EB:
222 if (direction == -1) {
223 /* other causes */
224 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
225 index = ((queue & 1) * 8);
226 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
227 ivar &= ~(0xFF << index);
228 ivar |= (msix_vector << index);
229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
230 break;
231 } else {
232 /* tx or rx causes */
233 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
234 index = ((16 * (queue & 1)) + (8 * direction));
235 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
236 ivar &= ~(0xFF << index);
237 ivar |= (msix_vector << index);
238 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
239 break;
240 }
241 default:
242 break;
243 }
9a799d71
AK		 244}
245
fe49f04a
AD		 246static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
247 u64 qmask)
248{
249 u32 mask;
250
251 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
252 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
254 } else {
255 mask = (qmask & 0xFFFFFFFF);
256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
257 mask = (qmask >> 32);
258 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
259 }
260}
261
9a799d71 262static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 263 struct ixgbe_tx_buffer
264 *tx_buffer_info)
9a799d71 265{
e5a43549
AD		 266 if (tx_buffer_info->dma) {
267 if (tx_buffer_info->mapped_as_page)
268 pci_unmap_page(adapter->pdev,
269 tx_buffer_info->dma,
270 tx_buffer_info->length,
271 PCI_DMA_TODEVICE);
272 else
273 pci_unmap_single(adapter->pdev,
274 tx_buffer_info->dma,
275 tx_buffer_info->length,
276 PCI_DMA_TODEVICE);
277 tx_buffer_info->dma = 0;
278 }
9a799d71
AK		 279 if (tx_buffer_info->skb) {
280 dev_kfree_skb_any(tx_buffer_info->skb);
281 tx_buffer_info->skb = NULL;
282 }
44df32c5 283 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 284 /* tx_buffer_info must be completely set up in the transmit path */
285}
286
26f23d82
YZ		 287/**
288 * ixgbe_tx_is_paused - check if the tx ring is paused
289 * @adapter: the ixgbe adapter
290 * @tx_ring: the corresponding tx_ring
291 *
292 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293 * corresponding TC of this tx_ring when checking TFCS.
294 *
295 * Returns : true if paused
296 */
297static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
298 struct ixgbe_ring *tx_ring)
299{
26f23d82
YZ		 300 u32 txoff = IXGBE_TFCS_TXOFF;
301
302#ifdef CONFIG_IXGBE_DCB
303 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
30b76832 304 int tc;
26f23d82
YZ		 305 int reg_idx = tx_ring->reg_idx;
306 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
307
6837e895
PW		 308 switch (adapter->hw.mac.type) {
309 case ixgbe_mac_82598EB:
26f23d82
YZ		 310 tc = reg_idx >> 2;
311 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 312 break;
313 case ixgbe_mac_82599EB:
26f23d82
YZ		 314 tc = 0;
315 txoff = IXGBE_TFCS_TXOFF;
316 if (dcb_i == 8) {
317 /* TC0, TC1 */
318 tc = reg_idx >> 5;
319 if (tc == 2) /* TC2, TC3 */
320 tc += (reg_idx - 64) >> 4;
321 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
322 tc += 1 + ((reg_idx - 96) >> 3);
323 } else if (dcb_i == 4) {
324 /* TC0, TC1 */
325 tc = reg_idx >> 6;
326 if (tc == 1) {
327 tc += (reg_idx - 64) >> 5;
328 if (tc == 2) /* TC2, TC3 */
329 tc += (reg_idx - 96) >> 4;
330 }
331 }
6837e895
PW		 332 break;
333 default:
334 tc = 0;
26f23d82
YZ		 335 }
336 txoff <<= tc;
337 }
338#endif
339 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
340}
341
9a799d71 342static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 343 struct ixgbe_ring *tx_ring,
344 unsigned int eop)
9a799d71 345{
e01c31a5 346 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 347
9a799d71 348 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 349 * check with the clearing of time_stamp and movement of eop */
9a799d71 350 adapter->detect_tx_hung = false;
44df32c5 351 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 352 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
26f23d82 353 !ixgbe_tx_is_paused(adapter, tx_ring)) {
9a799d71 354 /* detected Tx unit hang */
e01c31a5
JB		 355 union ixgbe_adv_tx_desc *tx_desc;
356 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 357 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 358 " Tx Queue <%d>\n"
359 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 360 " next_to_use <%x>\n"
361 " next_to_clean <%x>\n"
362 "tx_buffer_info[next_to_clean]\n"
363 " time_stamp <%lx>\n"
e01c31a5
JB		 364 " jiffies <%lx>\n",
365 tx_ring->queue_index,
44df32c5
AD		 366 IXGBE_READ_REG(hw, tx_ring->head),
367 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 368 tx_ring->next_to_use, eop,
369 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 370 return true;
371 }
372
373 return false;
374}
375
b4617240
PW		 376#define IXGBE_MAX_TXD_PWR 14
377#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 378
379/* Tx Descriptors needed, worst case */
380#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
381 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
382#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 383 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 384
e01c31a5
JB		 385static void ixgbe_tx_timeout(struct net_device *netdev);
386
9a799d71
AK		 387/**
388 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 389 * @q_vector: structure containing interrupt and ring information
e01c31a5 390 * @tx_ring: tx ring to clean
9a799d71 391 **/
fe49f04a 392static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 393 struct ixgbe_ring *tx_ring)
9a799d71 394{
fe49f04a 395 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 396 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 397 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
398 struct ixgbe_tx_buffer *tx_buffer_info;
399 unsigned int i, eop, count = 0;
e01c31a5 400 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 401
402 i = tx_ring->next_to_clean;
12207e49
PWJ		 403 eop = tx_ring->tx_buffer_info[i].next_to_watch;
404 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
405
406 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 407 (count < tx_ring->work_limit)) {
12207e49
PWJ		 408 bool cleaned = false;
409 for ( ; !cleaned; count++) {
410 struct sk_buff *skb;
9a799d71
AK		 411 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
412 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 413 cleaned = (i == eop);
e01c31a5 414 skb = tx_buffer_info->skb;
9a799d71 415
12207e49 416 if (cleaned && skb) {
e092be60 417 unsigned int segs, bytecount;
3d8fd385 418 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 419
420 /* gso_segs is currently only valid for tcp */
e092be60 421 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 422#ifdef IXGBE_FCOE
423 /* adjust for FCoE Sequence Offload */
424 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
425 && (skb->protocol == htons(ETH_P_FCOE)) &&
426 skb_is_gso(skb)) {
427 hlen = skb_transport_offset(skb) +
428 sizeof(struct fc_frame_header) +
429 sizeof(struct fcoe_crc_eof);
430 segs = DIV_ROUND_UP(skb->len - hlen,
431 skb_shinfo(skb)->gso_size);
432 }
433#endif /* IXGBE_FCOE */
e092be60 434 /* multiply data chunks by size of headers */
3d8fd385 435 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 436 total_packets += segs;
437 total_bytes += bytecount;
e092be60 438 }
e01c31a5 439
9a799d71 440 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 441 tx_buffer_info);
9a799d71 442
12207e49
PWJ		 443 tx_desc->wb.status = 0;
444
9a799d71
AK		 445 i++;
446 if (i == tx_ring->count)
447 i = 0;
e01c31a5 448 }
12207e49
PWJ		 449
450 eop = tx_ring->tx_buffer_info[i].next_to_watch;
451 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
452 }
453
9a799d71
AK		 454 tx_ring->next_to_clean = i;
455
e092be60 456#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 457 if (unlikely(count && netif_carrier_ok(netdev) &&
458 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 459 /* Make sure that anybody stopping the queue after this
460 * sees the new next_to_clean.
461 */
462 smp_mb();
30eba97a
AV		 463 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
464 !test_bit(__IXGBE_DOWN, &adapter->state)) {
465 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 466 ++tx_ring->restart_queue;
30eba97a 467 }
e092be60 468 }
9a799d71 469
e01c31a5
JB		 470 if (adapter->detect_tx_hung) {
471 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
472 /* schedule immediate reset if we believe we hung */
473 DPRINTK(PROBE, INFO,
474 "tx hang %d detected, resetting adapter\n",
475 adapter->tx_timeout_count + 1);
476 ixgbe_tx_timeout(adapter->netdev);
477 }
478 }
9a799d71 479
e01c31a5 480 /* re-arm the interrupt */
fe49f04a
AD		 481 if (count >= tx_ring->work_limit)
482 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 483
e01c31a5
JB		 484 tx_ring->total_bytes += total_bytes;
485 tx_ring->total_packets += total_packets;
e01c31a5 486 tx_ring->stats.packets += total_packets;
12207e49 487 tx_ring->stats.bytes += total_bytes;
9a1a69ad 488 return (count < tx_ring->work_limit);
9a799d71
AK		 489}
490
5dd2d332 491#ifdef CONFIG_IXGBE_DCA
bd0362dd 492static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 493 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 494{
495 u32 rxctrl;
496 int cpu = get_cpu();
3a581073 497 int q = rx_ring - adapter->rx_ring;
bd0362dd 498
3a581073 499 if (rx_ring->cpu != cpu) {
bd0362dd 500 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 501 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
502 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
503 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
504 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
505 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
506 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
507 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
508 }
bd0362dd
JC		 509 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
510 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 511 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
512 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 513 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 515 rx_ring->cpu = cpu;
bd0362dd
JC		 516 }
517 put_cpu();
518}
519
520static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 521 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 522{
523 u32 txctrl;
524 int cpu = get_cpu();
3a581073 525 int q = tx_ring - adapter->tx_ring;
ee5f784a 526 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 527
3a581073 528 if (tx_ring->cpu != cpu) {
e8e26350 529 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 530 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 531 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
532 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 533 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
534 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 535 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 536 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 537 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
538 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
ee5f784a
DS		 539 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
540 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
541 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 542 }
3a581073 543 tx_ring->cpu = cpu;
bd0362dd
JC		 544 }
545 put_cpu();
546}
547
548static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
549{
550 int i;
551
552 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
553 return;
554
e35ec126
AD		 555 /* always use CB2 mode, difference is masked in the CB driver */
556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
557
bd0362dd
JC		 558 for (i = 0; i < adapter->num_tx_queues; i++) {
559 adapter->tx_ring[i].cpu = -1;
560 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
561 }
562 for (i = 0; i < adapter->num_rx_queues; i++) {
563 adapter->rx_ring[i].cpu = -1;
564 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
565 }
566}
567
568static int __ixgbe_notify_dca(struct device *dev, void *data)
569{
570 struct net_device *netdev = dev_get_drvdata(dev);
571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
572 unsigned long event = *(unsigned long *)data;
573
574 switch (event) {
575 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 576 /* if we're already enabled, don't do it again */
577 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
578 break;
652f093f 579 if (dca_add_requester(dev) == 0) {
96b0e0f6 580 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 581 ixgbe_setup_dca(adapter);
582 break;
583 }
584 /* Fall Through since DCA is disabled. */
585 case DCA_PROVIDER_REMOVE:
586 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
587 dca_remove_requester(dev);
588 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
590 }
591 break;
592 }
593
652f093f 594 return 0;
bd0362dd
JC		 595}
596
5dd2d332 597#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 598/**
599 * ixgbe_receive_skb - Send a completed packet up the stack
600 * @adapter: board private structure
601 * @skb: packet to send up
177db6ff
MC		 602 * @status: hardware indication of status of receive
603 * @rx_ring: rx descriptor ring (for a specific queue) to setup
604 * @rx_desc: rx descriptor
9a799d71 605 **/
78b6f4ce 606static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 607 struct sk_buff *skb, u8 status,
fdaff1ce 608 struct ixgbe_ring *ring,
177db6ff 609 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 610{
78b6f4ce
HX		 611 struct ixgbe_adapter *adapter = q_vector->adapter;
612 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 613 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
614 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 615
fdaff1ce 616 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 617 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 618 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 619 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 620 else
78b6f4ce 621 napi_gro_receive(napi, skb);
177db6ff 622 } else {
8a62babf 623 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 624 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
625 else
626 netif_rx(skb);
9a799d71
AK		 627 }
628}
629
e59bd25d
AV		 630/**
631 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
632 * @adapter: address of board private structure
633 * @status_err: hardware indication of status of receive
634 * @skb: skb currently being received and modified
635 **/
9a799d71 636static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 637 union ixgbe_adv_rx_desc *rx_desc,
638 struct sk_buff *skb)
9a799d71 639{
8bae1b2b
DS		 640 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
641
9a799d71
AK		 642 skb->ip_summed = CHECKSUM_NONE;
643
712744be
JB		 644 /* Rx csum disabled */
645 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 646 return;
e59bd25d
AV		 647
648 /* if IP and error */
649 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
650 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 651 adapter->hw_csum_rx_error++;
652 return;
653 }
e59bd25d
AV		 654
655 if (!(status_err & IXGBE_RXD_STAT_L4CS))
656 return;
657
658 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 659 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
660
661 /*
662 * 82599 errata, UDP frames with a 0 checksum can be marked as
663 * checksum errors.
664 */
665 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
666 (adapter->hw.mac.type == ixgbe_mac_82599EB))
667 return;
668
e59bd25d
AV		 669 adapter->hw_csum_rx_error++;
670 return;
671 }
672
9a799d71 673 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 674 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 675}
676
e8e26350
PW		 677static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
678 struct ixgbe_ring *rx_ring, u32 val)
679{
680 /*
681 * Force memory writes to complete before letting h/w
682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
684 * such as IA-64).
685 */
686 wmb();
687 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
688}
689
9a799d71
AK		 690/**
691 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
692 * @adapter: address of board private structure
693 **/
694static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 695 struct ixgbe_ring *rx_ring,
696 int cleaned_count)
9a799d71 697{
9a799d71
AK		 698 struct pci_dev *pdev = adapter->pdev;
699 union ixgbe_adv_rx_desc *rx_desc;
3a581073 700 struct ixgbe_rx_buffer *bi;
9a799d71 701 unsigned int i;
9a799d71
AK		 702
703 i = rx_ring->next_to_use;
3a581073 704 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 705
706 while (cleaned_count--) {
707 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
708
762f4c57 709 if (!bi->page_dma &&
6e455b89 710 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 711 if (!bi->page) {
762f4c57
JB		 712 bi->page = alloc_page(GFP_ATOMIC);
713 if (!bi->page) {
714 adapter->alloc_rx_page_failed++;
715 goto no_buffers;
716 }
717 bi->page_offset = 0;
718 } else {
719 /* use a half page if we're re-using */
720 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 721 }
762f4c57
JB		 722
723 bi->page_dma = pci_map_page(pdev, bi->page,
724 bi->page_offset,
725 (PAGE_SIZE / 2),
726 PCI_DMA_FROMDEVICE);
9a799d71
AK		 727 }
728
3a581073 729 if (!bi->skb) {
5ecc3614 730 struct sk_buff *skb;
7ca3bc58
JB		 731 /* netdev_alloc_skb reserves 32 bytes up front!! */
732 uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
733 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 734
735 if (!skb) {
736 adapter->alloc_rx_buff_failed++;
737 goto no_buffers;
738 }
739
7ca3bc58
JB		 740 /* advance the data pointer to the next cache line */
741 skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
742 - skb->data));
743
3a581073 744 bi->skb = skb;
4f57ca6e
JB		 745 bi->dma = pci_map_single(pdev, skb->data,
746 rx_ring->rx_buf_len,
3a581073 747 PCI_DMA_FROMDEVICE);
9a799d71
AK		 748 }
749 /* Refresh the desc even if buffer_addrs didn't change because
750 * each write-back erases this info. */
6e455b89 751 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 752 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
753 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 754 } else {
3a581073 755 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 756 }
757
758 i++;
759 if (i == rx_ring->count)
760 i = 0;
3a581073 761 bi = &rx_ring->rx_buffer_info[i];
9a799d71 762 }
7c6e0a43 763
9a799d71
AK		 764no_buffers:
765 if (rx_ring->next_to_use != i) {
766 rx_ring->next_to_use = i;
767 if (i-- == 0)
768 i = (rx_ring->count - 1);
769
e8e26350 770 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 771 }
772}
773
7c6e0a43
JB		 774static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
775{
776 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
777}
778
779static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
780{
781 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
782}
783
f8212f97
AD		 784static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
785{
786 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
787 IXGBE_RXDADV_RSCCNT_MASK) >>
788 IXGBE_RXDADV_RSCCNT_SHIFT;
789}
790
791/**
792 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
793 * @skb: pointer to the last skb in the rsc queue
94b982b2 794 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 795 *
796 * This function changes a queue full of hw rsc buffers into a completed
797 * packet. It uses the ->prev pointers to find the first packet and then
798 * turns it into the frag list owner.
799 **/
94b982b2
MC		 800static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
801 u64 *count)
f8212f97
AD		 802{
803 unsigned int frag_list_size = 0;
804
805 while (skb->prev) {
806 struct sk_buff *prev = skb->prev;
807 frag_list_size += skb->len;
808 skb->prev = NULL;
809 skb = prev;
94b982b2 810 *count += 1;
f8212f97
AD		 811 }
812
813 skb_shinfo(skb)->frag_list = skb->next;
814 skb->next = NULL;
815 skb->len += frag_list_size;
816 skb->data_len += frag_list_size;
817 skb->truesize += frag_list_size;
818 return skb;
819}
820
78b6f4ce 821static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 822 struct ixgbe_ring *rx_ring,
823 int *work_done, int work_to_do)
9a799d71 824{
78b6f4ce 825 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 826 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 827 struct pci_dev *pdev = adapter->pdev;
828 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
829 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
830 struct sk_buff *skb;
f8212f97 831 unsigned int i, rsc_count = 0;
7c6e0a43 832 u32 len, staterr;
177db6ff
MC		 833 u16 hdr_info;
834 bool cleaned = false;
9a799d71 835 int cleaned_count = 0;
d2f4fbe2 836 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 837#ifdef IXGBE_FCOE
838 int ddp_bytes = 0;
839#endif /* IXGBE_FCOE */
9a799d71
AK		 840
841 i = rx_ring->next_to_clean;
9a799d71
AK		 842 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
843 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
844 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 845
846 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 847 u32 upper_len = 0;
9a799d71
AK		 848 if (*work_done >= work_to_do)
849 break;
850 (*work_done)++;
851
6e455b89 852 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 853 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
854 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 855 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 856 if (len > IXGBE_RX_HDR_SIZE)
857 len = IXGBE_RX_HDR_SIZE;
858 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 859 } else {
9a799d71 860 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 861 }
9a799d71
AK		 862
863 cleaned = true;
864 skb = rx_buffer_info->skb;
7ca3bc58 865 prefetch(skb->data);
9a799d71
AK		 866 rx_buffer_info->skb = NULL;
867
21fa4e66 868 if (rx_buffer_info->dma) {
9a799d71 869 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 870 rx_ring->rx_buf_len,
b4617240 871 PCI_DMA_FROMDEVICE);
4f57ca6e 872 rx_buffer_info->dma = 0;
9a799d71
AK		 873 skb_put(skb, len);
874 }
875
876 if (upper_len) {
877 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 878 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 879 rx_buffer_info->page_dma = 0;
880 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 881 rx_buffer_info->page,
882 rx_buffer_info->page_offset,
883 upper_len);
884
885 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
886 (page_count(rx_buffer_info->page) != 1))
887 rx_buffer_info->page = NULL;
888 else
889 get_page(rx_buffer_info->page);
9a799d71
AK		 890
891 skb->len += upper_len;
892 skb->data_len += upper_len;
893 skb->truesize += upper_len;
894 }
895
896 i++;
897 if (i == rx_ring->count)
898 i = 0;
9a799d71
AK		 899
900 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
901 prefetch(next_rxd);
9a799d71 902 cleaned_count++;
f8212f97 903
0c19d6af 904 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 905 rsc_count = ixgbe_get_rsc_count(rx_desc);
906
907 if (rsc_count) {
908 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
909 IXGBE_RXDADV_NEXTP_SHIFT;
910 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 911 } else {
912 next_buffer = &rx_ring->rx_buffer_info[i];
913 }
914
9a799d71 915 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 916 if (skb->prev)
94b982b2
MC		 917 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
918 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
919 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
920 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
921 else
922 rx_ring->rsc_count++;
923 rx_ring->rsc_flush++;
924 }
9a799d71
AK		 925 rx_ring->stats.packets++;
926 rx_ring->stats.bytes += skb->len;
927 } else {
6e455b89 928 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 929 rx_buffer_info->skb = next_buffer->skb;
930 rx_buffer_info->dma = next_buffer->dma;
931 next_buffer->skb = skb;
932 next_buffer->dma = 0;
933 } else {
934 skb->next = next_buffer->skb;
935 skb->next->prev = skb;
936 }
7ca3bc58 937 rx_ring->non_eop_descs++;
9a799d71
AK		 938 goto next_desc;
939 }
940
941 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
942 dev_kfree_skb_irq(skb);
943 goto next_desc;
944 }
945
8bae1b2b 946 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 947
948 /* probably a little skewed due to removing CRC */
949 total_rx_bytes += skb->len;
950 total_rx_packets++;
951
74ce8dd2 952 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 953#ifdef IXGBE_FCOE
954 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 955 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
956 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
957 if (!ddp_bytes)
332d4a7d 958 goto next_desc;
3d8fd385 959 }
332d4a7d 960#endif /* IXGBE_FCOE */
fdaff1ce 961 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 962
963next_desc:
964 rx_desc->wb.upper.status_error = 0;
965
966 /* return some buffers to hardware, one at a time is too slow */
967 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
968 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
969 cleaned_count = 0;
970 }
971
972 /* use prefetched values */
973 rx_desc = next_rxd;
f8212f97 974 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 975
976 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 977 }
978
9a799d71
AK		 979 rx_ring->next_to_clean = i;
980 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
981
982 if (cleaned_count)
983 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
984
3d8fd385
YZ		 985#ifdef IXGBE_FCOE
986 /* include DDPed FCoE data */
987 if (ddp_bytes > 0) {
988 unsigned int mss;
989
990 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
991 sizeof(struct fc_frame_header) -
992 sizeof(struct fcoe_crc_eof);
993 if (mss > 512)
994 mss &= ~511;
995 total_rx_bytes += ddp_bytes;
996 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
997 }
998#endif /* IXGBE_FCOE */
999
f494e8fa
AV		 1000 rx_ring->total_packets += total_rx_packets;
1001 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1002 netdev->stats.rx_bytes += total_rx_bytes;
1003 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1004
9a799d71
AK		 1005 return cleaned;
1006}
1007
021230d4 1008static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1009/**
1010 * ixgbe_configure_msix - Configure MSI-X hardware
1011 * @adapter: board private structure
1012 *
1013 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1014 * interrupts.
1015 **/
1016static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1017{
021230d4
AV		 1018 struct ixgbe_q_vector *q_vector;
1019 int i, j, q_vectors, v_idx, r_idx;
1020 u32 mask;
9a799d71 1021
021230d4 1022 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1023
4df10466
JB		 1024 /*
1025 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1026 * corresponding register.
1027 */
1028 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1029 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 1030 /* XXX for_each_bit(...) */
1031 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 1032 adapter->num_rx_queues);
021230d4
AV		 1033
1034 for (i = 0; i < q_vector->rxr_count; i++) {
1035 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 1036 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1037 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 1038 adapter->num_rx_queues,
1039 r_idx + 1);
021230d4
AV		 1040 }
1041 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 1042 adapter->num_tx_queues);
021230d4
AV		 1043
1044 for (i = 0; i < q_vector->txr_count; i++) {
1045 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 1046 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1047 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 1048 adapter->num_tx_queues,
1049 r_idx + 1);
021230d4
AV		 1050 }
1051
021230d4 1052 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1053 /* tx only */
1054 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1055 else if (q_vector->rxr_count)
f7554a2b
NS		 1056 /* rx or mixed */
1057 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1058
fe49f04a 1059 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1060 }
1061
e8e26350
PW		 1062 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1063 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1064 v_idx);
1065 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1066 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1067 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1068
41fb9248 1069 /* set up to autoclear timer, and the vectors */
021230d4 1070 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1071 if (adapter->num_vfs)
1072 mask &= ~(IXGBE_EIMS_OTHER |
1073 IXGBE_EIMS_MAILBOX |
1074 IXGBE_EIMS_LSC);
1075 else
1076 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1077 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1078}
1079
f494e8fa
AV		 1080enum latency_range {
1081 lowest_latency = 0,
1082 low_latency = 1,
1083 bulk_latency = 2,
1084 latency_invalid = 255
1085};
1086
1087/**
1088 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1089 * @adapter: pointer to adapter
1090 * @eitr: eitr setting (ints per sec) to give last timeslice
1091 * @itr_setting: current throttle rate in ints/second
1092 * @packets: the number of packets during this measurement interval
1093 * @bytes: the number of bytes during this measurement interval
1094 *
1095 * Stores a new ITR value based on packets and byte
1096 * counts during the last interrupt. The advantage of per interrupt
1097 * computation is faster updates and more accurate ITR for the current
1098 * traffic pattern. Constants in this function were computed
1099 * based on theoretical maximum wire speed and thresholds were set based
1100 * on testing data as well as attempting to minimize response time
1101 * while increasing bulk throughput.
1102 * this functionality is controlled by the InterruptThrottleRate module
1103 * parameter (see ixgbe_param.c)
1104 **/
1105static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 1106 u32 eitr, u8 itr_setting,
1107 int packets, int bytes)
f494e8fa
AV		 1108{
1109 unsigned int retval = itr_setting;
1110 u32 timepassed_us;
1111 u64 bytes_perint;
1112
1113 if (packets == 0)
1114 goto update_itr_done;
1115
1116
1117 /* simple throttlerate management
1118 * 0-20MB/s lowest (100000 ints/s)
1119 * 20-100MB/s low (20000 ints/s)
1120 * 100-1249MB/s bulk (8000 ints/s)
1121 */
1122 /* what was last interrupt timeslice? */
1123 timepassed_us = 1000000/eitr;
1124 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1125
1126 switch (itr_setting) {
1127 case lowest_latency:
1128 if (bytes_perint > adapter->eitr_low)
1129 retval = low_latency;
1130 break;
1131 case low_latency:
1132 if (bytes_perint > adapter->eitr_high)
1133 retval = bulk_latency;
1134 else if (bytes_perint <= adapter->eitr_low)
1135 retval = lowest_latency;
1136 break;
1137 case bulk_latency:
1138 if (bytes_perint <= adapter->eitr_high)
1139 retval = low_latency;
1140 break;
1141 }
1142
1143update_itr_done:
1144 return retval;
1145}
1146
509ee935
JB		 1147/**
1148 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1149 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1150 *
1151 * This function is made to be called by ethtool and by the driver
1152 * when it needs to update EITR registers at runtime. Hardware
1153 * specific quirks/differences are taken care of here.
1154 */
fe49f04a 1155void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1156{
fe49f04a 1157 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1158 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1159 int v_idx = q_vector->v_idx;
1160 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1161
509ee935
JB		 1162 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1163 /* must write high and low 16 bits to reset counter */
1164 itr_reg |= (itr_reg << 16);
1165 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1166 /*
1167 * set the WDIS bit to not clear the timer bits and cause an
1168 * immediate assertion of the interrupt
1169 */
1170 itr_reg |= IXGBE_EITR_CNT_WDIS;
1171 }
1172 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1173}
1174
f494e8fa
AV		 1175static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1176{
1177 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1178 u32 new_itr;
1179 u8 current_itr, ret_itr;
fe49f04a 1180 int i, r_idx;
f494e8fa
AV		 1181 struct ixgbe_ring *rx_ring, *tx_ring;
1182
1183 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1184 for (i = 0; i < q_vector->txr_count; i++) {
1185 tx_ring = &(adapter->tx_ring[r_idx]);
1186 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1187 q_vector->tx_itr,
1188 tx_ring->total_packets,
1189 tx_ring->total_bytes);
f494e8fa
AV		 1190 /* if the result for this queue would decrease interrupt
1191 * rate for this vector then use that result */
30efa5a3 1192 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1193 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1194 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1195 r_idx + 1);
f494e8fa
AV		 1196 }
1197
1198 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1199 for (i = 0; i < q_vector->rxr_count; i++) {
1200 rx_ring = &(adapter->rx_ring[r_idx]);
1201 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1202 q_vector->rx_itr,
1203 rx_ring->total_packets,
1204 rx_ring->total_bytes);
f494e8fa
AV		 1205 /* if the result for this queue would decrease interrupt
1206 * rate for this vector then use that result */
30efa5a3 1207 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1208 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1209 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1210 r_idx + 1);
f494e8fa
AV		 1211 }
1212
30efa5a3 1213 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1214
1215 switch (current_itr) {
1216 /* counts and packets in update_itr are dependent on these numbers */
1217 case lowest_latency:
1218 new_itr = 100000;
1219 break;
1220 case low_latency:
1221 new_itr = 20000; /* aka hwitr = ~200 */
1222 break;
1223 case bulk_latency:
1224 default:
1225 new_itr = 8000;
1226 break;
1227 }
1228
1229 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1230 /* do an exponential smoothing */
1231 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1232
1233 /* save the algorithm value here, not the smoothed one */
1234 q_vector->eitr = new_itr;
fe49f04a
AD		 1235
1236 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1237 }
1238
1239 return;
1240}
1241
0befdb3e
JB		 1242static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1243{
1244 struct ixgbe_hw *hw = &adapter->hw;
1245
1246 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1247 (eicr & IXGBE_EICR_GPI_SDP1)) {
1248 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1249 /* write to clear the interrupt */
1250 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1251 }
1252}
cf8280ee 1253
e8e26350
PW		 1254static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1255{
1256 struct ixgbe_hw *hw = &adapter->hw;
1257
1258 if (eicr & IXGBE_EICR_GPI_SDP1) {
1259 /* Clear the interrupt */
1260 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1261 schedule_work(&adapter->multispeed_fiber_task);
1262 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1263 /* Clear the interrupt */
1264 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1265 schedule_work(&adapter->sfp_config_module_task);
1266 } else {
1267 /* Interrupt isn't for us... */
1268 return;
1269 }
1270}
1271
cf8280ee
JB		 1272static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1273{
1274 struct ixgbe_hw *hw = &adapter->hw;
1275
1276 adapter->lsc_int++;
1277 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1278 adapter->link_check_timeout = jiffies;
1279 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1280 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1281 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1282 schedule_work(&adapter->watchdog_task);
1283 }
1284}
1285
9a799d71
AK		 1286static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1287{
1288 struct net_device *netdev = data;
1289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1290 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1291 u32 eicr;
1292
1293 /*
1294 * Workaround for Silicon errata. Use clear-by-write instead
1295 * of clear-by-read. Reading with EICS will return the
1296 * interrupt causes without clearing, which later be done
1297 * with the write to EICR.
1298 */
1299 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1300 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1301
cf8280ee
JB		 1302 if (eicr & IXGBE_EICR_LSC)
1303 ixgbe_check_lsc(adapter);
d4f80882 1304
1cdd1ec8
GR		 1305 if (eicr & IXGBE_EICR_MAILBOX)
1306 ixgbe_msg_task(adapter);
1307
e8e26350
PW		 1308 if (hw->mac.type == ixgbe_mac_82598EB)
1309 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1310
c4cf55e5 1311 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1312 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1313
1314 /* Handle Flow Director Full threshold interrupt */
1315 if (eicr & IXGBE_EICR_FLOW_DIR) {
1316 int i;
1317 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1318 /* Disable transmits before FDIR Re-initialization */
1319 netif_tx_stop_all_queues(netdev);
1320 for (i = 0; i < adapter->num_tx_queues; i++) {
1321 struct ixgbe_ring *tx_ring =
1322 &adapter->tx_ring[i];
1323 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1324 &tx_ring->reinit_state))
1325 schedule_work(&adapter->fdir_reinit_task);
1326 }
1327 }
1328 }
d4f80882
AV		 1329 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1330 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1331
1332 return IRQ_HANDLED;
1333}
1334
fe49f04a
AD		 1335static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1336 u64 qmask)
1337{
1338 u32 mask;
1339
1340 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1341 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1342 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1343 } else {
1344 mask = (qmask & 0xFFFFFFFF);
1345 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1346 mask = (qmask >> 32);
1347 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1348 }
1349 /* skip the flush */
1350}
1351
1352static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1353 u64 qmask)
1354{
1355 u32 mask;
1356
1357 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1358 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1359 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1360 } else {
1361 mask = (qmask & 0xFFFFFFFF);
1362 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1363 mask = (qmask >> 32);
1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1365 }
1366 /* skip the flush */
1367}
1368
9a799d71
AK		 1369static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1370{
021230d4
AV		 1371 struct ixgbe_q_vector *q_vector = data;
1372 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1373 struct ixgbe_ring *tx_ring;
021230d4
AV		 1374 int i, r_idx;
1375
1376 if (!q_vector->txr_count)
1377 return IRQ_HANDLED;
1378
1379 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1380 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1381 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1382 tx_ring->total_bytes = 0;
1383 tx_ring->total_packets = 0;
021230d4 1384 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1385 r_idx + 1);
021230d4 1386 }
9a799d71 1387
9b471446 1388 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1389 napi_schedule(&q_vector->napi);
1390
9a799d71
AK		 1391 return IRQ_HANDLED;
1392}
1393
021230d4
AV		 1394/**
1395 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1396 * @irq: unused
1397 * @data: pointer to our q_vector struct for this interrupt vector
1398 **/
9a799d71
AK		 1399static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1400{
021230d4
AV		 1401 struct ixgbe_q_vector *q_vector = data;
1402 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1403 struct ixgbe_ring *rx_ring;
021230d4 1404 int r_idx;
30efa5a3 1405 int i;
021230d4
AV		 1406
1407 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1408 for (i = 0; i < q_vector->rxr_count; i++) {
1409 rx_ring = &(adapter->rx_ring[r_idx]);
1410 rx_ring->total_bytes = 0;
1411 rx_ring->total_packets = 0;
1412 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1413 r_idx + 1);
1414 }
1415
021230d4
AV		 1416 if (!q_vector->rxr_count)
1417 return IRQ_HANDLED;
1418
021230d4 1419 /* disable interrupts on this vector only */
9b471446 1420 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1421 napi_schedule(&q_vector->napi);
021230d4
AV		 1422
1423 return IRQ_HANDLED;
1424}
1425
1426static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1427{
91281fd3
AD		 1428 struct ixgbe_q_vector *q_vector = data;
1429 struct ixgbe_adapter *adapter = q_vector->adapter;
1430 struct ixgbe_ring *ring;
1431 int r_idx;
1432 int i;
1433
1434 if (!q_vector->txr_count && !q_vector->rxr_count)
1435 return IRQ_HANDLED;
1436
1437 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1438 for (i = 0; i < q_vector->txr_count; i++) {
1439 ring = &(adapter->tx_ring[r_idx]);
1440 ring->total_bytes = 0;
1441 ring->total_packets = 0;
1442 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1443 r_idx + 1);
1444 }
1445
1446 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1447 for (i = 0; i < q_vector->rxr_count; i++) {
1448 ring = &(adapter->rx_ring[r_idx]);
1449 ring->total_bytes = 0;
1450 ring->total_packets = 0;
1451 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1452 r_idx + 1);
1453 }
1454
9b471446 1455 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1456 napi_schedule(&q_vector->napi);
9a799d71 1457
9a799d71
AK		 1458 return IRQ_HANDLED;
1459}
1460
021230d4
AV		 1461/**
1462 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1463 * @napi: napi struct with our devices info in it
1464 * @budget: amount of work driver is allowed to do this pass, in packets
1465 *
f0848276
JB		 1466 * This function is optimized for cleaning one queue only on a single
1467 * q_vector!!!
021230d4 1468 **/
9a799d71
AK		 1469static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1470{
021230d4 1471 struct ixgbe_q_vector *q_vector =
b4617240 1472 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1473 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1474 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1475 int work_done = 0;
021230d4 1476 long r_idx;
9a799d71 1477
021230d4 1478 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1479 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1480#ifdef CONFIG_IXGBE_DCA
bd0362dd 1481 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1482 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1483#endif
9a799d71 1484
78b6f4ce 1485 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1486
021230d4
AV		 1487 /* If all Rx work done, exit the polling mode */
1488 if (work_done < budget) {
288379f0 1489 napi_complete(napi);
f7554a2b 1490 if (adapter->rx_itr_setting & 1)
f494e8fa 1491 ixgbe_set_itr_msix(q_vector);
9a799d71 1492 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1493 ixgbe_irq_enable_queues(adapter,
1494 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1495 }
1496
1497 return work_done;
1498}
1499
f0848276 1500/**
91281fd3 1501 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1502 * @napi: napi struct with our devices info in it
1503 * @budget: amount of work driver is allowed to do this pass, in packets
1504 *
1505 * This function will clean more than one rx queue associated with a
1506 * q_vector.
1507 **/
91281fd3 1508static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1509{
1510 struct ixgbe_q_vector *q_vector =
1511 container_of(napi, struct ixgbe_q_vector, napi);
1512 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1513 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1514 int work_done = 0, i;
1515 long r_idx;
91281fd3
AD		 1516 bool tx_clean_complete = true;
1517
1518 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1519 for (i = 0; i < q_vector->txr_count; i++) {
1520 ring = &(adapter->tx_ring[r_idx]);
1521#ifdef CONFIG_IXGBE_DCA
1522 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1523 ixgbe_update_tx_dca(adapter, ring);
1524#endif
1525 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1526 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1527 r_idx + 1);
1528 }
f0848276
JB		 1529
1530 /* attempt to distribute budget to each queue fairly, but don't allow
1531 * the budget to go below 1 because we'll exit polling */
1532 budget /= (q_vector->rxr_count ?: 1);
1533 budget = max(budget, 1);
1534 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1535 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1536 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1537#ifdef CONFIG_IXGBE_DCA
f0848276 1538 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1539 ixgbe_update_rx_dca(adapter, ring);
f0848276 1540#endif
91281fd3 1541 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1542 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1543 r_idx + 1);
1544 }
1545
1546 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1547 ring = &(adapter->rx_ring[r_idx]);
f0848276 1548 /* If all Rx work done, exit the polling mode */
7f821875 1549 if (work_done < budget) {
288379f0 1550 napi_complete(napi);
f7554a2b 1551 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1552 ixgbe_set_itr_msix(q_vector);
1553 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1554 ixgbe_irq_enable_queues(adapter,
1555 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1556 return 0;
1557 }
1558
1559 return work_done;
1560}
91281fd3
AD		 1561
1562/**
1563 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1564 * @napi: napi struct with our devices info in it
1565 * @budget: amount of work driver is allowed to do this pass, in packets
1566 *
1567 * This function is optimized for cleaning one queue only on a single
1568 * q_vector!!!
1569 **/
1570static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1571{
1572 struct ixgbe_q_vector *q_vector =
1573 container_of(napi, struct ixgbe_q_vector, napi);
1574 struct ixgbe_adapter *adapter = q_vector->adapter;
1575 struct ixgbe_ring *tx_ring = NULL;
1576 int work_done = 0;
1577 long r_idx;
1578
1579 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1580 tx_ring = &(adapter->tx_ring[r_idx]);
1581#ifdef CONFIG_IXGBE_DCA
1582 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1583 ixgbe_update_tx_dca(adapter, tx_ring);
1584#endif
1585
1586 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1587 work_done = budget;
1588
f7554a2b 1589 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1590 if (work_done < budget) {
1591 napi_complete(napi);
f7554a2b 1592 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1593 ixgbe_set_itr_msix(q_vector);
1594 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1595 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1596 }
1597
1598 return work_done;
1599}
1600
021230d4 1601static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1602 int r_idx)
021230d4 1603{
7a921c93
AD		 1604 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1605
1606 set_bit(r_idx, q_vector->rxr_idx);
1607 q_vector->rxr_count++;
021230d4
AV		 1608}
1609
1610static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1611 int t_idx)
021230d4 1612{
7a921c93
AD		 1613 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1614
1615 set_bit(t_idx, q_vector->txr_idx);
1616 q_vector->txr_count++;
021230d4
AV		 1617}
1618
9a799d71 1619/**
021230d4
AV		 1620 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1621 * @adapter: board private structure to initialize
1622 * @vectors: allotted vector count for descriptor rings
9a799d71 1623 *
021230d4
AV		 1624 * This function maps descriptor rings to the queue-specific vectors
1625 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1626 * one vector per ring/queue, but on a constrained vector budget, we
1627 * group the rings as "efficiently" as possible. You would add new
1628 * mapping configurations in here.
9a799d71 1629 **/
021230d4 1630static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1631 int vectors)
021230d4
AV		 1632{
1633 int v_start = 0;
1634 int rxr_idx = 0, txr_idx = 0;
1635 int rxr_remaining = adapter->num_rx_queues;
1636 int txr_remaining = adapter->num_tx_queues;
1637 int i, j;
1638 int rqpv, tqpv;
1639 int err = 0;
1640
1641 /* No mapping required if MSI-X is disabled. */
1642 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1643 goto out;
9a799d71 1644
021230d4
AV		 1645 /*
1646 * The ideal configuration...
1647 * We have enough vectors to map one per queue.
1648 */
1649 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1650 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1651 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1652
021230d4
AV		 1653 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1654 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1655
9a799d71 1656 goto out;
021230d4 1657 }
9a799d71 1658
021230d4
AV		 1659 /*
1660 * If we don't have enough vectors for a 1-to-1
1661 * mapping, we'll have to group them so there are
1662 * multiple queues per vector.
1663 */
1664 /* Re-adjusting *qpv takes care of the remainder. */
1665 for (i = v_start; i < vectors; i++) {
1666 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1667 for (j = 0; j < rqpv; j++) {
1668 map_vector_to_rxq(adapter, i, rxr_idx);
1669 rxr_idx++;
1670 rxr_remaining--;
1671 }
1672 }
1673 for (i = v_start; i < vectors; i++) {
1674 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1675 for (j = 0; j < tqpv; j++) {
1676 map_vector_to_txq(adapter, i, txr_idx);
1677 txr_idx++;
1678 txr_remaining--;
9a799d71 1679 }
9a799d71
AK		 1680 }
1681
021230d4
AV		 1682out:
1683 return err;
1684}
1685
1686/**
1687 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1688 * @adapter: board private structure
1689 *
1690 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1691 * interrupts from the kernel.
1692 **/
1693static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1694{
1695 struct net_device *netdev = adapter->netdev;
1696 irqreturn_t (*handler)(int, void *);
1697 int i, vector, q_vectors, err;
cb13fc20 1698 int ri=0, ti=0;
021230d4
AV		 1699
1700 /* Decrement for Other and TCP Timer vectors */
1701 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1702
1703 /* Map the Tx/Rx rings to the vectors we were allotted. */
1704 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1705 if (err)
1706 goto out;
1707
1708#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1709 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1710 &ixgbe_msix_clean_many)
021230d4 1711 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1712 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1713
1714 if(handler == &ixgbe_msix_clean_rx) {
1715 sprintf(adapter->name[vector], "%s-%s-%d",
1716 netdev->name, "rx", ri++);
1717 }
1718 else if(handler == &ixgbe_msix_clean_tx) {
1719 sprintf(adapter->name[vector], "%s-%s-%d",
1720 netdev->name, "tx", ti++);
1721 }
1722 else
1723 sprintf(adapter->name[vector], "%s-%s-%d",
1724 netdev->name, "TxRx", vector);
1725
021230d4 1726 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1727 handler, 0, adapter->name[vector],
7a921c93 1728 adapter->q_vector[vector]);
9a799d71
AK		 1729 if (err) {
1730 DPRINTK(PROBE, ERR,
b4617240
PW		 1731 "request_irq failed for MSIX interrupt "
1732 "Error: %d\n", err);
021230d4 1733 goto free_queue_irqs;
9a799d71 1734 }
9a799d71
AK		 1735 }
1736
021230d4
AV		 1737 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1738 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1739 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1740 if (err) {
1741 DPRINTK(PROBE, ERR,
1742 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1743 goto free_queue_irqs;
9a799d71
AK		 1744 }
1745
9a799d71
AK		 1746 return 0;
1747
021230d4
AV		 1748free_queue_irqs:
1749 for (i = vector - 1; i >= 0; i--)
1750 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1751 adapter->q_vector[i]);
021230d4
AV		 1752 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1753 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1754 kfree(adapter->msix_entries);
1755 adapter->msix_entries = NULL;
021230d4 1756out:
9a799d71
AK		 1757 return err;
1758}
1759
f494e8fa
AV		 1760static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1761{
7a921c93 1762 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1763 u8 current_itr;
1764 u32 new_itr = q_vector->eitr;
1765 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1766 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1767
30efa5a3 1768 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1769 q_vector->tx_itr,
1770 tx_ring->total_packets,
1771 tx_ring->total_bytes);
30efa5a3 1772 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1773 q_vector->rx_itr,
1774 rx_ring->total_packets,
1775 rx_ring->total_bytes);
f494e8fa 1776
30efa5a3 1777 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1778
1779 switch (current_itr) {
1780 /* counts and packets in update_itr are dependent on these numbers */
1781 case lowest_latency:
1782 new_itr = 100000;
1783 break;
1784 case low_latency:
1785 new_itr = 20000; /* aka hwitr = ~200 */
1786 break;
1787 case bulk_latency:
1788 new_itr = 8000;
1789 break;
1790 default:
1791 break;
1792 }
1793
1794 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1795 /* do an exponential smoothing */
1796 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1797
1798 /* save the algorithm value here, not the smoothed one */
1799 q_vector->eitr = new_itr;
fe49f04a
AD		 1800
1801 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1802 }
1803
1804 return;
1805}
1806
79aefa45
AD		 1807/**
1808 * ixgbe_irq_enable - Enable default interrupt generation settings
1809 * @adapter: board private structure
1810 **/
1811static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1812{
1813 u32 mask;
835462fc
NS		 1814
1815 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1816 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1817 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1818 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1819 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1820 mask |= IXGBE_EIMS_GPI_SDP1;
1821 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 1822 if (adapter->num_vfs)
1823 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 1824 }
c4cf55e5
PWJ		 1825 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1826 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1827 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1828
79aefa45 1829 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1830 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 1831 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 1832
1833 if (adapter->num_vfs > 32) {
1834 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1836 }
79aefa45 1837}
021230d4 1838
9a799d71 1839/**
021230d4 1840 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1841 * @irq: interrupt number
1842 * @data: pointer to a network interface device structure
9a799d71
AK		 1843 **/
1844static irqreturn_t ixgbe_intr(int irq, void *data)
1845{
1846 struct net_device *netdev = data;
1847 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1848 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1849 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1850 u32 eicr;
1851
54037505
DS		 1852 /*
1853 * Workaround for silicon errata. Mask the interrupts
1854 * before the read of EICR.
1855 */
1856 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1857
021230d4
AV		 1858 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1859 * therefore no explict interrupt disable is necessary */
1860 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1861 if (!eicr) {
1862 /* shared interrupt alert!
1863 * make sure interrupts are enabled because the read will
1864 * have disabled interrupts due to EIAM */
1865 ixgbe_irq_enable(adapter);
9a799d71 1866 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1867 }
9a799d71 1868
cf8280ee
JB		 1869 if (eicr & IXGBE_EICR_LSC)
1870 ixgbe_check_lsc(adapter);
021230d4 1871
e8e26350
PW		 1872 if (hw->mac.type == ixgbe_mac_82599EB)
1873 ixgbe_check_sfp_event(adapter, eicr);
1874
0befdb3e
JB		 1875 ixgbe_check_fan_failure(adapter, eicr);
1876
7a921c93 1877 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1878 adapter->tx_ring[0].total_packets = 0;
1879 adapter->tx_ring[0].total_bytes = 0;
1880 adapter->rx_ring[0].total_packets = 0;
1881 adapter->rx_ring[0].total_bytes = 0;
021230d4 1882 /* would disable interrupts here but EIAM disabled it */
7a921c93 1883 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1884 }
1885
1886 return IRQ_HANDLED;
1887}
1888
021230d4
AV		 1889static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1890{
1891 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1892
1893 for (i = 0; i < q_vectors; i++) {
7a921c93 1894 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1895 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1896 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1897 q_vector->rxr_count = 0;
1898 q_vector->txr_count = 0;
1899 }
1900}
1901
9a799d71
AK		 1902/**
1903 * ixgbe_request_irq - initialize interrupts
1904 * @adapter: board private structure
1905 *
1906 * Attempts to configure interrupts using the best available
1907 * capabilities of the hardware and kernel.
1908 **/
021230d4 1909static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1910{
1911 struct net_device *netdev = adapter->netdev;
021230d4 1912 int err;
9a799d71 1913
021230d4
AV		 1914 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1915 err = ixgbe_request_msix_irqs(adapter);
1916 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 1917 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
b4617240 1918 netdev->name, netdev);
021230d4 1919 } else {
a0607fd3 1920 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
b4617240 1921 netdev->name, netdev);
9a799d71
AK		 1922 }
1923
9a799d71
AK		 1924 if (err)
1925 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1926
9a799d71
AK		 1927 return err;
1928}
1929
1930static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1931{
1932 struct net_device *netdev = adapter->netdev;
1933
1934 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1935 int i, q_vectors;
9a799d71 1936
021230d4
AV		 1937 q_vectors = adapter->num_msix_vectors;
1938
1939 i = q_vectors - 1;
9a799d71 1940 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1941
021230d4
AV		 1942 i--;
1943 for (; i >= 0; i--) {
1944 free_irq(adapter->msix_entries[i].vector,
7a921c93 1945 adapter->q_vector[i]);
021230d4
AV		 1946 }
1947
1948 ixgbe_reset_q_vectors(adapter);
1949 } else {
1950 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1951 }
1952}
1953
22d5a71b
JB		 1954/**
1955 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1956 * @adapter: board private structure
1957 **/
1958static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1959{
835462fc
NS		 1960 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1961 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1962 } else {
1963 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1964 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1965 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 1966 if (adapter->num_vfs > 32)
1967 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 1968 }
1969 IXGBE_WRITE_FLUSH(&adapter->hw);
1970 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1971 int i;
1972 for (i = 0; i < adapter->num_msix_vectors; i++)
1973 synchronize_irq(adapter->msix_entries[i].vector);
1974 } else {
1975 synchronize_irq(adapter->pdev->irq);
1976 }
1977}
1978
9a799d71
AK		 1979/**
1980 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1981 *
1982 **/
1983static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1984{
9a799d71
AK		 1985 struct ixgbe_hw *hw = &adapter->hw;
1986
021230d4 1987 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 1988 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 1989
e8e26350
PW		 1990 ixgbe_set_ivar(adapter, 0, 0, 0);
1991 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1992
1993 map_vector_to_rxq(adapter, 0, 0);
1994 map_vector_to_txq(adapter, 0, 0);
1995
1996 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1997}
1998
1999/**
3a581073 2000 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2001 * @adapter: board private structure
2002 *
2003 * Configure the Tx unit of the MAC after a reset.
2004 **/
2005static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2006{
12207e49 2007 u64 tdba;
9a799d71 2008 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2009 u32 i, j, tdlen, txctrl;
9a799d71
AK		 2010
2011 /* Setup the HW Tx Head and Tail descriptor pointers */
2012 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 2013 struct ixgbe_ring *ring = &adapter->tx_ring[i];
2014 j = ring->reg_idx;
2015 tdba = ring->dma;
2016 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 2017 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 2018 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 2019 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2020 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2021 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2022 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2023 adapter->tx_ring[i].head = IXGBE_TDH(j);
2024 adapter->tx_ring[i].tail = IXGBE_TDT(j);
84f62d4b
PWJ		 2025 /*
2026 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 2027 * bookkeeping if things aren't delivered in order.
2028 */
84f62d4b
PWJ		 2029 switch (hw->mac.type) {
2030 case ixgbe_mac_82598EB:
2031 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2032 break;
2033 case ixgbe_mac_82599EB:
2034 default:
2035 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2036 break;
2037 }
021230d4 2038 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 2039 switch (hw->mac.type) {
2040 case ixgbe_mac_82598EB:
2041 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2042 break;
2043 case ixgbe_mac_82599EB:
2044 default:
2045 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2046 break;
2047 }
9a799d71 2048 }
ee5f784a 2049
e8e26350 2050 if (hw->mac.type == ixgbe_mac_82599EB) {
ee5f784a 2051 u32 rttdcs;
1cdd1ec8 2052 u32 mask;
ee5f784a
DS		 2053
2054 /* disable the arbiter while setting MTQC */
2055 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2056 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2057 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2058
1cdd1ec8
GR		 2059 /* set transmit pool layout */
2060 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2061 switch (adapter->flags & mask) {
2062
2063 case (IXGBE_FLAG_SRIOV_ENABLED):
2064 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2065 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2066 break;
2067
2068 case (IXGBE_FLAG_DCB_ENABLED):
2069 /* We enable 8 traffic classes, DCB only */
2070 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2071 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2072 break;
2073
2074 default:
ee5f784a 2075 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1cdd1ec8
GR		 2076 break;
2077 }
ee5f784a
DS		 2078
2079 /* re-eable the arbiter */
2080 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2081 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
e8e26350 2082 }
9a799d71
AK		 2083}
2084
e8e26350 2085#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2086
a6616b42
YZ		 2087static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2088 struct ixgbe_ring *rx_ring)
cc41ac7c 2089{
cc41ac7c 2090 u32 srrctl;
a6616b42 2091 int index;
0cefafad 2092 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2093
a6616b42
YZ		 2094 index = rx_ring->reg_idx;
2095 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2096 unsigned long mask;
0cefafad 2097 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2098 index = index & mask;
cc41ac7c 2099 }
cc41ac7c
JB		 2100 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2101
2102 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2103 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2104
afafd5b0
AD		 2105 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2106 IXGBE_SRRCTL_BSIZEHDR_MASK;
2107
6e455b89 2108 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2109#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2110 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2111#else
2112 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2113#endif
cc41ac7c 2114 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2115 } else {
afafd5b0
AD		 2116 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2117 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2118 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2119 }
e8e26350 2120
cc41ac7c
JB		 2121 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2122}
9a799d71 2123
0cefafad
JB		 2124static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2125{
2126 u32 mrqc = 0;
2127 int mask;
2128
2129 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2130 return mrqc;
2131
2132 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2133#ifdef CONFIG_IXGBE_DCB
2134 | IXGBE_FLAG_DCB_ENABLED
2135#endif
1cdd1ec8 2136 | IXGBE_FLAG_SRIOV_ENABLED
0cefafad
JB		 2137 );
2138
2139 switch (mask) {
2140 case (IXGBE_FLAG_RSS_ENABLED):
2141 mrqc = IXGBE_MRQC_RSSEN;
2142 break;
1cdd1ec8
GR		 2143 case (IXGBE_FLAG_SRIOV_ENABLED):
2144 mrqc = IXGBE_MRQC_VMDQEN;
2145 break;
0cefafad
JB		 2146#ifdef CONFIG_IXGBE_DCB
2147 case (IXGBE_FLAG_DCB_ENABLED):
2148 mrqc = IXGBE_MRQC_RT8TCEN;
2149 break;
2150#endif /* CONFIG_IXGBE_DCB */
2151 default:
2152 break;
2153 }
2154
2155 return mrqc;
2156}
2157
bb5a9ad2
NS		 2158/**
2159 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2160 * @adapter: address of board private structure
2161 * @index: index of ring to set
bb5a9ad2 2162 **/
edd2ea55 2163static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
bb5a9ad2
NS		 2164{
2165 struct ixgbe_ring *rx_ring;
2166 struct ixgbe_hw *hw = &adapter->hw;
2167 int j;
2168 u32 rscctrl;
edd2ea55 2169 int rx_buf_len;
bb5a9ad2
NS		 2170
2171 rx_ring = &adapter->rx_ring[index];
2172 j = rx_ring->reg_idx;
edd2ea55 2173 rx_buf_len = rx_ring->rx_buf_len;
bb5a9ad2
NS		 2174 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2175 rscctrl |= IXGBE_RSCCTL_RSCEN;
2176 /*
2177 * we must limit the number of descriptors so that the
2178 * total size of max desc * buf_len is not greater
2179 * than 65535
2180 */
2181 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2182#if (MAX_SKB_FRAGS > 16)
2183 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2184#elif (MAX_SKB_FRAGS > 8)
2185 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2186#elif (MAX_SKB_FRAGS > 4)
2187 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2188#else
2189 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2190#endif
2191 } else {
2192 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2193 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2194 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2195 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2196 else
2197 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2198 }
2199 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2200}
2201
9a799d71 2202/**
3a581073 2203 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2204 * @adapter: board private structure
2205 *
2206 * Configure the Rx unit of the MAC after a reset.
2207 **/
2208static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2209{
2210 u64 rdba;
2211 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2212 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2213 struct net_device *netdev = adapter->netdev;
2214 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2215 int i, j;
9a799d71 2216 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2217 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2218 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2219 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2220 u32 fctrl, hlreg0;
509ee935 2221 u32 reta = 0, mrqc = 0;
cc41ac7c 2222 u32 rdrxctl;
7c6e0a43 2223 int rx_buf_len;
9a799d71
AK		 2224
2225 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2226 /* Do not use packet split if we're in SR-IOV Mode */
2227 if (!adapter->num_vfs)
2228 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2229
2230 /* Set the RX buffer length according to the mode */
2231 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2232 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2233 if (hw->mac.type == ixgbe_mac_82599EB) {
2234 /* PSRTYPE must be initialized in 82599 */
2235 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2236 IXGBE_PSRTYPE_UDPHDR |
2237 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2238 IXGBE_PSRTYPE_IPV6HDR |
2239 IXGBE_PSRTYPE_L2HDR;
1cdd1ec8
GR		 2240 IXGBE_WRITE_REG(hw,
2241 IXGBE_PSRTYPE(adapter->num_vfs),
2242 psrtype);
e8e26350 2243 }
9a799d71 2244 } else {
0c19d6af 2245 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2246 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2247 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2248 else
7c6e0a43 2249 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2250 }
2251
2252 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2253 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2254 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2255 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2257
2258 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2259 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2260 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2261 else
2262 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2263#ifdef IXGBE_FCOE
f34c5c82 2264 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2265 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2266#endif
9a799d71
AK		 2267 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2268
9a799d71
AK		 2269 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2270 /* disable receives while setting up the descriptors */
2271 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2272 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2273
0cefafad
JB		 2274 /*
2275 * Setup the HW Rx Head and Tail Descriptor Pointers and
2276 * the Base and Length of the Rx Descriptor Ring
2277 */
9a799d71 2278 for (i = 0; i < adapter->num_rx_queues; i++) {
a6616b42
YZ		 2279 rx_ring = &adapter->rx_ring[i];
2280 rdba = rx_ring->dma;
2281 j = rx_ring->reg_idx;
284901a9 2282 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2283 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2284 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2285 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2286 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2287 rx_ring->head = IXGBE_RDH(j);
2288 rx_ring->tail = IXGBE_RDT(j);
2289 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2290
6e455b89
YZ		 2291 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2292 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2293 else
2294 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2295
63f39bd1 2296#ifdef IXGBE_FCOE
f34c5c82 2297 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2298 struct ixgbe_ring_feature *f;
2299 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2300 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2301 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2302 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2303 rx_ring->rx_buf_len =
2304 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2305 }
63f39bd1
YZ		 2306 }
2307
2308#endif /* IXGBE_FCOE */
a6616b42 2309 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2310 }
2311
e8e26350
PW		 2312 if (hw->mac.type == ixgbe_mac_82598EB) {
2313 /*
2314 * For VMDq support of different descriptor types or
2315 * buffer sizes through the use of multiple SRRCTL
2316 * registers, RDRXCTL.MVMEN must be set to 1
2317 *
2318 * also, the manual doesn't mention it clearly but DCA hints
2319 * will only use queue 0's tags unless this bit is set. Side
2320 * effects of setting this bit are only that SRRCTL must be
2321 * fully programmed [0..15]
2322 */
2a41ff81
JB		 2323 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2324 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2325 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2326 }
177db6ff 2327
1cdd1ec8
GR		 2328 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2329 u32 vt_reg_bits;
2330 u32 reg_offset, vf_shift;
2331 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2332 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2333 | IXGBE_VT_CTL_REPLEN;
2334 vt_reg_bits |= (adapter->num_vfs <<
2335 IXGBE_VT_CTL_POOL_SHIFT);
2336 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2337 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2338
2339 vf_shift = adapter->num_vfs % 32;
2340 reg_offset = adapter->num_vfs / 32;
2341 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2342 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2343 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2344 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2345 /* Enable only the PF's pool for Tx/Rx */
2346 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2347 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2348 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2349 ixgbe_set_vmolr(hw, adapter->num_vfs);
2350 }
2351
e8e26350 2352 /* Program MRQC for the distribution of queues */
0cefafad 2353 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2354
021230d4 2355 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2356 /* Fill out redirection table */
021230d4
AV		 2357 for (i = 0, j = 0; i < 128; i++, j++) {
2358 if (j == adapter->ring_feature[RING_F_RSS].indices)
2359 j = 0;
2360 /* reta = 4-byte sliding window of
2361 * 0x00..(indices-1)(indices-1)00..etc. */
2362 reta = (reta << 8) | (j * 0x11);
2363 if ((i & 3) == 3)
2364 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2365 }
2366
2367 /* Fill out hash function seeds */
2368 for (i = 0; i < 10; i++)
7c6e0a43 2369 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2370
2a41ff81
JB		 2371 if (hw->mac.type == ixgbe_mac_82598EB)
2372 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2373 /* Perform hash on these packet types */
2a41ff81
JB		 2374 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2375 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2376 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2377 | IXGBE_MRQC_RSS_FIELD_IPV6
2378 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2379 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2380 }
2a41ff81 2381 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2382
1cdd1ec8
GR		 2383 if (adapter->num_vfs) {
2384 u32 reg;
2385
2386 /* Map PF MAC address in RAR Entry 0 to first pool
2387 * following VFs */
2388 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2389
2390 /* Set up VF register offsets for selected VT Mode, i.e.
2391 * 64 VFs for SR-IOV */
2392 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2393 reg |= IXGBE_GCR_EXT_SRIOV;
2394 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2395 }
2396
021230d4
AV		 2397 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2398
2399 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2400 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2401 /* Disable indicating checksum in descriptor, enables
2402 * RSS hash */
9a799d71 2403 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2404 }
021230d4
AV		 2405 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2406 /* Enable IPv4 payload checksum for UDP fragments
2407 * if PCSD is not set */
2408 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2409 }
2410
2411 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2412
2413 if (hw->mac.type == ixgbe_mac_82599EB) {
2414 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2415 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2416 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2417 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2418 }
f8212f97 2419
0c19d6af 2420 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2421 /* Enable 82599 HW-RSC */
bb5a9ad2 2422 for (i = 0; i < adapter->num_rx_queues; i++)
edd2ea55 2423 ixgbe_configure_rscctl(adapter, i);
bb5a9ad2 2424
f8212f97
AD		 2425 /* Disable RSC for ACK packets */
2426 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2427 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2428 }
9a799d71
AK		 2429}
2430
068c89b0
DS		 2431static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2432{
2433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2434 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2435 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2436
2437 /* add VID to filter table */
1ada1b1b 2438 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 2439}
2440
2441static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2442{
2443 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2444 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 2445 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 2446
2447 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2448 ixgbe_irq_disable(adapter);
2449
2450 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2451
2452 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2453 ixgbe_irq_enable(adapter);
2454
2455 /* remove VID from filter table */
1ada1b1b 2456 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 2457}
2458
9a799d71 2459static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2460 struct vlan_group *grp)
9a799d71
AK		 2461{
2462 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2463 u32 ctrl;
e8e26350 2464 int i, j;
9a799d71 2465
d4f80882
AV		 2466 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2467 ixgbe_irq_disable(adapter);
9a799d71
AK		 2468 adapter->vlgrp = grp;
2469
2f90b865
AD		 2470 /*
2471 * For a DCB driver, always enable VLAN tag stripping so we can
2472 * still receive traffic from a DCB-enabled host even if we're
2473 * not in DCB mode.
2474 */
2475 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
dc63d377
AD		 2476
2477 /* Disable CFI check */
2478 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2479
2480 /* enable VLAN tag stripping */
e8e26350 2481 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
dc63d377 2482 ctrl |= IXGBE_VLNCTRL_VME;
e8e26350 2483 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
e8e26350 2484 for (i = 0; i < adapter->num_rx_queues; i++) {
dc63d377 2485 u32 ctrl;
e8e26350
PW		 2486 j = adapter->rx_ring[i].reg_idx;
2487 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2488 ctrl |= IXGBE_RXDCTL_VME;
2489 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2490 }
9a799d71 2491 }
dc63d377
AD		 2492
2493 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2494
e8e26350 2495 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2496
d4f80882
AV		 2497 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2498 ixgbe_irq_enable(adapter);
9a799d71
AK		 2499}
2500
9a799d71
AK		 2501static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2502{
2503 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2504
2505 if (adapter->vlgrp) {
2506 u16 vid;
2507 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2508 if (!vlan_group_get_device(adapter->vlgrp, vid))
2509 continue;
2510 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2511 }
2512 }
2513}
2514
2c5645cf
CL		 2515static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2516{
2517 struct dev_mc_list *mc_ptr;
2518 u8 *addr = *mc_addr_ptr;
2519 *vmdq = 0;
2520
2521 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2522 if (mc_ptr->next)
2523 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2524 else
2525 *mc_addr_ptr = NULL;
2526
2527 return addr;
2528}
2529
9a799d71 2530/**
2c5645cf 2531 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2532 * @netdev: network interface device structure
2533 *
2c5645cf
CL		 2534 * The set_rx_method entry point is called whenever the unicast/multicast
2535 * address list or the network interface flags are updated. This routine is
2536 * responsible for configuring the hardware for proper unicast, multicast and
2537 * promiscuous mode.
9a799d71 2538 **/
7f870475 2539void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2540{
2541 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2542 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2543 u32 fctrl, vlnctrl;
2c5645cf
CL		 2544 u8 *addr_list = NULL;
2545 int addr_count = 0;
9a799d71
AK		 2546
2547 /* Check for Promiscuous and All Multicast modes */
2548
2549 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2550 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2551
2552 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2553 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2554 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2555 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2556 } else {
746b9f02
PM		 2557 if (netdev->flags & IFF_ALLMULTI) {
2558 fctrl |= IXGBE_FCTRL_MPE;
2559 fctrl &= ~IXGBE_FCTRL_UPE;
2560 } else {
2561 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2562 }
3d01625a 2563 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2564 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2565 }
2566
2567 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2568 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2569
2c5645cf 2570 /* reprogram secondary unicast list */
32e7bfc4 2571 hw->mac.ops.update_uc_addr_list(hw, netdev);
9a799d71 2572
2c5645cf
CL		 2573 /* reprogram multicast list */
2574 addr_count = netdev->mc_count;
2575 if (addr_count)
2576 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2577 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2578 ixgbe_addr_list_itr);
1cdd1ec8
GR		 2579 if (adapter->num_vfs)
2580 ixgbe_restore_vf_multicasts(adapter);
9a799d71
AK		 2581}
2582
021230d4
AV		 2583static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2584{
2585 int q_idx;
2586 struct ixgbe_q_vector *q_vector;
2587 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2588
2589 /* legacy and MSI only use one vector */
2590 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2591 q_vectors = 1;
2592
2593 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2594 struct napi_struct *napi;
7a921c93 2595 q_vector = adapter->q_vector[q_idx];
f0848276 2596 napi = &q_vector->napi;
91281fd3
AD		 2597 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2598 if (!q_vector->rxr_count || !q_vector->txr_count) {
2599 if (q_vector->txr_count == 1)
2600 napi->poll = &ixgbe_clean_txonly;
2601 else if (q_vector->rxr_count == 1)
2602 napi->poll = &ixgbe_clean_rxonly;
2603 }
2604 }
f0848276
JB		 2605
2606 napi_enable(napi);
021230d4
AV		 2607 }
2608}
2609
2610static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2611{
2612 int q_idx;
2613 struct ixgbe_q_vector *q_vector;
2614 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2615
2616 /* legacy and MSI only use one vector */
2617 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2618 q_vectors = 1;
2619
2620 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2621 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2622 napi_disable(&q_vector->napi);
2623 }
2624}
2625
7a6b6f51 2626#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2627/*
2628 * ixgbe_configure_dcb - Configure DCB hardware
2629 * @adapter: ixgbe adapter struct
2630 *
2631 * This is called by the driver on open to configure the DCB hardware.
2632 * This is also called by the gennetlink interface when reconfiguring
2633 * the DCB state.
2634 */
2635static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2636{
2637 struct ixgbe_hw *hw = &adapter->hw;
2638 u32 txdctl, vlnctrl;
2639 int i, j;
2640
2641 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2642 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2643 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2644
2645 /* reconfigure the hardware */
2646 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2647
2648 for (i = 0; i < adapter->num_tx_queues; i++) {
2649 j = adapter->tx_ring[i].reg_idx;
2650 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2651 /* PThresh workaround for Tx hang with DFP enabled. */
2652 txdctl |= 32;
2653 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2654 }
2655 /* Enable VLAN tag insert/strip */
2656 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2657 if (hw->mac.type == ixgbe_mac_82598EB) {
2658 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2659 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2660 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2661 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2662 vlnctrl |= IXGBE_VLNCTRL_VFE;
2663 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2664 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2665 for (i = 0; i < adapter->num_rx_queues; i++) {
2666 j = adapter->rx_ring[i].reg_idx;
2667 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2668 vlnctrl |= IXGBE_RXDCTL_VME;
2669 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2670 }
2671 }
2f90b865
AD		 2672 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2673}
2674
2675#endif
9a799d71
AK		 2676static void ixgbe_configure(struct ixgbe_adapter *adapter)
2677{
2678 struct net_device *netdev = adapter->netdev;
c4cf55e5 2679 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2680 int i;
2681
2c5645cf 2682 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2683
2684 ixgbe_restore_vlan(adapter);
7a6b6f51 2685#ifdef CONFIG_IXGBE_DCB
2f90b865 2686 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
b352e40d
YZ		 2687 if (hw->mac.type == ixgbe_mac_82598EB)
2688 netif_set_gso_max_size(netdev, 32768);
2689 else
2690 netif_set_gso_max_size(netdev, 65536);
2f90b865
AD		 2691 ixgbe_configure_dcb(adapter);
2692 } else {
2693 netif_set_gso_max_size(netdev, 65536);
2694 }
2695#else
2696 netif_set_gso_max_size(netdev, 65536);
2697#endif
9a799d71 2698
eacd73f7
YZ		 2699#ifdef IXGBE_FCOE
2700 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2701 ixgbe_configure_fcoe(adapter);
2702
2703#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2704 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2705 for (i = 0; i < adapter->num_tx_queues; i++)
2706 adapter->tx_ring[i].atr_sample_rate =
2707 adapter->atr_sample_rate;
2708 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2709 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2710 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2711 }
2712
9a799d71
AK		 2713 ixgbe_configure_tx(adapter);
2714 ixgbe_configure_rx(adapter);
2715 for (i = 0; i < adapter->num_rx_queues; i++)
2716 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2717 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2718}
2719
e8e26350
PW		 2720static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2721{
2722 switch (hw->phy.type) {
2723 case ixgbe_phy_sfp_avago:
2724 case ixgbe_phy_sfp_ftl:
2725 case ixgbe_phy_sfp_intel:
2726 case ixgbe_phy_sfp_unknown:
2727 case ixgbe_phy_tw_tyco:
2728 case ixgbe_phy_tw_unknown:
2729 return true;
2730 default:
2731 return false;
2732 }
2733}
2734
0ecc061d 2735/**
e8e26350
PW		 2736 * ixgbe_sfp_link_config - set up SFP+ link
2737 * @adapter: pointer to private adapter struct
2738 **/
2739static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2740{
2741 struct ixgbe_hw *hw = &adapter->hw;
2742
2743 if (hw->phy.multispeed_fiber) {
2744 /*
2745 * In multispeed fiber setups, the device may not have
2746 * had a physical connection when the driver loaded.
2747 * If that's the case, the initial link configuration
2748 * couldn't get the MAC into 10G or 1G mode, so we'll
2749 * never have a link status change interrupt fire.
2750 * We need to try and force an autonegotiation
2751 * session, then bring up link.
2752 */
2753 hw->mac.ops.setup_sfp(hw);
2754 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2755 schedule_work(&adapter->multispeed_fiber_task);
2756 } else {
2757 /*
2758 * Direct Attach Cu and non-multispeed fiber modules
2759 * still need to be configured properly prior to
2760 * attempting link.
2761 */
2762 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2763 schedule_work(&adapter->sfp_config_module_task);
2764 }
2765}
2766
2767/**
2768 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2769 * @hw: pointer to private hardware struct
2770 *
2771 * Returns 0 on success, negative on failure
2772 **/
e8e26350 2773static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2774{
2775 u32 autoneg;
8620a103 2776 bool negotiation, link_up = false;
0ecc061d
PWJ		 2777 u32 ret = IXGBE_ERR_LINK_SETUP;
2778
2779 if (hw->mac.ops.check_link)
2780 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2781
2782 if (ret)
2783 goto link_cfg_out;
2784
2785 if (hw->mac.ops.get_link_capabilities)
8620a103 2786 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2787 if (ret)
2788 goto link_cfg_out;
2789
8620a103
MC		 2790 if (hw->mac.ops.setup_link)
2791 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2792link_cfg_out:
2793 return ret;
2794}
2795
e8e26350
PW		 2796#define IXGBE_MAX_RX_DESC_POLL 10
2797static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2798 int rxr)
2799{
2800 int j = adapter->rx_ring[rxr].reg_idx;
2801 int k;
2802
2803 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2804 if (IXGBE_READ_REG(&adapter->hw,
2805 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2806 break;
2807 else
2808 msleep(1);
2809 }
2810 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2811 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2812 "not set within the polling period\n", rxr);
2813 }
2814 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2815 (adapter->rx_ring[rxr].count - 1));
2816}
2817
9a799d71
AK		 2818static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2819{
2820 struct net_device *netdev = adapter->netdev;
9a799d71 2821 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2822 int i, j = 0;
e8e26350 2823 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2824 int err;
9a799d71 2825 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2826 u32 txdctl, rxdctl, mhadd;
e8e26350 2827 u32 dmatxctl;
021230d4 2828 u32 gpie;
c9205697 2829 u32 ctrl_ext;
9a799d71 2830
5eba3699
AV		 2831 ixgbe_get_hw_control(adapter);
2832
021230d4
AV		 2833 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2834 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2835 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2836 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2837 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2838 } else {
2839 /* MSI only */
021230d4 2840 gpie = 0;
9a799d71 2841 }
1cdd1ec8
GR		 2842 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2843 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
2844 gpie |= IXGBE_GPIE_VTMODE_64;
2845 }
021230d4
AV		 2846 /* XXX: to interrupt immediately for EICS writes, enable this */
2847 /* gpie |= IXGBE_GPIE_EIMEN; */
2848 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2849 }
2850
9b471446
JB		 2851 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2852 /*
2853 * use EIAM to auto-mask when MSI-X interrupt is asserted
2854 * this saves a register write for every interrupt
2855 */
2856 switch (hw->mac.type) {
2857 case ixgbe_mac_82598EB:
2858 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2859 break;
2860 default:
2861 case ixgbe_mac_82599EB:
2862 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2863 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2864 break;
2865 }
2866 } else {
021230d4
AV		 2867 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2868 * specifically only auto mask tx and rx interrupts */
2869 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2870 }
9a799d71 2871
0befdb3e
JB		 2872 /* Enable fan failure interrupt if media type is copper */
2873 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2874 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2875 gpie |= IXGBE_SDP1_GPIEN;
2876 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2877 }
2878
e8e26350
PW		 2879 if (hw->mac.type == ixgbe_mac_82599EB) {
2880 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2881 gpie |= IXGBE_SDP1_GPIEN;
2882 gpie |= IXGBE_SDP2_GPIEN;
2883 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2884 }
2885
63f39bd1
YZ		 2886#ifdef IXGBE_FCOE
2887 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2888 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2889 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2890 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2891
2892#endif /* IXGBE_FCOE */
021230d4 2893 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2894 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2895 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2896 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2897
2898 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2899 }
2900
2901 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2902 j = adapter->tx_ring[i].reg_idx;
2903 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2904 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2905 txdctl |= (8 << 16);
e8e26350
PW		 2906 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2907 }
2908
2909 if (hw->mac.type == ixgbe_mac_82599EB) {
2910 /* DMATXCTL.EN must be set after all Tx queue config is done */
2911 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2912 dmatxctl |= IXGBE_DMATXCTL_TE;
2913 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2914 }
2915 for (i = 0; i < adapter->num_tx_queues; i++) {
2916 j = adapter->tx_ring[i].reg_idx;
2917 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2918 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2919 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1cdd1ec8
GR		 2920 if (hw->mac.type == ixgbe_mac_82599EB) {
2921 int wait_loop = 10;
2922 /* poll for Tx Enable ready */
2923 do {
2924 msleep(1);
2925 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2926 } while (--wait_loop &&
2927 !(txdctl & IXGBE_TXDCTL_ENABLE));
2928 if (!wait_loop)
2929 DPRINTK(DRV, ERR, "Could not enable "
2930 "Tx Queue %d\n", j);
2931 }
9a799d71
AK		 2932 }
2933
e8e26350 2934 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2935 j = adapter->rx_ring[i].reg_idx;
2936 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2937 /* enable PTHRESH=32 descriptors (half the internal cache)
2938 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2939 * this also removes a pesky rx_no_buffer_count increment */
2940 rxdctl |= 0x0020;
9a799d71 2941 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2942 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2943 if (hw->mac.type == ixgbe_mac_82599EB)
2944 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2945 }
2946 /* enable all receives */
2947 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2948 if (hw->mac.type == ixgbe_mac_82598EB)
2949 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2950 else
2951 rxdctl |= IXGBE_RXCTRL_RXEN;
2952 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2953
2954 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2955 ixgbe_configure_msix(adapter);
2956 else
2957 ixgbe_configure_msi_and_legacy(adapter);
2958
2959 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2960 ixgbe_napi_enable_all(adapter);
2961
2962 /* clear any pending interrupts, may auto mask */
2963 IXGBE_READ_REG(hw, IXGBE_EICR);
2964
9a799d71
AK		 2965 ixgbe_irq_enable(adapter);
2966
bf069c97
DS		 2967 /*
2968 * If this adapter has a fan, check to see if we had a failure
2969 * before we enabled the interrupt.
2970 */
2971 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2972 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2973 if (esdp & IXGBE_ESDP_SDP1)
2974 DPRINTK(DRV, CRIT,
2975 "Fan has stopped, replace the adapter\n");
2976 }
2977
e8e26350
PW		 2978 /*
2979 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2980 * arrived before interrupts were enabled but after probe. Such
2981 * devices wouldn't have their type identified yet. We need to
2982 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2983 * If we're not hot-pluggable SFP+, we just need to configure link
2984 * and bring it up.
2985 */
19343de2
DS		 2986 if (hw->phy.type == ixgbe_phy_unknown) {
2987 err = hw->phy.ops.identify(hw);
2988 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2989 /*
2990 * Take the device down and schedule the sfp tasklet
2991 * which will unregister_netdev and log it.
2992 */
19343de2 2993 ixgbe_down(adapter);
5da43c1a 2994 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2995 return err;
2996 }
e8e26350
PW		 2997 }
2998
2999 if (ixgbe_is_sfp(hw)) {
3000 ixgbe_sfp_link_config(adapter);
3001 } else {
3002 err = ixgbe_non_sfp_link_config(hw);
3003 if (err)
3004 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
3005 }
0ecc061d 3006
c4cf55e5
PWJ		 3007 for (i = 0; i < adapter->num_tx_queues; i++)
3008 set_bit(__IXGBE_FDIR_INIT_DONE,
3009 &(adapter->tx_ring[i].reinit_state));
3010
1da100bb
PWJ		 3011 /* enable transmits */
3012 netif_tx_start_all_queues(netdev);
3013
9a799d71
AK		 3014 /* bring the link up in the watchdog, this could race with our first
3015 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3016 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3017 adapter->link_check_timeout = jiffies;
9a799d71 3018 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3019
3020 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3021 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3022 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3023 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3024
9a799d71
AK		 3025 return 0;
3026}
3027
d4f80882
AV		 3028void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3029{
3030 WARN_ON(in_interrupt());
3031 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3032 msleep(1);
3033 ixgbe_down(adapter);
3034 ixgbe_up(adapter);
3035 clear_bit(__IXGBE_RESETTING, &adapter->state);
3036}
3037
9a799d71
AK		 3038int ixgbe_up(struct ixgbe_adapter *adapter)
3039{
3040 /* hardware has been reset, we need to reload some things */
3041 ixgbe_configure(adapter);
3042
3043 return ixgbe_up_complete(adapter);
3044}
3045
3046void ixgbe_reset(struct ixgbe_adapter *adapter)
3047{
c44ade9e 3048 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3049 int err;
3050
3051 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3052 switch (err) {
3053 case 0:
3054 case IXGBE_ERR_SFP_NOT_PRESENT:
3055 break;
3056 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3057 dev_err(&adapter->pdev->dev, "master disable timed out\n");
3058 break;
794caeb2
PWJ		 3059 case IXGBE_ERR_EEPROM_VERSION:
3060 /* We are running on a pre-production device, log a warning */
3061 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
3062 "adapter/LOM. Please be aware there may be issues "
3063 "associated with your hardware. If you are "
3064 "experiencing problems please contact your Intel or "
3065 "hardware representative who provided you with this "
3066 "hardware.\n");
3067 break;
da4dd0f7
PWJ		 3068 default:
3069 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
3070 }
9a799d71
AK		 3071
3072 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3073 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3074 IXGBE_RAH_AV);
9a799d71
AK		 3075}
3076
9a799d71
AK		 3077/**
3078 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3079 * @adapter: board private structure
3080 * @rx_ring: ring to free buffers from
3081 **/
3082static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 3083 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3084{
3085 struct pci_dev *pdev = adapter->pdev;
3086 unsigned long size;
3087 unsigned int i;
3088
3089 /* Free all the Rx ring sk_buffs */
3090
3091 for (i = 0; i < rx_ring->count; i++) {
3092 struct ixgbe_rx_buffer *rx_buffer_info;
3093
3094 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3095 if (rx_buffer_info->dma) {
3096 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 3097 rx_ring->rx_buf_len,
3098 PCI_DMA_FROMDEVICE);
9a799d71
AK		 3099 rx_buffer_info->dma = 0;
3100 }
3101 if (rx_buffer_info->skb) {
f8212f97 3102 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3103 rx_buffer_info->skb = NULL;
f8212f97
AD		 3104 do {
3105 struct sk_buff *this = skb;
3106 skb = skb->prev;
3107 dev_kfree_skb(this);
3108 } while (skb);
9a799d71
AK		 3109 }
3110 if (!rx_buffer_info->page)
3111 continue;
4f57ca6e
JB		 3112 if (rx_buffer_info->page_dma) {
3113 pci_unmap_page(pdev, rx_buffer_info->page_dma,
3114 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
3115 rx_buffer_info->page_dma = 0;
3116 }
9a799d71
AK		 3117 put_page(rx_buffer_info->page);
3118 rx_buffer_info->page = NULL;
762f4c57 3119 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3120 }
3121
3122 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3123 memset(rx_ring->rx_buffer_info, 0, size);
3124
3125 /* Zero out the descriptor ring */
3126 memset(rx_ring->desc, 0, rx_ring->size);
3127
3128 rx_ring->next_to_clean = 0;
3129 rx_ring->next_to_use = 0;
3130
9891ca7c
JB		 3131 if (rx_ring->head)
3132 writel(0, adapter->hw.hw_addr + rx_ring->head);
3133 if (rx_ring->tail)
3134 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3135}
3136
3137/**
3138 * ixgbe_clean_tx_ring - Free Tx Buffers
3139 * @adapter: board private structure
3140 * @tx_ring: ring to be cleaned
3141 **/
3142static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 3143 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3144{
3145 struct ixgbe_tx_buffer *tx_buffer_info;
3146 unsigned long size;
3147 unsigned int i;
3148
3149 /* Free all the Tx ring sk_buffs */
3150
3151 for (i = 0; i < tx_ring->count; i++) {
3152 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3153 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3154 }
3155
3156 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3157 memset(tx_ring->tx_buffer_info, 0, size);
3158
3159 /* Zero out the descriptor ring */
3160 memset(tx_ring->desc, 0, tx_ring->size);
3161
3162 tx_ring->next_to_use = 0;
3163 tx_ring->next_to_clean = 0;
3164
9891ca7c
JB		 3165 if (tx_ring->head)
3166 writel(0, adapter->hw.hw_addr + tx_ring->head);
3167 if (tx_ring->tail)
3168 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3169}
3170
3171/**
021230d4 3172 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3173 * @adapter: board private structure
3174 **/
021230d4 3175static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3176{
3177 int i;
3178
021230d4
AV		 3179 for (i = 0; i < adapter->num_rx_queues; i++)
3180 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3181}
3182
3183/**
021230d4 3184 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3185 * @adapter: board private structure
3186 **/
021230d4 3187static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3188{
3189 int i;
3190
021230d4
AV		 3191 for (i = 0; i < adapter->num_tx_queues; i++)
3192 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3193}
3194
3195void ixgbe_down(struct ixgbe_adapter *adapter)
3196{
3197 struct net_device *netdev = adapter->netdev;
7f821875 3198 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3199 u32 rxctrl;
7f821875
JB		 3200 u32 txdctl;
3201 int i, j;
9a799d71
AK		 3202
3203 /* signal that we are down to the interrupt handler */
3204 set_bit(__IXGBE_DOWN, &adapter->state);
3205
767081ad
GR		 3206 /* disable receive for all VFs and wait one second */
3207 if (adapter->num_vfs) {
3208 for (i = 0 ; i < adapter->num_vfs; i++)
3209 adapter->vfinfo[i].clear_to_send = 0;
3210
3211 /* ping all the active vfs to let them know we are going down */
3212 ixgbe_ping_all_vfs(adapter);
3213 /* Disable all VFTE/VFRE TX/RX */
3214 ixgbe_disable_tx_rx(adapter);
3215 }
3216
9a799d71 3217 /* disable receives */
7f821875
JB		 3218 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3219 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 3220
3221 netif_tx_disable(netdev);
3222
7f821875 3223 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3224 msleep(10);
3225
7f821875
JB		 3226 netif_tx_stop_all_queues(netdev);
3227
9a799d71
AK		 3228 ixgbe_irq_disable(adapter);
3229
021230d4 3230 ixgbe_napi_disable_all(adapter);
7f821875 3231
0a1f87cb
DS		 3232 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3233 del_timer_sync(&adapter->sfp_timer);
9a799d71 3234 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3235 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3236
c4cf55e5
PWJ		 3237 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3238 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3239 cancel_work_sync(&adapter->fdir_reinit_task);
3240
7f821875
JB		 3241 /* disable transmits in the hardware now that interrupts are off */
3242 for (i = 0; i < adapter->num_tx_queues; i++) {
3243 j = adapter->tx_ring[i].reg_idx;
3244 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3245 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3246 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3247 }
88512539
PW		 3248 /* Disable the Tx DMA engine on 82599 */
3249 if (hw->mac.type == ixgbe_mac_82599EB)
3250 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3251 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3252 ~IXGBE_DMATXCTL_TE));
7f821875 3253
9a799d71 3254 netif_carrier_off(netdev);
9a799d71 3255
6f4a0e45
PL		 3256 if (!pci_channel_offline(adapter->pdev))
3257 ixgbe_reset(adapter);
9a799d71
AK		 3258 ixgbe_clean_all_tx_rings(adapter);
3259 ixgbe_clean_all_rx_rings(adapter);
3260
5dd2d332 3261#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3262 /* since we reset the hardware DCA settings were cleared */
e35ec126 3263 ixgbe_setup_dca(adapter);
96b0e0f6 3264#endif
9a799d71
AK		 3265}
3266
9a799d71 3267/**
021230d4
AV		 3268 * ixgbe_poll - NAPI Rx polling callback
3269 * @napi: structure for representing this polling device
3270 * @budget: how many packets driver is allowed to clean
3271 *
3272 * This function is used for legacy and MSI, NAPI mode
9a799d71 3273 **/
021230d4 3274static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3275{
9a1a69ad
JB		 3276 struct ixgbe_q_vector *q_vector =
3277 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3278 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3279 int tx_clean_complete, work_done = 0;
9a799d71 3280
5dd2d332 3281#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 3282 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3283 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3284 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3285 }
3286#endif
3287
fe49f04a 3288 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 3289 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 3290
9a1a69ad 3291 if (!tx_clean_complete)
d2c7ddd6
DM		 3292 work_done = budget;
3293
53e52c72
DM		 3294 /* If budget not fully consumed, exit the polling mode */
3295 if (work_done < budget) {
288379f0 3296 napi_complete(napi);
f7554a2b 3297 if (adapter->rx_itr_setting & 1)
f494e8fa 3298 ixgbe_set_itr(adapter);
d4f80882 3299 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3300 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3301 }
9a799d71
AK		 3302 return work_done;
3303}
3304
3305/**
3306 * ixgbe_tx_timeout - Respond to a Tx Hang
3307 * @netdev: network interface device structure
3308 **/
3309static void ixgbe_tx_timeout(struct net_device *netdev)
3310{
3311 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3312
3313 /* Do the reset outside of interrupt context */
3314 schedule_work(&adapter->reset_task);
3315}
3316
3317static void ixgbe_reset_task(struct work_struct *work)
3318{
3319 struct ixgbe_adapter *adapter;
3320 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3321
2f90b865
AD		 3322 /* If we're already down or resetting, just bail */
3323 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3324 test_bit(__IXGBE_RESETTING, &adapter->state))
3325 return;
3326
9a799d71
AK		 3327 adapter->tx_timeout_count++;
3328
d4f80882 3329 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3330}
3331
bc97114d
PWJ		 3332#ifdef CONFIG_IXGBE_DCB
3333static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3334{
bc97114d 3335 bool ret = false;
0cefafad 3336 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3337
0cefafad
JB		 3338 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3339 return ret;
3340
3341 f->mask = 0x7 << 3;
3342 adapter->num_rx_queues = f->indices;
3343 adapter->num_tx_queues = f->indices;
3344 ret = true;
2f90b865 3345
bc97114d
PWJ		 3346 return ret;
3347}
3348#endif
3349
4df10466
JB		 3350/**
3351 * ixgbe_set_rss_queues: Allocate queues for RSS
3352 * @adapter: board private structure to initialize
3353 *
3354 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3355 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3356 *
3357 **/
bc97114d
PWJ		 3358static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3359{
3360 bool ret = false;
0cefafad 3361 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3362
3363 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3364 f->mask = 0xF;
3365 adapter->num_rx_queues = f->indices;
3366 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3367 ret = true;
3368 } else {
bc97114d 3369 ret = false;
b9804972
JB		 3370 }
3371
bc97114d
PWJ		 3372 return ret;
3373}
3374
c4cf55e5
PWJ		 3375/**
3376 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3377 * @adapter: board private structure to initialize
3378 *
3379 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3380 * to the original CPU that initiated the Tx session. This runs in addition
3381 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3382 * Rx load across CPUs using RSS.
3383 *
3384 **/
3385static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3386{
3387 bool ret = false;
3388 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3389
3390 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3391 f_fdir->mask = 0;
3392
3393 /* Flow Director must have RSS enabled */
3394 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3395 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3396 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3397 adapter->num_tx_queues = f_fdir->indices;
3398 adapter->num_rx_queues = f_fdir->indices;
3399 ret = true;
3400 } else {
3401 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3402 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3403 }
3404 return ret;
3405}
3406
0331a832
YZ		 3407#ifdef IXGBE_FCOE
3408/**
3409 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3410 * @adapter: board private structure to initialize
3411 *
3412 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3413 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3414 * rx queues out of the max number of rx queues, instead, it is used as the
3415 * index of the first rx queue used by FCoE.
3416 *
3417 **/
3418static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3419{
3420 bool ret = false;
3421 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3422
3423 f->indices = min((int)num_online_cpus(), f->indices);
3424 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3425 adapter->num_rx_queues = 1;
3426 adapter->num_tx_queues = 1;
0331a832
YZ		 3427#ifdef CONFIG_IXGBE_DCB
3428 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3429 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3430 ixgbe_set_dcb_queues(adapter);
3431 }
3432#endif
3433 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3434 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3435 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3436 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3437 ixgbe_set_fdir_queues(adapter);
3438 else
3439 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3440 }
3441 /* adding FCoE rx rings to the end */
3442 f->mask = adapter->num_rx_queues;
3443 adapter->num_rx_queues += f->indices;
8de8b2e6 3444 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3445
3446 ret = true;
3447 }
3448
3449 return ret;
3450}
3451
3452#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3453/**
3454 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3455 * @adapter: board private structure to initialize
3456 *
3457 * IOV doesn't actually use anything, so just NAK the
3458 * request for now and let the other queue routines
3459 * figure out what to do.
3460 */
3461static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
3462{
3463 return false;
3464}
3465
4df10466
JB		 3466/*
3467 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3468 * @adapter: board private structure to initialize
3469 *
3470 * This is the top level queue allocation routine. The order here is very
3471 * important, starting with the "most" number of features turned on at once,
3472 * and ending with the smallest set of features. This way large combinations
3473 * can be allocated if they're turned on, and smaller combinations are the
3474 * fallthrough conditions.
3475 *
3476 **/
bc97114d
PWJ		 3477static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3478{
1cdd1ec8
GR		 3479 /* Start with base case */
3480 adapter->num_rx_queues = 1;
3481 adapter->num_tx_queues = 1;
3482 adapter->num_rx_pools = adapter->num_rx_queues;
3483 adapter->num_rx_queues_per_pool = 1;
3484
3485 if (ixgbe_set_sriov_queues(adapter))
3486 return;
3487
0331a832
YZ		 3488#ifdef IXGBE_FCOE
3489 if (ixgbe_set_fcoe_queues(adapter))
3490 goto done;
3491
3492#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3493#ifdef CONFIG_IXGBE_DCB
3494 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3495 goto done;
bc97114d
PWJ		 3496
3497#endif
c4cf55e5
PWJ		 3498 if (ixgbe_set_fdir_queues(adapter))
3499 goto done;
3500
bc97114d 3501 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3502 goto done;
3503
3504 /* fallback to base case */
3505 adapter->num_rx_queues = 1;
3506 adapter->num_tx_queues = 1;
3507
3508done:
3509 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3510 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3511}
3512
021230d4 3513static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3514 int vectors)
021230d4
AV		 3515{
3516 int err, vector_threshold;
3517
3518 /* We'll want at least 3 (vector_threshold):
3519 * 1) TxQ[0] Cleanup
3520 * 2) RxQ[0] Cleanup
3521 * 3) Other (Link Status Change, etc.)
3522 * 4) TCP Timer (optional)
3523 */
3524 vector_threshold = MIN_MSIX_COUNT;
3525
3526 /* The more we get, the more we will assign to Tx/Rx Cleanup
3527 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3528 * Right now, we simply care about how many we'll get; we'll
3529 * set them up later while requesting irq's.
3530 */
3531 while (vectors >= vector_threshold) {
3532 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3533 vectors);
021230d4
AV		 3534 if (!err) /* Success in acquiring all requested vectors. */
3535 break;
3536 else if (err < 0)
3537 vectors = 0; /* Nasty failure, quit now */
3538 else /* err == number of vectors we should try again with */
3539 vectors = err;
3540 }
3541
3542 if (vectors < vector_threshold) {
3543 /* Can't allocate enough MSI-X interrupts? Oh well.
3544 * This just means we'll go with either a single MSI
3545 * vector or fall back to legacy interrupts.
3546 */
3547 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3548 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3549 kfree(adapter->msix_entries);
3550 adapter->msix_entries = NULL;
021230d4
AV		 3551 } else {
3552 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3553 /*
3554 * Adjust for only the vectors we'll use, which is minimum
3555 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3556 * vectors we were allocated.
3557 */
3558 adapter->num_msix_vectors = min(vectors,
3559 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3560 }
3561}
3562
021230d4 3563/**
bc97114d 3564 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3565 * @adapter: board private structure to initialize
3566 *
bc97114d
PWJ		 3567 * Cache the descriptor ring offsets for RSS to the assigned rings.
3568 *
021230d4 3569 **/
bc97114d 3570static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3571{
bc97114d
PWJ		 3572 int i;
3573 bool ret = false;
3574
3575 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3576 for (i = 0; i < adapter->num_rx_queues; i++)
3577 adapter->rx_ring[i].reg_idx = i;
3578 for (i = 0; i < adapter->num_tx_queues; i++)
3579 adapter->tx_ring[i].reg_idx = i;
3580 ret = true;
3581 } else {
3582 ret = false;
3583 }
3584
3585 return ret;
3586}
3587
3588#ifdef CONFIG_IXGBE_DCB
3589/**
3590 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3591 * @adapter: board private structure to initialize
3592 *
3593 * Cache the descriptor ring offsets for DCB to the assigned rings.
3594 *
3595 **/
3596static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3597{
3598 int i;
3599 bool ret = false;
3600 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3601
3602 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3603 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3604 /* the number of queues is assumed to be symmetric */
3605 for (i = 0; i < dcb_i; i++) {
3606 adapter->rx_ring[i].reg_idx = i << 3;
3607 adapter->tx_ring[i].reg_idx = i << 2;
3608 }
bc97114d 3609 ret = true;
e8e26350 3610 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3611 if (dcb_i == 8) {
3612 /*
3613 * Tx TC0 starts at: descriptor queue 0
3614 * Tx TC1 starts at: descriptor queue 32
3615 * Tx TC2 starts at: descriptor queue 64
3616 * Tx TC3 starts at: descriptor queue 80
3617 * Tx TC4 starts at: descriptor queue 96
3618 * Tx TC5 starts at: descriptor queue 104
3619 * Tx TC6 starts at: descriptor queue 112
3620 * Tx TC7 starts at: descriptor queue 120
3621 *
3622 * Rx TC0-TC7 are offset by 16 queues each
3623 */
3624 for (i = 0; i < 3; i++) {
3625 adapter->tx_ring[i].reg_idx = i << 5;
3626 adapter->rx_ring[i].reg_idx = i << 4;
3627 }
3628 for ( ; i < 5; i++) {
3629 adapter->tx_ring[i].reg_idx =
3630 ((i + 2) << 4);
3631 adapter->rx_ring[i].reg_idx = i << 4;
3632 }
3633 for ( ; i < dcb_i; i++) {
3634 adapter->tx_ring[i].reg_idx =
3635 ((i + 8) << 3);
3636 adapter->rx_ring[i].reg_idx = i << 4;
3637 }
3638
3639 ret = true;
3640 } else if (dcb_i == 4) {
3641 /*
3642 * Tx TC0 starts at: descriptor queue 0
3643 * Tx TC1 starts at: descriptor queue 64
3644 * Tx TC2 starts at: descriptor queue 96
3645 * Tx TC3 starts at: descriptor queue 112
3646 *
3647 * Rx TC0-TC3 are offset by 32 queues each
3648 */
3649 adapter->tx_ring[0].reg_idx = 0;
3650 adapter->tx_ring[1].reg_idx = 64;
3651 adapter->tx_ring[2].reg_idx = 96;
3652 adapter->tx_ring[3].reg_idx = 112;
3653 for (i = 0 ; i < dcb_i; i++)
3654 adapter->rx_ring[i].reg_idx = i << 5;
3655
3656 ret = true;
3657 } else {
3658 ret = false;
e8e26350 3659 }
bc97114d
PWJ		 3660 } else {
3661 ret = false;
021230d4 3662 }
bc97114d
PWJ		 3663 } else {
3664 ret = false;
021230d4 3665 }
bc97114d
PWJ		 3666
3667 return ret;
3668}
3669#endif
3670
c4cf55e5
PWJ		 3671/**
3672 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3673 * @adapter: board private structure to initialize
3674 *
3675 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3676 *
3677 **/
3678static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3679{
3680 int i;
3681 bool ret = false;
3682
3683 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3684 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3685 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3686 for (i = 0; i < adapter->num_rx_queues; i++)
3687 adapter->rx_ring[i].reg_idx = i;
3688 for (i = 0; i < adapter->num_tx_queues; i++)
3689 adapter->tx_ring[i].reg_idx = i;
3690 ret = true;
3691 }
3692
3693 return ret;
3694}
3695
0331a832
YZ		 3696#ifdef IXGBE_FCOE
3697/**
3698 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3699 * @adapter: board private structure to initialize
3700 *
3701 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3702 *
3703 */
3704static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3705{
8de8b2e6 3706 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3707 bool ret = false;
3708 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3709
3710 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3711#ifdef CONFIG_IXGBE_DCB
3712 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3713 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3714
0331a832 3715 ixgbe_cache_ring_dcb(adapter);
8de8b2e6
YZ		 3716 /* find out queues in TC for FCoE */
3717 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3718 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3719 /*
3720 * In 82599, the number of Tx queues for each traffic
3721 * class for both 8-TC and 4-TC modes are:
3722 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3723 * 8 TCs: 32 32 16 16 8 8 8 8
3724 * 4 TCs: 64 64 32 32
3725 * We have max 8 queues for FCoE, where 8 the is
3726 * FCoE redirection table size. If TC for FCoE is
3727 * less than or equal to TC3, we have enough queues
3728 * to add max of 8 queues for FCoE, so we start FCoE
3729 * tx descriptor from the next one, i.e., reg_idx + 1.
3730 * If TC for FCoE is above TC3, implying 8 TC mode,
3731 * and we need 8 for FCoE, we have to take all queues
3732 * in that traffic class for FCoE.
3733 */
3734 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3735 fcoe_tx_i--;
0331a832
YZ		 3736 }
3737#endif /* CONFIG_IXGBE_DCB */
3738 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3739 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3740 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3741 ixgbe_cache_ring_fdir(adapter);
3742 else
3743 ixgbe_cache_ring_rss(adapter);
3744
8de8b2e6
YZ		 3745 fcoe_rx_i = f->mask;
3746 fcoe_tx_i = f->mask;
3747 }
3748 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3749 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3750 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
0331a832 3751 }
0331a832
YZ		 3752 ret = true;
3753 }
3754 return ret;
3755}
3756
3757#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 3758/**
3759 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3760 * @adapter: board private structure to initialize
3761 *
3762 * SR-IOV doesn't use any descriptor rings but changes the default if
3763 * no other mapping is used.
3764 *
3765 */
3766static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
3767{
3768 adapter->rx_ring[0].reg_idx = adapter->num_vfs * 2;
3769 adapter->tx_ring[0].reg_idx = adapter->num_vfs * 2;
3770 if (adapter->num_vfs)
3771 return true;
3772 else
3773 return false;
3774}
3775
bc97114d
PWJ		 3776/**
3777 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3778 * @adapter: board private structure to initialize
3779 *
3780 * Once we know the feature-set enabled for the device, we'll cache
3781 * the register offset the descriptor ring is assigned to.
3782 *
3783 * Note, the order the various feature calls is important. It must start with
3784 * the "most" features enabled at the same time, then trickle down to the
3785 * least amount of features turned on at once.
3786 **/
3787static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3788{
3789 /* start with default case */
3790 adapter->rx_ring[0].reg_idx = 0;
3791 adapter->tx_ring[0].reg_idx = 0;
3792
1cdd1ec8
GR		 3793 if (ixgbe_cache_ring_sriov(adapter))
3794 return;
3795
0331a832
YZ		 3796#ifdef IXGBE_FCOE
3797 if (ixgbe_cache_ring_fcoe(adapter))
3798 return;
3799
3800#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3801#ifdef CONFIG_IXGBE_DCB
3802 if (ixgbe_cache_ring_dcb(adapter))
3803 return;
3804
3805#endif
c4cf55e5
PWJ		 3806 if (ixgbe_cache_ring_fdir(adapter))
3807 return;
3808
bc97114d
PWJ		 3809 if (ixgbe_cache_ring_rss(adapter))
3810 return;
021230d4
AV		 3811}
3812
9a799d71
AK		 3813/**
3814 * ixgbe_alloc_queues - Allocate memory for all rings
3815 * @adapter: board private structure to initialize
3816 *
3817 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3818 * number of queues at compile-time. The polling_netdev array is
3819 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3820 **/
2f90b865 3821static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3822{
3823 int i;
3824
3825 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3826 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3827 if (!adapter->tx_ring)
021230d4 3828 goto err_tx_ring_allocation;
9a799d71
AK		 3829
3830 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3831 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3832 if (!adapter->rx_ring)
3833 goto err_rx_ring_allocation;
9a799d71 3834
021230d4 3835 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3836 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3837 adapter->tx_ring[i].queue_index = i;
3838 }
b9804972 3839
9a799d71 3840 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3841 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3842 adapter->rx_ring[i].queue_index = i;
3843 }
3844
3845 ixgbe_cache_ring_register(adapter);
3846
3847 return 0;
3848
3849err_rx_ring_allocation:
3850 kfree(adapter->tx_ring);
3851err_tx_ring_allocation:
3852 return -ENOMEM;
3853}
3854
3855/**
3856 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3857 * @adapter: board private structure to initialize
3858 *
3859 * Attempt to configure the interrupts using the best available
3860 * capabilities of the hardware and the kernel.
3861 **/
feea6a57 3862static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3863{
8be0e467 3864 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3865 int err = 0;
3866 int vector, v_budget;
3867
3868 /*
3869 * It's easy to be greedy for MSI-X vectors, but it really
3870 * doesn't do us much good if we have a lot more vectors
3871 * than CPU's. So let's be conservative and only ask for
342bde1b 3872 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 3873 */
3874 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
342bde1b 3875 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 3876
3877 /*
3878 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3879 * hw.mac->max_msix_vectors vectors. With features
3880 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3881 * descriptor queues supported by our device. Thus, we cap it off in
3882 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3883 */
8be0e467 3884 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3885
3886 /* A failure in MSI-X entry allocation isn't fatal, but it does
3887 * mean we disable MSI-X capabilities of the adapter. */
3888 adapter->msix_entries = kcalloc(v_budget,
b4617240 3889 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3890 if (adapter->msix_entries) {
3891 for (vector = 0; vector < v_budget; vector++)
3892 adapter->msix_entries[vector].entry = vector;
021230d4 3893
7a921c93 3894 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3895
7a921c93
AD		 3896 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3897 goto out;
3898 }
021230d4 3899
7a921c93
AD		 3900 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3901 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3902 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3903 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3904 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 3905 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3906 ixgbe_disable_sriov(adapter);
3907
7a921c93 3908 ixgbe_set_num_queues(adapter);
021230d4 3909
021230d4
AV		 3910 err = pci_enable_msi(adapter->pdev);
3911 if (!err) {
3912 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3913 } else {
3914 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3915 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3916 /* reset err */
3917 err = 0;
3918 }
3919
3920out:
021230d4
AV		 3921 return err;
3922}
3923
7a921c93
AD		 3924/**
3925 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3926 * @adapter: board private structure to initialize
3927 *
3928 * We allocate one q_vector per queue interrupt. If allocation fails we
3929 * return -ENOMEM.
3930 **/
3931static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3932{
3933 int q_idx, num_q_vectors;
3934 struct ixgbe_q_vector *q_vector;
3935 int napi_vectors;
3936 int (*poll)(struct napi_struct *, int);
3937
3938 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3939 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3940 napi_vectors = adapter->num_rx_queues;
91281fd3 3941 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3942 } else {
3943 num_q_vectors = 1;
3944 napi_vectors = 1;
3945 poll = &ixgbe_poll;
3946 }
3947
3948 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3949 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3950 if (!q_vector)
3951 goto err_out;
3952 q_vector->adapter = adapter;
f7554a2b
NS		 3953 if (q_vector->txr_count && !q_vector->rxr_count)
3954 q_vector->eitr = adapter->tx_eitr_param;
3955 else
3956 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 3957 q_vector->v_idx = q_idx;
91281fd3 3958 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3959 adapter->q_vector[q_idx] = q_vector;
3960 }
3961
3962 return 0;
3963
3964err_out:
3965 while (q_idx) {
3966 q_idx--;
3967 q_vector = adapter->q_vector[q_idx];
3968 netif_napi_del(&q_vector->napi);
3969 kfree(q_vector);
3970 adapter->q_vector[q_idx] = NULL;
3971 }
3972 return -ENOMEM;
3973}
3974
3975/**
3976 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3977 * @adapter: board private structure to initialize
3978 *
3979 * This function frees the memory allocated to the q_vectors. In addition if
3980 * NAPI is enabled it will delete any references to the NAPI struct prior
3981 * to freeing the q_vector.
3982 **/
3983static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3984{
3985 int q_idx, num_q_vectors;
7a921c93 3986
91281fd3 3987 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3988 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3989 else
7a921c93 3990 num_q_vectors = 1;
7a921c93
AD		 3991
3992 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3993 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3994 adapter->q_vector[q_idx] = NULL;
91281fd3 3995 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3996 kfree(q_vector);
3997 }
3998}
3999
7b25cdba 4000static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4001{
4002 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4003 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4004 pci_disable_msix(adapter->pdev);
4005 kfree(adapter->msix_entries);
4006 adapter->msix_entries = NULL;
4007 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4008 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4009 pci_disable_msi(adapter->pdev);
4010 }
4011 return;
4012}
4013
4014/**
4015 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4016 * @adapter: board private structure to initialize
4017 *
4018 * We determine which interrupt scheme to use based on...
4019 * - Kernel support (MSI, MSI-X)
4020 * - which can be user-defined (via MODULE_PARAM)
4021 * - Hardware queue count (num_*_queues)
4022 * - defined by miscellaneous hardware support/features (RSS, etc.)
4023 **/
2f90b865 4024int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4025{
4026 int err;
4027
4028 /* Number of supported queues */
4029 ixgbe_set_num_queues(adapter);
4030
021230d4
AV		 4031 err = ixgbe_set_interrupt_capability(adapter);
4032 if (err) {
4033 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
4034 goto err_set_interrupt;
9a799d71
AK		 4035 }
4036
7a921c93
AD		 4037 err = ixgbe_alloc_q_vectors(adapter);
4038 if (err) {
4039 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
4040 "vectors\n");
4041 goto err_alloc_q_vectors;
4042 }
4043
4044 err = ixgbe_alloc_queues(adapter);
4045 if (err) {
4046 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
4047 goto err_alloc_queues;
4048 }
4049
021230d4 4050 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 4051 "Tx Queue count = %u\n",
4052 (adapter->num_rx_queues > 1) ? "Enabled" :
4053 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4054
4055 set_bit(__IXGBE_DOWN, &adapter->state);
4056
9a799d71 4057 return 0;
021230d4 4058
7a921c93
AD		 4059err_alloc_queues:
4060 ixgbe_free_q_vectors(adapter);
4061err_alloc_q_vectors:
4062 ixgbe_reset_interrupt_capability(adapter);
021230d4 4063err_set_interrupt:
7a921c93
AD		 4064 return err;
4065}
4066
4067/**
4068 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4069 * @adapter: board private structure to clear interrupt scheme on
4070 *
4071 * We go through and clear interrupt specific resources and reset the structure
4072 * to pre-load conditions
4073 **/
4074void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4075{
021230d4
AV		 4076 kfree(adapter->tx_ring);
4077 kfree(adapter->rx_ring);
7a921c93
AD		 4078 adapter->tx_ring = NULL;
4079 adapter->rx_ring = NULL;
4080
4081 ixgbe_free_q_vectors(adapter);
4082 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4083}
4084
c4900be0
DS		 4085/**
4086 * ixgbe_sfp_timer - worker thread to find a missing module
4087 * @data: pointer to our adapter struct
4088 **/
4089static void ixgbe_sfp_timer(unsigned long data)
4090{
4091 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4092
4df10466
JB		 4093 /*
4094 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4095 * delays that sfp+ detection requires
4096 */
4097 schedule_work(&adapter->sfp_task);
4098}
4099
4100/**
4101 * ixgbe_sfp_task - worker thread to find a missing module
4102 * @work: pointer to work_struct containing our data
4103 **/
4104static void ixgbe_sfp_task(struct work_struct *work)
4105{
4106 struct ixgbe_adapter *adapter = container_of(work,
4107 struct ixgbe_adapter,
4108 sfp_task);
4109 struct ixgbe_hw *hw = &adapter->hw;
4110
4111 if ((hw->phy.type == ixgbe_phy_nl) &&
4112 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4113 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4114 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4115 goto reschedule;
4116 ret = hw->phy.ops.reset(hw);
4117 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4118 dev_err(&adapter->pdev->dev, "failed to initialize "
4119 "because an unsupported SFP+ module type "
4120 "was detected.\n"
4121 "Reload the driver after installing a "
4122 "supported module.\n");
c4900be0
DS		 4123 unregister_netdev(adapter->netdev);
4124 } else {
4125 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
4126 hw->phy.sfp_type);
4127 }
4128 /* don't need this routine any more */
4129 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4130 }
4131 return;
4132reschedule:
4133 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4134 mod_timer(&adapter->sfp_timer,
4135 round_jiffies(jiffies + (2 * HZ)));
4136}
4137
9a799d71
AK		 4138/**
4139 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4140 * @adapter: board private structure to initialize
4141 *
4142 * ixgbe_sw_init initializes the Adapter private data structure.
4143 * Fields are initialized based on PCI device information and
4144 * OS network device settings (MTU size).
4145 **/
4146static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4147{
4148 struct ixgbe_hw *hw = &adapter->hw;
4149 struct pci_dev *pdev = adapter->pdev;
021230d4 4150 unsigned int rss;
7a6b6f51 4151#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4152 int j;
4153 struct tc_configuration *tc;
4154#endif
021230d4 4155
c44ade9e
JB		 4156 /* PCI config space info */
4157
4158 hw->vendor_id = pdev->vendor;
4159 hw->device_id = pdev->device;
4160 hw->revision_id = pdev->revision;
4161 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4162 hw->subsystem_device_id = pdev->subsystem_device;
4163
021230d4
AV		 4164 /* Set capability flags */
4165 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4166 adapter->ring_feature[RING_F_RSS].indices = rss;
4167 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4168 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4169 if (hw->mac.type == ixgbe_mac_82598EB) {
4170 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4171 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4172 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4173 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4174 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4175 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4176 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 4177 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4178 adapter->ring_feature[RING_F_FDIR].indices =
4179 IXGBE_MAX_FDIR_INDICES;
4180 adapter->atr_sample_rate = 20;
4181 adapter->fdir_pballoc = 0;
eacd73f7 4182#ifdef IXGBE_FCOE
0d551589
YZ		 4183 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4184 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4185 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4186#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4187 /* Default traffic class to use for FCoE */
4188 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
61a0f421 4189#endif
eacd73f7 4190#endif /* IXGBE_FCOE */
f8212f97 4191 }
2f90b865 4192
7a6b6f51 4193#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4194 /* Configure DCB traffic classes */
4195 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4196 tc = &adapter->dcb_cfg.tc_config[j];
4197 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4198 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4199 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4200 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4201 tc->dcb_pfc = pfc_disabled;
4202 }
4203 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4204 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4205 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4206 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4207 adapter->dcb_cfg.round_robin_enable = false;
4208 adapter->dcb_set_bitmap = 0x00;
4209 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4210 adapter->ring_feature[RING_F_DCB].indices);
4211
4212#endif
9a799d71
AK		 4213
4214 /* default flow control settings */
cd7664f6 4215 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4216 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4217#ifdef CONFIG_DCB
4218 adapter->last_lfc_mode = hw->fc.current_mode;
4219#endif
2b9ade93
JB		 4220 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4221 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4222 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4223 hw->fc.send_xon = true;
71fd570b 4224 hw->fc.disable_fc_autoneg = false;
9a799d71 4225
30efa5a3 4226 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4227 adapter->rx_itr_setting = 1;
4228 adapter->rx_eitr_param = 20000;
4229 adapter->tx_itr_setting = 1;
4230 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4231
4232 /* set defaults for eitr in MegaBytes */
4233 adapter->eitr_low = 10;
4234 adapter->eitr_high = 20;
4235
4236 /* set default ring sizes */
4237 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4238 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4239
9a799d71 4240 /* initialize eeprom parameters */
c44ade9e 4241 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 4242 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4243 return -EIO;
4244 }
4245
021230d4 4246 /* enable rx csum by default */
9a799d71
AK		 4247 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4248
9a799d71
AK		 4249 set_bit(__IXGBE_DOWN, &adapter->state);
4250
4251 return 0;
4252}
4253
4254/**
4255 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4256 * @adapter: board private structure
3a581073 4257 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4258 *
4259 * Return 0 on success, negative on failure
4260 **/
4261int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 4262 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4263{
4264 struct pci_dev *pdev = adapter->pdev;
4265 int size;
4266
3a581073
JB		 4267 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4268 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4269 if (!tx_ring->tx_buffer_info)
4270 goto err;
3a581073 4271 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4272
4273 /* round up to nearest 4K */
12207e49 4274 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4275 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4276
3a581073
JB		 4277 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4278 &tx_ring->dma);
e01c31a5
JB		 4279 if (!tx_ring->desc)
4280 goto err;
9a799d71 4281
3a581073
JB		 4282 tx_ring->next_to_use = 0;
4283 tx_ring->next_to_clean = 0;
4284 tx_ring->work_limit = tx_ring->count;
9a799d71 4285 return 0;
e01c31a5
JB		 4286
4287err:
4288 vfree(tx_ring->tx_buffer_info);
4289 tx_ring->tx_buffer_info = NULL;
4290 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4291 "descriptor ring\n");
4292 return -ENOMEM;
9a799d71
AK		 4293}
4294
69888674
AD		 4295/**
4296 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4297 * @adapter: board private structure
4298 *
4299 * If this function returns with an error, then it's possible one or
4300 * more of the rings is populated (while the rest are not). It is the
4301 * callers duty to clean those orphaned rings.
4302 *
4303 * Return 0 on success, negative on failure
4304 **/
4305static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4306{
4307 int i, err = 0;
4308
4309 for (i = 0; i < adapter->num_tx_queues; i++) {
4310 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4311 if (!err)
4312 continue;
4313 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4314 break;
4315 }
4316
4317 return err;
4318}
4319
9a799d71
AK		 4320/**
4321 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4322 * @adapter: board private structure
3a581073 4323 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4324 *
4325 * Returns 0 on success, negative on failure
4326 **/
4327int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4328 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4329{
4330 struct pci_dev *pdev = adapter->pdev;
021230d4 4331 int size;
9a799d71 4332
3a581073
JB		 4333 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4334 rx_ring->rx_buffer_info = vmalloc(size);
4335 if (!rx_ring->rx_buffer_info) {
9a799d71 4336 DPRINTK(PROBE, ERR,
b4617240 4337 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4338 goto alloc_failed;
9a799d71 4339 }
3a581073 4340 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4341
9a799d71 4342 /* Round up to nearest 4K */
3a581073
JB		 4343 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4344 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4345
3a581073 4346 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4347
3a581073 4348 if (!rx_ring->desc) {
9a799d71 4349 DPRINTK(PROBE, ERR,
b4617240 4350 "Memory allocation failed for the rx desc ring\n");
3a581073 4351 vfree(rx_ring->rx_buffer_info);
177db6ff 4352 goto alloc_failed;
9a799d71
AK		 4353 }
4354
3a581073
JB		 4355 rx_ring->next_to_clean = 0;
4356 rx_ring->next_to_use = 0;
9a799d71
AK		 4357
4358 return 0;
177db6ff
MC		 4359
4360alloc_failed:
177db6ff 4361 return -ENOMEM;
9a799d71
AK		 4362}
4363
69888674
AD		 4364/**
4365 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4366 * @adapter: board private structure
4367 *
4368 * If this function returns with an error, then it's possible one or
4369 * more of the rings is populated (while the rest are not). It is the
4370 * callers duty to clean those orphaned rings.
4371 *
4372 * Return 0 on success, negative on failure
4373 **/
4374
4375static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4376{
4377 int i, err = 0;
4378
4379 for (i = 0; i < adapter->num_rx_queues; i++) {
4380 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4381 if (!err)
4382 continue;
4383 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4384 break;
4385 }
4386
4387 return err;
4388}
4389
9a799d71
AK		 4390/**
4391 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4392 * @adapter: board private structure
4393 * @tx_ring: Tx descriptor ring for a specific queue
4394 *
4395 * Free all transmit software resources
4396 **/
c431f97e
JB		 4397void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4398 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4399{
4400 struct pci_dev *pdev = adapter->pdev;
4401
4402 ixgbe_clean_tx_ring(adapter, tx_ring);
4403
4404 vfree(tx_ring->tx_buffer_info);
4405 tx_ring->tx_buffer_info = NULL;
4406
4407 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4408
4409 tx_ring->desc = NULL;
4410}
4411
4412/**
4413 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4414 * @adapter: board private structure
4415 *
4416 * Free all transmit software resources
4417 **/
4418static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4419{
4420 int i;
4421
4422 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4423 if (adapter->tx_ring[i].desc)
4424 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4425}
4426
4427/**
b4617240 4428 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4429 * @adapter: board private structure
4430 * @rx_ring: ring to clean the resources from
4431 *
4432 * Free all receive software resources
4433 **/
c431f97e
JB		 4434void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4435 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4436{
4437 struct pci_dev *pdev = adapter->pdev;
4438
4439 ixgbe_clean_rx_ring(adapter, rx_ring);
4440
4441 vfree(rx_ring->rx_buffer_info);
4442 rx_ring->rx_buffer_info = NULL;
4443
4444 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4445
4446 rx_ring->desc = NULL;
4447}
4448
4449/**
4450 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4451 * @adapter: board private structure
4452 *
4453 * Free all receive software resources
4454 **/
4455static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4456{
4457 int i;
4458
4459 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4460 if (adapter->rx_ring[i].desc)
4461 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4462}
4463
9a799d71
AK		 4464/**
4465 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4466 * @netdev: network interface device structure
4467 * @new_mtu: new value for maximum frame size
4468 *
4469 * Returns 0 on success, negative on failure
4470 **/
4471static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4472{
4473 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4474 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4475
42c783c5
JB		 4476 /* MTU < 68 is an error and causes problems on some kernels */
4477 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4478 return -EINVAL;
4479
021230d4 4480 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4481 netdev->mtu, new_mtu);
021230d4 4482 /* must set new MTU before calling down or up */
9a799d71
AK		 4483 netdev->mtu = new_mtu;
4484
d4f80882
AV		 4485 if (netif_running(netdev))
4486 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4487
4488 return 0;
4489}
4490
4491/**
4492 * ixgbe_open - Called when a network interface is made active
4493 * @netdev: network interface device structure
4494 *
4495 * Returns 0 on success, negative value on failure
4496 *
4497 * The open entry point is called when a network interface is made
4498 * active by the system (IFF_UP). At this point all resources needed
4499 * for transmit and receive operations are allocated, the interrupt
4500 * handler is registered with the OS, the watchdog timer is started,
4501 * and the stack is notified that the interface is ready.
4502 **/
4503static int ixgbe_open(struct net_device *netdev)
4504{
4505 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4506 int err;
4bebfaa5
AK		 4507
4508 /* disallow open during test */
4509 if (test_bit(__IXGBE_TESTING, &adapter->state))
4510 return -EBUSY;
9a799d71 4511
54386467
JB		 4512 netif_carrier_off(netdev);
4513
9a799d71
AK		 4514 /* allocate transmit descriptors */
4515 err = ixgbe_setup_all_tx_resources(adapter);
4516 if (err)
4517 goto err_setup_tx;
4518
9a799d71
AK		 4519 /* allocate receive descriptors */
4520 err = ixgbe_setup_all_rx_resources(adapter);
4521 if (err)
4522 goto err_setup_rx;
4523
4524 ixgbe_configure(adapter);
4525
021230d4 4526 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4527 if (err)
4528 goto err_req_irq;
4529
9a799d71
AK		 4530 err = ixgbe_up_complete(adapter);
4531 if (err)
4532 goto err_up;
4533
d55b53ff
JK		 4534 netif_tx_start_all_queues(netdev);
4535
9a799d71
AK		 4536 return 0;
4537
4538err_up:
5eba3699 4539 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4540 ixgbe_free_irq(adapter);
4541err_req_irq:
9a799d71 4542err_setup_rx:
a20a1199 4543 ixgbe_free_all_rx_resources(adapter);
9a799d71 4544err_setup_tx:
a20a1199 4545 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4546 ixgbe_reset(adapter);
4547
4548 return err;
4549}
4550
4551/**
4552 * ixgbe_close - Disables a network interface
4553 * @netdev: network interface device structure
4554 *
4555 * Returns 0, this is not allowed to fail
4556 *
4557 * The close entry point is called when an interface is de-activated
4558 * by the OS. The hardware is still under the drivers control, but
4559 * needs to be disabled. A global MAC reset is issued to stop the
4560 * hardware, and all transmit and receive resources are freed.
4561 **/
4562static int ixgbe_close(struct net_device *netdev)
4563{
4564 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4565
4566 ixgbe_down(adapter);
4567 ixgbe_free_irq(adapter);
4568
4569 ixgbe_free_all_tx_resources(adapter);
4570 ixgbe_free_all_rx_resources(adapter);
4571
5eba3699 4572 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4573
4574 return 0;
4575}
4576
b3c8b4ba
AD		 4577#ifdef CONFIG_PM
4578static int ixgbe_resume(struct pci_dev *pdev)
4579{
4580 struct net_device *netdev = pci_get_drvdata(pdev);
4581 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4582 u32 err;
4583
4584 pci_set_power_state(pdev, PCI_D0);
4585 pci_restore_state(pdev);
656ab817
DS		 4586 /*
4587 * pci_restore_state clears dev->state_saved so call
4588 * pci_save_state to restore it.
4589 */
4590 pci_save_state(pdev);
9ce77666 4591
4592 err = pci_enable_device_mem(pdev);
b3c8b4ba 4593 if (err) {
69888674 4594 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4595 "suspend\n");
4596 return err;
4597 }
4598 pci_set_master(pdev);
4599
dd4d8ca6 4600 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4601
4602 err = ixgbe_init_interrupt_scheme(adapter);
4603 if (err) {
4604 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4605 "device\n");
4606 return err;
4607 }
4608
b3c8b4ba
AD		 4609 ixgbe_reset(adapter);
4610
495dce12
WJP		 4611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4612
b3c8b4ba
AD		 4613 if (netif_running(netdev)) {
4614 err = ixgbe_open(adapter->netdev);
4615 if (err)
4616 return err;
4617 }
4618
4619 netif_device_attach(netdev);
4620
4621 return 0;
4622}
b3c8b4ba 4623#endif /* CONFIG_PM */
9d8d05ae
RW		 4624
4625static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4626{
4627 struct net_device *netdev = pci_get_drvdata(pdev);
4628 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4629 struct ixgbe_hw *hw = &adapter->hw;
4630 u32 ctrl, fctrl;
4631 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4632#ifdef CONFIG_PM
4633 int retval = 0;
4634#endif
4635
4636 netif_device_detach(netdev);
4637
4638 if (netif_running(netdev)) {
4639 ixgbe_down(adapter);
4640 ixgbe_free_irq(adapter);
4641 ixgbe_free_all_tx_resources(adapter);
4642 ixgbe_free_all_rx_resources(adapter);
4643 }
7a921c93 4644 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4645
4646#ifdef CONFIG_PM
4647 retval = pci_save_state(pdev);
4648 if (retval)
4649 return retval;
4df10466 4650
b3c8b4ba 4651#endif
e8e26350
PW		 4652 if (wufc) {
4653 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4654
e8e26350
PW		 4655 /* turn on all-multi mode if wake on multicast is enabled */
4656 if (wufc & IXGBE_WUFC_MC) {
4657 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4658 fctrl |= IXGBE_FCTRL_MPE;
4659 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4660 }
4661
4662 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4663 ctrl |= IXGBE_CTRL_GIO_DIS;
4664 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4665
4666 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4667 } else {
4668 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4669 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4670 }
4671
dd4d8ca6
DS		 4672 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4673 pci_wake_from_d3(pdev, true);
4674 else
4675 pci_wake_from_d3(pdev, false);
b3c8b4ba 4676
9d8d05ae
RW		 4677 *enable_wake = !!wufc;
4678
b3c8b4ba
AD		 4679 ixgbe_release_hw_control(adapter);
4680
4681 pci_disable_device(pdev);
4682
9d8d05ae
RW		 4683 return 0;
4684}
4685
4686#ifdef CONFIG_PM
4687static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4688{
4689 int retval;
4690 bool wake;
4691
4692 retval = __ixgbe_shutdown(pdev, &wake);
4693 if (retval)
4694 return retval;
4695
4696 if (wake) {
4697 pci_prepare_to_sleep(pdev);
4698 } else {
4699 pci_wake_from_d3(pdev, false);
4700 pci_set_power_state(pdev, PCI_D3hot);
4701 }
b3c8b4ba
AD		 4702
4703 return 0;
4704}
9d8d05ae 4705#endif /* CONFIG_PM */
b3c8b4ba
AD		 4706
4707static void ixgbe_shutdown(struct pci_dev *pdev)
4708{
9d8d05ae
RW		 4709 bool wake;
4710
4711 __ixgbe_shutdown(pdev, &wake);
4712
4713 if (system_state == SYSTEM_POWER_OFF) {
4714 pci_wake_from_d3(pdev, wake);
4715 pci_set_power_state(pdev, PCI_D3hot);
4716 }
b3c8b4ba
AD		 4717}
4718
9a799d71
AK		 4719/**
4720 * ixgbe_update_stats - Update the board statistics counters.
4721 * @adapter: board private structure
4722 **/
4723void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4724{
2d86f139 4725 struct net_device *netdev = adapter->netdev;
9a799d71 4726 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4727 u64 total_mpc = 0;
4728 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 4729 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 4730
94b982b2 4731 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 4732 u64 rsc_count = 0;
94b982b2 4733 u64 rsc_flush = 0;
d51019a4
PW		 4734 for (i = 0; i < 16; i++)
4735 adapter->hw_rx_no_dma_resources +=
4736 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 4737 for (i = 0; i < adapter->num_rx_queues; i++) {
f8212f97 4738 rsc_count += adapter->rx_ring[i].rsc_count;
94b982b2
MC		 4739 rsc_flush += adapter->rx_ring[i].rsc_flush;
4740 }
4741 adapter->rsc_total_count = rsc_count;
4742 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 4743 }
4744
7ca3bc58
JB		 4745 /* gather some stats to the adapter struct that are per queue */
4746 for (i = 0; i < adapter->num_tx_queues; i++)
eb985f09
MC		 4747 restart_queue += adapter->tx_ring[i].restart_queue;
4748 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 4749
4750 for (i = 0; i < adapter->num_rx_queues; i++)
eb985f09
MC		 4751 non_eop_descs += adapter->rx_ring[i].non_eop_descs;
4752 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 4753
9a799d71 4754 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4755 for (i = 0; i < 8; i++) {
4756 /* for packet buffers not used, the register should read 0 */
4757 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4758 missed_rx += mpc;
4759 adapter->stats.mpc[i] += mpc;
4760 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4761 if (hw->mac.type == ixgbe_mac_82598EB)
4762 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4763 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4764 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4765 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4766 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4767 if (hw->mac.type == ixgbe_mac_82599EB) {
4768 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4769 IXGBE_PXONRXCNT(i));
4770 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4771 IXGBE_PXOFFRXCNT(i));
4772 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4773 } else {
4774 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4775 IXGBE_PXONRXC(i));
4776 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4777 IXGBE_PXOFFRXC(i));
4778 }
2f90b865
AD		 4779 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4780 IXGBE_PXONTXC(i));
2f90b865 4781 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4782 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4783 }
4784 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4785 /* work around hardware counting issue */
4786 adapter->stats.gprc -= missed_rx;
4787
4788 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4789 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4790 u64 tmp;
e8e26350 4791 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4792 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4793 adapter->stats.gorc += (tmp << 32);
e8e26350 4794 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4795 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4796 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4797 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4798 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4799 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4800 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4801 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4802 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4803#ifdef IXGBE_FCOE
4804 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4805 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4806 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4807 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4808 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4809 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4810#endif /* IXGBE_FCOE */
e8e26350
PW		 4811 } else {
4812 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4813 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4814 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4815 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4816 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4817 }
9a799d71
AK		 4818 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4819 adapter->stats.bprc += bprc;
4820 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4821 if (hw->mac.type == ixgbe_mac_82598EB)
4822 adapter->stats.mprc -= bprc;
9a799d71
AK		 4823 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4824 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4825 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4826 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4827 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4828 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4829 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4830 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4831 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4832 adapter->stats.lxontxc += lxon;
4833 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4834 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4835 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4836 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4837 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4838 /*
4839 * 82598 errata - tx of flow control packets is included in tx counters
4840 */
4841 xon_off_tot = lxon + lxoff;
4842 adapter->stats.gptc -= xon_off_tot;
4843 adapter->stats.mptc -= xon_off_tot;
4844 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4845 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4846 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4847 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4848 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4849 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4850 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4851 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4852 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4853 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4854 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4855 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4856 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4857
4858 /* Fill out the OS statistics structure */
2d86f139 4859 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 4860
4861 /* Rx Errors */
2d86f139 4862 netdev->stats.rx_errors = adapter->stats.crcerrs +
b4617240 4863 adapter->stats.rlec;
2d86f139
AK		 4864 netdev->stats.rx_dropped = 0;
4865 netdev->stats.rx_length_errors = adapter->stats.rlec;
4866 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4867 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4868}
4869
4870/**
4871 * ixgbe_watchdog - Timer Call-back
4872 * @data: pointer to adapter cast into an unsigned long
4873 **/
4874static void ixgbe_watchdog(unsigned long data)
4875{
4876 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4877 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4878 u64 eics = 0;
4879 int i;
cf8280ee 4880
fe49f04a
AD		 4881 /*
4882 * Do the watchdog outside of interrupt context due to the lovely
4883 * delays that some of the newer hardware requires
4884 */
22d5a71b 4885
fe49f04a
AD		 4886 if (test_bit(__IXGBE_DOWN, &adapter->state))
4887 goto watchdog_short_circuit;
22d5a71b 4888
fe49f04a
AD		 4889 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4890 /*
4891 * for legacy and MSI interrupts don't set any bits
4892 * that are enabled for EIAM, because this operation
4893 * would set *both* EIMS and EICS for any bit in EIAM
4894 */
4895 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4896 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4897 goto watchdog_reschedule;
4898 }
4899
4900 /* get one bit for every active tx/rx interrupt vector */
4901 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4902 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4903 if (qv->rxr_count || qv->txr_count)
4904 eics |= ((u64)1 << i);
cf8280ee 4905 }
9a799d71 4906
fe49f04a
AD		 4907 /* Cause software interrupt to ensure rx rings are cleaned */
4908 ixgbe_irq_rearm_queues(adapter, eics);
4909
4910watchdog_reschedule:
4911 /* Reset the timer */
4912 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4913
4914watchdog_short_circuit:
cf8280ee
JB		 4915 schedule_work(&adapter->watchdog_task);
4916}
4917
e8e26350
PW		 4918/**
4919 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4920 * @work: pointer to work_struct containing our data
4921 **/
4922static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4923{
4924 struct ixgbe_adapter *adapter = container_of(work,
4925 struct ixgbe_adapter,
4926 multispeed_fiber_task);
4927 struct ixgbe_hw *hw = &adapter->hw;
4928 u32 autoneg;
8620a103 4929 bool negotiation;
e8e26350
PW		 4930
4931 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4932 autoneg = hw->phy.autoneg_advertised;
4933 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 4934 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4935 if (hw->mac.ops.setup_link)
4936 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 4937 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4938 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4939}
4940
4941/**
4942 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4943 * @work: pointer to work_struct containing our data
4944 **/
4945static void ixgbe_sfp_config_module_task(struct work_struct *work)
4946{
4947 struct ixgbe_adapter *adapter = container_of(work,
4948 struct ixgbe_adapter,
4949 sfp_config_module_task);
4950 struct ixgbe_hw *hw = &adapter->hw;
4951 u32 err;
4952
4953 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4954
4955 /* Time for electrical oscillations to settle down */
4956 msleep(100);
e8e26350 4957 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4958
e8e26350 4959 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4960 dev_err(&adapter->pdev->dev, "failed to initialize because "
4961 "an unsupported SFP+ module type was detected.\n"
4962 "Reload the driver after installing a supported "
4963 "module.\n");
63d6e1d8 4964 unregister_netdev(adapter->netdev);
e8e26350
PW		 4965 return;
4966 }
4967 hw->mac.ops.setup_sfp(hw);
4968
8d1c3c07 4969 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4970 /* This will also work for DA Twinax connections */
4971 schedule_work(&adapter->multispeed_fiber_task);
4972 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4973}
4974
c4cf55e5
PWJ		 4975/**
4976 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4977 * @work: pointer to work_struct containing our data
4978 **/
4979static void ixgbe_fdir_reinit_task(struct work_struct *work)
4980{
4981 struct ixgbe_adapter *adapter = container_of(work,
4982 struct ixgbe_adapter,
4983 fdir_reinit_task);
4984 struct ixgbe_hw *hw = &adapter->hw;
4985 int i;
4986
4987 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4988 for (i = 0; i < adapter->num_tx_queues; i++)
4989 set_bit(__IXGBE_FDIR_INIT_DONE,
4990 &(adapter->tx_ring[i].reinit_state));
4991 } else {
4992 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4993 "ignored adding FDIR ATR filters \n");
4994 }
4995 /* Done FDIR Re-initialization, enable transmits */
4996 netif_tx_start_all_queues(adapter->netdev);
4997}
4998
10eec955
JF		 4999static DEFINE_MUTEX(ixgbe_watchdog_lock);
5000
cf8280ee 5001/**
69888674
AD		 5002 * ixgbe_watchdog_task - worker thread to bring link up
5003 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5004 **/
5005static void ixgbe_watchdog_task(struct work_struct *work)
5006{
5007 struct ixgbe_adapter *adapter = container_of(work,
5008 struct ixgbe_adapter,
5009 watchdog_task);
5010 struct net_device *netdev = adapter->netdev;
5011 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5012 u32 link_speed;
5013 bool link_up;
bc59fcda
NS		 5014 int i;
5015 struct ixgbe_ring *tx_ring;
5016 int some_tx_pending = 0;
cf8280ee 5017
10eec955
JF		 5018 mutex_lock(&ixgbe_watchdog_lock);
5019
5020 link_up = adapter->link_up;
5021 link_speed = adapter->link_speed;
cf8280ee
JB		 5022
5023 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5024 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5025 if (link_up) {
5026#ifdef CONFIG_DCB
5027 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5028 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5029 hw->mac.ops.fc_enable(hw, i);
264857b8 5030 } else {
620fa036 5031 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5032 }
5033#else
620fa036 5034 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5035#endif
5036 }
5037
cf8280ee
JB		 5038 if (link_up ||
5039 time_after(jiffies, (adapter->link_check_timeout +
5040 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5041 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5042 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5043 }
5044 adapter->link_up = link_up;
5045 adapter->link_speed = link_speed;
5046 }
9a799d71
AK		 5047
5048 if (link_up) {
5049 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5050 bool flow_rx, flow_tx;
5051
5052 if (hw->mac.type == ixgbe_mac_82599EB) {
5053 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5054 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5055 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5056 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5057 } else {
5058 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5059 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5060 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5061 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5062 }
5063
a46e534b
JK		 5064 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
5065 "Flow Control: %s\n",
5066 netdev->name,
5067 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5068 "10 Gbps" :
5069 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5070 "1 Gbps" : "unknown speed")),
e8e26350
PW		 5071 ((flow_rx && flow_tx) ? "RX/TX" :
5072 (flow_rx ? "RX" :
5073 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5074
5075 netif_carrier_on(netdev);
9a799d71
AK		 5076 } else {
5077 /* Force detection of hung controller */
5078 adapter->detect_tx_hung = true;
5079 }
5080 } else {
cf8280ee
JB		 5081 adapter->link_up = false;
5082 adapter->link_speed = 0;
9a799d71 5083 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 5084 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
5085 netdev->name);
9a799d71 5086 netif_carrier_off(netdev);
9a799d71
AK		 5087 }
5088 }
5089
bc59fcda
NS		 5090 if (!netif_carrier_ok(netdev)) {
5091 for (i = 0; i < adapter->num_tx_queues; i++) {
5092 tx_ring = &adapter->tx_ring[i];
5093 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5094 some_tx_pending = 1;
5095 break;
5096 }
5097 }
5098
5099 if (some_tx_pending) {
5100 /* We've lost link, so the controller stops DMA,
5101 * but we've got queued Tx work that's never going
5102 * to get done, so reset controller to flush Tx.
5103 * (Do the reset outside of interrupt context).
5104 */
5105 schedule_work(&adapter->reset_task);
5106 }
5107 }
5108
9a799d71 5109 ixgbe_update_stats(adapter);
10eec955 5110 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5111}
5112
9a799d71 5113static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 5114 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5115 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5116{
5117 struct ixgbe_adv_tx_context_desc *context_desc;
5118 unsigned int i;
5119 int err;
5120 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5121 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5122 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5123
5124 if (skb_is_gso(skb)) {
5125 if (skb_header_cloned(skb)) {
5126 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5127 if (err)
5128 return err;
5129 }
5130 l4len = tcp_hdrlen(skb);
5131 *hdr_len += l4len;
5132
8327d000 5133 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5134 struct iphdr *iph = ip_hdr(skb);
5135 iph->tot_len = 0;
5136 iph->check = 0;
5137 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 5138 iph->daddr, 0,
5139 IPPROTO_TCP,
5140 0);
8e1e8a47 5141 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5142 ipv6_hdr(skb)->payload_len = 0;
5143 tcp_hdr(skb)->check =
5144 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 5145 &ipv6_hdr(skb)->daddr,
5146 0, IPPROTO_TCP, 0);
9a799d71
AK		 5147 }
5148
5149 i = tx_ring->next_to_use;
5150
5151 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5152 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5153
5154 /* VLAN MACLEN IPLEN */
5155 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5156 vlan_macip_lens |=
5157 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5158 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 5159 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5160 *hdr_len += skb_network_offset(skb);
5161 vlan_macip_lens |=
5162 (skb_transport_header(skb) - skb_network_header(skb));
5163 *hdr_len +=
5164 (skb_transport_header(skb) - skb_network_header(skb));
5165 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5166 context_desc->seqnum_seed = 0;
5167
5168 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5169 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 5170 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5171
8327d000 5172 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5173 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5174 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5175 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5176
5177 /* MSS L4LEN IDX */
9f8cdf4f 5178 mss_l4len_idx =
9a799d71
AK		 5179 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5180 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5181 /* use index 1 for TSO */
5182 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5183 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5184
5185 tx_buffer_info->time_stamp = jiffies;
5186 tx_buffer_info->next_to_watch = i;
5187
5188 i++;
5189 if (i == tx_ring->count)
5190 i = 0;
5191 tx_ring->next_to_use = i;
5192
5193 return true;
5194 }
5195 return false;
5196}
5197
5198static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 5199 struct ixgbe_ring *tx_ring,
5200 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5201{
5202 struct ixgbe_adv_tx_context_desc *context_desc;
5203 unsigned int i;
5204 struct ixgbe_tx_buffer *tx_buffer_info;
5205 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5206
5207 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5208 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5209 i = tx_ring->next_to_use;
5210 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5211 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5212
5213 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5214 vlan_macip_lens |=
5215 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5216 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 5217 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5218 if (skb->ip_summed == CHECKSUM_PARTIAL)
5219 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 5220 skb_network_header(skb));
9a799d71
AK		 5221
5222 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5223 context_desc->seqnum_seed = 0;
5224
5225 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 5226 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5227
5228 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5229 __be16 protocol;
5230
5231 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5232 const struct vlan_ethhdr *vhdr =
5233 (const struct vlan_ethhdr *)skb->data;
5234
5235 protocol = vhdr->h_vlan_encapsulated_proto;
5236 } else {
5237 protocol = skb->protocol;
5238 }
5239
5240 switch (protocol) {
09640e63 5241 case cpu_to_be16(ETH_P_IP):
9a799d71 5242 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5243 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5244 type_tucmd_mlhl |=
b4617240 5245 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5246 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5247 type_tucmd_mlhl |=
5248 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5249 break;
09640e63 5250 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5251 /* XXX what about other V6 headers?? */
5252 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5253 type_tucmd_mlhl |=
b4617240 5254 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5255 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5256 type_tucmd_mlhl |=
5257 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5258 break;
41825d71
AK		 5259 default:
5260 if (unlikely(net_ratelimit())) {
5261 DPRINTK(PROBE, WARNING,
5262 "partial checksum but proto=%x!\n",
5263 skb->protocol);
5264 }
5265 break;
5266 }
9a799d71
AK		 5267 }
5268
5269 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5270 /* use index zero for tx checksum offload */
9a799d71
AK		 5271 context_desc->mss_l4len_idx = 0;
5272
5273 tx_buffer_info->time_stamp = jiffies;
5274 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5275
9a799d71
AK		 5276 i++;
5277 if (i == tx_ring->count)
5278 i = 0;
5279 tx_ring->next_to_use = i;
5280
5281 return true;
5282 }
9f8cdf4f 5283
9a799d71
AK		 5284 return false;
5285}
5286
5287static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 5288 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 5289 struct sk_buff *skb, u32 tx_flags,
5290 unsigned int first)
9a799d71 5291{
e5a43549 5292 struct pci_dev *pdev = adapter->pdev;
9a799d71 5293 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5294 unsigned int len;
5295 unsigned int total = skb->len;
9a799d71
AK		 5296 unsigned int offset = 0, size, count = 0, i;
5297 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5298 unsigned int f;
9a799d71
AK		 5299
5300 i = tx_ring->next_to_use;
5301
eacd73f7
YZ		 5302 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5303 /* excluding fcoe_crc_eof for FCoE */
5304 total -= sizeof(struct fcoe_crc_eof);
5305
5306 len = min(skb_headlen(skb), total);
9a799d71
AK		 5307 while (len) {
5308 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5309 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5310
5311 tx_buffer_info->length = size;
e5a43549
AD		 5312 tx_buffer_info->mapped_as_page = false;
5313 tx_buffer_info->dma = pci_map_single(pdev,
5314 skb->data + offset,
5315 size, PCI_DMA_TODEVICE);
5316 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5317 goto dma_error;
9a799d71
AK		 5318 tx_buffer_info->time_stamp = jiffies;
5319 tx_buffer_info->next_to_watch = i;
5320
5321 len -= size;
eacd73f7 5322 total -= size;
9a799d71
AK		 5323 offset += size;
5324 count++;
44df32c5
AD		 5325
5326 if (len) {
5327 i++;
5328 if (i == tx_ring->count)
5329 i = 0;
5330 }
9a799d71
AK		 5331 }
5332
5333 for (f = 0; f < nr_frags; f++) {
5334 struct skb_frag_struct *frag;
5335
5336 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 5337 len = min((unsigned int)frag->size, total);
e5a43549 5338 offset = frag->page_offset;
9a799d71
AK		 5339
5340 while (len) {
44df32c5
AD		 5341 i++;
5342 if (i == tx_ring->count)
5343 i = 0;
5344
9a799d71
AK		 5345 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5346 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5347
5348 tx_buffer_info->length = size;
e5a43549
AD		 5349 tx_buffer_info->dma = pci_map_page(adapter->pdev,
5350 frag->page,
5351 offset, size,
5352 PCI_DMA_TODEVICE);
5353 tx_buffer_info->mapped_as_page = true;
5354 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5355 goto dma_error;
9a799d71
AK		 5356 tx_buffer_info->time_stamp = jiffies;
5357 tx_buffer_info->next_to_watch = i;
5358
5359 len -= size;
eacd73f7 5360 total -= size;
9a799d71
AK		 5361 offset += size;
5362 count++;
9a799d71 5363 }
eacd73f7
YZ		 5364 if (total == 0)
5365 break;
9a799d71 5366 }
44df32c5 5367
9a799d71
AK		 5368 tx_ring->tx_buffer_info[i].skb = skb;
5369 tx_ring->tx_buffer_info[first].next_to_watch = i;
5370
e5a43549
AD		 5371 return count;
5372
5373dma_error:
5374 dev_err(&pdev->dev, "TX DMA map failed\n");
5375
5376 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5377 tx_buffer_info->dma = 0;
5378 tx_buffer_info->time_stamp = 0;
5379 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 5380 if (count)
5381 count--;
e5a43549
AD		 5382
5383 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f
RK		 5384 while (count--) {
5385 if (i==0)
e5a43549 5386 i += tx_ring->count;
c1fa347f 5387 i--;
e5a43549
AD		 5388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5389 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5390 }
5391
e44d38e1 5392 return 0;
9a799d71
AK		 5393}
5394
5395static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5396 struct ixgbe_ring *tx_ring,
5397 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5398{
5399 union ixgbe_adv_tx_desc *tx_desc = NULL;
5400 struct ixgbe_tx_buffer *tx_buffer_info;
5401 u32 olinfo_status = 0, cmd_type_len = 0;
5402 unsigned int i;
5403 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5404
5405 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5406
5407 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5408
5409 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5410 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5411
5412 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5413 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5414
5415 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5416 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5417
4eeae6fd
PW		 5418 /* use index 1 context for tso */
5419 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5420 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5421 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5422 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5423
5424 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5425 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5426 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5427
eacd73f7
YZ		 5428 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5429 olinfo_status |= IXGBE_ADVTXD_CC;
5430 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5431 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5432 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5433 }
5434
9a799d71
AK		 5435 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5436
5437 i = tx_ring->next_to_use;
5438 while (count--) {
5439 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5440 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5441 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5442 tx_desc->read.cmd_type_len =
b4617240 5443 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5444 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5445 i++;
5446 if (i == tx_ring->count)
5447 i = 0;
5448 }
5449
5450 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5451
5452 /*
5453 * Force memory writes to complete before letting h/w
5454 * know there are new descriptors to fetch. (Only
5455 * applicable for weak-ordered memory model archs,
5456 * such as IA-64).
5457 */
5458 wmb();
5459
5460 tx_ring->next_to_use = i;
5461 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5462}
5463
c4cf55e5
PWJ		 5464static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5465 int queue, u32 tx_flags)
5466{
5467 /* Right now, we support IPv4 only */
5468 struct ixgbe_atr_input atr_input;
5469 struct tcphdr *th;
c4cf55e5
PWJ		 5470 struct iphdr *iph = ip_hdr(skb);
5471 struct ethhdr *eth = (struct ethhdr *)skb->data;
5472 u16 vlan_id, src_port, dst_port, flex_bytes;
5473 u32 src_ipv4_addr, dst_ipv4_addr;
5474 u8 l4type = 0;
5475
5476 /* check if we're UDP or TCP */
5477 if (iph->protocol == IPPROTO_TCP) {
5478 th = tcp_hdr(skb);
5479 src_port = th->source;
5480 dst_port = th->dest;
5481 l4type |= IXGBE_ATR_L4TYPE_TCP;
5482 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5483 } else {
5484 /* Unsupported L4 header, just bail here */
5485 return;
5486 }
5487
5488 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5489
5490 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5491 IXGBE_TX_FLAGS_VLAN_SHIFT;
5492 src_ipv4_addr = iph->saddr;
5493 dst_ipv4_addr = iph->daddr;
5494 flex_bytes = eth->h_proto;
5495
5496 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5497 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5498 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5499 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5500 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5501 /* src and dst are inverted, think how the receiver sees them */
5502 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5503 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5504
5505 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5506 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5507}
5508
e092be60 5509static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5510 struct ixgbe_ring *tx_ring, int size)
e092be60 5511{
30eba97a 5512 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5513 /* Herbert's original patch had:
5514 * smp_mb__after_netif_stop_queue();
5515 * but since that doesn't exist yet, just open code it. */
5516 smp_mb();
5517
5518 /* We need to check again in a case another CPU has just
5519 * made room available. */
5520 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5521 return -EBUSY;
5522
5523 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5524 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 5525 ++tx_ring->restart_queue;
e092be60
AV		 5526 return 0;
5527}
5528
5529static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5530 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5531{
5532 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5533 return 0;
5534 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5535}
5536
09a3b1f8
SH		 5537static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5538{
5539 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 5540 int txq = smp_processor_id();
09a3b1f8 5541
fdd3d631
KK		 5542 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5543 while (unlikely(txq >= dev->real_num_tx_queues))
5544 txq -= dev->real_num_tx_queues;
5f715823 5545 return txq;
fdd3d631 5546 }
c4cf55e5 5547
5f715823
YZ		 5548#ifdef IXGBE_FCOE
5549 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5550 (skb->protocol == htons(ETH_P_FCOE))) {
5551 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5552 txq += adapter->ring_feature[RING_F_FCOE].mask;
5553 return txq;
5554 }
5555#endif
09a3b1f8 5556 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5557 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5558
5559 return skb_tx_hash(dev, skb);
5560}
5561
3b29a56d
SH		 5562static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5563 struct net_device *netdev)
9a799d71
AK		 5564{
5565 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5566 struct ixgbe_ring *tx_ring;
60d51134 5567 struct netdev_queue *txq;
9a799d71
AK		 5568 unsigned int first;
5569 unsigned int tx_flags = 0;
30eba97a 5570 u8 hdr_len = 0;
5f715823 5571 int tso;
9a799d71
AK		 5572 int count = 0;
5573 unsigned int f;
9f8cdf4f 5574
9f8cdf4f
JB		 5575 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5576 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5577 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5578 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 5579 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 5580 }
5581 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5582 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5583 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865 5584 if (skb->priority != TC_PRIO_CONTROL) {
5f715823 5585 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
60127865
LL		 5586 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5587 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5588 } else {
5589 skb->queue_mapping =
5590 adapter->ring_feature[RING_F_DCB].indices-1;
5591 }
9a799d71 5592 }
eacd73f7 5593
5f715823 5594 tx_ring = &adapter->tx_ring[skb->queue_mapping];
60127865 5595
eacd73f7 5596 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5597 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5598 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 5599#ifdef IXGBE_FCOE
61a0f421
YZ		 5600#ifdef CONFIG_IXGBE_DCB
5601 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5602 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5603 tx_flags |= ((adapter->fcoe.up << 13)
5604 << IXGBE_TX_FLAGS_VLAN_SHIFT);
5605#endif
09ad1cc0
YZ		 5606#endif
5607 }
eacd73f7 5608 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5609 if (skb_is_gso(skb) ||
5610 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5611 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5612 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5613 count++;
5614
9f8cdf4f
JB		 5615 count += TXD_USE_COUNT(skb_headlen(skb));
5616 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5617 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5618
e092be60 5619 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5620 adapter->tx_busy++;
9a799d71
AK		 5621 return NETDEV_TX_BUSY;
5622 }
9a799d71 5623
9a799d71 5624 first = tx_ring->next_to_use;
eacd73f7
YZ		 5625 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5626#ifdef IXGBE_FCOE
5627 /* setup tx offload for FCoE */
5628 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5629 if (tso < 0) {
5630 dev_kfree_skb_any(skb);
5631 return NETDEV_TX_OK;
5632 }
5633 if (tso)
5634 tx_flags |= IXGBE_TX_FLAGS_FSO;
5635#endif /* IXGBE_FCOE */
5636 } else {
5637 if (skb->protocol == htons(ETH_P_IP))
5638 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5639 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5640 if (tso < 0) {
5641 dev_kfree_skb_any(skb);
5642 return NETDEV_TX_OK;
5643 }
9a799d71 5644
eacd73f7
YZ		 5645 if (tso)
5646 tx_flags |= IXGBE_TX_FLAGS_TSO;
5647 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5648 (skb->ip_summed == CHECKSUM_PARTIAL))
5649 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5650 }
9a799d71 5651
eacd73f7 5652 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5653 if (count) {
c4cf55e5
PWJ		 5654 /* add the ATR filter if ATR is on */
5655 if (tx_ring->atr_sample_rate) {
5656 ++tx_ring->atr_count;
5657 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5658 test_bit(__IXGBE_FDIR_INIT_DONE,
5659 &tx_ring->reinit_state)) {
5660 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5661 tx_flags);
5662 tx_ring->atr_count = 0;
5663 }
5664 }
60d51134
ED		 5665 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5666 txq->tx_bytes += skb->len;
5667 txq->tx_packets++;
44df32c5
AD		 5668 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5669 hdr_len);
44df32c5 5670 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5671
44df32c5
AD		 5672 } else {
5673 dev_kfree_skb_any(skb);
5674 tx_ring->tx_buffer_info[first].time_stamp = 0;
5675 tx_ring->next_to_use = first;
5676 }
9a799d71
AK		 5677
5678 return NETDEV_TX_OK;
5679}
5680
9a799d71
AK		 5681/**
5682 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5683 * @netdev: network interface device structure
5684 * @p: pointer to an address structure
5685 *
5686 * Returns 0 on success, negative on failure
5687 **/
5688static int ixgbe_set_mac(struct net_device *netdev, void *p)
5689{
5690 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5691 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5692 struct sockaddr *addr = p;
5693
5694 if (!is_valid_ether_addr(addr->sa_data))
5695 return -EADDRNOTAVAIL;
5696
5697 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5698 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5699
1cdd1ec8
GR		 5700 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
5701 IXGBE_RAH_AV);
9a799d71
AK		 5702
5703 return 0;
5704}
5705
6b73e10d
BH		 5706static int
5707ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5708{
5709 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5710 struct ixgbe_hw *hw = &adapter->hw;
5711 u16 value;
5712 int rc;
5713
5714 if (prtad != hw->phy.mdio.prtad)
5715 return -EINVAL;
5716 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5717 if (!rc)
5718 rc = value;
5719 return rc;
5720}
5721
5722static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5723 u16 addr, u16 value)
5724{
5725 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5726 struct ixgbe_hw *hw = &adapter->hw;
5727
5728 if (prtad != hw->phy.mdio.prtad)
5729 return -EINVAL;
5730 return hw->phy.ops.write_reg(hw, addr, devad, value);
5731}
5732
5733static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5734{
5735 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5736
5737 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5738}
5739
0365e6e4
PW		 5740/**
5741 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5742 * netdev->dev_addrs
0365e6e4
PW		 5743 * @netdev: network interface device structure
5744 *
5745 * Returns non-zero on failure
5746 **/
5747static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5748{
5749 int err = 0;
5750 struct ixgbe_adapter *adapter = netdev_priv(dev);
5751 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5752
5753 if (is_valid_ether_addr(mac->san_addr)) {
5754 rtnl_lock();
5755 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5756 rtnl_unlock();
5757 }
5758 return err;
5759}
5760
5761/**
5762 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5763 * netdev->dev_addrs
0365e6e4
PW		 5764 * @netdev: network interface device structure
5765 *
5766 * Returns non-zero on failure
5767 **/
5768static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5769{
5770 int err = 0;
5771 struct ixgbe_adapter *adapter = netdev_priv(dev);
5772 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5773
5774 if (is_valid_ether_addr(mac->san_addr)) {
5775 rtnl_lock();
5776 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5777 rtnl_unlock();
5778 }
5779 return err;
5780}
5781
9a799d71
AK		 5782#ifdef CONFIG_NET_POLL_CONTROLLER
5783/*
5784 * Polling 'interrupt' - used by things like netconsole to send skbs
5785 * without having to re-enable interrupts. It's not called while
5786 * the interrupt routine is executing.
5787 */
5788static void ixgbe_netpoll(struct net_device *netdev)
5789{
5790 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5791 int i;
9a799d71 5792
1a647bd2
AD		 5793 /* if interface is down do nothing */
5794 if (test_bit(__IXGBE_DOWN, &adapter->state))
5795 return;
5796
9a799d71 5797 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5798 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5799 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5800 for (i = 0; i < num_q_vectors; i++) {
5801 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5802 ixgbe_msix_clean_many(0, q_vector);
5803 }
5804 } else {
5805 ixgbe_intr(adapter->pdev->irq, netdev);
5806 }
9a799d71 5807 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5808}
5809#endif
5810
0edc3527
SH		 5811static const struct net_device_ops ixgbe_netdev_ops = {
5812 .ndo_open = ixgbe_open,
5813 .ndo_stop = ixgbe_close,
00829823 5814 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5815 .ndo_select_queue = ixgbe_select_queue,
e90d400c 5816 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5817 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5818 .ndo_validate_addr = eth_validate_addr,
5819 .ndo_set_mac_address = ixgbe_set_mac,
5820 .ndo_change_mtu = ixgbe_change_mtu,
5821 .ndo_tx_timeout = ixgbe_tx_timeout,
5822 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5823 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5824 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5825 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5826#ifdef CONFIG_NET_POLL_CONTROLLER
5827 .ndo_poll_controller = ixgbe_netpoll,
5828#endif
332d4a7d
YZ		 5829#ifdef IXGBE_FCOE
5830 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5831 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5832 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5833 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 5834 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 5835#endif /* IXGBE_FCOE */
0edc3527
SH		 5836};
5837
1cdd1ec8
GR		 5838static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
5839 const struct ixgbe_info *ii)
5840{
5841#ifdef CONFIG_PCI_IOV
5842 struct ixgbe_hw *hw = &adapter->hw;
5843 int err;
5844
5845 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
5846 return;
5847
5848 /* The 82599 supports up to 64 VFs per physical function
5849 * but this implementation limits allocation to 63 so that
5850 * basic networking resources are still available to the
5851 * physical function
5852 */
5853 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
5854 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
5855 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
5856 if (err) {
5857 DPRINTK(PROBE, ERR,
5858 "Failed to enable PCI sriov: %d\n", err);
5859 goto err_novfs;
5860 }
5861 /* If call to enable VFs succeeded then allocate memory
5862 * for per VF control structures.
5863 */
5864 adapter->vfinfo =
5865 kcalloc(adapter->num_vfs,
5866 sizeof(struct vf_data_storage), GFP_KERNEL);
5867 if (adapter->vfinfo) {
5868 /* Now that we're sure SR-IOV is enabled
5869 * and memory allocated set up the mailbox parameters
5870 */
5871 ixgbe_init_mbx_params_pf(hw);
5872 memcpy(&hw->mbx.ops, ii->mbx_ops,
5873 sizeof(hw->mbx.ops));
5874
5875 /* Disable RSC when in SR-IOV mode */
5876 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
5877 IXGBE_FLAG2_RSC_ENABLED);
5878 return;
5879 }
5880
5881 /* Oh oh */
5882 DPRINTK(PROBE, ERR,
5883 "Unable to allocate memory for VF "
5884 "Data Storage - SRIOV disabled\n");
5885 pci_disable_sriov(adapter->pdev);
5886
5887err_novfs:
5888 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
5889 adapter->num_vfs = 0;
5890#endif /* CONFIG_PCI_IOV */
5891}
5892
9a799d71
AK		 5893/**
5894 * ixgbe_probe - Device Initialization Routine
5895 * @pdev: PCI device information struct
5896 * @ent: entry in ixgbe_pci_tbl
5897 *
5898 * Returns 0 on success, negative on failure
5899 *
5900 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5901 * The OS initialization, configuring of the adapter private structure,
5902 * and a hardware reset occur.
5903 **/
5904static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5905 const struct pci_device_id *ent)
9a799d71
AK		 5906{
5907 struct net_device *netdev;
5908 struct ixgbe_adapter *adapter = NULL;
5909 struct ixgbe_hw *hw;
5910 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5911 static int cards_found;
5912 int i, err, pci_using_dac;
eacd73f7
YZ		 5913#ifdef IXGBE_FCOE
5914 u16 device_caps;
5915#endif
c44ade9e 5916 u32 part_num, eec;
9a799d71 5917
9ce77666 5918 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5919 if (err)
5920 return err;
5921
6a35528a
YH		 5922 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5923 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5924 pci_using_dac = 1;
5925 } else {
284901a9 5926 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5927 if (err) {
284901a9 5928 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5929 if (err) {
b4617240
PW		 5930 dev_err(&pdev->dev, "No usable DMA "
5931 "configuration, aborting\n");
9a799d71
AK		 5932 goto err_dma;
5933 }
5934 }
5935 pci_using_dac = 0;
5936 }
5937
9ce77666 5938 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5939 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5940 if (err) {
9ce77666 5941 dev_err(&pdev->dev,
5942 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5943 goto err_pci_reg;
5944 }
5945
19d5afd4 5946 pci_enable_pcie_error_reporting(pdev);
6fabd715 5947
9a799d71 5948 pci_set_master(pdev);
fb3b27bc 5949 pci_save_state(pdev);
9a799d71 5950
30eba97a 5951 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5952 if (!netdev) {
5953 err = -ENOMEM;
5954 goto err_alloc_etherdev;
5955 }
5956
9a799d71
AK		 5957 SET_NETDEV_DEV(netdev, &pdev->dev);
5958
5959 pci_set_drvdata(pdev, netdev);
5960 adapter = netdev_priv(netdev);
5961
5962 adapter->netdev = netdev;
5963 adapter->pdev = pdev;
5964 hw = &adapter->hw;
5965 hw->back = adapter;
5966 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5967
05857980
JK		 5968 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5969 pci_resource_len(pdev, 0));
9a799d71
AK		 5970 if (!hw->hw_addr) {
5971 err = -EIO;
5972 goto err_ioremap;
5973 }
5974
5975 for (i = 1; i <= 5; i++) {
5976 if (pci_resource_len(pdev, i) == 0)
5977 continue;
5978 }
5979
0edc3527 5980 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5981 ixgbe_set_ethtool_ops(netdev);
9a799d71 5982 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5983 strcpy(netdev->name, pci_name(pdev));
5984
9a799d71
AK		 5985 adapter->bd_number = cards_found;
5986
9a799d71
AK		 5987 /* Setup hw api */
5988 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5989 hw->mac.type = ii->mac;
9a799d71 5990
c44ade9e
JB		 5991 /* EEPROM */
5992 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5993 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5994 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5995 if (!(eec & (1 << 8)))
5996 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5997
5998 /* PHY */
5999 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6000 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6001 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6002 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6003 hw->phy.mdio.mmds = 0;
6004 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6005 hw->phy.mdio.dev = netdev;
6006 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6007 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6008
6009 /* set up this timer and work struct before calling get_invariants
6010 * which might start the timer
6011 */
6012 init_timer(&adapter->sfp_timer);
6013 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6014 adapter->sfp_timer.data = (unsigned long) adapter;
6015
6016 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6017
e8e26350
PW		 6018 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6019 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6020
6021 /* a new SFP+ module arrival, called from GPI SDP2 context */
6022 INIT_WORK(&adapter->sfp_config_module_task,
6023 ixgbe_sfp_config_module_task);
6024
8ca783ab 6025 ii->get_invariants(hw);
9a799d71
AK		 6026
6027 /* setup the private structure */
6028 err = ixgbe_sw_init(adapter);
6029 if (err)
6030 goto err_sw_init;
6031
bf069c97
DS		 6032 /*
6033 * If there is a fan on this device and it has failed log the
6034 * failure.
6035 */
6036 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6037 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6038 if (esdp & IXGBE_ESDP_SDP1)
6039 DPRINTK(PROBE, CRIT,
6040 "Fan has stopped, replace the adapter\n");
6041 }
6042
c44ade9e
JB		 6043 /* reset_hw fills in the perm_addr as well */
6044 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 6045 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6046 hw->mac.type == ixgbe_mac_82598EB) {
6047 /*
6048 * Start a kernel thread to watch for a module to arrive.
6049 * Only do this for 82598, since 82599 will generate
6050 * interrupts on module arrival.
6051 */
6052 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6053 mod_timer(&adapter->sfp_timer,
6054 round_jiffies(jiffies + (2 * HZ)));
6055 err = 0;
6056 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 6057 dev_err(&adapter->pdev->dev, "failed to initialize because "
6058 "an unsupported SFP+ module type was detected.\n"
6059 "Reload the driver after installing a supported "
6060 "module.\n");
04f165ef
PW		 6061 goto err_sw_init;
6062 } else if (err) {
c44ade9e
JB		 6063 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
6064 goto err_sw_init;
6065 }
6066
1cdd1ec8
GR		 6067 ixgbe_probe_vf(adapter, ii);
6068
9a799d71 6069 netdev->features = NETIF_F_SG |
b4617240
PW		 6070 NETIF_F_IP_CSUM |
6071 NETIF_F_HW_VLAN_TX |
6072 NETIF_F_HW_VLAN_RX |
6073 NETIF_F_HW_VLAN_FILTER;
9a799d71 6074
e9990a9c 6075 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6076 netdev->features |= NETIF_F_TSO;
9a799d71 6077 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6078 netdev->features |= NETIF_F_GRO;
ad31c402 6079
45a5ead0
JB		 6080 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6081 netdev->features |= NETIF_F_SCTP_CSUM;
6082
ad31c402
JK		 6083 netdev->vlan_features |= NETIF_F_TSO;
6084 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6085 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6086 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6087 netdev->vlan_features |= NETIF_F_SG;
6088
1cdd1ec8
GR		 6089 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6090 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6091 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6092 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6093 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6094
7a6b6f51 6095#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6096 netdev->dcbnl_ops = &dcbnl_ops;
6097#endif
6098
eacd73f7 6099#ifdef IXGBE_FCOE
0d551589 6100 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6101 if (hw->mac.ops.get_device_caps) {
6102 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6103 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6104 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6105 }
6106 }
6107#endif /* IXGBE_FCOE */
9a799d71
AK		 6108 if (pci_using_dac)
6109 netdev->features |= NETIF_F_HIGHDMA;
6110
0c19d6af 6111 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6112 netdev->features |= NETIF_F_LRO;
6113
9a799d71 6114 /* make sure the EEPROM is good */
c44ade9e 6115 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 6116 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
6117 err = -EIO;
6118 goto err_eeprom;
6119 }
6120
6121 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6122 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6123
c44ade9e
JB		 6124 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6125 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 6126 err = -EIO;
6127 goto err_eeprom;
6128 }
6129
6130 init_timer(&adapter->watchdog_timer);
6131 adapter->watchdog_timer.function = &ixgbe_watchdog;
6132 adapter->watchdog_timer.data = (unsigned long)adapter;
6133
6134 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6135 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6136
021230d4
AV		 6137 err = ixgbe_init_interrupt_scheme(adapter);
6138 if (err)
6139 goto err_sw_init;
9a799d71 6140
e8e26350
PW		 6141 switch (pdev->device) {
6142 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 6143 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6144 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 6145 /* Enable ACPI wakeup in GRC */
6146 IXGBE_WRITE_REG(hw, IXGBE_GRC,
6147 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 6148 break;
6149 default:
6150 adapter->wol = 0;
6151 break;
6152 }
e8e26350
PW		 6153 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6154
04f165ef
PW		 6155 /* pick up the PCI bus settings for reporting later */
6156 hw->mac.ops.get_bus_info(hw);
6157
9a799d71 6158 /* print bus type/speed/width info */
7c510e4b 6159 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 6160 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6161 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6162 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6163 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6164 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 6165 "Unknown"),
7c510e4b 6166 netdev->dev_addr);
c44ade9e 6167 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 6168 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6169 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6170 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6171 (part_num >> 8), (part_num & 0xff));
6172 else
6173 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6174 hw->mac.type, hw->phy.type,
6175 (part_num >> 8), (part_num & 0xff));
9a799d71 6176
e8e26350 6177 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 6178 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 6179 "this card is not sufficient for optimal "
6180 "performance.\n");
0c254d86 6181 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 6182 "PCI-Express slot is required.\n");
0c254d86
AK		 6183 }
6184
34b0368c
PWJ		 6185 /* save off EEPROM version number */
6186 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6187
9a799d71 6188 /* reset the hardware with the new settings */
794caeb2 6189 err = hw->mac.ops.start_hw(hw);
c44ade9e 6190
794caeb2
PWJ		 6191 if (err == IXGBE_ERR_EEPROM_VERSION) {
6192 /* We are running on a pre-production device, log a warning */
6193 dev_warn(&pdev->dev, "This device is a pre-production "
6194 "adapter/LOM. Please be aware there may be issues "
6195 "associated with your hardware. If you are "
6196 "experiencing problems please contact your Intel or "
6197 "hardware representative who provided you with this "
6198 "hardware.\n");
6199 }
9a799d71
AK		 6200 strcpy(netdev->name, "eth%d");
6201 err = register_netdev(netdev);
6202 if (err)
6203 goto err_register;
6204
54386467
JB		 6205 /* carrier off reporting is important to ethtool even BEFORE open */
6206 netif_carrier_off(netdev);
6207
c4cf55e5
PWJ		 6208 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6209 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6210 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6211
5dd2d332 6212#ifdef CONFIG_IXGBE_DCA
652f093f 6213 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6214 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6215 ixgbe_setup_dca(adapter);
6216 }
6217#endif
1cdd1ec8
GR		 6218 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6219 DPRINTK(PROBE, INFO, "IOV is enabled with %d VFs\n",
6220 adapter->num_vfs);
6221 for (i = 0; i < adapter->num_vfs; i++)
6222 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6223 }
6224
0365e6e4
PW		 6225 /* add san mac addr to netdev */
6226 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 6227
6228 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
6229 cards_found++;
6230 return 0;
6231
6232err_register:
5eba3699 6233 ixgbe_release_hw_control(adapter);
7a921c93 6234 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6235err_sw_init:
6236err_eeprom:
1cdd1ec8
GR		 6237 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6238 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6239 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6240 del_timer_sync(&adapter->sfp_timer);
6241 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6242 cancel_work_sync(&adapter->multispeed_fiber_task);
6243 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6244 iounmap(hw->hw_addr);
6245err_ioremap:
6246 free_netdev(netdev);
6247err_alloc_etherdev:
9ce77666 6248 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6249 IORESOURCE_MEM));
9a799d71
AK		 6250err_pci_reg:
6251err_dma:
6252 pci_disable_device(pdev);
6253 return err;
6254}
6255
6256/**
6257 * ixgbe_remove - Device Removal Routine
6258 * @pdev: PCI device information struct
6259 *
6260 * ixgbe_remove is called by the PCI subsystem to alert the driver
6261 * that it should release a PCI device. The could be caused by a
6262 * Hot-Plug event, or because the driver is going to be removed from
6263 * memory.
6264 **/
6265static void __devexit ixgbe_remove(struct pci_dev *pdev)
6266{
6267 struct net_device *netdev = pci_get_drvdata(pdev);
6268 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6269
6270 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 6271 /* clear the module not found bit to make sure the worker won't
6272 * reschedule
6273 */
6274 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 6275 del_timer_sync(&adapter->watchdog_timer);
6276
c4900be0
DS		 6277 del_timer_sync(&adapter->sfp_timer);
6278 cancel_work_sync(&adapter->watchdog_task);
6279 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6280 cancel_work_sync(&adapter->multispeed_fiber_task);
6281 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 6282 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6283 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6284 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 6285 flush_scheduled_work();
6286
5dd2d332 6287#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6288 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6289 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6290 dca_remove_requester(&pdev->dev);
6291 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6292 }
6293
6294#endif
332d4a7d
YZ		 6295#ifdef IXGBE_FCOE
6296 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6297 ixgbe_cleanup_fcoe(adapter);
6298
6299#endif /* IXGBE_FCOE */
0365e6e4
PW		 6300
6301 /* remove the added san mac */
6302 ixgbe_del_sanmac_netdev(netdev);
6303
c4900be0
DS		 6304 if (netdev->reg_state == NETREG_REGISTERED)
6305 unregister_netdev(netdev);
9a799d71 6306
1cdd1ec8
GR		 6307 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6308 ixgbe_disable_sriov(adapter);
6309
7a921c93 6310 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 6311
021230d4 6312 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6313
6314 iounmap(adapter->hw.hw_addr);
9ce77666 6315 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6316 IORESOURCE_MEM));
9a799d71 6317
021230d4 6318 DPRINTK(PROBE, INFO, "complete\n");
021230d4 6319
9a799d71
AK		 6320 free_netdev(netdev);
6321
19d5afd4 6322 pci_disable_pcie_error_reporting(pdev);
6fabd715 6323
9a799d71
AK		 6324 pci_disable_device(pdev);
6325}
6326
6327/**
6328 * ixgbe_io_error_detected - called when PCI error is detected
6329 * @pdev: Pointer to PCI device
6330 * @state: The current pci connection state
6331 *
6332 * This function is called after a PCI bus error affecting
6333 * this device has been detected.
6334 */
6335static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 6336 pci_channel_state_t state)
9a799d71
AK		 6337{
6338 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6339 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6340
6341 netif_device_detach(netdev);
6342
3044b8d1
BL		 6343 if (state == pci_channel_io_perm_failure)
6344 return PCI_ERS_RESULT_DISCONNECT;
6345
9a799d71
AK		 6346 if (netif_running(netdev))
6347 ixgbe_down(adapter);
6348 pci_disable_device(pdev);
6349
b4617240 6350 /* Request a slot reset. */
9a799d71
AK		 6351 return PCI_ERS_RESULT_NEED_RESET;
6352}
6353
6354/**
6355 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6356 * @pdev: Pointer to PCI device
6357 *
6358 * Restart the card from scratch, as if from a cold-boot.
6359 */
6360static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6361{
6362 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6363 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 6364 pci_ers_result_t result;
6365 int err;
9a799d71 6366
9ce77666 6367 if (pci_enable_device_mem(pdev)) {
9a799d71 6368 DPRINTK(PROBE, ERR,
b4617240 6369 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 6370 result = PCI_ERS_RESULT_DISCONNECT;
6371 } else {
6372 pci_set_master(pdev);
6373 pci_restore_state(pdev);
c0e1f68b 6374 pci_save_state(pdev);
9a799d71 6375
dd4d8ca6 6376 pci_wake_from_d3(pdev, false);
9a799d71 6377
6fabd715 6378 ixgbe_reset(adapter);
88512539 6379 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 6380 result = PCI_ERS_RESULT_RECOVERED;
6381 }
6382
6383 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6384 if (err) {
6385 dev_err(&pdev->dev,
6386 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6387 /* non-fatal, continue */
6388 }
9a799d71 6389
6fabd715 6390 return result;
9a799d71
AK		 6391}
6392
6393/**
6394 * ixgbe_io_resume - called when traffic can start flowing again.
6395 * @pdev: Pointer to PCI device
6396 *
6397 * This callback is called when the error recovery driver tells us that
6398 * its OK to resume normal operation.
6399 */
6400static void ixgbe_io_resume(struct pci_dev *pdev)
6401{
6402 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 6403 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 6404
6405 if (netif_running(netdev)) {
6406 if (ixgbe_up(adapter)) {
6407 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6408 return;
6409 }
6410 }
6411
6412 netif_device_attach(netdev);
9a799d71
AK		 6413}
6414
6415static struct pci_error_handlers ixgbe_err_handler = {
6416 .error_detected = ixgbe_io_error_detected,
6417 .slot_reset = ixgbe_io_slot_reset,
6418 .resume = ixgbe_io_resume,
6419};
6420
6421static struct pci_driver ixgbe_driver = {
6422 .name = ixgbe_driver_name,
6423 .id_table = ixgbe_pci_tbl,
6424 .probe = ixgbe_probe,
6425 .remove = __devexit_p(ixgbe_remove),
6426#ifdef CONFIG_PM
6427 .suspend = ixgbe_suspend,
6428 .resume = ixgbe_resume,
6429#endif
6430 .shutdown = ixgbe_shutdown,
6431 .err_handler = &ixgbe_err_handler
6432};
6433
6434/**
6435 * ixgbe_init_module - Driver Registration Routine
6436 *
6437 * ixgbe_init_module is the first routine called when the driver is
6438 * loaded. All it does is register with the PCI subsystem.
6439 **/
6440static int __init ixgbe_init_module(void)
6441{
6442 int ret;
6443 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6444 ixgbe_driver_string, ixgbe_driver_version);
6445
6446 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6447
5dd2d332 6448#ifdef CONFIG_IXGBE_DCA
bd0362dd 6449 dca_register_notify(&dca_notifier);
bd0362dd 6450#endif
5dd2d332 6451
9a799d71
AK		 6452 ret = pci_register_driver(&ixgbe_driver);
6453 return ret;
6454}
b4617240 6455
9a799d71
AK		 6456module_init(ixgbe_init_module);
6457
6458/**
6459 * ixgbe_exit_module - Driver Exit Cleanup Routine
6460 *
6461 * ixgbe_exit_module is called just before the driver is removed
6462 * from memory.
6463 **/
6464static void __exit ixgbe_exit_module(void)
6465{
5dd2d332 6466#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6467 dca_unregister_notify(&dca_notifier);
6468#endif
9a799d71
AK		 6469 pci_unregister_driver(&ixgbe_driver);
6470}
bd0362dd 6471
5dd2d332 6472#ifdef CONFIG_IXGBE_DCA
bd0362dd 6473static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6474 void *p)
bd0362dd
JC		 6475{
6476 int ret_val;
6477
6478 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6479 __ixgbe_notify_dca);
bd0362dd
JC		 6480
6481 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6482}
b453368d 6483
5dd2d332 6484#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6485#ifdef DEBUG
6486/**
6487 * ixgbe_get_hw_dev_name - return device name string
6488 * used by hardware layer to print debugging information
6489 **/
6490char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6491{
6492 struct ixgbe_adapter *adapter = hw->back;
6493 return adapter->netdev->name;
6494}
bd0362dd 6495
b453368d 6496#endif
9a799d71
AK		 6497module_exit(ixgbe_exit_module);
6498
6499/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree