]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/benet/be_main.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
be2net: Patch removes redundant while statement in loop.
[net-next-2.6.git] / drivers / net / benet / be_main.c
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
28static unsigned int rx_frag_size = 2048;
ba343c77 29static unsigned int num_vfs;
6b7c5b94 30module_param(rx_frag_size, uint, S_IRUGO);
ba343c77 31module_param(num_vfs, uint, S_IRUGO);
6b7c5b94 32MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
ba343c77 33MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 34
6b7c5b94 35static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 36 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 37 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 38 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
39 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
6b7c5b94
SP		 40 { 0 }
41};
42MODULE_DEVICE_TABLE(pci, be_dev_ids);
43
44static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
45{
46 struct be_dma_mem *mem = &q->dma_mem;
47 if (mem->va)
48 pci_free_consistent(adapter->pdev, mem->size,
49 mem->va, mem->dma);
50}
51
52static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
53 u16 len, u16 entry_size)
54{
55 struct be_dma_mem *mem = &q->dma_mem;
56
57 memset(q, 0, sizeof(*q));
58 q->len = len;
59 q->entry_size = entry_size;
60 mem->size = len * entry_size;
61 mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
62 if (!mem->va)
63 return -1;
64 memset(mem->va, 0, mem->size);
65 return 0;
66}
67
8788fdc2 68static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 69{
8788fdc2 70 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 71 u32 reg = ioread32(addr);
72 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 73
cf588477
SP		 74 if (adapter->eeh_err)
75 return;
76
5f0b849e 77 if (!enabled && enable)
6b7c5b94 78 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 79 else if (enabled && !enable)
6b7c5b94 80 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 81 else
6b7c5b94 82 return;
5f0b849e 83
6b7c5b94
SP		 84 iowrite32(reg, addr);
85}
86
8788fdc2 87static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 88{
89 u32 val = 0;
90 val |= qid & DB_RQ_RING_ID_MASK;
91 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
8788fdc2 92 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 93}
94
8788fdc2 95static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 96{
97 u32 val = 0;
98 val |= qid & DB_TXULP_RING_ID_MASK;
99 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
8788fdc2 100 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 101}
102
8788fdc2 103static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 104 bool arm, bool clear_int, u16 num_popped)
105{
106 u32 val = 0;
107 val |= qid & DB_EQ_RING_ID_MASK;
cf588477
SP		 108
109 if (adapter->eeh_err)
110 return;
111
6b7c5b94
SP		 112 if (arm)
113 val |= 1 << DB_EQ_REARM_SHIFT;
114 if (clear_int)
115 val |= 1 << DB_EQ_CLR_SHIFT;
116 val |= 1 << DB_EQ_EVNT_SHIFT;
117 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 118 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 119}
120
8788fdc2 121void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 122{
123 u32 val = 0;
124 val |= qid & DB_CQ_RING_ID_MASK;
cf588477
SP		 125
126 if (adapter->eeh_err)
127 return;
128
6b7c5b94
SP		 129 if (arm)
130 val |= 1 << DB_CQ_REARM_SHIFT;
131 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 132 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 133}
134
6b7c5b94
SP		 135static int be_mac_addr_set(struct net_device *netdev, void *p)
136{
137 struct be_adapter *adapter = netdev_priv(netdev);
138 struct sockaddr *addr = p;
139 int status = 0;
140
ca9e4988
AK		 141 if (!is_valid_ether_addr(addr->sa_data))
142 return -EADDRNOTAVAIL;
143
ba343c77
SB		 144 /* MAC addr configuration will be done in hardware for VFs
145 * by their corresponding PFs. Just copy to netdev addr here
146 */
147 if (!be_physfn(adapter))
148 goto netdev_addr;
149
a65027e4
SP		 150 status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
151 if (status)
152 return status;
6b7c5b94 153
a65027e4
SP		 154 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
155 adapter->if_handle, &adapter->pmac_id);
ba343c77 156netdev_addr:
6b7c5b94
SP		 157 if (!status)
158 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
159
160 return status;
161}
162
b31c50a7 163void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94
SP		 164{
165 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
166 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
167 struct be_port_rxf_stats *port_stats =
168 &rxf_stats->port[adapter->port_num];
78122a52 169 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 170 struct be_erx_stats *erx_stats = &hw_stats->erx;
6b7c5b94 171
91992e44
AK		 172 dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
173 dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
174 dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
175 dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 176
177 /* bad pkts received */
178 dev_stats->rx_errors = port_stats->rx_crc_errors +
179 port_stats->rx_alignment_symbol_errors +
180 port_stats->rx_in_range_errors +
68110868
SP		 181 port_stats->rx_out_range_errors +
182 port_stats->rx_frame_too_long +
183 port_stats->rx_dropped_too_small +
184 port_stats->rx_dropped_too_short +
185 port_stats->rx_dropped_header_too_small +
186 port_stats->rx_dropped_tcp_length +
187 port_stats->rx_dropped_runt +
188 port_stats->rx_tcp_checksum_errs +
189 port_stats->rx_ip_checksum_errs +
190 port_stats->rx_udp_checksum_errs;
191
192 /* no space in linux buffers: best possible approximation */
01ed30da
SP		 193 dev_stats->rx_dropped =
194 erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
6b7c5b94
SP		 195
196 /* detailed rx errors */
197 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 198 port_stats->rx_out_range_errors +
199 port_stats->rx_frame_too_long;
200
6b7c5b94
SP		 201 /* receive ring buffer overflow */
202 dev_stats->rx_over_errors = 0;
68110868 203
6b7c5b94
SP		 204 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
205
206 /* frame alignment errors */
207 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 208
6b7c5b94
SP		 209 /* receiver fifo overrun */
210 /* drops_no_pbuf is no per i/f, it's per BE card */
211 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
212 port_stats->rx_input_fifo_overflow +
213 rxf_stats->rx_drops_no_pbuf;
214 /* receiver missed packetd */
215 dev_stats->rx_missed_errors = 0;
68110868
SP		 216
217 /* packet transmit problems */
218 dev_stats->tx_errors = 0;
219
220 /* no space available in linux */
221 dev_stats->tx_dropped = 0;
222
c5b9b92e 223 dev_stats->multicast = port_stats->rx_multicast_frames;
68110868
SP		 224 dev_stats->collisions = 0;
225
6b7c5b94
SP		 226 /* detailed tx_errors */
227 dev_stats->tx_aborted_errors = 0;
228 dev_stats->tx_carrier_errors = 0;
229 dev_stats->tx_fifo_errors = 0;
230 dev_stats->tx_heartbeat_errors = 0;
231 dev_stats->tx_window_errors = 0;
232}
233
8788fdc2 234void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 235{
6b7c5b94
SP		 236 struct net_device *netdev = adapter->netdev;
237
6b7c5b94 238 /* If link came up or went down */
a8f447bd 239 if (adapter->link_up != link_up) {
0dffc83e 240 adapter->link_speed = -1;
a8f447bd 241 if (link_up) {
6b7c5b94
SP		 242 netif_start_queue(netdev);
243 netif_carrier_on(netdev);
244 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd
SP		 245 } else {
246 netif_stop_queue(netdev);
247 netif_carrier_off(netdev);
248 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 249 }
a8f447bd 250 adapter->link_up = link_up;
6b7c5b94 251 }
6b7c5b94
SP		 252}
253
254/* Update the EQ delay n BE based on the RX frags consumed / sec */
255static void be_rx_eqd_update(struct be_adapter *adapter)
256{
6b7c5b94
SP		 257 struct be_eq_obj *rx_eq = &adapter->rx_eq;
258 struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
4097f663
SP		 259 ulong now = jiffies;
260 u32 eqd;
261
262 if (!rx_eq->enable_aic)
263 return;
264
265 /* Wrapped around */
266 if (time_before(now, stats->rx_fps_jiffies)) {
267 stats->rx_fps_jiffies = now;
268 return;
269 }
6b7c5b94
SP		 270
271 /* Update once a second */
4097f663 272 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 273 return;
274
275 stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
4097f663 276 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 277
4097f663 278 stats->rx_fps_jiffies = now;
6b7c5b94
SP		 279 stats->be_prev_rx_frags = stats->be_rx_frags;
280 eqd = stats->be_rx_fps / 110000;
281 eqd = eqd << 3;
282 if (eqd > rx_eq->max_eqd)
283 eqd = rx_eq->max_eqd;
284 if (eqd < rx_eq->min_eqd)
285 eqd = rx_eq->min_eqd;
286 if (eqd < 10)
287 eqd = 0;
288 if (eqd != rx_eq->cur_eqd)
8788fdc2 289 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 290
291 rx_eq->cur_eqd = eqd;
292}
293
6b7c5b94
SP		 294static struct net_device_stats *be_get_stats(struct net_device *dev)
295{
78122a52 296 return &dev->stats;
6b7c5b94
SP		 297}
298
65f71b8b
SH		 299static u32 be_calc_rate(u64 bytes, unsigned long ticks)
300{
301 u64 rate = bytes;
302
303 do_div(rate, ticks / HZ);
304 rate <<= 3; /* bytes/sec -> bits/sec */
305 do_div(rate, 1000000ul); /* MB/Sec */
306
307 return rate;
308}
309
4097f663
SP		 310static void be_tx_rate_update(struct be_adapter *adapter)
311{
312 struct be_drvr_stats *stats = drvr_stats(adapter);
313 ulong now = jiffies;
314
315 /* Wrapped around? */
316 if (time_before(now, stats->be_tx_jiffies)) {
317 stats->be_tx_jiffies = now;
318 return;
319 }
320
321 /* Update tx rate once in two seconds */
322 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 323 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
324 - stats->be_tx_bytes_prev,
325 now - stats->be_tx_jiffies);
4097f663
SP		 326 stats->be_tx_jiffies = now;
327 stats->be_tx_bytes_prev = stats->be_tx_bytes;
328 }
329}
330
6b7c5b94 331static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 332 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 333{
4097f663 334 struct be_drvr_stats *stats = drvr_stats(adapter);
6b7c5b94
SP		 335 stats->be_tx_reqs++;
336 stats->be_tx_wrbs += wrb_cnt;
337 stats->be_tx_bytes += copied;
91992e44 338 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 339 if (stopped)
340 stats->be_tx_stops++;
6b7c5b94
SP		 341}
342
343/* Determine number of WRB entries needed to xmit data in an skb */
344static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
345{
ebc8d2ab
DM		 346 int cnt = (skb->len > skb->data_len);
347
348 cnt += skb_shinfo(skb)->nr_frags;
349
6b7c5b94
SP		 350 /* to account for hdr wrb */
351 cnt++;
352 if (cnt & 1) {
353 /* add a dummy to make it an even num */
354 cnt++;
355 *dummy = true;
356 } else
357 *dummy = false;
358 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
359 return cnt;
360}
361
362static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
363{
364 wrb->frag_pa_hi = upper_32_bits(addr);
365 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
366 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
367}
368
369static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
370 bool vlan, u32 wrb_cnt, u32 len)
371{
372 memset(hdr, 0, sizeof(*hdr));
373
374 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
375
376 if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) {
377 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
378 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
379 hdr, skb_shinfo(skb)->gso_size);
380 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
381 if (is_tcp_pkt(skb))
382 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
383 else if (is_udp_pkt(skb))
384 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
385 }
386
387 if (vlan && vlan_tx_tag_present(skb)) {
388 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
389 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
390 hdr, vlan_tx_tag_get(skb));
391 }
392
393 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
394 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
395 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
396 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
397}
398
7101e111
SP		 399static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
400 bool unmap_single)
401{
402 dma_addr_t dma;
403
404 be_dws_le_to_cpu(wrb, sizeof(*wrb));
405
406 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 407 if (wrb->frag_len) {
7101e111
SP		 408 if (unmap_single)
409 pci_unmap_single(pdev, dma, wrb->frag_len,
410 PCI_DMA_TODEVICE);
411 else
412 pci_unmap_page(pdev, dma, wrb->frag_len,
413 PCI_DMA_TODEVICE);
414 }
415}
6b7c5b94
SP		 416
417static int make_tx_wrbs(struct be_adapter *adapter,
418 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
419{
7101e111
SP		 420 dma_addr_t busaddr;
421 int i, copied = 0;
6b7c5b94
SP		 422 struct pci_dev *pdev = adapter->pdev;
423 struct sk_buff *first_skb = skb;
424 struct be_queue_info *txq = &adapter->tx_obj.q;
425 struct be_eth_wrb *wrb;
426 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 427 bool map_single = false;
428 u16 map_head;
6b7c5b94 429
6b7c5b94
SP		 430 hdr = queue_head_node(txq);
431 queue_head_inc(txq);
7101e111 432 map_head = txq->head;
6b7c5b94 433
ebc8d2ab 434 if (skb->len > skb->data_len) {
e743d313 435 int len = skb_headlen(skb);
a73b796e
AD		 436 busaddr = pci_map_single(pdev, skb->data, len,
437 PCI_DMA_TODEVICE);
7101e111
SP		 438 if (pci_dma_mapping_error(pdev, busaddr))
439 goto dma_err;
440 map_single = true;
ebc8d2ab
DM		 441 wrb = queue_head_node(txq);
442 wrb_fill(wrb, busaddr, len);
443 be_dws_cpu_to_le(wrb, sizeof(*wrb));
444 queue_head_inc(txq);
445 copied += len;
446 }
6b7c5b94 447
ebc8d2ab
DM		 448 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
449 struct skb_frag_struct *frag =
450 &skb_shinfo(skb)->frags[i];
a73b796e
AD		 451 busaddr = pci_map_page(pdev, frag->page,
452 frag->page_offset,
453 frag->size, PCI_DMA_TODEVICE);
7101e111
SP		 454 if (pci_dma_mapping_error(pdev, busaddr))
455 goto dma_err;
ebc8d2ab
DM		 456 wrb = queue_head_node(txq);
457 wrb_fill(wrb, busaddr, frag->size);
458 be_dws_cpu_to_le(wrb, sizeof(*wrb));
459 queue_head_inc(txq);
460 copied += frag->size;
6b7c5b94
SP		 461 }
462
463 if (dummy_wrb) {
464 wrb = queue_head_node(txq);
465 wrb_fill(wrb, 0, 0);
466 be_dws_cpu_to_le(wrb, sizeof(*wrb));
467 queue_head_inc(txq);
468 }
469
470 wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
471 wrb_cnt, copied);
472 be_dws_cpu_to_le(hdr, sizeof(*hdr));
473
474 return copied;
7101e111
SP		 475dma_err:
476 txq->head = map_head;
477 while (copied) {
478 wrb = queue_head_node(txq);
479 unmap_tx_frag(pdev, wrb, map_single);
480 map_single = false;
481 copied -= wrb->frag_len;
482 queue_head_inc(txq);
483 }
484 return 0;
6b7c5b94
SP		 485}
486
61357325 487static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 488 struct net_device *netdev)
6b7c5b94
SP		 489{
490 struct be_adapter *adapter = netdev_priv(netdev);
491 struct be_tx_obj *tx_obj = &adapter->tx_obj;
492 struct be_queue_info *txq = &tx_obj->q;
493 u32 wrb_cnt = 0, copied = 0;
494 u32 start = txq->head;
495 bool dummy_wrb, stopped = false;
496
497 wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
498
499 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 500 if (copied) {
501 /* record the sent skb in the sent_skb table */
502 BUG_ON(tx_obj->sent_skb_list[start]);
503 tx_obj->sent_skb_list[start] = skb;
504
505 /* Ensure txq has space for the next skb; Else stop the queue
506 * *BEFORE* ringing the tx doorbell, so that we serialze the
507 * tx compls of the current transmit which'll wake up the queue
508 */
7101e111 509 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 510 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
511 txq->len) {
512 netif_stop_queue(netdev);
513 stopped = true;
514 }
6b7c5b94 515
c190e3c8 516 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 517
91992e44
AK		 518 be_tx_stats_update(adapter, wrb_cnt, copied,
519 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 520 } else {
521 txq->head = start;
522 dev_kfree_skb_any(skb);
6b7c5b94 523 }
6b7c5b94
SP		 524 return NETDEV_TX_OK;
525}
526
527static int be_change_mtu(struct net_device *netdev, int new_mtu)
528{
529 struct be_adapter *adapter = netdev_priv(netdev);
530 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 531 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
532 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 533 dev_info(&adapter->pdev->dev,
534 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 535 BE_MIN_MTU,
536 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 537 return -EINVAL;
538 }
539 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
540 netdev->mtu, new_mtu);
541 netdev->mtu = new_mtu;
542 return 0;
543}
544
545/*
82903e4b
AK		 546 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
547 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 548 */
b31c50a7 549static int be_vid_config(struct be_adapter *adapter)
6b7c5b94 550{
6b7c5b94
SP		 551 u16 vtag[BE_NUM_VLANS_SUPPORTED];
552 u16 ntags = 0, i;
82903e4b 553 int status = 0;
6b7c5b94 554
82903e4b 555 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94
SP		 556 /* Construct VLAN Table to give to HW */
557 for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
558 if (adapter->vlan_tag[i]) {
559 vtag[ntags] = cpu_to_le16(i);
560 ntags++;
561 }
562 }
b31c50a7
SP		 563 status = be_cmd_vlan_config(adapter, adapter->if_handle,
564 vtag, ntags, 1, 0);
6b7c5b94 565 } else {
b31c50a7
SP		 566 status = be_cmd_vlan_config(adapter, adapter->if_handle,
567 NULL, 0, 1, 1);
6b7c5b94 568 }
b31c50a7 569 return status;
6b7c5b94
SP		 570}
571
572static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
573{
574 struct be_adapter *adapter = netdev_priv(netdev);
575 struct be_eq_obj *rx_eq = &adapter->rx_eq;
576 struct be_eq_obj *tx_eq = &adapter->tx_eq;
6b7c5b94 577
8788fdc2
SP		 578 be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
579 be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
6b7c5b94 580 adapter->vlan_grp = grp;
8788fdc2
SP		 581 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
582 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
6b7c5b94
SP		 583}
584
585static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
586{
587 struct be_adapter *adapter = netdev_priv(netdev);
588
ba343c77
SB		 589 if (!be_physfn(adapter))
590 return;
591
6b7c5b94 592 adapter->vlan_tag[vid] = 1;
82903e4b
AK		 593 adapter->vlans_added++;
594 if (adapter->vlans_added <= (adapter->max_vlans + 1))
595 be_vid_config(adapter);
6b7c5b94
SP		 596}
597
598static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
599{
600 struct be_adapter *adapter = netdev_priv(netdev);
601
ba343c77
SB		 602 if (!be_physfn(adapter))
603 return;
604
6b7c5b94 605 adapter->vlan_tag[vid] = 0;
6b7c5b94 606 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
82903e4b
AK		 607 adapter->vlans_added--;
608 if (adapter->vlans_added <= adapter->max_vlans)
609 be_vid_config(adapter);
6b7c5b94
SP		 610}
611
24307eef 612static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 613{
614 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 615
24307eef 616 if (netdev->flags & IFF_PROMISC) {
8788fdc2 617 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 618 adapter->promiscuous = true;
619 goto done;
6b7c5b94
SP		 620 }
621
24307eef
SP		 622 /* BE was previously in promiscous mode; disable it */
623 if (adapter->promiscuous) {
624 adapter->promiscuous = false;
8788fdc2 625 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 626 }
627
e7b909a6 628 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 629 if (netdev->flags & IFF_ALLMULTI ||
630 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 631 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 632 &adapter->mc_cmd_mem);
24307eef 633 goto done;
6b7c5b94 634 }
6b7c5b94 635
0ddf477b 636 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 637 &adapter->mc_cmd_mem);
24307eef
SP		 638done:
639 return;
6b7c5b94
SP		 640}
641
ba343c77
SB		 642static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
643{
644 struct be_adapter *adapter = netdev_priv(netdev);
645 int status;
646
647 if (!adapter->sriov_enabled)
648 return -EPERM;
649
650 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
651 return -EINVAL;
652
653 status = be_cmd_pmac_del(adapter, adapter->vf_if_handle[vf],
654 adapter->vf_pmac_id[vf]);
655
656 status = be_cmd_pmac_add(adapter, mac, adapter->vf_if_handle[vf],
657 &adapter->vf_pmac_id[vf]);
658 if (!status)
659 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
660 mac, vf);
661 return status;
662}
663
4097f663 664static void be_rx_rate_update(struct be_adapter *adapter)
6b7c5b94 665{
4097f663
SP		 666 struct be_drvr_stats *stats = drvr_stats(adapter);
667 ulong now = jiffies;
6b7c5b94 668
4097f663
SP		 669 /* Wrapped around */
670 if (time_before(now, stats->be_rx_jiffies)) {
671 stats->be_rx_jiffies = now;
672 return;
673 }
6b7c5b94
SP		 674
675 /* Update the rate once in two seconds */
4097f663 676 if ((now - stats->be_rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 677 return;
678
65f71b8b
SH		 679 stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
680 - stats->be_rx_bytes_prev,
681 now - stats->be_rx_jiffies);
4097f663 682 stats->be_rx_jiffies = now;
6b7c5b94
SP		 683 stats->be_rx_bytes_prev = stats->be_rx_bytes;
684}
685
4097f663
SP		 686static void be_rx_stats_update(struct be_adapter *adapter,
687 u32 pktsize, u16 numfrags)
688{
689 struct be_drvr_stats *stats = drvr_stats(adapter);
690
691 stats->be_rx_compl++;
692 stats->be_rx_frags += numfrags;
693 stats->be_rx_bytes += pktsize;
91992e44 694 stats->be_rx_pkts++;
4097f663
SP		 695}
696
728a9972
AK		 697static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
698{
699 u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
700
701 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
702 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
703 ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
704 if (ip_version) {
705 tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
706 udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
707 }
708 ipv6_chk = (ip_version && (tcpf || udpf));
709
710 return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
711}
712
6b7c5b94
SP		 713static struct be_rx_page_info *
714get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
715{
716 struct be_rx_page_info *rx_page_info;
717 struct be_queue_info *rxq = &adapter->rx_obj.q;
718
719 rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
720 BUG_ON(!rx_page_info->page);
721
205859a2 722 if (rx_page_info->last_page_user) {
fac6da5b 723 pci_unmap_page(adapter->pdev, dma_unmap_addr(rx_page_info, bus),
6b7c5b94 724 adapter->big_page_size, PCI_DMA_FROMDEVICE);
205859a2
AK		 725 rx_page_info->last_page_user = false;
726 }
6b7c5b94
SP		 727
728 atomic_dec(&rxq->used);
729 return rx_page_info;
730}
731
732/* Throwaway the data in the Rx completion */
733static void be_rx_compl_discard(struct be_adapter *adapter,
734 struct be_eth_rx_compl *rxcp)
735{
736 struct be_queue_info *rxq = &adapter->rx_obj.q;
737 struct be_rx_page_info *page_info;
738 u16 rxq_idx, i, num_rcvd;
739
740 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
741 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
742
743 for (i = 0; i < num_rcvd; i++) {
744 page_info = get_rx_page_info(adapter, rxq_idx);
745 put_page(page_info->page);
746 memset(page_info, 0, sizeof(*page_info));
747 index_inc(&rxq_idx, rxq->len);
748 }
749}
750
751/*
752 * skb_fill_rx_data forms a complete skb for an ether frame
753 * indicated by rxcp.
754 */
755static void skb_fill_rx_data(struct be_adapter *adapter,
89420424
SP		 756 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
757 u16 num_rcvd)
6b7c5b94
SP		 758{
759 struct be_queue_info *rxq = &adapter->rx_obj.q;
760 struct be_rx_page_info *page_info;
89420424 761 u16 rxq_idx, i, j;
fa77406a 762 u32 pktsize, hdr_len, curr_frag_len, size;
6b7c5b94
SP		 763 u8 *start;
764
765 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
766 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
6b7c5b94
SP		 767
768 page_info = get_rx_page_info(adapter, rxq_idx);
769
770 start = page_address(page_info->page) + page_info->page_offset;
771 prefetch(start);
772
773 /* Copy data in the first descriptor of this completion */
774 curr_frag_len = min(pktsize, rx_frag_size);
775
776 /* Copy the header portion into skb_data */
777 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
778 memcpy(skb->data, start, hdr_len);
779 skb->len = curr_frag_len;
780 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
781 /* Complete packet has now been moved to data */
782 put_page(page_info->page);
783 skb->data_len = 0;
784 skb->tail += curr_frag_len;
785 } else {
786 skb_shinfo(skb)->nr_frags = 1;
787 skb_shinfo(skb)->frags[0].page = page_info->page;
788 skb_shinfo(skb)->frags[0].page_offset =
789 page_info->page_offset + hdr_len;
790 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
791 skb->data_len = curr_frag_len - hdr_len;
792 skb->tail += hdr_len;
793 }
205859a2 794 page_info->page = NULL;
6b7c5b94
SP		 795
796 if (pktsize <= rx_frag_size) {
797 BUG_ON(num_rcvd != 1);
76fbb429 798 goto done;
6b7c5b94
SP		 799 }
800
801 /* More frags present for this completion */
fa77406a 802 size = pktsize;
bd46cb6c 803 for (i = 1, j = 0; i < num_rcvd; i++) {
fa77406a 804 size -= curr_frag_len;
6b7c5b94
SP		 805 index_inc(&rxq_idx, rxq->len);
806 page_info = get_rx_page_info(adapter, rxq_idx);
807
fa77406a 808 curr_frag_len = min(size, rx_frag_size);
6b7c5b94 809
bd46cb6c
AK		 810 /* Coalesce all frags from the same physical page in one slot */
811 if (page_info->page_offset == 0) {
812 /* Fresh page */
813 j++;
814 skb_shinfo(skb)->frags[j].page = page_info->page;
815 skb_shinfo(skb)->frags[j].page_offset =
816 page_info->page_offset;
817 skb_shinfo(skb)->frags[j].size = 0;
818 skb_shinfo(skb)->nr_frags++;
819 } else {
820 put_page(page_info->page);
821 }
822
823 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 824 skb->len += curr_frag_len;
825 skb->data_len += curr_frag_len;
6b7c5b94 826
205859a2 827 page_info->page = NULL;
6b7c5b94 828 }
bd46cb6c 829 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 830
76fbb429 831done:
4097f663 832 be_rx_stats_update(adapter, pktsize, num_rcvd);
6b7c5b94
SP		 833}
834
5be93b9a 835/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94
SP		 836static void be_rx_compl_process(struct be_adapter *adapter,
837 struct be_eth_rx_compl *rxcp)
838{
839 struct sk_buff *skb;
dcb9b564 840 u32 vlanf, vid;
89420424 841 u16 num_rcvd;
dcb9b564 842 u8 vtm;
6b7c5b94 843
89420424
SP		 844 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
845 /* Is it a flush compl that has no data */
846 if (unlikely(num_rcvd == 0))
847 return;
848
89d71a66 849 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 850 if (unlikely(!skb)) {
6b7c5b94
SP		 851 if (net_ratelimit())
852 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
853 be_rx_compl_discard(adapter, rxcp);
854 return;
855 }
856
89420424 857 skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
6b7c5b94 858
728a9972 859 if (do_pkt_csum(rxcp, adapter->rx_csum))
6b7c5b94 860 skb->ip_summed = CHECKSUM_NONE;
728a9972
AK		 861 else
862 skb->ip_summed = CHECKSUM_UNNECESSARY;
6b7c5b94
SP		 863
864 skb->truesize = skb->len + sizeof(struct sk_buff);
865 skb->protocol = eth_type_trans(skb, adapter->netdev);
6b7c5b94 866
a058a632
SP		 867 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
868 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
869
870 /* vlanf could be wrongly set in some cards.
871 * ignore if vtm is not set */
872 if ((adapter->cap & 0x400) && !vtm)
873 vlanf = 0;
874
875 if (unlikely(vlanf)) {
82903e4b 876 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 877 kfree_skb(skb);
878 return;
879 }
880 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
9cae9e4f 881 vid = swab16(vid);
6b7c5b94
SP		 882 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
883 } else {
884 netif_receive_skb(skb);
885 }
6b7c5b94
SP		 886}
887
5be93b9a
AK		 888/* Process the RX completion indicated by rxcp when GRO is enabled */
889static void be_rx_compl_process_gro(struct be_adapter *adapter,
6b7c5b94
SP		 890 struct be_eth_rx_compl *rxcp)
891{
892 struct be_rx_page_info *page_info;
5be93b9a 893 struct sk_buff *skb = NULL;
6b7c5b94 894 struct be_queue_info *rxq = &adapter->rx_obj.q;
5be93b9a 895 struct be_eq_obj *eq_obj = &adapter->rx_eq;
6b7c5b94 896 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
bd46cb6c 897 u16 i, rxq_idx = 0, vid, j;
dcb9b564 898 u8 vtm;
6b7c5b94
SP		 899
900 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
89420424
SP		 901 /* Is it a flush compl that has no data */
902 if (unlikely(num_rcvd == 0))
903 return;
904
6b7c5b94
SP		 905 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
906 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
907 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
dcb9b564
AK		 908 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
909
910 /* vlanf could be wrongly set in some cards.
911 * ignore if vtm is not set */
e1187b3b 912 if ((adapter->cap & 0x400) && !vtm)
dcb9b564 913 vlanf = 0;
6b7c5b94 914
5be93b9a
AK		 915 skb = napi_get_frags(&eq_obj->napi);
916 if (!skb) {
917 be_rx_compl_discard(adapter, rxcp);
918 return;
919 }
920
6b7c5b94 921 remaining = pkt_size;
bd46cb6c 922 for (i = 0, j = -1; i < num_rcvd; i++) {
6b7c5b94
SP		 923 page_info = get_rx_page_info(adapter, rxq_idx);
924
925 curr_frag_len = min(remaining, rx_frag_size);
926
bd46cb6c
AK		 927 /* Coalesce all frags from the same physical page in one slot */
928 if (i == 0 || page_info->page_offset == 0) {
929 /* First frag or Fresh page */
930 j++;
5be93b9a
AK		 931 skb_shinfo(skb)->frags[j].page = page_info->page;
932 skb_shinfo(skb)->frags[j].page_offset =
933 page_info->page_offset;
934 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 935 } else {
936 put_page(page_info->page);
937 }
5be93b9a 938 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 939
bd46cb6c 940 remaining -= curr_frag_len;
6b7c5b94 941 index_inc(&rxq_idx, rxq->len);
6b7c5b94
SP		 942 memset(page_info, 0, sizeof(*page_info));
943 }
bd46cb6c 944 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 945
5be93b9a
AK		 946 skb_shinfo(skb)->nr_frags = j + 1;
947 skb->len = pkt_size;
948 skb->data_len = pkt_size;
949 skb->truesize += pkt_size;
950 skb->ip_summed = CHECKSUM_UNNECESSARY;
951
6b7c5b94 952 if (likely(!vlanf)) {
5be93b9a 953 napi_gro_frags(&eq_obj->napi);
6b7c5b94
SP		 954 } else {
955 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
9cae9e4f 956 vid = swab16(vid);
6b7c5b94 957
82903e4b 958 if (!adapter->vlan_grp || adapter->vlans_added == 0)
6b7c5b94
SP		 959 return;
960
5be93b9a 961 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
6b7c5b94
SP		 962 }
963
4097f663 964 be_rx_stats_update(adapter, pkt_size, num_rcvd);
6b7c5b94
SP		 965}
966
967static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
968{
969 struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
970
971 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
972 return NULL;
973
974 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
975
6b7c5b94
SP		 976 queue_tail_inc(&adapter->rx_obj.cq);
977 return rxcp;
978}
979
a7a0ef31
SP		 980/* To reset the valid bit, we need to reset the whole word as
981 * when walking the queue the valid entries are little-endian
982 * and invalid entries are host endian
983 */
984static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
985{
986 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
987}
988
6b7c5b94
SP		 989static inline struct page *be_alloc_pages(u32 size)
990{
991 gfp_t alloc_flags = GFP_ATOMIC;
992 u32 order = get_order(size);
993 if (order > 0)
994 alloc_flags |= __GFP_COMP;
995 return alloc_pages(alloc_flags, order);
996}
997
998/*
999 * Allocate a page, split it to fragments of size rx_frag_size and post as
1000 * receive buffers to BE
1001 */
1002static void be_post_rx_frags(struct be_adapter *adapter)
1003{
1004 struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
26d92f92 1005 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
6b7c5b94
SP		 1006 struct be_queue_info *rxq = &adapter->rx_obj.q;
1007 struct page *pagep = NULL;
1008 struct be_eth_rx_d *rxd;
1009 u64 page_dmaaddr = 0, frag_dmaaddr;
1010 u32 posted, page_offset = 0;
1011
6b7c5b94
SP		 1012 page_info = &page_info_tbl[rxq->head];
1013 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1014 if (!pagep) {
1015 pagep = be_alloc_pages(adapter->big_page_size);
1016 if (unlikely(!pagep)) {
1017 drvr_stats(adapter)->be_ethrx_post_fail++;
1018 break;
1019 }
1020 page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
1021 adapter->big_page_size,
1022 PCI_DMA_FROMDEVICE);
1023 page_info->page_offset = 0;
1024 } else {
1025 get_page(pagep);
1026 page_info->page_offset = page_offset + rx_frag_size;
1027 }
1028 page_offset = page_info->page_offset;
1029 page_info->page = pagep;
fac6da5b 1030 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1031 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1032
1033 rxd = queue_head_node(rxq);
1034 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1035 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1036
1037 /* Any space left in the current big page for another frag? */
1038 if ((page_offset + rx_frag_size + rx_frag_size) >
1039 adapter->big_page_size) {
1040 pagep = NULL;
1041 page_info->last_page_user = true;
1042 }
26d92f92
SP		 1043
1044 prev_page_info = page_info;
1045 queue_head_inc(rxq);
6b7c5b94
SP		 1046 page_info = &page_info_tbl[rxq->head];
1047 }
1048 if (pagep)
26d92f92 1049 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1050
1051 if (posted) {
6b7c5b94 1052 atomic_add(posted, &rxq->used);
8788fdc2 1053 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1054 } else if (atomic_read(&rxq->used) == 0) {
1055 /* Let be_worker replenish when memory is available */
1056 adapter->rx_post_starved = true;
6b7c5b94 1057 }
6b7c5b94
SP		 1058}
1059
5fb379ee 1060static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1061{
6b7c5b94
SP		 1062 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1063
1064 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1065 return NULL;
1066
1067 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1068
1069 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1070
1071 queue_tail_inc(tx_cq);
1072 return txcp;
1073}
1074
1075static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1076{
1077 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1078 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1079 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1080 struct sk_buff *sent_skb;
ec43b1a6
SP		 1081 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1082 bool unmap_skb_hdr = true;
6b7c5b94 1083
ec43b1a6 1084 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1085 BUG_ON(!sent_skb);
ec43b1a6
SP		 1086 sent_skbs[txq->tail] = NULL;
1087
1088 /* skip header wrb */
a73b796e 1089 queue_tail_inc(txq);
6b7c5b94 1090
ec43b1a6 1091 do {
6b7c5b94 1092 cur_index = txq->tail;
a73b796e 1093 wrb = queue_tail_node(txq);
ec43b1a6 1094 unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
e743d313 1095 skb_headlen(sent_skb)));
ec43b1a6
SP		 1096 unmap_skb_hdr = false;
1097
6b7c5b94
SP		 1098 num_wrbs++;
1099 queue_tail_inc(txq);
ec43b1a6 1100 } while (cur_index != last_index);
6b7c5b94
SP		 1101
1102 atomic_sub(num_wrbs, &txq->used);
a73b796e 1103
6b7c5b94
SP		 1104 kfree_skb(sent_skb);
1105}
1106
859b1e4e
SP		 1107static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1108{
1109 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1110
1111 if (!eqe->evt)
1112 return NULL;
1113
1114 eqe->evt = le32_to_cpu(eqe->evt);
1115 queue_tail_inc(&eq_obj->q);
1116 return eqe;
1117}
1118
1119static int event_handle(struct be_adapter *adapter,
1120 struct be_eq_obj *eq_obj)
1121{
1122 struct be_eq_entry *eqe;
1123 u16 num = 0;
1124
1125 while ((eqe = event_get(eq_obj)) != NULL) {
1126 eqe->evt = 0;
1127 num++;
1128 }
1129
1130 /* Deal with any spurious interrupts that come
1131 * without events
1132 */
1133 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1134 if (num)
1135 napi_schedule(&eq_obj->napi);
1136
1137 return num;
1138}
1139
1140/* Just read and notify events without processing them.
1141 * Used at the time of destroying event queues */
1142static void be_eq_clean(struct be_adapter *adapter,
1143 struct be_eq_obj *eq_obj)
1144{
1145 struct be_eq_entry *eqe;
1146 u16 num = 0;
1147
1148 while ((eqe = event_get(eq_obj)) != NULL) {
1149 eqe->evt = 0;
1150 num++;
1151 }
1152
1153 if (num)
1154 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1155}
1156
6b7c5b94
SP		 1157static void be_rx_q_clean(struct be_adapter *adapter)
1158{
1159 struct be_rx_page_info *page_info;
1160 struct be_queue_info *rxq = &adapter->rx_obj.q;
1161 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1162 struct be_eth_rx_compl *rxcp;
1163 u16 tail;
1164
1165 /* First cleanup pending rx completions */
1166 while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
1167 be_rx_compl_discard(adapter, rxcp);
a7a0ef31 1168 be_rx_compl_reset(rxcp);
8788fdc2 1169 be_cq_notify(adapter, rx_cq->id, true, 1);
6b7c5b94
SP		 1170 }
1171
1172 /* Then free posted rx buffer that were not used */
1173 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1174 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
6b7c5b94
SP		 1175 page_info = get_rx_page_info(adapter, tail);
1176 put_page(page_info->page);
1177 memset(page_info, 0, sizeof(*page_info));
1178 }
1179 BUG_ON(atomic_read(&rxq->used));
1180}
1181
a8e9179a 1182static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1183{
a8e9179a 1184 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1185 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1186 struct be_eth_tx_compl *txcp;
1187 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1188 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1189 struct sk_buff *sent_skb;
1190 bool dummy_wrb;
a8e9179a
SP		 1191
1192 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1193 do {
1194 while ((txcp = be_tx_compl_get(tx_cq))) {
1195 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1196 wrb_index, txcp);
1197 be_tx_compl_process(adapter, end_idx);
1198 cmpl++;
1199 }
1200 if (cmpl) {
1201 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1202 cmpl = 0;
1203 }
1204
1205 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1206 break;
1207
1208 mdelay(1);
1209 } while (true);
1210
1211 if (atomic_read(&txq->used))
1212 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1213 atomic_read(&txq->used));
b03388d6
SP		 1214
1215 /* free posted tx for which compls will never arrive */
1216 while (atomic_read(&txq->used)) {
1217 sent_skb = sent_skbs[txq->tail];
1218 end_idx = txq->tail;
1219 index_adv(&end_idx,
1220 wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
1221 be_tx_compl_process(adapter, end_idx);
1222 }
6b7c5b94
SP		 1223}
1224
5fb379ee
SP		 1225static void be_mcc_queues_destroy(struct be_adapter *adapter)
1226{
1227 struct be_queue_info *q;
5fb379ee 1228
8788fdc2 1229 q = &adapter->mcc_obj.q;
5fb379ee 1230 if (q->created)
8788fdc2 1231 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1232 be_queue_free(adapter, q);
1233
8788fdc2 1234 q = &adapter->mcc_obj.cq;
5fb379ee 1235 if (q->created)
8788fdc2 1236 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1237 be_queue_free(adapter, q);
1238}
1239
1240/* Must be called only after TX qs are created as MCC shares TX EQ */
1241static int be_mcc_queues_create(struct be_adapter *adapter)
1242{
1243 struct be_queue_info *q, *cq;
5fb379ee
SP		 1244
1245 /* Alloc MCC compl queue */
8788fdc2 1246 cq = &adapter->mcc_obj.cq;
5fb379ee 1247 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1248 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1249 goto err;
1250
1251 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1252 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1253 goto mcc_cq_free;
1254
1255 /* Alloc MCC queue */
8788fdc2 1256 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1257 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1258 goto mcc_cq_destroy;
1259
1260 /* Ask BE to create MCC queue */
8788fdc2 1261 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1262 goto mcc_q_free;
1263
1264 return 0;
1265
1266mcc_q_free:
1267 be_queue_free(adapter, q);
1268mcc_cq_destroy:
8788fdc2 1269 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1270mcc_cq_free:
1271 be_queue_free(adapter, cq);
1272err:
1273 return -1;
1274}
1275
6b7c5b94
SP		 1276static void be_tx_queues_destroy(struct be_adapter *adapter)
1277{
1278 struct be_queue_info *q;
1279
1280 q = &adapter->tx_obj.q;
a8e9179a 1281 if (q->created)
8788fdc2 1282 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1283 be_queue_free(adapter, q);
1284
1285 q = &adapter->tx_obj.cq;
1286 if (q->created)
8788fdc2 1287 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1288 be_queue_free(adapter, q);
1289
859b1e4e
SP		 1290 /* Clear any residual events */
1291 be_eq_clean(adapter, &adapter->tx_eq);
1292
6b7c5b94
SP		 1293 q = &adapter->tx_eq.q;
1294 if (q->created)
8788fdc2 1295 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1296 be_queue_free(adapter, q);
1297}
1298
1299static int be_tx_queues_create(struct be_adapter *adapter)
1300{
1301 struct be_queue_info *eq, *q, *cq;
1302
1303 adapter->tx_eq.max_eqd = 0;
1304 adapter->tx_eq.min_eqd = 0;
1305 adapter->tx_eq.cur_eqd = 96;
1306 adapter->tx_eq.enable_aic = false;
1307 /* Alloc Tx Event queue */
1308 eq = &adapter->tx_eq.q;
1309 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1310 return -1;
1311
1312 /* Ask BE to create Tx Event queue */
8788fdc2 1313 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94 1314 goto tx_eq_free;
ba343c77
SB		 1315 adapter->base_eq_id = adapter->tx_eq.q.id;
1316
6b7c5b94
SP		 1317 /* Alloc TX eth compl queue */
1318 cq = &adapter->tx_obj.cq;
1319 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1320 sizeof(struct be_eth_tx_compl)))
1321 goto tx_eq_destroy;
1322
1323 /* Ask BE to create Tx eth compl queue */
8788fdc2 1324 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1325 goto tx_cq_free;
1326
1327 /* Alloc TX eth queue */
1328 q = &adapter->tx_obj.q;
1329 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1330 goto tx_cq_destroy;
1331
1332 /* Ask BE to create Tx eth queue */
8788fdc2 1333 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1334 goto tx_q_free;
1335 return 0;
1336
1337tx_q_free:
1338 be_queue_free(adapter, q);
1339tx_cq_destroy:
8788fdc2 1340 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1341tx_cq_free:
1342 be_queue_free(adapter, cq);
1343tx_eq_destroy:
8788fdc2 1344 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1345tx_eq_free:
1346 be_queue_free(adapter, eq);
1347 return -1;
1348}
1349
1350static void be_rx_queues_destroy(struct be_adapter *adapter)
1351{
1352 struct be_queue_info *q;
1353
1354 q = &adapter->rx_obj.q;
1355 if (q->created) {
8788fdc2 1356 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
89420424
SP		 1357
1358 /* After the rxq is invalidated, wait for a grace time
1359 * of 1ms for all dma to end and the flush compl to arrive
1360 */
1361 mdelay(1);
6b7c5b94
SP		 1362 be_rx_q_clean(adapter);
1363 }
1364 be_queue_free(adapter, q);
1365
1366 q = &adapter->rx_obj.cq;
1367 if (q->created)
8788fdc2 1368 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1369 be_queue_free(adapter, q);
1370
859b1e4e
SP		 1371 /* Clear any residual events */
1372 be_eq_clean(adapter, &adapter->rx_eq);
1373
6b7c5b94
SP		 1374 q = &adapter->rx_eq.q;
1375 if (q->created)
8788fdc2 1376 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1377 be_queue_free(adapter, q);
1378}
1379
1380static int be_rx_queues_create(struct be_adapter *adapter)
1381{
1382 struct be_queue_info *eq, *q, *cq;
1383 int rc;
1384
6b7c5b94
SP		 1385 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
1386 adapter->rx_eq.max_eqd = BE_MAX_EQD;
1387 adapter->rx_eq.min_eqd = 0;
1388 adapter->rx_eq.cur_eqd = 0;
1389 adapter->rx_eq.enable_aic = true;
1390
1391 /* Alloc Rx Event queue */
1392 eq = &adapter->rx_eq.q;
1393 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1394 sizeof(struct be_eq_entry));
1395 if (rc)
1396 return rc;
1397
1398 /* Ask BE to create Rx Event queue */
8788fdc2 1399 rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
6b7c5b94
SP		 1400 if (rc)
1401 goto rx_eq_free;
1402
1403 /* Alloc RX eth compl queue */
1404 cq = &adapter->rx_obj.cq;
1405 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1406 sizeof(struct be_eth_rx_compl));
1407 if (rc)
1408 goto rx_eq_destroy;
1409
1410 /* Ask BE to create Rx eth compl queue */
8788fdc2 1411 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
6b7c5b94
SP		 1412 if (rc)
1413 goto rx_cq_free;
1414
1415 /* Alloc RX eth queue */
1416 q = &adapter->rx_obj.q;
1417 rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
1418 if (rc)
1419 goto rx_cq_destroy;
1420
1421 /* Ask BE to create Rx eth queue */
8788fdc2 1422 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
6b7c5b94
SP		 1423 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
1424 if (rc)
1425 goto rx_q_free;
1426
1427 return 0;
1428rx_q_free:
1429 be_queue_free(adapter, q);
1430rx_cq_destroy:
8788fdc2 1431 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1432rx_cq_free:
1433 be_queue_free(adapter, cq);
1434rx_eq_destroy:
8788fdc2 1435 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1436rx_eq_free:
1437 be_queue_free(adapter, eq);
1438 return rc;
1439}
6b7c5b94 1440
b628bde2
SP		 1441/* There are 8 evt ids per func. Retruns the evt id's bit number */
1442static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
1443{
ba343c77 1444 return eq_id - adapter->base_eq_id;
b628bde2
SP		 1445}
1446
6b7c5b94
SP		 1447static irqreturn_t be_intx(int irq, void *dev)
1448{
1449 struct be_adapter *adapter = dev;
8788fdc2 1450 int isr;
6b7c5b94 1451
8788fdc2 1452 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
55bdeed9 1453 (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
c001c213 1454 if (!isr)
8788fdc2 1455 return IRQ_NONE;
6b7c5b94 1456
8788fdc2
SP		 1457 event_handle(adapter, &adapter->tx_eq);
1458 event_handle(adapter, &adapter->rx_eq);
c001c213 1459
8788fdc2 1460 return IRQ_HANDLED;
6b7c5b94
SP		 1461}
1462
1463static irqreturn_t be_msix_rx(int irq, void *dev)
1464{
1465 struct be_adapter *adapter = dev;
1466
8788fdc2 1467 event_handle(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1468
1469 return IRQ_HANDLED;
1470}
1471
5fb379ee 1472static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1473{
1474 struct be_adapter *adapter = dev;
1475
8788fdc2 1476 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1477
1478 return IRQ_HANDLED;
1479}
1480
5be93b9a 1481static inline bool do_gro(struct be_adapter *adapter,
6b7c5b94
SP		 1482 struct be_eth_rx_compl *rxcp)
1483{
1484 int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1485 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1486
1487 if (err)
1488 drvr_stats(adapter)->be_rxcp_err++;
1489
5be93b9a 1490 return (tcp_frame && !err) ? true : false;
6b7c5b94
SP		 1491}
1492
1493int be_poll_rx(struct napi_struct *napi, int budget)
1494{
1495 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
1496 struct be_adapter *adapter =
1497 container_of(rx_eq, struct be_adapter, rx_eq);
1498 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1499 struct be_eth_rx_compl *rxcp;
1500 u32 work_done;
1501
b7b83ac3 1502 adapter->stats.drvr_stats.be_rx_polls++;
6b7c5b94
SP		 1503 for (work_done = 0; work_done < budget; work_done++) {
1504 rxcp = be_rx_compl_get(adapter);
1505 if (!rxcp)
1506 break;
1507
5be93b9a
AK		 1508 if (do_gro(adapter, rxcp))
1509 be_rx_compl_process_gro(adapter, rxcp);
6b7c5b94
SP		 1510 else
1511 be_rx_compl_process(adapter, rxcp);
a7a0ef31
SP		 1512
1513 be_rx_compl_reset(rxcp);
6b7c5b94
SP		 1514 }
1515
6b7c5b94
SP		 1516 /* Refill the queue */
1517 if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
1518 be_post_rx_frags(adapter);
1519
1520 /* All consumed */
1521 if (work_done < budget) {
1522 napi_complete(napi);
8788fdc2 1523 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1524 } else {
1525 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1526 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1527 }
1528 return work_done;
1529}
1530
f31e50a8
SP		 1531/* As TX and MCC share the same EQ check for both TX and MCC completions.
1532 * For TX/MCC we don't honour budget; consume everything
1533 */
1534static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1535{
f31e50a8
SP		 1536 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1537 struct be_adapter *adapter =
1538 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1539 struct be_queue_info *txq = &adapter->tx_obj.q;
1540 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1541 struct be_eth_tx_compl *txcp;
f31e50a8 1542 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1543 u16 end_idx;
1544
5fb379ee 1545 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1546 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1547 wrb_index, txcp);
6b7c5b94 1548 be_tx_compl_process(adapter, end_idx);
f31e50a8 1549 tx_compl++;
6b7c5b94
SP		 1550 }
1551
f31e50a8
SP		 1552 mcc_compl = be_process_mcc(adapter, &status);
1553
1554 napi_complete(napi);
1555
1556 if (mcc_compl) {
1557 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1558 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1559 }
1560
1561 if (tx_compl) {
1562 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1563
1564 /* As Tx wrbs have been freed up, wake up netdev queue if
1565 * it was stopped due to lack of tx wrbs.
1566 */
1567 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1568 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1569 netif_wake_queue(adapter->netdev);
1570 }
1571
1572 drvr_stats(adapter)->be_tx_events++;
f31e50a8 1573 drvr_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1574 }
6b7c5b94
SP		 1575
1576 return 1;
1577}
1578
ea1dae11
SP		 1579static void be_worker(struct work_struct *work)
1580{
1581 struct be_adapter *adapter =
1582 container_of(work, struct be_adapter, work.work);
ea1dae11 1583
b31c50a7 1584 be_cmd_get_stats(adapter, &adapter->stats.cmd);
ea1dae11
SP		 1585
1586 /* Set EQ delay */
1587 be_rx_eqd_update(adapter);
1588
4097f663
SP		 1589 be_tx_rate_update(adapter);
1590 be_rx_rate_update(adapter);
1591
ea1dae11
SP		 1592 if (adapter->rx_post_starved) {
1593 adapter->rx_post_starved = false;
1594 be_post_rx_frags(adapter);
1595 }
1596
1597 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1598}
1599
8d56ff11
SP		 1600static void be_msix_disable(struct be_adapter *adapter)
1601{
1602 if (adapter->msix_enabled) {
1603 pci_disable_msix(adapter->pdev);
1604 adapter->msix_enabled = false;
1605 }
1606}
1607
6b7c5b94
SP		 1608static void be_msix_enable(struct be_adapter *adapter)
1609{
1610 int i, status;
1611
1612 for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
1613 adapter->msix_entries[i].entry = i;
1614
1615 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1616 BE_NUM_MSIX_VECTORS);
1617 if (status == 0)
1618 adapter->msix_enabled = true;
6b7c5b94
SP		 1619}
1620
ba343c77
SB		 1621static void be_sriov_enable(struct be_adapter *adapter)
1622{
1623#ifdef CONFIG_PCI_IOV
1624 int status;
1625 if (be_physfn(adapter) && num_vfs) {
1626 status = pci_enable_sriov(adapter->pdev, num_vfs);
1627 adapter->sriov_enabled = status ? false : true;
1628 }
1629#endif
ba343c77
SB		 1630}
1631
1632static void be_sriov_disable(struct be_adapter *adapter)
1633{
1634#ifdef CONFIG_PCI_IOV
1635 if (adapter->sriov_enabled) {
1636 pci_disable_sriov(adapter->pdev);
1637 adapter->sriov_enabled = false;
1638 }
1639#endif
1640}
1641
6b7c5b94
SP		 1642static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
1643{
b628bde2
SP		 1644 return adapter->msix_entries[
1645 be_evt_bit_get(adapter, eq_id)].vector;
6b7c5b94
SP		 1646}
1647
b628bde2
SP		 1648static int be_request_irq(struct be_adapter *adapter,
1649 struct be_eq_obj *eq_obj,
1650 void *handler, char *desc)
6b7c5b94
SP		 1651{
1652 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1653 int vec;
1654
1655 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
1656 vec = be_msix_vec_get(adapter, eq_obj->q.id);
1657 return request_irq(vec, handler, 0, eq_obj->desc, adapter);
1658}
1659
1660static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
1661{
1662 int vec = be_msix_vec_get(adapter, eq_obj->q.id);
1663 free_irq(vec, adapter);
1664}
6b7c5b94 1665
b628bde2
SP		 1666static int be_msix_register(struct be_adapter *adapter)
1667{
1668 int status;
1669
1670 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
6b7c5b94
SP		 1671 if (status)
1672 goto err;
1673
b628bde2
SP		 1674 status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
1675 if (status)
1676 goto free_tx_irq;
1677
6b7c5b94 1678 return 0;
b628bde2
SP		 1679
1680free_tx_irq:
1681 be_free_irq(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1682err:
1683 dev_warn(&adapter->pdev->dev,
1684 "MSIX Request IRQ failed - err %d\n", status);
1685 pci_disable_msix(adapter->pdev);
1686 adapter->msix_enabled = false;
1687 return status;
1688}
1689
1690static int be_irq_register(struct be_adapter *adapter)
1691{
1692 struct net_device *netdev = adapter->netdev;
1693 int status;
1694
1695 if (adapter->msix_enabled) {
1696 status = be_msix_register(adapter);
1697 if (status == 0)
1698 goto done;
ba343c77
SB		 1699 /* INTx is not supported for VF */
1700 if (!be_physfn(adapter))
1701 return status;
6b7c5b94
SP		 1702 }
1703
1704 /* INTx */
1705 netdev->irq = adapter->pdev->irq;
1706 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
1707 adapter);
1708 if (status) {
1709 dev_err(&adapter->pdev->dev,
1710 "INTx request IRQ failed - err %d\n", status);
1711 return status;
1712 }
1713done:
1714 adapter->isr_registered = true;
1715 return 0;
1716}
1717
1718static void be_irq_unregister(struct be_adapter *adapter)
1719{
1720 struct net_device *netdev = adapter->netdev;
6b7c5b94
SP		 1721
1722 if (!adapter->isr_registered)
1723 return;
1724
1725 /* INTx */
1726 if (!adapter->msix_enabled) {
1727 free_irq(netdev->irq, adapter);
1728 goto done;
1729 }
1730
1731 /* MSIx */
b628bde2
SP		 1732 be_free_irq(adapter, &adapter->tx_eq);
1733 be_free_irq(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1734done:
1735 adapter->isr_registered = false;
6b7c5b94
SP		 1736}
1737
1738static int be_open(struct net_device *netdev)
1739{
1740 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1741 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1742 struct be_eq_obj *tx_eq = &adapter->tx_eq;
a8f447bd
SP		 1743 bool link_up;
1744 int status;
0388f251
SB		 1745 u8 mac_speed;
1746 u16 link_speed;
5fb379ee
SP		 1747
1748 /* First time posting */
1749 be_post_rx_frags(adapter);
1750
1751 napi_enable(&rx_eq->napi);
1752 napi_enable(&tx_eq->napi);
1753
1754 be_irq_register(adapter);
1755
8788fdc2 1756 be_intr_set(adapter, true);
5fb379ee
SP		 1757
1758 /* The evt queues are created in unarmed state; arm them */
8788fdc2
SP		 1759 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
1760 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee
SP		 1761
1762 /* Rx compl queue may be in unarmed state; rearm it */
8788fdc2 1763 be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
5fb379ee 1764
7a1e9b20
SP		 1765 /* Now that interrupts are on we can process async mcc */
1766 be_async_mcc_enable(adapter);
1767
0388f251
SB		 1768 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
1769 &link_speed);
a8f447bd 1770 if (status)
4f2aa89c 1771 goto ret_sts;
a8f447bd 1772 be_link_status_update(adapter, link_up);
5fb379ee 1773
ba343c77
SB		 1774 if (be_physfn(adapter))
1775 status = be_vid_config(adapter);
4f2aa89c
AK		 1776 if (status)
1777 goto ret_sts;
1778
ba343c77
SB		 1779 if (be_physfn(adapter)) {
1780 status = be_cmd_set_flow_control(adapter,
1781 adapter->tx_fc, adapter->rx_fc);
1782 if (status)
1783 goto ret_sts;
1784 }
4f2aa89c 1785
5fb379ee 1786 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
4f2aa89c
AK		 1787ret_sts:
1788 return status;
5fb379ee
SP		 1789}
1790
71d8d1b5
AK		 1791static int be_setup_wol(struct be_adapter *adapter, bool enable)
1792{
1793 struct be_dma_mem cmd;
1794 int status = 0;
1795 u8 mac[ETH_ALEN];
1796
1797 memset(mac, 0, ETH_ALEN);
1798
1799 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
1800 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
1801 if (cmd.va == NULL)
1802 return -1;
1803 memset(cmd.va, 0, cmd.size);
1804
1805 if (enable) {
1806 status = pci_write_config_dword(adapter->pdev,
1807 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
1808 if (status) {
1809 dev_err(&adapter->pdev->dev,
2381a55c 1810 "Could not enable Wake-on-lan\n");
71d8d1b5
AK		 1811 pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
1812 cmd.dma);
1813 return status;
1814 }
1815 status = be_cmd_enable_magic_wol(adapter,
1816 adapter->netdev->dev_addr, &cmd);
1817 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
1818 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
1819 } else {
1820 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
1821 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
1822 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
1823 }
1824
1825 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
1826 return status;
1827}
1828
5fb379ee
SP		 1829static int be_setup(struct be_adapter *adapter)
1830{
5fb379ee 1831 struct net_device *netdev = adapter->netdev;
ba343c77 1832 u32 cap_flags, en_flags, vf = 0;
6b7c5b94 1833 int status;
ba343c77
SB		 1834 u8 mac[ETH_ALEN];
1835
1836 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
6b7c5b94 1837
ba343c77
SB		 1838 if (be_physfn(adapter)) {
1839 cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
1840 BE_IF_FLAGS_PROMISCUOUS |
1841 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1842 en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
1843 }
73d540f2
SP		 1844
1845 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1846 netdev->dev_addr, false/* pmac_invalid */,
ba343c77 1847 &adapter->if_handle, &adapter->pmac_id, 0);
6b7c5b94
SP		 1848 if (status != 0)
1849 goto do_none;
1850
ba343c77
SB		 1851 if (be_physfn(adapter)) {
1852 while (vf < num_vfs) {
1853 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED
1854 | BE_IF_FLAGS_BROADCAST;
1855 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1856 mac, true, &adapter->vf_if_handle[vf],
1857 NULL, vf+1);
1858 if (status) {
1859 dev_err(&adapter->pdev->dev,
1860 "Interface Create failed for VF %d\n", vf);
1861 goto if_destroy;
1862 }
1863 vf++;
84e5b9f7 1864 }
ba343c77
SB		 1865 } else if (!be_physfn(adapter)) {
1866 status = be_cmd_mac_addr_query(adapter, mac,
1867 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
1868 if (!status) {
1869 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
1870 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
1871 }
1872 }
1873
6b7c5b94
SP		 1874 status = be_tx_queues_create(adapter);
1875 if (status != 0)
1876 goto if_destroy;
1877
1878 status = be_rx_queues_create(adapter);
1879 if (status != 0)
1880 goto tx_qs_destroy;
1881
5fb379ee
SP		 1882 status = be_mcc_queues_create(adapter);
1883 if (status != 0)
1884 goto rx_qs_destroy;
6b7c5b94 1885
0dffc83e
AK		 1886 adapter->link_speed = -1;
1887
6b7c5b94
SP		 1888 return 0;
1889
5fb379ee
SP		 1890rx_qs_destroy:
1891 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 1892tx_qs_destroy:
1893 be_tx_queues_destroy(adapter);
1894if_destroy:
ba343c77
SB		 1895 for (vf = 0; vf < num_vfs; vf++)
1896 if (adapter->vf_if_handle[vf])
1897 be_cmd_if_destroy(adapter, adapter->vf_if_handle[vf]);
8788fdc2 1898 be_cmd_if_destroy(adapter, adapter->if_handle);
6b7c5b94
SP		 1899do_none:
1900 return status;
1901}
1902
5fb379ee
SP		 1903static int be_clear(struct be_adapter *adapter)
1904{
1a8887d8 1905 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 1906 be_rx_queues_destroy(adapter);
1907 be_tx_queues_destroy(adapter);
1908
8788fdc2 1909 be_cmd_if_destroy(adapter, adapter->if_handle);
5fb379ee 1910
2243e2e9
SP		 1911 /* tell fw we're done with firing cmds */
1912 be_cmd_fw_clean(adapter);
5fb379ee
SP		 1913 return 0;
1914}
1915
6b7c5b94
SP		 1916static int be_close(struct net_device *netdev)
1917{
1918 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1919 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1920 struct be_eq_obj *tx_eq = &adapter->tx_eq;
1921 int vec;
1922
b305be78 1923 cancel_delayed_work_sync(&adapter->work);
6b7c5b94 1924
7a1e9b20
SP		 1925 be_async_mcc_disable(adapter);
1926
6b7c5b94
SP		 1927 netif_stop_queue(netdev);
1928 netif_carrier_off(netdev);
a8f447bd 1929 adapter->link_up = false;
6b7c5b94 1930
8788fdc2 1931 be_intr_set(adapter, false);
6b7c5b94
SP		 1932
1933 if (adapter->msix_enabled) {
1934 vec = be_msix_vec_get(adapter, tx_eq->q.id);
1935 synchronize_irq(vec);
1936 vec = be_msix_vec_get(adapter, rx_eq->q.id);
1937 synchronize_irq(vec);
1938 } else {
1939 synchronize_irq(netdev->irq);
1940 }
1941 be_irq_unregister(adapter);
1942
1943 napi_disable(&rx_eq->napi);
1944 napi_disable(&tx_eq->napi);
1945
a8e9179a
SP		 1946 /* Wait for all pending tx completions to arrive so that
1947 * all tx skbs are freed.
1948 */
1949 be_tx_compl_clean(adapter);
1950
6b7c5b94
SP		 1951 return 0;
1952}
1953
84517482
AK		 1954#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
1955char flash_cookie[2][16] = {"*** SE FLAS",
1956 "H DIRECTORY *** "};
fa9a6fed
SB		 1957
1958static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 1959 const u8 *p, u32 img_start, int image_size,
1960 int hdr_size)
fa9a6fed
SB		 1961{
1962 u32 crc_offset;
1963 u8 flashed_crc[4];
1964 int status;
3f0d4560
AK		 1965
1966 crc_offset = hdr_size + img_start + image_size - 4;
1967
fa9a6fed 1968 p += crc_offset;
3f0d4560
AK		 1969
1970 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 1971 (image_size - 4));
fa9a6fed
SB		 1972 if (status) {
1973 dev_err(&adapter->pdev->dev,
1974 "could not get crc from flash, not flashing redboot\n");
1975 return false;
1976 }
1977
1978 /*update redboot only if crc does not match*/
1979 if (!memcmp(flashed_crc, p, 4))
1980 return false;
1981 else
1982 return true;
fa9a6fed
SB		 1983}
1984
3f0d4560 1985static int be_flash_data(struct be_adapter *adapter,
84517482 1986 const struct firmware *fw,
3f0d4560
AK		 1987 struct be_dma_mem *flash_cmd, int num_of_images)
1988
84517482 1989{
3f0d4560
AK		 1990 int status = 0, i, filehdr_size = 0;
1991 u32 total_bytes = 0, flash_op;
84517482
AK		 1992 int num_bytes;
1993 const u8 *p = fw->data;
1994 struct be_cmd_write_flashrom *req = flash_cmd->va;
3f0d4560 1995 struct flash_comp *pflashcomp;
9fe96934 1996 int num_comp;
3f0d4560 1997
9fe96934 1998 struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 1999 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2000 FLASH_IMAGE_MAX_SIZE_g3},
2001 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2002 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2003 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2004 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2005 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2006 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2007 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2008 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2009 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2010 FLASH_IMAGE_MAX_SIZE_g3},
2011 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2012 FLASH_IMAGE_MAX_SIZE_g3},
2013 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 2014 FLASH_IMAGE_MAX_SIZE_g3},
2015 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
2016 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560
AK		 2017 };
2018 struct flash_comp gen2_flash_types[8] = {
2019 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2020 FLASH_IMAGE_MAX_SIZE_g2},
2021 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2022 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2023 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2024 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2025 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2026 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2027 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2028 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2029 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2030 FLASH_IMAGE_MAX_SIZE_g2},
2031 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2032 FLASH_IMAGE_MAX_SIZE_g2},
2033 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2034 FLASH_IMAGE_MAX_SIZE_g2}
2035 };
2036
2037 if (adapter->generation == BE_GEN3) {
2038 pflashcomp = gen3_flash_types;
2039 filehdr_size = sizeof(struct flash_file_hdr_g3);
9fe96934 2040 num_comp = 9;
3f0d4560
AK		 2041 } else {
2042 pflashcomp = gen2_flash_types;
2043 filehdr_size = sizeof(struct flash_file_hdr_g2);
9fe96934 2044 num_comp = 8;
84517482 2045 }
9fe96934
SB		 2046 for (i = 0; i < num_comp; i++) {
2047 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2048 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2049 continue;
3f0d4560
AK		 2050 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2051 (!be_flash_redboot(adapter, fw->data,
2052 pflashcomp[i].offset, pflashcomp[i].size,
2053 filehdr_size)))
2054 continue;
2055 p = fw->data;
2056 p += filehdr_size + pflashcomp[i].offset
2057 + (num_of_images * sizeof(struct image_hdr));
2058 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 2059 return -1;
3f0d4560
AK		 2060 total_bytes = pflashcomp[i].size;
2061 while (total_bytes) {
2062 if (total_bytes > 32*1024)
2063 num_bytes = 32*1024;
2064 else
2065 num_bytes = total_bytes;
2066 total_bytes -= num_bytes;
2067
2068 if (!total_bytes)
2069 flash_op = FLASHROM_OPER_FLASH;
2070 else
2071 flash_op = FLASHROM_OPER_SAVE;
2072 memcpy(req->params.data_buf, p, num_bytes);
2073 p += num_bytes;
2074 status = be_cmd_write_flashrom(adapter, flash_cmd,
2075 pflashcomp[i].optype, flash_op, num_bytes);
2076 if (status) {
2077 dev_err(&adapter->pdev->dev,
2078 "cmd to write to flash rom failed.\n");
2079 return -1;
2080 }
2081 yield();
84517482 2082 }
84517482 2083 }
84517482
AK		 2084 return 0;
2085}
2086
3f0d4560
AK		 2087static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2088{
2089 if (fhdr == NULL)
2090 return 0;
2091 if (fhdr->build[0] == '3')
2092 return BE_GEN3;
2093 else if (fhdr->build[0] == '2')
2094 return BE_GEN2;
2095 else
2096 return 0;
2097}
2098
84517482
AK		 2099int be_load_fw(struct be_adapter *adapter, u8 *func)
2100{
2101 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2102 const struct firmware *fw;
3f0d4560
AK		 2103 struct flash_file_hdr_g2 *fhdr;
2104 struct flash_file_hdr_g3 *fhdr3;
2105 struct image_hdr *img_hdr_ptr = NULL;
84517482 2106 struct be_dma_mem flash_cmd;
8b93b710 2107 int status, i = 0, num_imgs = 0;
84517482 2108 const u8 *p;
84517482 2109
84517482
AK		 2110 strcpy(fw_file, func);
2111
2112 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2113 if (status)
2114 goto fw_exit;
2115
2116 p = fw->data;
3f0d4560 2117 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2118 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2119
84517482
AK		 2120 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2121 flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
2122 &flash_cmd.dma);
2123 if (!flash_cmd.va) {
2124 status = -ENOMEM;
2125 dev_err(&adapter->pdev->dev,
2126 "Memory allocation failure while flashing\n");
2127 goto fw_exit;
2128 }
2129
3f0d4560
AK		 2130 if ((adapter->generation == BE_GEN3) &&
2131 (get_ufigen_type(fhdr) == BE_GEN3)) {
2132 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 2133 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2134 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 2135 img_hdr_ptr = (struct image_hdr *) (fw->data +
2136 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 2137 i * sizeof(struct image_hdr)));
2138 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2139 status = be_flash_data(adapter, fw, &flash_cmd,
2140 num_imgs);
3f0d4560
AK		 2141 }
2142 } else if ((adapter->generation == BE_GEN2) &&
2143 (get_ufigen_type(fhdr) == BE_GEN2)) {
2144 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2145 } else {
2146 dev_err(&adapter->pdev->dev,
2147 "UFI and Interface are not compatible for flashing\n");
2148 status = -1;
84517482
AK		 2149 }
2150
2151 pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
2152 flash_cmd.dma);
2153 if (status) {
2154 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2155 goto fw_exit;
2156 }
2157
af901ca1 2158 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2159
2160fw_exit:
2161 release_firmware(fw);
2162 return status;
2163}
2164
6b7c5b94
SP		 2165static struct net_device_ops be_netdev_ops = {
2166 .ndo_open = be_open,
2167 .ndo_stop = be_close,
2168 .ndo_start_xmit = be_xmit,
2169 .ndo_get_stats = be_get_stats,
2170 .ndo_set_rx_mode = be_set_multicast_list,
2171 .ndo_set_mac_address = be_mac_addr_set,
2172 .ndo_change_mtu = be_change_mtu,
2173 .ndo_validate_addr = eth_validate_addr,
2174 .ndo_vlan_rx_register = be_vlan_register,
2175 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2176 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
ba343c77 2177 .ndo_set_vf_mac = be_set_vf_mac
6b7c5b94
SP		 2178};
2179
2180static void be_netdev_init(struct net_device *netdev)
2181{
2182 struct be_adapter *adapter = netdev_priv(netdev);
2183
2184 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
583e3f34
AK		 2185 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
2186 NETIF_F_GRO;
6b7c5b94 2187
51c59870
AK		 2188 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
2189
6b7c5b94
SP		 2190 netdev->flags |= IFF_MULTICAST;
2191
728a9972
AK		 2192 adapter->rx_csum = true;
2193
9e90c961
AK		 2194 /* Default settings for Rx and Tx flow control */
2195 adapter->rx_fc = true;
2196 adapter->tx_fc = true;
2197
c190e3c8
AK		 2198 netif_set_gso_max_size(netdev, 65535);
2199
6b7c5b94
SP		 2200 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2201
2202 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2203
6b7c5b94
SP		 2204 netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
2205 BE_NAPI_WEIGHT);
5fb379ee 2206 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94
SP		 2207 BE_NAPI_WEIGHT);
2208
2209 netif_carrier_off(netdev);
2210 netif_stop_queue(netdev);
2211}
2212
2213static void be_unmap_pci_bars(struct be_adapter *adapter)
2214{
8788fdc2
SP		 2215 if (adapter->csr)
2216 iounmap(adapter->csr);
2217 if (adapter->db)
2218 iounmap(adapter->db);
ba343c77 2219 if (adapter->pcicfg && be_physfn(adapter))
8788fdc2 2220 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2221}
2222
2223static int be_map_pci_bars(struct be_adapter *adapter)
2224{
2225 u8 __iomem *addr;
ba343c77 2226 int pcicfg_reg, db_reg;
6b7c5b94 2227
ba343c77
SB		 2228 if (be_physfn(adapter)) {
2229 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2230 pci_resource_len(adapter->pdev, 2));
2231 if (addr == NULL)
2232 return -ENOMEM;
2233 adapter->csr = addr;
2234 }
6b7c5b94 2235
ba343c77 2236 if (adapter->generation == BE_GEN2) {
7b139c83 2237 pcicfg_reg = 1;
ba343c77
SB		 2238 db_reg = 4;
2239 } else {
7b139c83 2240 pcicfg_reg = 0;
ba343c77
SB		 2241 if (be_physfn(adapter))
2242 db_reg = 4;
2243 else
2244 db_reg = 0;
2245 }
2246 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
2247 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 2248 if (addr == NULL)
2249 goto pci_map_err;
ba343c77
SB		 2250 adapter->db = addr;
2251
2252 if (be_physfn(adapter)) {
2253 addr = ioremap_nocache(
2254 pci_resource_start(adapter->pdev, pcicfg_reg),
2255 pci_resource_len(adapter->pdev, pcicfg_reg));
2256 if (addr == NULL)
2257 goto pci_map_err;
2258 adapter->pcicfg = addr;
2259 } else
2260 adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
6b7c5b94
SP		 2261
2262 return 0;
2263pci_map_err:
2264 be_unmap_pci_bars(adapter);
2265 return -ENOMEM;
2266}
2267
2268
2269static void be_ctrl_cleanup(struct be_adapter *adapter)
2270{
8788fdc2 2271 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2272
2273 be_unmap_pci_bars(adapter);
2274
2275 if (mem->va)
2276 pci_free_consistent(adapter->pdev, mem->size,
2277 mem->va, mem->dma);
e7b909a6
SP		 2278
2279 mem = &adapter->mc_cmd_mem;
2280 if (mem->va)
2281 pci_free_consistent(adapter->pdev, mem->size,
2282 mem->va, mem->dma);
6b7c5b94
SP		 2283}
2284
6b7c5b94
SP		 2285static int be_ctrl_init(struct be_adapter *adapter)
2286{
8788fdc2
SP		 2287 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2288 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2289 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2290 int status;
6b7c5b94
SP		 2291
2292 status = be_map_pci_bars(adapter);
2293 if (status)
e7b909a6 2294 goto done;
6b7c5b94
SP		 2295
2296 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2297 mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
2298 mbox_mem_alloc->size, &mbox_mem_alloc->dma);
2299 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2300 status = -ENOMEM;
2301 goto unmap_pci_bars;
6b7c5b94 2302 }
e7b909a6 2303
6b7c5b94
SP		 2304 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2305 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2306 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2307 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2308
2309 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2310 mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
2311 &mc_cmd_mem->dma);
2312 if (mc_cmd_mem->va == NULL) {
2313 status = -ENOMEM;
2314 goto free_mbox;
2315 }
2316 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2317
8788fdc2
SP		 2318 spin_lock_init(&adapter->mbox_lock);
2319 spin_lock_init(&adapter->mcc_lock);
2320 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2321
dd131e76 2322 init_completion(&adapter->flash_compl);
cf588477 2323 pci_save_state(adapter->pdev);
6b7c5b94 2324 return 0;
e7b909a6
SP		 2325
2326free_mbox:
2327 pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
2328 mbox_mem_alloc->va, mbox_mem_alloc->dma);
2329
2330unmap_pci_bars:
2331 be_unmap_pci_bars(adapter);
2332
2333done:
2334 return status;
6b7c5b94
SP		 2335}
2336
2337static void be_stats_cleanup(struct be_adapter *adapter)
2338{
2339 struct be_stats_obj *stats = &adapter->stats;
2340 struct be_dma_mem *cmd = &stats->cmd;
2341
2342 if (cmd->va)
2343 pci_free_consistent(adapter->pdev, cmd->size,
2344 cmd->va, cmd->dma);
2345}
2346
2347static int be_stats_init(struct be_adapter *adapter)
2348{
2349 struct be_stats_obj *stats = &adapter->stats;
2350 struct be_dma_mem *cmd = &stats->cmd;
2351
2352 cmd->size = sizeof(struct be_cmd_req_get_stats);
2353 cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
2354 if (cmd->va == NULL)
2355 return -1;
d291b9af 2356 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2357 return 0;
2358}
2359
2360static void __devexit be_remove(struct pci_dev *pdev)
2361{
2362 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2363
6b7c5b94
SP		 2364 if (!adapter)
2365 return;
2366
2367 unregister_netdev(adapter->netdev);
2368
5fb379ee
SP		 2369 be_clear(adapter);
2370
6b7c5b94
SP		 2371 be_stats_cleanup(adapter);
2372
2373 be_ctrl_cleanup(adapter);
2374
ba343c77
SB		 2375 be_sriov_disable(adapter);
2376
8d56ff11 2377 be_msix_disable(adapter);
6b7c5b94
SP		 2378
2379 pci_set_drvdata(pdev, NULL);
2380 pci_release_regions(pdev);
2381 pci_disable_device(pdev);
2382
2383 free_netdev(adapter->netdev);
2384}
2385
2243e2e9 2386static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2387{
6b7c5b94 2388 int status;
2243e2e9 2389 u8 mac[ETH_ALEN];
6b7c5b94 2390
2243e2e9 2391 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2392 if (status)
2393 return status;
2394
2243e2e9
SP		 2395 status = be_cmd_query_fw_cfg(adapter,
2396 &adapter->port_num, &adapter->cap);
43a04fdc
SP		 2397 if (status)
2398 return status;
2399
2243e2e9 2400 memset(mac, 0, ETH_ALEN);
ba343c77
SB		 2401
2402 if (be_physfn(adapter)) {
2403 status = be_cmd_mac_addr_query(adapter, mac,
2243e2e9 2404 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
ca9e4988 2405
ba343c77
SB		 2406 if (status)
2407 return status;
ca9e4988 2408
ba343c77
SB		 2409 if (!is_valid_ether_addr(mac))
2410 return -EADDRNOTAVAIL;
2411
2412 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2413 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2414 }
6b7c5b94 2415
82903e4b
AK		 2416 if (adapter->cap & 0x400)
2417 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2418 else
2419 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2420
2243e2e9 2421 return 0;
6b7c5b94
SP		 2422}
2423
2424static int __devinit be_probe(struct pci_dev *pdev,
2425 const struct pci_device_id *pdev_id)
2426{
2427 int status = 0;
2428 struct be_adapter *adapter;
2429 struct net_device *netdev;
6b7c5b94 2430
ba343c77 2431
6b7c5b94
SP		 2432 status = pci_enable_device(pdev);
2433 if (status)
2434 goto do_none;
2435
2436 status = pci_request_regions(pdev, DRV_NAME);
2437 if (status)
2438 goto disable_dev;
2439 pci_set_master(pdev);
2440
2441 netdev = alloc_etherdev(sizeof(struct be_adapter));
2442 if (netdev == NULL) {
2443 status = -ENOMEM;
2444 goto rel_reg;
2445 }
2446 adapter = netdev_priv(netdev);
7b139c83
AK		 2447
2448 switch (pdev->device) {
2449 case BE_DEVICE_ID1:
2450 case OC_DEVICE_ID1:
2451 adapter->generation = BE_GEN2;
2452 break;
2453 case BE_DEVICE_ID2:
2454 case OC_DEVICE_ID2:
2455 adapter->generation = BE_GEN3;
2456 break;
2457 default:
2458 adapter->generation = 0;
2459 }
2460
6b7c5b94
SP		 2461 adapter->pdev = pdev;
2462 pci_set_drvdata(pdev, adapter);
2463 adapter->netdev = netdev;
2243e2e9
SP		 2464 be_netdev_init(netdev);
2465 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94
SP		 2466
2467 be_msix_enable(adapter);
2468
e930438c 2469 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2470 if (!status) {
2471 netdev->features |= NETIF_F_HIGHDMA;
2472 } else {
e930438c 2473 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2474 if (status) {
2475 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2476 goto free_netdev;
2477 }
2478 }
2479
ba343c77
SB		 2480 be_sriov_enable(adapter);
2481
6b7c5b94
SP		 2482 status = be_ctrl_init(adapter);
2483 if (status)
2484 goto free_netdev;
2485
2243e2e9 2486 /* sync up with fw's ready state */
ba343c77
SB		 2487 if (be_physfn(adapter)) {
2488 status = be_cmd_POST(adapter);
2489 if (status)
2490 goto ctrl_clean;
ba343c77 2491 }
6b7c5b94 2492
2243e2e9
SP		 2493 /* tell fw we're ready to fire cmds */
2494 status = be_cmd_fw_init(adapter);
6b7c5b94 2495 if (status)
2243e2e9
SP		 2496 goto ctrl_clean;
2497
556ae191
SB		 2498 if (be_physfn(adapter)) {
2499 status = be_cmd_reset_function(adapter);
2500 if (status)
2501 goto ctrl_clean;
2502 }
2503
2243e2e9
SP		 2504 status = be_stats_init(adapter);
2505 if (status)
2506 goto ctrl_clean;
2507
2508 status = be_get_config(adapter);
6b7c5b94
SP		 2509 if (status)
2510 goto stats_clean;
6b7c5b94
SP		 2511
2512 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 2513
5fb379ee
SP		 2514 status = be_setup(adapter);
2515 if (status)
2516 goto stats_clean;
2243e2e9 2517
6b7c5b94
SP		 2518 status = register_netdev(netdev);
2519 if (status != 0)
5fb379ee 2520 goto unsetup;
6b7c5b94 2521
c4ca2374 2522 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
6b7c5b94
SP		 2523 return 0;
2524
5fb379ee
SP		 2525unsetup:
2526 be_clear(adapter);
6b7c5b94
SP		 2527stats_clean:
2528 be_stats_cleanup(adapter);
2529ctrl_clean:
2530 be_ctrl_cleanup(adapter);
2531free_netdev:
8d56ff11 2532 be_msix_disable(adapter);
ba343c77 2533 be_sriov_disable(adapter);
6b7c5b94 2534 free_netdev(adapter->netdev);
8d56ff11 2535 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 2536rel_reg:
2537 pci_release_regions(pdev);
2538disable_dev:
2539 pci_disable_device(pdev);
2540do_none:
c4ca2374 2541 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 2542 return status;
2543}
2544
2545static int be_suspend(struct pci_dev *pdev, pm_message_t state)
2546{
2547 struct be_adapter *adapter = pci_get_drvdata(pdev);
2548 struct net_device *netdev = adapter->netdev;
2549
71d8d1b5
AK		 2550 if (adapter->wol)
2551 be_setup_wol(adapter, true);
2552
6b7c5b94
SP		 2553 netif_device_detach(netdev);
2554 if (netif_running(netdev)) {
2555 rtnl_lock();
2556 be_close(netdev);
2557 rtnl_unlock();
2558 }
9e90c961 2559 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 2560 be_clear(adapter);
6b7c5b94
SP		 2561
2562 pci_save_state(pdev);
2563 pci_disable_device(pdev);
2564 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2565 return 0;
2566}
2567
2568static int be_resume(struct pci_dev *pdev)
2569{
2570 int status = 0;
2571 struct be_adapter *adapter = pci_get_drvdata(pdev);
2572 struct net_device *netdev = adapter->netdev;
2573
2574 netif_device_detach(netdev);
2575
2576 status = pci_enable_device(pdev);
2577 if (status)
2578 return status;
2579
2580 pci_set_power_state(pdev, 0);
2581 pci_restore_state(pdev);
2582
2243e2e9
SP		 2583 /* tell fw we're ready to fire cmds */
2584 status = be_cmd_fw_init(adapter);
2585 if (status)
2586 return status;
2587
9b0365f1 2588 be_setup(adapter);
6b7c5b94
SP		 2589 if (netif_running(netdev)) {
2590 rtnl_lock();
2591 be_open(netdev);
2592 rtnl_unlock();
2593 }
2594 netif_device_attach(netdev);
71d8d1b5
AK		 2595
2596 if (adapter->wol)
2597 be_setup_wol(adapter, false);
6b7c5b94
SP		 2598 return 0;
2599}
2600
82456b03
SP		 2601/*
2602 * An FLR will stop BE from DMAing any data.
2603 */
2604static void be_shutdown(struct pci_dev *pdev)
2605{
2606 struct be_adapter *adapter = pci_get_drvdata(pdev);
2607 struct net_device *netdev = adapter->netdev;
2608
2609 netif_device_detach(netdev);
2610
2611 be_cmd_reset_function(adapter);
2612
2613 if (adapter->wol)
2614 be_setup_wol(adapter, true);
2615
2616 pci_disable_device(pdev);
82456b03
SP		 2617}
2618
cf588477
SP		 2619static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
2620 pci_channel_state_t state)
2621{
2622 struct be_adapter *adapter = pci_get_drvdata(pdev);
2623 struct net_device *netdev = adapter->netdev;
2624
2625 dev_err(&adapter->pdev->dev, "EEH error detected\n");
2626
2627 adapter->eeh_err = true;
2628
2629 netif_device_detach(netdev);
2630
2631 if (netif_running(netdev)) {
2632 rtnl_lock();
2633 be_close(netdev);
2634 rtnl_unlock();
2635 }
2636 be_clear(adapter);
2637
2638 if (state == pci_channel_io_perm_failure)
2639 return PCI_ERS_RESULT_DISCONNECT;
2640
2641 pci_disable_device(pdev);
2642
2643 return PCI_ERS_RESULT_NEED_RESET;
2644}
2645
2646static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
2647{
2648 struct be_adapter *adapter = pci_get_drvdata(pdev);
2649 int status;
2650
2651 dev_info(&adapter->pdev->dev, "EEH reset\n");
2652 adapter->eeh_err = false;
2653
2654 status = pci_enable_device(pdev);
2655 if (status)
2656 return PCI_ERS_RESULT_DISCONNECT;
2657
2658 pci_set_master(pdev);
2659 pci_set_power_state(pdev, 0);
2660 pci_restore_state(pdev);
2661
2662 /* Check if card is ok and fw is ready */
2663 status = be_cmd_POST(adapter);
2664 if (status)
2665 return PCI_ERS_RESULT_DISCONNECT;
2666
2667 return PCI_ERS_RESULT_RECOVERED;
2668}
2669
2670static void be_eeh_resume(struct pci_dev *pdev)
2671{
2672 int status = 0;
2673 struct be_adapter *adapter = pci_get_drvdata(pdev);
2674 struct net_device *netdev = adapter->netdev;
2675
2676 dev_info(&adapter->pdev->dev, "EEH resume\n");
2677
2678 pci_save_state(pdev);
2679
2680 /* tell fw we're ready to fire cmds */
2681 status = be_cmd_fw_init(adapter);
2682 if (status)
2683 goto err;
2684
2685 status = be_setup(adapter);
2686 if (status)
2687 goto err;
2688
2689 if (netif_running(netdev)) {
2690 status = be_open(netdev);
2691 if (status)
2692 goto err;
2693 }
2694 netif_device_attach(netdev);
2695 return;
2696err:
2697 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 2698}
2699
2700static struct pci_error_handlers be_eeh_handlers = {
2701 .error_detected = be_eeh_err_detected,
2702 .slot_reset = be_eeh_reset,
2703 .resume = be_eeh_resume,
2704};
2705
6b7c5b94
SP		 2706static struct pci_driver be_driver = {
2707 .name = DRV_NAME,
2708 .id_table = be_dev_ids,
2709 .probe = be_probe,
2710 .remove = be_remove,
2711 .suspend = be_suspend,
cf588477 2712 .resume = be_resume,
82456b03 2713 .shutdown = be_shutdown,
cf588477 2714 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 2715};
2716
2717static int __init be_init_module(void)
2718{
8e95a202
JP		 2719 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
2720 rx_frag_size != 2048) {
6b7c5b94
SP		 2721 printk(KERN_WARNING DRV_NAME
2722 " : Module param rx_frag_size must be 2048/4096/8192."
2723 " Using 2048\n");
2724 rx_frag_size = 2048;
2725 }
6b7c5b94 2726
ba343c77
SB		 2727 if (num_vfs > 32) {
2728 printk(KERN_WARNING DRV_NAME
2729 " : Module param num_vfs must not be greater than 32."
2730 "Using 32\n");
2731 num_vfs = 32;
2732 }
2733
6b7c5b94
SP		 2734 return pci_register_driver(&be_driver);
2735}
2736module_init(be_init_module);
2737
2738static void __exit be_exit_module(void)
2739{
2740 pci_unregister_driver(&be_driver);
2741}
2742module_exit(be_exit_module);
Clone of davem's net-next-2.6 tree