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net/pcmcia/3c589_cs: using netdev_info and friends where appropriate
[net-next-2.6.git] / drivers / net / benet / be_main.c
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
28static unsigned int rx_frag_size = 2048;
29module_param(rx_frag_size, uint, S_IRUGO);
30MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
31
6b7c5b94 32static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 33 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 34 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 35 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
36 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
6b7c5b94
SP		 37 { 0 }
38};
39MODULE_DEVICE_TABLE(pci, be_dev_ids);
40
41static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
42{
43 struct be_dma_mem *mem = &q->dma_mem;
44 if (mem->va)
45 pci_free_consistent(adapter->pdev, mem->size,
46 mem->va, mem->dma);
47}
48
49static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
50 u16 len, u16 entry_size)
51{
52 struct be_dma_mem *mem = &q->dma_mem;
53
54 memset(q, 0, sizeof(*q));
55 q->len = len;
56 q->entry_size = entry_size;
57 mem->size = len * entry_size;
58 mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
59 if (!mem->va)
60 return -1;
61 memset(mem->va, 0, mem->size);
62 return 0;
63}
64
8788fdc2 65static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 66{
8788fdc2 67 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 68 u32 reg = ioread32(addr);
69 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 70
cf588477
SP		 71 if (adapter->eeh_err)
72 return;
73
5f0b849e 74 if (!enabled && enable)
6b7c5b94 75 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 76 else if (enabled && !enable)
6b7c5b94 77 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 78 else
6b7c5b94 79 return;
5f0b849e 80
6b7c5b94
SP		 81 iowrite32(reg, addr);
82}
83
8788fdc2 84static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 85{
86 u32 val = 0;
87 val |= qid & DB_RQ_RING_ID_MASK;
88 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
8788fdc2 89 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 90}
91
8788fdc2 92static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 93{
94 u32 val = 0;
95 val |= qid & DB_TXULP_RING_ID_MASK;
96 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
8788fdc2 97 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 98}
99
8788fdc2 100static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 101 bool arm, bool clear_int, u16 num_popped)
102{
103 u32 val = 0;
104 val |= qid & DB_EQ_RING_ID_MASK;
cf588477
SP		 105
106 if (adapter->eeh_err)
107 return;
108
6b7c5b94
SP		 109 if (arm)
110 val |= 1 << DB_EQ_REARM_SHIFT;
111 if (clear_int)
112 val |= 1 << DB_EQ_CLR_SHIFT;
113 val |= 1 << DB_EQ_EVNT_SHIFT;
114 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 115 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 116}
117
8788fdc2 118void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 119{
120 u32 val = 0;
121 val |= qid & DB_CQ_RING_ID_MASK;
cf588477
SP		 122
123 if (adapter->eeh_err)
124 return;
125
6b7c5b94
SP		 126 if (arm)
127 val |= 1 << DB_CQ_REARM_SHIFT;
128 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 129 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 130}
131
6b7c5b94
SP		 132static int be_mac_addr_set(struct net_device *netdev, void *p)
133{
134 struct be_adapter *adapter = netdev_priv(netdev);
135 struct sockaddr *addr = p;
136 int status = 0;
137
ca9e4988
AK		 138 if (!is_valid_ether_addr(addr->sa_data))
139 return -EADDRNOTAVAIL;
140
a65027e4
SP		 141 status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
142 if (status)
143 return status;
6b7c5b94 144
a65027e4
SP		 145 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
146 adapter->if_handle, &adapter->pmac_id);
6b7c5b94
SP		 147 if (!status)
148 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
149
150 return status;
151}
152
b31c50a7 153void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94
SP		 154{
155 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
156 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
157 struct be_port_rxf_stats *port_stats =
158 &rxf_stats->port[adapter->port_num];
78122a52 159 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 160 struct be_erx_stats *erx_stats = &hw_stats->erx;
6b7c5b94 161
91992e44
AK		 162 dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
163 dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
164 dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
165 dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 166
167 /* bad pkts received */
168 dev_stats->rx_errors = port_stats->rx_crc_errors +
169 port_stats->rx_alignment_symbol_errors +
170 port_stats->rx_in_range_errors +
68110868
SP		 171 port_stats->rx_out_range_errors +
172 port_stats->rx_frame_too_long +
173 port_stats->rx_dropped_too_small +
174 port_stats->rx_dropped_too_short +
175 port_stats->rx_dropped_header_too_small +
176 port_stats->rx_dropped_tcp_length +
177 port_stats->rx_dropped_runt +
178 port_stats->rx_tcp_checksum_errs +
179 port_stats->rx_ip_checksum_errs +
180 port_stats->rx_udp_checksum_errs;
181
182 /* no space in linux buffers: best possible approximation */
01ed30da
SP		 183 dev_stats->rx_dropped =
184 erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
6b7c5b94
SP		 185
186 /* detailed rx errors */
187 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 188 port_stats->rx_out_range_errors +
189 port_stats->rx_frame_too_long;
190
6b7c5b94
SP		 191 /* receive ring buffer overflow */
192 dev_stats->rx_over_errors = 0;
68110868 193
6b7c5b94
SP		 194 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
195
196 /* frame alignment errors */
197 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 198
6b7c5b94
SP		 199 /* receiver fifo overrun */
200 /* drops_no_pbuf is no per i/f, it's per BE card */
201 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
202 port_stats->rx_input_fifo_overflow +
203 rxf_stats->rx_drops_no_pbuf;
204 /* receiver missed packetd */
205 dev_stats->rx_missed_errors = 0;
68110868
SP		 206
207 /* packet transmit problems */
208 dev_stats->tx_errors = 0;
209
210 /* no space available in linux */
211 dev_stats->tx_dropped = 0;
212
c5b9b92e 213 dev_stats->multicast = port_stats->rx_multicast_frames;
68110868
SP		 214 dev_stats->collisions = 0;
215
6b7c5b94
SP		 216 /* detailed tx_errors */
217 dev_stats->tx_aborted_errors = 0;
218 dev_stats->tx_carrier_errors = 0;
219 dev_stats->tx_fifo_errors = 0;
220 dev_stats->tx_heartbeat_errors = 0;
221 dev_stats->tx_window_errors = 0;
222}
223
8788fdc2 224void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 225{
6b7c5b94
SP		 226 struct net_device *netdev = adapter->netdev;
227
6b7c5b94 228 /* If link came up or went down */
a8f447bd 229 if (adapter->link_up != link_up) {
0dffc83e 230 adapter->link_speed = -1;
a8f447bd 231 if (link_up) {
6b7c5b94
SP		 232 netif_start_queue(netdev);
233 netif_carrier_on(netdev);
234 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd
SP		 235 } else {
236 netif_stop_queue(netdev);
237 netif_carrier_off(netdev);
238 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 239 }
a8f447bd 240 adapter->link_up = link_up;
6b7c5b94 241 }
6b7c5b94
SP		 242}
243
244/* Update the EQ delay n BE based on the RX frags consumed / sec */
245static void be_rx_eqd_update(struct be_adapter *adapter)
246{
6b7c5b94
SP		 247 struct be_eq_obj *rx_eq = &adapter->rx_eq;
248 struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
4097f663
SP		 249 ulong now = jiffies;
250 u32 eqd;
251
252 if (!rx_eq->enable_aic)
253 return;
254
255 /* Wrapped around */
256 if (time_before(now, stats->rx_fps_jiffies)) {
257 stats->rx_fps_jiffies = now;
258 return;
259 }
6b7c5b94
SP		 260
261 /* Update once a second */
4097f663 262 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 263 return;
264
265 stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
4097f663 266 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 267
4097f663 268 stats->rx_fps_jiffies = now;
6b7c5b94
SP		 269 stats->be_prev_rx_frags = stats->be_rx_frags;
270 eqd = stats->be_rx_fps / 110000;
271 eqd = eqd << 3;
272 if (eqd > rx_eq->max_eqd)
273 eqd = rx_eq->max_eqd;
274 if (eqd < rx_eq->min_eqd)
275 eqd = rx_eq->min_eqd;
276 if (eqd < 10)
277 eqd = 0;
278 if (eqd != rx_eq->cur_eqd)
8788fdc2 279 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 280
281 rx_eq->cur_eqd = eqd;
282}
283
6b7c5b94
SP		 284static struct net_device_stats *be_get_stats(struct net_device *dev)
285{
78122a52 286 return &dev->stats;
6b7c5b94
SP		 287}
288
65f71b8b
SH		 289static u32 be_calc_rate(u64 bytes, unsigned long ticks)
290{
291 u64 rate = bytes;
292
293 do_div(rate, ticks / HZ);
294 rate <<= 3; /* bytes/sec -> bits/sec */
295 do_div(rate, 1000000ul); /* MB/Sec */
296
297 return rate;
298}
299
4097f663
SP		 300static void be_tx_rate_update(struct be_adapter *adapter)
301{
302 struct be_drvr_stats *stats = drvr_stats(adapter);
303 ulong now = jiffies;
304
305 /* Wrapped around? */
306 if (time_before(now, stats->be_tx_jiffies)) {
307 stats->be_tx_jiffies = now;
308 return;
309 }
310
311 /* Update tx rate once in two seconds */
312 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 313 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
314 - stats->be_tx_bytes_prev,
315 now - stats->be_tx_jiffies);
4097f663
SP		 316 stats->be_tx_jiffies = now;
317 stats->be_tx_bytes_prev = stats->be_tx_bytes;
318 }
319}
320
6b7c5b94 321static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 322 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 323{
4097f663 324 struct be_drvr_stats *stats = drvr_stats(adapter);
6b7c5b94
SP		 325 stats->be_tx_reqs++;
326 stats->be_tx_wrbs += wrb_cnt;
327 stats->be_tx_bytes += copied;
91992e44 328 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 329 if (stopped)
330 stats->be_tx_stops++;
6b7c5b94
SP		 331}
332
333/* Determine number of WRB entries needed to xmit data in an skb */
334static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
335{
ebc8d2ab
DM		 336 int cnt = (skb->len > skb->data_len);
337
338 cnt += skb_shinfo(skb)->nr_frags;
339
6b7c5b94
SP		 340 /* to account for hdr wrb */
341 cnt++;
342 if (cnt & 1) {
343 /* add a dummy to make it an even num */
344 cnt++;
345 *dummy = true;
346 } else
347 *dummy = false;
348 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
349 return cnt;
350}
351
352static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
353{
354 wrb->frag_pa_hi = upper_32_bits(addr);
355 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
356 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
357}
358
359static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
360 bool vlan, u32 wrb_cnt, u32 len)
361{
362 memset(hdr, 0, sizeof(*hdr));
363
364 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
365
366 if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) {
367 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
368 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
369 hdr, skb_shinfo(skb)->gso_size);
370 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
371 if (is_tcp_pkt(skb))
372 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
373 else if (is_udp_pkt(skb))
374 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
375 }
376
377 if (vlan && vlan_tx_tag_present(skb)) {
378 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
379 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
380 hdr, vlan_tx_tag_get(skb));
381 }
382
383 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
384 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
385 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
386 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
387}
388
7101e111
SP		 389static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
390 bool unmap_single)
391{
392 dma_addr_t dma;
393
394 be_dws_le_to_cpu(wrb, sizeof(*wrb));
395
396 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
397 if (dma != 0) {
398 if (unmap_single)
399 pci_unmap_single(pdev, dma, wrb->frag_len,
400 PCI_DMA_TODEVICE);
401 else
402 pci_unmap_page(pdev, dma, wrb->frag_len,
403 PCI_DMA_TODEVICE);
404 }
405}
6b7c5b94
SP		 406
407static int make_tx_wrbs(struct be_adapter *adapter,
408 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
409{
7101e111
SP		 410 dma_addr_t busaddr;
411 int i, copied = 0;
6b7c5b94
SP		 412 struct pci_dev *pdev = adapter->pdev;
413 struct sk_buff *first_skb = skb;
414 struct be_queue_info *txq = &adapter->tx_obj.q;
415 struct be_eth_wrb *wrb;
416 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 417 bool map_single = false;
418 u16 map_head;
6b7c5b94 419
6b7c5b94
SP		 420 hdr = queue_head_node(txq);
421 queue_head_inc(txq);
7101e111 422 map_head = txq->head;
6b7c5b94 423
ebc8d2ab
DM		 424 if (skb->len > skb->data_len) {
425 int len = skb->len - skb->data_len;
a73b796e
AD		 426 busaddr = pci_map_single(pdev, skb->data, len,
427 PCI_DMA_TODEVICE);
7101e111
SP		 428 if (pci_dma_mapping_error(pdev, busaddr))
429 goto dma_err;
430 map_single = true;
ebc8d2ab
DM		 431 wrb = queue_head_node(txq);
432 wrb_fill(wrb, busaddr, len);
433 be_dws_cpu_to_le(wrb, sizeof(*wrb));
434 queue_head_inc(txq);
435 copied += len;
436 }
6b7c5b94 437
ebc8d2ab
DM		 438 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
439 struct skb_frag_struct *frag =
440 &skb_shinfo(skb)->frags[i];
a73b796e
AD		 441 busaddr = pci_map_page(pdev, frag->page,
442 frag->page_offset,
443 frag->size, PCI_DMA_TODEVICE);
7101e111
SP		 444 if (pci_dma_mapping_error(pdev, busaddr))
445 goto dma_err;
ebc8d2ab
DM		 446 wrb = queue_head_node(txq);
447 wrb_fill(wrb, busaddr, frag->size);
448 be_dws_cpu_to_le(wrb, sizeof(*wrb));
449 queue_head_inc(txq);
450 copied += frag->size;
6b7c5b94
SP		 451 }
452
453 if (dummy_wrb) {
454 wrb = queue_head_node(txq);
455 wrb_fill(wrb, 0, 0);
456 be_dws_cpu_to_le(wrb, sizeof(*wrb));
457 queue_head_inc(txq);
458 }
459
460 wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
461 wrb_cnt, copied);
462 be_dws_cpu_to_le(hdr, sizeof(*hdr));
463
464 return copied;
7101e111
SP		 465dma_err:
466 txq->head = map_head;
467 while (copied) {
468 wrb = queue_head_node(txq);
469 unmap_tx_frag(pdev, wrb, map_single);
470 map_single = false;
471 copied -= wrb->frag_len;
472 queue_head_inc(txq);
473 }
474 return 0;
6b7c5b94
SP		 475}
476
61357325 477static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 478 struct net_device *netdev)
6b7c5b94
SP		 479{
480 struct be_adapter *adapter = netdev_priv(netdev);
481 struct be_tx_obj *tx_obj = &adapter->tx_obj;
482 struct be_queue_info *txq = &tx_obj->q;
483 u32 wrb_cnt = 0, copied = 0;
484 u32 start = txq->head;
485 bool dummy_wrb, stopped = false;
486
487 wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
488
489 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 490 if (copied) {
491 /* record the sent skb in the sent_skb table */
492 BUG_ON(tx_obj->sent_skb_list[start]);
493 tx_obj->sent_skb_list[start] = skb;
494
495 /* Ensure txq has space for the next skb; Else stop the queue
496 * *BEFORE* ringing the tx doorbell, so that we serialze the
497 * tx compls of the current transmit which'll wake up the queue
498 */
7101e111 499 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 500 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
501 txq->len) {
502 netif_stop_queue(netdev);
503 stopped = true;
504 }
6b7c5b94 505
c190e3c8 506 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 507
91992e44
AK		 508 be_tx_stats_update(adapter, wrb_cnt, copied,
509 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 510 } else {
511 txq->head = start;
512 dev_kfree_skb_any(skb);
6b7c5b94 513 }
6b7c5b94
SP		 514 return NETDEV_TX_OK;
515}
516
517static int be_change_mtu(struct net_device *netdev, int new_mtu)
518{
519 struct be_adapter *adapter = netdev_priv(netdev);
520 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 521 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
522 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 523 dev_info(&adapter->pdev->dev,
524 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 525 BE_MIN_MTU,
526 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 527 return -EINVAL;
528 }
529 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
530 netdev->mtu, new_mtu);
531 netdev->mtu = new_mtu;
532 return 0;
533}
534
535/*
82903e4b
AK		 536 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
537 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 538 */
b31c50a7 539static int be_vid_config(struct be_adapter *adapter)
6b7c5b94 540{
6b7c5b94
SP		 541 u16 vtag[BE_NUM_VLANS_SUPPORTED];
542 u16 ntags = 0, i;
82903e4b 543 int status = 0;
6b7c5b94 544
82903e4b 545 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94
SP		 546 /* Construct VLAN Table to give to HW */
547 for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
548 if (adapter->vlan_tag[i]) {
549 vtag[ntags] = cpu_to_le16(i);
550 ntags++;
551 }
552 }
b31c50a7
SP		 553 status = be_cmd_vlan_config(adapter, adapter->if_handle,
554 vtag, ntags, 1, 0);
6b7c5b94 555 } else {
b31c50a7
SP		 556 status = be_cmd_vlan_config(adapter, adapter->if_handle,
557 NULL, 0, 1, 1);
6b7c5b94 558 }
b31c50a7 559 return status;
6b7c5b94
SP		 560}
561
562static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
563{
564 struct be_adapter *adapter = netdev_priv(netdev);
565 struct be_eq_obj *rx_eq = &adapter->rx_eq;
566 struct be_eq_obj *tx_eq = &adapter->tx_eq;
6b7c5b94 567
8788fdc2
SP		 568 be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
569 be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
6b7c5b94 570 adapter->vlan_grp = grp;
8788fdc2
SP		 571 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
572 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
6b7c5b94
SP		 573}
574
575static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
576{
577 struct be_adapter *adapter = netdev_priv(netdev);
578
6b7c5b94 579 adapter->vlan_tag[vid] = 1;
82903e4b
AK		 580 adapter->vlans_added++;
581 if (adapter->vlans_added <= (adapter->max_vlans + 1))
582 be_vid_config(adapter);
6b7c5b94
SP		 583}
584
585static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
586{
587 struct be_adapter *adapter = netdev_priv(netdev);
588
6b7c5b94 589 adapter->vlan_tag[vid] = 0;
6b7c5b94 590 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
82903e4b
AK		 591 adapter->vlans_added--;
592 if (adapter->vlans_added <= adapter->max_vlans)
593 be_vid_config(adapter);
6b7c5b94
SP		 594}
595
24307eef 596static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 597{
598 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 599
24307eef 600 if (netdev->flags & IFF_PROMISC) {
8788fdc2 601 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 602 adapter->promiscuous = true;
603 goto done;
6b7c5b94
SP		 604 }
605
24307eef
SP		 606 /* BE was previously in promiscous mode; disable it */
607 if (adapter->promiscuous) {
608 adapter->promiscuous = false;
8788fdc2 609 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 610 }
611
e7b909a6 612 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 613 if (netdev->flags & IFF_ALLMULTI ||
614 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 615 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 616 &adapter->mc_cmd_mem);
24307eef 617 goto done;
6b7c5b94 618 }
6b7c5b94 619
0ddf477b 620 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 621 &adapter->mc_cmd_mem);
24307eef
SP		 622done:
623 return;
6b7c5b94
SP		 624}
625
4097f663 626static void be_rx_rate_update(struct be_adapter *adapter)
6b7c5b94 627{
4097f663
SP		 628 struct be_drvr_stats *stats = drvr_stats(adapter);
629 ulong now = jiffies;
6b7c5b94 630
4097f663
SP		 631 /* Wrapped around */
632 if (time_before(now, stats->be_rx_jiffies)) {
633 stats->be_rx_jiffies = now;
634 return;
635 }
6b7c5b94
SP		 636
637 /* Update the rate once in two seconds */
4097f663 638 if ((now - stats->be_rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 639 return;
640
65f71b8b
SH		 641 stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
642 - stats->be_rx_bytes_prev,
643 now - stats->be_rx_jiffies);
4097f663 644 stats->be_rx_jiffies = now;
6b7c5b94
SP		 645 stats->be_rx_bytes_prev = stats->be_rx_bytes;
646}
647
4097f663
SP		 648static void be_rx_stats_update(struct be_adapter *adapter,
649 u32 pktsize, u16 numfrags)
650{
651 struct be_drvr_stats *stats = drvr_stats(adapter);
652
653 stats->be_rx_compl++;
654 stats->be_rx_frags += numfrags;
655 stats->be_rx_bytes += pktsize;
91992e44 656 stats->be_rx_pkts++;
4097f663
SP		 657}
658
728a9972
AK		 659static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
660{
661 u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
662
663 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
664 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
665 ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
666 if (ip_version) {
667 tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
668 udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
669 }
670 ipv6_chk = (ip_version && (tcpf || udpf));
671
672 return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
673}
674
6b7c5b94
SP		 675static struct be_rx_page_info *
676get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
677{
678 struct be_rx_page_info *rx_page_info;
679 struct be_queue_info *rxq = &adapter->rx_obj.q;
680
681 rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
682 BUG_ON(!rx_page_info->page);
683
205859a2 684 if (rx_page_info->last_page_user) {
6b7c5b94
SP		 685 pci_unmap_page(adapter->pdev, pci_unmap_addr(rx_page_info, bus),
686 adapter->big_page_size, PCI_DMA_FROMDEVICE);
205859a2
AK		 687 rx_page_info->last_page_user = false;
688 }
6b7c5b94
SP		 689
690 atomic_dec(&rxq->used);
691 return rx_page_info;
692}
693
694/* Throwaway the data in the Rx completion */
695static void be_rx_compl_discard(struct be_adapter *adapter,
696 struct be_eth_rx_compl *rxcp)
697{
698 struct be_queue_info *rxq = &adapter->rx_obj.q;
699 struct be_rx_page_info *page_info;
700 u16 rxq_idx, i, num_rcvd;
701
702 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
703 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
704
705 for (i = 0; i < num_rcvd; i++) {
706 page_info = get_rx_page_info(adapter, rxq_idx);
707 put_page(page_info->page);
708 memset(page_info, 0, sizeof(*page_info));
709 index_inc(&rxq_idx, rxq->len);
710 }
711}
712
713/*
714 * skb_fill_rx_data forms a complete skb for an ether frame
715 * indicated by rxcp.
716 */
717static void skb_fill_rx_data(struct be_adapter *adapter,
89420424
SP		 718 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
719 u16 num_rcvd)
6b7c5b94
SP		 720{
721 struct be_queue_info *rxq = &adapter->rx_obj.q;
722 struct be_rx_page_info *page_info;
89420424 723 u16 rxq_idx, i, j;
fa77406a 724 u32 pktsize, hdr_len, curr_frag_len, size;
6b7c5b94
SP		 725 u8 *start;
726
727 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
728 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
6b7c5b94
SP		 729
730 page_info = get_rx_page_info(adapter, rxq_idx);
731
732 start = page_address(page_info->page) + page_info->page_offset;
733 prefetch(start);
734
735 /* Copy data in the first descriptor of this completion */
736 curr_frag_len = min(pktsize, rx_frag_size);
737
738 /* Copy the header portion into skb_data */
739 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
740 memcpy(skb->data, start, hdr_len);
741 skb->len = curr_frag_len;
742 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
743 /* Complete packet has now been moved to data */
744 put_page(page_info->page);
745 skb->data_len = 0;
746 skb->tail += curr_frag_len;
747 } else {
748 skb_shinfo(skb)->nr_frags = 1;
749 skb_shinfo(skb)->frags[0].page = page_info->page;
750 skb_shinfo(skb)->frags[0].page_offset =
751 page_info->page_offset + hdr_len;
752 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
753 skb->data_len = curr_frag_len - hdr_len;
754 skb->tail += hdr_len;
755 }
205859a2 756 page_info->page = NULL;
6b7c5b94
SP		 757
758 if (pktsize <= rx_frag_size) {
759 BUG_ON(num_rcvd != 1);
76fbb429 760 goto done;
6b7c5b94
SP		 761 }
762
763 /* More frags present for this completion */
fa77406a 764 size = pktsize;
bd46cb6c 765 for (i = 1, j = 0; i < num_rcvd; i++) {
fa77406a 766 size -= curr_frag_len;
6b7c5b94
SP		 767 index_inc(&rxq_idx, rxq->len);
768 page_info = get_rx_page_info(adapter, rxq_idx);
769
fa77406a 770 curr_frag_len = min(size, rx_frag_size);
6b7c5b94 771
bd46cb6c
AK		 772 /* Coalesce all frags from the same physical page in one slot */
773 if (page_info->page_offset == 0) {
774 /* Fresh page */
775 j++;
776 skb_shinfo(skb)->frags[j].page = page_info->page;
777 skb_shinfo(skb)->frags[j].page_offset =
778 page_info->page_offset;
779 skb_shinfo(skb)->frags[j].size = 0;
780 skb_shinfo(skb)->nr_frags++;
781 } else {
782 put_page(page_info->page);
783 }
784
785 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 786 skb->len += curr_frag_len;
787 skb->data_len += curr_frag_len;
6b7c5b94 788
205859a2 789 page_info->page = NULL;
6b7c5b94 790 }
bd46cb6c 791 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 792
76fbb429 793done:
4097f663 794 be_rx_stats_update(adapter, pktsize, num_rcvd);
6b7c5b94
SP		 795 return;
796}
797
5be93b9a 798/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94
SP		 799static void be_rx_compl_process(struct be_adapter *adapter,
800 struct be_eth_rx_compl *rxcp)
801{
802 struct sk_buff *skb;
dcb9b564 803 u32 vlanf, vid;
89420424 804 u16 num_rcvd;
dcb9b564 805 u8 vtm;
6b7c5b94 806
89420424
SP		 807 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
808 /* Is it a flush compl that has no data */
809 if (unlikely(num_rcvd == 0))
810 return;
811
89d71a66 812 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 813 if (unlikely(!skb)) {
6b7c5b94
SP		 814 if (net_ratelimit())
815 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
816 be_rx_compl_discard(adapter, rxcp);
817 return;
818 }
819
89420424 820 skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
6b7c5b94 821
728a9972 822 if (do_pkt_csum(rxcp, adapter->rx_csum))
6b7c5b94 823 skb->ip_summed = CHECKSUM_NONE;
728a9972
AK		 824 else
825 skb->ip_summed = CHECKSUM_UNNECESSARY;
6b7c5b94
SP		 826
827 skb->truesize = skb->len + sizeof(struct sk_buff);
828 skb->protocol = eth_type_trans(skb, adapter->netdev);
6b7c5b94 829
a058a632
SP		 830 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
831 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
832
833 /* vlanf could be wrongly set in some cards.
834 * ignore if vtm is not set */
835 if ((adapter->cap & 0x400) && !vtm)
836 vlanf = 0;
837
838 if (unlikely(vlanf)) {
82903e4b 839 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 840 kfree_skb(skb);
841 return;
842 }
843 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
844 vid = be16_to_cpu(vid);
845 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
846 } else {
847 netif_receive_skb(skb);
848 }
849
6b7c5b94
SP		 850 return;
851}
852
5be93b9a
AK		 853/* Process the RX completion indicated by rxcp when GRO is enabled */
854static void be_rx_compl_process_gro(struct be_adapter *adapter,
6b7c5b94
SP		 855 struct be_eth_rx_compl *rxcp)
856{
857 struct be_rx_page_info *page_info;
5be93b9a 858 struct sk_buff *skb = NULL;
6b7c5b94 859 struct be_queue_info *rxq = &adapter->rx_obj.q;
5be93b9a 860 struct be_eq_obj *eq_obj = &adapter->rx_eq;
6b7c5b94 861 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
bd46cb6c 862 u16 i, rxq_idx = 0, vid, j;
dcb9b564 863 u8 vtm;
6b7c5b94
SP		 864
865 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
89420424
SP		 866 /* Is it a flush compl that has no data */
867 if (unlikely(num_rcvd == 0))
868 return;
869
6b7c5b94
SP		 870 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
871 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
872 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
dcb9b564
AK		 873 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
874
875 /* vlanf could be wrongly set in some cards.
876 * ignore if vtm is not set */
e1187b3b 877 if ((adapter->cap & 0x400) && !vtm)
dcb9b564 878 vlanf = 0;
6b7c5b94 879
5be93b9a
AK		 880 skb = napi_get_frags(&eq_obj->napi);
881 if (!skb) {
882 be_rx_compl_discard(adapter, rxcp);
883 return;
884 }
885
6b7c5b94 886 remaining = pkt_size;
bd46cb6c 887 for (i = 0, j = -1; i < num_rcvd; i++) {
6b7c5b94
SP		 888 page_info = get_rx_page_info(adapter, rxq_idx);
889
890 curr_frag_len = min(remaining, rx_frag_size);
891
bd46cb6c
AK		 892 /* Coalesce all frags from the same physical page in one slot */
893 if (i == 0 || page_info->page_offset == 0) {
894 /* First frag or Fresh page */
895 j++;
5be93b9a
AK		 896 skb_shinfo(skb)->frags[j].page = page_info->page;
897 skb_shinfo(skb)->frags[j].page_offset =
898 page_info->page_offset;
899 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 900 } else {
901 put_page(page_info->page);
902 }
5be93b9a 903 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 904
bd46cb6c 905 remaining -= curr_frag_len;
6b7c5b94 906 index_inc(&rxq_idx, rxq->len);
6b7c5b94
SP		 907 memset(page_info, 0, sizeof(*page_info));
908 }
bd46cb6c 909 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 910
5be93b9a
AK		 911 skb_shinfo(skb)->nr_frags = j + 1;
912 skb->len = pkt_size;
913 skb->data_len = pkt_size;
914 skb->truesize += pkt_size;
915 skb->ip_summed = CHECKSUM_UNNECESSARY;
916
6b7c5b94 917 if (likely(!vlanf)) {
5be93b9a 918 napi_gro_frags(&eq_obj->napi);
6b7c5b94
SP		 919 } else {
920 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
921 vid = be16_to_cpu(vid);
922
82903e4b 923 if (!adapter->vlan_grp || adapter->vlans_added == 0)
6b7c5b94
SP		 924 return;
925
5be93b9a 926 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
6b7c5b94
SP		 927 }
928
4097f663 929 be_rx_stats_update(adapter, pkt_size, num_rcvd);
6b7c5b94
SP		 930 return;
931}
932
933static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
934{
935 struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
936
937 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
938 return NULL;
939
940 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
941
6b7c5b94
SP		 942 queue_tail_inc(&adapter->rx_obj.cq);
943 return rxcp;
944}
945
a7a0ef31
SP		 946/* To reset the valid bit, we need to reset the whole word as
947 * when walking the queue the valid entries are little-endian
948 * and invalid entries are host endian
949 */
950static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
951{
952 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
953}
954
6b7c5b94
SP		 955static inline struct page *be_alloc_pages(u32 size)
956{
957 gfp_t alloc_flags = GFP_ATOMIC;
958 u32 order = get_order(size);
959 if (order > 0)
960 alloc_flags |= __GFP_COMP;
961 return alloc_pages(alloc_flags, order);
962}
963
964/*
965 * Allocate a page, split it to fragments of size rx_frag_size and post as
966 * receive buffers to BE
967 */
968static void be_post_rx_frags(struct be_adapter *adapter)
969{
970 struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
26d92f92 971 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
6b7c5b94
SP		 972 struct be_queue_info *rxq = &adapter->rx_obj.q;
973 struct page *pagep = NULL;
974 struct be_eth_rx_d *rxd;
975 u64 page_dmaaddr = 0, frag_dmaaddr;
976 u32 posted, page_offset = 0;
977
6b7c5b94
SP		 978 page_info = &page_info_tbl[rxq->head];
979 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
980 if (!pagep) {
981 pagep = be_alloc_pages(adapter->big_page_size);
982 if (unlikely(!pagep)) {
983 drvr_stats(adapter)->be_ethrx_post_fail++;
984 break;
985 }
986 page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
987 adapter->big_page_size,
988 PCI_DMA_FROMDEVICE);
989 page_info->page_offset = 0;
990 } else {
991 get_page(pagep);
992 page_info->page_offset = page_offset + rx_frag_size;
993 }
994 page_offset = page_info->page_offset;
995 page_info->page = pagep;
996 pci_unmap_addr_set(page_info, bus, page_dmaaddr);
997 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
998
999 rxd = queue_head_node(rxq);
1000 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1001 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1002
1003 /* Any space left in the current big page for another frag? */
1004 if ((page_offset + rx_frag_size + rx_frag_size) >
1005 adapter->big_page_size) {
1006 pagep = NULL;
1007 page_info->last_page_user = true;
1008 }
26d92f92
SP		 1009
1010 prev_page_info = page_info;
1011 queue_head_inc(rxq);
6b7c5b94
SP		 1012 page_info = &page_info_tbl[rxq->head];
1013 }
1014 if (pagep)
26d92f92 1015 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1016
1017 if (posted) {
6b7c5b94 1018 atomic_add(posted, &rxq->used);
8788fdc2 1019 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1020 } else if (atomic_read(&rxq->used) == 0) {
1021 /* Let be_worker replenish when memory is available */
1022 adapter->rx_post_starved = true;
6b7c5b94
SP		 1023 }
1024
1025 return;
1026}
1027
5fb379ee 1028static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1029{
6b7c5b94
SP		 1030 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1031
1032 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1033 return NULL;
1034
1035 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1036
1037 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1038
1039 queue_tail_inc(tx_cq);
1040 return txcp;
1041}
1042
1043static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1044{
1045 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1046 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1047 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1048 struct sk_buff *sent_skb;
ec43b1a6
SP		 1049 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1050 bool unmap_skb_hdr = true;
6b7c5b94 1051
ec43b1a6 1052 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1053 BUG_ON(!sent_skb);
ec43b1a6
SP		 1054 sent_skbs[txq->tail] = NULL;
1055
1056 /* skip header wrb */
a73b796e 1057 queue_tail_inc(txq);
6b7c5b94 1058
ec43b1a6 1059 do {
6b7c5b94 1060 cur_index = txq->tail;
a73b796e 1061 wrb = queue_tail_node(txq);
ec43b1a6
SP		 1062 unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
1063 sent_skb->len > sent_skb->data_len));
1064 unmap_skb_hdr = false;
1065
6b7c5b94
SP		 1066 num_wrbs++;
1067 queue_tail_inc(txq);
ec43b1a6 1068 } while (cur_index != last_index);
6b7c5b94
SP		 1069
1070 atomic_sub(num_wrbs, &txq->used);
a73b796e 1071
6b7c5b94
SP		 1072 kfree_skb(sent_skb);
1073}
1074
859b1e4e
SP		 1075static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1076{
1077 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1078
1079 if (!eqe->evt)
1080 return NULL;
1081
1082 eqe->evt = le32_to_cpu(eqe->evt);
1083 queue_tail_inc(&eq_obj->q);
1084 return eqe;
1085}
1086
1087static int event_handle(struct be_adapter *adapter,
1088 struct be_eq_obj *eq_obj)
1089{
1090 struct be_eq_entry *eqe;
1091 u16 num = 0;
1092
1093 while ((eqe = event_get(eq_obj)) != NULL) {
1094 eqe->evt = 0;
1095 num++;
1096 }
1097
1098 /* Deal with any spurious interrupts that come
1099 * without events
1100 */
1101 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1102 if (num)
1103 napi_schedule(&eq_obj->napi);
1104
1105 return num;
1106}
1107
1108/* Just read and notify events without processing them.
1109 * Used at the time of destroying event queues */
1110static void be_eq_clean(struct be_adapter *adapter,
1111 struct be_eq_obj *eq_obj)
1112{
1113 struct be_eq_entry *eqe;
1114 u16 num = 0;
1115
1116 while ((eqe = event_get(eq_obj)) != NULL) {
1117 eqe->evt = 0;
1118 num++;
1119 }
1120
1121 if (num)
1122 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1123}
1124
6b7c5b94
SP		 1125static void be_rx_q_clean(struct be_adapter *adapter)
1126{
1127 struct be_rx_page_info *page_info;
1128 struct be_queue_info *rxq = &adapter->rx_obj.q;
1129 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1130 struct be_eth_rx_compl *rxcp;
1131 u16 tail;
1132
1133 /* First cleanup pending rx completions */
1134 while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
1135 be_rx_compl_discard(adapter, rxcp);
a7a0ef31 1136 be_rx_compl_reset(rxcp);
8788fdc2 1137 be_cq_notify(adapter, rx_cq->id, true, 1);
6b7c5b94
SP		 1138 }
1139
1140 /* Then free posted rx buffer that were not used */
1141 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1142 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
6b7c5b94
SP		 1143 page_info = get_rx_page_info(adapter, tail);
1144 put_page(page_info->page);
1145 memset(page_info, 0, sizeof(*page_info));
1146 }
1147 BUG_ON(atomic_read(&rxq->used));
1148}
1149
a8e9179a 1150static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1151{
a8e9179a 1152 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1153 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1154 struct be_eth_tx_compl *txcp;
1155 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1156 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1157 struct sk_buff *sent_skb;
1158 bool dummy_wrb;
a8e9179a
SP		 1159
1160 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1161 do {
1162 while ((txcp = be_tx_compl_get(tx_cq))) {
1163 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1164 wrb_index, txcp);
1165 be_tx_compl_process(adapter, end_idx);
1166 cmpl++;
1167 }
1168 if (cmpl) {
1169 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1170 cmpl = 0;
1171 }
1172
1173 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1174 break;
1175
1176 mdelay(1);
1177 } while (true);
1178
1179 if (atomic_read(&txq->used))
1180 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1181 atomic_read(&txq->used));
b03388d6
SP		 1182
1183 /* free posted tx for which compls will never arrive */
1184 while (atomic_read(&txq->used)) {
1185 sent_skb = sent_skbs[txq->tail];
1186 end_idx = txq->tail;
1187 index_adv(&end_idx,
1188 wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
1189 be_tx_compl_process(adapter, end_idx);
1190 }
6b7c5b94
SP		 1191}
1192
5fb379ee
SP		 1193static void be_mcc_queues_destroy(struct be_adapter *adapter)
1194{
1195 struct be_queue_info *q;
5fb379ee 1196
8788fdc2 1197 q = &adapter->mcc_obj.q;
5fb379ee 1198 if (q->created)
8788fdc2 1199 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1200 be_queue_free(adapter, q);
1201
8788fdc2 1202 q = &adapter->mcc_obj.cq;
5fb379ee 1203 if (q->created)
8788fdc2 1204 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1205 be_queue_free(adapter, q);
1206}
1207
1208/* Must be called only after TX qs are created as MCC shares TX EQ */
1209static int be_mcc_queues_create(struct be_adapter *adapter)
1210{
1211 struct be_queue_info *q, *cq;
5fb379ee
SP		 1212
1213 /* Alloc MCC compl queue */
8788fdc2 1214 cq = &adapter->mcc_obj.cq;
5fb379ee 1215 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1216 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1217 goto err;
1218
1219 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1220 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1221 goto mcc_cq_free;
1222
1223 /* Alloc MCC queue */
8788fdc2 1224 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1225 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1226 goto mcc_cq_destroy;
1227
1228 /* Ask BE to create MCC queue */
8788fdc2 1229 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1230 goto mcc_q_free;
1231
1232 return 0;
1233
1234mcc_q_free:
1235 be_queue_free(adapter, q);
1236mcc_cq_destroy:
8788fdc2 1237 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1238mcc_cq_free:
1239 be_queue_free(adapter, cq);
1240err:
1241 return -1;
1242}
1243
6b7c5b94
SP		 1244static void be_tx_queues_destroy(struct be_adapter *adapter)
1245{
1246 struct be_queue_info *q;
1247
1248 q = &adapter->tx_obj.q;
a8e9179a 1249 if (q->created)
8788fdc2 1250 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1251 be_queue_free(adapter, q);
1252
1253 q = &adapter->tx_obj.cq;
1254 if (q->created)
8788fdc2 1255 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1256 be_queue_free(adapter, q);
1257
859b1e4e
SP		 1258 /* Clear any residual events */
1259 be_eq_clean(adapter, &adapter->tx_eq);
1260
6b7c5b94
SP		 1261 q = &adapter->tx_eq.q;
1262 if (q->created)
8788fdc2 1263 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1264 be_queue_free(adapter, q);
1265}
1266
1267static int be_tx_queues_create(struct be_adapter *adapter)
1268{
1269 struct be_queue_info *eq, *q, *cq;
1270
1271 adapter->tx_eq.max_eqd = 0;
1272 adapter->tx_eq.min_eqd = 0;
1273 adapter->tx_eq.cur_eqd = 96;
1274 adapter->tx_eq.enable_aic = false;
1275 /* Alloc Tx Event queue */
1276 eq = &adapter->tx_eq.q;
1277 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1278 return -1;
1279
1280 /* Ask BE to create Tx Event queue */
8788fdc2 1281 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94
SP		 1282 goto tx_eq_free;
1283 /* Alloc TX eth compl queue */
1284 cq = &adapter->tx_obj.cq;
1285 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1286 sizeof(struct be_eth_tx_compl)))
1287 goto tx_eq_destroy;
1288
1289 /* Ask BE to create Tx eth compl queue */
8788fdc2 1290 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1291 goto tx_cq_free;
1292
1293 /* Alloc TX eth queue */
1294 q = &adapter->tx_obj.q;
1295 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1296 goto tx_cq_destroy;
1297
1298 /* Ask BE to create Tx eth queue */
8788fdc2 1299 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1300 goto tx_q_free;
1301 return 0;
1302
1303tx_q_free:
1304 be_queue_free(adapter, q);
1305tx_cq_destroy:
8788fdc2 1306 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1307tx_cq_free:
1308 be_queue_free(adapter, cq);
1309tx_eq_destroy:
8788fdc2 1310 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1311tx_eq_free:
1312 be_queue_free(adapter, eq);
1313 return -1;
1314}
1315
1316static void be_rx_queues_destroy(struct be_adapter *adapter)
1317{
1318 struct be_queue_info *q;
1319
1320 q = &adapter->rx_obj.q;
1321 if (q->created) {
8788fdc2 1322 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
89420424
SP		 1323
1324 /* After the rxq is invalidated, wait for a grace time
1325 * of 1ms for all dma to end and the flush compl to arrive
1326 */
1327 mdelay(1);
6b7c5b94
SP		 1328 be_rx_q_clean(adapter);
1329 }
1330 be_queue_free(adapter, q);
1331
1332 q = &adapter->rx_obj.cq;
1333 if (q->created)
8788fdc2 1334 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1335 be_queue_free(adapter, q);
1336
859b1e4e
SP		 1337 /* Clear any residual events */
1338 be_eq_clean(adapter, &adapter->rx_eq);
1339
6b7c5b94
SP		 1340 q = &adapter->rx_eq.q;
1341 if (q->created)
8788fdc2 1342 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1343 be_queue_free(adapter, q);
1344}
1345
1346static int be_rx_queues_create(struct be_adapter *adapter)
1347{
1348 struct be_queue_info *eq, *q, *cq;
1349 int rc;
1350
6b7c5b94
SP		 1351 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
1352 adapter->rx_eq.max_eqd = BE_MAX_EQD;
1353 adapter->rx_eq.min_eqd = 0;
1354 adapter->rx_eq.cur_eqd = 0;
1355 adapter->rx_eq.enable_aic = true;
1356
1357 /* Alloc Rx Event queue */
1358 eq = &adapter->rx_eq.q;
1359 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1360 sizeof(struct be_eq_entry));
1361 if (rc)
1362 return rc;
1363
1364 /* Ask BE to create Rx Event queue */
8788fdc2 1365 rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
6b7c5b94
SP		 1366 if (rc)
1367 goto rx_eq_free;
1368
1369 /* Alloc RX eth compl queue */
1370 cq = &adapter->rx_obj.cq;
1371 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1372 sizeof(struct be_eth_rx_compl));
1373 if (rc)
1374 goto rx_eq_destroy;
1375
1376 /* Ask BE to create Rx eth compl queue */
8788fdc2 1377 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
6b7c5b94
SP		 1378 if (rc)
1379 goto rx_cq_free;
1380
1381 /* Alloc RX eth queue */
1382 q = &adapter->rx_obj.q;
1383 rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
1384 if (rc)
1385 goto rx_cq_destroy;
1386
1387 /* Ask BE to create Rx eth queue */
8788fdc2 1388 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
6b7c5b94
SP		 1389 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
1390 if (rc)
1391 goto rx_q_free;
1392
1393 return 0;
1394rx_q_free:
1395 be_queue_free(adapter, q);
1396rx_cq_destroy:
8788fdc2 1397 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1398rx_cq_free:
1399 be_queue_free(adapter, cq);
1400rx_eq_destroy:
8788fdc2 1401 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1402rx_eq_free:
1403 be_queue_free(adapter, eq);
1404 return rc;
1405}
6b7c5b94 1406
b628bde2
SP		 1407/* There are 8 evt ids per func. Retruns the evt id's bit number */
1408static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
1409{
500ca9ba 1410 return eq_id % 8;
b628bde2
SP		 1411}
1412
6b7c5b94
SP		 1413static irqreturn_t be_intx(int irq, void *dev)
1414{
1415 struct be_adapter *adapter = dev;
8788fdc2 1416 int isr;
6b7c5b94 1417
8788fdc2 1418 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
55bdeed9 1419 (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
c001c213 1420 if (!isr)
8788fdc2 1421 return IRQ_NONE;
6b7c5b94 1422
8788fdc2
SP		 1423 event_handle(adapter, &adapter->tx_eq);
1424 event_handle(adapter, &adapter->rx_eq);
c001c213 1425
8788fdc2 1426 return IRQ_HANDLED;
6b7c5b94
SP		 1427}
1428
1429static irqreturn_t be_msix_rx(int irq, void *dev)
1430{
1431 struct be_adapter *adapter = dev;
1432
8788fdc2 1433 event_handle(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1434
1435 return IRQ_HANDLED;
1436}
1437
5fb379ee 1438static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1439{
1440 struct be_adapter *adapter = dev;
1441
8788fdc2 1442 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1443
1444 return IRQ_HANDLED;
1445}
1446
5be93b9a 1447static inline bool do_gro(struct be_adapter *adapter,
6b7c5b94
SP		 1448 struct be_eth_rx_compl *rxcp)
1449{
1450 int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1451 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1452
1453 if (err)
1454 drvr_stats(adapter)->be_rxcp_err++;
1455
5be93b9a 1456 return (tcp_frame && !err) ? true : false;
6b7c5b94
SP		 1457}
1458
1459int be_poll_rx(struct napi_struct *napi, int budget)
1460{
1461 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
1462 struct be_adapter *adapter =
1463 container_of(rx_eq, struct be_adapter, rx_eq);
1464 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1465 struct be_eth_rx_compl *rxcp;
1466 u32 work_done;
1467
b7b83ac3 1468 adapter->stats.drvr_stats.be_rx_polls++;
6b7c5b94
SP		 1469 for (work_done = 0; work_done < budget; work_done++) {
1470 rxcp = be_rx_compl_get(adapter);
1471 if (!rxcp)
1472 break;
1473
5be93b9a
AK		 1474 if (do_gro(adapter, rxcp))
1475 be_rx_compl_process_gro(adapter, rxcp);
6b7c5b94
SP		 1476 else
1477 be_rx_compl_process(adapter, rxcp);
a7a0ef31
SP		 1478
1479 be_rx_compl_reset(rxcp);
6b7c5b94
SP		 1480 }
1481
6b7c5b94
SP		 1482 /* Refill the queue */
1483 if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
1484 be_post_rx_frags(adapter);
1485
1486 /* All consumed */
1487 if (work_done < budget) {
1488 napi_complete(napi);
8788fdc2 1489 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1490 } else {
1491 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1492 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1493 }
1494 return work_done;
1495}
1496
f31e50a8
SP		 1497/* As TX and MCC share the same EQ check for both TX and MCC completions.
1498 * For TX/MCC we don't honour budget; consume everything
1499 */
1500static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1501{
f31e50a8
SP		 1502 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1503 struct be_adapter *adapter =
1504 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1505 struct be_queue_info *txq = &adapter->tx_obj.q;
1506 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1507 struct be_eth_tx_compl *txcp;
f31e50a8 1508 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1509 u16 end_idx;
1510
5fb379ee 1511 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1512 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1513 wrb_index, txcp);
6b7c5b94 1514 be_tx_compl_process(adapter, end_idx);
f31e50a8 1515 tx_compl++;
6b7c5b94
SP		 1516 }
1517
f31e50a8
SP		 1518 mcc_compl = be_process_mcc(adapter, &status);
1519
1520 napi_complete(napi);
1521
1522 if (mcc_compl) {
1523 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1524 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1525 }
1526
1527 if (tx_compl) {
1528 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1529
1530 /* As Tx wrbs have been freed up, wake up netdev queue if
1531 * it was stopped due to lack of tx wrbs.
1532 */
1533 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1534 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1535 netif_wake_queue(adapter->netdev);
1536 }
1537
1538 drvr_stats(adapter)->be_tx_events++;
f31e50a8 1539 drvr_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1540 }
6b7c5b94
SP		 1541
1542 return 1;
1543}
1544
ea1dae11
SP		 1545static void be_worker(struct work_struct *work)
1546{
1547 struct be_adapter *adapter =
1548 container_of(work, struct be_adapter, work.work);
ea1dae11 1549
b31c50a7 1550 be_cmd_get_stats(adapter, &adapter->stats.cmd);
ea1dae11
SP		 1551
1552 /* Set EQ delay */
1553 be_rx_eqd_update(adapter);
1554
4097f663
SP		 1555 be_tx_rate_update(adapter);
1556 be_rx_rate_update(adapter);
1557
ea1dae11
SP		 1558 if (adapter->rx_post_starved) {
1559 adapter->rx_post_starved = false;
1560 be_post_rx_frags(adapter);
1561 }
1562
1563 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1564}
1565
8d56ff11
SP		 1566static void be_msix_disable(struct be_adapter *adapter)
1567{
1568 if (adapter->msix_enabled) {
1569 pci_disable_msix(adapter->pdev);
1570 adapter->msix_enabled = false;
1571 }
1572}
1573
6b7c5b94
SP		 1574static void be_msix_enable(struct be_adapter *adapter)
1575{
1576 int i, status;
1577
1578 for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
1579 adapter->msix_entries[i].entry = i;
1580
1581 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1582 BE_NUM_MSIX_VECTORS);
1583 if (status == 0)
1584 adapter->msix_enabled = true;
1585 return;
1586}
1587
1588static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
1589{
b628bde2
SP		 1590 return adapter->msix_entries[
1591 be_evt_bit_get(adapter, eq_id)].vector;
6b7c5b94
SP		 1592}
1593
b628bde2
SP		 1594static int be_request_irq(struct be_adapter *adapter,
1595 struct be_eq_obj *eq_obj,
1596 void *handler, char *desc)
6b7c5b94
SP		 1597{
1598 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1599 int vec;
1600
1601 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
1602 vec = be_msix_vec_get(adapter, eq_obj->q.id);
1603 return request_irq(vec, handler, 0, eq_obj->desc, adapter);
1604}
1605
1606static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
1607{
1608 int vec = be_msix_vec_get(adapter, eq_obj->q.id);
1609 free_irq(vec, adapter);
1610}
6b7c5b94 1611
b628bde2
SP		 1612static int be_msix_register(struct be_adapter *adapter)
1613{
1614 int status;
1615
1616 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
6b7c5b94
SP		 1617 if (status)
1618 goto err;
1619
b628bde2
SP		 1620 status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
1621 if (status)
1622 goto free_tx_irq;
1623
6b7c5b94 1624 return 0;
b628bde2
SP		 1625
1626free_tx_irq:
1627 be_free_irq(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1628err:
1629 dev_warn(&adapter->pdev->dev,
1630 "MSIX Request IRQ failed - err %d\n", status);
1631 pci_disable_msix(adapter->pdev);
1632 adapter->msix_enabled = false;
1633 return status;
1634}
1635
1636static int be_irq_register(struct be_adapter *adapter)
1637{
1638 struct net_device *netdev = adapter->netdev;
1639 int status;
1640
1641 if (adapter->msix_enabled) {
1642 status = be_msix_register(adapter);
1643 if (status == 0)
1644 goto done;
1645 }
1646
1647 /* INTx */
1648 netdev->irq = adapter->pdev->irq;
1649 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
1650 adapter);
1651 if (status) {
1652 dev_err(&adapter->pdev->dev,
1653 "INTx request IRQ failed - err %d\n", status);
1654 return status;
1655 }
1656done:
1657 adapter->isr_registered = true;
1658 return 0;
1659}
1660
1661static void be_irq_unregister(struct be_adapter *adapter)
1662{
1663 struct net_device *netdev = adapter->netdev;
6b7c5b94
SP		 1664
1665 if (!adapter->isr_registered)
1666 return;
1667
1668 /* INTx */
1669 if (!adapter->msix_enabled) {
1670 free_irq(netdev->irq, adapter);
1671 goto done;
1672 }
1673
1674 /* MSIx */
b628bde2
SP		 1675 be_free_irq(adapter, &adapter->tx_eq);
1676 be_free_irq(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1677done:
1678 adapter->isr_registered = false;
1679 return;
1680}
1681
1682static int be_open(struct net_device *netdev)
1683{
1684 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1685 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1686 struct be_eq_obj *tx_eq = &adapter->tx_eq;
a8f447bd
SP		 1687 bool link_up;
1688 int status;
0388f251
SB		 1689 u8 mac_speed;
1690 u16 link_speed;
5fb379ee
SP		 1691
1692 /* First time posting */
1693 be_post_rx_frags(adapter);
1694
1695 napi_enable(&rx_eq->napi);
1696 napi_enable(&tx_eq->napi);
1697
1698 be_irq_register(adapter);
1699
8788fdc2 1700 be_intr_set(adapter, true);
5fb379ee
SP		 1701
1702 /* The evt queues are created in unarmed state; arm them */
8788fdc2
SP		 1703 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
1704 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee
SP		 1705
1706 /* Rx compl queue may be in unarmed state; rearm it */
8788fdc2 1707 be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
5fb379ee 1708
7a1e9b20
SP		 1709 /* Now that interrupts are on we can process async mcc */
1710 be_async_mcc_enable(adapter);
1711
0388f251
SB		 1712 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
1713 &link_speed);
a8f447bd 1714 if (status)
4f2aa89c 1715 goto ret_sts;
a8f447bd 1716 be_link_status_update(adapter, link_up);
5fb379ee 1717
4f2aa89c
AK		 1718 status = be_vid_config(adapter);
1719 if (status)
1720 goto ret_sts;
1721
1722 status = be_cmd_set_flow_control(adapter,
1723 adapter->tx_fc, adapter->rx_fc);
1724 if (status)
1725 goto ret_sts;
1726
5fb379ee 1727 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
4f2aa89c
AK		 1728ret_sts:
1729 return status;
5fb379ee
SP		 1730}
1731
71d8d1b5
AK		 1732static int be_setup_wol(struct be_adapter *adapter, bool enable)
1733{
1734 struct be_dma_mem cmd;
1735 int status = 0;
1736 u8 mac[ETH_ALEN];
1737
1738 memset(mac, 0, ETH_ALEN);
1739
1740 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
1741 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
1742 if (cmd.va == NULL)
1743 return -1;
1744 memset(cmd.va, 0, cmd.size);
1745
1746 if (enable) {
1747 status = pci_write_config_dword(adapter->pdev,
1748 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
1749 if (status) {
1750 dev_err(&adapter->pdev->dev,
2381a55c 1751 "Could not enable Wake-on-lan\n");
71d8d1b5
AK		 1752 pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
1753 cmd.dma);
1754 return status;
1755 }
1756 status = be_cmd_enable_magic_wol(adapter,
1757 adapter->netdev->dev_addr, &cmd);
1758 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
1759 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
1760 } else {
1761 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
1762 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
1763 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
1764 }
1765
1766 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
1767 return status;
1768}
1769
5fb379ee
SP		 1770static int be_setup(struct be_adapter *adapter)
1771{
5fb379ee 1772 struct net_device *netdev = adapter->netdev;
73d540f2 1773 u32 cap_flags, en_flags;
6b7c5b94
SP		 1774 int status;
1775
73d540f2
SP		 1776 cap_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
1777 BE_IF_FLAGS_MCAST_PROMISCUOUS |
1778 BE_IF_FLAGS_PROMISCUOUS |
1779 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1780 en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
1781 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1782
1783 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1784 netdev->dev_addr, false/* pmac_invalid */,
1785 &adapter->if_handle, &adapter->pmac_id);
6b7c5b94
SP		 1786 if (status != 0)
1787 goto do_none;
1788
6b7c5b94
SP		 1789 status = be_tx_queues_create(adapter);
1790 if (status != 0)
1791 goto if_destroy;
1792
1793 status = be_rx_queues_create(adapter);
1794 if (status != 0)
1795 goto tx_qs_destroy;
1796
5fb379ee
SP		 1797 status = be_mcc_queues_create(adapter);
1798 if (status != 0)
1799 goto rx_qs_destroy;
6b7c5b94 1800
0dffc83e
AK		 1801 adapter->link_speed = -1;
1802
6b7c5b94
SP		 1803 return 0;
1804
5fb379ee
SP		 1805rx_qs_destroy:
1806 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 1807tx_qs_destroy:
1808 be_tx_queues_destroy(adapter);
1809if_destroy:
8788fdc2 1810 be_cmd_if_destroy(adapter, adapter->if_handle);
6b7c5b94
SP		 1811do_none:
1812 return status;
1813}
1814
5fb379ee
SP		 1815static int be_clear(struct be_adapter *adapter)
1816{
1a8887d8 1817 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 1818 be_rx_queues_destroy(adapter);
1819 be_tx_queues_destroy(adapter);
1820
8788fdc2 1821 be_cmd_if_destroy(adapter, adapter->if_handle);
5fb379ee 1822
2243e2e9
SP		 1823 /* tell fw we're done with firing cmds */
1824 be_cmd_fw_clean(adapter);
5fb379ee
SP		 1825 return 0;
1826}
1827
6b7c5b94
SP		 1828static int be_close(struct net_device *netdev)
1829{
1830 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1831 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1832 struct be_eq_obj *tx_eq = &adapter->tx_eq;
1833 int vec;
1834
b305be78 1835 cancel_delayed_work_sync(&adapter->work);
6b7c5b94 1836
7a1e9b20
SP		 1837 be_async_mcc_disable(adapter);
1838
6b7c5b94
SP		 1839 netif_stop_queue(netdev);
1840 netif_carrier_off(netdev);
a8f447bd 1841 adapter->link_up = false;
6b7c5b94 1842
8788fdc2 1843 be_intr_set(adapter, false);
6b7c5b94
SP		 1844
1845 if (adapter->msix_enabled) {
1846 vec = be_msix_vec_get(adapter, tx_eq->q.id);
1847 synchronize_irq(vec);
1848 vec = be_msix_vec_get(adapter, rx_eq->q.id);
1849 synchronize_irq(vec);
1850 } else {
1851 synchronize_irq(netdev->irq);
1852 }
1853 be_irq_unregister(adapter);
1854
1855 napi_disable(&rx_eq->napi);
1856 napi_disable(&tx_eq->napi);
1857
a8e9179a
SP		 1858 /* Wait for all pending tx completions to arrive so that
1859 * all tx skbs are freed.
1860 */
1861 be_tx_compl_clean(adapter);
1862
6b7c5b94
SP		 1863 return 0;
1864}
1865
84517482
AK		 1866#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
1867char flash_cookie[2][16] = {"*** SE FLAS",
1868 "H DIRECTORY *** "};
fa9a6fed
SB		 1869
1870static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 1871 const u8 *p, u32 img_start, int image_size,
1872 int hdr_size)
fa9a6fed
SB		 1873{
1874 u32 crc_offset;
1875 u8 flashed_crc[4];
1876 int status;
3f0d4560
AK		 1877
1878 crc_offset = hdr_size + img_start + image_size - 4;
1879
fa9a6fed 1880 p += crc_offset;
3f0d4560
AK		 1881
1882 status = be_cmd_get_flash_crc(adapter, flashed_crc,
1883 (img_start + image_size - 4));
fa9a6fed
SB		 1884 if (status) {
1885 dev_err(&adapter->pdev->dev,
1886 "could not get crc from flash, not flashing redboot\n");
1887 return false;
1888 }
1889
1890 /*update redboot only if crc does not match*/
1891 if (!memcmp(flashed_crc, p, 4))
1892 return false;
1893 else
1894 return true;
fa9a6fed
SB		 1895}
1896
3f0d4560 1897static int be_flash_data(struct be_adapter *adapter,
84517482 1898 const struct firmware *fw,
3f0d4560
AK		 1899 struct be_dma_mem *flash_cmd, int num_of_images)
1900
84517482 1901{
3f0d4560
AK		 1902 int status = 0, i, filehdr_size = 0;
1903 u32 total_bytes = 0, flash_op;
84517482
AK		 1904 int num_bytes;
1905 const u8 *p = fw->data;
1906 struct be_cmd_write_flashrom *req = flash_cmd->va;
3f0d4560 1907 struct flash_comp *pflashcomp;
9fe96934 1908 int num_comp;
3f0d4560 1909
9fe96934 1910 struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 1911 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
1912 FLASH_IMAGE_MAX_SIZE_g3},
1913 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
1914 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
1915 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
1916 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
1917 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
1918 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
1919 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
1920 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
1921 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
1922 FLASH_IMAGE_MAX_SIZE_g3},
1923 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
1924 FLASH_IMAGE_MAX_SIZE_g3},
1925 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 1926 FLASH_IMAGE_MAX_SIZE_g3},
1927 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
1928 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560
AK		 1929 };
1930 struct flash_comp gen2_flash_types[8] = {
1931 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
1932 FLASH_IMAGE_MAX_SIZE_g2},
1933 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
1934 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
1935 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
1936 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
1937 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
1938 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
1939 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
1940 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
1941 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
1942 FLASH_IMAGE_MAX_SIZE_g2},
1943 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
1944 FLASH_IMAGE_MAX_SIZE_g2},
1945 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
1946 FLASH_IMAGE_MAX_SIZE_g2}
1947 };
1948
1949 if (adapter->generation == BE_GEN3) {
1950 pflashcomp = gen3_flash_types;
1951 filehdr_size = sizeof(struct flash_file_hdr_g3);
9fe96934 1952 num_comp = 9;
3f0d4560
AK		 1953 } else {
1954 pflashcomp = gen2_flash_types;
1955 filehdr_size = sizeof(struct flash_file_hdr_g2);
9fe96934 1956 num_comp = 8;
84517482 1957 }
9fe96934
SB		 1958 for (i = 0; i < num_comp; i++) {
1959 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
1960 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
1961 continue;
3f0d4560
AK		 1962 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
1963 (!be_flash_redboot(adapter, fw->data,
1964 pflashcomp[i].offset, pflashcomp[i].size,
1965 filehdr_size)))
1966 continue;
1967 p = fw->data;
1968 p += filehdr_size + pflashcomp[i].offset
1969 + (num_of_images * sizeof(struct image_hdr));
1970 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 1971 return -1;
3f0d4560
AK		 1972 total_bytes = pflashcomp[i].size;
1973 while (total_bytes) {
1974 if (total_bytes > 32*1024)
1975 num_bytes = 32*1024;
1976 else
1977 num_bytes = total_bytes;
1978 total_bytes -= num_bytes;
1979
1980 if (!total_bytes)
1981 flash_op = FLASHROM_OPER_FLASH;
1982 else
1983 flash_op = FLASHROM_OPER_SAVE;
1984 memcpy(req->params.data_buf, p, num_bytes);
1985 p += num_bytes;
1986 status = be_cmd_write_flashrom(adapter, flash_cmd,
1987 pflashcomp[i].optype, flash_op, num_bytes);
1988 if (status) {
1989 dev_err(&adapter->pdev->dev,
1990 "cmd to write to flash rom failed.\n");
1991 return -1;
1992 }
1993 yield();
84517482 1994 }
84517482 1995 }
84517482
AK		 1996 return 0;
1997}
1998
3f0d4560
AK		 1999static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2000{
2001 if (fhdr == NULL)
2002 return 0;
2003 if (fhdr->build[0] == '3')
2004 return BE_GEN3;
2005 else if (fhdr->build[0] == '2')
2006 return BE_GEN2;
2007 else
2008 return 0;
2009}
2010
84517482
AK		 2011int be_load_fw(struct be_adapter *adapter, u8 *func)
2012{
2013 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2014 const struct firmware *fw;
3f0d4560
AK		 2015 struct flash_file_hdr_g2 *fhdr;
2016 struct flash_file_hdr_g3 *fhdr3;
2017 struct image_hdr *img_hdr_ptr = NULL;
84517482 2018 struct be_dma_mem flash_cmd;
3f0d4560 2019 int status, i = 0;
84517482 2020 const u8 *p;
84517482 2021
84517482
AK		 2022 strcpy(fw_file, func);
2023
2024 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2025 if (status)
2026 goto fw_exit;
2027
2028 p = fw->data;
3f0d4560 2029 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2030 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2031
84517482
AK		 2032 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2033 flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
2034 &flash_cmd.dma);
2035 if (!flash_cmd.va) {
2036 status = -ENOMEM;
2037 dev_err(&adapter->pdev->dev,
2038 "Memory allocation failure while flashing\n");
2039 goto fw_exit;
2040 }
2041
3f0d4560
AK		 2042 if ((adapter->generation == BE_GEN3) &&
2043 (get_ufigen_type(fhdr) == BE_GEN3)) {
2044 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
2045 for (i = 0; i < fhdr3->num_imgs; i++) {
2046 img_hdr_ptr = (struct image_hdr *) (fw->data +
2047 (sizeof(struct flash_file_hdr_g3) +
2048 i * sizeof(struct image_hdr)));
2049 if (img_hdr_ptr->imageid == 1) {
2050 status = be_flash_data(adapter, fw,
2051 &flash_cmd, fhdr3->num_imgs);
2052 }
2053
2054 }
2055 } else if ((adapter->generation == BE_GEN2) &&
2056 (get_ufigen_type(fhdr) == BE_GEN2)) {
2057 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2058 } else {
2059 dev_err(&adapter->pdev->dev,
2060 "UFI and Interface are not compatible for flashing\n");
2061 status = -1;
84517482
AK		 2062 }
2063
2064 pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
2065 flash_cmd.dma);
2066 if (status) {
2067 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2068 goto fw_exit;
2069 }
2070
af901ca1 2071 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2072
2073fw_exit:
2074 release_firmware(fw);
2075 return status;
2076}
2077
6b7c5b94
SP		 2078static struct net_device_ops be_netdev_ops = {
2079 .ndo_open = be_open,
2080 .ndo_stop = be_close,
2081 .ndo_start_xmit = be_xmit,
2082 .ndo_get_stats = be_get_stats,
2083 .ndo_set_rx_mode = be_set_multicast_list,
2084 .ndo_set_mac_address = be_mac_addr_set,
2085 .ndo_change_mtu = be_change_mtu,
2086 .ndo_validate_addr = eth_validate_addr,
2087 .ndo_vlan_rx_register = be_vlan_register,
2088 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2089 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
2090};
2091
2092static void be_netdev_init(struct net_device *netdev)
2093{
2094 struct be_adapter *adapter = netdev_priv(netdev);
2095
2096 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
583e3f34
AK		 2097 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
2098 NETIF_F_GRO;
6b7c5b94 2099
51c59870
AK		 2100 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
2101
6b7c5b94
SP		 2102 netdev->flags |= IFF_MULTICAST;
2103
728a9972
AK		 2104 adapter->rx_csum = true;
2105
9e90c961
AK		 2106 /* Default settings for Rx and Tx flow control */
2107 adapter->rx_fc = true;
2108 adapter->tx_fc = true;
2109
c190e3c8
AK		 2110 netif_set_gso_max_size(netdev, 65535);
2111
6b7c5b94
SP		 2112 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2113
2114 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2115
6b7c5b94
SP		 2116 netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
2117 BE_NAPI_WEIGHT);
5fb379ee 2118 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94
SP		 2119 BE_NAPI_WEIGHT);
2120
2121 netif_carrier_off(netdev);
2122 netif_stop_queue(netdev);
2123}
2124
2125static void be_unmap_pci_bars(struct be_adapter *adapter)
2126{
8788fdc2
SP		 2127 if (adapter->csr)
2128 iounmap(adapter->csr);
2129 if (adapter->db)
2130 iounmap(adapter->db);
2131 if (adapter->pcicfg)
2132 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2133}
2134
2135static int be_map_pci_bars(struct be_adapter *adapter)
2136{
2137 u8 __iomem *addr;
7b139c83 2138 int pcicfg_reg;
6b7c5b94
SP		 2139
2140 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2141 pci_resource_len(adapter->pdev, 2));
2142 if (addr == NULL)
2143 return -ENOMEM;
8788fdc2 2144 adapter->csr = addr;
6b7c5b94
SP		 2145
2146 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 4),
2147 128 * 1024);
2148 if (addr == NULL)
2149 goto pci_map_err;
8788fdc2 2150 adapter->db = addr;
6b7c5b94 2151
7b139c83
AK		 2152 if (adapter->generation == BE_GEN2)
2153 pcicfg_reg = 1;
2154 else
2155 pcicfg_reg = 0;
2156
2157 addr = ioremap_nocache(pci_resource_start(adapter->pdev, pcicfg_reg),
2158 pci_resource_len(adapter->pdev, pcicfg_reg));
6b7c5b94
SP		 2159 if (addr == NULL)
2160 goto pci_map_err;
8788fdc2 2161 adapter->pcicfg = addr;
6b7c5b94
SP		 2162
2163 return 0;
2164pci_map_err:
2165 be_unmap_pci_bars(adapter);
2166 return -ENOMEM;
2167}
2168
2169
2170static void be_ctrl_cleanup(struct be_adapter *adapter)
2171{
8788fdc2 2172 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2173
2174 be_unmap_pci_bars(adapter);
2175
2176 if (mem->va)
2177 pci_free_consistent(adapter->pdev, mem->size,
2178 mem->va, mem->dma);
e7b909a6
SP		 2179
2180 mem = &adapter->mc_cmd_mem;
2181 if (mem->va)
2182 pci_free_consistent(adapter->pdev, mem->size,
2183 mem->va, mem->dma);
6b7c5b94
SP		 2184}
2185
6b7c5b94
SP		 2186static int be_ctrl_init(struct be_adapter *adapter)
2187{
8788fdc2
SP		 2188 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2189 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2190 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2191 int status;
6b7c5b94
SP		 2192
2193 status = be_map_pci_bars(adapter);
2194 if (status)
e7b909a6 2195 goto done;
6b7c5b94
SP		 2196
2197 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2198 mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
2199 mbox_mem_alloc->size, &mbox_mem_alloc->dma);
2200 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2201 status = -ENOMEM;
2202 goto unmap_pci_bars;
6b7c5b94 2203 }
e7b909a6 2204
6b7c5b94
SP		 2205 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2206 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2207 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2208 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2209
2210 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2211 mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
2212 &mc_cmd_mem->dma);
2213 if (mc_cmd_mem->va == NULL) {
2214 status = -ENOMEM;
2215 goto free_mbox;
2216 }
2217 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2218
8788fdc2
SP		 2219 spin_lock_init(&adapter->mbox_lock);
2220 spin_lock_init(&adapter->mcc_lock);
2221 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2222
cf588477 2223 pci_save_state(adapter->pdev);
6b7c5b94 2224 return 0;
e7b909a6
SP		 2225
2226free_mbox:
2227 pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
2228 mbox_mem_alloc->va, mbox_mem_alloc->dma);
2229
2230unmap_pci_bars:
2231 be_unmap_pci_bars(adapter);
2232
2233done:
2234 return status;
6b7c5b94
SP		 2235}
2236
2237static void be_stats_cleanup(struct be_adapter *adapter)
2238{
2239 struct be_stats_obj *stats = &adapter->stats;
2240 struct be_dma_mem *cmd = &stats->cmd;
2241
2242 if (cmd->va)
2243 pci_free_consistent(adapter->pdev, cmd->size,
2244 cmd->va, cmd->dma);
2245}
2246
2247static int be_stats_init(struct be_adapter *adapter)
2248{
2249 struct be_stats_obj *stats = &adapter->stats;
2250 struct be_dma_mem *cmd = &stats->cmd;
2251
2252 cmd->size = sizeof(struct be_cmd_req_get_stats);
2253 cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
2254 if (cmd->va == NULL)
2255 return -1;
d291b9af 2256 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2257 return 0;
2258}
2259
2260static void __devexit be_remove(struct pci_dev *pdev)
2261{
2262 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2263
6b7c5b94
SP		 2264 if (!adapter)
2265 return;
2266
2267 unregister_netdev(adapter->netdev);
2268
5fb379ee
SP		 2269 be_clear(adapter);
2270
6b7c5b94
SP		 2271 be_stats_cleanup(adapter);
2272
2273 be_ctrl_cleanup(adapter);
2274
8d56ff11 2275 be_msix_disable(adapter);
6b7c5b94
SP		 2276
2277 pci_set_drvdata(pdev, NULL);
2278 pci_release_regions(pdev);
2279 pci_disable_device(pdev);
2280
2281 free_netdev(adapter->netdev);
2282}
2283
2243e2e9 2284static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2285{
6b7c5b94 2286 int status;
2243e2e9 2287 u8 mac[ETH_ALEN];
6b7c5b94 2288
2243e2e9 2289 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2290 if (status)
2291 return status;
2292
2243e2e9
SP		 2293 status = be_cmd_query_fw_cfg(adapter,
2294 &adapter->port_num, &adapter->cap);
43a04fdc
SP		 2295 if (status)
2296 return status;
2297
2243e2e9
SP		 2298 memset(mac, 0, ETH_ALEN);
2299 status = be_cmd_mac_addr_query(adapter, mac,
2300 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
6b7c5b94
SP		 2301 if (status)
2302 return status;
ca9e4988
AK		 2303
2304 if (!is_valid_ether_addr(mac))
2305 return -EADDRNOTAVAIL;
2306
2243e2e9 2307 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
35a65285 2308 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
6b7c5b94 2309
82903e4b
AK		 2310 if (adapter->cap & 0x400)
2311 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2312 else
2313 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2314
2243e2e9 2315 return 0;
6b7c5b94
SP		 2316}
2317
2318static int __devinit be_probe(struct pci_dev *pdev,
2319 const struct pci_device_id *pdev_id)
2320{
2321 int status = 0;
2322 struct be_adapter *adapter;
2323 struct net_device *netdev;
6b7c5b94
SP		 2324
2325 status = pci_enable_device(pdev);
2326 if (status)
2327 goto do_none;
2328
2329 status = pci_request_regions(pdev, DRV_NAME);
2330 if (status)
2331 goto disable_dev;
2332 pci_set_master(pdev);
2333
2334 netdev = alloc_etherdev(sizeof(struct be_adapter));
2335 if (netdev == NULL) {
2336 status = -ENOMEM;
2337 goto rel_reg;
2338 }
2339 adapter = netdev_priv(netdev);
7b139c83
AK		 2340
2341 switch (pdev->device) {
2342 case BE_DEVICE_ID1:
2343 case OC_DEVICE_ID1:
2344 adapter->generation = BE_GEN2;
2345 break;
2346 case BE_DEVICE_ID2:
2347 case OC_DEVICE_ID2:
2348 adapter->generation = BE_GEN3;
2349 break;
2350 default:
2351 adapter->generation = 0;
2352 }
2353
6b7c5b94
SP		 2354 adapter->pdev = pdev;
2355 pci_set_drvdata(pdev, adapter);
2356 adapter->netdev = netdev;
2243e2e9
SP		 2357 be_netdev_init(netdev);
2358 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94
SP		 2359
2360 be_msix_enable(adapter);
2361
e930438c 2362 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2363 if (!status) {
2364 netdev->features |= NETIF_F_HIGHDMA;
2365 } else {
e930438c 2366 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2367 if (status) {
2368 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2369 goto free_netdev;
2370 }
2371 }
2372
6b7c5b94
SP		 2373 status = be_ctrl_init(adapter);
2374 if (status)
2375 goto free_netdev;
2376
2243e2e9
SP		 2377 /* sync up with fw's ready state */
2378 status = be_cmd_POST(adapter);
6b7c5b94
SP		 2379 if (status)
2380 goto ctrl_clean;
2381
2243e2e9
SP		 2382 /* tell fw we're ready to fire cmds */
2383 status = be_cmd_fw_init(adapter);
6b7c5b94 2384 if (status)
2243e2e9
SP		 2385 goto ctrl_clean;
2386
2387 status = be_cmd_reset_function(adapter);
2388 if (status)
2389 goto ctrl_clean;
6b7c5b94 2390
2243e2e9
SP		 2391 status = be_stats_init(adapter);
2392 if (status)
2393 goto ctrl_clean;
2394
2395 status = be_get_config(adapter);
6b7c5b94
SP		 2396 if (status)
2397 goto stats_clean;
6b7c5b94
SP		 2398
2399 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 2400
5fb379ee
SP		 2401 status = be_setup(adapter);
2402 if (status)
2403 goto stats_clean;
2243e2e9 2404
6b7c5b94
SP		 2405 status = register_netdev(netdev);
2406 if (status != 0)
5fb379ee 2407 goto unsetup;
6b7c5b94 2408
c4ca2374 2409 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
6b7c5b94
SP		 2410 return 0;
2411
5fb379ee
SP		 2412unsetup:
2413 be_clear(adapter);
6b7c5b94
SP		 2414stats_clean:
2415 be_stats_cleanup(adapter);
2416ctrl_clean:
2417 be_ctrl_cleanup(adapter);
2418free_netdev:
8d56ff11 2419 be_msix_disable(adapter);
6b7c5b94 2420 free_netdev(adapter->netdev);
8d56ff11 2421 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 2422rel_reg:
2423 pci_release_regions(pdev);
2424disable_dev:
2425 pci_disable_device(pdev);
2426do_none:
c4ca2374 2427 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 2428 return status;
2429}
2430
2431static int be_suspend(struct pci_dev *pdev, pm_message_t state)
2432{
2433 struct be_adapter *adapter = pci_get_drvdata(pdev);
2434 struct net_device *netdev = adapter->netdev;
2435
71d8d1b5
AK		 2436 if (adapter->wol)
2437 be_setup_wol(adapter, true);
2438
6b7c5b94
SP		 2439 netif_device_detach(netdev);
2440 if (netif_running(netdev)) {
2441 rtnl_lock();
2442 be_close(netdev);
2443 rtnl_unlock();
2444 }
9e90c961 2445 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 2446 be_clear(adapter);
6b7c5b94
SP		 2447
2448 pci_save_state(pdev);
2449 pci_disable_device(pdev);
2450 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2451 return 0;
2452}
2453
2454static int be_resume(struct pci_dev *pdev)
2455{
2456 int status = 0;
2457 struct be_adapter *adapter = pci_get_drvdata(pdev);
2458 struct net_device *netdev = adapter->netdev;
2459
2460 netif_device_detach(netdev);
2461
2462 status = pci_enable_device(pdev);
2463 if (status)
2464 return status;
2465
2466 pci_set_power_state(pdev, 0);
2467 pci_restore_state(pdev);
2468
2243e2e9
SP		 2469 /* tell fw we're ready to fire cmds */
2470 status = be_cmd_fw_init(adapter);
2471 if (status)
2472 return status;
2473
9b0365f1 2474 be_setup(adapter);
6b7c5b94
SP		 2475 if (netif_running(netdev)) {
2476 rtnl_lock();
2477 be_open(netdev);
2478 rtnl_unlock();
2479 }
2480 netif_device_attach(netdev);
71d8d1b5
AK		 2481
2482 if (adapter->wol)
2483 be_setup_wol(adapter, false);
6b7c5b94
SP		 2484 return 0;
2485}
2486
82456b03
SP		 2487/*
2488 * An FLR will stop BE from DMAing any data.
2489 */
2490static void be_shutdown(struct pci_dev *pdev)
2491{
2492 struct be_adapter *adapter = pci_get_drvdata(pdev);
2493 struct net_device *netdev = adapter->netdev;
2494
2495 netif_device_detach(netdev);
2496
2497 be_cmd_reset_function(adapter);
2498
2499 if (adapter->wol)
2500 be_setup_wol(adapter, true);
2501
2502 pci_disable_device(pdev);
2503
2504 return;
2505}
2506
cf588477
SP		 2507static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
2508 pci_channel_state_t state)
2509{
2510 struct be_adapter *adapter = pci_get_drvdata(pdev);
2511 struct net_device *netdev = adapter->netdev;
2512
2513 dev_err(&adapter->pdev->dev, "EEH error detected\n");
2514
2515 adapter->eeh_err = true;
2516
2517 netif_device_detach(netdev);
2518
2519 if (netif_running(netdev)) {
2520 rtnl_lock();
2521 be_close(netdev);
2522 rtnl_unlock();
2523 }
2524 be_clear(adapter);
2525
2526 if (state == pci_channel_io_perm_failure)
2527 return PCI_ERS_RESULT_DISCONNECT;
2528
2529 pci_disable_device(pdev);
2530
2531 return PCI_ERS_RESULT_NEED_RESET;
2532}
2533
2534static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
2535{
2536 struct be_adapter *adapter = pci_get_drvdata(pdev);
2537 int status;
2538
2539 dev_info(&adapter->pdev->dev, "EEH reset\n");
2540 adapter->eeh_err = false;
2541
2542 status = pci_enable_device(pdev);
2543 if (status)
2544 return PCI_ERS_RESULT_DISCONNECT;
2545
2546 pci_set_master(pdev);
2547 pci_set_power_state(pdev, 0);
2548 pci_restore_state(pdev);
2549
2550 /* Check if card is ok and fw is ready */
2551 status = be_cmd_POST(adapter);
2552 if (status)
2553 return PCI_ERS_RESULT_DISCONNECT;
2554
2555 return PCI_ERS_RESULT_RECOVERED;
2556}
2557
2558static void be_eeh_resume(struct pci_dev *pdev)
2559{
2560 int status = 0;
2561 struct be_adapter *adapter = pci_get_drvdata(pdev);
2562 struct net_device *netdev = adapter->netdev;
2563
2564 dev_info(&adapter->pdev->dev, "EEH resume\n");
2565
2566 pci_save_state(pdev);
2567
2568 /* tell fw we're ready to fire cmds */
2569 status = be_cmd_fw_init(adapter);
2570 if (status)
2571 goto err;
2572
2573 status = be_setup(adapter);
2574 if (status)
2575 goto err;
2576
2577 if (netif_running(netdev)) {
2578 status = be_open(netdev);
2579 if (status)
2580 goto err;
2581 }
2582 netif_device_attach(netdev);
2583 return;
2584err:
2585 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
2586 return;
2587}
2588
2589static struct pci_error_handlers be_eeh_handlers = {
2590 .error_detected = be_eeh_err_detected,
2591 .slot_reset = be_eeh_reset,
2592 .resume = be_eeh_resume,
2593};
2594
6b7c5b94
SP		 2595static struct pci_driver be_driver = {
2596 .name = DRV_NAME,
2597 .id_table = be_dev_ids,
2598 .probe = be_probe,
2599 .remove = be_remove,
2600 .suspend = be_suspend,
cf588477 2601 .resume = be_resume,
82456b03 2602 .shutdown = be_shutdown,
cf588477 2603 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 2604};
2605
2606static int __init be_init_module(void)
2607{
8e95a202
JP		 2608 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
2609 rx_frag_size != 2048) {
6b7c5b94
SP		 2610 printk(KERN_WARNING DRV_NAME
2611 " : Module param rx_frag_size must be 2048/4096/8192."
2612 " Using 2048\n");
2613 rx_frag_size = 2048;
2614 }
6b7c5b94
SP		 2615
2616 return pci_register_driver(&be_driver);
2617}
2618module_init(be_init_module);
2619
2620static void __exit be_exit_module(void)
2621{
2622 pci_unregister_driver(&be_driver);
2623}
2624module_exit(be_exit_module);
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