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[net-next-2.6.git] / drivers / net / benet / be_main.c
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6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
28static unsigned int rx_frag_size = 2048;
29module_param(rx_frag_size, uint, S_IRUGO);
30MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
31
6b7c5b94 32static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 33 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 34 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 35 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
36 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
6b7c5b94
SP		 37 { 0 }
38};
39MODULE_DEVICE_TABLE(pci, be_dev_ids);
40
41static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
42{
43 struct be_dma_mem *mem = &q->dma_mem;
44 if (mem->va)
45 pci_free_consistent(adapter->pdev, mem->size,
46 mem->va, mem->dma);
47}
48
49static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
50 u16 len, u16 entry_size)
51{
52 struct be_dma_mem *mem = &q->dma_mem;
53
54 memset(q, 0, sizeof(*q));
55 q->len = len;
56 q->entry_size = entry_size;
57 mem->size = len * entry_size;
58 mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
59 if (!mem->va)
60 return -1;
61 memset(mem->va, 0, mem->size);
62 return 0;
63}
64
8788fdc2 65static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 66{
8788fdc2 67 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 68 u32 reg = ioread32(addr);
69 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 70
cf588477
SP		 71 if (adapter->eeh_err)
72 return;
73
5f0b849e 74 if (!enabled && enable)
6b7c5b94 75 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 76 else if (enabled && !enable)
6b7c5b94 77 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 78 else
6b7c5b94 79 return;
5f0b849e 80
6b7c5b94
SP		 81 iowrite32(reg, addr);
82}
83
8788fdc2 84static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 85{
86 u32 val = 0;
87 val |= qid & DB_RQ_RING_ID_MASK;
88 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
8788fdc2 89 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 90}
91
8788fdc2 92static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 93{
94 u32 val = 0;
95 val |= qid & DB_TXULP_RING_ID_MASK;
96 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
8788fdc2 97 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 98}
99
8788fdc2 100static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 101 bool arm, bool clear_int, u16 num_popped)
102{
103 u32 val = 0;
104 val |= qid & DB_EQ_RING_ID_MASK;
cf588477
SP		 105
106 if (adapter->eeh_err)
107 return;
108
6b7c5b94
SP		 109 if (arm)
110 val |= 1 << DB_EQ_REARM_SHIFT;
111 if (clear_int)
112 val |= 1 << DB_EQ_CLR_SHIFT;
113 val |= 1 << DB_EQ_EVNT_SHIFT;
114 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 115 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 116}
117
8788fdc2 118void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 119{
120 u32 val = 0;
121 val |= qid & DB_CQ_RING_ID_MASK;
cf588477
SP		 122
123 if (adapter->eeh_err)
124 return;
125
6b7c5b94
SP		 126 if (arm)
127 val |= 1 << DB_CQ_REARM_SHIFT;
128 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 129 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 130}
131
6b7c5b94
SP		 132static int be_mac_addr_set(struct net_device *netdev, void *p)
133{
134 struct be_adapter *adapter = netdev_priv(netdev);
135 struct sockaddr *addr = p;
136 int status = 0;
137
ca9e4988
AK		 138 if (!is_valid_ether_addr(addr->sa_data))
139 return -EADDRNOTAVAIL;
140
a65027e4
SP		 141 status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
142 if (status)
143 return status;
6b7c5b94 144
a65027e4
SP		 145 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
146 adapter->if_handle, &adapter->pmac_id);
6b7c5b94
SP		 147 if (!status)
148 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
149
150 return status;
151}
152
b31c50a7 153void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94
SP		 154{
155 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
156 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
157 struct be_port_rxf_stats *port_stats =
158 &rxf_stats->port[adapter->port_num];
78122a52 159 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 160 struct be_erx_stats *erx_stats = &hw_stats->erx;
6b7c5b94 161
91992e44
AK		 162 dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
163 dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
164 dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
165 dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 166
167 /* bad pkts received */
168 dev_stats->rx_errors = port_stats->rx_crc_errors +
169 port_stats->rx_alignment_symbol_errors +
170 port_stats->rx_in_range_errors +
68110868
SP		 171 port_stats->rx_out_range_errors +
172 port_stats->rx_frame_too_long +
173 port_stats->rx_dropped_too_small +
174 port_stats->rx_dropped_too_short +
175 port_stats->rx_dropped_header_too_small +
176 port_stats->rx_dropped_tcp_length +
177 port_stats->rx_dropped_runt +
178 port_stats->rx_tcp_checksum_errs +
179 port_stats->rx_ip_checksum_errs +
180 port_stats->rx_udp_checksum_errs;
181
182 /* no space in linux buffers: best possible approximation */
01ed30da
SP		 183 dev_stats->rx_dropped =
184 erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
6b7c5b94
SP		 185
186 /* detailed rx errors */
187 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 188 port_stats->rx_out_range_errors +
189 port_stats->rx_frame_too_long;
190
6b7c5b94
SP		 191 /* receive ring buffer overflow */
192 dev_stats->rx_over_errors = 0;
68110868 193
6b7c5b94
SP		 194 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
195
196 /* frame alignment errors */
197 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 198
6b7c5b94
SP		 199 /* receiver fifo overrun */
200 /* drops_no_pbuf is no per i/f, it's per BE card */
201 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
202 port_stats->rx_input_fifo_overflow +
203 rxf_stats->rx_drops_no_pbuf;
204 /* receiver missed packetd */
205 dev_stats->rx_missed_errors = 0;
68110868
SP		 206
207 /* packet transmit problems */
208 dev_stats->tx_errors = 0;
209
210 /* no space available in linux */
211 dev_stats->tx_dropped = 0;
212
c5b9b92e 213 dev_stats->multicast = port_stats->rx_multicast_frames;
68110868
SP		 214 dev_stats->collisions = 0;
215
6b7c5b94
SP		 216 /* detailed tx_errors */
217 dev_stats->tx_aborted_errors = 0;
218 dev_stats->tx_carrier_errors = 0;
219 dev_stats->tx_fifo_errors = 0;
220 dev_stats->tx_heartbeat_errors = 0;
221 dev_stats->tx_window_errors = 0;
222}
223
8788fdc2 224void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 225{
6b7c5b94
SP		 226 struct net_device *netdev = adapter->netdev;
227
6b7c5b94 228 /* If link came up or went down */
a8f447bd 229 if (adapter->link_up != link_up) {
0dffc83e 230 adapter->link_speed = -1;
a8f447bd 231 if (link_up) {
6b7c5b94
SP		 232 netif_start_queue(netdev);
233 netif_carrier_on(netdev);
234 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd
SP		 235 } else {
236 netif_stop_queue(netdev);
237 netif_carrier_off(netdev);
238 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 239 }
a8f447bd 240 adapter->link_up = link_up;
6b7c5b94 241 }
6b7c5b94
SP		 242}
243
244/* Update the EQ delay n BE based on the RX frags consumed / sec */
245static void be_rx_eqd_update(struct be_adapter *adapter)
246{
6b7c5b94
SP		 247 struct be_eq_obj *rx_eq = &adapter->rx_eq;
248 struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
4097f663
SP		 249 ulong now = jiffies;
250 u32 eqd;
251
252 if (!rx_eq->enable_aic)
253 return;
254
255 /* Wrapped around */
256 if (time_before(now, stats->rx_fps_jiffies)) {
257 stats->rx_fps_jiffies = now;
258 return;
259 }
6b7c5b94
SP		 260
261 /* Update once a second */
4097f663 262 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 263 return;
264
265 stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
4097f663 266 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 267
4097f663 268 stats->rx_fps_jiffies = now;
6b7c5b94
SP		 269 stats->be_prev_rx_frags = stats->be_rx_frags;
270 eqd = stats->be_rx_fps / 110000;
271 eqd = eqd << 3;
272 if (eqd > rx_eq->max_eqd)
273 eqd = rx_eq->max_eqd;
274 if (eqd < rx_eq->min_eqd)
275 eqd = rx_eq->min_eqd;
276 if (eqd < 10)
277 eqd = 0;
278 if (eqd != rx_eq->cur_eqd)
8788fdc2 279 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 280
281 rx_eq->cur_eqd = eqd;
282}
283
6b7c5b94
SP		 284static struct net_device_stats *be_get_stats(struct net_device *dev)
285{
78122a52 286 return &dev->stats;
6b7c5b94
SP		 287}
288
65f71b8b
SH		 289static u32 be_calc_rate(u64 bytes, unsigned long ticks)
290{
291 u64 rate = bytes;
292
293 do_div(rate, ticks / HZ);
294 rate <<= 3; /* bytes/sec -> bits/sec */
295 do_div(rate, 1000000ul); /* MB/Sec */
296
297 return rate;
298}
299
4097f663
SP		 300static void be_tx_rate_update(struct be_adapter *adapter)
301{
302 struct be_drvr_stats *stats = drvr_stats(adapter);
303 ulong now = jiffies;
304
305 /* Wrapped around? */
306 if (time_before(now, stats->be_tx_jiffies)) {
307 stats->be_tx_jiffies = now;
308 return;
309 }
310
311 /* Update tx rate once in two seconds */
312 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 313 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
314 - stats->be_tx_bytes_prev,
315 now - stats->be_tx_jiffies);
4097f663
SP		 316 stats->be_tx_jiffies = now;
317 stats->be_tx_bytes_prev = stats->be_tx_bytes;
318 }
319}
320
6b7c5b94 321static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 322 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 323{
4097f663 324 struct be_drvr_stats *stats = drvr_stats(adapter);
6b7c5b94
SP		 325 stats->be_tx_reqs++;
326 stats->be_tx_wrbs += wrb_cnt;
327 stats->be_tx_bytes += copied;
91992e44 328 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 329 if (stopped)
330 stats->be_tx_stops++;
6b7c5b94
SP		 331}
332
333/* Determine number of WRB entries needed to xmit data in an skb */
334static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
335{
ebc8d2ab
DM		 336 int cnt = (skb->len > skb->data_len);
337
338 cnt += skb_shinfo(skb)->nr_frags;
339
6b7c5b94
SP		 340 /* to account for hdr wrb */
341 cnt++;
342 if (cnt & 1) {
343 /* add a dummy to make it an even num */
344 cnt++;
345 *dummy = true;
346 } else
347 *dummy = false;
348 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
349 return cnt;
350}
351
352static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
353{
354 wrb->frag_pa_hi = upper_32_bits(addr);
355 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
356 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
357}
358
359static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
360 bool vlan, u32 wrb_cnt, u32 len)
361{
362 memset(hdr, 0, sizeof(*hdr));
363
364 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
365
366 if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) {
367 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
368 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
369 hdr, skb_shinfo(skb)->gso_size);
370 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
371 if (is_tcp_pkt(skb))
372 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
373 else if (is_udp_pkt(skb))
374 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
375 }
376
377 if (vlan && vlan_tx_tag_present(skb)) {
378 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
379 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
380 hdr, vlan_tx_tag_get(skb));
381 }
382
383 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
384 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
385 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
386 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
387}
388
7101e111
SP		 389static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
390 bool unmap_single)
391{
392 dma_addr_t dma;
393
394 be_dws_le_to_cpu(wrb, sizeof(*wrb));
395
396 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
397 if (dma != 0) {
398 if (unmap_single)
399 pci_unmap_single(pdev, dma, wrb->frag_len,
400 PCI_DMA_TODEVICE);
401 else
402 pci_unmap_page(pdev, dma, wrb->frag_len,
403 PCI_DMA_TODEVICE);
404 }
405}
6b7c5b94
SP		 406
407static int make_tx_wrbs(struct be_adapter *adapter,
408 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
409{
7101e111
SP		 410 dma_addr_t busaddr;
411 int i, copied = 0;
6b7c5b94
SP		 412 struct pci_dev *pdev = adapter->pdev;
413 struct sk_buff *first_skb = skb;
414 struct be_queue_info *txq = &adapter->tx_obj.q;
415 struct be_eth_wrb *wrb;
416 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 417 bool map_single = false;
418 u16 map_head;
6b7c5b94 419
6b7c5b94
SP		 420 hdr = queue_head_node(txq);
421 queue_head_inc(txq);
7101e111 422 map_head = txq->head;
6b7c5b94 423
ebc8d2ab
DM		 424 if (skb->len > skb->data_len) {
425 int len = skb->len - skb->data_len;
a73b796e
AD		 426 busaddr = pci_map_single(pdev, skb->data, len,
427 PCI_DMA_TODEVICE);
7101e111
SP		 428 if (pci_dma_mapping_error(pdev, busaddr))
429 goto dma_err;
430 map_single = true;
ebc8d2ab
DM		 431 wrb = queue_head_node(txq);
432 wrb_fill(wrb, busaddr, len);
433 be_dws_cpu_to_le(wrb, sizeof(*wrb));
434 queue_head_inc(txq);
435 copied += len;
436 }
6b7c5b94 437
ebc8d2ab
DM		 438 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
439 struct skb_frag_struct *frag =
440 &skb_shinfo(skb)->frags[i];
a73b796e
AD		 441 busaddr = pci_map_page(pdev, frag->page,
442 frag->page_offset,
443 frag->size, PCI_DMA_TODEVICE);
7101e111
SP		 444 if (pci_dma_mapping_error(pdev, busaddr))
445 goto dma_err;
ebc8d2ab
DM		 446 wrb = queue_head_node(txq);
447 wrb_fill(wrb, busaddr, frag->size);
448 be_dws_cpu_to_le(wrb, sizeof(*wrb));
449 queue_head_inc(txq);
450 copied += frag->size;
6b7c5b94
SP		 451 }
452
453 if (dummy_wrb) {
454 wrb = queue_head_node(txq);
455 wrb_fill(wrb, 0, 0);
456 be_dws_cpu_to_le(wrb, sizeof(*wrb));
457 queue_head_inc(txq);
458 }
459
460 wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
461 wrb_cnt, copied);
462 be_dws_cpu_to_le(hdr, sizeof(*hdr));
463
464 return copied;
7101e111
SP		 465dma_err:
466 txq->head = map_head;
467 while (copied) {
468 wrb = queue_head_node(txq);
469 unmap_tx_frag(pdev, wrb, map_single);
470 map_single = false;
471 copied -= wrb->frag_len;
472 queue_head_inc(txq);
473 }
474 return 0;
6b7c5b94
SP		 475}
476
61357325 477static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 478 struct net_device *netdev)
6b7c5b94
SP		 479{
480 struct be_adapter *adapter = netdev_priv(netdev);
481 struct be_tx_obj *tx_obj = &adapter->tx_obj;
482 struct be_queue_info *txq = &tx_obj->q;
483 u32 wrb_cnt = 0, copied = 0;
484 u32 start = txq->head;
485 bool dummy_wrb, stopped = false;
486
487 wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
488
489 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 490 if (copied) {
491 /* record the sent skb in the sent_skb table */
492 BUG_ON(tx_obj->sent_skb_list[start]);
493 tx_obj->sent_skb_list[start] = skb;
494
495 /* Ensure txq has space for the next skb; Else stop the queue
496 * *BEFORE* ringing the tx doorbell, so that we serialze the
497 * tx compls of the current transmit which'll wake up the queue
498 */
7101e111 499 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 500 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
501 txq->len) {
502 netif_stop_queue(netdev);
503 stopped = true;
504 }
6b7c5b94 505
c190e3c8 506 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 507
91992e44
AK		 508 be_tx_stats_update(adapter, wrb_cnt, copied,
509 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 510 } else {
511 txq->head = start;
512 dev_kfree_skb_any(skb);
6b7c5b94 513 }
6b7c5b94
SP		 514 return NETDEV_TX_OK;
515}
516
517static int be_change_mtu(struct net_device *netdev, int new_mtu)
518{
519 struct be_adapter *adapter = netdev_priv(netdev);
520 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 521 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
522 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 523 dev_info(&adapter->pdev->dev,
524 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 525 BE_MIN_MTU,
526 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 527 return -EINVAL;
528 }
529 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
530 netdev->mtu, new_mtu);
531 netdev->mtu = new_mtu;
532 return 0;
533}
534
535/*
82903e4b
AK		 536 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
537 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 538 */
b31c50a7 539static int be_vid_config(struct be_adapter *adapter)
6b7c5b94 540{
6b7c5b94
SP		 541 u16 vtag[BE_NUM_VLANS_SUPPORTED];
542 u16 ntags = 0, i;
82903e4b 543 int status = 0;
6b7c5b94 544
82903e4b 545 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94
SP		 546 /* Construct VLAN Table to give to HW */
547 for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
548 if (adapter->vlan_tag[i]) {
549 vtag[ntags] = cpu_to_le16(i);
550 ntags++;
551 }
552 }
b31c50a7
SP		 553 status = be_cmd_vlan_config(adapter, adapter->if_handle,
554 vtag, ntags, 1, 0);
6b7c5b94 555 } else {
b31c50a7
SP		 556 status = be_cmd_vlan_config(adapter, adapter->if_handle,
557 NULL, 0, 1, 1);
6b7c5b94 558 }
b31c50a7 559 return status;
6b7c5b94
SP		 560}
561
562static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
563{
564 struct be_adapter *adapter = netdev_priv(netdev);
565 struct be_eq_obj *rx_eq = &adapter->rx_eq;
566 struct be_eq_obj *tx_eq = &adapter->tx_eq;
6b7c5b94 567
8788fdc2
SP		 568 be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
569 be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
6b7c5b94 570 adapter->vlan_grp = grp;
8788fdc2
SP		 571 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
572 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
6b7c5b94
SP		 573}
574
575static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
576{
577 struct be_adapter *adapter = netdev_priv(netdev);
578
6b7c5b94 579 adapter->vlan_tag[vid] = 1;
82903e4b
AK		 580 adapter->vlans_added++;
581 if (adapter->vlans_added <= (adapter->max_vlans + 1))
582 be_vid_config(adapter);
6b7c5b94
SP		 583}
584
585static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
586{
587 struct be_adapter *adapter = netdev_priv(netdev);
588
6b7c5b94 589 adapter->vlan_tag[vid] = 0;
6b7c5b94 590 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
82903e4b
AK		 591 adapter->vlans_added--;
592 if (adapter->vlans_added <= adapter->max_vlans)
593 be_vid_config(adapter);
6b7c5b94
SP		 594}
595
24307eef 596static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 597{
598 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 599
24307eef 600 if (netdev->flags & IFF_PROMISC) {
8788fdc2 601 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 602 adapter->promiscuous = true;
603 goto done;
6b7c5b94
SP		 604 }
605
24307eef
SP		 606 /* BE was previously in promiscous mode; disable it */
607 if (adapter->promiscuous) {
608 adapter->promiscuous = false;
8788fdc2 609 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 610 }
611
e7b909a6 612 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 613 if (netdev->flags & IFF_ALLMULTI ||
614 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 615 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 616 &adapter->mc_cmd_mem);
24307eef 617 goto done;
6b7c5b94 618 }
6b7c5b94 619
0ddf477b 620 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 621 &adapter->mc_cmd_mem);
24307eef
SP		 622done:
623 return;
6b7c5b94
SP		 624}
625
4097f663 626static void be_rx_rate_update(struct be_adapter *adapter)
6b7c5b94 627{
4097f663
SP		 628 struct be_drvr_stats *stats = drvr_stats(adapter);
629 ulong now = jiffies;
6b7c5b94 630
4097f663
SP		 631 /* Wrapped around */
632 if (time_before(now, stats->be_rx_jiffies)) {
633 stats->be_rx_jiffies = now;
634 return;
635 }
6b7c5b94
SP		 636
637 /* Update the rate once in two seconds */
4097f663 638 if ((now - stats->be_rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 639 return;
640
65f71b8b
SH		 641 stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
642 - stats->be_rx_bytes_prev,
643 now - stats->be_rx_jiffies);
4097f663 644 stats->be_rx_jiffies = now;
6b7c5b94
SP		 645 stats->be_rx_bytes_prev = stats->be_rx_bytes;
646}
647
4097f663
SP		 648static void be_rx_stats_update(struct be_adapter *adapter,
649 u32 pktsize, u16 numfrags)
650{
651 struct be_drvr_stats *stats = drvr_stats(adapter);
652
653 stats->be_rx_compl++;
654 stats->be_rx_frags += numfrags;
655 stats->be_rx_bytes += pktsize;
91992e44 656 stats->be_rx_pkts++;
4097f663
SP		 657}
658
728a9972
AK		 659static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
660{
661 u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
662
663 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
664 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
665 ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
666 if (ip_version) {
667 tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
668 udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
669 }
670 ipv6_chk = (ip_version && (tcpf || udpf));
671
672 return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
673}
674
6b7c5b94
SP		 675static struct be_rx_page_info *
676get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
677{
678 struct be_rx_page_info *rx_page_info;
679 struct be_queue_info *rxq = &adapter->rx_obj.q;
680
681 rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
682 BUG_ON(!rx_page_info->page);
683
205859a2 684 if (rx_page_info->last_page_user) {
6b7c5b94
SP		 685 pci_unmap_page(adapter->pdev, pci_unmap_addr(rx_page_info, bus),
686 adapter->big_page_size, PCI_DMA_FROMDEVICE);
205859a2
AK		 687 rx_page_info->last_page_user = false;
688 }
6b7c5b94
SP		 689
690 atomic_dec(&rxq->used);
691 return rx_page_info;
692}
693
694/* Throwaway the data in the Rx completion */
695static void be_rx_compl_discard(struct be_adapter *adapter,
696 struct be_eth_rx_compl *rxcp)
697{
698 struct be_queue_info *rxq = &adapter->rx_obj.q;
699 struct be_rx_page_info *page_info;
700 u16 rxq_idx, i, num_rcvd;
701
702 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
703 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
704
705 for (i = 0; i < num_rcvd; i++) {
706 page_info = get_rx_page_info(adapter, rxq_idx);
707 put_page(page_info->page);
708 memset(page_info, 0, sizeof(*page_info));
709 index_inc(&rxq_idx, rxq->len);
710 }
711}
712
713/*
714 * skb_fill_rx_data forms a complete skb for an ether frame
715 * indicated by rxcp.
716 */
717static void skb_fill_rx_data(struct be_adapter *adapter,
89420424
SP		 718 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
719 u16 num_rcvd)
6b7c5b94
SP		 720{
721 struct be_queue_info *rxq = &adapter->rx_obj.q;
722 struct be_rx_page_info *page_info;
89420424 723 u16 rxq_idx, i, j;
fa77406a 724 u32 pktsize, hdr_len, curr_frag_len, size;
6b7c5b94
SP		 725 u8 *start;
726
727 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
728 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
6b7c5b94
SP		 729
730 page_info = get_rx_page_info(adapter, rxq_idx);
731
732 start = page_address(page_info->page) + page_info->page_offset;
733 prefetch(start);
734
735 /* Copy data in the first descriptor of this completion */
736 curr_frag_len = min(pktsize, rx_frag_size);
737
738 /* Copy the header portion into skb_data */
739 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
740 memcpy(skb->data, start, hdr_len);
741 skb->len = curr_frag_len;
742 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
743 /* Complete packet has now been moved to data */
744 put_page(page_info->page);
745 skb->data_len = 0;
746 skb->tail += curr_frag_len;
747 } else {
748 skb_shinfo(skb)->nr_frags = 1;
749 skb_shinfo(skb)->frags[0].page = page_info->page;
750 skb_shinfo(skb)->frags[0].page_offset =
751 page_info->page_offset + hdr_len;
752 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
753 skb->data_len = curr_frag_len - hdr_len;
754 skb->tail += hdr_len;
755 }
205859a2 756 page_info->page = NULL;
6b7c5b94
SP		 757
758 if (pktsize <= rx_frag_size) {
759 BUG_ON(num_rcvd != 1);
76fbb429 760 goto done;
6b7c5b94
SP		 761 }
762
763 /* More frags present for this completion */
fa77406a 764 size = pktsize;
bd46cb6c 765 for (i = 1, j = 0; i < num_rcvd; i++) {
fa77406a 766 size -= curr_frag_len;
6b7c5b94
SP		 767 index_inc(&rxq_idx, rxq->len);
768 page_info = get_rx_page_info(adapter, rxq_idx);
769
fa77406a 770 curr_frag_len = min(size, rx_frag_size);
6b7c5b94 771
bd46cb6c
AK		 772 /* Coalesce all frags from the same physical page in one slot */
773 if (page_info->page_offset == 0) {
774 /* Fresh page */
775 j++;
776 skb_shinfo(skb)->frags[j].page = page_info->page;
777 skb_shinfo(skb)->frags[j].page_offset =
778 page_info->page_offset;
779 skb_shinfo(skb)->frags[j].size = 0;
780 skb_shinfo(skb)->nr_frags++;
781 } else {
782 put_page(page_info->page);
783 }
784
785 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 786 skb->len += curr_frag_len;
787 skb->data_len += curr_frag_len;
6b7c5b94 788
205859a2 789 page_info->page = NULL;
6b7c5b94 790 }
bd46cb6c 791 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 792
76fbb429 793done:
4097f663 794 be_rx_stats_update(adapter, pktsize, num_rcvd);
6b7c5b94
SP		 795 return;
796}
797
5be93b9a 798/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94
SP		 799static void be_rx_compl_process(struct be_adapter *adapter,
800 struct be_eth_rx_compl *rxcp)
801{
802 struct sk_buff *skb;
dcb9b564 803 u32 vlanf, vid;
89420424 804 u16 num_rcvd;
dcb9b564 805 u8 vtm;
6b7c5b94 806
89420424
SP		 807 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
808 /* Is it a flush compl that has no data */
809 if (unlikely(num_rcvd == 0))
810 return;
811
89d71a66 812 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 813 if (unlikely(!skb)) {
6b7c5b94
SP		 814 if (net_ratelimit())
815 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
816 be_rx_compl_discard(adapter, rxcp);
817 return;
818 }
819
89420424 820 skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
6b7c5b94 821
728a9972 822 if (do_pkt_csum(rxcp, adapter->rx_csum))
6b7c5b94 823 skb->ip_summed = CHECKSUM_NONE;
728a9972
AK		 824 else
825 skb->ip_summed = CHECKSUM_UNNECESSARY;
6b7c5b94
SP		 826
827 skb->truesize = skb->len + sizeof(struct sk_buff);
828 skb->protocol = eth_type_trans(skb, adapter->netdev);
829 skb->dev = adapter->netdev;
830
a058a632
SP		 831 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
832 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
833
834 /* vlanf could be wrongly set in some cards.
835 * ignore if vtm is not set */
836 if ((adapter->cap & 0x400) && !vtm)
837 vlanf = 0;
838
839 if (unlikely(vlanf)) {
82903e4b 840 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 841 kfree_skb(skb);
842 return;
843 }
844 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
845 vid = be16_to_cpu(vid);
846 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
847 } else {
848 netif_receive_skb(skb);
849 }
850
6b7c5b94
SP		 851 return;
852}
853
5be93b9a
AK		 854/* Process the RX completion indicated by rxcp when GRO is enabled */
855static void be_rx_compl_process_gro(struct be_adapter *adapter,
6b7c5b94
SP		 856 struct be_eth_rx_compl *rxcp)
857{
858 struct be_rx_page_info *page_info;
5be93b9a 859 struct sk_buff *skb = NULL;
6b7c5b94 860 struct be_queue_info *rxq = &adapter->rx_obj.q;
5be93b9a 861 struct be_eq_obj *eq_obj = &adapter->rx_eq;
6b7c5b94 862 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
bd46cb6c 863 u16 i, rxq_idx = 0, vid, j;
dcb9b564 864 u8 vtm;
6b7c5b94
SP		 865
866 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
89420424
SP		 867 /* Is it a flush compl that has no data */
868 if (unlikely(num_rcvd == 0))
869 return;
870
6b7c5b94
SP		 871 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
872 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
873 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
dcb9b564
AK		 874 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
875
876 /* vlanf could be wrongly set in some cards.
877 * ignore if vtm is not set */
e1187b3b 878 if ((adapter->cap & 0x400) && !vtm)
dcb9b564 879 vlanf = 0;
6b7c5b94 880
5be93b9a
AK		 881 skb = napi_get_frags(&eq_obj->napi);
882 if (!skb) {
883 be_rx_compl_discard(adapter, rxcp);
884 return;
885 }
886
6b7c5b94 887 remaining = pkt_size;
bd46cb6c 888 for (i = 0, j = -1; i < num_rcvd; i++) {
6b7c5b94
SP		 889 page_info = get_rx_page_info(adapter, rxq_idx);
890
891 curr_frag_len = min(remaining, rx_frag_size);
892
bd46cb6c
AK		 893 /* Coalesce all frags from the same physical page in one slot */
894 if (i == 0 || page_info->page_offset == 0) {
895 /* First frag or Fresh page */
896 j++;
5be93b9a
AK		 897 skb_shinfo(skb)->frags[j].page = page_info->page;
898 skb_shinfo(skb)->frags[j].page_offset =
899 page_info->page_offset;
900 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 901 } else {
902 put_page(page_info->page);
903 }
5be93b9a 904 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 905
bd46cb6c 906 remaining -= curr_frag_len;
6b7c5b94 907 index_inc(&rxq_idx, rxq->len);
6b7c5b94
SP		 908 memset(page_info, 0, sizeof(*page_info));
909 }
bd46cb6c 910 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 911
5be93b9a
AK		 912 skb_shinfo(skb)->nr_frags = j + 1;
913 skb->len = pkt_size;
914 skb->data_len = pkt_size;
915 skb->truesize += pkt_size;
916 skb->ip_summed = CHECKSUM_UNNECESSARY;
917
6b7c5b94 918 if (likely(!vlanf)) {
5be93b9a 919 napi_gro_frags(&eq_obj->napi);
6b7c5b94
SP		 920 } else {
921 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
922 vid = be16_to_cpu(vid);
923
82903e4b 924 if (!adapter->vlan_grp || adapter->vlans_added == 0)
6b7c5b94
SP		 925 return;
926
5be93b9a 927 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
6b7c5b94
SP		 928 }
929
4097f663 930 be_rx_stats_update(adapter, pkt_size, num_rcvd);
6b7c5b94
SP		 931 return;
932}
933
934static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
935{
936 struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
937
938 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
939 return NULL;
940
941 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
942
6b7c5b94
SP		 943 queue_tail_inc(&adapter->rx_obj.cq);
944 return rxcp;
945}
946
a7a0ef31
SP		 947/* To reset the valid bit, we need to reset the whole word as
948 * when walking the queue the valid entries are little-endian
949 * and invalid entries are host endian
950 */
951static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
952{
953 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
954}
955
6b7c5b94
SP		 956static inline struct page *be_alloc_pages(u32 size)
957{
958 gfp_t alloc_flags = GFP_ATOMIC;
959 u32 order = get_order(size);
960 if (order > 0)
961 alloc_flags |= __GFP_COMP;
962 return alloc_pages(alloc_flags, order);
963}
964
965/*
966 * Allocate a page, split it to fragments of size rx_frag_size and post as
967 * receive buffers to BE
968 */
969static void be_post_rx_frags(struct be_adapter *adapter)
970{
971 struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
26d92f92 972 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
6b7c5b94
SP		 973 struct be_queue_info *rxq = &adapter->rx_obj.q;
974 struct page *pagep = NULL;
975 struct be_eth_rx_d *rxd;
976 u64 page_dmaaddr = 0, frag_dmaaddr;
977 u32 posted, page_offset = 0;
978
6b7c5b94
SP		 979 page_info = &page_info_tbl[rxq->head];
980 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
981 if (!pagep) {
982 pagep = be_alloc_pages(adapter->big_page_size);
983 if (unlikely(!pagep)) {
984 drvr_stats(adapter)->be_ethrx_post_fail++;
985 break;
986 }
987 page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
988 adapter->big_page_size,
989 PCI_DMA_FROMDEVICE);
990 page_info->page_offset = 0;
991 } else {
992 get_page(pagep);
993 page_info->page_offset = page_offset + rx_frag_size;
994 }
995 page_offset = page_info->page_offset;
996 page_info->page = pagep;
997 pci_unmap_addr_set(page_info, bus, page_dmaaddr);
998 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
999
1000 rxd = queue_head_node(rxq);
1001 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1002 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1003
1004 /* Any space left in the current big page for another frag? */
1005 if ((page_offset + rx_frag_size + rx_frag_size) >
1006 adapter->big_page_size) {
1007 pagep = NULL;
1008 page_info->last_page_user = true;
1009 }
26d92f92
SP		 1010
1011 prev_page_info = page_info;
1012 queue_head_inc(rxq);
6b7c5b94
SP		 1013 page_info = &page_info_tbl[rxq->head];
1014 }
1015 if (pagep)
26d92f92 1016 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1017
1018 if (posted) {
6b7c5b94 1019 atomic_add(posted, &rxq->used);
8788fdc2 1020 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1021 } else if (atomic_read(&rxq->used) == 0) {
1022 /* Let be_worker replenish when memory is available */
1023 adapter->rx_post_starved = true;
6b7c5b94
SP		 1024 }
1025
1026 return;
1027}
1028
5fb379ee 1029static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1030{
6b7c5b94
SP		 1031 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1032
1033 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1034 return NULL;
1035
1036 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1037
1038 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1039
1040 queue_tail_inc(tx_cq);
1041 return txcp;
1042}
1043
1044static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1045{
1046 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1047 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1048 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1049 struct sk_buff *sent_skb;
ec43b1a6
SP		 1050 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1051 bool unmap_skb_hdr = true;
6b7c5b94 1052
ec43b1a6 1053 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1054 BUG_ON(!sent_skb);
ec43b1a6
SP		 1055 sent_skbs[txq->tail] = NULL;
1056
1057 /* skip header wrb */
a73b796e 1058 queue_tail_inc(txq);
6b7c5b94 1059
ec43b1a6 1060 do {
6b7c5b94 1061 cur_index = txq->tail;
a73b796e 1062 wrb = queue_tail_node(txq);
ec43b1a6
SP		 1063 unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
1064 sent_skb->len > sent_skb->data_len));
1065 unmap_skb_hdr = false;
1066
6b7c5b94
SP		 1067 num_wrbs++;
1068 queue_tail_inc(txq);
ec43b1a6 1069 } while (cur_index != last_index);
6b7c5b94
SP		 1070
1071 atomic_sub(num_wrbs, &txq->used);
a73b796e 1072
6b7c5b94
SP		 1073 kfree_skb(sent_skb);
1074}
1075
859b1e4e
SP		 1076static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1077{
1078 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1079
1080 if (!eqe->evt)
1081 return NULL;
1082
1083 eqe->evt = le32_to_cpu(eqe->evt);
1084 queue_tail_inc(&eq_obj->q);
1085 return eqe;
1086}
1087
1088static int event_handle(struct be_adapter *adapter,
1089 struct be_eq_obj *eq_obj)
1090{
1091 struct be_eq_entry *eqe;
1092 u16 num = 0;
1093
1094 while ((eqe = event_get(eq_obj)) != NULL) {
1095 eqe->evt = 0;
1096 num++;
1097 }
1098
1099 /* Deal with any spurious interrupts that come
1100 * without events
1101 */
1102 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1103 if (num)
1104 napi_schedule(&eq_obj->napi);
1105
1106 return num;
1107}
1108
1109/* Just read and notify events without processing them.
1110 * Used at the time of destroying event queues */
1111static void be_eq_clean(struct be_adapter *adapter,
1112 struct be_eq_obj *eq_obj)
1113{
1114 struct be_eq_entry *eqe;
1115 u16 num = 0;
1116
1117 while ((eqe = event_get(eq_obj)) != NULL) {
1118 eqe->evt = 0;
1119 num++;
1120 }
1121
1122 if (num)
1123 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1124}
1125
6b7c5b94
SP		 1126static void be_rx_q_clean(struct be_adapter *adapter)
1127{
1128 struct be_rx_page_info *page_info;
1129 struct be_queue_info *rxq = &adapter->rx_obj.q;
1130 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1131 struct be_eth_rx_compl *rxcp;
1132 u16 tail;
1133
1134 /* First cleanup pending rx completions */
1135 while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
1136 be_rx_compl_discard(adapter, rxcp);
a7a0ef31 1137 be_rx_compl_reset(rxcp);
8788fdc2 1138 be_cq_notify(adapter, rx_cq->id, true, 1);
6b7c5b94
SP		 1139 }
1140
1141 /* Then free posted rx buffer that were not used */
1142 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1143 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
6b7c5b94
SP		 1144 page_info = get_rx_page_info(adapter, tail);
1145 put_page(page_info->page);
1146 memset(page_info, 0, sizeof(*page_info));
1147 }
1148 BUG_ON(atomic_read(&rxq->used));
1149}
1150
a8e9179a 1151static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1152{
a8e9179a 1153 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1154 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1155 struct be_eth_tx_compl *txcp;
1156 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1157 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1158 struct sk_buff *sent_skb;
1159 bool dummy_wrb;
a8e9179a
SP		 1160
1161 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1162 do {
1163 while ((txcp = be_tx_compl_get(tx_cq))) {
1164 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1165 wrb_index, txcp);
1166 be_tx_compl_process(adapter, end_idx);
1167 cmpl++;
1168 }
1169 if (cmpl) {
1170 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1171 cmpl = 0;
1172 }
1173
1174 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1175 break;
1176
1177 mdelay(1);
1178 } while (true);
1179
1180 if (atomic_read(&txq->used))
1181 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1182 atomic_read(&txq->used));
b03388d6
SP		 1183
1184 /* free posted tx for which compls will never arrive */
1185 while (atomic_read(&txq->used)) {
1186 sent_skb = sent_skbs[txq->tail];
1187 end_idx = txq->tail;
1188 index_adv(&end_idx,
1189 wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
1190 be_tx_compl_process(adapter, end_idx);
1191 }
6b7c5b94
SP		 1192}
1193
5fb379ee
SP		 1194static void be_mcc_queues_destroy(struct be_adapter *adapter)
1195{
1196 struct be_queue_info *q;
5fb379ee 1197
8788fdc2 1198 q = &adapter->mcc_obj.q;
5fb379ee 1199 if (q->created)
8788fdc2 1200 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1201 be_queue_free(adapter, q);
1202
8788fdc2 1203 q = &adapter->mcc_obj.cq;
5fb379ee 1204 if (q->created)
8788fdc2 1205 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1206 be_queue_free(adapter, q);
1207}
1208
1209/* Must be called only after TX qs are created as MCC shares TX EQ */
1210static int be_mcc_queues_create(struct be_adapter *adapter)
1211{
1212 struct be_queue_info *q, *cq;
5fb379ee
SP		 1213
1214 /* Alloc MCC compl queue */
8788fdc2 1215 cq = &adapter->mcc_obj.cq;
5fb379ee 1216 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1217 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1218 goto err;
1219
1220 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1221 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1222 goto mcc_cq_free;
1223
1224 /* Alloc MCC queue */
8788fdc2 1225 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1226 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1227 goto mcc_cq_destroy;
1228
1229 /* Ask BE to create MCC queue */
8788fdc2 1230 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1231 goto mcc_q_free;
1232
1233 return 0;
1234
1235mcc_q_free:
1236 be_queue_free(adapter, q);
1237mcc_cq_destroy:
8788fdc2 1238 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1239mcc_cq_free:
1240 be_queue_free(adapter, cq);
1241err:
1242 return -1;
1243}
1244
6b7c5b94
SP		 1245static void be_tx_queues_destroy(struct be_adapter *adapter)
1246{
1247 struct be_queue_info *q;
1248
1249 q = &adapter->tx_obj.q;
a8e9179a 1250 if (q->created)
8788fdc2 1251 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1252 be_queue_free(adapter, q);
1253
1254 q = &adapter->tx_obj.cq;
1255 if (q->created)
8788fdc2 1256 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1257 be_queue_free(adapter, q);
1258
859b1e4e
SP		 1259 /* Clear any residual events */
1260 be_eq_clean(adapter, &adapter->tx_eq);
1261
6b7c5b94
SP		 1262 q = &adapter->tx_eq.q;
1263 if (q->created)
8788fdc2 1264 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1265 be_queue_free(adapter, q);
1266}
1267
1268static int be_tx_queues_create(struct be_adapter *adapter)
1269{
1270 struct be_queue_info *eq, *q, *cq;
1271
1272 adapter->tx_eq.max_eqd = 0;
1273 adapter->tx_eq.min_eqd = 0;
1274 adapter->tx_eq.cur_eqd = 96;
1275 adapter->tx_eq.enable_aic = false;
1276 /* Alloc Tx Event queue */
1277 eq = &adapter->tx_eq.q;
1278 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1279 return -1;
1280
1281 /* Ask BE to create Tx Event queue */
8788fdc2 1282 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94
SP		 1283 goto tx_eq_free;
1284 /* Alloc TX eth compl queue */
1285 cq = &adapter->tx_obj.cq;
1286 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1287 sizeof(struct be_eth_tx_compl)))
1288 goto tx_eq_destroy;
1289
1290 /* Ask BE to create Tx eth compl queue */
8788fdc2 1291 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1292 goto tx_cq_free;
1293
1294 /* Alloc TX eth queue */
1295 q = &adapter->tx_obj.q;
1296 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1297 goto tx_cq_destroy;
1298
1299 /* Ask BE to create Tx eth queue */
8788fdc2 1300 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1301 goto tx_q_free;
1302 return 0;
1303
1304tx_q_free:
1305 be_queue_free(adapter, q);
1306tx_cq_destroy:
8788fdc2 1307 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1308tx_cq_free:
1309 be_queue_free(adapter, cq);
1310tx_eq_destroy:
8788fdc2 1311 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1312tx_eq_free:
1313 be_queue_free(adapter, eq);
1314 return -1;
1315}
1316
1317static void be_rx_queues_destroy(struct be_adapter *adapter)
1318{
1319 struct be_queue_info *q;
1320
1321 q = &adapter->rx_obj.q;
1322 if (q->created) {
8788fdc2 1323 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
89420424
SP		 1324
1325 /* After the rxq is invalidated, wait for a grace time
1326 * of 1ms for all dma to end and the flush compl to arrive
1327 */
1328 mdelay(1);
6b7c5b94
SP		 1329 be_rx_q_clean(adapter);
1330 }
1331 be_queue_free(adapter, q);
1332
1333 q = &adapter->rx_obj.cq;
1334 if (q->created)
8788fdc2 1335 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1336 be_queue_free(adapter, q);
1337
859b1e4e
SP		 1338 /* Clear any residual events */
1339 be_eq_clean(adapter, &adapter->rx_eq);
1340
6b7c5b94
SP		 1341 q = &adapter->rx_eq.q;
1342 if (q->created)
8788fdc2 1343 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1344 be_queue_free(adapter, q);
1345}
1346
1347static int be_rx_queues_create(struct be_adapter *adapter)
1348{
1349 struct be_queue_info *eq, *q, *cq;
1350 int rc;
1351
6b7c5b94
SP		 1352 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
1353 adapter->rx_eq.max_eqd = BE_MAX_EQD;
1354 adapter->rx_eq.min_eqd = 0;
1355 adapter->rx_eq.cur_eqd = 0;
1356 adapter->rx_eq.enable_aic = true;
1357
1358 /* Alloc Rx Event queue */
1359 eq = &adapter->rx_eq.q;
1360 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1361 sizeof(struct be_eq_entry));
1362 if (rc)
1363 return rc;
1364
1365 /* Ask BE to create Rx Event queue */
8788fdc2 1366 rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
6b7c5b94
SP		 1367 if (rc)
1368 goto rx_eq_free;
1369
1370 /* Alloc RX eth compl queue */
1371 cq = &adapter->rx_obj.cq;
1372 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1373 sizeof(struct be_eth_rx_compl));
1374 if (rc)
1375 goto rx_eq_destroy;
1376
1377 /* Ask BE to create Rx eth compl queue */
8788fdc2 1378 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
6b7c5b94
SP		 1379 if (rc)
1380 goto rx_cq_free;
1381
1382 /* Alloc RX eth queue */
1383 q = &adapter->rx_obj.q;
1384 rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
1385 if (rc)
1386 goto rx_cq_destroy;
1387
1388 /* Ask BE to create Rx eth queue */
8788fdc2 1389 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
6b7c5b94
SP		 1390 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
1391 if (rc)
1392 goto rx_q_free;
1393
1394 return 0;
1395rx_q_free:
1396 be_queue_free(adapter, q);
1397rx_cq_destroy:
8788fdc2 1398 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1399rx_cq_free:
1400 be_queue_free(adapter, cq);
1401rx_eq_destroy:
8788fdc2 1402 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1403rx_eq_free:
1404 be_queue_free(adapter, eq);
1405 return rc;
1406}
6b7c5b94 1407
b628bde2
SP		 1408/* There are 8 evt ids per func. Retruns the evt id's bit number */
1409static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
1410{
500ca9ba 1411 return eq_id % 8;
b628bde2
SP		 1412}
1413
6b7c5b94
SP		 1414static irqreturn_t be_intx(int irq, void *dev)
1415{
1416 struct be_adapter *adapter = dev;
8788fdc2 1417 int isr;
6b7c5b94 1418
8788fdc2 1419 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
55bdeed9 1420 (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
c001c213 1421 if (!isr)
8788fdc2 1422 return IRQ_NONE;
6b7c5b94 1423
8788fdc2
SP		 1424 event_handle(adapter, &adapter->tx_eq);
1425 event_handle(adapter, &adapter->rx_eq);
c001c213 1426
8788fdc2 1427 return IRQ_HANDLED;
6b7c5b94
SP		 1428}
1429
1430static irqreturn_t be_msix_rx(int irq, void *dev)
1431{
1432 struct be_adapter *adapter = dev;
1433
8788fdc2 1434 event_handle(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1435
1436 return IRQ_HANDLED;
1437}
1438
5fb379ee 1439static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1440{
1441 struct be_adapter *adapter = dev;
1442
8788fdc2 1443 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1444
1445 return IRQ_HANDLED;
1446}
1447
5be93b9a 1448static inline bool do_gro(struct be_adapter *adapter,
6b7c5b94
SP		 1449 struct be_eth_rx_compl *rxcp)
1450{
1451 int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1452 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1453
1454 if (err)
1455 drvr_stats(adapter)->be_rxcp_err++;
1456
5be93b9a 1457 return (tcp_frame && !err) ? true : false;
6b7c5b94
SP		 1458}
1459
1460int be_poll_rx(struct napi_struct *napi, int budget)
1461{
1462 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
1463 struct be_adapter *adapter =
1464 container_of(rx_eq, struct be_adapter, rx_eq);
1465 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1466 struct be_eth_rx_compl *rxcp;
1467 u32 work_done;
1468
b7b83ac3 1469 adapter->stats.drvr_stats.be_rx_polls++;
6b7c5b94
SP		 1470 for (work_done = 0; work_done < budget; work_done++) {
1471 rxcp = be_rx_compl_get(adapter);
1472 if (!rxcp)
1473 break;
1474
5be93b9a
AK		 1475 if (do_gro(adapter, rxcp))
1476 be_rx_compl_process_gro(adapter, rxcp);
6b7c5b94
SP		 1477 else
1478 be_rx_compl_process(adapter, rxcp);
a7a0ef31
SP		 1479
1480 be_rx_compl_reset(rxcp);
6b7c5b94
SP		 1481 }
1482
6b7c5b94
SP		 1483 /* Refill the queue */
1484 if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
1485 be_post_rx_frags(adapter);
1486
1487 /* All consumed */
1488 if (work_done < budget) {
1489 napi_complete(napi);
8788fdc2 1490 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1491 } else {
1492 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1493 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1494 }
1495 return work_done;
1496}
1497
f31e50a8
SP		 1498/* As TX and MCC share the same EQ check for both TX and MCC completions.
1499 * For TX/MCC we don't honour budget; consume everything
1500 */
1501static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1502{
f31e50a8
SP		 1503 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1504 struct be_adapter *adapter =
1505 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1506 struct be_queue_info *txq = &adapter->tx_obj.q;
1507 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1508 struct be_eth_tx_compl *txcp;
f31e50a8 1509 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1510 u16 end_idx;
1511
5fb379ee 1512 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1513 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1514 wrb_index, txcp);
6b7c5b94 1515 be_tx_compl_process(adapter, end_idx);
f31e50a8 1516 tx_compl++;
6b7c5b94
SP		 1517 }
1518
f31e50a8
SP		 1519 mcc_compl = be_process_mcc(adapter, &status);
1520
1521 napi_complete(napi);
1522
1523 if (mcc_compl) {
1524 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1525 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1526 }
1527
1528 if (tx_compl) {
1529 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1530
1531 /* As Tx wrbs have been freed up, wake up netdev queue if
1532 * it was stopped due to lack of tx wrbs.
1533 */
1534 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1535 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1536 netif_wake_queue(adapter->netdev);
1537 }
1538
1539 drvr_stats(adapter)->be_tx_events++;
f31e50a8 1540 drvr_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1541 }
6b7c5b94
SP		 1542
1543 return 1;
1544}
1545
ea1dae11
SP		 1546static void be_worker(struct work_struct *work)
1547{
1548 struct be_adapter *adapter =
1549 container_of(work, struct be_adapter, work.work);
ea1dae11 1550
b31c50a7 1551 be_cmd_get_stats(adapter, &adapter->stats.cmd);
ea1dae11
SP		 1552
1553 /* Set EQ delay */
1554 be_rx_eqd_update(adapter);
1555
4097f663
SP		 1556 be_tx_rate_update(adapter);
1557 be_rx_rate_update(adapter);
1558
ea1dae11
SP		 1559 if (adapter->rx_post_starved) {
1560 adapter->rx_post_starved = false;
1561 be_post_rx_frags(adapter);
1562 }
1563
1564 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1565}
1566
8d56ff11
SP		 1567static void be_msix_disable(struct be_adapter *adapter)
1568{
1569 if (adapter->msix_enabled) {
1570 pci_disable_msix(adapter->pdev);
1571 adapter->msix_enabled = false;
1572 }
1573}
1574
6b7c5b94
SP		 1575static void be_msix_enable(struct be_adapter *adapter)
1576{
1577 int i, status;
1578
1579 for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
1580 adapter->msix_entries[i].entry = i;
1581
1582 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1583 BE_NUM_MSIX_VECTORS);
1584 if (status == 0)
1585 adapter->msix_enabled = true;
1586 return;
1587}
1588
1589static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
1590{
b628bde2
SP		 1591 return adapter->msix_entries[
1592 be_evt_bit_get(adapter, eq_id)].vector;
6b7c5b94
SP		 1593}
1594
b628bde2
SP		 1595static int be_request_irq(struct be_adapter *adapter,
1596 struct be_eq_obj *eq_obj,
1597 void *handler, char *desc)
6b7c5b94
SP		 1598{
1599 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1600 int vec;
1601
1602 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
1603 vec = be_msix_vec_get(adapter, eq_obj->q.id);
1604 return request_irq(vec, handler, 0, eq_obj->desc, adapter);
1605}
1606
1607static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
1608{
1609 int vec = be_msix_vec_get(adapter, eq_obj->q.id);
1610 free_irq(vec, adapter);
1611}
6b7c5b94 1612
b628bde2
SP		 1613static int be_msix_register(struct be_adapter *adapter)
1614{
1615 int status;
1616
1617 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
6b7c5b94
SP		 1618 if (status)
1619 goto err;
1620
b628bde2
SP		 1621 status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
1622 if (status)
1623 goto free_tx_irq;
1624
6b7c5b94 1625 return 0;
b628bde2
SP		 1626
1627free_tx_irq:
1628 be_free_irq(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1629err:
1630 dev_warn(&adapter->pdev->dev,
1631 "MSIX Request IRQ failed - err %d\n", status);
1632 pci_disable_msix(adapter->pdev);
1633 adapter->msix_enabled = false;
1634 return status;
1635}
1636
1637static int be_irq_register(struct be_adapter *adapter)
1638{
1639 struct net_device *netdev = adapter->netdev;
1640 int status;
1641
1642 if (adapter->msix_enabled) {
1643 status = be_msix_register(adapter);
1644 if (status == 0)
1645 goto done;
1646 }
1647
1648 /* INTx */
1649 netdev->irq = adapter->pdev->irq;
1650 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
1651 adapter);
1652 if (status) {
1653 dev_err(&adapter->pdev->dev,
1654 "INTx request IRQ failed - err %d\n", status);
1655 return status;
1656 }
1657done:
1658 adapter->isr_registered = true;
1659 return 0;
1660}
1661
1662static void be_irq_unregister(struct be_adapter *adapter)
1663{
1664 struct net_device *netdev = adapter->netdev;
6b7c5b94
SP		 1665
1666 if (!adapter->isr_registered)
1667 return;
1668
1669 /* INTx */
1670 if (!adapter->msix_enabled) {
1671 free_irq(netdev->irq, adapter);
1672 goto done;
1673 }
1674
1675 /* MSIx */
b628bde2
SP		 1676 be_free_irq(adapter, &adapter->tx_eq);
1677 be_free_irq(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1678done:
1679 adapter->isr_registered = false;
1680 return;
1681}
1682
1683static int be_open(struct net_device *netdev)
1684{
1685 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1686 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1687 struct be_eq_obj *tx_eq = &adapter->tx_eq;
a8f447bd
SP		 1688 bool link_up;
1689 int status;
0388f251
SB		 1690 u8 mac_speed;
1691 u16 link_speed;
5fb379ee
SP		 1692
1693 /* First time posting */
1694 be_post_rx_frags(adapter);
1695
1696 napi_enable(&rx_eq->napi);
1697 napi_enable(&tx_eq->napi);
1698
1699 be_irq_register(adapter);
1700
8788fdc2 1701 be_intr_set(adapter, true);
5fb379ee
SP		 1702
1703 /* The evt queues are created in unarmed state; arm them */
8788fdc2
SP		 1704 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
1705 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee
SP		 1706
1707 /* Rx compl queue may be in unarmed state; rearm it */
8788fdc2 1708 be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
5fb379ee 1709
7a1e9b20
SP		 1710 /* Now that interrupts are on we can process async mcc */
1711 be_async_mcc_enable(adapter);
1712
0388f251
SB		 1713 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
1714 &link_speed);
a8f447bd 1715 if (status)
4f2aa89c 1716 goto ret_sts;
a8f447bd 1717 be_link_status_update(adapter, link_up);
5fb379ee 1718
4f2aa89c
AK		 1719 status = be_vid_config(adapter);
1720 if (status)
1721 goto ret_sts;
1722
1723 status = be_cmd_set_flow_control(adapter,
1724 adapter->tx_fc, adapter->rx_fc);
1725 if (status)
1726 goto ret_sts;
1727
5fb379ee 1728 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
4f2aa89c
AK		 1729ret_sts:
1730 return status;
5fb379ee
SP		 1731}
1732
71d8d1b5
AK		 1733static int be_setup_wol(struct be_adapter *adapter, bool enable)
1734{
1735 struct be_dma_mem cmd;
1736 int status = 0;
1737 u8 mac[ETH_ALEN];
1738
1739 memset(mac, 0, ETH_ALEN);
1740
1741 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
1742 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
1743 if (cmd.va == NULL)
1744 return -1;
1745 memset(cmd.va, 0, cmd.size);
1746
1747 if (enable) {
1748 status = pci_write_config_dword(adapter->pdev,
1749 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
1750 if (status) {
1751 dev_err(&adapter->pdev->dev,
1752 "Could not enable Wake-on-lan \n");
1753 pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
1754 cmd.dma);
1755 return status;
1756 }
1757 status = be_cmd_enable_magic_wol(adapter,
1758 adapter->netdev->dev_addr, &cmd);
1759 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
1760 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
1761 } else {
1762 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
1763 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
1764 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
1765 }
1766
1767 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
1768 return status;
1769}
1770
5fb379ee
SP		 1771static int be_setup(struct be_adapter *adapter)
1772{
5fb379ee 1773 struct net_device *netdev = adapter->netdev;
73d540f2 1774 u32 cap_flags, en_flags;
6b7c5b94
SP		 1775 int status;
1776
73d540f2
SP		 1777 cap_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
1778 BE_IF_FLAGS_MCAST_PROMISCUOUS |
1779 BE_IF_FLAGS_PROMISCUOUS |
1780 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1781 en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST |
1782 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1783
1784 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1785 netdev->dev_addr, false/* pmac_invalid */,
1786 &adapter->if_handle, &adapter->pmac_id);
6b7c5b94
SP		 1787 if (status != 0)
1788 goto do_none;
1789
6b7c5b94
SP		 1790 status = be_tx_queues_create(adapter);
1791 if (status != 0)
1792 goto if_destroy;
1793
1794 status = be_rx_queues_create(adapter);
1795 if (status != 0)
1796 goto tx_qs_destroy;
1797
5fb379ee
SP		 1798 status = be_mcc_queues_create(adapter);
1799 if (status != 0)
1800 goto rx_qs_destroy;
6b7c5b94 1801
0dffc83e
AK		 1802 adapter->link_speed = -1;
1803
6b7c5b94
SP		 1804 return 0;
1805
5fb379ee
SP		 1806rx_qs_destroy:
1807 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 1808tx_qs_destroy:
1809 be_tx_queues_destroy(adapter);
1810if_destroy:
8788fdc2 1811 be_cmd_if_destroy(adapter, adapter->if_handle);
6b7c5b94
SP		 1812do_none:
1813 return status;
1814}
1815
5fb379ee
SP		 1816static int be_clear(struct be_adapter *adapter)
1817{
1a8887d8 1818 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 1819 be_rx_queues_destroy(adapter);
1820 be_tx_queues_destroy(adapter);
1821
8788fdc2 1822 be_cmd_if_destroy(adapter, adapter->if_handle);
5fb379ee 1823
2243e2e9
SP		 1824 /* tell fw we're done with firing cmds */
1825 be_cmd_fw_clean(adapter);
5fb379ee
SP		 1826 return 0;
1827}
1828
6b7c5b94
SP		 1829static int be_close(struct net_device *netdev)
1830{
1831 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1832 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1833 struct be_eq_obj *tx_eq = &adapter->tx_eq;
1834 int vec;
1835
b305be78 1836 cancel_delayed_work_sync(&adapter->work);
6b7c5b94 1837
7a1e9b20
SP		 1838 be_async_mcc_disable(adapter);
1839
6b7c5b94
SP		 1840 netif_stop_queue(netdev);
1841 netif_carrier_off(netdev);
a8f447bd 1842 adapter->link_up = false;
6b7c5b94 1843
8788fdc2 1844 be_intr_set(adapter, false);
6b7c5b94
SP		 1845
1846 if (adapter->msix_enabled) {
1847 vec = be_msix_vec_get(adapter, tx_eq->q.id);
1848 synchronize_irq(vec);
1849 vec = be_msix_vec_get(adapter, rx_eq->q.id);
1850 synchronize_irq(vec);
1851 } else {
1852 synchronize_irq(netdev->irq);
1853 }
1854 be_irq_unregister(adapter);
1855
1856 napi_disable(&rx_eq->napi);
1857 napi_disable(&tx_eq->napi);
1858
a8e9179a
SP		 1859 /* Wait for all pending tx completions to arrive so that
1860 * all tx skbs are freed.
1861 */
1862 be_tx_compl_clean(adapter);
1863
6b7c5b94
SP		 1864 return 0;
1865}
1866
84517482
AK		 1867#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
1868char flash_cookie[2][16] = {"*** SE FLAS",
1869 "H DIRECTORY *** "};
fa9a6fed
SB		 1870
1871static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 1872 const u8 *p, u32 img_start, int image_size,
1873 int hdr_size)
fa9a6fed
SB		 1874{
1875 u32 crc_offset;
1876 u8 flashed_crc[4];
1877 int status;
3f0d4560
AK		 1878
1879 crc_offset = hdr_size + img_start + image_size - 4;
1880
fa9a6fed 1881 p += crc_offset;
3f0d4560
AK		 1882
1883 status = be_cmd_get_flash_crc(adapter, flashed_crc,
1884 (img_start + image_size - 4));
fa9a6fed
SB		 1885 if (status) {
1886 dev_err(&adapter->pdev->dev,
1887 "could not get crc from flash, not flashing redboot\n");
1888 return false;
1889 }
1890
1891 /*update redboot only if crc does not match*/
1892 if (!memcmp(flashed_crc, p, 4))
1893 return false;
1894 else
1895 return true;
fa9a6fed
SB		 1896}
1897
3f0d4560 1898static int be_flash_data(struct be_adapter *adapter,
84517482 1899 const struct firmware *fw,
3f0d4560
AK		 1900 struct be_dma_mem *flash_cmd, int num_of_images)
1901
84517482 1902{
3f0d4560
AK		 1903 int status = 0, i, filehdr_size = 0;
1904 u32 total_bytes = 0, flash_op;
84517482
AK		 1905 int num_bytes;
1906 const u8 *p = fw->data;
1907 struct be_cmd_write_flashrom *req = flash_cmd->va;
3f0d4560 1908 struct flash_comp *pflashcomp;
9fe96934 1909 int num_comp;
3f0d4560 1910
9fe96934 1911 struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 1912 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
1913 FLASH_IMAGE_MAX_SIZE_g3},
1914 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
1915 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
1916 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
1917 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
1918 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
1919 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
1920 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
1921 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
1922 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
1923 FLASH_IMAGE_MAX_SIZE_g3},
1924 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
1925 FLASH_IMAGE_MAX_SIZE_g3},
1926 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 1927 FLASH_IMAGE_MAX_SIZE_g3},
1928 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
1929 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560
AK		 1930 };
1931 struct flash_comp gen2_flash_types[8] = {
1932 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
1933 FLASH_IMAGE_MAX_SIZE_g2},
1934 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
1935 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
1936 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
1937 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
1938 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
1939 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
1940 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
1941 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
1942 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
1943 FLASH_IMAGE_MAX_SIZE_g2},
1944 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
1945 FLASH_IMAGE_MAX_SIZE_g2},
1946 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
1947 FLASH_IMAGE_MAX_SIZE_g2}
1948 };
1949
1950 if (adapter->generation == BE_GEN3) {
1951 pflashcomp = gen3_flash_types;
1952 filehdr_size = sizeof(struct flash_file_hdr_g3);
9fe96934 1953 num_comp = 9;
3f0d4560
AK		 1954 } else {
1955 pflashcomp = gen2_flash_types;
1956 filehdr_size = sizeof(struct flash_file_hdr_g2);
9fe96934 1957 num_comp = 8;
84517482 1958 }
9fe96934
SB		 1959 for (i = 0; i < num_comp; i++) {
1960 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
1961 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
1962 continue;
3f0d4560
AK		 1963 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
1964 (!be_flash_redboot(adapter, fw->data,
1965 pflashcomp[i].offset, pflashcomp[i].size,
1966 filehdr_size)))
1967 continue;
1968 p = fw->data;
1969 p += filehdr_size + pflashcomp[i].offset
1970 + (num_of_images * sizeof(struct image_hdr));
1971 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 1972 return -1;
3f0d4560
AK		 1973 total_bytes = pflashcomp[i].size;
1974 while (total_bytes) {
1975 if (total_bytes > 32*1024)
1976 num_bytes = 32*1024;
1977 else
1978 num_bytes = total_bytes;
1979 total_bytes -= num_bytes;
1980
1981 if (!total_bytes)
1982 flash_op = FLASHROM_OPER_FLASH;
1983 else
1984 flash_op = FLASHROM_OPER_SAVE;
1985 memcpy(req->params.data_buf, p, num_bytes);
1986 p += num_bytes;
1987 status = be_cmd_write_flashrom(adapter, flash_cmd,
1988 pflashcomp[i].optype, flash_op, num_bytes);
1989 if (status) {
1990 dev_err(&adapter->pdev->dev,
1991 "cmd to write to flash rom failed.\n");
1992 return -1;
1993 }
1994 yield();
84517482 1995 }
84517482 1996 }
84517482
AK		 1997 return 0;
1998}
1999
3f0d4560
AK		 2000static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2001{
2002 if (fhdr == NULL)
2003 return 0;
2004 if (fhdr->build[0] == '3')
2005 return BE_GEN3;
2006 else if (fhdr->build[0] == '2')
2007 return BE_GEN2;
2008 else
2009 return 0;
2010}
2011
84517482
AK		 2012int be_load_fw(struct be_adapter *adapter, u8 *func)
2013{
2014 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2015 const struct firmware *fw;
3f0d4560
AK		 2016 struct flash_file_hdr_g2 *fhdr;
2017 struct flash_file_hdr_g3 *fhdr3;
2018 struct image_hdr *img_hdr_ptr = NULL;
84517482 2019 struct be_dma_mem flash_cmd;
3f0d4560 2020 int status, i = 0;
84517482 2021 const u8 *p;
84517482 2022
84517482
AK		 2023 strcpy(fw_file, func);
2024
2025 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2026 if (status)
2027 goto fw_exit;
2028
2029 p = fw->data;
3f0d4560 2030 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2031 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2032
84517482
AK		 2033 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2034 flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
2035 &flash_cmd.dma);
2036 if (!flash_cmd.va) {
2037 status = -ENOMEM;
2038 dev_err(&adapter->pdev->dev,
2039 "Memory allocation failure while flashing\n");
2040 goto fw_exit;
2041 }
2042
3f0d4560
AK		 2043 if ((adapter->generation == BE_GEN3) &&
2044 (get_ufigen_type(fhdr) == BE_GEN3)) {
2045 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
2046 for (i = 0; i < fhdr3->num_imgs; i++) {
2047 img_hdr_ptr = (struct image_hdr *) (fw->data +
2048 (sizeof(struct flash_file_hdr_g3) +
2049 i * sizeof(struct image_hdr)));
2050 if (img_hdr_ptr->imageid == 1) {
2051 status = be_flash_data(adapter, fw,
2052 &flash_cmd, fhdr3->num_imgs);
2053 }
2054
2055 }
2056 } else if ((adapter->generation == BE_GEN2) &&
2057 (get_ufigen_type(fhdr) == BE_GEN2)) {
2058 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2059 } else {
2060 dev_err(&adapter->pdev->dev,
2061 "UFI and Interface are not compatible for flashing\n");
2062 status = -1;
84517482
AK		 2063 }
2064
2065 pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
2066 flash_cmd.dma);
2067 if (status) {
2068 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2069 goto fw_exit;
2070 }
2071
af901ca1 2072 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2073
2074fw_exit:
2075 release_firmware(fw);
2076 return status;
2077}
2078
6b7c5b94
SP		 2079static struct net_device_ops be_netdev_ops = {
2080 .ndo_open = be_open,
2081 .ndo_stop = be_close,
2082 .ndo_start_xmit = be_xmit,
2083 .ndo_get_stats = be_get_stats,
2084 .ndo_set_rx_mode = be_set_multicast_list,
2085 .ndo_set_mac_address = be_mac_addr_set,
2086 .ndo_change_mtu = be_change_mtu,
2087 .ndo_validate_addr = eth_validate_addr,
2088 .ndo_vlan_rx_register = be_vlan_register,
2089 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2090 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
2091};
2092
2093static void be_netdev_init(struct net_device *netdev)
2094{
2095 struct be_adapter *adapter = netdev_priv(netdev);
2096
2097 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
583e3f34
AK		 2098 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
2099 NETIF_F_GRO;
6b7c5b94 2100
51c59870
AK		 2101 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
2102
6b7c5b94
SP		 2103 netdev->flags |= IFF_MULTICAST;
2104
728a9972
AK		 2105 adapter->rx_csum = true;
2106
9e90c961
AK		 2107 /* Default settings for Rx and Tx flow control */
2108 adapter->rx_fc = true;
2109 adapter->tx_fc = true;
2110
c190e3c8
AK		 2111 netif_set_gso_max_size(netdev, 65535);
2112
6b7c5b94
SP		 2113 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2114
2115 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2116
6b7c5b94
SP		 2117 netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
2118 BE_NAPI_WEIGHT);
5fb379ee 2119 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94
SP		 2120 BE_NAPI_WEIGHT);
2121
2122 netif_carrier_off(netdev);
2123 netif_stop_queue(netdev);
2124}
2125
2126static void be_unmap_pci_bars(struct be_adapter *adapter)
2127{
8788fdc2
SP		 2128 if (adapter->csr)
2129 iounmap(adapter->csr);
2130 if (adapter->db)
2131 iounmap(adapter->db);
2132 if (adapter->pcicfg)
2133 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2134}
2135
2136static int be_map_pci_bars(struct be_adapter *adapter)
2137{
2138 u8 __iomem *addr;
7b139c83 2139 int pcicfg_reg;
6b7c5b94
SP		 2140
2141 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2142 pci_resource_len(adapter->pdev, 2));
2143 if (addr == NULL)
2144 return -ENOMEM;
8788fdc2 2145 adapter->csr = addr;
6b7c5b94
SP		 2146
2147 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 4),
2148 128 * 1024);
2149 if (addr == NULL)
2150 goto pci_map_err;
8788fdc2 2151 adapter->db = addr;
6b7c5b94 2152
7b139c83
AK		 2153 if (adapter->generation == BE_GEN2)
2154 pcicfg_reg = 1;
2155 else
2156 pcicfg_reg = 0;
2157
2158 addr = ioremap_nocache(pci_resource_start(adapter->pdev, pcicfg_reg),
2159 pci_resource_len(adapter->pdev, pcicfg_reg));
6b7c5b94
SP		 2160 if (addr == NULL)
2161 goto pci_map_err;
8788fdc2 2162 adapter->pcicfg = addr;
6b7c5b94
SP		 2163
2164 return 0;
2165pci_map_err:
2166 be_unmap_pci_bars(adapter);
2167 return -ENOMEM;
2168}
2169
2170
2171static void be_ctrl_cleanup(struct be_adapter *adapter)
2172{
8788fdc2 2173 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2174
2175 be_unmap_pci_bars(adapter);
2176
2177 if (mem->va)
2178 pci_free_consistent(adapter->pdev, mem->size,
2179 mem->va, mem->dma);
e7b909a6
SP		 2180
2181 mem = &adapter->mc_cmd_mem;
2182 if (mem->va)
2183 pci_free_consistent(adapter->pdev, mem->size,
2184 mem->va, mem->dma);
6b7c5b94
SP		 2185}
2186
6b7c5b94
SP		 2187static int be_ctrl_init(struct be_adapter *adapter)
2188{
8788fdc2
SP		 2189 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2190 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2191 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2192 int status;
6b7c5b94
SP		 2193
2194 status = be_map_pci_bars(adapter);
2195 if (status)
e7b909a6 2196 goto done;
6b7c5b94
SP		 2197
2198 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2199 mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
2200 mbox_mem_alloc->size, &mbox_mem_alloc->dma);
2201 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2202 status = -ENOMEM;
2203 goto unmap_pci_bars;
6b7c5b94 2204 }
e7b909a6 2205
6b7c5b94
SP		 2206 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2207 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2208 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2209 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2210
2211 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2212 mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
2213 &mc_cmd_mem->dma);
2214 if (mc_cmd_mem->va == NULL) {
2215 status = -ENOMEM;
2216 goto free_mbox;
2217 }
2218 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2219
8788fdc2
SP		 2220 spin_lock_init(&adapter->mbox_lock);
2221 spin_lock_init(&adapter->mcc_lock);
2222 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2223
cf588477 2224 pci_save_state(adapter->pdev);
6b7c5b94 2225 return 0;
e7b909a6
SP		 2226
2227free_mbox:
2228 pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
2229 mbox_mem_alloc->va, mbox_mem_alloc->dma);
2230
2231unmap_pci_bars:
2232 be_unmap_pci_bars(adapter);
2233
2234done:
2235 return status;
6b7c5b94
SP		 2236}
2237
2238static void be_stats_cleanup(struct be_adapter *adapter)
2239{
2240 struct be_stats_obj *stats = &adapter->stats;
2241 struct be_dma_mem *cmd = &stats->cmd;
2242
2243 if (cmd->va)
2244 pci_free_consistent(adapter->pdev, cmd->size,
2245 cmd->va, cmd->dma);
2246}
2247
2248static int be_stats_init(struct be_adapter *adapter)
2249{
2250 struct be_stats_obj *stats = &adapter->stats;
2251 struct be_dma_mem *cmd = &stats->cmd;
2252
2253 cmd->size = sizeof(struct be_cmd_req_get_stats);
2254 cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
2255 if (cmd->va == NULL)
2256 return -1;
d291b9af 2257 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2258 return 0;
2259}
2260
2261static void __devexit be_remove(struct pci_dev *pdev)
2262{
2263 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2264
6b7c5b94
SP		 2265 if (!adapter)
2266 return;
2267
2268 unregister_netdev(adapter->netdev);
2269
5fb379ee
SP		 2270 be_clear(adapter);
2271
6b7c5b94
SP		 2272 be_stats_cleanup(adapter);
2273
2274 be_ctrl_cleanup(adapter);
2275
8d56ff11 2276 be_msix_disable(adapter);
6b7c5b94
SP		 2277
2278 pci_set_drvdata(pdev, NULL);
2279 pci_release_regions(pdev);
2280 pci_disable_device(pdev);
2281
2282 free_netdev(adapter->netdev);
2283}
2284
2243e2e9 2285static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2286{
6b7c5b94 2287 int status;
2243e2e9 2288 u8 mac[ETH_ALEN];
6b7c5b94 2289
2243e2e9 2290 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2291 if (status)
2292 return status;
2293
2243e2e9
SP		 2294 status = be_cmd_query_fw_cfg(adapter,
2295 &adapter->port_num, &adapter->cap);
43a04fdc
SP		 2296 if (status)
2297 return status;
2298
2243e2e9
SP		 2299 memset(mac, 0, ETH_ALEN);
2300 status = be_cmd_mac_addr_query(adapter, mac,
2301 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
6b7c5b94
SP		 2302 if (status)
2303 return status;
ca9e4988
AK		 2304
2305 if (!is_valid_ether_addr(mac))
2306 return -EADDRNOTAVAIL;
2307
2243e2e9 2308 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
35a65285 2309 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
6b7c5b94 2310
82903e4b
AK		 2311 if (adapter->cap & 0x400)
2312 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2313 else
2314 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2315
2243e2e9 2316 return 0;
6b7c5b94
SP		 2317}
2318
2319static int __devinit be_probe(struct pci_dev *pdev,
2320 const struct pci_device_id *pdev_id)
2321{
2322 int status = 0;
2323 struct be_adapter *adapter;
2324 struct net_device *netdev;
6b7c5b94
SP		 2325
2326 status = pci_enable_device(pdev);
2327 if (status)
2328 goto do_none;
2329
2330 status = pci_request_regions(pdev, DRV_NAME);
2331 if (status)
2332 goto disable_dev;
2333 pci_set_master(pdev);
2334
2335 netdev = alloc_etherdev(sizeof(struct be_adapter));
2336 if (netdev == NULL) {
2337 status = -ENOMEM;
2338 goto rel_reg;
2339 }
2340 adapter = netdev_priv(netdev);
7b139c83
AK		 2341
2342 switch (pdev->device) {
2343 case BE_DEVICE_ID1:
2344 case OC_DEVICE_ID1:
2345 adapter->generation = BE_GEN2;
2346 break;
2347 case BE_DEVICE_ID2:
2348 case OC_DEVICE_ID2:
2349 adapter->generation = BE_GEN3;
2350 break;
2351 default:
2352 adapter->generation = 0;
2353 }
2354
6b7c5b94
SP		 2355 adapter->pdev = pdev;
2356 pci_set_drvdata(pdev, adapter);
2357 adapter->netdev = netdev;
2243e2e9
SP		 2358 be_netdev_init(netdev);
2359 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94
SP		 2360
2361 be_msix_enable(adapter);
2362
e930438c 2363 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2364 if (!status) {
2365 netdev->features |= NETIF_F_HIGHDMA;
2366 } else {
e930438c 2367 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2368 if (status) {
2369 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2370 goto free_netdev;
2371 }
2372 }
2373
6b7c5b94
SP		 2374 status = be_ctrl_init(adapter);
2375 if (status)
2376 goto free_netdev;
2377
2243e2e9
SP		 2378 /* sync up with fw's ready state */
2379 status = be_cmd_POST(adapter);
6b7c5b94
SP		 2380 if (status)
2381 goto ctrl_clean;
2382
2243e2e9
SP		 2383 /* tell fw we're ready to fire cmds */
2384 status = be_cmd_fw_init(adapter);
6b7c5b94 2385 if (status)
2243e2e9
SP		 2386 goto ctrl_clean;
2387
2388 status = be_cmd_reset_function(adapter);
2389 if (status)
2390 goto ctrl_clean;
6b7c5b94 2391
2243e2e9
SP		 2392 status = be_stats_init(adapter);
2393 if (status)
2394 goto ctrl_clean;
2395
2396 status = be_get_config(adapter);
6b7c5b94
SP		 2397 if (status)
2398 goto stats_clean;
6b7c5b94
SP		 2399
2400 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 2401
5fb379ee
SP		 2402 status = be_setup(adapter);
2403 if (status)
2404 goto stats_clean;
2243e2e9 2405
6b7c5b94
SP		 2406 status = register_netdev(netdev);
2407 if (status != 0)
5fb379ee 2408 goto unsetup;
6b7c5b94 2409
c4ca2374 2410 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
6b7c5b94
SP		 2411 return 0;
2412
5fb379ee
SP		 2413unsetup:
2414 be_clear(adapter);
6b7c5b94
SP		 2415stats_clean:
2416 be_stats_cleanup(adapter);
2417ctrl_clean:
2418 be_ctrl_cleanup(adapter);
2419free_netdev:
8d56ff11 2420 be_msix_disable(adapter);
6b7c5b94 2421 free_netdev(adapter->netdev);
8d56ff11 2422 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 2423rel_reg:
2424 pci_release_regions(pdev);
2425disable_dev:
2426 pci_disable_device(pdev);
2427do_none:
c4ca2374 2428 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 2429 return status;
2430}
2431
2432static int be_suspend(struct pci_dev *pdev, pm_message_t state)
2433{
2434 struct be_adapter *adapter = pci_get_drvdata(pdev);
2435 struct net_device *netdev = adapter->netdev;
2436
71d8d1b5
AK		 2437 if (adapter->wol)
2438 be_setup_wol(adapter, true);
2439
6b7c5b94
SP		 2440 netif_device_detach(netdev);
2441 if (netif_running(netdev)) {
2442 rtnl_lock();
2443 be_close(netdev);
2444 rtnl_unlock();
2445 }
9e90c961 2446 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 2447 be_clear(adapter);
6b7c5b94
SP		 2448
2449 pci_save_state(pdev);
2450 pci_disable_device(pdev);
2451 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2452 return 0;
2453}
2454
2455static int be_resume(struct pci_dev *pdev)
2456{
2457 int status = 0;
2458 struct be_adapter *adapter = pci_get_drvdata(pdev);
2459 struct net_device *netdev = adapter->netdev;
2460
2461 netif_device_detach(netdev);
2462
2463 status = pci_enable_device(pdev);
2464 if (status)
2465 return status;
2466
2467 pci_set_power_state(pdev, 0);
2468 pci_restore_state(pdev);
2469
2243e2e9
SP		 2470 /* tell fw we're ready to fire cmds */
2471 status = be_cmd_fw_init(adapter);
2472 if (status)
2473 return status;
2474
9b0365f1 2475 be_setup(adapter);
6b7c5b94
SP		 2476 if (netif_running(netdev)) {
2477 rtnl_lock();
2478 be_open(netdev);
2479 rtnl_unlock();
2480 }
2481 netif_device_attach(netdev);
71d8d1b5
AK		 2482
2483 if (adapter->wol)
2484 be_setup_wol(adapter, false);
6b7c5b94
SP		 2485 return 0;
2486}
2487
82456b03
SP		 2488/*
2489 * An FLR will stop BE from DMAing any data.
2490 */
2491static void be_shutdown(struct pci_dev *pdev)
2492{
2493 struct be_adapter *adapter = pci_get_drvdata(pdev);
2494 struct net_device *netdev = adapter->netdev;
2495
2496 netif_device_detach(netdev);
2497
2498 be_cmd_reset_function(adapter);
2499
2500 if (adapter->wol)
2501 be_setup_wol(adapter, true);
2502
2503 pci_disable_device(pdev);
2504
2505 return;
2506}
2507
cf588477
SP		 2508static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
2509 pci_channel_state_t state)
2510{
2511 struct be_adapter *adapter = pci_get_drvdata(pdev);
2512 struct net_device *netdev = adapter->netdev;
2513
2514 dev_err(&adapter->pdev->dev, "EEH error detected\n");
2515
2516 adapter->eeh_err = true;
2517
2518 netif_device_detach(netdev);
2519
2520 if (netif_running(netdev)) {
2521 rtnl_lock();
2522 be_close(netdev);
2523 rtnl_unlock();
2524 }
2525 be_clear(adapter);
2526
2527 if (state == pci_channel_io_perm_failure)
2528 return PCI_ERS_RESULT_DISCONNECT;
2529
2530 pci_disable_device(pdev);
2531
2532 return PCI_ERS_RESULT_NEED_RESET;
2533}
2534
2535static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
2536{
2537 struct be_adapter *adapter = pci_get_drvdata(pdev);
2538 int status;
2539
2540 dev_info(&adapter->pdev->dev, "EEH reset\n");
2541 adapter->eeh_err = false;
2542
2543 status = pci_enable_device(pdev);
2544 if (status)
2545 return PCI_ERS_RESULT_DISCONNECT;
2546
2547 pci_set_master(pdev);
2548 pci_set_power_state(pdev, 0);
2549 pci_restore_state(pdev);
2550
2551 /* Check if card is ok and fw is ready */
2552 status = be_cmd_POST(adapter);
2553 if (status)
2554 return PCI_ERS_RESULT_DISCONNECT;
2555
2556 return PCI_ERS_RESULT_RECOVERED;
2557}
2558
2559static void be_eeh_resume(struct pci_dev *pdev)
2560{
2561 int status = 0;
2562 struct be_adapter *adapter = pci_get_drvdata(pdev);
2563 struct net_device *netdev = adapter->netdev;
2564
2565 dev_info(&adapter->pdev->dev, "EEH resume\n");
2566
2567 pci_save_state(pdev);
2568
2569 /* tell fw we're ready to fire cmds */
2570 status = be_cmd_fw_init(adapter);
2571 if (status)
2572 goto err;
2573
2574 status = be_setup(adapter);
2575 if (status)
2576 goto err;
2577
2578 if (netif_running(netdev)) {
2579 status = be_open(netdev);
2580 if (status)
2581 goto err;
2582 }
2583 netif_device_attach(netdev);
2584 return;
2585err:
2586 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
2587 return;
2588}
2589
2590static struct pci_error_handlers be_eeh_handlers = {
2591 .error_detected = be_eeh_err_detected,
2592 .slot_reset = be_eeh_reset,
2593 .resume = be_eeh_resume,
2594};
2595
6b7c5b94
SP		 2596static struct pci_driver be_driver = {
2597 .name = DRV_NAME,
2598 .id_table = be_dev_ids,
2599 .probe = be_probe,
2600 .remove = be_remove,
2601 .suspend = be_suspend,
cf588477 2602 .resume = be_resume,
82456b03 2603 .shutdown = be_shutdown,
cf588477 2604 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 2605};
2606
2607static int __init be_init_module(void)
2608{
8e95a202
JP		 2609 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
2610 rx_frag_size != 2048) {
6b7c5b94
SP		 2611 printk(KERN_WARNING DRV_NAME
2612 " : Module param rx_frag_size must be 2048/4096/8192."
2613 " Using 2048\n");
2614 rx_frag_size = 2048;
2615 }
6b7c5b94
SP		 2616
2617 return pci_register_driver(&be_driver);
2618}
2619module_init(be_init_module);
2620
2621static void __exit be_exit_module(void)
2622{
2623 pci_unregister_driver(&be_driver);
2624}
2625module_exit(be_exit_module);
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