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be2net: Patch to determine if function is VF while running in guest OS.
[net-next-2.6.git] / drivers / net / benet / be_main.c
CommitLineData
6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
28static unsigned int rx_frag_size = 2048;
ba343c77 29static unsigned int num_vfs;
6b7c5b94 30module_param(rx_frag_size, uint, S_IRUGO);
ba343c77 31module_param(num_vfs, uint, S_IRUGO);
6b7c5b94 32MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
ba343c77 33MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 34
6b7c5b94 35static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 36 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 37 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 38 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
39 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
6b7c5b94
SP		 40 { 0 }
41};
42MODULE_DEVICE_TABLE(pci, be_dev_ids);
43
44static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
45{
46 struct be_dma_mem *mem = &q->dma_mem;
47 if (mem->va)
48 pci_free_consistent(adapter->pdev, mem->size,
49 mem->va, mem->dma);
50}
51
52static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
53 u16 len, u16 entry_size)
54{
55 struct be_dma_mem *mem = &q->dma_mem;
56
57 memset(q, 0, sizeof(*q));
58 q->len = len;
59 q->entry_size = entry_size;
60 mem->size = len * entry_size;
61 mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
62 if (!mem->va)
63 return -1;
64 memset(mem->va, 0, mem->size);
65 return 0;
66}
67
8788fdc2 68static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 69{
8788fdc2 70 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 71 u32 reg = ioread32(addr);
72 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 73
cf588477
SP		 74 if (adapter->eeh_err)
75 return;
76
5f0b849e 77 if (!enabled && enable)
6b7c5b94 78 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 79 else if (enabled && !enable)
6b7c5b94 80 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 81 else
6b7c5b94 82 return;
5f0b849e 83
6b7c5b94
SP		 84 iowrite32(reg, addr);
85}
86
8788fdc2 87static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 88{
89 u32 val = 0;
90 val |= qid & DB_RQ_RING_ID_MASK;
91 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 92
93 wmb();
8788fdc2 94 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 95}
96
8788fdc2 97static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 98{
99 u32 val = 0;
100 val |= qid & DB_TXULP_RING_ID_MASK;
101 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
f3eb62d2
SP		 102
103 wmb();
8788fdc2 104 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 105}
106
8788fdc2 107static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 108 bool arm, bool clear_int, u16 num_popped)
109{
110 u32 val = 0;
111 val |= qid & DB_EQ_RING_ID_MASK;
cf588477
SP		 112
113 if (adapter->eeh_err)
114 return;
115
6b7c5b94
SP		 116 if (arm)
117 val |= 1 << DB_EQ_REARM_SHIFT;
118 if (clear_int)
119 val |= 1 << DB_EQ_CLR_SHIFT;
120 val |= 1 << DB_EQ_EVNT_SHIFT;
121 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 122 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 123}
124
8788fdc2 125void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 126{
127 u32 val = 0;
128 val |= qid & DB_CQ_RING_ID_MASK;
cf588477
SP		 129
130 if (adapter->eeh_err)
131 return;
132
6b7c5b94
SP		 133 if (arm)
134 val |= 1 << DB_CQ_REARM_SHIFT;
135 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 136 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 137}
138
6b7c5b94
SP		 139static int be_mac_addr_set(struct net_device *netdev, void *p)
140{
141 struct be_adapter *adapter = netdev_priv(netdev);
142 struct sockaddr *addr = p;
143 int status = 0;
144
ca9e4988
AK		 145 if (!is_valid_ether_addr(addr->sa_data))
146 return -EADDRNOTAVAIL;
147
ba343c77
SB		 148 /* MAC addr configuration will be done in hardware for VFs
149 * by their corresponding PFs. Just copy to netdev addr here
150 */
151 if (!be_physfn(adapter))
152 goto netdev_addr;
153
a65027e4
SP		 154 status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
155 if (status)
156 return status;
6b7c5b94 157
a65027e4
SP		 158 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
159 adapter->if_handle, &adapter->pmac_id);
ba343c77 160netdev_addr:
6b7c5b94
SP		 161 if (!status)
162 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
163
164 return status;
165}
166
b31c50a7 167void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94
SP		 168{
169 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
170 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
171 struct be_port_rxf_stats *port_stats =
172 &rxf_stats->port[adapter->port_num];
78122a52 173 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 174 struct be_erx_stats *erx_stats = &hw_stats->erx;
6b7c5b94 175
91992e44
AK		 176 dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
177 dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
178 dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
179 dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 180
181 /* bad pkts received */
182 dev_stats->rx_errors = port_stats->rx_crc_errors +
183 port_stats->rx_alignment_symbol_errors +
184 port_stats->rx_in_range_errors +
68110868
SP		 185 port_stats->rx_out_range_errors +
186 port_stats->rx_frame_too_long +
187 port_stats->rx_dropped_too_small +
188 port_stats->rx_dropped_too_short +
189 port_stats->rx_dropped_header_too_small +
190 port_stats->rx_dropped_tcp_length +
191 port_stats->rx_dropped_runt +
192 port_stats->rx_tcp_checksum_errs +
193 port_stats->rx_ip_checksum_errs +
194 port_stats->rx_udp_checksum_errs;
195
196 /* no space in linux buffers: best possible approximation */
01ed30da
SP		 197 dev_stats->rx_dropped =
198 erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
6b7c5b94
SP		 199
200 /* detailed rx errors */
201 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 202 port_stats->rx_out_range_errors +
203 port_stats->rx_frame_too_long;
204
6b7c5b94
SP		 205 /* receive ring buffer overflow */
206 dev_stats->rx_over_errors = 0;
68110868 207
6b7c5b94
SP		 208 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
209
210 /* frame alignment errors */
211 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 212
6b7c5b94
SP		 213 /* receiver fifo overrun */
214 /* drops_no_pbuf is no per i/f, it's per BE card */
215 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
216 port_stats->rx_input_fifo_overflow +
217 rxf_stats->rx_drops_no_pbuf;
218 /* receiver missed packetd */
219 dev_stats->rx_missed_errors = 0;
68110868
SP		 220
221 /* packet transmit problems */
222 dev_stats->tx_errors = 0;
223
224 /* no space available in linux */
225 dev_stats->tx_dropped = 0;
226
c5b9b92e 227 dev_stats->multicast = port_stats->rx_multicast_frames;
68110868
SP		 228 dev_stats->collisions = 0;
229
6b7c5b94
SP		 230 /* detailed tx_errors */
231 dev_stats->tx_aborted_errors = 0;
232 dev_stats->tx_carrier_errors = 0;
233 dev_stats->tx_fifo_errors = 0;
234 dev_stats->tx_heartbeat_errors = 0;
235 dev_stats->tx_window_errors = 0;
236}
237
8788fdc2 238void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 239{
6b7c5b94
SP		 240 struct net_device *netdev = adapter->netdev;
241
6b7c5b94 242 /* If link came up or went down */
a8f447bd 243 if (adapter->link_up != link_up) {
0dffc83e 244 adapter->link_speed = -1;
a8f447bd 245 if (link_up) {
6b7c5b94
SP		 246 netif_start_queue(netdev);
247 netif_carrier_on(netdev);
248 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd
SP		 249 } else {
250 netif_stop_queue(netdev);
251 netif_carrier_off(netdev);
252 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 253 }
a8f447bd 254 adapter->link_up = link_up;
6b7c5b94 255 }
6b7c5b94
SP		 256}
257
258/* Update the EQ delay n BE based on the RX frags consumed / sec */
259static void be_rx_eqd_update(struct be_adapter *adapter)
260{
6b7c5b94
SP		 261 struct be_eq_obj *rx_eq = &adapter->rx_eq;
262 struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
4097f663
SP		 263 ulong now = jiffies;
264 u32 eqd;
265
266 if (!rx_eq->enable_aic)
267 return;
268
269 /* Wrapped around */
270 if (time_before(now, stats->rx_fps_jiffies)) {
271 stats->rx_fps_jiffies = now;
272 return;
273 }
6b7c5b94
SP		 274
275 /* Update once a second */
4097f663 276 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 277 return;
278
279 stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
4097f663 280 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 281
4097f663 282 stats->rx_fps_jiffies = now;
6b7c5b94
SP		 283 stats->be_prev_rx_frags = stats->be_rx_frags;
284 eqd = stats->be_rx_fps / 110000;
285 eqd = eqd << 3;
286 if (eqd > rx_eq->max_eqd)
287 eqd = rx_eq->max_eqd;
288 if (eqd < rx_eq->min_eqd)
289 eqd = rx_eq->min_eqd;
290 if (eqd < 10)
291 eqd = 0;
292 if (eqd != rx_eq->cur_eqd)
8788fdc2 293 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 294
295 rx_eq->cur_eqd = eqd;
296}
297
6b7c5b94
SP		 298static struct net_device_stats *be_get_stats(struct net_device *dev)
299{
78122a52 300 return &dev->stats;
6b7c5b94
SP		 301}
302
65f71b8b
SH		 303static u32 be_calc_rate(u64 bytes, unsigned long ticks)
304{
305 u64 rate = bytes;
306
307 do_div(rate, ticks / HZ);
308 rate <<= 3; /* bytes/sec -> bits/sec */
309 do_div(rate, 1000000ul); /* MB/Sec */
310
311 return rate;
312}
313
4097f663
SP		 314static void be_tx_rate_update(struct be_adapter *adapter)
315{
316 struct be_drvr_stats *stats = drvr_stats(adapter);
317 ulong now = jiffies;
318
319 /* Wrapped around? */
320 if (time_before(now, stats->be_tx_jiffies)) {
321 stats->be_tx_jiffies = now;
322 return;
323 }
324
325 /* Update tx rate once in two seconds */
326 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 327 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
328 - stats->be_tx_bytes_prev,
329 now - stats->be_tx_jiffies);
4097f663
SP		 330 stats->be_tx_jiffies = now;
331 stats->be_tx_bytes_prev = stats->be_tx_bytes;
332 }
333}
334
6b7c5b94 335static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 336 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 337{
4097f663 338 struct be_drvr_stats *stats = drvr_stats(adapter);
6b7c5b94
SP		 339 stats->be_tx_reqs++;
340 stats->be_tx_wrbs += wrb_cnt;
341 stats->be_tx_bytes += copied;
91992e44 342 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 343 if (stopped)
344 stats->be_tx_stops++;
6b7c5b94
SP		 345}
346
347/* Determine number of WRB entries needed to xmit data in an skb */
348static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
349{
ebc8d2ab
DM		 350 int cnt = (skb->len > skb->data_len);
351
352 cnt += skb_shinfo(skb)->nr_frags;
353
6b7c5b94
SP		 354 /* to account for hdr wrb */
355 cnt++;
356 if (cnt & 1) {
357 /* add a dummy to make it an even num */
358 cnt++;
359 *dummy = true;
360 } else
361 *dummy = false;
362 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
363 return cnt;
364}
365
366static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
367{
368 wrb->frag_pa_hi = upper_32_bits(addr);
369 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
370 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
371}
372
373static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
374 bool vlan, u32 wrb_cnt, u32 len)
375{
376 memset(hdr, 0, sizeof(*hdr));
377
378 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
379
49e4b847 380 if (skb_is_gso(skb)) {
6b7c5b94
SP		 381 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
382 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
383 hdr, skb_shinfo(skb)->gso_size);
49e4b847
AK		 384 if (skb_is_gso_v6(skb))
385 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
6b7c5b94
SP		 386 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
387 if (is_tcp_pkt(skb))
388 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
389 else if (is_udp_pkt(skb))
390 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
391 }
392
393 if (vlan && vlan_tx_tag_present(skb)) {
394 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
395 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
396 hdr, vlan_tx_tag_get(skb));
397 }
398
399 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
400 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
401 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
402 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
403}
404
7101e111
SP		 405static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
406 bool unmap_single)
407{
408 dma_addr_t dma;
409
410 be_dws_le_to_cpu(wrb, sizeof(*wrb));
411
412 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 413 if (wrb->frag_len) {
7101e111
SP		 414 if (unmap_single)
415 pci_unmap_single(pdev, dma, wrb->frag_len,
416 PCI_DMA_TODEVICE);
417 else
418 pci_unmap_page(pdev, dma, wrb->frag_len,
419 PCI_DMA_TODEVICE);
420 }
421}
6b7c5b94
SP		 422
423static int make_tx_wrbs(struct be_adapter *adapter,
424 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
425{
7101e111
SP		 426 dma_addr_t busaddr;
427 int i, copied = 0;
6b7c5b94
SP		 428 struct pci_dev *pdev = adapter->pdev;
429 struct sk_buff *first_skb = skb;
430 struct be_queue_info *txq = &adapter->tx_obj.q;
431 struct be_eth_wrb *wrb;
432 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 433 bool map_single = false;
434 u16 map_head;
6b7c5b94 435
6b7c5b94
SP		 436 hdr = queue_head_node(txq);
437 queue_head_inc(txq);
7101e111 438 map_head = txq->head;
6b7c5b94 439
ebc8d2ab 440 if (skb->len > skb->data_len) {
e743d313 441 int len = skb_headlen(skb);
a73b796e
AD		 442 busaddr = pci_map_single(pdev, skb->data, len,
443 PCI_DMA_TODEVICE);
7101e111
SP		 444 if (pci_dma_mapping_error(pdev, busaddr))
445 goto dma_err;
446 map_single = true;
ebc8d2ab
DM		 447 wrb = queue_head_node(txq);
448 wrb_fill(wrb, busaddr, len);
449 be_dws_cpu_to_le(wrb, sizeof(*wrb));
450 queue_head_inc(txq);
451 copied += len;
452 }
6b7c5b94 453
ebc8d2ab
DM		 454 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
455 struct skb_frag_struct *frag =
456 &skb_shinfo(skb)->frags[i];
a73b796e
AD		 457 busaddr = pci_map_page(pdev, frag->page,
458 frag->page_offset,
459 frag->size, PCI_DMA_TODEVICE);
7101e111
SP		 460 if (pci_dma_mapping_error(pdev, busaddr))
461 goto dma_err;
ebc8d2ab
DM		 462 wrb = queue_head_node(txq);
463 wrb_fill(wrb, busaddr, frag->size);
464 be_dws_cpu_to_le(wrb, sizeof(*wrb));
465 queue_head_inc(txq);
466 copied += frag->size;
6b7c5b94
SP		 467 }
468
469 if (dummy_wrb) {
470 wrb = queue_head_node(txq);
471 wrb_fill(wrb, 0, 0);
472 be_dws_cpu_to_le(wrb, sizeof(*wrb));
473 queue_head_inc(txq);
474 }
475
476 wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
477 wrb_cnt, copied);
478 be_dws_cpu_to_le(hdr, sizeof(*hdr));
479
480 return copied;
7101e111
SP		 481dma_err:
482 txq->head = map_head;
483 while (copied) {
484 wrb = queue_head_node(txq);
485 unmap_tx_frag(pdev, wrb, map_single);
486 map_single = false;
487 copied -= wrb->frag_len;
488 queue_head_inc(txq);
489 }
490 return 0;
6b7c5b94
SP		 491}
492
61357325 493static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 494 struct net_device *netdev)
6b7c5b94
SP		 495{
496 struct be_adapter *adapter = netdev_priv(netdev);
497 struct be_tx_obj *tx_obj = &adapter->tx_obj;
498 struct be_queue_info *txq = &tx_obj->q;
499 u32 wrb_cnt = 0, copied = 0;
500 u32 start = txq->head;
501 bool dummy_wrb, stopped = false;
502
503 wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
504
505 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 506 if (copied) {
507 /* record the sent skb in the sent_skb table */
508 BUG_ON(tx_obj->sent_skb_list[start]);
509 tx_obj->sent_skb_list[start] = skb;
510
511 /* Ensure txq has space for the next skb; Else stop the queue
512 * *BEFORE* ringing the tx doorbell, so that we serialze the
513 * tx compls of the current transmit which'll wake up the queue
514 */
7101e111 515 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 516 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
517 txq->len) {
518 netif_stop_queue(netdev);
519 stopped = true;
520 }
6b7c5b94 521
c190e3c8 522 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 523
91992e44
AK		 524 be_tx_stats_update(adapter, wrb_cnt, copied,
525 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 526 } else {
527 txq->head = start;
528 dev_kfree_skb_any(skb);
6b7c5b94 529 }
6b7c5b94
SP		 530 return NETDEV_TX_OK;
531}
532
533static int be_change_mtu(struct net_device *netdev, int new_mtu)
534{
535 struct be_adapter *adapter = netdev_priv(netdev);
536 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 537 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
538 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 539 dev_info(&adapter->pdev->dev,
540 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 541 BE_MIN_MTU,
542 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 543 return -EINVAL;
544 }
545 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
546 netdev->mtu, new_mtu);
547 netdev->mtu = new_mtu;
548 return 0;
549}
550
551/*
82903e4b
AK		 552 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
553 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 554 */
b31c50a7 555static int be_vid_config(struct be_adapter *adapter)
6b7c5b94 556{
6b7c5b94
SP		 557 u16 vtag[BE_NUM_VLANS_SUPPORTED];
558 u16 ntags = 0, i;
82903e4b 559 int status = 0;
6b7c5b94 560
82903e4b 561 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94
SP		 562 /* Construct VLAN Table to give to HW */
563 for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
564 if (adapter->vlan_tag[i]) {
565 vtag[ntags] = cpu_to_le16(i);
566 ntags++;
567 }
568 }
b31c50a7
SP		 569 status = be_cmd_vlan_config(adapter, adapter->if_handle,
570 vtag, ntags, 1, 0);
6b7c5b94 571 } else {
b31c50a7
SP		 572 status = be_cmd_vlan_config(adapter, adapter->if_handle,
573 NULL, 0, 1, 1);
6b7c5b94 574 }
b31c50a7 575 return status;
6b7c5b94
SP		 576}
577
578static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
579{
580 struct be_adapter *adapter = netdev_priv(netdev);
581 struct be_eq_obj *rx_eq = &adapter->rx_eq;
582 struct be_eq_obj *tx_eq = &adapter->tx_eq;
6b7c5b94 583
8788fdc2
SP		 584 be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
585 be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
6b7c5b94 586 adapter->vlan_grp = grp;
8788fdc2
SP		 587 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
588 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
6b7c5b94
SP		 589}
590
591static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
592{
593 struct be_adapter *adapter = netdev_priv(netdev);
594
ba343c77
SB		 595 if (!be_physfn(adapter))
596 return;
597
6b7c5b94 598 adapter->vlan_tag[vid] = 1;
82903e4b
AK		 599 adapter->vlans_added++;
600 if (adapter->vlans_added <= (adapter->max_vlans + 1))
601 be_vid_config(adapter);
6b7c5b94
SP		 602}
603
604static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
605{
606 struct be_adapter *adapter = netdev_priv(netdev);
607
ba343c77
SB		 608 if (!be_physfn(adapter))
609 return;
610
6b7c5b94 611 adapter->vlan_tag[vid] = 0;
6b7c5b94 612 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
82903e4b
AK		 613 adapter->vlans_added--;
614 if (adapter->vlans_added <= adapter->max_vlans)
615 be_vid_config(adapter);
6b7c5b94
SP		 616}
617
24307eef 618static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 619{
620 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 621
24307eef 622 if (netdev->flags & IFF_PROMISC) {
8788fdc2 623 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 624 adapter->promiscuous = true;
625 goto done;
6b7c5b94
SP		 626 }
627
24307eef
SP		 628 /* BE was previously in promiscous mode; disable it */
629 if (adapter->promiscuous) {
630 adapter->promiscuous = false;
8788fdc2 631 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 632 }
633
e7b909a6 634 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 635 if (netdev->flags & IFF_ALLMULTI ||
636 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 637 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 638 &adapter->mc_cmd_mem);
24307eef 639 goto done;
6b7c5b94 640 }
6b7c5b94 641
0ddf477b 642 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 643 &adapter->mc_cmd_mem);
24307eef
SP		 644done:
645 return;
6b7c5b94
SP		 646}
647
ba343c77
SB		 648static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
649{
650 struct be_adapter *adapter = netdev_priv(netdev);
651 int status;
652
653 if (!adapter->sriov_enabled)
654 return -EPERM;
655
656 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
657 return -EINVAL;
658
659 status = be_cmd_pmac_del(adapter, adapter->vf_if_handle[vf],
660 adapter->vf_pmac_id[vf]);
661
662 status = be_cmd_pmac_add(adapter, mac, adapter->vf_if_handle[vf],
663 &adapter->vf_pmac_id[vf]);
664 if (!status)
665 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
666 mac, vf);
667 return status;
668}
669
4097f663 670static void be_rx_rate_update(struct be_adapter *adapter)
6b7c5b94 671{
4097f663
SP		 672 struct be_drvr_stats *stats = drvr_stats(adapter);
673 ulong now = jiffies;
6b7c5b94 674
4097f663
SP		 675 /* Wrapped around */
676 if (time_before(now, stats->be_rx_jiffies)) {
677 stats->be_rx_jiffies = now;
678 return;
679 }
6b7c5b94
SP		 680
681 /* Update the rate once in two seconds */
4097f663 682 if ((now - stats->be_rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 683 return;
684
65f71b8b
SH		 685 stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
686 - stats->be_rx_bytes_prev,
687 now - stats->be_rx_jiffies);
4097f663 688 stats->be_rx_jiffies = now;
6b7c5b94
SP		 689 stats->be_rx_bytes_prev = stats->be_rx_bytes;
690}
691
4097f663
SP		 692static void be_rx_stats_update(struct be_adapter *adapter,
693 u32 pktsize, u16 numfrags)
694{
695 struct be_drvr_stats *stats = drvr_stats(adapter);
696
697 stats->be_rx_compl++;
698 stats->be_rx_frags += numfrags;
699 stats->be_rx_bytes += pktsize;
91992e44 700 stats->be_rx_pkts++;
4097f663
SP		 701}
702
728a9972
AK		 703static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
704{
705 u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
706
707 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
708 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
709 ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
710 if (ip_version) {
711 tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
712 udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
713 }
714 ipv6_chk = (ip_version && (tcpf || udpf));
715
716 return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
717}
718
6b7c5b94
SP		 719static struct be_rx_page_info *
720get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
721{
722 struct be_rx_page_info *rx_page_info;
723 struct be_queue_info *rxq = &adapter->rx_obj.q;
724
725 rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
726 BUG_ON(!rx_page_info->page);
727
205859a2 728 if (rx_page_info->last_page_user) {
fac6da5b 729 pci_unmap_page(adapter->pdev, dma_unmap_addr(rx_page_info, bus),
6b7c5b94 730 adapter->big_page_size, PCI_DMA_FROMDEVICE);
205859a2
AK		 731 rx_page_info->last_page_user = false;
732 }
6b7c5b94
SP		 733
734 atomic_dec(&rxq->used);
735 return rx_page_info;
736}
737
738/* Throwaway the data in the Rx completion */
739static void be_rx_compl_discard(struct be_adapter *adapter,
740 struct be_eth_rx_compl *rxcp)
741{
742 struct be_queue_info *rxq = &adapter->rx_obj.q;
743 struct be_rx_page_info *page_info;
744 u16 rxq_idx, i, num_rcvd;
745
746 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
747 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
748
749 for (i = 0; i < num_rcvd; i++) {
750 page_info = get_rx_page_info(adapter, rxq_idx);
751 put_page(page_info->page);
752 memset(page_info, 0, sizeof(*page_info));
753 index_inc(&rxq_idx, rxq->len);
754 }
755}
756
757/*
758 * skb_fill_rx_data forms a complete skb for an ether frame
759 * indicated by rxcp.
760 */
761static void skb_fill_rx_data(struct be_adapter *adapter,
89420424
SP		 762 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
763 u16 num_rcvd)
6b7c5b94
SP		 764{
765 struct be_queue_info *rxq = &adapter->rx_obj.q;
766 struct be_rx_page_info *page_info;
89420424 767 u16 rxq_idx, i, j;
fa77406a 768 u32 pktsize, hdr_len, curr_frag_len, size;
6b7c5b94
SP		 769 u8 *start;
770
771 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
772 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
6b7c5b94
SP		 773
774 page_info = get_rx_page_info(adapter, rxq_idx);
775
776 start = page_address(page_info->page) + page_info->page_offset;
777 prefetch(start);
778
779 /* Copy data in the first descriptor of this completion */
780 curr_frag_len = min(pktsize, rx_frag_size);
781
782 /* Copy the header portion into skb_data */
783 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
784 memcpy(skb->data, start, hdr_len);
785 skb->len = curr_frag_len;
786 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
787 /* Complete packet has now been moved to data */
788 put_page(page_info->page);
789 skb->data_len = 0;
790 skb->tail += curr_frag_len;
791 } else {
792 skb_shinfo(skb)->nr_frags = 1;
793 skb_shinfo(skb)->frags[0].page = page_info->page;
794 skb_shinfo(skb)->frags[0].page_offset =
795 page_info->page_offset + hdr_len;
796 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
797 skb->data_len = curr_frag_len - hdr_len;
798 skb->tail += hdr_len;
799 }
205859a2 800 page_info->page = NULL;
6b7c5b94
SP		 801
802 if (pktsize <= rx_frag_size) {
803 BUG_ON(num_rcvd != 1);
76fbb429 804 goto done;
6b7c5b94
SP		 805 }
806
807 /* More frags present for this completion */
fa77406a 808 size = pktsize;
bd46cb6c 809 for (i = 1, j = 0; i < num_rcvd; i++) {
fa77406a 810 size -= curr_frag_len;
6b7c5b94
SP		 811 index_inc(&rxq_idx, rxq->len);
812 page_info = get_rx_page_info(adapter, rxq_idx);
813
fa77406a 814 curr_frag_len = min(size, rx_frag_size);
6b7c5b94 815
bd46cb6c
AK		 816 /* Coalesce all frags from the same physical page in one slot */
817 if (page_info->page_offset == 0) {
818 /* Fresh page */
819 j++;
820 skb_shinfo(skb)->frags[j].page = page_info->page;
821 skb_shinfo(skb)->frags[j].page_offset =
822 page_info->page_offset;
823 skb_shinfo(skb)->frags[j].size = 0;
824 skb_shinfo(skb)->nr_frags++;
825 } else {
826 put_page(page_info->page);
827 }
828
829 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 830 skb->len += curr_frag_len;
831 skb->data_len += curr_frag_len;
6b7c5b94 832
205859a2 833 page_info->page = NULL;
6b7c5b94 834 }
bd46cb6c 835 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 836
76fbb429 837done:
4097f663 838 be_rx_stats_update(adapter, pktsize, num_rcvd);
6b7c5b94
SP		 839}
840
5be93b9a 841/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94
SP		 842static void be_rx_compl_process(struct be_adapter *adapter,
843 struct be_eth_rx_compl *rxcp)
844{
845 struct sk_buff *skb;
dcb9b564 846 u32 vlanf, vid;
89420424 847 u16 num_rcvd;
dcb9b564 848 u8 vtm;
6b7c5b94 849
89420424
SP		 850 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
851 /* Is it a flush compl that has no data */
852 if (unlikely(num_rcvd == 0))
853 return;
854
89d71a66 855 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 856 if (unlikely(!skb)) {
6b7c5b94
SP		 857 if (net_ratelimit())
858 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
859 be_rx_compl_discard(adapter, rxcp);
860 return;
861 }
862
89420424 863 skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
6b7c5b94 864
728a9972 865 if (do_pkt_csum(rxcp, adapter->rx_csum))
6b7c5b94 866 skb->ip_summed = CHECKSUM_NONE;
728a9972
AK		 867 else
868 skb->ip_summed = CHECKSUM_UNNECESSARY;
6b7c5b94
SP		 869
870 skb->truesize = skb->len + sizeof(struct sk_buff);
871 skb->protocol = eth_type_trans(skb, adapter->netdev);
6b7c5b94 872
a058a632
SP		 873 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
874 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
875
876 /* vlanf could be wrongly set in some cards.
877 * ignore if vtm is not set */
878 if ((adapter->cap & 0x400) && !vtm)
879 vlanf = 0;
880
881 if (unlikely(vlanf)) {
82903e4b 882 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 883 kfree_skb(skb);
884 return;
885 }
886 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
9cae9e4f 887 vid = swab16(vid);
6b7c5b94
SP		 888 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
889 } else {
890 netif_receive_skb(skb);
891 }
6b7c5b94
SP		 892}
893
5be93b9a
AK		 894/* Process the RX completion indicated by rxcp when GRO is enabled */
895static void be_rx_compl_process_gro(struct be_adapter *adapter,
6b7c5b94
SP		 896 struct be_eth_rx_compl *rxcp)
897{
898 struct be_rx_page_info *page_info;
5be93b9a 899 struct sk_buff *skb = NULL;
6b7c5b94 900 struct be_queue_info *rxq = &adapter->rx_obj.q;
5be93b9a 901 struct be_eq_obj *eq_obj = &adapter->rx_eq;
6b7c5b94 902 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
bd46cb6c 903 u16 i, rxq_idx = 0, vid, j;
dcb9b564 904 u8 vtm;
6b7c5b94
SP		 905
906 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
89420424
SP		 907 /* Is it a flush compl that has no data */
908 if (unlikely(num_rcvd == 0))
909 return;
910
6b7c5b94
SP		 911 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
912 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
913 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
dcb9b564
AK		 914 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
915
916 /* vlanf could be wrongly set in some cards.
917 * ignore if vtm is not set */
e1187b3b 918 if ((adapter->cap & 0x400) && !vtm)
dcb9b564 919 vlanf = 0;
6b7c5b94 920
5be93b9a
AK		 921 skb = napi_get_frags(&eq_obj->napi);
922 if (!skb) {
923 be_rx_compl_discard(adapter, rxcp);
924 return;
925 }
926
6b7c5b94 927 remaining = pkt_size;
bd46cb6c 928 for (i = 0, j = -1; i < num_rcvd; i++) {
6b7c5b94
SP		 929 page_info = get_rx_page_info(adapter, rxq_idx);
930
931 curr_frag_len = min(remaining, rx_frag_size);
932
bd46cb6c
AK		 933 /* Coalesce all frags from the same physical page in one slot */
934 if (i == 0 || page_info->page_offset == 0) {
935 /* First frag or Fresh page */
936 j++;
5be93b9a
AK		 937 skb_shinfo(skb)->frags[j].page = page_info->page;
938 skb_shinfo(skb)->frags[j].page_offset =
939 page_info->page_offset;
940 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 941 } else {
942 put_page(page_info->page);
943 }
5be93b9a 944 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 945
bd46cb6c 946 remaining -= curr_frag_len;
6b7c5b94 947 index_inc(&rxq_idx, rxq->len);
6b7c5b94
SP		 948 memset(page_info, 0, sizeof(*page_info));
949 }
bd46cb6c 950 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 951
5be93b9a
AK		 952 skb_shinfo(skb)->nr_frags = j + 1;
953 skb->len = pkt_size;
954 skb->data_len = pkt_size;
955 skb->truesize += pkt_size;
956 skb->ip_summed = CHECKSUM_UNNECESSARY;
957
6b7c5b94 958 if (likely(!vlanf)) {
5be93b9a 959 napi_gro_frags(&eq_obj->napi);
6b7c5b94
SP		 960 } else {
961 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
9cae9e4f 962 vid = swab16(vid);
6b7c5b94 963
82903e4b 964 if (!adapter->vlan_grp || adapter->vlans_added == 0)
6b7c5b94
SP		 965 return;
966
5be93b9a 967 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
6b7c5b94
SP		 968 }
969
4097f663 970 be_rx_stats_update(adapter, pkt_size, num_rcvd);
6b7c5b94
SP		 971}
972
973static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
974{
975 struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
976
977 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
978 return NULL;
979
f3eb62d2 980 rmb();
6b7c5b94
SP		 981 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
982
6b7c5b94
SP		 983 queue_tail_inc(&adapter->rx_obj.cq);
984 return rxcp;
985}
986
a7a0ef31
SP		 987/* To reset the valid bit, we need to reset the whole word as
988 * when walking the queue the valid entries are little-endian
989 * and invalid entries are host endian
990 */
991static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
992{
993 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
994}
995
6b7c5b94
SP		 996static inline struct page *be_alloc_pages(u32 size)
997{
998 gfp_t alloc_flags = GFP_ATOMIC;
999 u32 order = get_order(size);
1000 if (order > 0)
1001 alloc_flags |= __GFP_COMP;
1002 return alloc_pages(alloc_flags, order);
1003}
1004
1005/*
1006 * Allocate a page, split it to fragments of size rx_frag_size and post as
1007 * receive buffers to BE
1008 */
1009static void be_post_rx_frags(struct be_adapter *adapter)
1010{
1011 struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
26d92f92 1012 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
6b7c5b94
SP		 1013 struct be_queue_info *rxq = &adapter->rx_obj.q;
1014 struct page *pagep = NULL;
1015 struct be_eth_rx_d *rxd;
1016 u64 page_dmaaddr = 0, frag_dmaaddr;
1017 u32 posted, page_offset = 0;
1018
6b7c5b94
SP		 1019 page_info = &page_info_tbl[rxq->head];
1020 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1021 if (!pagep) {
1022 pagep = be_alloc_pages(adapter->big_page_size);
1023 if (unlikely(!pagep)) {
1024 drvr_stats(adapter)->be_ethrx_post_fail++;
1025 break;
1026 }
1027 page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
1028 adapter->big_page_size,
1029 PCI_DMA_FROMDEVICE);
1030 page_info->page_offset = 0;
1031 } else {
1032 get_page(pagep);
1033 page_info->page_offset = page_offset + rx_frag_size;
1034 }
1035 page_offset = page_info->page_offset;
1036 page_info->page = pagep;
fac6da5b 1037 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1038 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1039
1040 rxd = queue_head_node(rxq);
1041 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1042 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1043
1044 /* Any space left in the current big page for another frag? */
1045 if ((page_offset + rx_frag_size + rx_frag_size) >
1046 adapter->big_page_size) {
1047 pagep = NULL;
1048 page_info->last_page_user = true;
1049 }
26d92f92
SP		 1050
1051 prev_page_info = page_info;
1052 queue_head_inc(rxq);
6b7c5b94
SP		 1053 page_info = &page_info_tbl[rxq->head];
1054 }
1055 if (pagep)
26d92f92 1056 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1057
1058 if (posted) {
6b7c5b94 1059 atomic_add(posted, &rxq->used);
8788fdc2 1060 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1061 } else if (atomic_read(&rxq->used) == 0) {
1062 /* Let be_worker replenish when memory is available */
1063 adapter->rx_post_starved = true;
6b7c5b94 1064 }
6b7c5b94
SP		 1065}
1066
5fb379ee 1067static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1068{
6b7c5b94
SP		 1069 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1070
1071 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1072 return NULL;
1073
f3eb62d2 1074 rmb();
6b7c5b94
SP		 1075 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1076
1077 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1078
1079 queue_tail_inc(tx_cq);
1080 return txcp;
1081}
1082
1083static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1084{
1085 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1086 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1087 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1088 struct sk_buff *sent_skb;
ec43b1a6
SP		 1089 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1090 bool unmap_skb_hdr = true;
6b7c5b94 1091
ec43b1a6 1092 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1093 BUG_ON(!sent_skb);
ec43b1a6
SP		 1094 sent_skbs[txq->tail] = NULL;
1095
1096 /* skip header wrb */
a73b796e 1097 queue_tail_inc(txq);
6b7c5b94 1098
ec43b1a6 1099 do {
6b7c5b94 1100 cur_index = txq->tail;
a73b796e 1101 wrb = queue_tail_node(txq);
ec43b1a6 1102 unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
e743d313 1103 skb_headlen(sent_skb)));
ec43b1a6
SP		 1104 unmap_skb_hdr = false;
1105
6b7c5b94
SP		 1106 num_wrbs++;
1107 queue_tail_inc(txq);
ec43b1a6 1108 } while (cur_index != last_index);
6b7c5b94
SP		 1109
1110 atomic_sub(num_wrbs, &txq->used);
a73b796e 1111
6b7c5b94
SP		 1112 kfree_skb(sent_skb);
1113}
1114
859b1e4e
SP		 1115static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1116{
1117 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1118
1119 if (!eqe->evt)
1120 return NULL;
1121
f3eb62d2 1122 rmb();
859b1e4e
SP		 1123 eqe->evt = le32_to_cpu(eqe->evt);
1124 queue_tail_inc(&eq_obj->q);
1125 return eqe;
1126}
1127
1128static int event_handle(struct be_adapter *adapter,
1129 struct be_eq_obj *eq_obj)
1130{
1131 struct be_eq_entry *eqe;
1132 u16 num = 0;
1133
1134 while ((eqe = event_get(eq_obj)) != NULL) {
1135 eqe->evt = 0;
1136 num++;
1137 }
1138
1139 /* Deal with any spurious interrupts that come
1140 * without events
1141 */
1142 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1143 if (num)
1144 napi_schedule(&eq_obj->napi);
1145
1146 return num;
1147}
1148
1149/* Just read and notify events without processing them.
1150 * Used at the time of destroying event queues */
1151static void be_eq_clean(struct be_adapter *adapter,
1152 struct be_eq_obj *eq_obj)
1153{
1154 struct be_eq_entry *eqe;
1155 u16 num = 0;
1156
1157 while ((eqe = event_get(eq_obj)) != NULL) {
1158 eqe->evt = 0;
1159 num++;
1160 }
1161
1162 if (num)
1163 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1164}
1165
6b7c5b94
SP		 1166static void be_rx_q_clean(struct be_adapter *adapter)
1167{
1168 struct be_rx_page_info *page_info;
1169 struct be_queue_info *rxq = &adapter->rx_obj.q;
1170 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1171 struct be_eth_rx_compl *rxcp;
1172 u16 tail;
1173
1174 /* First cleanup pending rx completions */
1175 while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
1176 be_rx_compl_discard(adapter, rxcp);
a7a0ef31 1177 be_rx_compl_reset(rxcp);
8788fdc2 1178 be_cq_notify(adapter, rx_cq->id, true, 1);
6b7c5b94
SP		 1179 }
1180
1181 /* Then free posted rx buffer that were not used */
1182 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1183 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
6b7c5b94
SP		 1184 page_info = get_rx_page_info(adapter, tail);
1185 put_page(page_info->page);
1186 memset(page_info, 0, sizeof(*page_info));
1187 }
1188 BUG_ON(atomic_read(&rxq->used));
1189}
1190
a8e9179a 1191static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1192{
a8e9179a 1193 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1194 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1195 struct be_eth_tx_compl *txcp;
1196 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1197 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1198 struct sk_buff *sent_skb;
1199 bool dummy_wrb;
a8e9179a
SP		 1200
1201 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1202 do {
1203 while ((txcp = be_tx_compl_get(tx_cq))) {
1204 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1205 wrb_index, txcp);
1206 be_tx_compl_process(adapter, end_idx);
1207 cmpl++;
1208 }
1209 if (cmpl) {
1210 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1211 cmpl = 0;
1212 }
1213
1214 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1215 break;
1216
1217 mdelay(1);
1218 } while (true);
1219
1220 if (atomic_read(&txq->used))
1221 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1222 atomic_read(&txq->used));
b03388d6
SP		 1223
1224 /* free posted tx for which compls will never arrive */
1225 while (atomic_read(&txq->used)) {
1226 sent_skb = sent_skbs[txq->tail];
1227 end_idx = txq->tail;
1228 index_adv(&end_idx,
1229 wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
1230 be_tx_compl_process(adapter, end_idx);
1231 }
6b7c5b94
SP		 1232}
1233
5fb379ee
SP		 1234static void be_mcc_queues_destroy(struct be_adapter *adapter)
1235{
1236 struct be_queue_info *q;
5fb379ee 1237
8788fdc2 1238 q = &adapter->mcc_obj.q;
5fb379ee 1239 if (q->created)
8788fdc2 1240 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1241 be_queue_free(adapter, q);
1242
8788fdc2 1243 q = &adapter->mcc_obj.cq;
5fb379ee 1244 if (q->created)
8788fdc2 1245 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1246 be_queue_free(adapter, q);
1247}
1248
1249/* Must be called only after TX qs are created as MCC shares TX EQ */
1250static int be_mcc_queues_create(struct be_adapter *adapter)
1251{
1252 struct be_queue_info *q, *cq;
5fb379ee
SP		 1253
1254 /* Alloc MCC compl queue */
8788fdc2 1255 cq = &adapter->mcc_obj.cq;
5fb379ee 1256 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1257 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1258 goto err;
1259
1260 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1261 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1262 goto mcc_cq_free;
1263
1264 /* Alloc MCC queue */
8788fdc2 1265 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1266 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1267 goto mcc_cq_destroy;
1268
1269 /* Ask BE to create MCC queue */
8788fdc2 1270 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1271 goto mcc_q_free;
1272
1273 return 0;
1274
1275mcc_q_free:
1276 be_queue_free(adapter, q);
1277mcc_cq_destroy:
8788fdc2 1278 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1279mcc_cq_free:
1280 be_queue_free(adapter, cq);
1281err:
1282 return -1;
1283}
1284
6b7c5b94
SP		 1285static void be_tx_queues_destroy(struct be_adapter *adapter)
1286{
1287 struct be_queue_info *q;
1288
1289 q = &adapter->tx_obj.q;
a8e9179a 1290 if (q->created)
8788fdc2 1291 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1292 be_queue_free(adapter, q);
1293
1294 q = &adapter->tx_obj.cq;
1295 if (q->created)
8788fdc2 1296 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1297 be_queue_free(adapter, q);
1298
859b1e4e
SP		 1299 /* Clear any residual events */
1300 be_eq_clean(adapter, &adapter->tx_eq);
1301
6b7c5b94
SP		 1302 q = &adapter->tx_eq.q;
1303 if (q->created)
8788fdc2 1304 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1305 be_queue_free(adapter, q);
1306}
1307
1308static int be_tx_queues_create(struct be_adapter *adapter)
1309{
1310 struct be_queue_info *eq, *q, *cq;
1311
1312 adapter->tx_eq.max_eqd = 0;
1313 adapter->tx_eq.min_eqd = 0;
1314 adapter->tx_eq.cur_eqd = 96;
1315 adapter->tx_eq.enable_aic = false;
1316 /* Alloc Tx Event queue */
1317 eq = &adapter->tx_eq.q;
1318 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1319 return -1;
1320
1321 /* Ask BE to create Tx Event queue */
8788fdc2 1322 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94 1323 goto tx_eq_free;
ba343c77
SB		 1324 adapter->base_eq_id = adapter->tx_eq.q.id;
1325
6b7c5b94
SP		 1326 /* Alloc TX eth compl queue */
1327 cq = &adapter->tx_obj.cq;
1328 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1329 sizeof(struct be_eth_tx_compl)))
1330 goto tx_eq_destroy;
1331
1332 /* Ask BE to create Tx eth compl queue */
8788fdc2 1333 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1334 goto tx_cq_free;
1335
1336 /* Alloc TX eth queue */
1337 q = &adapter->tx_obj.q;
1338 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1339 goto tx_cq_destroy;
1340
1341 /* Ask BE to create Tx eth queue */
8788fdc2 1342 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1343 goto tx_q_free;
1344 return 0;
1345
1346tx_q_free:
1347 be_queue_free(adapter, q);
1348tx_cq_destroy:
8788fdc2 1349 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1350tx_cq_free:
1351 be_queue_free(adapter, cq);
1352tx_eq_destroy:
8788fdc2 1353 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1354tx_eq_free:
1355 be_queue_free(adapter, eq);
1356 return -1;
1357}
1358
1359static void be_rx_queues_destroy(struct be_adapter *adapter)
1360{
1361 struct be_queue_info *q;
1362
1363 q = &adapter->rx_obj.q;
1364 if (q->created) {
8788fdc2 1365 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
89420424
SP		 1366
1367 /* After the rxq is invalidated, wait for a grace time
1368 * of 1ms for all dma to end and the flush compl to arrive
1369 */
1370 mdelay(1);
6b7c5b94
SP		 1371 be_rx_q_clean(adapter);
1372 }
1373 be_queue_free(adapter, q);
1374
1375 q = &adapter->rx_obj.cq;
1376 if (q->created)
8788fdc2 1377 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1378 be_queue_free(adapter, q);
1379
859b1e4e
SP		 1380 /* Clear any residual events */
1381 be_eq_clean(adapter, &adapter->rx_eq);
1382
6b7c5b94
SP		 1383 q = &adapter->rx_eq.q;
1384 if (q->created)
8788fdc2 1385 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1386 be_queue_free(adapter, q);
1387}
1388
1389static int be_rx_queues_create(struct be_adapter *adapter)
1390{
1391 struct be_queue_info *eq, *q, *cq;
1392 int rc;
1393
6b7c5b94
SP		 1394 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
1395 adapter->rx_eq.max_eqd = BE_MAX_EQD;
1396 adapter->rx_eq.min_eqd = 0;
1397 adapter->rx_eq.cur_eqd = 0;
1398 adapter->rx_eq.enable_aic = true;
1399
1400 /* Alloc Rx Event queue */
1401 eq = &adapter->rx_eq.q;
1402 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1403 sizeof(struct be_eq_entry));
1404 if (rc)
1405 return rc;
1406
1407 /* Ask BE to create Rx Event queue */
8788fdc2 1408 rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
6b7c5b94
SP		 1409 if (rc)
1410 goto rx_eq_free;
1411
1412 /* Alloc RX eth compl queue */
1413 cq = &adapter->rx_obj.cq;
1414 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1415 sizeof(struct be_eth_rx_compl));
1416 if (rc)
1417 goto rx_eq_destroy;
1418
1419 /* Ask BE to create Rx eth compl queue */
8788fdc2 1420 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
6b7c5b94
SP		 1421 if (rc)
1422 goto rx_cq_free;
1423
1424 /* Alloc RX eth queue */
1425 q = &adapter->rx_obj.q;
1426 rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
1427 if (rc)
1428 goto rx_cq_destroy;
1429
1430 /* Ask BE to create Rx eth queue */
8788fdc2 1431 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
6b7c5b94
SP		 1432 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
1433 if (rc)
1434 goto rx_q_free;
1435
1436 return 0;
1437rx_q_free:
1438 be_queue_free(adapter, q);
1439rx_cq_destroy:
8788fdc2 1440 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1441rx_cq_free:
1442 be_queue_free(adapter, cq);
1443rx_eq_destroy:
8788fdc2 1444 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1445rx_eq_free:
1446 be_queue_free(adapter, eq);
1447 return rc;
1448}
6b7c5b94 1449
b628bde2
SP		 1450/* There are 8 evt ids per func. Retruns the evt id's bit number */
1451static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
1452{
ba343c77 1453 return eq_id - adapter->base_eq_id;
b628bde2
SP		 1454}
1455
6b7c5b94
SP		 1456static irqreturn_t be_intx(int irq, void *dev)
1457{
1458 struct be_adapter *adapter = dev;
8788fdc2 1459 int isr;
6b7c5b94 1460
8788fdc2 1461 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
55bdeed9 1462 (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
c001c213 1463 if (!isr)
8788fdc2 1464 return IRQ_NONE;
6b7c5b94 1465
8788fdc2
SP		 1466 event_handle(adapter, &adapter->tx_eq);
1467 event_handle(adapter, &adapter->rx_eq);
c001c213 1468
8788fdc2 1469 return IRQ_HANDLED;
6b7c5b94
SP		 1470}
1471
1472static irqreturn_t be_msix_rx(int irq, void *dev)
1473{
1474 struct be_adapter *adapter = dev;
1475
8788fdc2 1476 event_handle(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1477
1478 return IRQ_HANDLED;
1479}
1480
5fb379ee 1481static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1482{
1483 struct be_adapter *adapter = dev;
1484
8788fdc2 1485 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1486
1487 return IRQ_HANDLED;
1488}
1489
5be93b9a 1490static inline bool do_gro(struct be_adapter *adapter,
6b7c5b94
SP		 1491 struct be_eth_rx_compl *rxcp)
1492{
1493 int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1494 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1495
1496 if (err)
1497 drvr_stats(adapter)->be_rxcp_err++;
1498
5be93b9a 1499 return (tcp_frame && !err) ? true : false;
6b7c5b94
SP		 1500}
1501
1502int be_poll_rx(struct napi_struct *napi, int budget)
1503{
1504 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
1505 struct be_adapter *adapter =
1506 container_of(rx_eq, struct be_adapter, rx_eq);
1507 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1508 struct be_eth_rx_compl *rxcp;
1509 u32 work_done;
1510
b7b83ac3 1511 adapter->stats.drvr_stats.be_rx_polls++;
6b7c5b94
SP		 1512 for (work_done = 0; work_done < budget; work_done++) {
1513 rxcp = be_rx_compl_get(adapter);
1514 if (!rxcp)
1515 break;
1516
5be93b9a
AK		 1517 if (do_gro(adapter, rxcp))
1518 be_rx_compl_process_gro(adapter, rxcp);
6b7c5b94
SP		 1519 else
1520 be_rx_compl_process(adapter, rxcp);
a7a0ef31
SP		 1521
1522 be_rx_compl_reset(rxcp);
6b7c5b94
SP		 1523 }
1524
6b7c5b94
SP		 1525 /* Refill the queue */
1526 if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
1527 be_post_rx_frags(adapter);
1528
1529 /* All consumed */
1530 if (work_done < budget) {
1531 napi_complete(napi);
8788fdc2 1532 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1533 } else {
1534 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1535 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1536 }
1537 return work_done;
1538}
1539
f31e50a8
SP		 1540/* As TX and MCC share the same EQ check for both TX and MCC completions.
1541 * For TX/MCC we don't honour budget; consume everything
1542 */
1543static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1544{
f31e50a8
SP		 1545 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1546 struct be_adapter *adapter =
1547 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1548 struct be_queue_info *txq = &adapter->tx_obj.q;
1549 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1550 struct be_eth_tx_compl *txcp;
f31e50a8 1551 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1552 u16 end_idx;
1553
5fb379ee 1554 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1555 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1556 wrb_index, txcp);
6b7c5b94 1557 be_tx_compl_process(adapter, end_idx);
f31e50a8 1558 tx_compl++;
6b7c5b94
SP		 1559 }
1560
f31e50a8
SP		 1561 mcc_compl = be_process_mcc(adapter, &status);
1562
1563 napi_complete(napi);
1564
1565 if (mcc_compl) {
1566 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1567 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1568 }
1569
1570 if (tx_compl) {
1571 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1572
1573 /* As Tx wrbs have been freed up, wake up netdev queue if
1574 * it was stopped due to lack of tx wrbs.
1575 */
1576 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1577 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1578 netif_wake_queue(adapter->netdev);
1579 }
1580
1581 drvr_stats(adapter)->be_tx_events++;
f31e50a8 1582 drvr_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1583 }
6b7c5b94
SP		 1584
1585 return 1;
1586}
1587
ea1dae11
SP		 1588static void be_worker(struct work_struct *work)
1589{
1590 struct be_adapter *adapter =
1591 container_of(work, struct be_adapter, work.work);
ea1dae11 1592
b31c50a7 1593 be_cmd_get_stats(adapter, &adapter->stats.cmd);
ea1dae11
SP		 1594
1595 /* Set EQ delay */
1596 be_rx_eqd_update(adapter);
1597
4097f663
SP		 1598 be_tx_rate_update(adapter);
1599 be_rx_rate_update(adapter);
1600
ea1dae11
SP		 1601 if (adapter->rx_post_starved) {
1602 adapter->rx_post_starved = false;
1603 be_post_rx_frags(adapter);
1604 }
1605
1606 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1607}
1608
8d56ff11
SP		 1609static void be_msix_disable(struct be_adapter *adapter)
1610{
1611 if (adapter->msix_enabled) {
1612 pci_disable_msix(adapter->pdev);
1613 adapter->msix_enabled = false;
1614 }
1615}
1616
6b7c5b94
SP		 1617static void be_msix_enable(struct be_adapter *adapter)
1618{
1619 int i, status;
1620
1621 for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
1622 adapter->msix_entries[i].entry = i;
1623
1624 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1625 BE_NUM_MSIX_VECTORS);
1626 if (status == 0)
1627 adapter->msix_enabled = true;
6b7c5b94
SP		 1628}
1629
ba343c77
SB		 1630static void be_sriov_enable(struct be_adapter *adapter)
1631{
1632#ifdef CONFIG_PCI_IOV
1633 int status;
344dbf10 1634 be_check_sriov_fn_type(adapter);
ba343c77
SB		 1635 if (be_physfn(adapter) && num_vfs) {
1636 status = pci_enable_sriov(adapter->pdev, num_vfs);
1637 adapter->sriov_enabled = status ? false : true;
1638 }
1639#endif
ba343c77
SB		 1640}
1641
1642static void be_sriov_disable(struct be_adapter *adapter)
1643{
1644#ifdef CONFIG_PCI_IOV
1645 if (adapter->sriov_enabled) {
1646 pci_disable_sriov(adapter->pdev);
1647 adapter->sriov_enabled = false;
1648 }
1649#endif
1650}
1651
6b7c5b94
SP		 1652static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
1653{
b628bde2
SP		 1654 return adapter->msix_entries[
1655 be_evt_bit_get(adapter, eq_id)].vector;
6b7c5b94
SP		 1656}
1657
b628bde2
SP		 1658static int be_request_irq(struct be_adapter *adapter,
1659 struct be_eq_obj *eq_obj,
1660 void *handler, char *desc)
6b7c5b94
SP		 1661{
1662 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1663 int vec;
1664
1665 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
1666 vec = be_msix_vec_get(adapter, eq_obj->q.id);
1667 return request_irq(vec, handler, 0, eq_obj->desc, adapter);
1668}
1669
1670static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
1671{
1672 int vec = be_msix_vec_get(adapter, eq_obj->q.id);
1673 free_irq(vec, adapter);
1674}
6b7c5b94 1675
b628bde2
SP		 1676static int be_msix_register(struct be_adapter *adapter)
1677{
1678 int status;
1679
1680 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
6b7c5b94
SP		 1681 if (status)
1682 goto err;
1683
b628bde2
SP		 1684 status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
1685 if (status)
1686 goto free_tx_irq;
1687
6b7c5b94 1688 return 0;
b628bde2
SP		 1689
1690free_tx_irq:
1691 be_free_irq(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1692err:
1693 dev_warn(&adapter->pdev->dev,
1694 "MSIX Request IRQ failed - err %d\n", status);
1695 pci_disable_msix(adapter->pdev);
1696 adapter->msix_enabled = false;
1697 return status;
1698}
1699
1700static int be_irq_register(struct be_adapter *adapter)
1701{
1702 struct net_device *netdev = adapter->netdev;
1703 int status;
1704
1705 if (adapter->msix_enabled) {
1706 status = be_msix_register(adapter);
1707 if (status == 0)
1708 goto done;
ba343c77
SB		 1709 /* INTx is not supported for VF */
1710 if (!be_physfn(adapter))
1711 return status;
6b7c5b94
SP		 1712 }
1713
1714 /* INTx */
1715 netdev->irq = adapter->pdev->irq;
1716 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
1717 adapter);
1718 if (status) {
1719 dev_err(&adapter->pdev->dev,
1720 "INTx request IRQ failed - err %d\n", status);
1721 return status;
1722 }
1723done:
1724 adapter->isr_registered = true;
1725 return 0;
1726}
1727
1728static void be_irq_unregister(struct be_adapter *adapter)
1729{
1730 struct net_device *netdev = adapter->netdev;
6b7c5b94
SP		 1731
1732 if (!adapter->isr_registered)
1733 return;
1734
1735 /* INTx */
1736 if (!adapter->msix_enabled) {
1737 free_irq(netdev->irq, adapter);
1738 goto done;
1739 }
1740
1741 /* MSIx */
b628bde2
SP		 1742 be_free_irq(adapter, &adapter->tx_eq);
1743 be_free_irq(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1744done:
1745 adapter->isr_registered = false;
6b7c5b94
SP		 1746}
1747
889cd4b2
SP		 1748static int be_close(struct net_device *netdev)
1749{
1750 struct be_adapter *adapter = netdev_priv(netdev);
1751 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1752 struct be_eq_obj *tx_eq = &adapter->tx_eq;
1753 int vec;
1754
1755 cancel_delayed_work_sync(&adapter->work);
1756
1757 be_async_mcc_disable(adapter);
1758
1759 netif_stop_queue(netdev);
1760 netif_carrier_off(netdev);
1761 adapter->link_up = false;
1762
1763 be_intr_set(adapter, false);
1764
1765 if (adapter->msix_enabled) {
1766 vec = be_msix_vec_get(adapter, tx_eq->q.id);
1767 synchronize_irq(vec);
1768 vec = be_msix_vec_get(adapter, rx_eq->q.id);
1769 synchronize_irq(vec);
1770 } else {
1771 synchronize_irq(netdev->irq);
1772 }
1773 be_irq_unregister(adapter);
1774
1775 napi_disable(&rx_eq->napi);
1776 napi_disable(&tx_eq->napi);
1777
1778 /* Wait for all pending tx completions to arrive so that
1779 * all tx skbs are freed.
1780 */
1781 be_tx_compl_clean(adapter);
1782
1783 return 0;
1784}
1785
6b7c5b94
SP		 1786static int be_open(struct net_device *netdev)
1787{
1788 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1789 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1790 struct be_eq_obj *tx_eq = &adapter->tx_eq;
a8f447bd
SP		 1791 bool link_up;
1792 int status;
0388f251
SB		 1793 u8 mac_speed;
1794 u16 link_speed;
5fb379ee
SP		 1795
1796 /* First time posting */
1797 be_post_rx_frags(adapter);
1798
1799 napi_enable(&rx_eq->napi);
1800 napi_enable(&tx_eq->napi);
1801
1802 be_irq_register(adapter);
1803
8788fdc2 1804 be_intr_set(adapter, true);
5fb379ee
SP		 1805
1806 /* The evt queues are created in unarmed state; arm them */
8788fdc2
SP		 1807 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
1808 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee
SP		 1809
1810 /* Rx compl queue may be in unarmed state; rearm it */
8788fdc2 1811 be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
5fb379ee 1812
7a1e9b20
SP		 1813 /* Now that interrupts are on we can process async mcc */
1814 be_async_mcc_enable(adapter);
1815
889cd4b2
SP		 1816 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
1817
0388f251
SB		 1818 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
1819 &link_speed);
a8f447bd 1820 if (status)
889cd4b2 1821 goto err;
a8f447bd 1822 be_link_status_update(adapter, link_up);
5fb379ee 1823
889cd4b2 1824 if (be_physfn(adapter)) {
ba343c77 1825 status = be_vid_config(adapter);
889cd4b2
SP		 1826 if (status)
1827 goto err;
4f2aa89c 1828
ba343c77
SB		 1829 status = be_cmd_set_flow_control(adapter,
1830 adapter->tx_fc, adapter->rx_fc);
1831 if (status)
889cd4b2 1832 goto err;
ba343c77 1833 }
4f2aa89c 1834
889cd4b2
SP		 1835 return 0;
1836err:
1837 be_close(adapter->netdev);
1838 return -EIO;
5fb379ee
SP		 1839}
1840
71d8d1b5
AK		 1841static int be_setup_wol(struct be_adapter *adapter, bool enable)
1842{
1843 struct be_dma_mem cmd;
1844 int status = 0;
1845 u8 mac[ETH_ALEN];
1846
1847 memset(mac, 0, ETH_ALEN);
1848
1849 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
1850 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
1851 if (cmd.va == NULL)
1852 return -1;
1853 memset(cmd.va, 0, cmd.size);
1854
1855 if (enable) {
1856 status = pci_write_config_dword(adapter->pdev,
1857 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
1858 if (status) {
1859 dev_err(&adapter->pdev->dev,
2381a55c 1860 "Could not enable Wake-on-lan\n");
71d8d1b5
AK		 1861 pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
1862 cmd.dma);
1863 return status;
1864 }
1865 status = be_cmd_enable_magic_wol(adapter,
1866 adapter->netdev->dev_addr, &cmd);
1867 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
1868 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
1869 } else {
1870 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
1871 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
1872 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
1873 }
1874
1875 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
1876 return status;
1877}
1878
5fb379ee
SP		 1879static int be_setup(struct be_adapter *adapter)
1880{
5fb379ee 1881 struct net_device *netdev = adapter->netdev;
ba343c77 1882 u32 cap_flags, en_flags, vf = 0;
6b7c5b94 1883 int status;
ba343c77
SB		 1884 u8 mac[ETH_ALEN];
1885
1886 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
6b7c5b94 1887
ba343c77
SB		 1888 if (be_physfn(adapter)) {
1889 cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
1890 BE_IF_FLAGS_PROMISCUOUS |
1891 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1892 en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
1893 }
73d540f2
SP		 1894
1895 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1896 netdev->dev_addr, false/* pmac_invalid */,
ba343c77 1897 &adapter->if_handle, &adapter->pmac_id, 0);
6b7c5b94
SP		 1898 if (status != 0)
1899 goto do_none;
1900
ba343c77
SB		 1901 if (be_physfn(adapter)) {
1902 while (vf < num_vfs) {
1903 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED
1904 | BE_IF_FLAGS_BROADCAST;
1905 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1906 mac, true, &adapter->vf_if_handle[vf],
1907 NULL, vf+1);
1908 if (status) {
1909 dev_err(&adapter->pdev->dev,
1910 "Interface Create failed for VF %d\n", vf);
1911 goto if_destroy;
1912 }
1913 vf++;
84e5b9f7 1914 }
ba343c77
SB		 1915 } else if (!be_physfn(adapter)) {
1916 status = be_cmd_mac_addr_query(adapter, mac,
1917 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
1918 if (!status) {
1919 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
1920 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
1921 }
1922 }
1923
6b7c5b94
SP		 1924 status = be_tx_queues_create(adapter);
1925 if (status != 0)
1926 goto if_destroy;
1927
1928 status = be_rx_queues_create(adapter);
1929 if (status != 0)
1930 goto tx_qs_destroy;
1931
5fb379ee
SP		 1932 status = be_mcc_queues_create(adapter);
1933 if (status != 0)
1934 goto rx_qs_destroy;
6b7c5b94 1935
0dffc83e
AK		 1936 adapter->link_speed = -1;
1937
6b7c5b94
SP		 1938 return 0;
1939
5fb379ee
SP		 1940rx_qs_destroy:
1941 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 1942tx_qs_destroy:
1943 be_tx_queues_destroy(adapter);
1944if_destroy:
ba343c77
SB		 1945 for (vf = 0; vf < num_vfs; vf++)
1946 if (adapter->vf_if_handle[vf])
1947 be_cmd_if_destroy(adapter, adapter->vf_if_handle[vf]);
8788fdc2 1948 be_cmd_if_destroy(adapter, adapter->if_handle);
6b7c5b94
SP		 1949do_none:
1950 return status;
1951}
1952
5fb379ee
SP		 1953static int be_clear(struct be_adapter *adapter)
1954{
1a8887d8 1955 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 1956 be_rx_queues_destroy(adapter);
1957 be_tx_queues_destroy(adapter);
1958
8788fdc2 1959 be_cmd_if_destroy(adapter, adapter->if_handle);
5fb379ee 1960
2243e2e9
SP		 1961 /* tell fw we're done with firing cmds */
1962 be_cmd_fw_clean(adapter);
5fb379ee
SP		 1963 return 0;
1964}
1965
6b7c5b94 1966
84517482
AK		 1967#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
1968char flash_cookie[2][16] = {"*** SE FLAS",
1969 "H DIRECTORY *** "};
fa9a6fed
SB		 1970
1971static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 1972 const u8 *p, u32 img_start, int image_size,
1973 int hdr_size)
fa9a6fed
SB		 1974{
1975 u32 crc_offset;
1976 u8 flashed_crc[4];
1977 int status;
3f0d4560
AK		 1978
1979 crc_offset = hdr_size + img_start + image_size - 4;
1980
fa9a6fed 1981 p += crc_offset;
3f0d4560
AK		 1982
1983 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 1984 (image_size - 4));
fa9a6fed
SB		 1985 if (status) {
1986 dev_err(&adapter->pdev->dev,
1987 "could not get crc from flash, not flashing redboot\n");
1988 return false;
1989 }
1990
1991 /*update redboot only if crc does not match*/
1992 if (!memcmp(flashed_crc, p, 4))
1993 return false;
1994 else
1995 return true;
fa9a6fed
SB		 1996}
1997
3f0d4560 1998static int be_flash_data(struct be_adapter *adapter,
84517482 1999 const struct firmware *fw,
3f0d4560
AK		 2000 struct be_dma_mem *flash_cmd, int num_of_images)
2001
84517482 2002{
3f0d4560
AK		 2003 int status = 0, i, filehdr_size = 0;
2004 u32 total_bytes = 0, flash_op;
84517482
AK		 2005 int num_bytes;
2006 const u8 *p = fw->data;
2007 struct be_cmd_write_flashrom *req = flash_cmd->va;
3f0d4560 2008 struct flash_comp *pflashcomp;
9fe96934 2009 int num_comp;
3f0d4560 2010
9fe96934 2011 struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 2012 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2013 FLASH_IMAGE_MAX_SIZE_g3},
2014 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2015 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2016 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2017 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2018 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2019 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2020 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2021 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2022 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2023 FLASH_IMAGE_MAX_SIZE_g3},
2024 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2025 FLASH_IMAGE_MAX_SIZE_g3},
2026 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 2027 FLASH_IMAGE_MAX_SIZE_g3},
2028 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
2029 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560
AK		 2030 };
2031 struct flash_comp gen2_flash_types[8] = {
2032 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2033 FLASH_IMAGE_MAX_SIZE_g2},
2034 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2035 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2036 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2037 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2038 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2039 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2040 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2041 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2042 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2043 FLASH_IMAGE_MAX_SIZE_g2},
2044 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2045 FLASH_IMAGE_MAX_SIZE_g2},
2046 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2047 FLASH_IMAGE_MAX_SIZE_g2}
2048 };
2049
2050 if (adapter->generation == BE_GEN3) {
2051 pflashcomp = gen3_flash_types;
2052 filehdr_size = sizeof(struct flash_file_hdr_g3);
9fe96934 2053 num_comp = 9;
3f0d4560
AK		 2054 } else {
2055 pflashcomp = gen2_flash_types;
2056 filehdr_size = sizeof(struct flash_file_hdr_g2);
9fe96934 2057 num_comp = 8;
84517482 2058 }
9fe96934
SB		 2059 for (i = 0; i < num_comp; i++) {
2060 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2061 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2062 continue;
3f0d4560
AK		 2063 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2064 (!be_flash_redboot(adapter, fw->data,
2065 pflashcomp[i].offset, pflashcomp[i].size,
2066 filehdr_size)))
2067 continue;
2068 p = fw->data;
2069 p += filehdr_size + pflashcomp[i].offset
2070 + (num_of_images * sizeof(struct image_hdr));
2071 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 2072 return -1;
3f0d4560
AK		 2073 total_bytes = pflashcomp[i].size;
2074 while (total_bytes) {
2075 if (total_bytes > 32*1024)
2076 num_bytes = 32*1024;
2077 else
2078 num_bytes = total_bytes;
2079 total_bytes -= num_bytes;
2080
2081 if (!total_bytes)
2082 flash_op = FLASHROM_OPER_FLASH;
2083 else
2084 flash_op = FLASHROM_OPER_SAVE;
2085 memcpy(req->params.data_buf, p, num_bytes);
2086 p += num_bytes;
2087 status = be_cmd_write_flashrom(adapter, flash_cmd,
2088 pflashcomp[i].optype, flash_op, num_bytes);
2089 if (status) {
2090 dev_err(&adapter->pdev->dev,
2091 "cmd to write to flash rom failed.\n");
2092 return -1;
2093 }
2094 yield();
84517482 2095 }
84517482 2096 }
84517482
AK		 2097 return 0;
2098}
2099
3f0d4560
AK		 2100static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2101{
2102 if (fhdr == NULL)
2103 return 0;
2104 if (fhdr->build[0] == '3')
2105 return BE_GEN3;
2106 else if (fhdr->build[0] == '2')
2107 return BE_GEN2;
2108 else
2109 return 0;
2110}
2111
84517482
AK		 2112int be_load_fw(struct be_adapter *adapter, u8 *func)
2113{
2114 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2115 const struct firmware *fw;
3f0d4560
AK		 2116 struct flash_file_hdr_g2 *fhdr;
2117 struct flash_file_hdr_g3 *fhdr3;
2118 struct image_hdr *img_hdr_ptr = NULL;
84517482 2119 struct be_dma_mem flash_cmd;
8b93b710 2120 int status, i = 0, num_imgs = 0;
84517482 2121 const u8 *p;
84517482 2122
84517482
AK		 2123 strcpy(fw_file, func);
2124
2125 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2126 if (status)
2127 goto fw_exit;
2128
2129 p = fw->data;
3f0d4560 2130 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2131 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2132
84517482
AK		 2133 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2134 flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
2135 &flash_cmd.dma);
2136 if (!flash_cmd.va) {
2137 status = -ENOMEM;
2138 dev_err(&adapter->pdev->dev,
2139 "Memory allocation failure while flashing\n");
2140 goto fw_exit;
2141 }
2142
3f0d4560
AK		 2143 if ((adapter->generation == BE_GEN3) &&
2144 (get_ufigen_type(fhdr) == BE_GEN3)) {
2145 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 2146 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2147 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 2148 img_hdr_ptr = (struct image_hdr *) (fw->data +
2149 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 2150 i * sizeof(struct image_hdr)));
2151 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2152 status = be_flash_data(adapter, fw, &flash_cmd,
2153 num_imgs);
3f0d4560
AK		 2154 }
2155 } else if ((adapter->generation == BE_GEN2) &&
2156 (get_ufigen_type(fhdr) == BE_GEN2)) {
2157 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2158 } else {
2159 dev_err(&adapter->pdev->dev,
2160 "UFI and Interface are not compatible for flashing\n");
2161 status = -1;
84517482
AK		 2162 }
2163
2164 pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
2165 flash_cmd.dma);
2166 if (status) {
2167 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2168 goto fw_exit;
2169 }
2170
af901ca1 2171 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2172
2173fw_exit:
2174 release_firmware(fw);
2175 return status;
2176}
2177
6b7c5b94
SP		 2178static struct net_device_ops be_netdev_ops = {
2179 .ndo_open = be_open,
2180 .ndo_stop = be_close,
2181 .ndo_start_xmit = be_xmit,
2182 .ndo_get_stats = be_get_stats,
2183 .ndo_set_rx_mode = be_set_multicast_list,
2184 .ndo_set_mac_address = be_mac_addr_set,
2185 .ndo_change_mtu = be_change_mtu,
2186 .ndo_validate_addr = eth_validate_addr,
2187 .ndo_vlan_rx_register = be_vlan_register,
2188 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2189 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
ba343c77 2190 .ndo_set_vf_mac = be_set_vf_mac
6b7c5b94
SP		 2191};
2192
2193static void be_netdev_init(struct net_device *netdev)
2194{
2195 struct be_adapter *adapter = netdev_priv(netdev);
2196
2197 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
583e3f34 2198 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
49e4b847 2199 NETIF_F_GRO | NETIF_F_TSO6;
6b7c5b94 2200
51c59870
AK		 2201 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
2202
6b7c5b94
SP		 2203 netdev->flags |= IFF_MULTICAST;
2204
728a9972
AK		 2205 adapter->rx_csum = true;
2206
9e90c961
AK		 2207 /* Default settings for Rx and Tx flow control */
2208 adapter->rx_fc = true;
2209 adapter->tx_fc = true;
2210
c190e3c8
AK		 2211 netif_set_gso_max_size(netdev, 65535);
2212
6b7c5b94
SP		 2213 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2214
2215 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2216
6b7c5b94
SP		 2217 netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
2218 BE_NAPI_WEIGHT);
5fb379ee 2219 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94
SP		 2220 BE_NAPI_WEIGHT);
2221
2222 netif_carrier_off(netdev);
2223 netif_stop_queue(netdev);
2224}
2225
2226static void be_unmap_pci_bars(struct be_adapter *adapter)
2227{
8788fdc2
SP		 2228 if (adapter->csr)
2229 iounmap(adapter->csr);
2230 if (adapter->db)
2231 iounmap(adapter->db);
ba343c77 2232 if (adapter->pcicfg && be_physfn(adapter))
8788fdc2 2233 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2234}
2235
2236static int be_map_pci_bars(struct be_adapter *adapter)
2237{
2238 u8 __iomem *addr;
ba343c77 2239 int pcicfg_reg, db_reg;
6b7c5b94 2240
ba343c77
SB		 2241 if (be_physfn(adapter)) {
2242 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2243 pci_resource_len(adapter->pdev, 2));
2244 if (addr == NULL)
2245 return -ENOMEM;
2246 adapter->csr = addr;
2247 }
6b7c5b94 2248
ba343c77 2249 if (adapter->generation == BE_GEN2) {
7b139c83 2250 pcicfg_reg = 1;
ba343c77
SB		 2251 db_reg = 4;
2252 } else {
7b139c83 2253 pcicfg_reg = 0;
ba343c77
SB		 2254 if (be_physfn(adapter))
2255 db_reg = 4;
2256 else
2257 db_reg = 0;
2258 }
2259 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
2260 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 2261 if (addr == NULL)
2262 goto pci_map_err;
ba343c77
SB		 2263 adapter->db = addr;
2264
2265 if (be_physfn(adapter)) {
2266 addr = ioremap_nocache(
2267 pci_resource_start(adapter->pdev, pcicfg_reg),
2268 pci_resource_len(adapter->pdev, pcicfg_reg));
2269 if (addr == NULL)
2270 goto pci_map_err;
2271 adapter->pcicfg = addr;
2272 } else
2273 adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
6b7c5b94
SP		 2274
2275 return 0;
2276pci_map_err:
2277 be_unmap_pci_bars(adapter);
2278 return -ENOMEM;
2279}
2280
2281
2282static void be_ctrl_cleanup(struct be_adapter *adapter)
2283{
8788fdc2 2284 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2285
2286 be_unmap_pci_bars(adapter);
2287
2288 if (mem->va)
2289 pci_free_consistent(adapter->pdev, mem->size,
2290 mem->va, mem->dma);
e7b909a6
SP		 2291
2292 mem = &adapter->mc_cmd_mem;
2293 if (mem->va)
2294 pci_free_consistent(adapter->pdev, mem->size,
2295 mem->va, mem->dma);
6b7c5b94
SP		 2296}
2297
6b7c5b94
SP		 2298static int be_ctrl_init(struct be_adapter *adapter)
2299{
8788fdc2
SP		 2300 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2301 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2302 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2303 int status;
6b7c5b94
SP		 2304
2305 status = be_map_pci_bars(adapter);
2306 if (status)
e7b909a6 2307 goto done;
6b7c5b94
SP		 2308
2309 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2310 mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
2311 mbox_mem_alloc->size, &mbox_mem_alloc->dma);
2312 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2313 status = -ENOMEM;
2314 goto unmap_pci_bars;
6b7c5b94 2315 }
e7b909a6 2316
6b7c5b94
SP		 2317 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2318 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2319 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2320 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2321
2322 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2323 mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
2324 &mc_cmd_mem->dma);
2325 if (mc_cmd_mem->va == NULL) {
2326 status = -ENOMEM;
2327 goto free_mbox;
2328 }
2329 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2330
8788fdc2
SP		 2331 spin_lock_init(&adapter->mbox_lock);
2332 spin_lock_init(&adapter->mcc_lock);
2333 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2334
dd131e76 2335 init_completion(&adapter->flash_compl);
cf588477 2336 pci_save_state(adapter->pdev);
6b7c5b94 2337 return 0;
e7b909a6
SP		 2338
2339free_mbox:
2340 pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
2341 mbox_mem_alloc->va, mbox_mem_alloc->dma);
2342
2343unmap_pci_bars:
2344 be_unmap_pci_bars(adapter);
2345
2346done:
2347 return status;
6b7c5b94
SP		 2348}
2349
2350static void be_stats_cleanup(struct be_adapter *adapter)
2351{
2352 struct be_stats_obj *stats = &adapter->stats;
2353 struct be_dma_mem *cmd = &stats->cmd;
2354
2355 if (cmd->va)
2356 pci_free_consistent(adapter->pdev, cmd->size,
2357 cmd->va, cmd->dma);
2358}
2359
2360static int be_stats_init(struct be_adapter *adapter)
2361{
2362 struct be_stats_obj *stats = &adapter->stats;
2363 struct be_dma_mem *cmd = &stats->cmd;
2364
2365 cmd->size = sizeof(struct be_cmd_req_get_stats);
2366 cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
2367 if (cmd->va == NULL)
2368 return -1;
d291b9af 2369 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2370 return 0;
2371}
2372
2373static void __devexit be_remove(struct pci_dev *pdev)
2374{
2375 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2376
6b7c5b94
SP		 2377 if (!adapter)
2378 return;
2379
2380 unregister_netdev(adapter->netdev);
2381
5fb379ee
SP		 2382 be_clear(adapter);
2383
6b7c5b94
SP		 2384 be_stats_cleanup(adapter);
2385
2386 be_ctrl_cleanup(adapter);
2387
ba343c77
SB		 2388 be_sriov_disable(adapter);
2389
8d56ff11 2390 be_msix_disable(adapter);
6b7c5b94
SP		 2391
2392 pci_set_drvdata(pdev, NULL);
2393 pci_release_regions(pdev);
2394 pci_disable_device(pdev);
2395
2396 free_netdev(adapter->netdev);
2397}
2398
2243e2e9 2399static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2400{
6b7c5b94 2401 int status;
2243e2e9 2402 u8 mac[ETH_ALEN];
6b7c5b94 2403
2243e2e9 2404 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2405 if (status)
2406 return status;
2407
2243e2e9
SP		 2408 status = be_cmd_query_fw_cfg(adapter,
2409 &adapter->port_num, &adapter->cap);
43a04fdc
SP		 2410 if (status)
2411 return status;
2412
2243e2e9 2413 memset(mac, 0, ETH_ALEN);
ba343c77
SB		 2414
2415 if (be_physfn(adapter)) {
2416 status = be_cmd_mac_addr_query(adapter, mac,
2243e2e9 2417 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
ca9e4988 2418
ba343c77
SB		 2419 if (status)
2420 return status;
ca9e4988 2421
ba343c77
SB		 2422 if (!is_valid_ether_addr(mac))
2423 return -EADDRNOTAVAIL;
2424
2425 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2426 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2427 }
6b7c5b94 2428
82903e4b
AK		 2429 if (adapter->cap & 0x400)
2430 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2431 else
2432 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2433
2243e2e9 2434 return 0;
6b7c5b94
SP		 2435}
2436
2437static int __devinit be_probe(struct pci_dev *pdev,
2438 const struct pci_device_id *pdev_id)
2439{
2440 int status = 0;
2441 struct be_adapter *adapter;
2442 struct net_device *netdev;
6b7c5b94 2443
ba343c77 2444
6b7c5b94
SP		 2445 status = pci_enable_device(pdev);
2446 if (status)
2447 goto do_none;
2448
2449 status = pci_request_regions(pdev, DRV_NAME);
2450 if (status)
2451 goto disable_dev;
2452 pci_set_master(pdev);
2453
2454 netdev = alloc_etherdev(sizeof(struct be_adapter));
2455 if (netdev == NULL) {
2456 status = -ENOMEM;
2457 goto rel_reg;
2458 }
2459 adapter = netdev_priv(netdev);
7b139c83
AK		 2460
2461 switch (pdev->device) {
2462 case BE_DEVICE_ID1:
2463 case OC_DEVICE_ID1:
2464 adapter->generation = BE_GEN2;
2465 break;
2466 case BE_DEVICE_ID2:
2467 case OC_DEVICE_ID2:
2468 adapter->generation = BE_GEN3;
2469 break;
2470 default:
2471 adapter->generation = 0;
2472 }
2473
6b7c5b94
SP		 2474 adapter->pdev = pdev;
2475 pci_set_drvdata(pdev, adapter);
2476 adapter->netdev = netdev;
2243e2e9
SP		 2477 be_netdev_init(netdev);
2478 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94
SP		 2479
2480 be_msix_enable(adapter);
2481
e930438c 2482 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2483 if (!status) {
2484 netdev->features |= NETIF_F_HIGHDMA;
2485 } else {
e930438c 2486 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2487 if (status) {
2488 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2489 goto free_netdev;
2490 }
2491 }
2492
ba343c77
SB		 2493 be_sriov_enable(adapter);
2494
6b7c5b94
SP		 2495 status = be_ctrl_init(adapter);
2496 if (status)
2497 goto free_netdev;
2498
2243e2e9 2499 /* sync up with fw's ready state */
ba343c77
SB		 2500 if (be_physfn(adapter)) {
2501 status = be_cmd_POST(adapter);
2502 if (status)
2503 goto ctrl_clean;
ba343c77 2504 }
6b7c5b94 2505
2243e2e9
SP		 2506 /* tell fw we're ready to fire cmds */
2507 status = be_cmd_fw_init(adapter);
6b7c5b94 2508 if (status)
2243e2e9
SP		 2509 goto ctrl_clean;
2510
556ae191
SB		 2511 if (be_physfn(adapter)) {
2512 status = be_cmd_reset_function(adapter);
2513 if (status)
2514 goto ctrl_clean;
2515 }
2516
2243e2e9
SP		 2517 status = be_stats_init(adapter);
2518 if (status)
2519 goto ctrl_clean;
2520
2521 status = be_get_config(adapter);
6b7c5b94
SP		 2522 if (status)
2523 goto stats_clean;
6b7c5b94
SP		 2524
2525 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 2526
5fb379ee
SP		 2527 status = be_setup(adapter);
2528 if (status)
2529 goto stats_clean;
2243e2e9 2530
6b7c5b94
SP		 2531 status = register_netdev(netdev);
2532 if (status != 0)
5fb379ee 2533 goto unsetup;
6b7c5b94 2534
c4ca2374 2535 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
6b7c5b94
SP		 2536 return 0;
2537
5fb379ee
SP		 2538unsetup:
2539 be_clear(adapter);
6b7c5b94
SP		 2540stats_clean:
2541 be_stats_cleanup(adapter);
2542ctrl_clean:
2543 be_ctrl_cleanup(adapter);
2544free_netdev:
8d56ff11 2545 be_msix_disable(adapter);
ba343c77 2546 be_sriov_disable(adapter);
6b7c5b94 2547 free_netdev(adapter->netdev);
8d56ff11 2548 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 2549rel_reg:
2550 pci_release_regions(pdev);
2551disable_dev:
2552 pci_disable_device(pdev);
2553do_none:
c4ca2374 2554 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 2555 return status;
2556}
2557
2558static int be_suspend(struct pci_dev *pdev, pm_message_t state)
2559{
2560 struct be_adapter *adapter = pci_get_drvdata(pdev);
2561 struct net_device *netdev = adapter->netdev;
2562
71d8d1b5
AK		 2563 if (adapter->wol)
2564 be_setup_wol(adapter, true);
2565
6b7c5b94
SP		 2566 netif_device_detach(netdev);
2567 if (netif_running(netdev)) {
2568 rtnl_lock();
2569 be_close(netdev);
2570 rtnl_unlock();
2571 }
9e90c961 2572 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 2573 be_clear(adapter);
6b7c5b94
SP		 2574
2575 pci_save_state(pdev);
2576 pci_disable_device(pdev);
2577 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2578 return 0;
2579}
2580
2581static int be_resume(struct pci_dev *pdev)
2582{
2583 int status = 0;
2584 struct be_adapter *adapter = pci_get_drvdata(pdev);
2585 struct net_device *netdev = adapter->netdev;
2586
2587 netif_device_detach(netdev);
2588
2589 status = pci_enable_device(pdev);
2590 if (status)
2591 return status;
2592
2593 pci_set_power_state(pdev, 0);
2594 pci_restore_state(pdev);
2595
2243e2e9
SP		 2596 /* tell fw we're ready to fire cmds */
2597 status = be_cmd_fw_init(adapter);
2598 if (status)
2599 return status;
2600
9b0365f1 2601 be_setup(adapter);
6b7c5b94
SP		 2602 if (netif_running(netdev)) {
2603 rtnl_lock();
2604 be_open(netdev);
2605 rtnl_unlock();
2606 }
2607 netif_device_attach(netdev);
71d8d1b5
AK		 2608
2609 if (adapter->wol)
2610 be_setup_wol(adapter, false);
6b7c5b94
SP		 2611 return 0;
2612}
2613
82456b03
SP		 2614/*
2615 * An FLR will stop BE from DMAing any data.
2616 */
2617static void be_shutdown(struct pci_dev *pdev)
2618{
2619 struct be_adapter *adapter = pci_get_drvdata(pdev);
2620 struct net_device *netdev = adapter->netdev;
2621
2622 netif_device_detach(netdev);
2623
2624 be_cmd_reset_function(adapter);
2625
2626 if (adapter->wol)
2627 be_setup_wol(adapter, true);
2628
2629 pci_disable_device(pdev);
82456b03
SP		 2630}
2631
cf588477
SP		 2632static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
2633 pci_channel_state_t state)
2634{
2635 struct be_adapter *adapter = pci_get_drvdata(pdev);
2636 struct net_device *netdev = adapter->netdev;
2637
2638 dev_err(&adapter->pdev->dev, "EEH error detected\n");
2639
2640 adapter->eeh_err = true;
2641
2642 netif_device_detach(netdev);
2643
2644 if (netif_running(netdev)) {
2645 rtnl_lock();
2646 be_close(netdev);
2647 rtnl_unlock();
2648 }
2649 be_clear(adapter);
2650
2651 if (state == pci_channel_io_perm_failure)
2652 return PCI_ERS_RESULT_DISCONNECT;
2653
2654 pci_disable_device(pdev);
2655
2656 return PCI_ERS_RESULT_NEED_RESET;
2657}
2658
2659static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
2660{
2661 struct be_adapter *adapter = pci_get_drvdata(pdev);
2662 int status;
2663
2664 dev_info(&adapter->pdev->dev, "EEH reset\n");
2665 adapter->eeh_err = false;
2666
2667 status = pci_enable_device(pdev);
2668 if (status)
2669 return PCI_ERS_RESULT_DISCONNECT;
2670
2671 pci_set_master(pdev);
2672 pci_set_power_state(pdev, 0);
2673 pci_restore_state(pdev);
2674
2675 /* Check if card is ok and fw is ready */
2676 status = be_cmd_POST(adapter);
2677 if (status)
2678 return PCI_ERS_RESULT_DISCONNECT;
2679
2680 return PCI_ERS_RESULT_RECOVERED;
2681}
2682
2683static void be_eeh_resume(struct pci_dev *pdev)
2684{
2685 int status = 0;
2686 struct be_adapter *adapter = pci_get_drvdata(pdev);
2687 struct net_device *netdev = adapter->netdev;
2688
2689 dev_info(&adapter->pdev->dev, "EEH resume\n");
2690
2691 pci_save_state(pdev);
2692
2693 /* tell fw we're ready to fire cmds */
2694 status = be_cmd_fw_init(adapter);
2695 if (status)
2696 goto err;
2697
2698 status = be_setup(adapter);
2699 if (status)
2700 goto err;
2701
2702 if (netif_running(netdev)) {
2703 status = be_open(netdev);
2704 if (status)
2705 goto err;
2706 }
2707 netif_device_attach(netdev);
2708 return;
2709err:
2710 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 2711}
2712
2713static struct pci_error_handlers be_eeh_handlers = {
2714 .error_detected = be_eeh_err_detected,
2715 .slot_reset = be_eeh_reset,
2716 .resume = be_eeh_resume,
2717};
2718
6b7c5b94
SP		 2719static struct pci_driver be_driver = {
2720 .name = DRV_NAME,
2721 .id_table = be_dev_ids,
2722 .probe = be_probe,
2723 .remove = be_remove,
2724 .suspend = be_suspend,
cf588477 2725 .resume = be_resume,
82456b03 2726 .shutdown = be_shutdown,
cf588477 2727 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 2728};
2729
2730static int __init be_init_module(void)
2731{
8e95a202
JP		 2732 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
2733 rx_frag_size != 2048) {
6b7c5b94
SP		 2734 printk(KERN_WARNING DRV_NAME
2735 " : Module param rx_frag_size must be 2048/4096/8192."
2736 " Using 2048\n");
2737 rx_frag_size = 2048;
2738 }
6b7c5b94 2739
ba343c77
SB		 2740 if (num_vfs > 32) {
2741 printk(KERN_WARNING DRV_NAME
2742 " : Module param num_vfs must not be greater than 32."
2743 "Using 32\n");
2744 num_vfs = 32;
2745 }
2746
6b7c5b94
SP		 2747 return pci_register_driver(&be_driver);
2748}
2749module_init(be_init_module);
2750
2751static void __exit be_exit_module(void)
2752{
2753 pci_unregister_driver(&be_driver);
2754}
2755module_exit(be_exit_module);
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