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[net-next-2.6.git] / drivers / net / benet / be_main.c
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6b7c5b94 1/*
294aedcf 2 * Copyright (C) 2005 - 2010 ServerEngines
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#include "be.h"
8788fdc2 19#include "be_cmds.h"
65f71b8b 20#include <asm/div64.h>
6b7c5b94
SP		 21
22MODULE_VERSION(DRV_VER);
23MODULE_DEVICE_TABLE(pci, be_dev_ids);
24MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25MODULE_AUTHOR("ServerEngines Corporation");
26MODULE_LICENSE("GPL");
27
28static unsigned int rx_frag_size = 2048;
ba343c77 29static unsigned int num_vfs;
6b7c5b94 30module_param(rx_frag_size, uint, S_IRUGO);
ba343c77 31module_param(num_vfs, uint, S_IRUGO);
6b7c5b94 32MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
ba343c77 33MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
6b7c5b94 34
6b7c5b94 35static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
c4ca2374 36 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
59fd5d87 37 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
c4ca2374
AK		 38 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
39 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
6b7c5b94
SP		 40 { 0 }
41};
42MODULE_DEVICE_TABLE(pci, be_dev_ids);
43
44static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
45{
46 struct be_dma_mem *mem = &q->dma_mem;
47 if (mem->va)
48 pci_free_consistent(adapter->pdev, mem->size,
49 mem->va, mem->dma);
50}
51
52static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
53 u16 len, u16 entry_size)
54{
55 struct be_dma_mem *mem = &q->dma_mem;
56
57 memset(q, 0, sizeof(*q));
58 q->len = len;
59 q->entry_size = entry_size;
60 mem->size = len * entry_size;
61 mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
62 if (!mem->va)
63 return -1;
64 memset(mem->va, 0, mem->size);
65 return 0;
66}
67
8788fdc2 68static void be_intr_set(struct be_adapter *adapter, bool enable)
6b7c5b94 69{
8788fdc2 70 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
6b7c5b94
SP		 71 u32 reg = ioread32(addr);
72 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 73
cf588477
SP		 74 if (adapter->eeh_err)
75 return;
76
5f0b849e 77 if (!enabled && enable)
6b7c5b94 78 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 79 else if (enabled && !enable)
6b7c5b94 80 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
5f0b849e 81 else
6b7c5b94 82 return;
5f0b849e 83
6b7c5b94
SP		 84 iowrite32(reg, addr);
85}
86
8788fdc2 87static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 88{
89 u32 val = 0;
90 val |= qid & DB_RQ_RING_ID_MASK;
91 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
f3eb62d2
SP		 92
93 wmb();
8788fdc2 94 iowrite32(val, adapter->db + DB_RQ_OFFSET);
6b7c5b94
SP		 95}
96
8788fdc2 97static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
6b7c5b94
SP		 98{
99 u32 val = 0;
100 val |= qid & DB_TXULP_RING_ID_MASK;
101 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
f3eb62d2
SP		 102
103 wmb();
8788fdc2 104 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
6b7c5b94
SP		 105}
106
8788fdc2 107static void be_eq_notify(struct be_adapter *adapter, u16 qid,
6b7c5b94
SP		 108 bool arm, bool clear_int, u16 num_popped)
109{
110 u32 val = 0;
111 val |= qid & DB_EQ_RING_ID_MASK;
cf588477
SP		 112
113 if (adapter->eeh_err)
114 return;
115
6b7c5b94
SP		 116 if (arm)
117 val |= 1 << DB_EQ_REARM_SHIFT;
118 if (clear_int)
119 val |= 1 << DB_EQ_CLR_SHIFT;
120 val |= 1 << DB_EQ_EVNT_SHIFT;
121 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
8788fdc2 122 iowrite32(val, adapter->db + DB_EQ_OFFSET);
6b7c5b94
SP		 123}
124
8788fdc2 125void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
6b7c5b94
SP		 126{
127 u32 val = 0;
128 val |= qid & DB_CQ_RING_ID_MASK;
cf588477
SP		 129
130 if (adapter->eeh_err)
131 return;
132
6b7c5b94
SP		 133 if (arm)
134 val |= 1 << DB_CQ_REARM_SHIFT;
135 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
8788fdc2 136 iowrite32(val, adapter->db + DB_CQ_OFFSET);
6b7c5b94
SP		 137}
138
6b7c5b94
SP		 139static int be_mac_addr_set(struct net_device *netdev, void *p)
140{
141 struct be_adapter *adapter = netdev_priv(netdev);
142 struct sockaddr *addr = p;
143 int status = 0;
144
ca9e4988
AK		 145 if (!is_valid_ether_addr(addr->sa_data))
146 return -EADDRNOTAVAIL;
147
ba343c77
SB		 148 /* MAC addr configuration will be done in hardware for VFs
149 * by their corresponding PFs. Just copy to netdev addr here
150 */
151 if (!be_physfn(adapter))
152 goto netdev_addr;
153
a65027e4
SP		 154 status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
155 if (status)
156 return status;
6b7c5b94 157
a65027e4
SP		 158 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
159 adapter->if_handle, &adapter->pmac_id);
ba343c77 160netdev_addr:
6b7c5b94
SP		 161 if (!status)
162 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
163
164 return status;
165}
166
b31c50a7 167void netdev_stats_update(struct be_adapter *adapter)
6b7c5b94
SP		 168{
169 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
170 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
171 struct be_port_rxf_stats *port_stats =
172 &rxf_stats->port[adapter->port_num];
78122a52 173 struct net_device_stats *dev_stats = &adapter->netdev->stats;
68110868 174 struct be_erx_stats *erx_stats = &hw_stats->erx;
6b7c5b94 175
91992e44
AK		 176 dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
177 dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
178 dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
179 dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
6b7c5b94
SP		 180
181 /* bad pkts received */
182 dev_stats->rx_errors = port_stats->rx_crc_errors +
183 port_stats->rx_alignment_symbol_errors +
184 port_stats->rx_in_range_errors +
68110868
SP		 185 port_stats->rx_out_range_errors +
186 port_stats->rx_frame_too_long +
187 port_stats->rx_dropped_too_small +
188 port_stats->rx_dropped_too_short +
189 port_stats->rx_dropped_header_too_small +
190 port_stats->rx_dropped_tcp_length +
191 port_stats->rx_dropped_runt +
192 port_stats->rx_tcp_checksum_errs +
193 port_stats->rx_ip_checksum_errs +
194 port_stats->rx_udp_checksum_errs;
195
196 /* no space in linux buffers: best possible approximation */
01ed30da
SP		 197 dev_stats->rx_dropped =
198 erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
6b7c5b94
SP		 199
200 /* detailed rx errors */
201 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
68110868
SP		 202 port_stats->rx_out_range_errors +
203 port_stats->rx_frame_too_long;
204
6b7c5b94
SP		 205 /* receive ring buffer overflow */
206 dev_stats->rx_over_errors = 0;
68110868 207
6b7c5b94
SP		 208 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
209
210 /* frame alignment errors */
211 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
68110868 212
6b7c5b94
SP		 213 /* receiver fifo overrun */
214 /* drops_no_pbuf is no per i/f, it's per BE card */
215 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
216 port_stats->rx_input_fifo_overflow +
217 rxf_stats->rx_drops_no_pbuf;
218 /* receiver missed packetd */
219 dev_stats->rx_missed_errors = 0;
68110868
SP		 220
221 /* packet transmit problems */
222 dev_stats->tx_errors = 0;
223
224 /* no space available in linux */
225 dev_stats->tx_dropped = 0;
226
c5b9b92e 227 dev_stats->multicast = port_stats->rx_multicast_frames;
68110868
SP		 228 dev_stats->collisions = 0;
229
6b7c5b94
SP		 230 /* detailed tx_errors */
231 dev_stats->tx_aborted_errors = 0;
232 dev_stats->tx_carrier_errors = 0;
233 dev_stats->tx_fifo_errors = 0;
234 dev_stats->tx_heartbeat_errors = 0;
235 dev_stats->tx_window_errors = 0;
236}
237
8788fdc2 238void be_link_status_update(struct be_adapter *adapter, bool link_up)
6b7c5b94 239{
6b7c5b94
SP		 240 struct net_device *netdev = adapter->netdev;
241
6b7c5b94 242 /* If link came up or went down */
a8f447bd 243 if (adapter->link_up != link_up) {
0dffc83e 244 adapter->link_speed = -1;
a8f447bd 245 if (link_up) {
6b7c5b94
SP		 246 netif_start_queue(netdev);
247 netif_carrier_on(netdev);
248 printk(KERN_INFO "%s: Link up\n", netdev->name);
a8f447bd
SP		 249 } else {
250 netif_stop_queue(netdev);
251 netif_carrier_off(netdev);
252 printk(KERN_INFO "%s: Link down\n", netdev->name);
6b7c5b94 253 }
a8f447bd 254 adapter->link_up = link_up;
6b7c5b94 255 }
6b7c5b94
SP		 256}
257
258/* Update the EQ delay n BE based on the RX frags consumed / sec */
259static void be_rx_eqd_update(struct be_adapter *adapter)
260{
6b7c5b94
SP		 261 struct be_eq_obj *rx_eq = &adapter->rx_eq;
262 struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
4097f663
SP		 263 ulong now = jiffies;
264 u32 eqd;
265
266 if (!rx_eq->enable_aic)
267 return;
268
269 /* Wrapped around */
270 if (time_before(now, stats->rx_fps_jiffies)) {
271 stats->rx_fps_jiffies = now;
272 return;
273 }
6b7c5b94
SP		 274
275 /* Update once a second */
4097f663 276 if ((now - stats->rx_fps_jiffies) < HZ)
6b7c5b94
SP		 277 return;
278
279 stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
4097f663 280 ((now - stats->rx_fps_jiffies) / HZ);
6b7c5b94 281
4097f663 282 stats->rx_fps_jiffies = now;
6b7c5b94
SP		 283 stats->be_prev_rx_frags = stats->be_rx_frags;
284 eqd = stats->be_rx_fps / 110000;
285 eqd = eqd << 3;
286 if (eqd > rx_eq->max_eqd)
287 eqd = rx_eq->max_eqd;
288 if (eqd < rx_eq->min_eqd)
289 eqd = rx_eq->min_eqd;
290 if (eqd < 10)
291 eqd = 0;
292 if (eqd != rx_eq->cur_eqd)
8788fdc2 293 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
6b7c5b94
SP		 294
295 rx_eq->cur_eqd = eqd;
296}
297
6b7c5b94
SP		 298static struct net_device_stats *be_get_stats(struct net_device *dev)
299{
78122a52 300 return &dev->stats;
6b7c5b94
SP		 301}
302
65f71b8b
SH		 303static u32 be_calc_rate(u64 bytes, unsigned long ticks)
304{
305 u64 rate = bytes;
306
307 do_div(rate, ticks / HZ);
308 rate <<= 3; /* bytes/sec -> bits/sec */
309 do_div(rate, 1000000ul); /* MB/Sec */
310
311 return rate;
312}
313
4097f663
SP		 314static void be_tx_rate_update(struct be_adapter *adapter)
315{
316 struct be_drvr_stats *stats = drvr_stats(adapter);
317 ulong now = jiffies;
318
319 /* Wrapped around? */
320 if (time_before(now, stats->be_tx_jiffies)) {
321 stats->be_tx_jiffies = now;
322 return;
323 }
324
325 /* Update tx rate once in two seconds */
326 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
65f71b8b
SH		 327 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
328 - stats->be_tx_bytes_prev,
329 now - stats->be_tx_jiffies);
4097f663
SP		 330 stats->be_tx_jiffies = now;
331 stats->be_tx_bytes_prev = stats->be_tx_bytes;
332 }
333}
334
6b7c5b94 335static void be_tx_stats_update(struct be_adapter *adapter,
91992e44 336 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
6b7c5b94 337{
4097f663 338 struct be_drvr_stats *stats = drvr_stats(adapter);
6b7c5b94
SP		 339 stats->be_tx_reqs++;
340 stats->be_tx_wrbs += wrb_cnt;
341 stats->be_tx_bytes += copied;
91992e44 342 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
6b7c5b94
SP		 343 if (stopped)
344 stats->be_tx_stops++;
6b7c5b94
SP		 345}
346
347/* Determine number of WRB entries needed to xmit data in an skb */
348static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
349{
ebc8d2ab
DM		 350 int cnt = (skb->len > skb->data_len);
351
352 cnt += skb_shinfo(skb)->nr_frags;
353
6b7c5b94
SP		 354 /* to account for hdr wrb */
355 cnt++;
356 if (cnt & 1) {
357 /* add a dummy to make it an even num */
358 cnt++;
359 *dummy = true;
360 } else
361 *dummy = false;
362 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
363 return cnt;
364}
365
366static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
367{
368 wrb->frag_pa_hi = upper_32_bits(addr);
369 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
370 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
371}
372
373static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
374 bool vlan, u32 wrb_cnt, u32 len)
375{
376 memset(hdr, 0, sizeof(*hdr));
377
378 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
379
49e4b847 380 if (skb_is_gso(skb)) {
6b7c5b94
SP		 381 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
382 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
383 hdr, skb_shinfo(skb)->gso_size);
49e4b847
AK		 384 if (skb_is_gso_v6(skb))
385 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
6b7c5b94
SP		 386 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
387 if (is_tcp_pkt(skb))
388 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
389 else if (is_udp_pkt(skb))
390 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
391 }
392
393 if (vlan && vlan_tx_tag_present(skb)) {
394 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
395 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
396 hdr, vlan_tx_tag_get(skb));
397 }
398
399 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
400 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
401 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
402 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
403}
404
7101e111
SP		 405static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
406 bool unmap_single)
407{
408 dma_addr_t dma;
409
410 be_dws_le_to_cpu(wrb, sizeof(*wrb));
411
412 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
b681ee77 413 if (wrb->frag_len) {
7101e111
SP		 414 if (unmap_single)
415 pci_unmap_single(pdev, dma, wrb->frag_len,
416 PCI_DMA_TODEVICE);
417 else
418 pci_unmap_page(pdev, dma, wrb->frag_len,
419 PCI_DMA_TODEVICE);
420 }
421}
6b7c5b94
SP		 422
423static int make_tx_wrbs(struct be_adapter *adapter,
424 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
425{
7101e111
SP		 426 dma_addr_t busaddr;
427 int i, copied = 0;
6b7c5b94
SP		 428 struct pci_dev *pdev = adapter->pdev;
429 struct sk_buff *first_skb = skb;
430 struct be_queue_info *txq = &adapter->tx_obj.q;
431 struct be_eth_wrb *wrb;
432 struct be_eth_hdr_wrb *hdr;
7101e111
SP		 433 bool map_single = false;
434 u16 map_head;
6b7c5b94 435
6b7c5b94
SP		 436 hdr = queue_head_node(txq);
437 queue_head_inc(txq);
7101e111 438 map_head = txq->head;
6b7c5b94 439
ebc8d2ab 440 if (skb->len > skb->data_len) {
e743d313 441 int len = skb_headlen(skb);
a73b796e
AD		 442 busaddr = pci_map_single(pdev, skb->data, len,
443 PCI_DMA_TODEVICE);
7101e111
SP		 444 if (pci_dma_mapping_error(pdev, busaddr))
445 goto dma_err;
446 map_single = true;
ebc8d2ab
DM		 447 wrb = queue_head_node(txq);
448 wrb_fill(wrb, busaddr, len);
449 be_dws_cpu_to_le(wrb, sizeof(*wrb));
450 queue_head_inc(txq);
451 copied += len;
452 }
6b7c5b94 453
ebc8d2ab
DM		 454 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
455 struct skb_frag_struct *frag =
456 &skb_shinfo(skb)->frags[i];
a73b796e
AD		 457 busaddr = pci_map_page(pdev, frag->page,
458 frag->page_offset,
459 frag->size, PCI_DMA_TODEVICE);
7101e111
SP		 460 if (pci_dma_mapping_error(pdev, busaddr))
461 goto dma_err;
ebc8d2ab
DM		 462 wrb = queue_head_node(txq);
463 wrb_fill(wrb, busaddr, frag->size);
464 be_dws_cpu_to_le(wrb, sizeof(*wrb));
465 queue_head_inc(txq);
466 copied += frag->size;
6b7c5b94
SP		 467 }
468
469 if (dummy_wrb) {
470 wrb = queue_head_node(txq);
471 wrb_fill(wrb, 0, 0);
472 be_dws_cpu_to_le(wrb, sizeof(*wrb));
473 queue_head_inc(txq);
474 }
475
476 wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
477 wrb_cnt, copied);
478 be_dws_cpu_to_le(hdr, sizeof(*hdr));
479
480 return copied;
7101e111
SP		 481dma_err:
482 txq->head = map_head;
483 while (copied) {
484 wrb = queue_head_node(txq);
485 unmap_tx_frag(pdev, wrb, map_single);
486 map_single = false;
487 copied -= wrb->frag_len;
488 queue_head_inc(txq);
489 }
490 return 0;
6b7c5b94
SP		 491}
492
61357325 493static netdev_tx_t be_xmit(struct sk_buff *skb,
b31c50a7 494 struct net_device *netdev)
6b7c5b94
SP		 495{
496 struct be_adapter *adapter = netdev_priv(netdev);
497 struct be_tx_obj *tx_obj = &adapter->tx_obj;
498 struct be_queue_info *txq = &tx_obj->q;
499 u32 wrb_cnt = 0, copied = 0;
500 u32 start = txq->head;
501 bool dummy_wrb, stopped = false;
502
503 wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
504
505 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
c190e3c8
AK		 506 if (copied) {
507 /* record the sent skb in the sent_skb table */
508 BUG_ON(tx_obj->sent_skb_list[start]);
509 tx_obj->sent_skb_list[start] = skb;
510
511 /* Ensure txq has space for the next skb; Else stop the queue
512 * *BEFORE* ringing the tx doorbell, so that we serialze the
513 * tx compls of the current transmit which'll wake up the queue
514 */
7101e111 515 atomic_add(wrb_cnt, &txq->used);
c190e3c8
AK		 516 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
517 txq->len) {
518 netif_stop_queue(netdev);
519 stopped = true;
520 }
6b7c5b94 521
c190e3c8 522 be_txq_notify(adapter, txq->id, wrb_cnt);
6b7c5b94 523
91992e44
AK		 524 be_tx_stats_update(adapter, wrb_cnt, copied,
525 skb_shinfo(skb)->gso_segs, stopped);
c190e3c8
AK		 526 } else {
527 txq->head = start;
528 dev_kfree_skb_any(skb);
6b7c5b94 529 }
6b7c5b94
SP		 530 return NETDEV_TX_OK;
531}
532
533static int be_change_mtu(struct net_device *netdev, int new_mtu)
534{
535 struct be_adapter *adapter = netdev_priv(netdev);
536 if (new_mtu < BE_MIN_MTU ||
34a89b8c
AK		 537 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
538 (ETH_HLEN + ETH_FCS_LEN))) {
6b7c5b94
SP		 539 dev_info(&adapter->pdev->dev,
540 "MTU must be between %d and %d bytes\n",
34a89b8c
AK		 541 BE_MIN_MTU,
542 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
6b7c5b94
SP		 543 return -EINVAL;
544 }
545 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
546 netdev->mtu, new_mtu);
547 netdev->mtu = new_mtu;
548 return 0;
549}
550
551/*
82903e4b
AK		 552 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
553 * If the user configures more, place BE in vlan promiscuous mode.
6b7c5b94 554 */
1da87b7f 555static int be_vid_config(struct be_adapter *adapter, bool vf, u32 vf_num)
6b7c5b94 556{
6b7c5b94
SP		 557 u16 vtag[BE_NUM_VLANS_SUPPORTED];
558 u16 ntags = 0, i;
82903e4b 559 int status = 0;
1da87b7f
AK		 560 u32 if_handle;
561
562 if (vf) {
563 if_handle = adapter->vf_cfg[vf_num].vf_if_handle;
564 vtag[0] = cpu_to_le16(adapter->vf_cfg[vf_num].vf_vlan_tag);
565 status = be_cmd_vlan_config(adapter, if_handle, vtag, 1, 1, 0);
566 }
6b7c5b94 567
82903e4b 568 if (adapter->vlans_added <= adapter->max_vlans) {
6b7c5b94
SP		 569 /* Construct VLAN Table to give to HW */
570 for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
571 if (adapter->vlan_tag[i]) {
572 vtag[ntags] = cpu_to_le16(i);
573 ntags++;
574 }
575 }
b31c50a7
SP		 576 status = be_cmd_vlan_config(adapter, adapter->if_handle,
577 vtag, ntags, 1, 0);
6b7c5b94 578 } else {
b31c50a7
SP		 579 status = be_cmd_vlan_config(adapter, adapter->if_handle,
580 NULL, 0, 1, 1);
6b7c5b94 581 }
1da87b7f 582
b31c50a7 583 return status;
6b7c5b94
SP		 584}
585
586static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
587{
588 struct be_adapter *adapter = netdev_priv(netdev);
589 struct be_eq_obj *rx_eq = &adapter->rx_eq;
590 struct be_eq_obj *tx_eq = &adapter->tx_eq;
6b7c5b94 591
8788fdc2
SP		 592 be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
593 be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
6b7c5b94 594 adapter->vlan_grp = grp;
8788fdc2
SP		 595 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
596 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
6b7c5b94
SP		 597}
598
599static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
600{
601 struct be_adapter *adapter = netdev_priv(netdev);
602
1da87b7f 603 adapter->vlans_added++;
ba343c77
SB		 604 if (!be_physfn(adapter))
605 return;
606
6b7c5b94 607 adapter->vlan_tag[vid] = 1;
82903e4b 608 if (adapter->vlans_added <= (adapter->max_vlans + 1))
1da87b7f 609 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 610}
611
612static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
613{
614 struct be_adapter *adapter = netdev_priv(netdev);
615
1da87b7f
AK		 616 adapter->vlans_added--;
617 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
618
ba343c77
SB		 619 if (!be_physfn(adapter))
620 return;
621
6b7c5b94 622 adapter->vlan_tag[vid] = 0;
82903e4b 623 if (adapter->vlans_added <= adapter->max_vlans)
1da87b7f 624 be_vid_config(adapter, false, 0);
6b7c5b94
SP		 625}
626
24307eef 627static void be_set_multicast_list(struct net_device *netdev)
6b7c5b94
SP		 628{
629 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94 630
24307eef 631 if (netdev->flags & IFF_PROMISC) {
8788fdc2 632 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
24307eef
SP		 633 adapter->promiscuous = true;
634 goto done;
6b7c5b94
SP		 635 }
636
24307eef
SP		 637 /* BE was previously in promiscous mode; disable it */
638 if (adapter->promiscuous) {
639 adapter->promiscuous = false;
8788fdc2 640 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
6b7c5b94
SP		 641 }
642
e7b909a6 643 /* Enable multicast promisc if num configured exceeds what we support */
4cd24eaf
JP		 644 if (netdev->flags & IFF_ALLMULTI ||
645 netdev_mc_count(netdev) > BE_MAX_MC) {
0ddf477b 646 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
e7b909a6 647 &adapter->mc_cmd_mem);
24307eef 648 goto done;
6b7c5b94 649 }
6b7c5b94 650
0ddf477b 651 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
f31e50a8 652 &adapter->mc_cmd_mem);
24307eef
SP		 653done:
654 return;
6b7c5b94
SP		 655}
656
ba343c77
SB		 657static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
658{
659 struct be_adapter *adapter = netdev_priv(netdev);
660 int status;
661
662 if (!adapter->sriov_enabled)
663 return -EPERM;
664
665 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
666 return -EINVAL;
667
64600ea5
AK		 668 if (adapter->vf_cfg[vf].vf_pmac_id != BE_INVALID_PMAC_ID)
669 status = be_cmd_pmac_del(adapter,
670 adapter->vf_cfg[vf].vf_if_handle,
671 adapter->vf_cfg[vf].vf_pmac_id);
ba343c77 672
64600ea5
AK		 673 status = be_cmd_pmac_add(adapter, mac,
674 adapter->vf_cfg[vf].vf_if_handle,
675 &adapter->vf_cfg[vf].vf_pmac_id);
676
677 if (status)
ba343c77
SB		 678 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
679 mac, vf);
64600ea5
AK		 680 else
681 memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN);
682
ba343c77
SB		 683 return status;
684}
685
64600ea5
AK		 686static int be_get_vf_config(struct net_device *netdev, int vf,
687 struct ifla_vf_info *vi)
688{
689 struct be_adapter *adapter = netdev_priv(netdev);
690
691 if (!adapter->sriov_enabled)
692 return -EPERM;
693
694 if (vf >= num_vfs)
695 return -EINVAL;
696
697 vi->vf = vf;
e1d18735 698 vi->tx_rate = adapter->vf_cfg[vf].vf_tx_rate;
1da87b7f 699 vi->vlan = adapter->vf_cfg[vf].vf_vlan_tag;
64600ea5
AK		 700 vi->qos = 0;
701 memcpy(&vi->mac, adapter->vf_cfg[vf].vf_mac_addr, ETH_ALEN);
702
703 return 0;
704}
705
1da87b7f
AK		 706static int be_set_vf_vlan(struct net_device *netdev,
707 int vf, u16 vlan, u8 qos)
708{
709 struct be_adapter *adapter = netdev_priv(netdev);
710 int status = 0;
711
712 if (!adapter->sriov_enabled)
713 return -EPERM;
714
715 if ((vf >= num_vfs) || (vlan > 4095))
716 return -EINVAL;
717
718 if (vlan) {
719 adapter->vf_cfg[vf].vf_vlan_tag = vlan;
720 adapter->vlans_added++;
721 } else {
722 adapter->vf_cfg[vf].vf_vlan_tag = 0;
723 adapter->vlans_added--;
724 }
725
726 status = be_vid_config(adapter, true, vf);
727
728 if (status)
729 dev_info(&adapter->pdev->dev,
730 "VLAN %d config on VF %d failed\n", vlan, vf);
731 return status;
732}
733
e1d18735
AK		 734static int be_set_vf_tx_rate(struct net_device *netdev,
735 int vf, int rate)
736{
737 struct be_adapter *adapter = netdev_priv(netdev);
738 int status = 0;
739
740 if (!adapter->sriov_enabled)
741 return -EPERM;
742
743 if ((vf >= num_vfs) || (rate < 0))
744 return -EINVAL;
745
746 if (rate > 10000)
747 rate = 10000;
748
749 adapter->vf_cfg[vf].vf_tx_rate = rate;
750 status = be_cmd_set_qos(adapter, rate / 10, vf);
751
752 if (status)
753 dev_info(&adapter->pdev->dev,
754 "tx rate %d on VF %d failed\n", rate, vf);
755 return status;
756}
757
4097f663 758static void be_rx_rate_update(struct be_adapter *adapter)
6b7c5b94 759{
4097f663
SP		 760 struct be_drvr_stats *stats = drvr_stats(adapter);
761 ulong now = jiffies;
6b7c5b94 762
4097f663
SP		 763 /* Wrapped around */
764 if (time_before(now, stats->be_rx_jiffies)) {
765 stats->be_rx_jiffies = now;
766 return;
767 }
6b7c5b94
SP		 768
769 /* Update the rate once in two seconds */
4097f663 770 if ((now - stats->be_rx_jiffies) < 2 * HZ)
6b7c5b94
SP		 771 return;
772
65f71b8b
SH		 773 stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
774 - stats->be_rx_bytes_prev,
775 now - stats->be_rx_jiffies);
4097f663 776 stats->be_rx_jiffies = now;
6b7c5b94
SP		 777 stats->be_rx_bytes_prev = stats->be_rx_bytes;
778}
779
4097f663
SP		 780static void be_rx_stats_update(struct be_adapter *adapter,
781 u32 pktsize, u16 numfrags)
782{
783 struct be_drvr_stats *stats = drvr_stats(adapter);
784
785 stats->be_rx_compl++;
786 stats->be_rx_frags += numfrags;
787 stats->be_rx_bytes += pktsize;
91992e44 788 stats->be_rx_pkts++;
4097f663
SP		 789}
790
728a9972
AK		 791static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
792{
793 u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
794
795 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
796 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
797 ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
798 if (ip_version) {
799 tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
800 udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
801 }
802 ipv6_chk = (ip_version && (tcpf || udpf));
803
804 return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
805}
806
6b7c5b94
SP		 807static struct be_rx_page_info *
808get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
809{
810 struct be_rx_page_info *rx_page_info;
811 struct be_queue_info *rxq = &adapter->rx_obj.q;
812
813 rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
814 BUG_ON(!rx_page_info->page);
815
205859a2 816 if (rx_page_info->last_page_user) {
fac6da5b 817 pci_unmap_page(adapter->pdev, dma_unmap_addr(rx_page_info, bus),
6b7c5b94 818 adapter->big_page_size, PCI_DMA_FROMDEVICE);
205859a2
AK		 819 rx_page_info->last_page_user = false;
820 }
6b7c5b94
SP		 821
822 atomic_dec(&rxq->used);
823 return rx_page_info;
824}
825
826/* Throwaway the data in the Rx completion */
827static void be_rx_compl_discard(struct be_adapter *adapter,
828 struct be_eth_rx_compl *rxcp)
829{
830 struct be_queue_info *rxq = &adapter->rx_obj.q;
831 struct be_rx_page_info *page_info;
832 u16 rxq_idx, i, num_rcvd;
833
834 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
835 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
836
837 for (i = 0; i < num_rcvd; i++) {
838 page_info = get_rx_page_info(adapter, rxq_idx);
839 put_page(page_info->page);
840 memset(page_info, 0, sizeof(*page_info));
841 index_inc(&rxq_idx, rxq->len);
842 }
843}
844
845/*
846 * skb_fill_rx_data forms a complete skb for an ether frame
847 * indicated by rxcp.
848 */
849static void skb_fill_rx_data(struct be_adapter *adapter,
89420424
SP		 850 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
851 u16 num_rcvd)
6b7c5b94
SP		 852{
853 struct be_queue_info *rxq = &adapter->rx_obj.q;
854 struct be_rx_page_info *page_info;
89420424 855 u16 rxq_idx, i, j;
fa77406a 856 u32 pktsize, hdr_len, curr_frag_len, size;
6b7c5b94
SP		 857 u8 *start;
858
859 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
860 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
6b7c5b94
SP		 861
862 page_info = get_rx_page_info(adapter, rxq_idx);
863
864 start = page_address(page_info->page) + page_info->page_offset;
865 prefetch(start);
866
867 /* Copy data in the first descriptor of this completion */
868 curr_frag_len = min(pktsize, rx_frag_size);
869
870 /* Copy the header portion into skb_data */
871 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
872 memcpy(skb->data, start, hdr_len);
873 skb->len = curr_frag_len;
874 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
875 /* Complete packet has now been moved to data */
876 put_page(page_info->page);
877 skb->data_len = 0;
878 skb->tail += curr_frag_len;
879 } else {
880 skb_shinfo(skb)->nr_frags = 1;
881 skb_shinfo(skb)->frags[0].page = page_info->page;
882 skb_shinfo(skb)->frags[0].page_offset =
883 page_info->page_offset + hdr_len;
884 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
885 skb->data_len = curr_frag_len - hdr_len;
886 skb->tail += hdr_len;
887 }
205859a2 888 page_info->page = NULL;
6b7c5b94
SP		 889
890 if (pktsize <= rx_frag_size) {
891 BUG_ON(num_rcvd != 1);
76fbb429 892 goto done;
6b7c5b94
SP		 893 }
894
895 /* More frags present for this completion */
fa77406a 896 size = pktsize;
bd46cb6c 897 for (i = 1, j = 0; i < num_rcvd; i++) {
fa77406a 898 size -= curr_frag_len;
6b7c5b94
SP		 899 index_inc(&rxq_idx, rxq->len);
900 page_info = get_rx_page_info(adapter, rxq_idx);
901
fa77406a 902 curr_frag_len = min(size, rx_frag_size);
6b7c5b94 903
bd46cb6c
AK		 904 /* Coalesce all frags from the same physical page in one slot */
905 if (page_info->page_offset == 0) {
906 /* Fresh page */
907 j++;
908 skb_shinfo(skb)->frags[j].page = page_info->page;
909 skb_shinfo(skb)->frags[j].page_offset =
910 page_info->page_offset;
911 skb_shinfo(skb)->frags[j].size = 0;
912 skb_shinfo(skb)->nr_frags++;
913 } else {
914 put_page(page_info->page);
915 }
916
917 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94
SP		 918 skb->len += curr_frag_len;
919 skb->data_len += curr_frag_len;
6b7c5b94 920
205859a2 921 page_info->page = NULL;
6b7c5b94 922 }
bd46cb6c 923 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 924
76fbb429 925done:
4097f663 926 be_rx_stats_update(adapter, pktsize, num_rcvd);
6b7c5b94
SP		 927}
928
5be93b9a 929/* Process the RX completion indicated by rxcp when GRO is disabled */
6b7c5b94
SP		 930static void be_rx_compl_process(struct be_adapter *adapter,
931 struct be_eth_rx_compl *rxcp)
932{
933 struct sk_buff *skb;
dcb9b564 934 u32 vlanf, vid;
89420424 935 u16 num_rcvd;
dcb9b564 936 u8 vtm;
6b7c5b94 937
89420424
SP		 938 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
939 /* Is it a flush compl that has no data */
940 if (unlikely(num_rcvd == 0))
941 return;
942
89d71a66 943 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
a058a632 944 if (unlikely(!skb)) {
6b7c5b94
SP		 945 if (net_ratelimit())
946 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
947 be_rx_compl_discard(adapter, rxcp);
948 return;
949 }
950
89420424 951 skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
6b7c5b94 952
728a9972 953 if (do_pkt_csum(rxcp, adapter->rx_csum))
6b7c5b94 954 skb->ip_summed = CHECKSUM_NONE;
728a9972
AK		 955 else
956 skb->ip_summed = CHECKSUM_UNNECESSARY;
6b7c5b94
SP		 957
958 skb->truesize = skb->len + sizeof(struct sk_buff);
959 skb->protocol = eth_type_trans(skb, adapter->netdev);
6b7c5b94 960
a058a632
SP		 961 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
962 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
963
964 /* vlanf could be wrongly set in some cards.
965 * ignore if vtm is not set */
3486be29 966 if ((adapter->function_mode & 0x400) && !vtm)
a058a632
SP		 967 vlanf = 0;
968
969 if (unlikely(vlanf)) {
82903e4b 970 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
6b7c5b94
SP		 971 kfree_skb(skb);
972 return;
973 }
974 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
9cae9e4f 975 vid = swab16(vid);
6b7c5b94
SP		 976 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
977 } else {
978 netif_receive_skb(skb);
979 }
6b7c5b94
SP		 980}
981
5be93b9a
AK		 982/* Process the RX completion indicated by rxcp when GRO is enabled */
983static void be_rx_compl_process_gro(struct be_adapter *adapter,
6b7c5b94
SP		 984 struct be_eth_rx_compl *rxcp)
985{
986 struct be_rx_page_info *page_info;
5be93b9a 987 struct sk_buff *skb = NULL;
6b7c5b94 988 struct be_queue_info *rxq = &adapter->rx_obj.q;
5be93b9a 989 struct be_eq_obj *eq_obj = &adapter->rx_eq;
6b7c5b94 990 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
bd46cb6c 991 u16 i, rxq_idx = 0, vid, j;
dcb9b564 992 u8 vtm;
6b7c5b94
SP		 993
994 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
89420424
SP		 995 /* Is it a flush compl that has no data */
996 if (unlikely(num_rcvd == 0))
997 return;
998
6b7c5b94
SP		 999 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
1000 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
1001 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
dcb9b564
AK		 1002 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
1003
1004 /* vlanf could be wrongly set in some cards.
1005 * ignore if vtm is not set */
3486be29 1006 if ((adapter->function_mode & 0x400) && !vtm)
dcb9b564 1007 vlanf = 0;
6b7c5b94 1008
5be93b9a
AK		 1009 skb = napi_get_frags(&eq_obj->napi);
1010 if (!skb) {
1011 be_rx_compl_discard(adapter, rxcp);
1012 return;
1013 }
1014
6b7c5b94 1015 remaining = pkt_size;
bd46cb6c 1016 for (i = 0, j = -1; i < num_rcvd; i++) {
6b7c5b94
SP		 1017 page_info = get_rx_page_info(adapter, rxq_idx);
1018
1019 curr_frag_len = min(remaining, rx_frag_size);
1020
bd46cb6c
AK		 1021 /* Coalesce all frags from the same physical page in one slot */
1022 if (i == 0 || page_info->page_offset == 0) {
1023 /* First frag or Fresh page */
1024 j++;
5be93b9a
AK		 1025 skb_shinfo(skb)->frags[j].page = page_info->page;
1026 skb_shinfo(skb)->frags[j].page_offset =
1027 page_info->page_offset;
1028 skb_shinfo(skb)->frags[j].size = 0;
bd46cb6c
AK		 1029 } else {
1030 put_page(page_info->page);
1031 }
5be93b9a 1032 skb_shinfo(skb)->frags[j].size += curr_frag_len;
6b7c5b94 1033
bd46cb6c 1034 remaining -= curr_frag_len;
6b7c5b94 1035 index_inc(&rxq_idx, rxq->len);
6b7c5b94
SP		 1036 memset(page_info, 0, sizeof(*page_info));
1037 }
bd46cb6c 1038 BUG_ON(j > MAX_SKB_FRAGS);
6b7c5b94 1039
5be93b9a
AK		 1040 skb_shinfo(skb)->nr_frags = j + 1;
1041 skb->len = pkt_size;
1042 skb->data_len = pkt_size;
1043 skb->truesize += pkt_size;
1044 skb->ip_summed = CHECKSUM_UNNECESSARY;
1045
6b7c5b94 1046 if (likely(!vlanf)) {
5be93b9a 1047 napi_gro_frags(&eq_obj->napi);
6b7c5b94
SP		 1048 } else {
1049 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
9cae9e4f 1050 vid = swab16(vid);
6b7c5b94 1051
82903e4b 1052 if (!adapter->vlan_grp || adapter->vlans_added == 0)
6b7c5b94
SP		 1053 return;
1054
5be93b9a 1055 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
6b7c5b94
SP		 1056 }
1057
4097f663 1058 be_rx_stats_update(adapter, pkt_size, num_rcvd);
6b7c5b94
SP		 1059}
1060
1061static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
1062{
1063 struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
1064
1065 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
1066 return NULL;
1067
f3eb62d2 1068 rmb();
6b7c5b94
SP		 1069 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
1070
6b7c5b94
SP		 1071 queue_tail_inc(&adapter->rx_obj.cq);
1072 return rxcp;
1073}
1074
a7a0ef31
SP		 1075/* To reset the valid bit, we need to reset the whole word as
1076 * when walking the queue the valid entries are little-endian
1077 * and invalid entries are host endian
1078 */
1079static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
1080{
1081 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
1082}
1083
6b7c5b94
SP		 1084static inline struct page *be_alloc_pages(u32 size)
1085{
1086 gfp_t alloc_flags = GFP_ATOMIC;
1087 u32 order = get_order(size);
1088 if (order > 0)
1089 alloc_flags |= __GFP_COMP;
1090 return alloc_pages(alloc_flags, order);
1091}
1092
1093/*
1094 * Allocate a page, split it to fragments of size rx_frag_size and post as
1095 * receive buffers to BE
1096 */
1097static void be_post_rx_frags(struct be_adapter *adapter)
1098{
1099 struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
26d92f92 1100 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
6b7c5b94
SP		 1101 struct be_queue_info *rxq = &adapter->rx_obj.q;
1102 struct page *pagep = NULL;
1103 struct be_eth_rx_d *rxd;
1104 u64 page_dmaaddr = 0, frag_dmaaddr;
1105 u32 posted, page_offset = 0;
1106
6b7c5b94
SP		 1107 page_info = &page_info_tbl[rxq->head];
1108 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1109 if (!pagep) {
1110 pagep = be_alloc_pages(adapter->big_page_size);
1111 if (unlikely(!pagep)) {
1112 drvr_stats(adapter)->be_ethrx_post_fail++;
1113 break;
1114 }
1115 page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
1116 adapter->big_page_size,
1117 PCI_DMA_FROMDEVICE);
1118 page_info->page_offset = 0;
1119 } else {
1120 get_page(pagep);
1121 page_info->page_offset = page_offset + rx_frag_size;
1122 }
1123 page_offset = page_info->page_offset;
1124 page_info->page = pagep;
fac6da5b 1125 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
6b7c5b94
SP		 1126 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1127
1128 rxd = queue_head_node(rxq);
1129 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1130 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
6b7c5b94
SP		 1131
1132 /* Any space left in the current big page for another frag? */
1133 if ((page_offset + rx_frag_size + rx_frag_size) >
1134 adapter->big_page_size) {
1135 pagep = NULL;
1136 page_info->last_page_user = true;
1137 }
26d92f92
SP		 1138
1139 prev_page_info = page_info;
1140 queue_head_inc(rxq);
6b7c5b94
SP		 1141 page_info = &page_info_tbl[rxq->head];
1142 }
1143 if (pagep)
26d92f92 1144 prev_page_info->last_page_user = true;
6b7c5b94
SP		 1145
1146 if (posted) {
6b7c5b94 1147 atomic_add(posted, &rxq->used);
8788fdc2 1148 be_rxq_notify(adapter, rxq->id, posted);
ea1dae11
SP		 1149 } else if (atomic_read(&rxq->used) == 0) {
1150 /* Let be_worker replenish when memory is available */
1151 adapter->rx_post_starved = true;
6b7c5b94 1152 }
6b7c5b94
SP		 1153}
1154
5fb379ee 1155static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
6b7c5b94 1156{
6b7c5b94
SP		 1157 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1158
1159 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1160 return NULL;
1161
f3eb62d2 1162 rmb();
6b7c5b94
SP		 1163 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1164
1165 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1166
1167 queue_tail_inc(tx_cq);
1168 return txcp;
1169}
1170
1171static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1172{
1173 struct be_queue_info *txq = &adapter->tx_obj.q;
a73b796e 1174 struct be_eth_wrb *wrb;
6b7c5b94
SP		 1175 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1176 struct sk_buff *sent_skb;
ec43b1a6
SP		 1177 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1178 bool unmap_skb_hdr = true;
6b7c5b94 1179
ec43b1a6 1180 sent_skb = sent_skbs[txq->tail];
6b7c5b94 1181 BUG_ON(!sent_skb);
ec43b1a6
SP		 1182 sent_skbs[txq->tail] = NULL;
1183
1184 /* skip header wrb */
a73b796e 1185 queue_tail_inc(txq);
6b7c5b94 1186
ec43b1a6 1187 do {
6b7c5b94 1188 cur_index = txq->tail;
a73b796e 1189 wrb = queue_tail_node(txq);
ec43b1a6 1190 unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
e743d313 1191 skb_headlen(sent_skb)));
ec43b1a6
SP		 1192 unmap_skb_hdr = false;
1193
6b7c5b94
SP		 1194 num_wrbs++;
1195 queue_tail_inc(txq);
ec43b1a6 1196 } while (cur_index != last_index);
6b7c5b94
SP		 1197
1198 atomic_sub(num_wrbs, &txq->used);
a73b796e 1199
6b7c5b94
SP		 1200 kfree_skb(sent_skb);
1201}
1202
859b1e4e
SP		 1203static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1204{
1205 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1206
1207 if (!eqe->evt)
1208 return NULL;
1209
f3eb62d2 1210 rmb();
859b1e4e
SP		 1211 eqe->evt = le32_to_cpu(eqe->evt);
1212 queue_tail_inc(&eq_obj->q);
1213 return eqe;
1214}
1215
1216static int event_handle(struct be_adapter *adapter,
1217 struct be_eq_obj *eq_obj)
1218{
1219 struct be_eq_entry *eqe;
1220 u16 num = 0;
1221
1222 while ((eqe = event_get(eq_obj)) != NULL) {
1223 eqe->evt = 0;
1224 num++;
1225 }
1226
1227 /* Deal with any spurious interrupts that come
1228 * without events
1229 */
1230 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1231 if (num)
1232 napi_schedule(&eq_obj->napi);
1233
1234 return num;
1235}
1236
1237/* Just read and notify events without processing them.
1238 * Used at the time of destroying event queues */
1239static void be_eq_clean(struct be_adapter *adapter,
1240 struct be_eq_obj *eq_obj)
1241{
1242 struct be_eq_entry *eqe;
1243 u16 num = 0;
1244
1245 while ((eqe = event_get(eq_obj)) != NULL) {
1246 eqe->evt = 0;
1247 num++;
1248 }
1249
1250 if (num)
1251 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1252}
1253
6b7c5b94
SP		 1254static void be_rx_q_clean(struct be_adapter *adapter)
1255{
1256 struct be_rx_page_info *page_info;
1257 struct be_queue_info *rxq = &adapter->rx_obj.q;
1258 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1259 struct be_eth_rx_compl *rxcp;
1260 u16 tail;
1261
1262 /* First cleanup pending rx completions */
1263 while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
1264 be_rx_compl_discard(adapter, rxcp);
a7a0ef31 1265 be_rx_compl_reset(rxcp);
8788fdc2 1266 be_cq_notify(adapter, rx_cq->id, true, 1);
6b7c5b94
SP		 1267 }
1268
1269 /* Then free posted rx buffer that were not used */
1270 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
cdab23b7 1271 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
6b7c5b94
SP		 1272 page_info = get_rx_page_info(adapter, tail);
1273 put_page(page_info->page);
1274 memset(page_info, 0, sizeof(*page_info));
1275 }
1276 BUG_ON(atomic_read(&rxq->used));
1277}
1278
a8e9179a 1279static void be_tx_compl_clean(struct be_adapter *adapter)
6b7c5b94 1280{
a8e9179a 1281 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1282 struct be_queue_info *txq = &adapter->tx_obj.q;
a8e9179a
SP		 1283 struct be_eth_tx_compl *txcp;
1284 u16 end_idx, cmpl = 0, timeo = 0;
b03388d6
SP		 1285 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1286 struct sk_buff *sent_skb;
1287 bool dummy_wrb;
a8e9179a
SP		 1288
1289 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1290 do {
1291 while ((txcp = be_tx_compl_get(tx_cq))) {
1292 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1293 wrb_index, txcp);
1294 be_tx_compl_process(adapter, end_idx);
1295 cmpl++;
1296 }
1297 if (cmpl) {
1298 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1299 cmpl = 0;
1300 }
1301
1302 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1303 break;
1304
1305 mdelay(1);
1306 } while (true);
1307
1308 if (atomic_read(&txq->used))
1309 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1310 atomic_read(&txq->used));
b03388d6
SP		 1311
1312 /* free posted tx for which compls will never arrive */
1313 while (atomic_read(&txq->used)) {
1314 sent_skb = sent_skbs[txq->tail];
1315 end_idx = txq->tail;
1316 index_adv(&end_idx,
1317 wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
1318 be_tx_compl_process(adapter, end_idx);
1319 }
6b7c5b94
SP		 1320}
1321
5fb379ee
SP		 1322static void be_mcc_queues_destroy(struct be_adapter *adapter)
1323{
1324 struct be_queue_info *q;
5fb379ee 1325
8788fdc2 1326 q = &adapter->mcc_obj.q;
5fb379ee 1327 if (q->created)
8788fdc2 1328 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
5fb379ee
SP		 1329 be_queue_free(adapter, q);
1330
8788fdc2 1331 q = &adapter->mcc_obj.cq;
5fb379ee 1332 if (q->created)
8788fdc2 1333 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
5fb379ee
SP		 1334 be_queue_free(adapter, q);
1335}
1336
1337/* Must be called only after TX qs are created as MCC shares TX EQ */
1338static int be_mcc_queues_create(struct be_adapter *adapter)
1339{
1340 struct be_queue_info *q, *cq;
5fb379ee
SP		 1341
1342 /* Alloc MCC compl queue */
8788fdc2 1343 cq = &adapter->mcc_obj.cq;
5fb379ee 1344 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
efd2e40a 1345 sizeof(struct be_mcc_compl)))
5fb379ee
SP		 1346 goto err;
1347
1348 /* Ask BE to create MCC compl queue; share TX's eq */
8788fdc2 1349 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
5fb379ee
SP		 1350 goto mcc_cq_free;
1351
1352 /* Alloc MCC queue */
8788fdc2 1353 q = &adapter->mcc_obj.q;
5fb379ee
SP		 1354 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1355 goto mcc_cq_destroy;
1356
1357 /* Ask BE to create MCC queue */
8788fdc2 1358 if (be_cmd_mccq_create(adapter, q, cq))
5fb379ee
SP		 1359 goto mcc_q_free;
1360
1361 return 0;
1362
1363mcc_q_free:
1364 be_queue_free(adapter, q);
1365mcc_cq_destroy:
8788fdc2 1366 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
5fb379ee
SP		 1367mcc_cq_free:
1368 be_queue_free(adapter, cq);
1369err:
1370 return -1;
1371}
1372
6b7c5b94
SP		 1373static void be_tx_queues_destroy(struct be_adapter *adapter)
1374{
1375 struct be_queue_info *q;
1376
1377 q = &adapter->tx_obj.q;
a8e9179a 1378 if (q->created)
8788fdc2 1379 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
6b7c5b94
SP		 1380 be_queue_free(adapter, q);
1381
1382 q = &adapter->tx_obj.cq;
1383 if (q->created)
8788fdc2 1384 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1385 be_queue_free(adapter, q);
1386
859b1e4e
SP		 1387 /* Clear any residual events */
1388 be_eq_clean(adapter, &adapter->tx_eq);
1389
6b7c5b94
SP		 1390 q = &adapter->tx_eq.q;
1391 if (q->created)
8788fdc2 1392 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1393 be_queue_free(adapter, q);
1394}
1395
1396static int be_tx_queues_create(struct be_adapter *adapter)
1397{
1398 struct be_queue_info *eq, *q, *cq;
1399
1400 adapter->tx_eq.max_eqd = 0;
1401 adapter->tx_eq.min_eqd = 0;
1402 adapter->tx_eq.cur_eqd = 96;
1403 adapter->tx_eq.enable_aic = false;
1404 /* Alloc Tx Event queue */
1405 eq = &adapter->tx_eq.q;
1406 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1407 return -1;
1408
1409 /* Ask BE to create Tx Event queue */
8788fdc2 1410 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
6b7c5b94 1411 goto tx_eq_free;
ba343c77
SB		 1412 adapter->base_eq_id = adapter->tx_eq.q.id;
1413
6b7c5b94
SP		 1414 /* Alloc TX eth compl queue */
1415 cq = &adapter->tx_obj.cq;
1416 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1417 sizeof(struct be_eth_tx_compl)))
1418 goto tx_eq_destroy;
1419
1420 /* Ask BE to create Tx eth compl queue */
8788fdc2 1421 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
6b7c5b94
SP		 1422 goto tx_cq_free;
1423
1424 /* Alloc TX eth queue */
1425 q = &adapter->tx_obj.q;
1426 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1427 goto tx_cq_destroy;
1428
1429 /* Ask BE to create Tx eth queue */
8788fdc2 1430 if (be_cmd_txq_create(adapter, q, cq))
6b7c5b94
SP		 1431 goto tx_q_free;
1432 return 0;
1433
1434tx_q_free:
1435 be_queue_free(adapter, q);
1436tx_cq_destroy:
8788fdc2 1437 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1438tx_cq_free:
1439 be_queue_free(adapter, cq);
1440tx_eq_destroy:
8788fdc2 1441 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1442tx_eq_free:
1443 be_queue_free(adapter, eq);
1444 return -1;
1445}
1446
1447static void be_rx_queues_destroy(struct be_adapter *adapter)
1448{
1449 struct be_queue_info *q;
1450
1451 q = &adapter->rx_obj.q;
1452 if (q->created) {
8788fdc2 1453 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
89420424
SP		 1454
1455 /* After the rxq is invalidated, wait for a grace time
1456 * of 1ms for all dma to end and the flush compl to arrive
1457 */
1458 mdelay(1);
6b7c5b94
SP		 1459 be_rx_q_clean(adapter);
1460 }
1461 be_queue_free(adapter, q);
1462
1463 q = &adapter->rx_obj.cq;
1464 if (q->created)
8788fdc2 1465 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
6b7c5b94
SP		 1466 be_queue_free(adapter, q);
1467
859b1e4e
SP		 1468 /* Clear any residual events */
1469 be_eq_clean(adapter, &adapter->rx_eq);
1470
6b7c5b94
SP		 1471 q = &adapter->rx_eq.q;
1472 if (q->created)
8788fdc2 1473 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
6b7c5b94
SP		 1474 be_queue_free(adapter, q);
1475}
1476
1477static int be_rx_queues_create(struct be_adapter *adapter)
1478{
1479 struct be_queue_info *eq, *q, *cq;
1480 int rc;
1481
6b7c5b94
SP		 1482 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
1483 adapter->rx_eq.max_eqd = BE_MAX_EQD;
1484 adapter->rx_eq.min_eqd = 0;
1485 adapter->rx_eq.cur_eqd = 0;
1486 adapter->rx_eq.enable_aic = true;
1487
1488 /* Alloc Rx Event queue */
1489 eq = &adapter->rx_eq.q;
1490 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1491 sizeof(struct be_eq_entry));
1492 if (rc)
1493 return rc;
1494
1495 /* Ask BE to create Rx Event queue */
8788fdc2 1496 rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
6b7c5b94
SP		 1497 if (rc)
1498 goto rx_eq_free;
1499
1500 /* Alloc RX eth compl queue */
1501 cq = &adapter->rx_obj.cq;
1502 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1503 sizeof(struct be_eth_rx_compl));
1504 if (rc)
1505 goto rx_eq_destroy;
1506
1507 /* Ask BE to create Rx eth compl queue */
8788fdc2 1508 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
6b7c5b94
SP		 1509 if (rc)
1510 goto rx_cq_free;
1511
1512 /* Alloc RX eth queue */
1513 q = &adapter->rx_obj.q;
1514 rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
1515 if (rc)
1516 goto rx_cq_destroy;
1517
1518 /* Ask BE to create Rx eth queue */
8788fdc2 1519 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
6b7c5b94
SP		 1520 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
1521 if (rc)
1522 goto rx_q_free;
1523
1524 return 0;
1525rx_q_free:
1526 be_queue_free(adapter, q);
1527rx_cq_destroy:
8788fdc2 1528 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
6b7c5b94
SP		 1529rx_cq_free:
1530 be_queue_free(adapter, cq);
1531rx_eq_destroy:
8788fdc2 1532 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
6b7c5b94
SP		 1533rx_eq_free:
1534 be_queue_free(adapter, eq);
1535 return rc;
1536}
6b7c5b94 1537
b628bde2
SP		 1538/* There are 8 evt ids per func. Retruns the evt id's bit number */
1539static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
1540{
ba343c77 1541 return eq_id - adapter->base_eq_id;
b628bde2
SP		 1542}
1543
6b7c5b94
SP		 1544static irqreturn_t be_intx(int irq, void *dev)
1545{
1546 struct be_adapter *adapter = dev;
8788fdc2 1547 int isr;
6b7c5b94 1548
8788fdc2 1549 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
55bdeed9 1550 (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
c001c213 1551 if (!isr)
8788fdc2 1552 return IRQ_NONE;
6b7c5b94 1553
8788fdc2
SP		 1554 event_handle(adapter, &adapter->tx_eq);
1555 event_handle(adapter, &adapter->rx_eq);
c001c213 1556
8788fdc2 1557 return IRQ_HANDLED;
6b7c5b94
SP		 1558}
1559
1560static irqreturn_t be_msix_rx(int irq, void *dev)
1561{
1562 struct be_adapter *adapter = dev;
1563
8788fdc2 1564 event_handle(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1565
1566 return IRQ_HANDLED;
1567}
1568
5fb379ee 1569static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
6b7c5b94
SP		 1570{
1571 struct be_adapter *adapter = dev;
1572
8788fdc2 1573 event_handle(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1574
1575 return IRQ_HANDLED;
1576}
1577
5be93b9a 1578static inline bool do_gro(struct be_adapter *adapter,
6b7c5b94
SP		 1579 struct be_eth_rx_compl *rxcp)
1580{
1581 int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1582 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1583
1584 if (err)
1585 drvr_stats(adapter)->be_rxcp_err++;
1586
5be93b9a 1587 return (tcp_frame && !err) ? true : false;
6b7c5b94
SP		 1588}
1589
1590int be_poll_rx(struct napi_struct *napi, int budget)
1591{
1592 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
1593 struct be_adapter *adapter =
1594 container_of(rx_eq, struct be_adapter, rx_eq);
1595 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1596 struct be_eth_rx_compl *rxcp;
1597 u32 work_done;
1598
b7b83ac3 1599 adapter->stats.drvr_stats.be_rx_polls++;
6b7c5b94
SP		 1600 for (work_done = 0; work_done < budget; work_done++) {
1601 rxcp = be_rx_compl_get(adapter);
1602 if (!rxcp)
1603 break;
1604
5be93b9a
AK		 1605 if (do_gro(adapter, rxcp))
1606 be_rx_compl_process_gro(adapter, rxcp);
6b7c5b94
SP		 1607 else
1608 be_rx_compl_process(adapter, rxcp);
a7a0ef31
SP		 1609
1610 be_rx_compl_reset(rxcp);
6b7c5b94
SP		 1611 }
1612
6b7c5b94
SP		 1613 /* Refill the queue */
1614 if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
1615 be_post_rx_frags(adapter);
1616
1617 /* All consumed */
1618 if (work_done < budget) {
1619 napi_complete(napi);
8788fdc2 1620 be_cq_notify(adapter, rx_cq->id, true, work_done);
6b7c5b94
SP		 1621 } else {
1622 /* More to be consumed; continue with interrupts disabled */
8788fdc2 1623 be_cq_notify(adapter, rx_cq->id, false, work_done);
6b7c5b94
SP		 1624 }
1625 return work_done;
1626}
1627
f31e50a8
SP		 1628/* As TX and MCC share the same EQ check for both TX and MCC completions.
1629 * For TX/MCC we don't honour budget; consume everything
1630 */
1631static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
6b7c5b94 1632{
f31e50a8
SP		 1633 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1634 struct be_adapter *adapter =
1635 container_of(tx_eq, struct be_adapter, tx_eq);
5fb379ee
SP		 1636 struct be_queue_info *txq = &adapter->tx_obj.q;
1637 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
6b7c5b94 1638 struct be_eth_tx_compl *txcp;
f31e50a8 1639 int tx_compl = 0, mcc_compl, status = 0;
6b7c5b94
SP		 1640 u16 end_idx;
1641
5fb379ee 1642 while ((txcp = be_tx_compl_get(tx_cq))) {
6b7c5b94 1643 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
f31e50a8 1644 wrb_index, txcp);
6b7c5b94 1645 be_tx_compl_process(adapter, end_idx);
f31e50a8 1646 tx_compl++;
6b7c5b94
SP		 1647 }
1648
f31e50a8
SP		 1649 mcc_compl = be_process_mcc(adapter, &status);
1650
1651 napi_complete(napi);
1652
1653 if (mcc_compl) {
1654 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1655 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1656 }
1657
1658 if (tx_compl) {
1659 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
5fb379ee
SP		 1660
1661 /* As Tx wrbs have been freed up, wake up netdev queue if
1662 * it was stopped due to lack of tx wrbs.
1663 */
1664 if (netif_queue_stopped(adapter->netdev) &&
6b7c5b94 1665 atomic_read(&txq->used) < txq->len / 2) {
5fb379ee
SP		 1666 netif_wake_queue(adapter->netdev);
1667 }
1668
1669 drvr_stats(adapter)->be_tx_events++;
f31e50a8 1670 drvr_stats(adapter)->be_tx_compl += tx_compl;
6b7c5b94 1671 }
6b7c5b94
SP		 1672
1673 return 1;
1674}
1675
ea1dae11
SP		 1676static void be_worker(struct work_struct *work)
1677{
1678 struct be_adapter *adapter =
1679 container_of(work, struct be_adapter, work.work);
ea1dae11 1680
b31c50a7 1681 be_cmd_get_stats(adapter, &adapter->stats.cmd);
ea1dae11
SP		 1682
1683 /* Set EQ delay */
1684 be_rx_eqd_update(adapter);
1685
4097f663
SP		 1686 be_tx_rate_update(adapter);
1687 be_rx_rate_update(adapter);
1688
ea1dae11
SP		 1689 if (adapter->rx_post_starved) {
1690 adapter->rx_post_starved = false;
1691 be_post_rx_frags(adapter);
1692 }
1693
1694 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1695}
1696
8d56ff11
SP		 1697static void be_msix_disable(struct be_adapter *adapter)
1698{
1699 if (adapter->msix_enabled) {
1700 pci_disable_msix(adapter->pdev);
1701 adapter->msix_enabled = false;
1702 }
1703}
1704
6b7c5b94
SP		 1705static void be_msix_enable(struct be_adapter *adapter)
1706{
1707 int i, status;
1708
1709 for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
1710 adapter->msix_entries[i].entry = i;
1711
1712 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1713 BE_NUM_MSIX_VECTORS);
1714 if (status == 0)
1715 adapter->msix_enabled = true;
6b7c5b94
SP		 1716}
1717
ba343c77
SB		 1718static void be_sriov_enable(struct be_adapter *adapter)
1719{
1720#ifdef CONFIG_PCI_IOV
1721 int status;
344dbf10 1722 be_check_sriov_fn_type(adapter);
ba343c77
SB		 1723 if (be_physfn(adapter) && num_vfs) {
1724 status = pci_enable_sriov(adapter->pdev, num_vfs);
1725 adapter->sriov_enabled = status ? false : true;
1726 }
1727#endif
ba343c77
SB		 1728}
1729
1730static void be_sriov_disable(struct be_adapter *adapter)
1731{
1732#ifdef CONFIG_PCI_IOV
1733 if (adapter->sriov_enabled) {
1734 pci_disable_sriov(adapter->pdev);
1735 adapter->sriov_enabled = false;
1736 }
1737#endif
1738}
1739
6b7c5b94
SP		 1740static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
1741{
b628bde2
SP		 1742 return adapter->msix_entries[
1743 be_evt_bit_get(adapter, eq_id)].vector;
6b7c5b94
SP		 1744}
1745
b628bde2
SP		 1746static int be_request_irq(struct be_adapter *adapter,
1747 struct be_eq_obj *eq_obj,
1748 void *handler, char *desc)
6b7c5b94
SP		 1749{
1750 struct net_device *netdev = adapter->netdev;
b628bde2
SP		 1751 int vec;
1752
1753 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
1754 vec = be_msix_vec_get(adapter, eq_obj->q.id);
1755 return request_irq(vec, handler, 0, eq_obj->desc, adapter);
1756}
1757
1758static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
1759{
1760 int vec = be_msix_vec_get(adapter, eq_obj->q.id);
1761 free_irq(vec, adapter);
1762}
6b7c5b94 1763
b628bde2
SP		 1764static int be_msix_register(struct be_adapter *adapter)
1765{
1766 int status;
1767
1768 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
6b7c5b94
SP		 1769 if (status)
1770 goto err;
1771
b628bde2
SP		 1772 status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
1773 if (status)
1774 goto free_tx_irq;
1775
6b7c5b94 1776 return 0;
b628bde2
SP		 1777
1778free_tx_irq:
1779 be_free_irq(adapter, &adapter->tx_eq);
6b7c5b94
SP		 1780err:
1781 dev_warn(&adapter->pdev->dev,
1782 "MSIX Request IRQ failed - err %d\n", status);
1783 pci_disable_msix(adapter->pdev);
1784 adapter->msix_enabled = false;
1785 return status;
1786}
1787
1788static int be_irq_register(struct be_adapter *adapter)
1789{
1790 struct net_device *netdev = adapter->netdev;
1791 int status;
1792
1793 if (adapter->msix_enabled) {
1794 status = be_msix_register(adapter);
1795 if (status == 0)
1796 goto done;
ba343c77
SB		 1797 /* INTx is not supported for VF */
1798 if (!be_physfn(adapter))
1799 return status;
6b7c5b94
SP		 1800 }
1801
1802 /* INTx */
1803 netdev->irq = adapter->pdev->irq;
1804 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
1805 adapter);
1806 if (status) {
1807 dev_err(&adapter->pdev->dev,
1808 "INTx request IRQ failed - err %d\n", status);
1809 return status;
1810 }
1811done:
1812 adapter->isr_registered = true;
1813 return 0;
1814}
1815
1816static void be_irq_unregister(struct be_adapter *adapter)
1817{
1818 struct net_device *netdev = adapter->netdev;
6b7c5b94
SP		 1819
1820 if (!adapter->isr_registered)
1821 return;
1822
1823 /* INTx */
1824 if (!adapter->msix_enabled) {
1825 free_irq(netdev->irq, adapter);
1826 goto done;
1827 }
1828
1829 /* MSIx */
b628bde2
SP		 1830 be_free_irq(adapter, &adapter->tx_eq);
1831 be_free_irq(adapter, &adapter->rx_eq);
6b7c5b94
SP		 1832done:
1833 adapter->isr_registered = false;
6b7c5b94
SP		 1834}
1835
889cd4b2
SP		 1836static int be_close(struct net_device *netdev)
1837{
1838 struct be_adapter *adapter = netdev_priv(netdev);
1839 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1840 struct be_eq_obj *tx_eq = &adapter->tx_eq;
1841 int vec;
1842
1843 cancel_delayed_work_sync(&adapter->work);
1844
1845 be_async_mcc_disable(adapter);
1846
1847 netif_stop_queue(netdev);
1848 netif_carrier_off(netdev);
1849 adapter->link_up = false;
1850
1851 be_intr_set(adapter, false);
1852
1853 if (adapter->msix_enabled) {
1854 vec = be_msix_vec_get(adapter, tx_eq->q.id);
1855 synchronize_irq(vec);
1856 vec = be_msix_vec_get(adapter, rx_eq->q.id);
1857 synchronize_irq(vec);
1858 } else {
1859 synchronize_irq(netdev->irq);
1860 }
1861 be_irq_unregister(adapter);
1862
1863 napi_disable(&rx_eq->napi);
1864 napi_disable(&tx_eq->napi);
1865
1866 /* Wait for all pending tx completions to arrive so that
1867 * all tx skbs are freed.
1868 */
1869 be_tx_compl_clean(adapter);
1870
1871 return 0;
1872}
1873
6b7c5b94
SP		 1874static int be_open(struct net_device *netdev)
1875{
1876 struct be_adapter *adapter = netdev_priv(netdev);
6b7c5b94
SP		 1877 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1878 struct be_eq_obj *tx_eq = &adapter->tx_eq;
a8f447bd
SP		 1879 bool link_up;
1880 int status;
0388f251
SB		 1881 u8 mac_speed;
1882 u16 link_speed;
5fb379ee
SP		 1883
1884 /* First time posting */
1885 be_post_rx_frags(adapter);
1886
1887 napi_enable(&rx_eq->napi);
1888 napi_enable(&tx_eq->napi);
1889
1890 be_irq_register(adapter);
1891
8788fdc2 1892 be_intr_set(adapter, true);
5fb379ee
SP		 1893
1894 /* The evt queues are created in unarmed state; arm them */
8788fdc2
SP		 1895 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
1896 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
5fb379ee
SP		 1897
1898 /* Rx compl queue may be in unarmed state; rearm it */
8788fdc2 1899 be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
5fb379ee 1900
7a1e9b20
SP		 1901 /* Now that interrupts are on we can process async mcc */
1902 be_async_mcc_enable(adapter);
1903
889cd4b2
SP		 1904 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
1905
0388f251
SB		 1906 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
1907 &link_speed);
a8f447bd 1908 if (status)
889cd4b2 1909 goto err;
a8f447bd 1910 be_link_status_update(adapter, link_up);
5fb379ee 1911
889cd4b2 1912 if (be_physfn(adapter)) {
1da87b7f 1913 status = be_vid_config(adapter, false, 0);
889cd4b2
SP		 1914 if (status)
1915 goto err;
4f2aa89c 1916
ba343c77
SB		 1917 status = be_cmd_set_flow_control(adapter,
1918 adapter->tx_fc, adapter->rx_fc);
1919 if (status)
889cd4b2 1920 goto err;
ba343c77 1921 }
4f2aa89c 1922
889cd4b2
SP		 1923 return 0;
1924err:
1925 be_close(adapter->netdev);
1926 return -EIO;
5fb379ee
SP		 1927}
1928
71d8d1b5
AK		 1929static int be_setup_wol(struct be_adapter *adapter, bool enable)
1930{
1931 struct be_dma_mem cmd;
1932 int status = 0;
1933 u8 mac[ETH_ALEN];
1934
1935 memset(mac, 0, ETH_ALEN);
1936
1937 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
1938 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
1939 if (cmd.va == NULL)
1940 return -1;
1941 memset(cmd.va, 0, cmd.size);
1942
1943 if (enable) {
1944 status = pci_write_config_dword(adapter->pdev,
1945 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
1946 if (status) {
1947 dev_err(&adapter->pdev->dev,
2381a55c 1948 "Could not enable Wake-on-lan\n");
71d8d1b5
AK		 1949 pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
1950 cmd.dma);
1951 return status;
1952 }
1953 status = be_cmd_enable_magic_wol(adapter,
1954 adapter->netdev->dev_addr, &cmd);
1955 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
1956 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
1957 } else {
1958 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
1959 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
1960 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
1961 }
1962
1963 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
1964 return status;
1965}
1966
5fb379ee
SP		 1967static int be_setup(struct be_adapter *adapter)
1968{
5fb379ee 1969 struct net_device *netdev = adapter->netdev;
ba343c77 1970 u32 cap_flags, en_flags, vf = 0;
6b7c5b94 1971 int status;
ba343c77
SB		 1972 u8 mac[ETH_ALEN];
1973
1974 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
6b7c5b94 1975
ba343c77
SB		 1976 if (be_physfn(adapter)) {
1977 cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
1978 BE_IF_FLAGS_PROMISCUOUS |
1979 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1980 en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
1981 }
73d540f2
SP		 1982
1983 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1984 netdev->dev_addr, false/* pmac_invalid */,
ba343c77 1985 &adapter->if_handle, &adapter->pmac_id, 0);
6b7c5b94
SP		 1986 if (status != 0)
1987 goto do_none;
1988
ba343c77
SB		 1989 if (be_physfn(adapter)) {
1990 while (vf < num_vfs) {
1991 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED
1992 | BE_IF_FLAGS_BROADCAST;
1993 status = be_cmd_if_create(adapter, cap_flags, en_flags,
64600ea5
AK		 1994 mac, true,
1995 &adapter->vf_cfg[vf].vf_if_handle,
ba343c77
SB		 1996 NULL, vf+1);
1997 if (status) {
1998 dev_err(&adapter->pdev->dev,
1999 "Interface Create failed for VF %d\n", vf);
2000 goto if_destroy;
2001 }
64600ea5 2002 adapter->vf_cfg[vf].vf_pmac_id = BE_INVALID_PMAC_ID;
ba343c77 2003 vf++;
84e5b9f7 2004 }
ba343c77
SB		 2005 } else if (!be_physfn(adapter)) {
2006 status = be_cmd_mac_addr_query(adapter, mac,
2007 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
2008 if (!status) {
2009 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2010 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2011 }
2012 }
2013
6b7c5b94
SP		 2014 status = be_tx_queues_create(adapter);
2015 if (status != 0)
2016 goto if_destroy;
2017
2018 status = be_rx_queues_create(adapter);
2019 if (status != 0)
2020 goto tx_qs_destroy;
2021
5fb379ee
SP		 2022 status = be_mcc_queues_create(adapter);
2023 if (status != 0)
2024 goto rx_qs_destroy;
6b7c5b94 2025
0dffc83e
AK		 2026 adapter->link_speed = -1;
2027
6b7c5b94
SP		 2028 return 0;
2029
5fb379ee
SP		 2030rx_qs_destroy:
2031 be_rx_queues_destroy(adapter);
6b7c5b94
SP		 2032tx_qs_destroy:
2033 be_tx_queues_destroy(adapter);
2034if_destroy:
ba343c77 2035 for (vf = 0; vf < num_vfs; vf++)
64600ea5
AK		 2036 if (adapter->vf_cfg[vf].vf_if_handle)
2037 be_cmd_if_destroy(adapter,
2038 adapter->vf_cfg[vf].vf_if_handle);
8788fdc2 2039 be_cmd_if_destroy(adapter, adapter->if_handle);
6b7c5b94
SP		 2040do_none:
2041 return status;
2042}
2043
5fb379ee
SP		 2044static int be_clear(struct be_adapter *adapter)
2045{
1a8887d8 2046 be_mcc_queues_destroy(adapter);
5fb379ee
SP		 2047 be_rx_queues_destroy(adapter);
2048 be_tx_queues_destroy(adapter);
2049
8788fdc2 2050 be_cmd_if_destroy(adapter, adapter->if_handle);
5fb379ee 2051
2243e2e9
SP		 2052 /* tell fw we're done with firing cmds */
2053 be_cmd_fw_clean(adapter);
5fb379ee
SP		 2054 return 0;
2055}
2056
6b7c5b94 2057
84517482
AK		 2058#define FW_FILE_HDR_SIGN "ServerEngines Corp. "
2059char flash_cookie[2][16] = {"*** SE FLAS",
2060 "H DIRECTORY *** "};
fa9a6fed
SB		 2061
2062static bool be_flash_redboot(struct be_adapter *adapter,
3f0d4560
AK		 2063 const u8 *p, u32 img_start, int image_size,
2064 int hdr_size)
fa9a6fed
SB		 2065{
2066 u32 crc_offset;
2067 u8 flashed_crc[4];
2068 int status;
3f0d4560
AK		 2069
2070 crc_offset = hdr_size + img_start + image_size - 4;
2071
fa9a6fed 2072 p += crc_offset;
3f0d4560
AK		 2073
2074 status = be_cmd_get_flash_crc(adapter, flashed_crc,
f510fc64 2075 (image_size - 4));
fa9a6fed
SB		 2076 if (status) {
2077 dev_err(&adapter->pdev->dev,
2078 "could not get crc from flash, not flashing redboot\n");
2079 return false;
2080 }
2081
2082 /*update redboot only if crc does not match*/
2083 if (!memcmp(flashed_crc, p, 4))
2084 return false;
2085 else
2086 return true;
fa9a6fed
SB		 2087}
2088
3f0d4560 2089static int be_flash_data(struct be_adapter *adapter,
84517482 2090 const struct firmware *fw,
3f0d4560
AK		 2091 struct be_dma_mem *flash_cmd, int num_of_images)
2092
84517482 2093{
3f0d4560
AK		 2094 int status = 0, i, filehdr_size = 0;
2095 u32 total_bytes = 0, flash_op;
84517482
AK		 2096 int num_bytes;
2097 const u8 *p = fw->data;
2098 struct be_cmd_write_flashrom *req = flash_cmd->va;
3f0d4560 2099 struct flash_comp *pflashcomp;
9fe96934 2100 int num_comp;
3f0d4560 2101
9fe96934 2102 struct flash_comp gen3_flash_types[9] = {
3f0d4560
AK		 2103 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2104 FLASH_IMAGE_MAX_SIZE_g3},
2105 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2106 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2107 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2108 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2109 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2110 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2111 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2112 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2113 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2114 FLASH_IMAGE_MAX_SIZE_g3},
2115 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2116 FLASH_IMAGE_MAX_SIZE_g3},
2117 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
9fe96934
SB		 2118 FLASH_IMAGE_MAX_SIZE_g3},
2119 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
2120 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
3f0d4560
AK		 2121 };
2122 struct flash_comp gen2_flash_types[8] = {
2123 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2124 FLASH_IMAGE_MAX_SIZE_g2},
2125 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2126 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2127 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2128 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2129 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2130 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2131 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2132 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2133 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2134 FLASH_IMAGE_MAX_SIZE_g2},
2135 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2136 FLASH_IMAGE_MAX_SIZE_g2},
2137 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2138 FLASH_IMAGE_MAX_SIZE_g2}
2139 };
2140
2141 if (adapter->generation == BE_GEN3) {
2142 pflashcomp = gen3_flash_types;
2143 filehdr_size = sizeof(struct flash_file_hdr_g3);
9fe96934 2144 num_comp = 9;
3f0d4560
AK		 2145 } else {
2146 pflashcomp = gen2_flash_types;
2147 filehdr_size = sizeof(struct flash_file_hdr_g2);
9fe96934 2148 num_comp = 8;
84517482 2149 }
9fe96934
SB		 2150 for (i = 0; i < num_comp; i++) {
2151 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2152 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2153 continue;
3f0d4560
AK		 2154 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2155 (!be_flash_redboot(adapter, fw->data,
2156 pflashcomp[i].offset, pflashcomp[i].size,
2157 filehdr_size)))
2158 continue;
2159 p = fw->data;
2160 p += filehdr_size + pflashcomp[i].offset
2161 + (num_of_images * sizeof(struct image_hdr));
2162 if (p + pflashcomp[i].size > fw->data + fw->size)
84517482 2163 return -1;
3f0d4560
AK		 2164 total_bytes = pflashcomp[i].size;
2165 while (total_bytes) {
2166 if (total_bytes > 32*1024)
2167 num_bytes = 32*1024;
2168 else
2169 num_bytes = total_bytes;
2170 total_bytes -= num_bytes;
2171
2172 if (!total_bytes)
2173 flash_op = FLASHROM_OPER_FLASH;
2174 else
2175 flash_op = FLASHROM_OPER_SAVE;
2176 memcpy(req->params.data_buf, p, num_bytes);
2177 p += num_bytes;
2178 status = be_cmd_write_flashrom(adapter, flash_cmd,
2179 pflashcomp[i].optype, flash_op, num_bytes);
2180 if (status) {
2181 dev_err(&adapter->pdev->dev,
2182 "cmd to write to flash rom failed.\n");
2183 return -1;
2184 }
2185 yield();
84517482 2186 }
84517482 2187 }
84517482
AK		 2188 return 0;
2189}
2190
3f0d4560
AK		 2191static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2192{
2193 if (fhdr == NULL)
2194 return 0;
2195 if (fhdr->build[0] == '3')
2196 return BE_GEN3;
2197 else if (fhdr->build[0] == '2')
2198 return BE_GEN2;
2199 else
2200 return 0;
2201}
2202
84517482
AK		 2203int be_load_fw(struct be_adapter *adapter, u8 *func)
2204{
2205 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2206 const struct firmware *fw;
3f0d4560
AK		 2207 struct flash_file_hdr_g2 *fhdr;
2208 struct flash_file_hdr_g3 *fhdr3;
2209 struct image_hdr *img_hdr_ptr = NULL;
84517482 2210 struct be_dma_mem flash_cmd;
8b93b710 2211 int status, i = 0, num_imgs = 0;
84517482 2212 const u8 *p;
84517482 2213
84517482
AK		 2214 strcpy(fw_file, func);
2215
2216 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2217 if (status)
2218 goto fw_exit;
2219
2220 p = fw->data;
3f0d4560 2221 fhdr = (struct flash_file_hdr_g2 *) p;
84517482
AK		 2222 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2223
84517482
AK		 2224 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2225 flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
2226 &flash_cmd.dma);
2227 if (!flash_cmd.va) {
2228 status = -ENOMEM;
2229 dev_err(&adapter->pdev->dev,
2230 "Memory allocation failure while flashing\n");
2231 goto fw_exit;
2232 }
2233
3f0d4560
AK		 2234 if ((adapter->generation == BE_GEN3) &&
2235 (get_ufigen_type(fhdr) == BE_GEN3)) {
2236 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
8b93b710
AK		 2237 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2238 for (i = 0; i < num_imgs; i++) {
3f0d4560
AK		 2239 img_hdr_ptr = (struct image_hdr *) (fw->data +
2240 (sizeof(struct flash_file_hdr_g3) +
8b93b710
AK		 2241 i * sizeof(struct image_hdr)));
2242 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2243 status = be_flash_data(adapter, fw, &flash_cmd,
2244 num_imgs);
3f0d4560
AK		 2245 }
2246 } else if ((adapter->generation == BE_GEN2) &&
2247 (get_ufigen_type(fhdr) == BE_GEN2)) {
2248 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2249 } else {
2250 dev_err(&adapter->pdev->dev,
2251 "UFI and Interface are not compatible for flashing\n");
2252 status = -1;
84517482
AK		 2253 }
2254
2255 pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
2256 flash_cmd.dma);
2257 if (status) {
2258 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2259 goto fw_exit;
2260 }
2261
af901ca1 2262 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
84517482
AK		 2263
2264fw_exit:
2265 release_firmware(fw);
2266 return status;
2267}
2268
6b7c5b94
SP		 2269static struct net_device_ops be_netdev_ops = {
2270 .ndo_open = be_open,
2271 .ndo_stop = be_close,
2272 .ndo_start_xmit = be_xmit,
2273 .ndo_get_stats = be_get_stats,
2274 .ndo_set_rx_mode = be_set_multicast_list,
2275 .ndo_set_mac_address = be_mac_addr_set,
2276 .ndo_change_mtu = be_change_mtu,
2277 .ndo_validate_addr = eth_validate_addr,
2278 .ndo_vlan_rx_register = be_vlan_register,
2279 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2280 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
64600ea5 2281 .ndo_set_vf_mac = be_set_vf_mac,
1da87b7f 2282 .ndo_set_vf_vlan = be_set_vf_vlan,
e1d18735 2283 .ndo_set_vf_tx_rate = be_set_vf_tx_rate,
64600ea5 2284 .ndo_get_vf_config = be_get_vf_config
6b7c5b94
SP		 2285};
2286
2287static void be_netdev_init(struct net_device *netdev)
2288{
2289 struct be_adapter *adapter = netdev_priv(netdev);
2290
2291 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
583e3f34 2292 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
49e4b847 2293 NETIF_F_GRO | NETIF_F_TSO6;
6b7c5b94 2294
51c59870
AK		 2295 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
2296
6b7c5b94
SP		 2297 netdev->flags |= IFF_MULTICAST;
2298
728a9972
AK		 2299 adapter->rx_csum = true;
2300
9e90c961
AK		 2301 /* Default settings for Rx and Tx flow control */
2302 adapter->rx_fc = true;
2303 adapter->tx_fc = true;
2304
c190e3c8
AK		 2305 netif_set_gso_max_size(netdev, 65535);
2306
6b7c5b94
SP		 2307 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2308
2309 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2310
6b7c5b94
SP		 2311 netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
2312 BE_NAPI_WEIGHT);
5fb379ee 2313 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
6b7c5b94
SP		 2314 BE_NAPI_WEIGHT);
2315
2316 netif_carrier_off(netdev);
2317 netif_stop_queue(netdev);
2318}
2319
2320static void be_unmap_pci_bars(struct be_adapter *adapter)
2321{
8788fdc2
SP		 2322 if (adapter->csr)
2323 iounmap(adapter->csr);
2324 if (adapter->db)
2325 iounmap(adapter->db);
ba343c77 2326 if (adapter->pcicfg && be_physfn(adapter))
8788fdc2 2327 iounmap(adapter->pcicfg);
6b7c5b94
SP		 2328}
2329
2330static int be_map_pci_bars(struct be_adapter *adapter)
2331{
2332 u8 __iomem *addr;
ba343c77 2333 int pcicfg_reg, db_reg;
6b7c5b94 2334
ba343c77
SB		 2335 if (be_physfn(adapter)) {
2336 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2337 pci_resource_len(adapter->pdev, 2));
2338 if (addr == NULL)
2339 return -ENOMEM;
2340 adapter->csr = addr;
2341 }
6b7c5b94 2342
ba343c77 2343 if (adapter->generation == BE_GEN2) {
7b139c83 2344 pcicfg_reg = 1;
ba343c77
SB		 2345 db_reg = 4;
2346 } else {
7b139c83 2347 pcicfg_reg = 0;
ba343c77
SB		 2348 if (be_physfn(adapter))
2349 db_reg = 4;
2350 else
2351 db_reg = 0;
2352 }
2353 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
2354 pci_resource_len(adapter->pdev, db_reg));
6b7c5b94
SP		 2355 if (addr == NULL)
2356 goto pci_map_err;
ba343c77
SB		 2357 adapter->db = addr;
2358
2359 if (be_physfn(adapter)) {
2360 addr = ioremap_nocache(
2361 pci_resource_start(adapter->pdev, pcicfg_reg),
2362 pci_resource_len(adapter->pdev, pcicfg_reg));
2363 if (addr == NULL)
2364 goto pci_map_err;
2365 adapter->pcicfg = addr;
2366 } else
2367 adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
6b7c5b94
SP		 2368
2369 return 0;
2370pci_map_err:
2371 be_unmap_pci_bars(adapter);
2372 return -ENOMEM;
2373}
2374
2375
2376static void be_ctrl_cleanup(struct be_adapter *adapter)
2377{
8788fdc2 2378 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
6b7c5b94
SP		 2379
2380 be_unmap_pci_bars(adapter);
2381
2382 if (mem->va)
2383 pci_free_consistent(adapter->pdev, mem->size,
2384 mem->va, mem->dma);
e7b909a6
SP		 2385
2386 mem = &adapter->mc_cmd_mem;
2387 if (mem->va)
2388 pci_free_consistent(adapter->pdev, mem->size,
2389 mem->va, mem->dma);
6b7c5b94
SP		 2390}
2391
6b7c5b94
SP		 2392static int be_ctrl_init(struct be_adapter *adapter)
2393{
8788fdc2
SP		 2394 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2395 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
e7b909a6 2396 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
6b7c5b94 2397 int status;
6b7c5b94
SP		 2398
2399 status = be_map_pci_bars(adapter);
2400 if (status)
e7b909a6 2401 goto done;
6b7c5b94
SP		 2402
2403 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2404 mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
2405 mbox_mem_alloc->size, &mbox_mem_alloc->dma);
2406 if (!mbox_mem_alloc->va) {
e7b909a6
SP		 2407 status = -ENOMEM;
2408 goto unmap_pci_bars;
6b7c5b94 2409 }
e7b909a6 2410
6b7c5b94
SP		 2411 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2412 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2413 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2414 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
e7b909a6
SP		 2415
2416 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2417 mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
2418 &mc_cmd_mem->dma);
2419 if (mc_cmd_mem->va == NULL) {
2420 status = -ENOMEM;
2421 goto free_mbox;
2422 }
2423 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2424
8788fdc2
SP		 2425 spin_lock_init(&adapter->mbox_lock);
2426 spin_lock_init(&adapter->mcc_lock);
2427 spin_lock_init(&adapter->mcc_cq_lock);
a8f447bd 2428
dd131e76 2429 init_completion(&adapter->flash_compl);
cf588477 2430 pci_save_state(adapter->pdev);
6b7c5b94 2431 return 0;
e7b909a6
SP		 2432
2433free_mbox:
2434 pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
2435 mbox_mem_alloc->va, mbox_mem_alloc->dma);
2436
2437unmap_pci_bars:
2438 be_unmap_pci_bars(adapter);
2439
2440done:
2441 return status;
6b7c5b94
SP		 2442}
2443
2444static void be_stats_cleanup(struct be_adapter *adapter)
2445{
2446 struct be_stats_obj *stats = &adapter->stats;
2447 struct be_dma_mem *cmd = &stats->cmd;
2448
2449 if (cmd->va)
2450 pci_free_consistent(adapter->pdev, cmd->size,
2451 cmd->va, cmd->dma);
2452}
2453
2454static int be_stats_init(struct be_adapter *adapter)
2455{
2456 struct be_stats_obj *stats = &adapter->stats;
2457 struct be_dma_mem *cmd = &stats->cmd;
2458
2459 cmd->size = sizeof(struct be_cmd_req_get_stats);
2460 cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
2461 if (cmd->va == NULL)
2462 return -1;
d291b9af 2463 memset(cmd->va, 0, cmd->size);
6b7c5b94
SP		 2464 return 0;
2465}
2466
2467static void __devexit be_remove(struct pci_dev *pdev)
2468{
2469 struct be_adapter *adapter = pci_get_drvdata(pdev);
8d56ff11 2470
6b7c5b94
SP		 2471 if (!adapter)
2472 return;
2473
2474 unregister_netdev(adapter->netdev);
2475
5fb379ee
SP		 2476 be_clear(adapter);
2477
6b7c5b94
SP		 2478 be_stats_cleanup(adapter);
2479
2480 be_ctrl_cleanup(adapter);
2481
ba343c77
SB		 2482 be_sriov_disable(adapter);
2483
8d56ff11 2484 be_msix_disable(adapter);
6b7c5b94
SP		 2485
2486 pci_set_drvdata(pdev, NULL);
2487 pci_release_regions(pdev);
2488 pci_disable_device(pdev);
2489
2490 free_netdev(adapter->netdev);
2491}
2492
2243e2e9 2493static int be_get_config(struct be_adapter *adapter)
6b7c5b94 2494{
6b7c5b94 2495 int status;
2243e2e9 2496 u8 mac[ETH_ALEN];
6b7c5b94 2497
2243e2e9 2498 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
6b7c5b94
SP		 2499 if (status)
2500 return status;
2501
2243e2e9 2502 status = be_cmd_query_fw_cfg(adapter,
3486be29 2503 &adapter->port_num, &adapter->function_mode);
43a04fdc
SP		 2504 if (status)
2505 return status;
2506
2243e2e9 2507 memset(mac, 0, ETH_ALEN);
ba343c77
SB		 2508
2509 if (be_physfn(adapter)) {
2510 status = be_cmd_mac_addr_query(adapter, mac,
2243e2e9 2511 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
ca9e4988 2512
ba343c77
SB		 2513 if (status)
2514 return status;
ca9e4988 2515
ba343c77
SB		 2516 if (!is_valid_ether_addr(mac))
2517 return -EADDRNOTAVAIL;
2518
2519 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2520 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2521 }
6b7c5b94 2522
3486be29 2523 if (adapter->function_mode & 0x400)
82903e4b
AK		 2524 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2525 else
2526 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2527
2243e2e9 2528 return 0;
6b7c5b94
SP		 2529}
2530
2531static int __devinit be_probe(struct pci_dev *pdev,
2532 const struct pci_device_id *pdev_id)
2533{
2534 int status = 0;
2535 struct be_adapter *adapter;
2536 struct net_device *netdev;
6b7c5b94 2537
ba343c77 2538
6b7c5b94
SP		 2539 status = pci_enable_device(pdev);
2540 if (status)
2541 goto do_none;
2542
2543 status = pci_request_regions(pdev, DRV_NAME);
2544 if (status)
2545 goto disable_dev;
2546 pci_set_master(pdev);
2547
2548 netdev = alloc_etherdev(sizeof(struct be_adapter));
2549 if (netdev == NULL) {
2550 status = -ENOMEM;
2551 goto rel_reg;
2552 }
2553 adapter = netdev_priv(netdev);
7b139c83
AK		 2554
2555 switch (pdev->device) {
2556 case BE_DEVICE_ID1:
2557 case OC_DEVICE_ID1:
2558 adapter->generation = BE_GEN2;
2559 break;
2560 case BE_DEVICE_ID2:
2561 case OC_DEVICE_ID2:
2562 adapter->generation = BE_GEN3;
2563 break;
2564 default:
2565 adapter->generation = 0;
2566 }
2567
6b7c5b94
SP		 2568 adapter->pdev = pdev;
2569 pci_set_drvdata(pdev, adapter);
2570 adapter->netdev = netdev;
2243e2e9
SP		 2571 be_netdev_init(netdev);
2572 SET_NETDEV_DEV(netdev, &pdev->dev);
6b7c5b94
SP		 2573
2574 be_msix_enable(adapter);
2575
e930438c 2576 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6b7c5b94
SP		 2577 if (!status) {
2578 netdev->features |= NETIF_F_HIGHDMA;
2579 } else {
e930438c 2580 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6b7c5b94
SP		 2581 if (status) {
2582 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2583 goto free_netdev;
2584 }
2585 }
2586
ba343c77
SB		 2587 be_sriov_enable(adapter);
2588
6b7c5b94
SP		 2589 status = be_ctrl_init(adapter);
2590 if (status)
2591 goto free_netdev;
2592
2243e2e9 2593 /* sync up with fw's ready state */
ba343c77
SB		 2594 if (be_physfn(adapter)) {
2595 status = be_cmd_POST(adapter);
2596 if (status)
2597 goto ctrl_clean;
ba343c77 2598 }
6b7c5b94 2599
2243e2e9
SP		 2600 /* tell fw we're ready to fire cmds */
2601 status = be_cmd_fw_init(adapter);
6b7c5b94 2602 if (status)
2243e2e9
SP		 2603 goto ctrl_clean;
2604
556ae191
SB		 2605 if (be_physfn(adapter)) {
2606 status = be_cmd_reset_function(adapter);
2607 if (status)
2608 goto ctrl_clean;
2609 }
2610
2243e2e9
SP		 2611 status = be_stats_init(adapter);
2612 if (status)
2613 goto ctrl_clean;
2614
2615 status = be_get_config(adapter);
6b7c5b94
SP		 2616 if (status)
2617 goto stats_clean;
6b7c5b94
SP		 2618
2619 INIT_DELAYED_WORK(&adapter->work, be_worker);
6b7c5b94 2620
5fb379ee
SP		 2621 status = be_setup(adapter);
2622 if (status)
2623 goto stats_clean;
2243e2e9 2624
6b7c5b94
SP		 2625 status = register_netdev(netdev);
2626 if (status != 0)
5fb379ee 2627 goto unsetup;
6b7c5b94 2628
c4ca2374 2629 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
6b7c5b94
SP		 2630 return 0;
2631
5fb379ee
SP		 2632unsetup:
2633 be_clear(adapter);
6b7c5b94
SP		 2634stats_clean:
2635 be_stats_cleanup(adapter);
2636ctrl_clean:
2637 be_ctrl_cleanup(adapter);
2638free_netdev:
8d56ff11 2639 be_msix_disable(adapter);
ba343c77 2640 be_sriov_disable(adapter);
6b7c5b94 2641 free_netdev(adapter->netdev);
8d56ff11 2642 pci_set_drvdata(pdev, NULL);
6b7c5b94
SP		 2643rel_reg:
2644 pci_release_regions(pdev);
2645disable_dev:
2646 pci_disable_device(pdev);
2647do_none:
c4ca2374 2648 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
6b7c5b94
SP		 2649 return status;
2650}
2651
2652static int be_suspend(struct pci_dev *pdev, pm_message_t state)
2653{
2654 struct be_adapter *adapter = pci_get_drvdata(pdev);
2655 struct net_device *netdev = adapter->netdev;
2656
71d8d1b5
AK		 2657 if (adapter->wol)
2658 be_setup_wol(adapter, true);
2659
6b7c5b94
SP		 2660 netif_device_detach(netdev);
2661 if (netif_running(netdev)) {
2662 rtnl_lock();
2663 be_close(netdev);
2664 rtnl_unlock();
2665 }
9e90c961 2666 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
9b0365f1 2667 be_clear(adapter);
6b7c5b94
SP		 2668
2669 pci_save_state(pdev);
2670 pci_disable_device(pdev);
2671 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2672 return 0;
2673}
2674
2675static int be_resume(struct pci_dev *pdev)
2676{
2677 int status = 0;
2678 struct be_adapter *adapter = pci_get_drvdata(pdev);
2679 struct net_device *netdev = adapter->netdev;
2680
2681 netif_device_detach(netdev);
2682
2683 status = pci_enable_device(pdev);
2684 if (status)
2685 return status;
2686
2687 pci_set_power_state(pdev, 0);
2688 pci_restore_state(pdev);
2689
2243e2e9
SP		 2690 /* tell fw we're ready to fire cmds */
2691 status = be_cmd_fw_init(adapter);
2692 if (status)
2693 return status;
2694
9b0365f1 2695 be_setup(adapter);
6b7c5b94
SP		 2696 if (netif_running(netdev)) {
2697 rtnl_lock();
2698 be_open(netdev);
2699 rtnl_unlock();
2700 }
2701 netif_device_attach(netdev);
71d8d1b5
AK		 2702
2703 if (adapter->wol)
2704 be_setup_wol(adapter, false);
6b7c5b94
SP		 2705 return 0;
2706}
2707
82456b03
SP		 2708/*
2709 * An FLR will stop BE from DMAing any data.
2710 */
2711static void be_shutdown(struct pci_dev *pdev)
2712{
2713 struct be_adapter *adapter = pci_get_drvdata(pdev);
2714 struct net_device *netdev = adapter->netdev;
2715
2716 netif_device_detach(netdev);
2717
2718 be_cmd_reset_function(adapter);
2719
2720 if (adapter->wol)
2721 be_setup_wol(adapter, true);
2722
2723 pci_disable_device(pdev);
82456b03
SP		 2724}
2725
cf588477
SP		 2726static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
2727 pci_channel_state_t state)
2728{
2729 struct be_adapter *adapter = pci_get_drvdata(pdev);
2730 struct net_device *netdev = adapter->netdev;
2731
2732 dev_err(&adapter->pdev->dev, "EEH error detected\n");
2733
2734 adapter->eeh_err = true;
2735
2736 netif_device_detach(netdev);
2737
2738 if (netif_running(netdev)) {
2739 rtnl_lock();
2740 be_close(netdev);
2741 rtnl_unlock();
2742 }
2743 be_clear(adapter);
2744
2745 if (state == pci_channel_io_perm_failure)
2746 return PCI_ERS_RESULT_DISCONNECT;
2747
2748 pci_disable_device(pdev);
2749
2750 return PCI_ERS_RESULT_NEED_RESET;
2751}
2752
2753static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
2754{
2755 struct be_adapter *adapter = pci_get_drvdata(pdev);
2756 int status;
2757
2758 dev_info(&adapter->pdev->dev, "EEH reset\n");
2759 adapter->eeh_err = false;
2760
2761 status = pci_enable_device(pdev);
2762 if (status)
2763 return PCI_ERS_RESULT_DISCONNECT;
2764
2765 pci_set_master(pdev);
2766 pci_set_power_state(pdev, 0);
2767 pci_restore_state(pdev);
2768
2769 /* Check if card is ok and fw is ready */
2770 status = be_cmd_POST(adapter);
2771 if (status)
2772 return PCI_ERS_RESULT_DISCONNECT;
2773
2774 return PCI_ERS_RESULT_RECOVERED;
2775}
2776
2777static void be_eeh_resume(struct pci_dev *pdev)
2778{
2779 int status = 0;
2780 struct be_adapter *adapter = pci_get_drvdata(pdev);
2781 struct net_device *netdev = adapter->netdev;
2782
2783 dev_info(&adapter->pdev->dev, "EEH resume\n");
2784
2785 pci_save_state(pdev);
2786
2787 /* tell fw we're ready to fire cmds */
2788 status = be_cmd_fw_init(adapter);
2789 if (status)
2790 goto err;
2791
2792 status = be_setup(adapter);
2793 if (status)
2794 goto err;
2795
2796 if (netif_running(netdev)) {
2797 status = be_open(netdev);
2798 if (status)
2799 goto err;
2800 }
2801 netif_device_attach(netdev);
2802 return;
2803err:
2804 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
cf588477
SP		 2805}
2806
2807static struct pci_error_handlers be_eeh_handlers = {
2808 .error_detected = be_eeh_err_detected,
2809 .slot_reset = be_eeh_reset,
2810 .resume = be_eeh_resume,
2811};
2812
6b7c5b94
SP		 2813static struct pci_driver be_driver = {
2814 .name = DRV_NAME,
2815 .id_table = be_dev_ids,
2816 .probe = be_probe,
2817 .remove = be_remove,
2818 .suspend = be_suspend,
cf588477 2819 .resume = be_resume,
82456b03 2820 .shutdown = be_shutdown,
cf588477 2821 .err_handler = &be_eeh_handlers
6b7c5b94
SP		 2822};
2823
2824static int __init be_init_module(void)
2825{
8e95a202
JP		 2826 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
2827 rx_frag_size != 2048) {
6b7c5b94
SP		 2828 printk(KERN_WARNING DRV_NAME
2829 " : Module param rx_frag_size must be 2048/4096/8192."
2830 " Using 2048\n");
2831 rx_frag_size = 2048;
2832 }
6b7c5b94 2833
ba343c77
SB		 2834 if (num_vfs > 32) {
2835 printk(KERN_WARNING DRV_NAME
2836 " : Module param num_vfs must not be greater than 32."
2837 "Using 32\n");
2838 num_vfs = 32;
2839 }
2840
6b7c5b94
SP		 2841 return pci_register_driver(&be_driver);
2842}
2843module_init(be_init_module);
2844
2845static void __exit be_exit_module(void)
2846{
2847 pci_unregister_driver(&be_driver);
2848}
2849module_exit(be_exit_module);
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