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4330c2f2 GFT |
1 | /* |
2 | * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver | |
3 | * | |
4 | * Copyright 2008 JMicron Technology Corporation | |
5 | * http://www.jmicron.com/ | |
d3d584f5 | 6 | * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org> |
4330c2f2 | 7 | * |
3bf61c55 GFT |
8 | * Author: Guo-Fu Tseng <cooldavid@cooldavid.org> |
9 | * | |
4330c2f2 GFT |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | * | |
23 | */ | |
24 | ||
cd0ff491 | 25 | #ifndef __JME_H_INCLUDED__ |
3b70a6fa | 26 | #define __JME_H_INCLUDED__ |
d7699f87 GFT |
27 | |
28 | #define DRV_NAME "jme" | |
b34adbb0 | 29 | #define DRV_VERSION "1.0.8-jmmod" |
cd0ff491 | 30 | #define PFX DRV_NAME ": " |
d7699f87 | 31 | |
cd0ff491 GFT |
32 | #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250 |
33 | #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260 | |
8d27293f | 34 | |
cd0ff491 GFT |
35 | /* |
36 | * Message related definitions | |
37 | */ | |
38 | #define JME_DEF_MSG_ENABLE \ | |
39 | (NETIF_MSG_PROBE | \ | |
40 | NETIF_MSG_LINK | \ | |
41 | NETIF_MSG_RX_ERR | \ | |
42 | NETIF_MSG_TX_ERR | \ | |
43 | NETIF_MSG_HW) | |
44 | ||
937ef75a JP |
45 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) |
46 | #define pr_err(fmt, arg...) \ | |
47 | printk(KERN_ERR fmt, ##arg) | |
48 | #endif | |
49 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33) | |
50 | #define netdev_err(netdev, fmt, arg...) \ | |
51 | pr_err(fmt, ##arg) | |
52 | #endif | |
d7699f87 | 53 | |
3bf61c55 | 54 | #ifdef TX_DEBUG |
7ca9ebee GFT |
55 | #define tx_dbg(priv, fmt, args...) \ |
56 | printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args) | |
3bf61c55 | 57 | #else |
7ca9ebee GFT |
58 | #define tx_dbg(priv, fmt, args...) \ |
59 | do { \ | |
60 | if (0) \ | |
61 | printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \ | |
62 | } while (0) | |
3bf61c55 GFT |
63 | #endif |
64 | ||
7ca9ebee | 65 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33) |
cd0ff491 GFT |
66 | #define jme_msg(msglvl, type, priv, fmt, args...) \ |
67 | if (netif_msg_##type(priv)) \ | |
68 | printk(msglvl "%s: " fmt, (priv)->dev->name, ## args) | |
3bf61c55 | 69 | |
cd0ff491 GFT |
70 | #define msg_probe(priv, fmt, args...) \ |
71 | jme_msg(KERN_INFO, probe, priv, fmt, ## args) | |
29bdd921 | 72 | |
cd0ff491 GFT |
73 | #define msg_link(priv, fmt, args...) \ |
74 | jme_msg(KERN_INFO, link, priv, fmt, ## args) | |
79ce639c | 75 | |
cd0ff491 GFT |
76 | #define msg_intr(priv, fmt, args...) \ |
77 | jme_msg(KERN_INFO, intr, priv, fmt, ## args) | |
78 | ||
79 | #define msg_rx_err(priv, fmt, args...) \ | |
80 | jme_msg(KERN_ERR, rx_err, priv, fmt, ## args) | |
b3821cc5 | 81 | |
cd0ff491 GFT |
82 | #define msg_rx_status(priv, fmt, args...) \ |
83 | jme_msg(KERN_INFO, rx_status, priv, fmt, ## args) | |
4330c2f2 | 84 | |
cd0ff491 GFT |
85 | #define msg_tx_err(priv, fmt, args...) \ |
86 | jme_msg(KERN_ERR, tx_err, priv, fmt, ## args) | |
4330c2f2 | 87 | |
cd0ff491 GFT |
88 | #define msg_tx_done(priv, fmt, args...) \ |
89 | jme_msg(KERN_INFO, tx_done, priv, fmt, ## args) | |
d7699f87 | 90 | |
cd0ff491 GFT |
91 | #define msg_tx_queued(priv, fmt, args...) \ |
92 | jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args) | |
93 | ||
94 | #define msg_hw(priv, fmt, args...) \ | |
95 | jme_msg(KERN_ERR, hw, priv, fmt, ## args) | |
937ef75a JP |
96 | |
97 | #define netif_info(priv, type, dev, fmt, args...) \ | |
98 | msg_ ## type(priv, fmt, ## args) | |
99 | #define netif_err(priv, type, dev, fmt, args...) \ | |
100 | msg_ ## type(priv, fmt, ## args) | |
7ca9ebee | 101 | #endif |
cd0ff491 | 102 | |
1a0b42f4 MM |
103 | #ifndef NETIF_F_TSO6 |
104 | #define NETIF_F_TSO6 0 | |
105 | #endif | |
106 | #ifndef NETIF_F_IPV6_CSUM | |
107 | #define NETIF_F_IPV6_CSUM 0 | |
108 | #endif | |
109 | ||
cd0ff491 GFT |
110 | /* |
111 | * Extra PCI Configuration space interface | |
112 | */ | |
113 | #define PCI_DCSR_MRRS 0x59 | |
114 | #define PCI_DCSR_MRRS_MASK 0x70 | |
115 | ||
116 | enum pci_dcsr_mrrs_vals { | |
4330c2f2 GFT |
117 | MRRS_128B = 0x00, |
118 | MRRS_256B = 0x10, | |
119 | MRRS_512B = 0x20, | |
120 | MRRS_1024B = 0x30, | |
121 | MRRS_2048B = 0x40, | |
122 | MRRS_4096B = 0x50, | |
123 | }; | |
d7699f87 | 124 | |
cd0ff491 GFT |
125 | #define PCI_SPI 0xB0 |
126 | ||
127 | enum pci_spi_bits { | |
128 | SPI_EN = 0x10, | |
129 | SPI_MISO = 0x08, | |
130 | SPI_MOSI = 0x04, | |
131 | SPI_SCLK = 0x02, | |
132 | SPI_CS = 0x01, | |
133 | }; | |
134 | ||
135 | struct jme_spi_op { | |
136 | void __user *uwbuf; | |
137 | void __user *urbuf; | |
138 | __u8 wn; /* Number of write actions */ | |
139 | __u8 rn; /* Number of read actions */ | |
140 | __u8 bitn; /* Number of bits per action */ | |
141 | __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/ | |
142 | __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */ | |
143 | ||
144 | /* Internal use only */ | |
145 | u8 *kwbuf; | |
146 | u8 *krbuf; | |
147 | u8 sr; | |
148 | u16 halfclk; /* Half of clock cycle calculated from spd, in ns */ | |
149 | }; | |
79ce639c | 150 | |
cd0ff491 GFT |
151 | enum jme_spi_op_bits { |
152 | SPI_MODE_CPHA = 0x01, | |
153 | SPI_MODE_CPOL = 0x02, | |
154 | SPI_MODE_DUP = 0x80, | |
155 | }; | |
156 | ||
157 | #define HALF_US 500 /* 500 ns */ | |
158 | #define JMESPIIOCTL SIOCDEVPRIVATE | |
159 | ||
ed457bcc GFT |
160 | #define PCI_PRIV_PE1 0xE4 |
161 | ||
162 | enum pci_priv_pe1_bit_masks { | |
163 | PE1_ASPMSUPRT = 0x00000003, /* | |
164 | * RW: | |
165 | * Aspm_support[1:0] | |
166 | * (R/W Port of 5C[11:10]) | |
167 | */ | |
168 | PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */ | |
169 | PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */ | |
170 | PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */ | |
171 | PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */ | |
172 | PE1_GPREG0 = 0x0000FF00, /* | |
173 | * SRW: | |
174 | * Cfg_gp_reg0 | |
175 | * [7:6] phy_giga BG control | |
176 | * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#) | |
177 | * [4:0] Reserved | |
178 | */ | |
179 | PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */ | |
180 | PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */ | |
181 | PE1_REVID = 0xFF000000, /* RO: Rev ID */ | |
182 | }; | |
183 | ||
184 | enum pci_priv_pe1_values { | |
185 | PE1_GPREG0_ENBG = 0x00000000, /* en BG */ | |
186 | PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */ | |
187 | PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */ | |
188 | PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */ | |
189 | }; | |
190 | ||
cd0ff491 GFT |
191 | /* |
192 | * Dynamic(adaptive)/Static PCC values | |
193 | */ | |
3bf61c55 | 194 | enum dynamic_pcc_values { |
192570e0 | 195 | PCC_OFF = 0, |
3bf61c55 GFT |
196 | PCC_P1 = 1, |
197 | PCC_P2 = 2, | |
198 | PCC_P3 = 3, | |
199 | ||
192570e0 | 200 | PCC_OFF_TO = 0, |
3bf61c55 | 201 | PCC_P1_TO = 1, |
192570e0 GFT |
202 | PCC_P2_TO = 64, |
203 | PCC_P3_TO = 128, | |
3bf61c55 | 204 | |
192570e0 | 205 | PCC_OFF_CNT = 0, |
3bf61c55 | 206 | PCC_P1_CNT = 1, |
192570e0 GFT |
207 | PCC_P2_CNT = 16, |
208 | PCC_P3_CNT = 32, | |
3bf61c55 GFT |
209 | }; |
210 | struct dynpcc_info { | |
3bf61c55 GFT |
211 | unsigned long last_bytes; |
212 | unsigned long last_pkts; | |
79ce639c | 213 | unsigned long intr_cnt; |
3bf61c55 GFT |
214 | unsigned char cur; |
215 | unsigned char attempt; | |
216 | unsigned char cnt; | |
217 | }; | |
79ce639c | 218 | #define PCC_INTERVAL_US 100000 |
cd0ff491 GFT |
219 | #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US)) |
220 | #define PCC_P3_THRESHOLD (2 * 1024 * 1024) | |
79ce639c GFT |
221 | #define PCC_P2_THRESHOLD 800 |
222 | #define PCC_INTR_THRESHOLD 800 | |
47220951 | 223 | #define PCC_TX_TO 1000 |
b3821cc5 | 224 | #define PCC_TX_CNT 8 |
3bf61c55 | 225 | |
d7699f87 GFT |
226 | /* |
227 | * TX/RX Descriptors | |
4330c2f2 | 228 | * |
cd0ff491 | 229 | * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024 |
d7699f87 | 230 | */ |
4330c2f2 | 231 | #define RING_DESC_ALIGN 16 /* Descriptor alignment */ |
d7699f87 GFT |
232 | #define TX_DESC_SIZE 16 |
233 | #define TX_RING_NR 8 | |
cd0ff491 | 234 | #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN) |
d7699f87 | 235 | |
3bf61c55 | 236 | struct txdesc { |
d7699f87 | 237 | union { |
cd0ff491 GFT |
238 | __u8 all[16]; |
239 | __le32 dw[4]; | |
d7699f87 GFT |
240 | struct { |
241 | /* DW0 */ | |
cd0ff491 GFT |
242 | __le16 vlan; |
243 | __u8 rsv1; | |
244 | __u8 flags; | |
d7699f87 GFT |
245 | |
246 | /* DW1 */ | |
cd0ff491 GFT |
247 | __le16 datalen; |
248 | __le16 mss; | |
d7699f87 GFT |
249 | |
250 | /* DW2 */ | |
cd0ff491 GFT |
251 | __le16 pktsize; |
252 | __le16 rsv2; | |
d7699f87 GFT |
253 | |
254 | /* DW3 */ | |
cd0ff491 | 255 | __le32 bufaddr; |
d7699f87 | 256 | } desc1; |
3bf61c55 GFT |
257 | struct { |
258 | /* DW0 */ | |
cd0ff491 GFT |
259 | __le16 rsv1; |
260 | __u8 rsv2; | |
261 | __u8 flags; | |
3bf61c55 GFT |
262 | |
263 | /* DW1 */ | |
cd0ff491 GFT |
264 | __le16 datalen; |
265 | __le16 rsv3; | |
3bf61c55 GFT |
266 | |
267 | /* DW2 */ | |
cd0ff491 | 268 | __le32 bufaddrh; |
3bf61c55 GFT |
269 | |
270 | /* DW3 */ | |
cd0ff491 | 271 | __le32 bufaddrl; |
3bf61c55 | 272 | } desc2; |
8c198884 GFT |
273 | struct { |
274 | /* DW0 */ | |
cd0ff491 GFT |
275 | __u8 ehdrsz; |
276 | __u8 rsv1; | |
277 | __u8 rsv2; | |
278 | __u8 flags; | |
8c198884 GFT |
279 | |
280 | /* DW1 */ | |
cd0ff491 GFT |
281 | __le16 trycnt; |
282 | __le16 segcnt; | |
8c198884 GFT |
283 | |
284 | /* DW2 */ | |
cd0ff491 GFT |
285 | __le16 pktsz; |
286 | __le16 rsv3; | |
8c198884 GFT |
287 | |
288 | /* DW3 */ | |
cd0ff491 | 289 | __le32 bufaddrl; |
8c198884 | 290 | } descwb; |
d7699f87 GFT |
291 | }; |
292 | }; | |
cd0ff491 | 293 | |
8c198884 | 294 | enum jme_txdesc_flags_bits { |
d7699f87 GFT |
295 | TXFLAG_OWN = 0x80, |
296 | TXFLAG_INT = 0x40, | |
3bf61c55 | 297 | TXFLAG_64BIT = 0x20, |
d7699f87 GFT |
298 | TXFLAG_TCPCS = 0x10, |
299 | TXFLAG_UDPCS = 0x08, | |
300 | TXFLAG_IPCS = 0x04, | |
301 | TXFLAG_LSEN = 0x02, | |
302 | TXFLAG_TAGON = 0x01, | |
303 | }; | |
cd0ff491 | 304 | |
b3821cc5 | 305 | #define TXDESC_MSS_SHIFT 2 |
0ede469c | 306 | enum jme_txwbdesc_flags_bits { |
8c198884 GFT |
307 | TXWBFLAG_OWN = 0x80, |
308 | TXWBFLAG_INT = 0x40, | |
309 | TXWBFLAG_TMOUT = 0x20, | |
310 | TXWBFLAG_TRYOUT = 0x10, | |
311 | TXWBFLAG_COL = 0x08, | |
312 | ||
313 | TXWBFLAG_ALLERR = TXWBFLAG_TMOUT | | |
314 | TXWBFLAG_TRYOUT | | |
315 | TXWBFLAG_COL, | |
316 | }; | |
d7699f87 | 317 | |
d7699f87 GFT |
318 | #define RX_DESC_SIZE 16 |
319 | #define RX_RING_NR 4 | |
cd0ff491 | 320 | #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN) |
d7699f87 | 321 | #define RX_BUF_DMA_ALIGN 8 |
3bf61c55 | 322 | #define RX_PREPAD_SIZE 10 |
79ce639c GFT |
323 | #define ETH_CRC_LEN 2 |
324 | #define RX_VLANHDR_LEN 2 | |
325 | #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \ | |
326 | ETH_HLEN + \ | |
327 | ETH_CRC_LEN + \ | |
328 | RX_VLANHDR_LEN + \ | |
329 | RX_BUF_DMA_ALIGN) | |
d7699f87 | 330 | |
3bf61c55 | 331 | struct rxdesc { |
d7699f87 | 332 | union { |
cd0ff491 GFT |
333 | __u8 all[16]; |
334 | __le32 dw[4]; | |
d7699f87 GFT |
335 | struct { |
336 | /* DW0 */ | |
cd0ff491 GFT |
337 | __le16 rsv2; |
338 | __u8 rsv1; | |
339 | __u8 flags; | |
d7699f87 GFT |
340 | |
341 | /* DW1 */ | |
cd0ff491 GFT |
342 | __le16 datalen; |
343 | __le16 wbcpl; | |
d7699f87 GFT |
344 | |
345 | /* DW2 */ | |
cd0ff491 | 346 | __le32 bufaddrh; |
d7699f87 GFT |
347 | |
348 | /* DW3 */ | |
cd0ff491 | 349 | __le32 bufaddrl; |
d7699f87 GFT |
350 | } desc1; |
351 | struct { | |
352 | /* DW0 */ | |
cd0ff491 GFT |
353 | __le16 vlan; |
354 | __le16 flags; | |
d7699f87 GFT |
355 | |
356 | /* DW1 */ | |
cd0ff491 GFT |
357 | __le16 framesize; |
358 | __u8 errstat; | |
359 | __u8 desccnt; | |
d7699f87 GFT |
360 | |
361 | /* DW2 */ | |
cd0ff491 | 362 | __le32 rsshash; |
d7699f87 GFT |
363 | |
364 | /* DW3 */ | |
cd0ff491 GFT |
365 | __u8 hashfun; |
366 | __u8 hashtype; | |
367 | __le16 resrv; | |
d7699f87 GFT |
368 | } descwb; |
369 | }; | |
370 | }; | |
cd0ff491 | 371 | |
d7699f87 GFT |
372 | enum jme_rxdesc_flags_bits { |
373 | RXFLAG_OWN = 0x80, | |
374 | RXFLAG_INT = 0x40, | |
375 | RXFLAG_64BIT = 0x20, | |
376 | }; | |
cd0ff491 | 377 | |
d7699f87 | 378 | enum jme_rxwbdesc_flags_bits { |
4330c2f2 GFT |
379 | RXWBFLAG_OWN = 0x8000, |
380 | RXWBFLAG_INT = 0x4000, | |
381 | RXWBFLAG_MF = 0x2000, | |
382 | RXWBFLAG_64BIT = 0x2000, | |
383 | RXWBFLAG_TCPON = 0x1000, | |
384 | RXWBFLAG_UDPON = 0x0800, | |
385 | RXWBFLAG_IPCS = 0x0400, | |
386 | RXWBFLAG_TCPCS = 0x0200, | |
387 | RXWBFLAG_UDPCS = 0x0100, | |
388 | RXWBFLAG_TAGON = 0x0080, | |
389 | RXWBFLAG_IPV4 = 0x0040, | |
390 | RXWBFLAG_IPV6 = 0x0020, | |
391 | RXWBFLAG_PAUSE = 0x0010, | |
392 | RXWBFLAG_MAGIC = 0x0008, | |
393 | RXWBFLAG_WAKEUP = 0x0004, | |
394 | RXWBFLAG_DEST = 0x0003, | |
395 | RXWBFLAG_DEST_UNI = 0x0001, | |
396 | RXWBFLAG_DEST_MUL = 0x0002, | |
397 | RXWBFLAG_DEST_BRO = 0x0003, | |
d7699f87 | 398 | }; |
cd0ff491 | 399 | |
d7699f87 GFT |
400 | enum jme_rxwbdesc_desccnt_mask { |
401 | RXWBDCNT_WBCPL = 0x80, | |
402 | RXWBDCNT_DCNT = 0x7F, | |
403 | }; | |
cd0ff491 | 404 | |
4330c2f2 GFT |
405 | enum jme_rxwbdesc_errstat_bits { |
406 | RXWBERR_LIMIT = 0x80, | |
407 | RXWBERR_MIIER = 0x40, | |
408 | RXWBERR_NIBON = 0x20, | |
409 | RXWBERR_COLON = 0x10, | |
410 | RXWBERR_ABORT = 0x08, | |
411 | RXWBERR_SHORT = 0x04, | |
412 | RXWBERR_OVERUN = 0x02, | |
413 | RXWBERR_CRCERR = 0x01, | |
414 | RXWBERR_ALLERR = 0xFF, | |
415 | }; | |
416 | ||
cd0ff491 GFT |
417 | /* |
418 | * Buffer information corresponding to ring descriptors. | |
419 | */ | |
4330c2f2 GFT |
420 | struct jme_buffer_info { |
421 | struct sk_buff *skb; | |
422 | dma_addr_t mapping; | |
423 | int len; | |
3bf61c55 | 424 | int nr_desc; |
cdcdc9eb | 425 | unsigned long start_xmit; |
4330c2f2 | 426 | }; |
d7699f87 | 427 | |
cd0ff491 GFT |
428 | /* |
429 | * The structure holding buffer information and ring descriptors all together. | |
430 | */ | |
d7699f87 | 431 | struct jme_ring { |
cd0ff491 GFT |
432 | void *alloc; /* pointer to allocated memory */ |
433 | void *desc; /* pointer to ring memory */ | |
434 | dma_addr_t dmaalloc; /* phys address of ring alloc */ | |
435 | dma_addr_t dma; /* phys address for ring dma */ | |
d7699f87 | 436 | |
4330c2f2 | 437 | /* Buffer information corresponding to each descriptor */ |
0ede469c | 438 | struct jme_buffer_info *bufinf; |
d7699f87 | 439 | |
cd0ff491 GFT |
440 | int next_to_use; |
441 | atomic_t next_to_clean; | |
79ce639c | 442 | atomic_t nr_free; |
d7699f87 GFT |
443 | }; |
444 | ||
3b70a6fa GFT |
445 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18) |
446 | #define false 0 | |
447 | #define true 0 | |
448 | #define netdev_alloc_skb(dev, len) dev_alloc_skb(len) | |
449 | #define PCI_VENDOR_ID_JMICRON 0x197B | |
450 | #endif | |
451 | ||
452 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19) | |
453 | #define PCI_VDEVICE(vendor, device) \ | |
454 | PCI_VENDOR_ID_##vendor, (device), \ | |
455 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 | |
456 | #endif | |
457 | ||
85776f33 GFT |
458 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) |
459 | #define NET_STAT(priv) priv->stats | |
460 | #define NETDEV_GET_STATS(netdev, fun_ptr) \ | |
461 | netdev->get_stats = fun_ptr | |
462 | #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats; | |
e5169728 GFT |
463 | /* |
464 | * CentOS 5.5 have *_hdr helpers back-ported | |
465 | */ | |
466 | #ifdef RHEL_RELEASE_CODE | |
467 | #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,5) | |
468 | #define __DEFINE_IPHDR_HELPERS__ | |
469 | #endif | |
470 | #else | |
471 | #define __DEFINE_IPHDR_HELPERS__ | |
472 | #endif | |
473 | #else | |
474 | #define NET_STAT(priv) (priv->dev->stats) | |
475 | #define NETDEV_GET_STATS(netdev, fun_ptr) | |
476 | #define DECLARE_NET_DEVICE_STATS | |
477 | #endif | |
478 | ||
479 | #ifdef __DEFINE_IPHDR_HELPERS__ | |
3b70a6fa GFT |
480 | static inline struct iphdr *ip_hdr(const struct sk_buff *skb) |
481 | { | |
482 | return skb->nh.iph; | |
483 | } | |
484 | ||
485 | static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb) | |
486 | { | |
487 | return skb->nh.ipv6h; | |
488 | } | |
489 | ||
490 | static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb) | |
491 | { | |
492 | return skb->h.th; | |
493 | } | |
85776f33 | 494 | #endif |
3bf61c55 | 495 | |
85776f33 GFT |
496 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) |
497 | #define DECLARE_NAPI_STRUCT | |
498 | #define NETIF_NAPI_SET(dev, napis, pollfn, q) \ | |
499 | dev->poll = pollfn; \ | |
500 | dev->weight = q; | |
501 | #define JME_NAPI_HOLDER(holder) struct net_device *holder | |
502 | #define JME_NAPI_WEIGHT(w) int *w | |
503 | #define JME_NAPI_WEIGHT_VAL(w) *w | |
504 | #define JME_NAPI_WEIGHT_SET(w, r) *w = r | |
3b70a6fa | 505 | #define DECLARE_NETDEV struct net_device *netdev = jme->dev; |
85776f33 GFT |
506 | #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev) |
507 | #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev); | |
508 | #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev); | |
509 | #define JME_RX_SCHEDULE_PREP(priv) \ | |
510 | netif_rx_schedule_prep(priv->dev) | |
511 | #define JME_RX_SCHEDULE(priv) \ | |
512 | __netif_rx_schedule(priv->dev); | |
0ede469c | 513 | #else |
3b70a6fa GFT |
514 | #define DECLARE_NAPI_STRUCT struct napi_struct napi; |
515 | #define NETIF_NAPI_SET(dev, napis, pollfn, q) \ | |
516 | netif_napi_add(dev, napis, pollfn, q); | |
517 | #define JME_NAPI_HOLDER(holder) struct napi_struct *holder | |
518 | #define JME_NAPI_WEIGHT(w) int w | |
519 | #define JME_NAPI_WEIGHT_VAL(w) w | |
520 | #define JME_NAPI_WEIGHT_SET(w, r) | |
521 | #define DECLARE_NETDEV | |
522 | #define JME_RX_COMPLETE(dev, napis) napi_complete(napis) | |
523 | #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); | |
524 | #define JME_NAPI_DISABLE(priv) \ | |
525 | if (!napi_disable_pending(&priv->napi)) \ | |
526 | napi_disable(&priv->napi); | |
527 | #define JME_RX_SCHEDULE_PREP(priv) \ | |
528 | napi_schedule_prep(&priv->napi) | |
529 | #define JME_RX_SCHEDULE(priv) \ | |
530 | __napi_schedule(&priv->napi); | |
85776f33 | 531 | #endif |
cdcdc9eb | 532 | |
d7699f87 GFT |
533 | /* |
534 | * Jmac Adapter Private data | |
535 | */ | |
536 | struct jme_adapter { | |
cd0ff491 GFT |
537 | struct pci_dev *pdev; |
538 | struct net_device *dev; | |
539 | void __iomem *regs; | |
d7699f87 GFT |
540 | struct mii_if_info mii_if; |
541 | struct jme_ring rxring[RX_RING_NR]; | |
542 | struct jme_ring txring[TX_RING_NR]; | |
d7699f87 | 543 | spinlock_t phy_lock; |
fcf45b4c | 544 | spinlock_t macaddr_lock; |
8c198884 | 545 | spinlock_t rxmcs_lock; |
fcf45b4c | 546 | struct tasklet_struct rxempty_task; |
4330c2f2 GFT |
547 | struct tasklet_struct rxclean_task; |
548 | struct tasklet_struct txclean_task; | |
549 | struct tasklet_struct linkch_task; | |
79ce639c | 550 | struct tasklet_struct pcc_task; |
cd0ff491 GFT |
551 | unsigned long flags; |
552 | u32 reg_txcs; | |
553 | u32 reg_txpfc; | |
554 | u32 reg_rxcs; | |
555 | u32 reg_rxmcs; | |
556 | u32 reg_ghc; | |
557 | u32 reg_pmcs; | |
dc4185bd | 558 | u32 reg_gpreg1; |
cd0ff491 GFT |
559 | u32 phylink; |
560 | u32 tx_ring_size; | |
561 | u32 tx_ring_mask; | |
562 | u32 tx_wake_threshold; | |
563 | u32 rx_ring_size; | |
564 | u32 rx_ring_mask; | |
565 | u8 mrrs; | |
566 | unsigned int fpgaver; | |
98ef18f1 GFT |
567 | u8 chiprev; |
568 | u8 chip_main_rev; | |
569 | u8 chip_sub_rev; | |
570 | u8 pcirev; | |
cd0ff491 | 571 | u32 msg_enable; |
29bdd921 GFT |
572 | struct ethtool_cmd old_ecmd; |
573 | unsigned int old_mtu; | |
cd0ff491 | 574 | struct vlan_group *vlgrp; |
3bf61c55 GFT |
575 | struct dynpcc_info dpi; |
576 | atomic_t intr_sem; | |
fcf45b4c GFT |
577 | atomic_t link_changing; |
578 | atomic_t tx_cleaning; | |
579 | atomic_t rx_cleaning; | |
192570e0 | 580 | atomic_t rx_empty; |
cdcdc9eb GFT |
581 | int (*jme_rx)(struct sk_buff *skb); |
582 | int (*jme_vlan_rx)(struct sk_buff *skb, | |
583 | struct vlan_group *grp, | |
584 | unsigned short vlan_tag); | |
0a0df947 GFT |
585 | |
586 | u8 flag_run_asd; /* Is Auto Speed Down polling function running*/ | |
587 | u32 mc_count; /* second counter as RJ45 is attached */ | |
588 | u8 flag_media_connected; /* Because PHY 0x13 is read and clear, we need to record it */ | |
589 | struct timer_list asd_timer; | |
590 | ||
591 | ||
cdcdc9eb | 592 | DECLARE_NAPI_STRUCT |
3bf61c55 | 593 | DECLARE_NET_DEVICE_STATS |
d7699f87 | 594 | }; |
cd0ff491 | 595 | |
3b70a6fa GFT |
596 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) |
597 | static struct net_device_stats * | |
598 | jme_get_stats(struct net_device *netdev) | |
599 | { | |
600 | struct jme_adapter *jme = netdev_priv(netdev); | |
601 | return &jme->stats; | |
602 | } | |
603 | #endif | |
604 | ||
79ce639c | 605 | enum jme_flags_bits { |
cd0ff491 GFT |
606 | JME_FLAG_MSI = 1, |
607 | JME_FLAG_SSET = 2, | |
608 | JME_FLAG_TXCSUM = 3, | |
609 | JME_FLAG_TSO = 4, | |
610 | JME_FLAG_POLL = 5, | |
611 | JME_FLAG_SHUTDOWN = 6, | |
8c198884 | 612 | }; |
cd0ff491 GFT |
613 | |
614 | #define TX_TIMEOUT (5 * HZ) | |
0a0df947 | 615 | #define JME_REG_LEN 0x500 |
cd0ff491 | 616 | #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 |
8c198884 | 617 | |
85776f33 | 618 | #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) |
7ee473a3 | 619 | static inline struct jme_adapter* |
85776f33 GFT |
620 | jme_napi_priv(struct net_device *holder) |
621 | { | |
7ee473a3 | 622 | struct jme_adapter *jme; |
85776f33 GFT |
623 | jme = netdev_priv(holder); |
624 | return jme; | |
625 | } | |
626 | #else | |
7ee473a3 | 627 | static inline struct jme_adapter* |
cdcdc9eb GFT |
628 | jme_napi_priv(struct napi_struct *napi) |
629 | { | |
7ee473a3 | 630 | struct jme_adapter *jme; |
cdcdc9eb GFT |
631 | jme = container_of(napi, struct jme_adapter, napi); |
632 | return jme; | |
633 | } | |
85776f33 | 634 | #endif |
d7699f87 GFT |
635 | |
636 | /* | |
637 | * MMaped I/O Resters | |
638 | */ | |
639 | enum jme_iomap_offsets { | |
4330c2f2 GFT |
640 | JME_MAC = 0x0000, |
641 | JME_PHY = 0x0400, | |
d7699f87 | 642 | JME_MISC = 0x0800, |
4330c2f2 | 643 | JME_RSS = 0x0C00, |
d7699f87 GFT |
644 | }; |
645 | ||
8c198884 GFT |
646 | enum jme_iomap_lens { |
647 | JME_MAC_LEN = 0x80, | |
648 | JME_PHY_LEN = 0x58, | |
649 | JME_MISC_LEN = 0x98, | |
650 | JME_RSS_LEN = 0xFF, | |
651 | }; | |
652 | ||
d7699f87 GFT |
653 | enum jme_iomap_regs { |
654 | JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */ | |
3bf61c55 GFT |
655 | JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */ |
656 | JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */ | |
d7699f87 GFT |
657 | JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */ |
658 | JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */ | |
659 | JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */ | |
660 | JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */ | |
661 | JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */ | |
662 | ||
663 | JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */ | |
3bf61c55 GFT |
664 | JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */ |
665 | JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */ | |
d7699f87 GFT |
666 | JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */ |
667 | JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */ | |
668 | JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */ | |
4330c2f2 GFT |
669 | JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */ |
670 | JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */ | |
3bf61c55 GFT |
671 | JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */ |
672 | JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */ | |
d7699f87 GFT |
673 | JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */ |
674 | JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */ | |
675 | ||
676 | JME_SMI = JME_MAC | 0x50, /* Station Management Interface */ | |
677 | JME_GHC = JME_MAC | 0x54, /* Global Host Control */ | |
678 | JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */ | |
679 | ||
680 | ||
ed457bcc | 681 | JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */ |
3bf61c55 | 682 | JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */ |
d7699f87 GFT |
683 | JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */ |
684 | JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ | |
186fc259 | 685 | JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */ |
d7699f87 GFT |
686 | |
687 | ||
cd0ff491 GFT |
688 | JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */ |
689 | JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */ | |
690 | JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */ | |
691 | JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */ | |
692 | JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */ | |
693 | JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */ | |
694 | JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */ | |
695 | JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */ | |
696 | JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */ | |
697 | JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */ | |
698 | JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */ | |
699 | JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */ | |
700 | JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */ | |
701 | JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */ | |
702 | JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */ | |
703 | JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */ | |
d7699f87 GFT |
704 | }; |
705 | ||
706 | /* | |
707 | * TX Control/Status Bits | |
708 | */ | |
709 | enum jme_txcs_bits { | |
710 | TXCS_QUEUE7S = 0x00008000, | |
711 | TXCS_QUEUE6S = 0x00004000, | |
712 | TXCS_QUEUE5S = 0x00002000, | |
713 | TXCS_QUEUE4S = 0x00001000, | |
714 | TXCS_QUEUE3S = 0x00000800, | |
715 | TXCS_QUEUE2S = 0x00000400, | |
716 | TXCS_QUEUE1S = 0x00000200, | |
717 | TXCS_QUEUE0S = 0x00000100, | |
718 | TXCS_FIFOTH = 0x000000C0, | |
719 | TXCS_DMASIZE = 0x00000030, | |
720 | TXCS_BURST = 0x00000004, | |
721 | TXCS_ENABLE = 0x00000001, | |
722 | }; | |
cd0ff491 | 723 | |
d7699f87 GFT |
724 | enum jme_txcs_value { |
725 | TXCS_FIFOTH_16QW = 0x000000C0, | |
726 | TXCS_FIFOTH_12QW = 0x00000080, | |
727 | TXCS_FIFOTH_8QW = 0x00000040, | |
728 | TXCS_FIFOTH_4QW = 0x00000000, | |
729 | ||
730 | TXCS_DMASIZE_64B = 0x00000000, | |
731 | TXCS_DMASIZE_128B = 0x00000010, | |
732 | TXCS_DMASIZE_256B = 0x00000020, | |
733 | TXCS_DMASIZE_512B = 0x00000030, | |
734 | ||
735 | TXCS_SELECT_QUEUE0 = 0x00000000, | |
736 | TXCS_SELECT_QUEUE1 = 0x00010000, | |
737 | TXCS_SELECT_QUEUE2 = 0x00020000, | |
738 | TXCS_SELECT_QUEUE3 = 0x00030000, | |
739 | TXCS_SELECT_QUEUE4 = 0x00040000, | |
740 | TXCS_SELECT_QUEUE5 = 0x00050000, | |
741 | TXCS_SELECT_QUEUE6 = 0x00060000, | |
742 | TXCS_SELECT_QUEUE7 = 0x00070000, | |
743 | ||
744 | TXCS_DEFAULT = TXCS_FIFOTH_4QW | | |
d7699f87 GFT |
745 | TXCS_BURST, |
746 | }; | |
cd0ff491 | 747 | |
29bdd921 | 748 | #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */ |
d7699f87 GFT |
749 | |
750 | /* | |
751 | * TX MAC Control/Status Bits | |
752 | */ | |
753 | enum jme_txmcs_bit_masks { | |
754 | TXMCS_IFG2 = 0xC0000000, | |
755 | TXMCS_IFG1 = 0x30000000, | |
756 | TXMCS_TTHOLD = 0x00000300, | |
757 | TXMCS_FBURST = 0x00000080, | |
758 | TXMCS_CARRIEREXT = 0x00000040, | |
759 | TXMCS_DEFER = 0x00000020, | |
760 | TXMCS_BACKOFF = 0x00000010, | |
761 | TXMCS_CARRIERSENSE = 0x00000008, | |
762 | TXMCS_COLLISION = 0x00000004, | |
763 | TXMCS_CRC = 0x00000002, | |
764 | TXMCS_PADDING = 0x00000001, | |
765 | }; | |
cd0ff491 | 766 | |
d7699f87 GFT |
767 | enum jme_txmcs_values { |
768 | TXMCS_IFG2_6_4 = 0x00000000, | |
769 | TXMCS_IFG2_8_5 = 0x40000000, | |
770 | TXMCS_IFG2_10_6 = 0x80000000, | |
771 | TXMCS_IFG2_12_7 = 0xC0000000, | |
772 | ||
773 | TXMCS_IFG1_8_4 = 0x00000000, | |
774 | TXMCS_IFG1_12_6 = 0x10000000, | |
775 | TXMCS_IFG1_16_8 = 0x20000000, | |
776 | TXMCS_IFG1_20_10 = 0x30000000, | |
777 | ||
778 | TXMCS_TTHOLD_1_8 = 0x00000000, | |
779 | TXMCS_TTHOLD_1_4 = 0x00000100, | |
780 | TXMCS_TTHOLD_1_2 = 0x00000200, | |
781 | TXMCS_TTHOLD_FULL = 0x00000300, | |
782 | ||
783 | TXMCS_DEFAULT = TXMCS_IFG2_8_5 | | |
784 | TXMCS_IFG1_16_8 | | |
785 | TXMCS_TTHOLD_FULL | | |
786 | TXMCS_DEFER | | |
787 | TXMCS_CRC | | |
788 | TXMCS_PADDING, | |
789 | }; | |
790 | ||
8c198884 GFT |
791 | enum jme_txpfc_bits_masks { |
792 | TXPFC_VLAN_TAG = 0xFFFF0000, | |
793 | TXPFC_VLAN_EN = 0x00008000, | |
794 | TXPFC_PF_EN = 0x00000001, | |
795 | }; | |
796 | ||
797 | enum jme_txtrhd_bits_masks { | |
798 | TXTRHD_TXPEN = 0x80000000, | |
799 | TXTRHD_TXP = 0x7FFFFF00, | |
800 | TXTRHD_TXREN = 0x00000080, | |
801 | TXTRHD_TXRL = 0x0000007F, | |
802 | }; | |
cd0ff491 | 803 | |
8c198884 GFT |
804 | enum jme_txtrhd_shifts { |
805 | TXTRHD_TXP_SHIFT = 8, | |
806 | TXTRHD_TXRL_SHIFT = 0, | |
807 | }; | |
808 | ||
809b2798 GFT |
809 | enum jme_txtrhd_values { |
810 | TXTRHD_FULLDUPLEX = 0x00000000, | |
811 | TXTRHD_HALFDUPLEX = TXTRHD_TXPEN | | |
812 | ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) | | |
813 | TXTRHD_TXREN | | |
814 | ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL), | |
815 | }; | |
816 | ||
d7699f87 GFT |
817 | /* |
818 | * RX Control/Status Bits | |
819 | */ | |
4330c2f2 | 820 | enum jme_rxcs_bit_masks { |
3bf61c55 GFT |
821 | /* FIFO full threshold for transmitting Tx Pause Packet */ |
822 | RXCS_FIFOTHTP = 0x30000000, | |
823 | /* FIFO threshold for processing next packet */ | |
824 | RXCS_FIFOTHNP = 0x0C000000, | |
4330c2f2 GFT |
825 | RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */ |
826 | RXCS_QUEUESEL = 0x00030000, /* Queue selection */ | |
827 | RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */ | |
828 | RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */ | |
829 | RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */ | |
830 | RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */ | |
831 | RXCS_SHORT = 0x00000010, /* Enable receive short packet */ | |
832 | RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */ | |
833 | RXCS_QST = 0x00000004, /* Receive queue start */ | |
834 | RXCS_SUSPEND = 0x00000002, | |
d7699f87 GFT |
835 | RXCS_ENABLE = 0x00000001, |
836 | }; | |
cd0ff491 | 837 | |
4330c2f2 GFT |
838 | enum jme_rxcs_values { |
839 | RXCS_FIFOTHTP_16T = 0x00000000, | |
840 | RXCS_FIFOTHTP_32T = 0x10000000, | |
841 | RXCS_FIFOTHTP_64T = 0x20000000, | |
842 | RXCS_FIFOTHTP_128T = 0x30000000, | |
843 | ||
844 | RXCS_FIFOTHNP_16QW = 0x00000000, | |
845 | RXCS_FIFOTHNP_32QW = 0x04000000, | |
846 | RXCS_FIFOTHNP_64QW = 0x08000000, | |
847 | RXCS_FIFOTHNP_128QW = 0x0C000000, | |
848 | ||
849 | RXCS_DMAREQSZ_16B = 0x00000000, | |
850 | RXCS_DMAREQSZ_32B = 0x01000000, | |
851 | RXCS_DMAREQSZ_64B = 0x02000000, | |
852 | RXCS_DMAREQSZ_128B = 0x03000000, | |
853 | ||
854 | RXCS_QUEUESEL_Q0 = 0x00000000, | |
855 | RXCS_QUEUESEL_Q1 = 0x00010000, | |
856 | RXCS_QUEUESEL_Q2 = 0x00020000, | |
857 | RXCS_QUEUESEL_Q3 = 0x00030000, | |
858 | ||
859 | RXCS_RETRYGAP_256ns = 0x00000000, | |
860 | RXCS_RETRYGAP_512ns = 0x00001000, | |
861 | RXCS_RETRYGAP_1024ns = 0x00002000, | |
862 | RXCS_RETRYGAP_2048ns = 0x00003000, | |
863 | RXCS_RETRYGAP_4096ns = 0x00004000, | |
864 | RXCS_RETRYGAP_8192ns = 0x00005000, | |
865 | RXCS_RETRYGAP_16384ns = 0x00006000, | |
866 | RXCS_RETRYGAP_32768ns = 0x00007000, | |
867 | ||
868 | RXCS_RETRYCNT_0 = 0x00000000, | |
869 | RXCS_RETRYCNT_4 = 0x00000100, | |
870 | RXCS_RETRYCNT_8 = 0x00000200, | |
871 | RXCS_RETRYCNT_12 = 0x00000300, | |
872 | RXCS_RETRYCNT_16 = 0x00000400, | |
873 | RXCS_RETRYCNT_20 = 0x00000500, | |
874 | RXCS_RETRYCNT_24 = 0x00000600, | |
875 | RXCS_RETRYCNT_28 = 0x00000700, | |
876 | RXCS_RETRYCNT_32 = 0x00000800, | |
877 | RXCS_RETRYCNT_36 = 0x00000900, | |
878 | RXCS_RETRYCNT_40 = 0x00000A00, | |
879 | RXCS_RETRYCNT_44 = 0x00000B00, | |
880 | RXCS_RETRYCNT_48 = 0x00000C00, | |
881 | RXCS_RETRYCNT_52 = 0x00000D00, | |
882 | RXCS_RETRYCNT_56 = 0x00000E00, | |
883 | RXCS_RETRYCNT_60 = 0x00000F00, | |
884 | ||
885 | RXCS_DEFAULT = RXCS_FIFOTHTP_128T | | |
79ce639c | 886 | RXCS_FIFOTHNP_128QW | |
4330c2f2 GFT |
887 | RXCS_DMAREQSZ_128B | |
888 | RXCS_RETRYGAP_256ns | | |
889 | RXCS_RETRYCNT_32, | |
890 | }; | |
cd0ff491 | 891 | |
29bdd921 | 892 | #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */ |
d7699f87 GFT |
893 | |
894 | /* | |
895 | * RX MAC Control/Status Bits | |
896 | */ | |
897 | enum jme_rxmcs_bits { | |
898 | RXMCS_ALLFRAME = 0x00000800, | |
899 | RXMCS_BRDFRAME = 0x00000400, | |
900 | RXMCS_MULFRAME = 0x00000200, | |
901 | RXMCS_UNIFRAME = 0x00000100, | |
902 | RXMCS_ALLMULFRAME = 0x00000080, | |
903 | RXMCS_MULFILTERED = 0x00000040, | |
3bf61c55 GFT |
904 | RXMCS_RXCOLLDEC = 0x00000020, |
905 | RXMCS_FLOWCTRL = 0x00000008, | |
906 | RXMCS_VTAGRM = 0x00000004, | |
907 | RXMCS_PREPAD = 0x00000002, | |
908 | RXMCS_CHECKSUM = 0x00000001, | |
b3821cc5 | 909 | |
8c198884 GFT |
910 | RXMCS_DEFAULT = RXMCS_VTAGRM | |
911 | RXMCS_PREPAD | | |
912 | RXMCS_FLOWCTRL | | |
913 | RXMCS_CHECKSUM, | |
d7699f87 GFT |
914 | }; |
915 | ||
b3821cc5 GFT |
916 | /* |
917 | * Wakeup Frame setup interface registers | |
918 | */ | |
919 | #define WAKEUP_FRAME_NR 8 | |
920 | #define WAKEUP_FRAME_MASK_DWNR 4 | |
cd0ff491 | 921 | |
b3821cc5 GFT |
922 | enum jme_wfoi_bit_masks { |
923 | WFOI_MASK_SEL = 0x00000070, | |
924 | WFOI_CRC_SEL = 0x00000008, | |
925 | WFOI_FRAME_SEL = 0x00000007, | |
926 | }; | |
cd0ff491 | 927 | |
b3821cc5 GFT |
928 | enum jme_wfoi_shifts { |
929 | WFOI_MASK_SHIFT = 4, | |
930 | }; | |
931 | ||
d7699f87 GFT |
932 | /* |
933 | * SMI Related definitions | |
934 | */ | |
cd0ff491 | 935 | enum jme_smi_bit_mask { |
d7699f87 GFT |
936 | SMI_DATA_MASK = 0xFFFF0000, |
937 | SMI_REG_ADDR_MASK = 0x0000F800, | |
938 | SMI_PHY_ADDR_MASK = 0x000007C0, | |
939 | SMI_OP_WRITE = 0x00000020, | |
3bf61c55 GFT |
940 | /* Set to 1, after req done it'll be cleared to 0 */ |
941 | SMI_OP_REQ = 0x00000010, | |
d7699f87 GFT |
942 | SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */ |
943 | SMI_OP_MDOE = 0x00000004, /* Software Output Enable */ | |
944 | SMI_OP_MDC = 0x00000002, /* Software CLK Control */ | |
945 | SMI_OP_MDEN = 0x00000001, /* Software access Enable */ | |
946 | }; | |
cd0ff491 GFT |
947 | |
948 | enum jme_smi_bit_shift { | |
d7699f87 GFT |
949 | SMI_DATA_SHIFT = 16, |
950 | SMI_REG_ADDR_SHIFT = 11, | |
951 | SMI_PHY_ADDR_SHIFT = 6, | |
952 | }; | |
cd0ff491 GFT |
953 | |
954 | static inline u32 smi_reg_addr(int x) | |
d7699f87 | 955 | { |
cd0ff491 | 956 | return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK; |
d7699f87 | 957 | } |
cd0ff491 GFT |
958 | |
959 | static inline u32 smi_phy_addr(int x) | |
d7699f87 | 960 | { |
cd0ff491 | 961 | return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK; |
d7699f87 | 962 | } |
cd0ff491 | 963 | |
8d27293f | 964 | #define JME_PHY_TIMEOUT 100 /* 100 msec */ |
186fc259 | 965 | #define JME_PHY_REG_NR 32 |
d7699f87 GFT |
966 | |
967 | /* | |
968 | * Global Host Control | |
969 | */ | |
970 | enum jme_ghc_bit_mask { | |
3b70a6fa | 971 | GHC_SWRST = 0x40000000, |
dc4185bd GFT |
972 | GHC_TO_CLK_SRC = 0x00C00000, |
973 | GHC_TXMAC_CLK_SRC = 0x00300000, | |
3b70a6fa GFT |
974 | GHC_DPX = 0x00000040, |
975 | GHC_SPEED = 0x00000030, | |
976 | GHC_LINK_POLL = 0x00000001, | |
d7699f87 | 977 | }; |
cd0ff491 | 978 | |
d7699f87 | 979 | enum jme_ghc_speed_val { |
3b70a6fa GFT |
980 | GHC_SPEED_10M = 0x00000010, |
981 | GHC_SPEED_100M = 0x00000020, | |
982 | GHC_SPEED_1000M = 0x00000030, | |
983 | }; | |
984 | ||
985 | enum jme_ghc_to_clk { | |
986 | GHC_TO_CLK_OFF = 0x00000000, | |
987 | GHC_TO_CLK_GPHY = 0x00400000, | |
988 | GHC_TO_CLK_PCIE = 0x00800000, | |
989 | GHC_TO_CLK_INVALID = 0x00C00000, | |
990 | }; | |
991 | ||
992 | enum jme_ghc_txmac_clk { | |
993 | GHC_TXMAC_CLK_OFF = 0x00000000, | |
994 | GHC_TXMAC_CLK_GPHY = 0x00100000, | |
995 | GHC_TXMAC_CLK_PCIE = 0x00200000, | |
996 | GHC_TXMAC_CLK_INVALID = 0x00300000, | |
d7699f87 GFT |
997 | }; |
998 | ||
29bdd921 GFT |
999 | /* |
1000 | * Power management control and status register | |
1001 | */ | |
1002 | enum jme_pmcs_bit_masks { | |
1003 | PMCS_WF7DET = 0x80000000, | |
1004 | PMCS_WF6DET = 0x40000000, | |
1005 | PMCS_WF5DET = 0x20000000, | |
1006 | PMCS_WF4DET = 0x10000000, | |
1007 | PMCS_WF3DET = 0x08000000, | |
1008 | PMCS_WF2DET = 0x04000000, | |
1009 | PMCS_WF1DET = 0x02000000, | |
1010 | PMCS_WF0DET = 0x01000000, | |
1011 | PMCS_LFDET = 0x00040000, | |
1012 | PMCS_LRDET = 0x00020000, | |
1013 | PMCS_MFDET = 0x00010000, | |
1014 | PMCS_WF7EN = 0x00008000, | |
1015 | PMCS_WF6EN = 0x00004000, | |
1016 | PMCS_WF5EN = 0x00002000, | |
1017 | PMCS_WF4EN = 0x00001000, | |
1018 | PMCS_WF3EN = 0x00000800, | |
1019 | PMCS_WF2EN = 0x00000400, | |
1020 | PMCS_WF1EN = 0x00000200, | |
1021 | PMCS_WF0EN = 0x00000100, | |
1022 | PMCS_LFEN = 0x00000004, | |
1023 | PMCS_LREN = 0x00000002, | |
1024 | PMCS_MFEN = 0x00000001, | |
1025 | }; | |
1026 | ||
ed457bcc GFT |
1027 | /* |
1028 | * New PHY Power Control Register | |
1029 | */ | |
1030 | enum jme_phy_pwr_bit_masks { | |
1031 | PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */ | |
1032 | PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */ | |
1033 | PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */ | |
1034 | PHY_PWR_CLKSEL = 0x08000000, /* | |
1035 | * XTL_OUT Clock select | |
1036 | * (an internal free-running clock) | |
1037 | * 0: xtl_out = phy_giga.A_XTL25_O | |
1038 | * 1: xtl_out = phy_giga.PD_OSC | |
1039 | */ | |
1040 | }; | |
0a0df947 GFT |
1041 | /* |
1042 | * False carrier Counter | |
1043 | */ | |
1044 | enum jme_phy_an_status { | |
1045 | PHY_SPEC_STATUS_AN_COMPLETE = 0x00000800, | |
1046 | PHY_SPEC_STATUS_AN_FAIL = 0x00008000, | |
1047 | }; | |
ed457bcc | 1048 | |
d7699f87 | 1049 | /* |
3bf61c55 | 1050 | * Giga PHY Status Registers |
d7699f87 GFT |
1051 | */ |
1052 | enum jme_phy_link_bit_mask { | |
1053 | PHY_LINK_SPEED_MASK = 0x0000C000, | |
1054 | PHY_LINK_DUPLEX = 0x00002000, | |
1055 | PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800, | |
1056 | PHY_LINK_UP = 0x00000400, | |
1057 | PHY_LINK_AUTONEG_COMPLETE = 0x00000200, | |
fcf45b4c | 1058 | PHY_LINK_MDI_STAT = 0x00000040, |
d7699f87 | 1059 | }; |
cd0ff491 | 1060 | |
d7699f87 GFT |
1061 | enum jme_phy_link_speed_val { |
1062 | PHY_LINK_SPEED_10M = 0x00000000, | |
1063 | PHY_LINK_SPEED_100M = 0x00004000, | |
1064 | PHY_LINK_SPEED_1000M = 0x00008000, | |
1065 | }; | |
cd0ff491 | 1066 | |
fcf45b4c | 1067 | #define JME_SPDRSV_TIMEOUT 500 /* 500 us */ |
d7699f87 GFT |
1068 | |
1069 | /* | |
1070 | * SMB Control and Status | |
1071 | */ | |
79ce639c | 1072 | enum jme_smbcsr_bit_mask { |
d7699f87 GFT |
1073 | SMBCSR_CNACK = 0x00020000, |
1074 | SMBCSR_RELOAD = 0x00010000, | |
1075 | SMBCSR_EEPROMD = 0x00000020, | |
186fc259 GFT |
1076 | SMBCSR_INITDONE = 0x00000010, |
1077 | SMBCSR_BUSY = 0x0000000F, | |
1078 | }; | |
cd0ff491 | 1079 | |
186fc259 GFT |
1080 | enum jme_smbintf_bit_mask { |
1081 | SMBINTF_HWDATR = 0xFF000000, | |
1082 | SMBINTF_HWDATW = 0x00FF0000, | |
1083 | SMBINTF_HWADDR = 0x0000FF00, | |
1084 | SMBINTF_HWRWN = 0x00000020, | |
1085 | SMBINTF_HWCMD = 0x00000010, | |
1086 | SMBINTF_FASTM = 0x00000008, | |
1087 | SMBINTF_GPIOSCL = 0x00000004, | |
1088 | SMBINTF_GPIOSDA = 0x00000002, | |
1089 | SMBINTF_GPIOEN = 0x00000001, | |
1090 | }; | |
cd0ff491 | 1091 | |
186fc259 GFT |
1092 | enum jme_smbintf_vals { |
1093 | SMBINTF_HWRWN_READ = 0x00000020, | |
1094 | SMBINTF_HWRWN_WRITE = 0x00000000, | |
1095 | }; | |
cd0ff491 | 1096 | |
186fc259 GFT |
1097 | enum jme_smbintf_shifts { |
1098 | SMBINTF_HWDATR_SHIFT = 24, | |
1099 | SMBINTF_HWDATW_SHIFT = 16, | |
1100 | SMBINTF_HWADDR_SHIFT = 8, | |
1101 | }; | |
cd0ff491 | 1102 | |
186fc259 GFT |
1103 | #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */ |
1104 | #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */ | |
1105 | #define JME_SMB_LEN 256 | |
1106 | #define JME_EEPROM_MAGIC 0x250 | |
d7699f87 | 1107 | |
79ce639c GFT |
1108 | /* |
1109 | * Timer Control/Status Register | |
1110 | */ | |
1111 | enum jme_tmcsr_bit_masks { | |
1112 | TMCSR_SWIT = 0x80000000, | |
1113 | TMCSR_EN = 0x01000000, | |
1114 | TMCSR_CNT = 0x00FFFFFF, | |
1115 | }; | |
1116 | ||
4330c2f2 | 1117 | /* |
cd0ff491 | 1118 | * General Purpose REG-0 |
4330c2f2 GFT |
1119 | */ |
1120 | enum jme_gpreg0_masks { | |
3bf61c55 GFT |
1121 | GPREG0_DISSH = 0xFF000000, |
1122 | GPREG0_PCIRLMT = 0x00300000, | |
1123 | GPREG0_PCCNOMUTCLR = 0x00040000, | |
cdcdc9eb | 1124 | GPREG0_LNKINTPOLL = 0x00001000, |
3bf61c55 GFT |
1125 | GPREG0_PCCTMR = 0x00000300, |
1126 | GPREG0_PHYADDR = 0x0000001F, | |
4330c2f2 | 1127 | }; |
cd0ff491 | 1128 | |
4330c2f2 GFT |
1129 | enum jme_gpreg0_vals { |
1130 | GPREG0_DISSH_DW7 = 0x80000000, | |
1131 | GPREG0_DISSH_DW6 = 0x40000000, | |
1132 | GPREG0_DISSH_DW5 = 0x20000000, | |
1133 | GPREG0_DISSH_DW4 = 0x10000000, | |
1134 | GPREG0_DISSH_DW3 = 0x08000000, | |
1135 | GPREG0_DISSH_DW2 = 0x04000000, | |
1136 | GPREG0_DISSH_DW1 = 0x02000000, | |
1137 | GPREG0_DISSH_DW0 = 0x01000000, | |
1138 | GPREG0_DISSH_ALL = 0xFF000000, | |
1139 | ||
1140 | GPREG0_PCIRLMT_8 = 0x00000000, | |
1141 | GPREG0_PCIRLMT_6 = 0x00100000, | |
1142 | GPREG0_PCIRLMT_5 = 0x00200000, | |
1143 | GPREG0_PCIRLMT_4 = 0x00300000, | |
1144 | ||
1145 | GPREG0_PCCTMR_16ns = 0x00000000, | |
3bf61c55 GFT |
1146 | GPREG0_PCCTMR_256ns = 0x00000100, |
1147 | GPREG0_PCCTMR_1us = 0x00000200, | |
1148 | GPREG0_PCCTMR_1ms = 0x00000300, | |
4330c2f2 GFT |
1149 | |
1150 | GPREG0_PHYADDR_1 = 0x00000001, | |
1151 | ||
1152 | GPREG0_DEFAULT = GPREG0_PCIRLMT_4 | | |
3bf61c55 GFT |
1153 | GPREG0_PCCTMR_1us | |
1154 | GPREG0_PHYADDR_1, | |
4330c2f2 GFT |
1155 | }; |
1156 | ||
7ee473a3 GFT |
1157 | /* |
1158 | * General Purpose REG-1 | |
7ee473a3 | 1159 | */ |
dc4185bd GFT |
1160 | enum jme_gpreg1_bit_masks { |
1161 | GPREG1_RXCLKOFF = 0x04000000, | |
1162 | GPREG1_PCREQN = 0x00020000, | |
1163 | GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */ | |
1164 | GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */ | |
7ee473a3 GFT |
1165 | GPREG1_INTRDELAYUNIT = 0x00000018, |
1166 | GPREG1_INTRDELAYENABLE = 0x00000007, | |
1167 | }; | |
1168 | ||
1169 | enum jme_gpreg1_vals { | |
7ee473a3 GFT |
1170 | GPREG1_INTDLYUNIT_16NS = 0x00000000, |
1171 | GPREG1_INTDLYUNIT_256NS = 0x00000008, | |
1172 | GPREG1_INTDLYUNIT_1US = 0x00000010, | |
1173 | GPREG1_INTDLYUNIT_16US = 0x00000018, | |
1174 | ||
1175 | GPREG1_INTDLYEN_1U = 0x00000001, | |
1176 | GPREG1_INTDLYEN_2U = 0x00000002, | |
1177 | GPREG1_INTDLYEN_3U = 0x00000003, | |
1178 | GPREG1_INTDLYEN_4U = 0x00000004, | |
1179 | GPREG1_INTDLYEN_5U = 0x00000005, | |
1180 | GPREG1_INTDLYEN_6U = 0x00000006, | |
1181 | GPREG1_INTDLYEN_7U = 0x00000007, | |
1182 | ||
dc4185bd | 1183 | GPREG1_DEFAULT = GPREG1_PCREQN, |
7ee473a3 GFT |
1184 | }; |
1185 | ||
d7699f87 GFT |
1186 | /* |
1187 | * Interrupt Status Bits | |
1188 | */ | |
cd0ff491 | 1189 | enum jme_interrupt_bits { |
d7699f87 GFT |
1190 | INTR_SWINTR = 0x80000000, |
1191 | INTR_TMINTR = 0x40000000, | |
1192 | INTR_LINKCH = 0x20000000, | |
1193 | INTR_PAUSERCV = 0x10000000, | |
1194 | INTR_MAGICRCV = 0x08000000, | |
1195 | INTR_WAKERCV = 0x04000000, | |
1196 | INTR_PCCRX0TO = 0x02000000, | |
1197 | INTR_PCCRX1TO = 0x01000000, | |
1198 | INTR_PCCRX2TO = 0x00800000, | |
1199 | INTR_PCCRX3TO = 0x00400000, | |
1200 | INTR_PCCTXTO = 0x00200000, | |
1201 | INTR_PCCRX0 = 0x00100000, | |
1202 | INTR_PCCRX1 = 0x00080000, | |
1203 | INTR_PCCRX2 = 0x00040000, | |
1204 | INTR_PCCRX3 = 0x00020000, | |
1205 | INTR_PCCTX = 0x00010000, | |
1206 | INTR_RX3EMP = 0x00008000, | |
1207 | INTR_RX2EMP = 0x00004000, | |
1208 | INTR_RX1EMP = 0x00002000, | |
1209 | INTR_RX0EMP = 0x00001000, | |
1210 | INTR_RX3 = 0x00000800, | |
1211 | INTR_RX2 = 0x00000400, | |
1212 | INTR_RX1 = 0x00000200, | |
1213 | INTR_RX0 = 0x00000100, | |
1214 | INTR_TX7 = 0x00000080, | |
1215 | INTR_TX6 = 0x00000040, | |
1216 | INTR_TX5 = 0x00000020, | |
1217 | INTR_TX4 = 0x00000010, | |
1218 | INTR_TX3 = 0x00000008, | |
1219 | INTR_TX2 = 0x00000004, | |
1220 | INTR_TX1 = 0x00000002, | |
1221 | INTR_TX0 = 0x00000001, | |
1222 | }; | |
cd0ff491 GFT |
1223 | |
1224 | static const u32 INTR_ENABLE = INTR_SWINTR | | |
79ce639c GFT |
1225 | INTR_TMINTR | |
1226 | INTR_LINKCH | | |
3bf61c55 GFT |
1227 | INTR_PCCRX0TO | |
1228 | INTR_PCCRX0 | | |
1229 | INTR_PCCTXTO | | |
cdcdc9eb GFT |
1230 | INTR_PCCTX | |
1231 | INTR_RX0EMP; | |
3bf61c55 GFT |
1232 | |
1233 | /* | |
1234 | * PCC Control Registers | |
1235 | */ | |
1236 | enum jme_pccrx_masks { | |
1237 | PCCRXTO_MASK = 0xFFFF0000, | |
1238 | PCCRX_MASK = 0x0000FF00, | |
1239 | }; | |
cd0ff491 | 1240 | |
3bf61c55 GFT |
1241 | enum jme_pcctx_masks { |
1242 | PCCTXTO_MASK = 0xFFFF0000, | |
1243 | PCCTX_MASK = 0x0000FF00, | |
1244 | PCCTX_QS_MASK = 0x000000FF, | |
1245 | }; | |
cd0ff491 | 1246 | |
3bf61c55 GFT |
1247 | enum jme_pccrx_shifts { |
1248 | PCCRXTO_SHIFT = 16, | |
1249 | PCCRX_SHIFT = 8, | |
1250 | }; | |
cd0ff491 | 1251 | |
3bf61c55 GFT |
1252 | enum jme_pcctx_shifts { |
1253 | PCCTXTO_SHIFT = 16, | |
1254 | PCCTX_SHIFT = 8, | |
1255 | }; | |
cd0ff491 | 1256 | |
3bf61c55 GFT |
1257 | enum jme_pcctx_bits { |
1258 | PCCTXQ0_EN = 0x00000001, | |
1259 | PCCTXQ1_EN = 0x00000002, | |
1260 | PCCTXQ2_EN = 0x00000004, | |
1261 | PCCTXQ3_EN = 0x00000008, | |
1262 | PCCTXQ4_EN = 0x00000010, | |
1263 | PCCTXQ5_EN = 0x00000020, | |
1264 | PCCTXQ6_EN = 0x00000040, | |
1265 | PCCTXQ7_EN = 0x00000080, | |
1266 | }; | |
1267 | ||
cdcdc9eb GFT |
1268 | /* |
1269 | * Chip Mode Register | |
1270 | */ | |
1271 | enum jme_chipmode_bit_masks { | |
1272 | CM_FPGAVER_MASK = 0xFFFF0000, | |
58c92f28 | 1273 | CM_CHIPREV_MASK = 0x0000FF00, |
cdcdc9eb GFT |
1274 | CM_CHIPMODE_MASK = 0x0000000F, |
1275 | }; | |
cd0ff491 | 1276 | |
cdcdc9eb GFT |
1277 | enum jme_chipmode_shifts { |
1278 | CM_FPGAVER_SHIFT = 16, | |
58c92f28 | 1279 | CM_CHIPREV_SHIFT = 8, |
cdcdc9eb | 1280 | }; |
d7699f87 | 1281 | |
cd0ff491 GFT |
1282 | /* |
1283 | * Aggressive Power Mode Control | |
1284 | */ | |
1285 | enum jme_apmc_bits { | |
1286 | JME_APMC_PCIE_SD_EN = 0x40000000, | |
1287 | JME_APMC_PSEUDO_HP_EN = 0x20000000, | |
1288 | JME_APMC_EPIEN = 0x04000000, | |
1289 | JME_APMC_EPIEN_CTRL = 0x03000000, | |
1290 | }; | |
1291 | ||
1292 | enum jme_apmc_values { | |
1293 | JME_APMC_EPIEN_CTRL_EN = 0x02000000, | |
1294 | JME_APMC_EPIEN_CTRL_DIS = 0x01000000, | |
1295 | }; | |
1296 | ||
1297 | #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000) | |
1298 | ||
1299 | #ifdef REG_DEBUG | |
1300 | static char *MAC_REG_NAME[] = { | |
1301 | "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC", | |
1302 | "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD", | |
1303 | "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC", | |
1304 | "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI", | |
1305 | "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI", | |
1306 | "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN", | |
1307 | "JME_PMCS"}; | |
7ee473a3 | 1308 | |
cd0ff491 GFT |
1309 | static char *PE_REG_NAME[] = { |
1310 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1311 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1312 | "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN", | |
1313 | "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1314 | "JME_SMBCSR", "JME_SMBINTF"}; | |
7ee473a3 | 1315 | |
cd0ff491 GFT |
1316 | static char *MISC_REG_NAME[] = { |
1317 | "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1", | |
1318 | "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC", | |
1319 | "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3", | |
1320 | "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO", | |
1321 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1322 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1323 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1324 | "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC", | |
1325 | "JME_PCCSRX0"}; | |
7ee473a3 | 1326 | |
cd0ff491 GFT |
1327 | static inline void reg_dbg(const struct jme_adapter *jme, |
1328 | const char *msg, u32 val, u32 reg) | |
1329 | { | |
1330 | const char *regname; | |
58c92f28 | 1331 | switch (reg & 0xF00) { |
cd0ff491 GFT |
1332 | case 0x000: |
1333 | regname = MAC_REG_NAME[(reg & 0xFF) >> 2]; | |
1334 | break; | |
1335 | case 0x400: | |
1336 | regname = PE_REG_NAME[(reg & 0xFF) >> 2]; | |
1337 | break; | |
1338 | case 0x800: | |
58c92f28 | 1339 | regname = MISC_REG_NAME[(reg & 0xFF) >> 2]; |
cd0ff491 GFT |
1340 | break; |
1341 | default: | |
1342 | regname = PE_REG_NAME[0]; | |
1343 | } | |
1344 | printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name, | |
1345 | msg, val, regname); | |
1346 | } | |
1347 | #else | |
1348 | static inline void reg_dbg(const struct jme_adapter *jme, | |
1349 | const char *msg, u32 val, u32 reg) {} | |
1350 | #endif | |
1351 | ||
d7699f87 GFT |
1352 | /* |
1353 | * Read/Write MMaped I/O Registers | |
1354 | */ | |
cd0ff491 | 1355 | static inline u32 jread32(struct jme_adapter *jme, u32 reg) |
d7699f87 | 1356 | { |
cd0ff491 | 1357 | return readl(jme->regs + reg); |
d7699f87 | 1358 | } |
cd0ff491 GFT |
1359 | |
1360 | static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val) | |
d7699f87 | 1361 | { |
cd0ff491 GFT |
1362 | reg_dbg(jme, "REG WRITE", val, reg); |
1363 | writel(val, jme->regs + reg); | |
1364 | reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); | |
d7699f87 | 1365 | } |
cd0ff491 GFT |
1366 | |
1367 | static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val) | |
d7699f87 GFT |
1368 | { |
1369 | /* | |
1370 | * Read after write should cause flush | |
1371 | */ | |
cd0ff491 GFT |
1372 | reg_dbg(jme, "REG WRITE FLUSH", val, reg); |
1373 | writel(val, jme->regs + reg); | |
1374 | readl(jme->regs + reg); | |
1375 | reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); | |
d7699f87 GFT |
1376 | } |
1377 | ||
cdcdc9eb GFT |
1378 | /* |
1379 | * PHY Regs | |
1380 | */ | |
1381 | enum jme_phy_reg17_bit_masks { | |
1382 | PREG17_SPEED = 0xC000, | |
1383 | PREG17_DUPLEX = 0x2000, | |
1384 | PREG17_SPDRSV = 0x0800, | |
1385 | PREG17_LNKUP = 0x0400, | |
1386 | PREG17_MDI = 0x0040, | |
1387 | }; | |
cd0ff491 | 1388 | |
cdcdc9eb GFT |
1389 | enum jme_phy_reg17_vals { |
1390 | PREG17_SPEED_10M = 0x0000, | |
1391 | PREG17_SPEED_100M = 0x4000, | |
1392 | PREG17_SPEED_1000M = 0x8000, | |
1393 | }; | |
cd0ff491 | 1394 | |
8d27293f | 1395 | #define BMSR_ANCOMP 0x0020 |
cdcdc9eb | 1396 | |
58c92f28 GFT |
1397 | /* |
1398 | * Workaround | |
1399 | */ | |
98ef18f1 | 1400 | static inline int is_buggy250(unsigned short device, u8 chiprev) |
58c92f28 GFT |
1401 | { |
1402 | return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11; | |
1403 | } | |
1404 | ||
ed457bcc GFT |
1405 | static inline int new_phy_power_ctrl(u8 chip_main_rev) |
1406 | { | |
1407 | return chip_main_rev >= 5; | |
1408 | } | |
1409 | ||
d7699f87 | 1410 | /* |
cd0ff491 | 1411 | * Function prototypes |
d7699f87 | 1412 | */ |
d7699f87 | 1413 | static int jme_set_settings(struct net_device *netdev, |
cd0ff491 | 1414 | struct ethtool_cmd *ecmd); |
e523cd89 | 1415 | static void jme_set_unicastaddr(struct net_device *netdev); |
d7699f87 GFT |
1416 | static void jme_set_multi(struct net_device *netdev); |
1417 | ||
cd0ff491 | 1418 | #endif |
e5169728 | 1419 |