jme: Fix bit typo of JMC250A2 workaround
[jme.git] / jme.c
CommitLineData
d7699f87
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
2e582300 25#include <linux/version.h>
937ef75a
JP
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
d7699f87
GFT
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
4330c2f2 38#include <linux/delay.h>
29bdd921 39#include <linux/spinlock.h>
8c198884
GFT
40#include <linux/in.h>
41#include <linux/ip.h>
79ce639c
GFT
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
42b1055e 45#include <linux/if_vlan.h>
38d1bc09 46#include <linux/slab.h>
3b70a6fa 47#include <net/ip6_checksum.h>
d7699f87
GFT
48#include "jme.h"
49
cd0ff491
GFT
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 61
3bf61c55
GFT
62static int
63jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT
64{
65 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 67
186fc259 68read_again:
cd0ff491 69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT
70 smi_phy_addr(phy) |
71 smi_reg_addr(reg));
d7699f87
GFT
72
73 wmb();
cd0ff491 74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 75 udelay(20);
b3821cc5
GFT
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
3bf61c55 78 break;
cd0ff491 79 }
d7699f87 80
cd0ff491 81 if (i == 0) {
937ef75a 82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 83 return 0;
cd0ff491 84 }
d7699f87 85
cd0ff491 86 if (again--)
186fc259
GFT
87 goto read_again;
88
cd0ff491 89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT
90}
91
3bf61c55
GFT
92static void
93jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
d7699f87
GFT
95{
96 struct jme_adapter *jme = netdev_priv(netdev);
97 int i;
98
3bf61c55
GFT
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT
102
103 wmb();
cdcdc9eb
GFT
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
105 udelay(20);
8d27293f 106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT
107 break;
108 }
d7699f87 109
3bf61c55 110 if (i == 0)
937ef75a 111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT
112}
113
cd0ff491 114static inline void
3bf61c55 115jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 116{
cd0ff491 117 u32 val;
3bf61c55
GFT
118
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
8c198884
GFT
121 MII_ADVERTISE, ADVERTISE_ALL |
122 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 123
cd0ff491 124 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
125 jme_mdio_write(jme->dev,
126 jme->mii_if.phy_id,
127 MII_CTRL1000,
128 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 129
fcf45b4c
GFT
130 val = jme_mdio_read(jme->dev,
131 jme->mii_if.phy_id,
132 MII_BMCR);
133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
136 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT
137}
138
b3821cc5
GFT
139static void
140jme_setup_wakeup_frame(struct jme_adapter *jme,
a4181cd4 141 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT
142{
143 int i;
144
145 /*
146 * Setup CRC pattern
147 */
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
149 wmb();
150 jwrite32(jme, JME_WFODP, crc);
151 wmb();
152
153 /*
154 * Setup Mask
155 */
cd0ff491 156 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
160 wmb();
161 jwrite32(jme, JME_WFODP, mask[i]);
162 wmb();
163 }
164}
3bf61c55 165
cd0ff491 166static inline void
3bf61c55
GFT
167jme_reset_mac_processor(struct jme_adapter *jme)
168{
a4181cd4 169 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT
170 u32 crc = 0xCDCDCDCD;
171 u32 gpreg0;
b3821cc5
GFT
172 int i;
173
3bf61c55 174 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 175 udelay(2);
3bf61c55 176 jwrite32(jme, JME_GHC, jme->reg_ghc);
cd0ff491
GFT
177
178 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
179 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
180 jwrite32(jme, JME_RXQDC, 0x00000000);
181 jwrite32(jme, JME_RXNDA, 0x00000000);
182 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
183 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
184 jwrite32(jme, JME_TXQDC, 0x00000000);
185 jwrite32(jme, JME_TXNDA, 0x00000000);
186
4330c2f2
GFT
187 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
188 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 189 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 190 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 191 if (jme->fpgaver)
cdcdc9eb
GFT
192 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
193 else
194 gpreg0 = GPREG0_DEFAULT;
195 jwrite32(jme, JME_GPREG0, gpreg0);
7ee473a3 196 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
d7699f87
GFT
197}
198
cd0ff491
GFT
199static inline void
200jme_reset_ghc_speed(struct jme_adapter *jme)
201{
202 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
203 jwrite32(jme, JME_GHC, jme->reg_ghc);
204}
205
206static inline void
3bf61c55 207jme_clear_pm(struct jme_adapter *jme)
d7699f87 208{
29bdd921 209 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 210 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 211 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT
212}
213
3bf61c55
GFT
214static int
215jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 216{
cd0ff491 217 u32 val;
d7699f87
GFT
218 int i;
219
220 val = jread32(jme, JME_SMBCSR);
221
cd0ff491 222 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT
223 val |= SMBCSR_CNACK;
224 jwrite32(jme, JME_SMBCSR, val);
225 val |= SMBCSR_RELOAD;
226 jwrite32(jme, JME_SMBCSR, val);
227 mdelay(12);
228
cd0ff491 229 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT
230 mdelay(1);
231 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
232 break;
233 }
234
cd0ff491 235 if (i == 0) {
937ef75a 236 pr_err("eeprom reload timeout\n");
d7699f87
GFT
237 return -EIO;
238 }
239 }
3bf61c55 240
d7699f87
GFT
241 return 0;
242}
243
3bf61c55
GFT
244static void
245jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT
246{
247 struct jme_adapter *jme = netdev_priv(netdev);
248 unsigned char macaddr[6];
cd0ff491 249 u32 val;
d7699f87 250
cd0ff491 251 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 252 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT
253 macaddr[0] = (val >> 0) & 0xFF;
254 macaddr[1] = (val >> 8) & 0xFF;
255 macaddr[2] = (val >> 16) & 0xFF;
256 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 257 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT
258 macaddr[4] = (val >> 0) & 0xFF;
259 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT
260 memcpy(netdev->dev_addr, macaddr, 6);
261 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT
262}
263
cd0ff491 264static inline void
3bf61c55
GFT
265jme_set_rx_pcc(struct jme_adapter *jme, int p)
266{
cd0ff491 267 switch (p) {
192570e0
GFT
268 case PCC_OFF:
269 jwrite32(jme, JME_PCCRX0,
270 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
271 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
272 break;
3bf61c55
GFT
273 case PCC_P1:
274 jwrite32(jme, JME_PCCRX0,
275 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
276 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
277 break;
278 case PCC_P2:
279 jwrite32(jme, JME_PCCRX0,
280 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
281 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
282 break;
283 case PCC_P3:
284 jwrite32(jme, JME_PCCRX0,
285 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
286 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
287 break;
288 default:
289 break;
290 }
192570e0 291 wmb();
3bf61c55 292
cd0ff491 293 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
7ca9ebee 294 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT
295}
296
fcf45b4c 297static void
3bf61c55 298jme_start_irq(struct jme_adapter *jme)
d7699f87 299{
3bf61c55
GFT
300 register struct dynpcc_info *dpi = &(jme->dpi);
301
302 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT
303 dpi->cur = PCC_P1;
304 dpi->attempt = PCC_P1;
305 dpi->cnt = 0;
306
307 jwrite32(jme, JME_PCCTX,
8c198884
GFT
308 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
309 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT
310 PCCTXQ0_EN
311 );
312
d7699f87
GFT
313 /*
314 * Enable Interrupts
315 */
316 jwrite32(jme, JME_IENS, INTR_ENABLE);
317}
318
cd0ff491 319static inline void
3bf61c55 320jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT
321{
322 /*
323 * Disable Interrupts
324 */
cd0ff491 325 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT
326}
327
cd0ff491 328static u32
cdcdc9eb
GFT
329jme_linkstat_from_phy(struct jme_adapter *jme)
330{
cd0ff491 331 u32 phylink, bmsr;
cdcdc9eb
GFT
332
333 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
334 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 335 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT
336 phylink |= PHY_LINK_AUTONEG_COMPLETE;
337
338 return phylink;
339}
340
cd0ff491 341static inline void
58c92f28 342jme_set_phyfifoa(struct jme_adapter *jme)
cd0ff491
GFT
343{
344 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
345}
346
347static inline void
58c92f28 348jme_set_phyfifob(struct jme_adapter *jme)
cd0ff491
GFT
349{
350 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
351}
352
fcf45b4c
GFT
353static int
354jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT
355{
356 struct jme_adapter *jme = netdev_priv(netdev);
7ee473a3 357 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
79ce639c 358 char linkmsg[64];
fcf45b4c 359 int rc = 0;
d7699f87 360
b3821cc5 361 linkmsg[0] = '\0';
cdcdc9eb 362
cd0ff491 363 if (jme->fpgaver)
cdcdc9eb
GFT
364 phylink = jme_linkstat_from_phy(jme);
365 else
366 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 367
cd0ff491
GFT
368 if (phylink & PHY_LINK_UP) {
369 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT
370 /*
371 * If we did not enable AN
372 * Speed/Duplex Info should be obtained from SMI
373 */
374 phylink = PHY_LINK_UP;
375
376 bmcr = jme_mdio_read(jme->dev,
377 jme->mii_if.phy_id,
378 MII_BMCR);
379
380 phylink |= ((bmcr & BMCR_SPEED1000) &&
381 (bmcr & BMCR_SPEED100) == 0) ?
382 PHY_LINK_SPEED_1000M :
383 (bmcr & BMCR_SPEED100) ?
384 PHY_LINK_SPEED_100M :
385 PHY_LINK_SPEED_10M;
386
387 phylink |= (bmcr & BMCR_FULLDPLX) ?
388 PHY_LINK_DUPLEX : 0;
79ce639c 389
b3821cc5 390 strcat(linkmsg, "Forced: ");
cd0ff491 391 } else {
8c198884
GFT
392 /*
393 * Keep polling for speed/duplex resolve complete
394 */
cd0ff491 395 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT
396 --cnt) {
397
398 udelay(1);
8c198884 399
cd0ff491 400 if (jme->fpgaver)
cdcdc9eb
GFT
401 phylink = jme_linkstat_from_phy(jme);
402 else
403 phylink = jread32(jme, JME_PHY_LINK);
8c198884 404 }
cd0ff491 405 if (!cnt)
937ef75a 406 pr_err("Waiting speed resolve timeout\n");
79ce639c 407
b3821cc5 408 strcat(linkmsg, "ANed: ");
d7699f87
GFT
409 }
410
cd0ff491 411 if (jme->phylink == phylink) {
fcf45b4c
GFT
412 rc = 1;
413 goto out;
414 }
cd0ff491 415 if (testonly)
fcf45b4c
GFT
416 goto out;
417
418 jme->phylink = phylink;
419
3b70a6fa
GFT
420 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
421 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
422 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
cd0ff491
GFT
423 switch (phylink & PHY_LINK_SPEED_MASK) {
424 case PHY_LINK_SPEED_10M:
3b70a6fa
GFT
425 ghc |= GHC_SPEED_10M |
426 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 427 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT
428 break;
429 case PHY_LINK_SPEED_100M:
3b70a6fa
GFT
430 ghc |= GHC_SPEED_100M |
431 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
cd0ff491 432 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT
433 break;
434 case PHY_LINK_SPEED_1000M:
3b70a6fa
GFT
435 ghc |= GHC_SPEED_1000M |
436 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
cd0ff491 437 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT
438 break;
439 default:
440 break;
d7699f87 441 }
d7699f87 442
cd0ff491 443 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 444 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
7ee473a3 445 ghc |= GHC_DPX;
cd0ff491 446 } else {
d7699f87 447 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT
448 TXMCS_BACKOFF |
449 TXMCS_CARRIERSENSE |
450 TXMCS_COLLISION);
8c198884
GFT
451 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
452 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
453 TXTRHD_TXREN |
454 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
455 }
7ee473a3
GFT
456
457 gpreg1 = GPREG1_DEFAULT;
458 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
459 if (!(phylink & PHY_LINK_DUPLEX))
460 gpreg1 |= GPREG1_HALFMODEPATCH;
461 switch (phylink & PHY_LINK_SPEED_MASK) {
462 case PHY_LINK_SPEED_10M:
463 jme_set_phyfifoa(jme);
464 gpreg1 |= GPREG1_RSSPATCH;
465 break;
466 case PHY_LINK_SPEED_100M:
467 jme_set_phyfifob(jme);
468 gpreg1 |= GPREG1_RSSPATCH;
469 break;
470 case PHY_LINK_SPEED_1000M:
471 jme_set_phyfifoa(jme);
472 break;
473 default:
474 break;
475 }
476 }
d7699f87 477
3b70a6fa 478 jwrite32(jme, JME_GPREG1, gpreg1);
fcf45b4c 479 jwrite32(jme, JME_GHC, ghc);
3b70a6fa 480 jme->reg_ghc = ghc;
fcf45b4c 481
3b70a6fa
GFT
482 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
483 "Full-Duplex, " :
484 "Half-Duplex, ");
485 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
486 "MDI-X" :
487 "MDI");
937ef75a 488 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT
489 netif_carrier_on(netdev);
490 } else {
491 if (testonly)
fcf45b4c
GFT
492 goto out;
493
937ef75a 494 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 495 jme->phylink = 0;
cd0ff491 496 netif_carrier_off(netdev);
d7699f87 497 }
fcf45b4c
GFT
498
499out:
500 return rc;
d7699f87
GFT
501}
502
3bf61c55
GFT
503static int
504jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 505{
d7699f87
GFT
506 struct jme_ring *txring = &(jme->txring[0]);
507
508 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
509 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
510 &(txring->dmaalloc),
511 GFP_ATOMIC);
fcf45b4c 512
0ede469c
GFT
513 if (!txring->alloc)
514 goto err_set_null;
d7699f87
GFT
515
516 /*
517 * 16 Bytes align
518 */
cd0ff491 519 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 520 RING_DESC_ALIGN);
4330c2f2 521 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 522 txring->next_to_use = 0;
cdcdc9eb 523 atomic_set(&txring->next_to_clean, 0);
b3821cc5 524 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 525
0ede469c
GFT
526 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
527 jme->tx_ring_size, GFP_ATOMIC);
528 if (unlikely(!(txring->bufinf)))
529 goto err_free_txring;
530
d7699f87 531 /*
b3821cc5 532 * Initialize Transmit Descriptors
d7699f87 533 */
b3821cc5 534 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 535 memset(txring->bufinf, 0,
b3821cc5 536 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT
537
538 return 0;
0ede469c
GFT
539
540err_free_txring:
541 dma_free_coherent(&(jme->pdev->dev),
542 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
543 txring->alloc,
544 txring->dmaalloc);
545
546err_set_null:
547 txring->desc = NULL;
548 txring->dmaalloc = 0;
549 txring->dma = 0;
550 txring->bufinf = NULL;
551
552 return -ENOMEM;
d7699f87
GFT
553}
554
3bf61c55
GFT
555static void
556jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT
557{
558 int i;
559 struct jme_ring *txring = &(jme->txring[0]);
0ede469c 560 struct jme_buffer_info *txbi;
d7699f87 561
cd0ff491 562 if (txring->alloc) {
0ede469c
GFT
563 if (txring->bufinf) {
564 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
565 txbi = txring->bufinf + i;
566 if (txbi->skb) {
567 dev_kfree_skb(txbi->skb);
568 txbi->skb = NULL;
569 }
570 txbi->mapping = 0;
571 txbi->len = 0;
572 txbi->nr_desc = 0;
573 txbi->start_xmit = 0;
d7699f87 574 }
0ede469c 575 kfree(txring->bufinf);
d7699f87
GFT
576 }
577
578 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 579 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT
580 txring->alloc,
581 txring->dmaalloc);
3bf61c55
GFT
582
583 txring->alloc = NULL;
584 txring->desc = NULL;
585 txring->dmaalloc = 0;
586 txring->dma = 0;
0ede469c 587 txring->bufinf = NULL;
d7699f87 588 }
3bf61c55 589 txring->next_to_use = 0;
cdcdc9eb 590 atomic_set(&txring->next_to_clean, 0);
79ce639c 591 atomic_set(&txring->nr_free, 0);
d7699f87
GFT
592}
593
cd0ff491 594static inline void
3bf61c55 595jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
596{
597 /*
598 * Select Queue 0
599 */
600 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 601 wmb();
d7699f87
GFT
602
603 /*
604 * Setup TX Queue 0 DMA Bass Address
605 */
fcf45b4c 606 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 607 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 608 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT
609
610 /*
611 * Setup TX Descptor Count
612 */
b3821cc5 613 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT
614
615 /*
616 * Enable TX Engine
617 */
618 wmb();
4330c2f2
GFT
619 jwrite32(jme, JME_TXCS, jme->reg_txcs |
620 TXCS_SELECT_QUEUE0 |
621 TXCS_ENABLE);
d7699f87
GFT
622
623}
624
cd0ff491 625static inline void
29bdd921
GFT
626jme_restart_tx_engine(struct jme_adapter *jme)
627{
628 /*
629 * Restart TX Engine
630 */
631 jwrite32(jme, JME_TXCS, jme->reg_txcs |
632 TXCS_SELECT_QUEUE0 |
633 TXCS_ENABLE);
634}
635
cd0ff491 636static inline void
3bf61c55 637jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT
638{
639 int i;
cd0ff491 640 u32 val;
d7699f87
GFT
641
642 /*
643 * Disable TX Engine
644 */
fcf45b4c 645 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 646 wmb();
d7699f87
GFT
647
648 val = jread32(jme, JME_TXCS);
cd0ff491 649 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 650 mdelay(1);
d7699f87 651 val = jread32(jme, JME_TXCS);
cd0ff491 652 rmb();
d7699f87
GFT
653 }
654
cd0ff491 655 if (!i)
937ef75a 656 pr_err("Disable TX engine timeout\n");
d7699f87
GFT
657}
658
3bf61c55
GFT
659static void
660jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 661{
0ede469c 662 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 663 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT
664 struct jme_buffer_info *rxbi = rxring->bufinf;
665 rxdesc += i;
666 rxbi += i;
667
668 rxdesc->dw[0] = 0;
669 rxdesc->dw[1] = 0;
3bf61c55 670 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT
671 rxdesc->desc1.bufaddrl = cpu_to_le32(
672 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 673 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 674 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 675 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 676 wmb();
3bf61c55 677 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT
678}
679
3bf61c55
GFT
680static int
681jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
682{
683 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 684 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 685 struct sk_buff *skb;
4330c2f2 686
79ce639c
GFT
687 skb = netdev_alloc_skb(jme->dev,
688 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 689 if (unlikely(!skb))
4330c2f2 690 return -ENOMEM;
3b70a6fa
GFT
691#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
692 skb->dev = jme->dev;
693#endif
3bf61c55 694
4330c2f2 695 rxbi->skb = skb;
3bf61c55 696 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT
697 rxbi->mapping = pci_map_page(jme->pdev,
698 virt_to_page(skb->data),
699 offset_in_page(skb->data),
700 rxbi->len,
701 PCI_DMA_FROMDEVICE);
4330c2f2
GFT
702
703 return 0;
704}
705
3bf61c55
GFT
706static void
707jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT
708{
709 struct jme_ring *rxring = &(jme->rxring[0]);
710 struct jme_buffer_info *rxbi = rxring->bufinf;
711 rxbi += i;
712
cd0ff491 713 if (rxbi->skb) {
b3821cc5 714 pci_unmap_page(jme->pdev,
4330c2f2 715 rxbi->mapping,
3bf61c55 716 rxbi->len,
4330c2f2
GFT
717 PCI_DMA_FROMDEVICE);
718 dev_kfree_skb(rxbi->skb);
719 rxbi->skb = NULL;
720 rxbi->mapping = 0;
3bf61c55 721 rxbi->len = 0;
4330c2f2
GFT
722 }
723}
724
3bf61c55
GFT
725static void
726jme_free_rx_resources(struct jme_adapter *jme)
727{
728 int i;
729 struct jme_ring *rxring = &(jme->rxring[0]);
730
cd0ff491 731 if (rxring->alloc) {
0ede469c
GFT
732 if (rxring->bufinf) {
733 for (i = 0 ; i < jme->rx_ring_size ; ++i)
734 jme_free_rx_buf(jme, i);
735 kfree(rxring->bufinf);
736 }
3bf61c55
GFT
737
738 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 739 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT
740 rxring->alloc,
741 rxring->dmaalloc);
742 rxring->alloc = NULL;
743 rxring->desc = NULL;
744 rxring->dmaalloc = 0;
745 rxring->dma = 0;
0ede469c 746 rxring->bufinf = NULL;
3bf61c55
GFT
747 }
748 rxring->next_to_use = 0;
cdcdc9eb 749 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT
750}
751
752static int
753jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT
754{
755 int i;
756 struct jme_ring *rxring = &(jme->rxring[0]);
757
758 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT
759 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
760 &(rxring->dmaalloc),
761 GFP_ATOMIC);
0ede469c
GFT
762 if (!rxring->alloc)
763 goto err_set_null;
d7699f87
GFT
764
765 /*
766 * 16 Bytes align
767 */
cd0ff491 768 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 769 RING_DESC_ALIGN);
4330c2f2 770 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 771 rxring->next_to_use = 0;
cdcdc9eb 772 atomic_set(&rxring->next_to_clean, 0);
d7699f87 773
0ede469c
GFT
774 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
775 jme->rx_ring_size, GFP_ATOMIC);
776 if (unlikely(!(rxring->bufinf)))
777 goto err_free_rxring;
778
d7699f87
GFT
779 /*
780 * Initiallize Receive Descriptors
781 */
0ede469c
GFT
782 memset(rxring->bufinf, 0,
783 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT
784 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
785 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT
786 jme_free_rx_resources(jme);
787 return -ENOMEM;
788 }
d7699f87
GFT
789
790 jme_set_clean_rxdesc(jme, i);
791 }
792
d7699f87 793 return 0;
0ede469c
GFT
794
795err_free_rxring:
796 dma_free_coherent(&(jme->pdev->dev),
797 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
798 rxring->alloc,
799 rxring->dmaalloc);
800err_set_null:
801 rxring->desc = NULL;
802 rxring->dmaalloc = 0;
803 rxring->dma = 0;
804 rxring->bufinf = NULL;
805
806 return -ENOMEM;
d7699f87
GFT
807}
808
cd0ff491 809static inline void
3bf61c55 810jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 811{
d7699f87 812 /*
cd0ff491
GFT
813 * Select Queue 0
814 */
815 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
816 RXCS_QUEUESEL_Q0);
817 wmb();
818
819 /*
d7699f87
GFT
820 * Setup RX DMA Bass Address
821 */
0ede469c 822 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 823 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
0ede469c 824 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT
825
826 /*
b3821cc5 827 * Setup RX Descriptor Count
d7699f87 828 */
b3821cc5 829 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 830
3bf61c55 831 /*
d7699f87
GFT
832 * Setup Unicast Filter
833 */
834 jme_set_multi(jme->dev);
835
836 /*
837 * Enable RX Engine
838 */
839 wmb();
79ce639c 840 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
841 RXCS_QUEUESEL_Q0 |
842 RXCS_ENABLE |
843 RXCS_QST);
d7699f87
GFT
844}
845
cd0ff491 846static inline void
3bf61c55 847jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT
848{
849 /*
3bf61c55 850 * Start RX Engine
4330c2f2 851 */
79ce639c 852 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT
853 RXCS_QUEUESEL_Q0 |
854 RXCS_ENABLE |
855 RXCS_QST);
856}
857
cd0ff491 858static inline void
3bf61c55 859jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT
860{
861 int i;
cd0ff491 862 u32 val;
d7699f87
GFT
863
864 /*
865 * Disable RX Engine
866 */
29bdd921 867 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 868 wmb();
d7699f87
GFT
869
870 val = jread32(jme, JME_RXCS);
cd0ff491 871 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 872 mdelay(1);
d7699f87 873 val = jread32(jme, JME_RXCS);
cd0ff491 874 rmb();
d7699f87
GFT
875 }
876
cd0ff491 877 if (!i)
937ef75a 878 pr_err("Disable RX engine timeout\n");
d7699f87
GFT
879
880}
881
192570e0 882static int
cd0ff491 883jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
192570e0 884{
cd0ff491 885 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT
886 return false;
887
0ede469c
GFT
888 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
889 == RXWBFLAG_TCPON)) {
890 if (flags & RXWBFLAG_IPV4)
7ca9ebee 891 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
0ede469c 892 return false;
192570e0
GFT
893 }
894
0ede469c
GFT
895 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
896 == RXWBFLAG_UDPON)) {
897 if (flags & RXWBFLAG_IPV4)
937ef75a 898 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
0ede469c 899 return false;
192570e0
GFT
900 }
901
0ede469c
GFT
902 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
903 == RXWBFLAG_IPV4)) {
937ef75a 904 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
0ede469c 905 return false;
192570e0
GFT
906 }
907
908 return true;
909}
910
3bf61c55 911static void
42b1055e 912jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 913{
d7699f87 914 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 915 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 916 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 917 struct sk_buff *skb;
3bf61c55 918 int framesize;
d7699f87 919
3bf61c55
GFT
920 rxdesc += idx;
921 rxbi += idx;
d7699f87 922
3bf61c55
GFT
923 skb = rxbi->skb;
924 pci_dma_sync_single_for_cpu(jme->pdev,
925 rxbi->mapping,
926 rxbi->len,
927 PCI_DMA_FROMDEVICE);
928
cd0ff491 929 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT
930 pci_dma_sync_single_for_device(jme->pdev,
931 rxbi->mapping,
932 rxbi->len,
933 PCI_DMA_FROMDEVICE);
934
935 ++(NET_STAT(jme).rx_dropped);
cd0ff491 936 } else {
3bf61c55
GFT
937 framesize = le16_to_cpu(rxdesc->descwb.framesize)
938 - RX_PREPAD_SIZE;
939
940 skb_reserve(skb, RX_PREPAD_SIZE);
941 skb_put(skb, framesize);
942 skb->protocol = eth_type_trans(skb, jme->dev);
943
3b70a6fa 944 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
8c198884 945 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 946 else
08f5fcfa 947#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
29bdd921 948 skb->ip_summed = CHECKSUM_NONE;
08f5fcfa
ED
949#else
950 skb_checksum_none_assert(skb);
951#endif
8c198884 952
3b70a6fa 953 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 954 if (jme->vlgrp) {
cdcdc9eb 955 jme->jme_vlan_rx(skb, jme->vlgrp,
3b70a6fa 956 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 957 NET_STAT(jme).rx_bytes += 4;
7ca9ebee 958 } else {
7ca9ebee 959 dev_kfree_skb(skb);
b3821cc5 960 }
cd0ff491 961 } else {
cdcdc9eb 962 jme->jme_rx(skb);
b3821cc5 963 }
3bf61c55 964
3b70a6fa
GFT
965 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
966 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT
967 ++(NET_STAT(jme).multicast);
968
3bf61c55
GFT
969 NET_STAT(jme).rx_bytes += framesize;
970 ++(NET_STAT(jme).rx_packets);
971 }
972
973 jme_set_clean_rxdesc(jme, idx);
974
975}
976
8c198884 977static int
3bf61c55
GFT
978jme_process_receive(struct jme_adapter *jme, int limit)
979{
980 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 981 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 982 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 983
cd0ff491 984 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT
985 goto out_inc;
986
cd0ff491 987 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT
988 goto out_inc;
989
cd0ff491 990 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT
991 goto out_inc;
992
cdcdc9eb 993 i = atomic_read(&rxring->next_to_clean);
0ede469c 994 while (limit > 0) {
3bf61c55
GFT
995 rxdesc = rxring->desc;
996 rxdesc += i;
997
3b70a6fa 998 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT
999 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1000 goto out;
0ede469c 1001 --limit;
d7699f87 1002
9134abda 1003 rmb();
4330c2f2
GFT
1004 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1005
cd0ff491 1006 if (unlikely(desccnt > 1 ||
192570e0 1007 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1008
cd0ff491 1009 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1010 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1011 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT
1012 ++(NET_STAT(jme).rx_fifo_errors);
1013 else
1014 ++(NET_STAT(jme).rx_errors);
4330c2f2 1015
cd0ff491 1016 if (desccnt > 1)
3bf61c55 1017 limit -= desccnt - 1;
4330c2f2 1018
cd0ff491 1019 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1020 jme_set_clean_rxdesc(jme, j);
b3821cc5 1021 j = (j + 1) & (mask);
4330c2f2 1022 }
3bf61c55 1023
cd0ff491 1024 } else {
42b1055e 1025 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1026 }
4330c2f2 1027
b3821cc5 1028 i = (i + desccnt) & (mask);
3bf61c55 1029 }
4330c2f2 1030
3bf61c55 1031out:
cdcdc9eb 1032 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1033
192570e0
GFT
1034out_inc:
1035 atomic_inc(&jme->rx_cleaning);
1036
3bf61c55 1037 return limit > 0 ? limit : 0;
4330c2f2 1038
3bf61c55 1039}
d7699f87 1040
3bf61c55 1041static void
79ce639c
GFT
1042jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1043{
cd0ff491 1044 if (likely(atmp == dpi->cur)) {
192570e0 1045 dpi->cnt = 0;
79ce639c 1046 return;
192570e0 1047 }
79ce639c 1048
cd0ff491 1049 if (dpi->attempt == atmp) {
79ce639c 1050 ++(dpi->cnt);
cd0ff491 1051 } else {
79ce639c
GFT
1052 dpi->attempt = atmp;
1053 dpi->cnt = 0;
1054 }
1055
1056}
1057
1058static void
1059jme_dynamic_pcc(struct jme_adapter *jme)
1060{
1061 register struct dynpcc_info *dpi = &(jme->dpi);
1062
cd0ff491 1063 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1064 jme_attempt_pcc(dpi, PCC_P3);
7ca9ebee
GFT
1065 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1066 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT
1067 jme_attempt_pcc(dpi, PCC_P2);
1068 else
1069 jme_attempt_pcc(dpi, PCC_P1);
1070
cd0ff491
GFT
1071 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1072 if (dpi->attempt < dpi->cur)
1073 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT
1074 jme_set_rx_pcc(jme, dpi->attempt);
1075 dpi->cur = dpi->attempt;
1076 dpi->cnt = 0;
1077 }
1078}
1079
1080static void
1081jme_start_pcc_timer(struct jme_adapter *jme)
1082{
1083 struct dynpcc_info *dpi = &(jme->dpi);
1084 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1085 dpi->last_pkts = NET_STAT(jme).rx_packets;
1086 dpi->intr_cnt = 0;
1087 jwrite32(jme, JME_TMCSR,
1088 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1089}
1090
cd0ff491 1091static inline void
29bdd921
GFT
1092jme_stop_pcc_timer(struct jme_adapter *jme)
1093{
1094 jwrite32(jme, JME_TMCSR, 0);
1095}
1096
1097static void
cd0ff491
GFT
1098jme_shutdown_nic(struct jme_adapter *jme)
1099{
1100 u32 phylink;
1101
1102 phylink = jme_linkstat_from_phy(jme);
1103
1104 if (!(phylink & PHY_LINK_UP)) {
1105 /*
1106 * Disable all interrupt before issue timer
1107 */
1108 jme_stop_irq(jme);
1109 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1110 }
1111}
1112
1113static void
79ce639c
GFT
1114jme_pcc_tasklet(unsigned long arg)
1115{
cd0ff491 1116 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT
1117 struct net_device *netdev = jme->dev;
1118
cd0ff491
GFT
1119 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1120 jme_shutdown_nic(jme);
1121 return;
1122 }
29bdd921 1123
cd0ff491 1124 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT
1125 (atomic_read(&jme->link_changing) != 1)
1126 )) {
1127 jme_stop_pcc_timer(jme);
79ce639c
GFT
1128 return;
1129 }
29bdd921 1130
cd0ff491 1131 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT
1132 jme_dynamic_pcc(jme);
1133
79ce639c
GFT
1134 jme_start_pcc_timer(jme);
1135}
1136
cd0ff491 1137static inline void
192570e0
GFT
1138jme_polling_mode(struct jme_adapter *jme)
1139{
1140 jme_set_rx_pcc(jme, PCC_OFF);
1141}
1142
cd0ff491 1143static inline void
192570e0
GFT
1144jme_interrupt_mode(struct jme_adapter *jme)
1145{
1146 jme_set_rx_pcc(jme, PCC_P1);
1147}
1148
cd0ff491
GFT
1149static inline int
1150jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1151{
1152 u32 apmc;
1153 apmc = jread32(jme, JME_APMC);
1154 return apmc & JME_APMC_PSEUDO_HP_EN;
1155}
1156
1157static void
1158jme_start_shutdown_timer(struct jme_adapter *jme)
1159{
1160 u32 apmc;
1161
1162 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1163 apmc &= ~JME_APMC_EPIEN_CTRL;
1164 if (!no_extplug) {
1165 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1166 wmb();
1167 }
1168 jwrite32f(jme, JME_APMC, apmc);
1169
1170 jwrite32f(jme, JME_TIMER2, 0);
1171 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1172 jwrite32(jme, JME_TMCSR,
1173 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1174}
1175
1176static void
1177jme_stop_shutdown_timer(struct jme_adapter *jme)
1178{
1179 u32 apmc;
1180
1181 jwrite32f(jme, JME_TMCSR, 0);
1182 jwrite32f(jme, JME_TIMER2, 0);
1183 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1184
1185 apmc = jread32(jme, JME_APMC);
1186 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1187 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1188 wmb();
1189 jwrite32f(jme, JME_APMC, apmc);
1190}
1191
79ce639c 1192static void
3bf61c55
GFT
1193jme_link_change_tasklet(unsigned long arg)
1194{
cd0ff491 1195 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1196 struct net_device *netdev = jme->dev;
fcf45b4c
GFT
1197 int rc;
1198
cd0ff491
GFT
1199 while (!atomic_dec_and_test(&jme->link_changing)) {
1200 atomic_inc(&jme->link_changing);
937ef75a 1201 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
58c92f28 1202 while (atomic_read(&jme->link_changing) != 1)
937ef75a 1203 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1204 }
fcf45b4c 1205
cd0ff491 1206 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT
1207 goto out;
1208
29bdd921 1209 jme->old_mtu = netdev->mtu;
fcf45b4c 1210 netif_stop_queue(netdev);
cd0ff491
GFT
1211 if (jme_pseudo_hotplug_enabled(jme))
1212 jme_stop_shutdown_timer(jme);
1213
1214 jme_stop_pcc_timer(jme);
1215 tasklet_disable(&jme->txclean_task);
1216 tasklet_disable(&jme->rxclean_task);
1217 tasklet_disable(&jme->rxempty_task);
1218
1219 if (netif_carrier_ok(netdev)) {
1220 jme_reset_ghc_speed(jme);
1221 jme_disable_rx_engine(jme);
1222 jme_disable_tx_engine(jme);
fcf45b4c
GFT
1223 jme_reset_mac_processor(jme);
1224 jme_free_rx_resources(jme);
1225 jme_free_tx_resources(jme);
192570e0 1226
cd0ff491 1227 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1228 jme_polling_mode(jme);
cd0ff491
GFT
1229
1230 netif_carrier_off(netdev);
fcf45b4c
GFT
1231 }
1232
1233 jme_check_link(netdev, 0);
cd0ff491 1234 if (netif_carrier_ok(netdev)) {
fcf45b4c 1235 rc = jme_setup_rx_resources(jme);
cd0ff491 1236 if (rc) {
937ef75a 1237 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1238 goto out_enable_tasklet;
fcf45b4c
GFT
1239 }
1240
fcf45b4c 1241 rc = jme_setup_tx_resources(jme);
cd0ff491 1242 if (rc) {
937ef75a 1243 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT
1244 goto err_out_free_rx_resources;
1245 }
1246
1247 jme_enable_rx_engine(jme);
1248 jme_enable_tx_engine(jme);
1249
1250 netif_start_queue(netdev);
192570e0 1251
cd0ff491 1252 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1253 jme_interrupt_mode(jme);
192570e0 1254
79ce639c 1255 jme_start_pcc_timer(jme);
cd0ff491
GFT
1256 } else if (jme_pseudo_hotplug_enabled(jme)) {
1257 jme_start_shutdown_timer(jme);
fcf45b4c
GFT
1258 }
1259
cd0ff491 1260 goto out_enable_tasklet;
fcf45b4c
GFT
1261
1262err_out_free_rx_resources:
1263 jme_free_rx_resources(jme);
cd0ff491
GFT
1264out_enable_tasklet:
1265 tasklet_enable(&jme->txclean_task);
1266 tasklet_hi_enable(&jme->rxclean_task);
1267 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT
1268out:
1269 atomic_inc(&jme->link_changing);
3bf61c55 1270}
d7699f87 1271
3bf61c55
GFT
1272static void
1273jme_rx_clean_tasklet(unsigned long arg)
1274{
cd0ff491 1275 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1276 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1277
192570e0
GFT
1278 jme_process_receive(jme, jme->rx_ring_size);
1279 ++(dpi->intr_cnt);
42b1055e 1280
192570e0 1281}
fcf45b4c 1282
192570e0 1283static int
cdcdc9eb 1284jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1285{
cdcdc9eb 1286 struct jme_adapter *jme = jme_napi_priv(holder);
3b70a6fa 1287 DECLARE_NETDEV
192570e0 1288 int rest;
fcf45b4c 1289
cdcdc9eb 1290 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1291
cd0ff491 1292 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1293 atomic_dec(&jme->rx_empty);
192570e0
GFT
1294 ++(NET_STAT(jme).rx_dropped);
1295 jme_restart_rx_engine(jme);
1296 }
1297 atomic_inc(&jme->rx_empty);
1298
cd0ff491 1299 if (rest) {
cdcdc9eb 1300 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT
1301 jme_interrupt_mode(jme);
1302 }
1303
cdcdc9eb
GFT
1304 JME_NAPI_WEIGHT_SET(budget, rest);
1305 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT
1306}
1307
1308static void
1309jme_rx_empty_tasklet(unsigned long arg)
1310{
cd0ff491 1311 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1312
cd0ff491 1313 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1314 return;
1315
cd0ff491 1316 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1317 return;
1318
7ca9ebee 1319 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1320
fcf45b4c 1321 jme_rx_clean_tasklet(arg);
cdcdc9eb 1322
cd0ff491 1323 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT
1324 atomic_dec(&jme->rx_empty);
1325 ++(NET_STAT(jme).rx_dropped);
1326 jme_restart_rx_engine(jme);
1327 }
1328 atomic_inc(&jme->rx_empty);
4330c2f2
GFT
1329}
1330
3bf61c55 1331static void
b3821cc5
GFT
1332jme_wake_queue_if_stopped(struct jme_adapter *jme)
1333{
0ede469c 1334 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1335
1336 smp_wmb();
cd0ff491 1337 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1338 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
937ef75a 1339 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1340 netif_wake_queue(jme->dev);
b3821cc5
GFT
1341 }
1342
1343}
1344
1345static void
3bf61c55 1346jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1347{
cd0ff491 1348 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1349 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1350 struct txdesc *txdesc = txring->desc;
3bf61c55 1351 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1352 int i, j, cnt = 0, max, err, mask;
3bf61c55 1353
937ef75a 1354 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT
1355
1356 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT
1357 goto out;
1358
cd0ff491 1359 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT
1360 goto out;
1361
cd0ff491 1362 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT
1363 goto out;
1364
b3821cc5
GFT
1365 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1366 mask = jme->tx_ring_mask;
3bf61c55 1367
cd0ff491 1368 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT
1369
1370 ctxbi = txbi + i;
1371
cd0ff491 1372 if (likely(ctxbi->skb &&
b3821cc5 1373 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1374
cd0ff491 1375 tx_dbg(jme, "txclean: %d+%d@%lu\n",
937ef75a 1376 i, ctxbi->nr_desc, jiffies);
3bf61c55 1377
cd0ff491 1378 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1379
cd0ff491 1380 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT
1381 ttxbi = txbi + ((i + j) & (mask));
1382 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1383
b3821cc5 1384 pci_unmap_page(jme->pdev,
3bf61c55
GFT
1385 ttxbi->mapping,
1386 ttxbi->len,
1387 PCI_DMA_TODEVICE);
1388
3bf61c55
GFT
1389 ttxbi->mapping = 0;
1390 ttxbi->len = 0;
1391 }
1392
1393 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT
1394
1395 cnt += ctxbi->nr_desc;
1396
cd0ff491 1397 if (unlikely(err)) {
8c198884 1398 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1399 } else {
8c198884 1400 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT
1401 NET_STAT(jme).tx_bytes += ctxbi->len;
1402 }
1403
1404 ctxbi->skb = NULL;
1405 ctxbi->len = 0;
cdcdc9eb 1406 ctxbi->start_xmit = 0;
cd0ff491
GFT
1407
1408 } else {
3bf61c55
GFT
1409 break;
1410 }
1411
b3821cc5 1412 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT
1413
1414 ctxbi->nr_desc = 0;
d7699f87
GFT
1415 }
1416
937ef75a 1417 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1418 atomic_set(&txring->next_to_clean, i);
79ce639c 1419 atomic_add(cnt, &txring->nr_free);
3bf61c55 1420
b3821cc5
GFT
1421 jme_wake_queue_if_stopped(jme);
1422
fcf45b4c
GFT
1423out:
1424 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT
1425}
1426
79ce639c 1427static void
cd0ff491 1428jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1429{
3bf61c55
GFT
1430 /*
1431 * Disable interrupt
1432 */
1433 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1434
cd0ff491 1435 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT
1436 /*
1437 * Link change event is critical
1438 * all other events are ignored
1439 */
1440 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1441 tasklet_schedule(&jme->linkch_task);
29bdd921 1442 goto out_reenable;
fcf45b4c 1443 }
d7699f87 1444
cd0ff491 1445 if (intrstat & INTR_TMINTR) {
47220951 1446 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1447 tasklet_schedule(&jme->pcc_task);
47220951 1448 }
79ce639c 1449
cd0ff491 1450 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1451 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1452 tasklet_schedule(&jme->txclean_task);
47220951
GFT
1453 }
1454
cd0ff491 1455 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT
1456 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1457 INTR_PCCRX0 |
1458 INTR_RX0EMP)) |
1459 INTR_RX0);
1460 }
d7699f87 1461
cd0ff491
GFT
1462 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1463 if (intrstat & INTR_RX0EMP)
192570e0
GFT
1464 atomic_inc(&jme->rx_empty);
1465
cd0ff491
GFT
1466 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1467 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1468 jme_polling_mode(jme);
cdcdc9eb 1469 JME_RX_SCHEDULE(jme);
192570e0
GFT
1470 }
1471 }
cd0ff491
GFT
1472 } else {
1473 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1474 atomic_inc(&jme->rx_empty);
cd0ff491
GFT
1475 tasklet_hi_schedule(&jme->rxempty_task);
1476 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1477 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1478 }
4330c2f2 1479 }
d7699f87 1480
29bdd921 1481out_reenable:
3bf61c55 1482 /*
fcf45b4c 1483 * Re-enable interrupt
3bf61c55 1484 */
fcf45b4c 1485 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT
1486}
1487
3b70a6fa
GFT
1488#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1489static irqreturn_t
1490jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1491#else
79ce639c
GFT
1492static irqreturn_t
1493jme_intr(int irq, void *dev_id)
3b70a6fa 1494#endif
79ce639c 1495{
cd0ff491
GFT
1496 struct net_device *netdev = dev_id;
1497 struct jme_adapter *jme = netdev_priv(netdev);
1498 u32 intrstat;
79ce639c
GFT
1499
1500 intrstat = jread32(jme, JME_IEVE);
1501
1502 /*
1503 * Check if it's really an interrupt for us
1504 */
7ee473a3 1505 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1506 return IRQ_NONE;
79ce639c
GFT
1507
1508 /*
1509 * Check if the device still exist
1510 */
cd0ff491
GFT
1511 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1512 return IRQ_NONE;
79ce639c
GFT
1513
1514 jme_intr_msi(jme, intrstat);
1515
cd0ff491 1516 return IRQ_HANDLED;
d7699f87
GFT
1517}
1518
3b70a6fa
GFT
1519#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1520static irqreturn_t
1521jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1522#else
79ce639c
GFT
1523static irqreturn_t
1524jme_msi(int irq, void *dev_id)
3b70a6fa 1525#endif
79ce639c 1526{
cd0ff491
GFT
1527 struct net_device *netdev = dev_id;
1528 struct jme_adapter *jme = netdev_priv(netdev);
1529 u32 intrstat;
79ce639c 1530
0ede469c 1531 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT
1532
1533 jme_intr_msi(jme, intrstat);
1534
cd0ff491 1535 return IRQ_HANDLED;
79ce639c
GFT
1536}
1537
79ce639c
GFT
1538static void
1539jme_reset_link(struct jme_adapter *jme)
1540{
1541 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1542}
1543
fcf45b4c
GFT
1544static void
1545jme_restart_an(struct jme_adapter *jme)
1546{
cd0ff491 1547 u32 bmcr;
fcf45b4c 1548
cd0ff491 1549 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT
1550 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1551 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1552 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1553 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT
1554}
1555
1556static int
1557jme_request_irq(struct jme_adapter *jme)
1558{
1559 int rc;
cd0ff491 1560 struct net_device *netdev = jme->dev;
3b70a6fa
GFT
1561#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1562 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1563 int irq_flags = SA_SHIRQ;
1564#else
cd0ff491
GFT
1565 irq_handler_t handler = jme_intr;
1566 int irq_flags = IRQF_SHARED;
3b70a6fa 1567#endif
cd0ff491
GFT
1568
1569 if (!pci_enable_msi(jme->pdev)) {
1570 set_bit(JME_FLAG_MSI, &jme->flags);
1571 handler = jme_msi;
1572 irq_flags = 0;
1573 }
1574
1575 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1576 netdev);
1577 if (rc) {
937ef75a
JP
1578 netdev_err(netdev,
1579 "Unable to request %s interrupt (return: %d)\n",
1580 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1581 rc);
79ce639c 1582
cd0ff491
GFT
1583 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1584 pci_disable_msi(jme->pdev);
1585 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1586 }
cd0ff491 1587 } else {
79ce639c
GFT
1588 netdev->irq = jme->pdev->irq;
1589 }
1590
cd0ff491 1591 return rc;
79ce639c
GFT
1592}
1593
1594static void
1595jme_free_irq(struct jme_adapter *jme)
1596{
cd0ff491
GFT
1597 free_irq(jme->pdev->irq, jme->dev);
1598 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1599 pci_disable_msi(jme->pdev);
1600 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1601 jme->dev->irq = jme->pdev->irq;
cd0ff491 1602 }
fcf45b4c
GFT
1603}
1604
e58b908e 1605static inline void
ed457bcc
GFT
1606jme_new_phy_on(struct jme_adapter *jme)
1607{
1608 u32 reg;
1609
1610 reg = jread32(jme, JME_PHY_PWR);
1611 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1612 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1613 jwrite32(jme, JME_PHY_PWR, reg);
1614
1615 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1616 reg &= ~PE1_GPREG0_PBG;
1617 reg |= PE1_GPREG0_ENBG;
1618 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1619}
1620
1621static inline void
1622jme_new_phy_off(struct jme_adapter *jme)
1623{
1624 u32 reg;
1625
1626 reg = jread32(jme, JME_PHY_PWR);
1627 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1628 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1629 jwrite32(jme, JME_PHY_PWR, reg);
1630
1631 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1632 reg &= ~PE1_GPREG0_PBG;
1633 reg |= PE1_GPREG0_PDD3COLD;
1634 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1635}
1636
1637static inline void
e58b908e
GFT
1638jme_phy_on(struct jme_adapter *jme)
1639{
1640 u32 bmcr;
1641
1642 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1643 bmcr &= ~BMCR_PDOWN;
1644 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
ed457bcc
GFT
1645
1646 if (new_phy_power_ctrl(jme->chip_main_rev))
1647 jme_new_phy_on(jme);
1648}
1649
1650static inline void
1651jme_phy_off(struct jme_adapter *jme)
1652{
1653 u32 bmcr;
1654
1655 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1656 bmcr |= BMCR_PDOWN;
1657 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1658
1659 if (new_phy_power_ctrl(jme->chip_main_rev))
1660 jme_new_phy_off(jme);
e58b908e
GFT
1661}
1662
3bf61c55
GFT
1663static int
1664jme_open(struct net_device *netdev)
d7699f87
GFT
1665{
1666 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1667 int rc;
79ce639c 1668
42b1055e 1669 jme_clear_pm(jme);
cdcdc9eb 1670 JME_NAPI_ENABLE(jme);
d7699f87 1671
0ede469c 1672 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT
1673 tasklet_enable(&jme->txclean_task);
1674 tasklet_hi_enable(&jme->rxclean_task);
1675 tasklet_hi_enable(&jme->rxempty_task);
1676
79ce639c 1677 rc = jme_request_irq(jme);
cd0ff491 1678 if (rc)
4330c2f2 1679 goto err_out;
79ce639c 1680
d7699f87 1681 jme_start_irq(jme);
42b1055e 1682
ed457bcc
GFT
1683 jme_phy_on(jme);
1684 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1685 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 1686 else
42b1055e
GFT
1687 jme_reset_phy_processor(jme);
1688
29bdd921 1689 jme_reset_link(jme);
d7699f87
GFT
1690
1691 return 0;
1692
d7699f87
GFT
1693err_out:
1694 netif_stop_queue(netdev);
1695 netif_carrier_off(netdev);
4330c2f2 1696 return rc;
d7699f87
GFT
1697}
1698
42b1055e
GFT
1699static void
1700jme_set_100m_half(struct jme_adapter *jme)
1701{
cd0ff491 1702 u32 bmcr, tmp;
42b1055e 1703
a82e368c 1704 jme_phy_on(jme);
42b1055e
GFT
1705 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1706 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1707 BMCR_SPEED1000 | BMCR_FULLDPLX);
1708 tmp |= BMCR_SPEED100;
1709
1710 if (bmcr != tmp)
1711 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1712
cd0ff491 1713 if (jme->fpgaver)
cdcdc9eb
GFT
1714 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1715 else
1716 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT
1717}
1718
47220951
GFT
1719#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1720static void
1721jme_wait_link(struct jme_adapter *jme)
1722{
cd0ff491 1723 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT
1724
1725 mdelay(1000);
1726 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1727 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT
1728 mdelay(10);
1729 phylink = jme_linkstat_from_phy(jme);
1730 }
1731}
1732
a82e368c
GFT
1733static void
1734jme_powersave_phy(struct jme_adapter *jme)
1735{
1736 if (jme->reg_pmcs) {
1737 jme_set_100m_half(jme);
1738
1739 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1740 jme_wait_link(jme);
1741
1742 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1743 } else {
1744 jme_phy_off(jme);
1745 }
1746}
1747
3bf61c55
GFT
1748static int
1749jme_close(struct net_device *netdev)
d7699f87
GFT
1750{
1751 struct jme_adapter *jme = netdev_priv(netdev);
1752
1753 netif_stop_queue(netdev);
1754 netif_carrier_off(netdev);
1755
1756 jme_stop_irq(jme);
79ce639c 1757 jme_free_irq(jme);
d7699f87 1758
cdcdc9eb 1759 JME_NAPI_DISABLE(jme);
192570e0 1760
0ede469c
GFT
1761 tasklet_disable(&jme->linkch_task);
1762 tasklet_disable(&jme->txclean_task);
1763 tasklet_disable(&jme->rxclean_task);
1764 tasklet_disable(&jme->rxempty_task);
8c198884 1765
cd0ff491
GFT
1766 jme_reset_ghc_speed(jme);
1767 jme_disable_rx_engine(jme);
1768 jme_disable_tx_engine(jme);
8c198884 1769 jme_reset_mac_processor(jme);
d7699f87
GFT
1770 jme_free_rx_resources(jme);
1771 jme_free_tx_resources(jme);
42b1055e 1772 jme->phylink = 0;
b3821cc5
GFT
1773 jme_phy_off(jme);
1774
1775 return 0;
1776}
1777
1778static int
1779jme_alloc_txdesc(struct jme_adapter *jme,
1780 struct sk_buff *skb)
1781{
0ede469c 1782 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT
1783 int idx, nr_alloc, mask = jme->tx_ring_mask;
1784
1785 idx = txring->next_to_use;
1786 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1787
cd0ff491 1788 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT
1789 return -1;
1790
1791 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1792
b3821cc5
GFT
1793 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1794
1795 return idx;
1796}
1797
1798static void
1799jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1800 struct txdesc *txdesc,
b3821cc5
GFT
1801 struct jme_buffer_info *txbi,
1802 struct page *page,
cd0ff491
GFT
1803 u32 page_offset,
1804 u32 len,
1805 u8 hidma)
b3821cc5
GFT
1806{
1807 dma_addr_t dmaaddr;
1808
1809 dmaaddr = pci_map_page(pdev,
1810 page,
1811 page_offset,
1812 len,
1813 PCI_DMA_TODEVICE);
1814
1815 pci_dma_sync_single_for_device(pdev,
1816 dmaaddr,
1817 len,
1818 PCI_DMA_TODEVICE);
1819
1820 txdesc->dw[0] = 0;
1821 txdesc->dw[1] = 0;
1822 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1823 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT
1824 txdesc->desc2.datalen = cpu_to_le16(len);
1825 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1826 txdesc->desc2.bufaddrl = cpu_to_le32(
1827 (__u64)dmaaddr & 0xFFFFFFFFUL);
1828
1829 txbi->mapping = dmaaddr;
1830 txbi->len = len;
1831}
1832
1833static void
1834jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1835{
0ede469c 1836 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1837 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1838 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1839 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT
1840 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1841 int mask = jme->tx_ring_mask;
1842 struct skb_frag_struct *frag;
cd0ff491 1843 u32 len;
b3821cc5 1844
cd0ff491
GFT
1845 for (i = 0 ; i < nr_frags ; ++i) {
1846 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT
1847 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1848 ctxbi = txbi + ((idx + i + 2) & (mask));
1849
1850 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1851 frag->page_offset, frag->size, hidma);
42b1055e 1852 }
b3821cc5 1853
cd0ff491 1854 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT
1855 ctxdesc = txdesc + ((idx + 1) & (mask));
1856 ctxbi = txbi + ((idx + 1) & (mask));
1857 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1858 offset_in_page(skb->data), len, hidma);
1859
1860}
1861
1862static int
1863jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1864{
3b70a6fa 1865 if (unlikely(
0ede469c 1866#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT
1867 skb_shinfo(skb)->tso_size
1868#else
1869 skb_shinfo(skb)->gso_size
1870#endif
1871 && skb_header_cloned(skb) &&
b3821cc5
GFT
1872 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1873 dev_kfree_skb(skb);
1874 return -1;
1875 }
1876
1877 return 0;
1878}
1879
1880static int
3b70a6fa 1881jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 1882{
0ede469c 1883#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT
1884 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1885#else
1886 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1887#endif
cd0ff491 1888 if (*mss) {
b3821cc5
GFT
1889 *flags |= TXFLAG_LSEN;
1890
cd0ff491 1891 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT
1892 struct iphdr *iph = ip_hdr(skb);
1893
1894 iph->check = 0;
cd0ff491 1895 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT
1896 iph->daddr, 0,
1897 IPPROTO_TCP,
1898 0);
cd0ff491 1899 } else {
b3821cc5
GFT
1900 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1901
cd0ff491 1902 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT
1903 &ip6h->daddr, 0,
1904 IPPROTO_TCP,
1905 0);
1906 }
1907
1908 return 0;
1909 }
1910
1911 return 1;
1912}
1913
1914static void
cd0ff491 1915jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 1916{
3b70a6fa
GFT
1917#ifdef CHECKSUM_PARTIAL
1918 if (skb->ip_summed == CHECKSUM_PARTIAL)
1919#else
1920 if (skb->ip_summed == CHECKSUM_HW)
1921#endif
1922 {
cd0ff491 1923 u8 ip_proto;
b3821cc5 1924
3b70a6fa
GFT
1925#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1926 if (skb->protocol == htons(ETH_P_IP))
1927 ip_proto = ip_hdr(skb)->protocol;
1928 else if (skb->protocol == htons(ETH_P_IPV6))
1929 ip_proto = ipv6_hdr(skb)->nexthdr;
1930 else
1931 ip_proto = 0;
1932#else
b3821cc5 1933 switch (skb->protocol) {
cd0ff491 1934 case htons(ETH_P_IP):
b3821cc5
GFT
1935 ip_proto = ip_hdr(skb)->protocol;
1936 break;
cd0ff491 1937 case htons(ETH_P_IPV6):
b3821cc5
GFT
1938 ip_proto = ipv6_hdr(skb)->nexthdr;
1939 break;
1940 default:
1941 ip_proto = 0;
1942 break;
1943 }
3b70a6fa 1944#endif
b3821cc5 1945
cd0ff491 1946 switch (ip_proto) {
b3821cc5
GFT
1947 case IPPROTO_TCP:
1948 *flags |= TXFLAG_TCPCS;
1949 break;
1950 case IPPROTO_UDP:
1951 *flags |= TXFLAG_UDPCS;
1952 break;
1953 default:
937ef75a 1954 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT
1955 break;
1956 }
1957 }
1958}
1959
cd0ff491 1960static inline void
3b70a6fa 1961jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 1962{
cd0ff491 1963 if (vlan_tx_tag_present(skb)) {
b3821cc5 1964 *flags |= TXFLAG_TAGON;
3b70a6fa 1965 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 1966 }
b3821cc5
GFT
1967}
1968
1969static int
3b70a6fa 1970jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 1971{
0ede469c 1972 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1973 struct txdesc *txdesc;
b3821cc5 1974 struct jme_buffer_info *txbi;
cd0ff491 1975 u8 flags;
b3821cc5 1976
cd0ff491 1977 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT
1978 txbi = txring->bufinf + idx;
1979
1980 txdesc->dw[0] = 0;
1981 txdesc->dw[1] = 0;
1982 txdesc->dw[2] = 0;
1983 txdesc->dw[3] = 0;
1984 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1985 /*
1986 * Set OWN bit at final.
1987 * When kernel transmit faster than NIC.
1988 * And NIC trying to send this descriptor before we tell
1989 * it to start sending this TX queue.
1990 * Other fields are already filled correctly.
1991 */
1992 wmb();
1993 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT
1994 /*
1995 * Set checksum flags while not tso
1996 */
1997 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1998 jme_tx_csum(jme, skb, &flags);
b3821cc5 1999 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
3b70a6fa 2000 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT
2001 txdesc->desc1.flags = flags;
2002 /*
2003 * Set tx buffer info after telling NIC to send
2004 * For better tx_clean timing
2005 */
2006 wmb();
2007 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2008 txbi->skb = skb;
2009 txbi->len = skb->len;
cd0ff491
GFT
2010 txbi->start_xmit = jiffies;
2011 if (!txbi->start_xmit)
8d27293f 2012 txbi->start_xmit = (0UL-1);
d7699f87
GFT
2013
2014 return 0;
2015}
2016
b3821cc5
GFT
2017static void
2018jme_stop_queue_if_full(struct jme_adapter *jme)
2019{
0ede469c 2020 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT
2021 struct jme_buffer_info *txbi = txring->bufinf;
2022 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2023
cd0ff491 2024 txbi += idx;
b3821cc5
GFT
2025
2026 smp_wmb();
cd0ff491 2027 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2028 netif_stop_queue(jme->dev);
937ef75a 2029 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2030 smp_wmb();
cd0ff491
GFT
2031 if (atomic_read(&txring->nr_free)
2032 >= (jme->tx_wake_threshold)) {
b3821cc5 2033 netif_wake_queue(jme->dev);
937ef75a 2034 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT
2035 }
2036 }
2037
cd0ff491 2038 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT
2039 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2040 txbi->skb)) {
2041 netif_stop_queue(jme->dev);
937ef75a 2042 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2043 }
b3821cc5
GFT
2044}
2045
3bf61c55
GFT
2046/*
2047 * This function is already protected by netif_tx_lock()
2048 */
cd0ff491 2049
7ca9ebee 2050#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
3bf61c55 2051static int
7ca9ebee
GFT
2052#else
2053static netdev_tx_t
2054#endif
3bf61c55 2055jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2056{
cd0ff491 2057 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2058 int idx;
d7699f87 2059
cd0ff491 2060 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT
2061 ++(NET_STAT(jme).tx_dropped);
2062 return NETDEV_TX_OK;
2063 }
2064
2065 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2066
cd0ff491 2067 if (unlikely(idx < 0)) {
b3821cc5 2068 netif_stop_queue(netdev);
937ef75a
JP
2069 netif_err(jme, tx_err, jme->dev,
2070 "BUG! Tx ring full when queue awake!\n");
d7699f87 2071
cd0ff491 2072 return NETDEV_TX_BUSY;
b3821cc5
GFT
2073 }
2074
3b70a6fa 2075 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2076
4330c2f2
GFT
2077 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2078 TXCS_SELECT_QUEUE0 |
2079 TXCS_QUEUE0S |
2080 TXCS_ENABLE);
0ede469c 2081#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
d7699f87 2082 netdev->trans_start = jiffies;
0ede469c 2083#endif
d7699f87 2084
937ef75a
JP
2085 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2086 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT
2087 jme_stop_queue_if_full(jme);
2088
cd0ff491 2089 return NETDEV_TX_OK;
d7699f87
GFT
2090}
2091
3bf61c55
GFT
2092static int
2093jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2094{
cd0ff491 2095 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2096 struct sockaddr *addr = p;
cd0ff491 2097 u32 val;
d7699f87 2098
cd0ff491 2099 if (netif_running(netdev))
d7699f87
GFT
2100 return -EBUSY;
2101
cd0ff491 2102 spin_lock_bh(&jme->macaddr_lock);
d7699f87
GFT
2103 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2104
186fc259
GFT
2105 val = (addr->sa_data[3] & 0xff) << 24 |
2106 (addr->sa_data[2] & 0xff) << 16 |
2107 (addr->sa_data[1] & 0xff) << 8 |
2108 (addr->sa_data[0] & 0xff);
4330c2f2 2109 jwrite32(jme, JME_RXUMA_LO, val);
186fc259
GFT
2110 val = (addr->sa_data[5] & 0xff) << 8 |
2111 (addr->sa_data[4] & 0xff);
4330c2f2 2112 jwrite32(jme, JME_RXUMA_HI, val);
cd0ff491 2113 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT
2114
2115 return 0;
2116}
2117
3bf61c55
GFT
2118static void
2119jme_set_multi(struct net_device *netdev)
d7699f87 2120{
3bf61c55 2121 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2122 u32 mc_hash[2] = {};
7ca9ebee 2123#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
d7699f87 2124 int i;
7ca9ebee 2125#endif
d7699f87 2126
cd0ff491 2127 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT
2128
2129 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2130
cd0ff491 2131 if (netdev->flags & IFF_PROMISC) {
8c198884 2132 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2133 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2134 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2135 } else if (netdev->flags & IFF_MULTICAST) {
8e14c278 2136#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
3bf61c55 2137 struct dev_mc_list *mclist;
8e14c278
JP
2138#else
2139 struct netdev_hw_addr *ha;
2140#endif
3bf61c55 2141 int bit_nr;
d7699f87 2142
8c198884 2143 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
7ca9ebee 2144#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
3bf61c55
GFT
2145 for (i = 0, mclist = netdev->mc_list;
2146 mclist && i < netdev->mc_count;
2147 ++i, mclist = mclist->next) {
8e14c278 2148#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
7ca9ebee 2149 netdev_for_each_mc_addr(mclist, netdev) {
8e14c278
JP
2150#else
2151 netdev_for_each_mc_addr(ha, netdev) {
7ca9ebee 2152#endif
8e14c278 2153#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
cd0ff491 2154 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
8e14c278
JP
2155#else
2156 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2157#endif
cd0ff491
GFT
2158 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2159 }
d7699f87 2160
4330c2f2
GFT
2161 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2162 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT
2163 }
2164
d7699f87 2165 wmb();
8c198884
GFT
2166 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2167
cd0ff491 2168 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT
2169}
2170
3bf61c55 2171static int
8c198884 2172jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2173{
cd0ff491 2174 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2175
cd0ff491 2176 if (new_mtu == jme->old_mtu)
29bdd921
GFT
2177 return 0;
2178
cd0ff491
GFT
2179 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2180 ((new_mtu) < IPV6_MIN_MTU))
2181 return -EINVAL;
79ce639c 2182
cd0ff491 2183 if (new_mtu > 4000) {
79ce639c
GFT
2184 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2185 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2186 jme_restart_rx_engine(jme);
cd0ff491 2187 } else {
79ce639c
GFT
2188 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2189 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2190 jme_restart_rx_engine(jme);
2191 }
2192
cd0ff491 2193 if (new_mtu > 1900) {
1a0b42f4
MM
2194 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2195 NETIF_F_TSO | NETIF_F_TSO6);
cd0ff491
GFT
2196 } else {
2197 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
1a0b42f4 2198 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491 2199 if (test_bit(JME_FLAG_TSO, &jme->flags))
1a0b42f4 2200 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT
2201 }
2202
cd0ff491
GFT
2203 netdev->mtu = new_mtu;
2204 jme_reset_link(jme);
79ce639c
GFT
2205
2206 return 0;
d7699f87
GFT
2207}
2208
3bf61c55 2209static void
8c198884
GFT
2210jme_tx_timeout(struct net_device *netdev)
2211{
cd0ff491 2212 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2213
cdcdc9eb
GFT
2214 jme->phylink = 0;
2215 jme_reset_phy_processor(jme);
cd0ff491 2216 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT
2217 jme_set_settings(netdev, &jme->old_ecmd);
2218
8c198884 2219 /*
cdcdc9eb 2220 * Force to Reset the link again
8c198884 2221 */
29bdd921 2222 jme_reset_link(jme);
8c198884
GFT
2223}
2224
1e5ebebc
GFT
2225static inline void jme_pause_rx(struct jme_adapter *jme)
2226{
2227 atomic_dec(&jme->link_changing);
2228
2229 jme_set_rx_pcc(jme, PCC_OFF);
2230 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2231 JME_NAPI_DISABLE(jme);
2232 } else {
2233 tasklet_disable(&jme->rxclean_task);
2234 tasklet_disable(&jme->rxempty_task);
2235 }
2236}
2237
2238static inline void jme_resume_rx(struct jme_adapter *jme)
2239{
2240 struct dynpcc_info *dpi = &(jme->dpi);
2241
2242 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2243 JME_NAPI_ENABLE(jme);
2244 } else {
2245 tasklet_hi_enable(&jme->rxclean_task);
2246 tasklet_hi_enable(&jme->rxempty_task);
2247 }
2248 dpi->cur = PCC_P1;
2249 dpi->attempt = PCC_P1;
2250 dpi->cnt = 0;
2251 jme_set_rx_pcc(jme, PCC_P1);
2252
2253 atomic_inc(&jme->link_changing);
2254}
2255
8c198884 2256static void
42b1055e
GFT
2257jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2258{
2259 struct jme_adapter *jme = netdev_priv(netdev);
2260
1e5ebebc 2261 jme_pause_rx(jme);
42b1055e 2262 jme->vlgrp = grp;
1e5ebebc 2263 jme_resume_rx(jme);
42b1055e
GFT
2264}
2265
7ca9ebee
GFT
2266#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2267static void
2268jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2269{
2270 struct jme_adapter *jme = netdev_priv(netdev);
2271
7ca9ebee 2272 if(jme->vlgrp) {
1e5ebebc 2273 jme_pause_rx(jme);
7ca9ebee
GFT
2274#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2275 jme->vlgrp->vlan_devices[vid] = NULL;
2276#else
2277 vlan_group_set_device(jme->vlgrp, vid, NULL);
2278#endif
1e5ebebc 2279 jme_resume_rx(jme);
7ca9ebee 2280 }
7ca9ebee
GFT
2281}
2282#endif
2283
42b1055e 2284static void
3bf61c55
GFT
2285jme_get_drvinfo(struct net_device *netdev,
2286 struct ethtool_drvinfo *info)
d7699f87 2287{
cd0ff491 2288 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2289
cd0ff491
GFT
2290 strcpy(info->driver, DRV_NAME);
2291 strcpy(info->version, DRV_VERSION);
2292 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT
2293}
2294
3bf61c55 2295static int
8c198884
GFT
2296jme_get_regs_len(struct net_device *netdev)
2297{
cd0ff491 2298 return JME_REG_LEN;
8c198884
GFT
2299}
2300
2301static void
cd0ff491 2302mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT
2303{
2304 int i;
2305
cd0ff491 2306 for (i = 0 ; i < len ; i += 4)
79ce639c 2307 p[i >> 2] = jread32(jme, reg + i);
186fc259 2308}
8c198884 2309
186fc259 2310static void
cd0ff491 2311mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT
2312{
2313 int i;
cd0ff491 2314 u16 *p16 = (u16 *)p;
186fc259 2315
cd0ff491 2316 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2317 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT
2318}
2319
2320static void
2321jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2322{
cd0ff491
GFT
2323 struct jme_adapter *jme = netdev_priv(netdev);
2324 u32 *p32 = (u32 *)p;
8c198884 2325
186fc259 2326 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT
2327
2328 regs->version = 1;
2329 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2330
2331 p32 += 0x100 >> 2;
2332 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2333
2334 p32 += 0x100 >> 2;
2335 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2336
2337 p32 += 0x100 >> 2;
2338 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2339
186fc259
GFT
2340 p32 += 0x100 >> 2;
2341 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT
2342}
2343
2344static int
2345jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2346{
2347 struct jme_adapter *jme = netdev_priv(netdev);
2348
8c198884
GFT
2349 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2350 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2351
cd0ff491 2352 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT
2353 ecmd->use_adaptive_rx_coalesce = false;
2354 ecmd->rx_coalesce_usecs = 0;
2355 ecmd->rx_max_coalesced_frames = 0;
2356 return 0;
2357 }
2358
2359 ecmd->use_adaptive_rx_coalesce = true;
2360
cd0ff491 2361 switch (jme->dpi.cur) {
8c198884
GFT
2362 case PCC_P1:
2363 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2364 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2365 break;
2366 case PCC_P2:
2367 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2368 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2369 break;
2370 case PCC_P3:
2371 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2372 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2373 break;
2374 default:
2375 break;
2376 }
2377
2378 return 0;
2379}
2380
192570e0
GFT
2381static int
2382jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2383{
2384 struct jme_adapter *jme = netdev_priv(netdev);
2385 struct dynpcc_info *dpi = &(jme->dpi);
2386
cd0ff491 2387 if (netif_running(netdev))
cdcdc9eb
GFT
2388 return -EBUSY;
2389
7ca9ebee
GFT
2390 if (ecmd->use_adaptive_rx_coalesce &&
2391 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2392 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2393 jme->jme_rx = netif_rx;
2394 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT
2395 dpi->cur = PCC_P1;
2396 dpi->attempt = PCC_P1;
2397 dpi->cnt = 0;
2398 jme_set_rx_pcc(jme, PCC_P1);
2399 jme_interrupt_mode(jme);
7ca9ebee
GFT
2400 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2401 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2402 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT
2403 jme->jme_rx = netif_receive_skb;
2404 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT
2405 jme_interrupt_mode(jme);
2406 }
2407
2408 return 0;
2409}
2410
8c198884
GFT
2411static void
2412jme_get_pauseparam(struct net_device *netdev,
2413 struct ethtool_pauseparam *ecmd)
2414{
2415 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2416 u32 val;
8c198884
GFT
2417
2418 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2419 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2420
cd0ff491
GFT
2421 spin_lock_bh(&jme->phy_lock);
2422 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2423 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT
2424
2425 ecmd->autoneg =
2426 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT
2427}
2428
2429static int
2430jme_set_pauseparam(struct net_device *netdev,
2431 struct ethtool_pauseparam *ecmd)
2432{
2433 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2434 u32 val;
8c198884 2435
cd0ff491 2436 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT
2437 (ecmd->tx_pause != 0)) {
2438
cd0ff491 2439 if (ecmd->tx_pause)
8c198884
GFT
2440 jme->reg_txpfc |= TXPFC_PF_EN;
2441 else
2442 jme->reg_txpfc &= ~TXPFC_PF_EN;
2443
2444 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2445 }
2446
cd0ff491
GFT
2447 spin_lock_bh(&jme->rxmcs_lock);
2448 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT
2449 (ecmd->rx_pause != 0)) {
2450
cd0ff491 2451 if (ecmd->rx_pause)
8c198884
GFT
2452 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2453 else
2454 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2455
2456 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2457 }
cd0ff491 2458 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2459
cd0ff491
GFT
2460 spin_lock_bh(&jme->phy_lock);
2461 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2462 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT
2463 (ecmd->autoneg != 0)) {
2464
cd0ff491 2465 if (ecmd->autoneg)
8c198884
GFT
2466 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2467 else
2468 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2469
b3821cc5
GFT
2470 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2471 MII_ADVERTISE, val);
8c198884 2472 }
cd0ff491 2473 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT
2474
2475 return 0;
2476}
2477
29bdd921
GFT
2478static void
2479jme_get_wol(struct net_device *netdev,
2480 struct ethtool_wolinfo *wol)
2481{
2482 struct jme_adapter *jme = netdev_priv(netdev);
2483
2484 wol->supported = WAKE_MAGIC | WAKE_PHY;
2485
2486 wol->wolopts = 0;
2487
cd0ff491 2488 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT
2489 wol->wolopts |= WAKE_PHY;
2490
cd0ff491 2491 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT
2492 wol->wolopts |= WAKE_MAGIC;
2493
2494}
2495
2496static int
2497jme_set_wol(struct net_device *netdev,
2498 struct ethtool_wolinfo *wol)
2499{
2500 struct jme_adapter *jme = netdev_priv(netdev);
2501
cd0ff491 2502 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT
2503 WAKE_UCAST |
2504 WAKE_MCAST |
2505 WAKE_BCAST |
2506 WAKE_ARP))
2507 return -EOPNOTSUPP;
2508
2509 jme->reg_pmcs = 0;
2510
cd0ff491 2511 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT
2512 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2513
cd0ff491 2514 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT
2515 jme->reg_pmcs |= PMCS_MFEN;
2516
cd0ff491 2517 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e 2518
29bdd921
GFT
2519 return 0;
2520}
b3821cc5 2521
8c198884 2522static int
3bf61c55
GFT
2523jme_get_settings(struct net_device *netdev,
2524 struct ethtool_cmd *ecmd)
d7699f87
GFT
2525{
2526 struct jme_adapter *jme = netdev_priv(netdev);
2527 int rc;
8c198884 2528
cd0ff491 2529 spin_lock_bh(&jme->phy_lock);
d7699f87 2530 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2531 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT
2532 return rc;
2533}
2534
3bf61c55
GFT
2535static int
2536jme_set_settings(struct net_device *netdev,
2537 struct ethtool_cmd *ecmd)
d7699f87
GFT
2538{
2539 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2540 int rc, fdc = 0;
fcf45b4c 2541
cd0ff491 2542 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT
2543 return -EINVAL;
2544
e6b41b51
GFT
2545 /*
2546 * Check If user changed duplex only while force_media.
2547 * Hardware would not generate link change interrupt.
2548 */
cd0ff491 2549 if (jme->mii_if.force_media &&
79ce639c
GFT
2550 ecmd->autoneg != AUTONEG_ENABLE &&
2551 (jme->mii_if.full_duplex != ecmd->duplex))
2552 fdc = 1;
2553
cd0ff491 2554 spin_lock_bh(&jme->phy_lock);
d7699f87 2555 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2556 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2557
cd0ff491 2558 if (!rc) {
e6b41b51
GFT
2559 if (fdc)
2560 jme_reset_link(jme);
29bdd921 2561 jme->old_ecmd = *ecmd;
aa1e7189
GFT
2562 set_bit(JME_FLAG_SSET, &jme->flags);
2563 }
2564
2565 return rc;
2566}
2567
2568static int
2569jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2570{
2571 int rc;
2572 struct jme_adapter *jme = netdev_priv(netdev);
2573 struct mii_ioctl_data *mii_data = if_mii(rq);
2574 unsigned int duplex_chg;
2575
2576 if (cmd == SIOCSMIIREG) {
2577 u16 val = mii_data->val_in;
2578 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2579 (val & BMCR_SPEED1000))
2580 return -EINVAL;
2581 }
2582
2583 spin_lock_bh(&jme->phy_lock);
2584 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2585 spin_unlock_bh(&jme->phy_lock);
2586
2587 if (!rc && (cmd == SIOCSMIIREG)) {
2588 if (duplex_chg)
2589 jme_reset_link(jme);
2590 jme_get_settings(netdev, &jme->old_ecmd);
2591 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT
2592 }
2593
d7699f87
GFT
2594 return rc;
2595}
2596
cd0ff491 2597static u32
3bf61c55
GFT
2598jme_get_link(struct net_device *netdev)
2599{
d7699f87
GFT
2600 struct jme_adapter *jme = netdev_priv(netdev);
2601 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2602}
2603
8c198884 2604static u32
cd0ff491
GFT
2605jme_get_msglevel(struct net_device *netdev)
2606{
2607 struct jme_adapter *jme = netdev_priv(netdev);
2608 return jme->msg_enable;
2609}
2610
2611static void
2612jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2613{
cd0ff491
GFT
2614 struct jme_adapter *jme = netdev_priv(netdev);
2615 jme->msg_enable = value;
2616}
8c198884 2617
cd0ff491
GFT
2618static u32
2619jme_get_rx_csum(struct net_device *netdev)
2620{
2621 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2622 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2623}
2624
2625static int
2626jme_set_rx_csum(struct net_device *netdev, u32 on)
2627{
cd0ff491 2628 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2629
cd0ff491
GFT
2630 spin_lock_bh(&jme->rxmcs_lock);
2631 if (on)
8c198884
GFT
2632 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2633 else
2634 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2635 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2636 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT
2637
2638 return 0;
2639}
2640
2641static int
2642jme_set_tx_csum(struct net_device *netdev, u32 on)
2643{
cd0ff491 2644 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2645
cd0ff491
GFT
2646 if (on) {
2647 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2648 if (netdev->mtu <= 1900)
1a0b42f4
MM
2649 netdev->features |=
2650 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491
GFT
2651 } else {
2652 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
1a0b42f4
MM
2653 netdev->features &=
2654 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
b3821cc5 2655 }
8c198884
GFT
2656
2657 return 0;
2658}
2659
2660static int
b3821cc5
GFT
2661jme_set_tso(struct net_device *netdev, u32 on)
2662{
cd0ff491 2663 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2664
cd0ff491
GFT
2665 if (on) {
2666 set_bit(JME_FLAG_TSO, &jme->flags);
2667 if (netdev->mtu <= 1900)
1a0b42f4 2668 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT
2669 } else {
2670 clear_bit(JME_FLAG_TSO, &jme->flags);
1a0b42f4 2671 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT
2672 }
2673
cd0ff491 2674 return 0;
b3821cc5
GFT
2675}
2676
2677static int
8c198884
GFT
2678jme_nway_reset(struct net_device *netdev)
2679{
cd0ff491 2680 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT
2681 jme_restart_an(jme);
2682 return 0;
2683}
2684
cd0ff491 2685static u8
186fc259
GFT
2686jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2687{
cd0ff491 2688 u32 val;
186fc259
GFT
2689 int to;
2690
2691 val = jread32(jme, JME_SMBCSR);
2692 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2693 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2694 msleep(1);
2695 val = jread32(jme, JME_SMBCSR);
2696 }
cd0ff491 2697 if (!to) {
937ef75a 2698 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2699 return 0xFF;
2700 }
2701
2702 jwrite32(jme, JME_SMBINTF,
2703 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2704 SMBINTF_HWRWN_READ |
2705 SMBINTF_HWCMD);
2706
2707 val = jread32(jme, JME_SMBINTF);
2708 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2709 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2710 msleep(1);
2711 val = jread32(jme, JME_SMBINTF);
2712 }
cd0ff491 2713 if (!to) {
937ef75a 2714 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2715 return 0xFF;
2716 }
2717
2718 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2719}
2720
2721static void
cd0ff491 2722jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2723{
cd0ff491 2724 u32 val;
186fc259
GFT
2725 int to;
2726
2727 val = jread32(jme, JME_SMBCSR);
2728 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2729 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT
2730 msleep(1);
2731 val = jread32(jme, JME_SMBCSR);
2732 }
cd0ff491 2733 if (!to) {
937ef75a 2734 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2735 return;
2736 }
2737
2738 jwrite32(jme, JME_SMBINTF,
2739 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2740 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2741 SMBINTF_HWRWN_WRITE |
2742 SMBINTF_HWCMD);
2743
2744 val = jread32(jme, JME_SMBINTF);
2745 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2746 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT
2747 msleep(1);
2748 val = jread32(jme, JME_SMBINTF);
2749 }
cd0ff491 2750 if (!to) {
937ef75a 2751 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT
2752 return;
2753 }
2754
2755 mdelay(2);
2756}
2757
2758static int
2759jme_get_eeprom_len(struct net_device *netdev)
2760{
cd0ff491
GFT
2761 struct jme_adapter *jme = netdev_priv(netdev);
2762 u32 val;
186fc259 2763 val = jread32(jme, JME_SMBCSR);
cd0ff491 2764 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT
2765}
2766
2767static int
2768jme_get_eeprom(struct net_device *netdev,
2769 struct ethtool_eeprom *eeprom, u8 *data)
2770{
cd0ff491 2771 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2772 int i, offset = eeprom->offset, len = eeprom->len;
2773
2774 /*
8d27293f 2775 * ethtool will check the boundary for us
186fc259
GFT
2776 */
2777 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2778 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2779 data[i] = jme_smb_read(jme, i + offset);
2780
2781 return 0;
2782}
2783
2784static int
2785jme_set_eeprom(struct net_device *netdev,
2786 struct ethtool_eeprom *eeprom, u8 *data)
2787{
cd0ff491 2788 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT
2789 int i, offset = eeprom->offset, len = eeprom->len;
2790
2791 if (eeprom->magic != JME_EEPROM_MAGIC)
2792 return -EINVAL;
2793
2794 /*
8d27293f 2795 * ethtool will check the boundary for us
186fc259 2796 */
cd0ff491 2797 for (i = 0 ; i < len ; ++i)
186fc259
GFT
2798 jme_smb_write(jme, i + offset, data[i]);
2799
2800 return 0;
2801}
2802
3b70a6fa
GFT
2803#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2804static struct ethtool_ops jme_ethtool_ops = {
2805#else
d7699f87 2806static const struct ethtool_ops jme_ethtool_ops = {
3b70a6fa 2807#endif
cd0ff491 2808 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT
2809 .get_regs_len = jme_get_regs_len,
2810 .get_regs = jme_get_regs,
2811 .get_coalesce = jme_get_coalesce,
192570e0 2812 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT
2813 .get_pauseparam = jme_get_pauseparam,
2814 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT
2815 .get_wol = jme_get_wol,
2816 .set_wol = jme_set_wol,
d7699f87
GFT
2817 .get_settings = jme_get_settings,
2818 .set_settings = jme_set_settings,
2819 .get_link = jme_get_link,
cd0ff491
GFT
2820 .get_msglevel = jme_get_msglevel,
2821 .set_msglevel = jme_set_msglevel,
8c198884
GFT
2822 .get_rx_csum = jme_get_rx_csum,
2823 .set_rx_csum = jme_set_rx_csum,
2824 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT
2825 .set_tso = jme_set_tso,
2826 .set_sg = ethtool_op_set_sg,
8c198884 2827 .nway_reset = jme_nway_reset,
186fc259
GFT
2828 .get_eeprom_len = jme_get_eeprom_len,
2829 .get_eeprom = jme_get_eeprom,
2830 .set_eeprom = jme_set_eeprom,
d7699f87
GFT
2831};
2832
3bf61c55
GFT
2833static int
2834jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2835{
3b70a6fa 2836 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT
2837#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2838 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2839#else
2840 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2841#endif
2842 )
2843#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2844 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2845#else
cd0ff491 2846 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
0ede469c 2847#endif
3bf61c55
GFT
2848 return 1;
2849
3b70a6fa 2850 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT
2851#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2852 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2853#else
2854 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2855#endif
2856 )
2857#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2858 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2859#else
cd0ff491 2860 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
0ede469c 2861#endif
8c198884
GFT
2862 return 1;
2863
0ede469c
GFT
2864#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2865 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2866 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2867#else
cd0ff491
GFT
2868 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2869 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
0ede469c 2870#endif
3bf61c55
GFT
2871 return 0;
2872
2873 return -1;
2874}
2875
cd0ff491 2876static inline void
cdcdc9eb
GFT
2877jme_phy_init(struct jme_adapter *jme)
2878{
cd0ff491 2879 u16 reg26;
cdcdc9eb
GFT
2880
2881 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2882 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2883}
2884
cd0ff491 2885static inline void
cdcdc9eb 2886jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 2887{
cd0ff491 2888 u32 chipmode;
cdcdc9eb
GFT
2889
2890 chipmode = jread32(jme, JME_CHIPMODE);
2891
2892 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 2893 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
98ef18f1
GFT
2894 jme->chip_main_rev = jme->chiprev & 0xF;
2895 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT
2896}
2897
3b70a6fa
GFT
2898#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2899static const struct net_device_ops jme_netdev_ops = {
2900 .ndo_open = jme_open,
2901 .ndo_stop = jme_close,
2902 .ndo_validate_addr = eth_validate_addr,
aa1e7189 2903 .ndo_do_ioctl = jme_ioctl,
3b70a6fa
GFT
2904 .ndo_start_xmit = jme_start_xmit,
2905 .ndo_set_mac_address = jme_set_macaddr,
2906 .ndo_set_multicast_list = jme_set_multi,
2907 .ndo_change_mtu = jme_change_mtu,
2908 .ndo_tx_timeout = jme_tx_timeout,
2909 .ndo_vlan_rx_register = jme_vlan_rx_register,
2910};
2911#endif
2912
3bf61c55
GFT
2913static int __devinit
2914jme_init_one(struct pci_dev *pdev,
2915 const struct pci_device_id *ent)
2916{
cdcdc9eb 2917 int rc = 0, using_dac, i;
d7699f87
GFT
2918 struct net_device *netdev;
2919 struct jme_adapter *jme;
cd0ff491
GFT
2920 u16 bmcr, bmsr;
2921 u32 apmc;
d7699f87
GFT
2922
2923 /*
2924 * set up PCI device basics
2925 */
4330c2f2 2926 rc = pci_enable_device(pdev);
cd0ff491 2927 if (rc) {
937ef75a 2928 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT
2929 goto err_out;
2930 }
d7699f87 2931
3bf61c55 2932 using_dac = jme_pci_dma64(pdev);
cd0ff491 2933 if (using_dac < 0) {
937ef75a 2934 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT
2935 rc = -EIO;
2936 goto err_out_disable_pdev;
2937 }
2938
cd0ff491 2939 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
937ef75a 2940 pr_err("No PCI resource region found\n");
4330c2f2
GFT
2941 rc = -ENOMEM;
2942 goto err_out_disable_pdev;
2943 }
d7699f87 2944
4330c2f2 2945 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 2946 if (rc) {
937ef75a 2947 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT
2948 goto err_out_disable_pdev;
2949 }
d7699f87
GFT
2950
2951 pci_set_master(pdev);
2952
2953 /*
2954 * alloc and init net device
2955 */
3bf61c55 2956 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 2957 if (!netdev) {
937ef75a 2958 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT
2959 rc = -ENOMEM;
2960 goto err_out_release_regions;
d7699f87 2961 }
3b70a6fa
GFT
2962#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2963 netdev->netdev_ops = &jme_netdev_ops;
2964#else
d7699f87
GFT
2965 netdev->open = jme_open;
2966 netdev->stop = jme_close;
aa1e7189 2967 netdev->do_ioctl = jme_ioctl;
d7699f87 2968 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT
2969 netdev->set_mac_address = jme_set_macaddr;
2970 netdev->set_multicast_list = jme_set_multi;
2971 netdev->change_mtu = jme_change_mtu;
8c198884 2972 netdev->tx_timeout = jme_tx_timeout;
42b1055e 2973 netdev->vlan_rx_register = jme_vlan_rx_register;
7ca9ebee
GFT
2974#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2975 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
2976#endif
3bf61c55 2977 NETDEV_GET_STATS(netdev, &jme_get_stats);
3b70a6fa
GFT
2978#endif
2979 netdev->ethtool_ops = &jme_ethtool_ops;
2980 netdev->watchdog_timeo = TX_TIMEOUT;
1a0b42f4
MM
2981 netdev->features = NETIF_F_IP_CSUM |
2982 NETIF_F_IPV6_CSUM |
b3821cc5
GFT
2983 NETIF_F_SG |
2984 NETIF_F_TSO |
2985 NETIF_F_TSO6 |
42b1055e
GFT
2986 NETIF_F_HW_VLAN_TX |
2987 NETIF_F_HW_VLAN_RX;
cd0ff491 2988 if (using_dac)
8c198884 2989 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT
2990
2991 SET_NETDEV_DEV(netdev, &pdev->dev);
2992 pci_set_drvdata(pdev, netdev);
2993
2994 /*
2995 * init adapter info
2996 */
2997 jme = netdev_priv(netdev);
2998 jme->pdev = pdev;
2999 jme->dev = netdev;
cdcdc9eb
GFT
3000 jme->jme_rx = netif_rx;
3001 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 3002 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 3003 jme->phylink = 0;
b3821cc5 3004 jme->tx_ring_size = 1 << 10;
0ede469c 3005 jme->tx_ring_mask = jme->tx_ring_size - 1;
b3821cc5
GFT
3006 jme->tx_wake_threshold = 1 << 9;
3007 jme->rx_ring_size = 1 << 9;
3008 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 3009 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT
3010 jme->regs = ioremap(pci_resource_start(pdev, 0),
3011 pci_resource_len(pdev, 0));
4330c2f2 3012 if (!(jme->regs)) {
937ef75a 3013 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT
3014 rc = -ENOMEM;
3015 goto err_out_free_netdev;
3016 }
4330c2f2 3017
cd0ff491
GFT
3018 if (no_pseudohp) {
3019 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3020 jwrite32(jme, JME_APMC, apmc);
3021 } else if (force_pseudohp) {
3022 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3023 jwrite32(jme, JME_APMC, apmc);
3024 }
3025
cdcdc9eb 3026 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 3027
d7699f87 3028 spin_lock_init(&jme->phy_lock);
fcf45b4c 3029 spin_lock_init(&jme->macaddr_lock);
8c198884 3030 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 3031
fcf45b4c
GFT
3032 atomic_set(&jme->link_changing, 1);
3033 atomic_set(&jme->rx_cleaning, 1);
3034 atomic_set(&jme->tx_cleaning, 1);
192570e0 3035 atomic_set(&jme->rx_empty, 1);
fcf45b4c 3036
79ce639c 3037 tasklet_init(&jme->pcc_task,
7ca9ebee 3038 jme_pcc_tasklet,
79ce639c 3039 (unsigned long) jme);
4330c2f2 3040 tasklet_init(&jme->linkch_task,
7ca9ebee 3041 jme_link_change_tasklet,
4330c2f2
GFT
3042 (unsigned long) jme);
3043 tasklet_init(&jme->txclean_task,
7ca9ebee 3044 jme_tx_clean_tasklet,
4330c2f2
GFT
3045 (unsigned long) jme);
3046 tasklet_init(&jme->rxclean_task,
7ca9ebee 3047 jme_rx_clean_tasklet,
4330c2f2 3048 (unsigned long) jme);
fcf45b4c 3049 tasklet_init(&jme->rxempty_task,
7ca9ebee 3050 jme_rx_empty_tasklet,
fcf45b4c 3051 (unsigned long) jme);
0ede469c 3052 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT
3053 tasklet_disable_nosync(&jme->txclean_task);
3054 tasklet_disable_nosync(&jme->rxclean_task);
3055 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT
3056 jme->dpi.cur = PCC_P1;
3057
cd0ff491 3058 jme->reg_ghc = 0;
79ce639c 3059 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT
3060 jme->reg_rxmcs = RXMCS_DEFAULT;
3061 jme->reg_txpfc = 0;
47220951 3062 jme->reg_pmcs = PMCS_MFEN;
cd0ff491
GFT
3063 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3064 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 3065
d7699f87 3066 /*
fcf45b4c
GFT
3067 * Get Max Read Req Size from PCI Config Space
3068 */
cd0ff491
GFT
3069 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3070 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3071 switch (jme->mrrs) {
3072 case MRRS_128B:
3073 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3074 break;
3075 case MRRS_256B:
3076 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3077 break;
3078 default:
3079 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3080 break;
cd54cf32 3081 }
fcf45b4c 3082
fcf45b4c 3083 /*
cdcdc9eb 3084 * Must check before reset_mac_processor
d7699f87 3085 */
cdcdc9eb
GFT
3086 jme_check_hw_ver(jme);
3087 jme->mii_if.dev = netdev;
cd0ff491 3088 if (jme->fpgaver) {
cdcdc9eb 3089 jme->mii_if.phy_id = 0;
cd0ff491 3090 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT
3091 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3092 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3093 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT
3094 jme->mii_if.phy_id = i;
3095 break;
3096 }
3097 }
3098
cd0ff491 3099 if (!jme->mii_if.phy_id) {
cdcdc9eb 3100 rc = -EIO;
937ef75a
JP
3101 pr_err("Can not find phy_id\n");
3102 goto err_out_unmap;
cdcdc9eb
GFT
3103 }
3104
3105 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3106 } else {
cdcdc9eb
GFT
3107 jme->mii_if.phy_id = 1;
3108 }
cd0ff491 3109 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT
3110 jme->mii_if.supports_gmii = true;
3111 else
3112 jme->mii_if.supports_gmii = false;
aa1e7189
GFT
3113 jme->mii_if.phy_id_mask = 0x1F;
3114 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT
3115 jme->mii_if.mdio_read = jme_mdio_read;
3116 jme->mii_if.mdio_write = jme_mdio_write;
3117
d7699f87 3118 jme_clear_pm(jme);
58c92f28 3119 jme_set_phyfifoa(jme);
98ef18f1 3120 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
cd0ff491 3121 if (!jme->fpgaver)
cdcdc9eb 3122 jme_phy_init(jme);
42b1055e 3123 jme_phy_off(jme);
cdcdc9eb
GFT
3124
3125 /*
3126 * Reset MAC processor and reload EEPROM for MAC Address
3127 */
d7699f87 3128 jme_reset_mac_processor(jme);
4330c2f2 3129 rc = jme_reload_eeprom(jme);
cd0ff491 3130 if (rc) {
937ef75a 3131 pr_err("Reload eeprom for reading MAC Address error\n");
0ede469c 3132 goto err_out_unmap;
4330c2f2 3133 }
d7699f87
GFT
3134 jme_load_macaddr(netdev);
3135
d7699f87
GFT
3136 /*
3137 * Tell stack that we are not ready to work until open()
3138 */
3139 netif_carrier_off(netdev);
d7699f87 3140
4330c2f2 3141 rc = register_netdev(netdev);
cd0ff491 3142 if (rc) {
937ef75a 3143 pr_err("Cannot register net device\n");
0ede469c 3144 goto err_out_unmap;
4330c2f2 3145 }
d7699f87 3146
98ef18f1 3147 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
937ef75a 3148 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
7ca9ebee
GFT
3149 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3150 "JMC250 Gigabit Ethernet" :
3151 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3152 "JMC260 Fast Ethernet" : "Unknown",
3153 (jme->fpgaver != 0) ? " (FPGA)" : "",
3154 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
98ef18f1 3155 jme->pcirev,
937ef75a
JP
3156 netdev->dev_addr[0],
3157 netdev->dev_addr[1],
3158 netdev->dev_addr[2],
3159 netdev->dev_addr[3],
3160 netdev->dev_addr[4],
3161 netdev->dev_addr[5]);
d7699f87
GFT
3162
3163 return 0;
3164
3165err_out_unmap:
3166 iounmap(jme->regs);
3167err_out_free_netdev:
3168 pci_set_drvdata(pdev, NULL);
3169 free_netdev(netdev);
4330c2f2
GFT
3170err_out_release_regions:
3171 pci_release_regions(pdev);
d7699f87 3172err_out_disable_pdev:
cd0ff491 3173 pci_disable_device(pdev);
d7699f87 3174err_out:
4330c2f2 3175 return rc;
d7699f87
GFT
3176}
3177
3bf61c55
GFT
3178static void __devexit
3179jme_remove_one(struct pci_dev *pdev)
3180{
d7699f87
GFT
3181 struct net_device *netdev = pci_get_drvdata(pdev);
3182 struct jme_adapter *jme = netdev_priv(netdev);
3183
3184 unregister_netdev(netdev);
3185 iounmap(jme->regs);
3186 pci_set_drvdata(pdev, NULL);
3187 free_netdev(netdev);
3188 pci_release_regions(pdev);
3189 pci_disable_device(pdev);
3190
3191}
3192
a82e368c
GFT
3193static void
3194jme_shutdown(struct pci_dev *pdev)
3195{
3196 struct net_device *netdev = pci_get_drvdata(pdev);
3197 struct jme_adapter *jme = netdev_priv(netdev);
3198
3199 jme_powersave_phy(jme);
3200#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3201 pci_enable_wake(pdev, PCI_D3hot, true);
3202#else
3203 pci_pme_active(pdev, true);
3204#endif
3205}
3206
7ee473a3 3207#ifdef CONFIG_PM
29bdd921
GFT
3208static int
3209jme_suspend(struct pci_dev *pdev, pm_message_t state)
3210{
3211 struct net_device *netdev = pci_get_drvdata(pdev);
3212 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT
3213
3214 atomic_dec(&jme->link_changing);
3215
3216 netif_device_detach(netdev);
3217 netif_stop_queue(netdev);
3218 jme_stop_irq(jme);
29bdd921 3219
cd0ff491
GFT
3220 tasklet_disable(&jme->txclean_task);
3221 tasklet_disable(&jme->rxclean_task);
3222 tasklet_disable(&jme->rxempty_task);
3223
cd0ff491
GFT
3224 if (netif_carrier_ok(netdev)) {
3225 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT
3226 jme_polling_mode(jme);
3227
29bdd921 3228 jme_stop_pcc_timer(jme);
cd0ff491
GFT
3229 jme_reset_ghc_speed(jme);
3230 jme_disable_rx_engine(jme);
3231 jme_disable_tx_engine(jme);
29bdd921
GFT
3232 jme_reset_mac_processor(jme);
3233 jme_free_rx_resources(jme);
3234 jme_free_tx_resources(jme);
3235 netif_carrier_off(netdev);
3236 jme->phylink = 0;
3237 }
3238
cd0ff491
GFT
3239 tasklet_enable(&jme->txclean_task);
3240 tasklet_hi_enable(&jme->rxclean_task);
3241 tasklet_hi_enable(&jme->rxempty_task);
29bdd921
GFT
3242
3243 pci_save_state(pdev);
a82e368c
GFT
3244 jme_powersave_phy(jme);
3245 pci_enable_wake(pdev, PCI_D3hot, true);
3246 pci_set_power_state(pdev, PCI_D3hot);
29bdd921
GFT
3247
3248 return 0;
3249}
3250
3251static int
3252jme_resume(struct pci_dev *pdev)
3253{
3254 struct net_device *netdev = pci_get_drvdata(pdev);
3255 struct jme_adapter *jme = netdev_priv(netdev);
3256
3257 jme_clear_pm(jme);
3258 pci_restore_state(pdev);
3259
ed457bcc
GFT
3260 jme_phy_on(jme);
3261 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3262 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 3263 else
29bdd921
GFT
3264 jme_reset_phy_processor(jme);
3265
29bdd921
GFT
3266 jme_start_irq(jme);
3267 netif_device_attach(netdev);
3268
3269 atomic_inc(&jme->link_changing);
3270
3271 jme_reset_link(jme);
3272
3273 return 0;
3274}
7ee473a3 3275#endif
29bdd921 3276
7ca9ebee 3277#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
d7699f87 3278static struct pci_device_id jme_pci_tbl[] = {
7ca9ebee
GFT
3279#else
3280static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3281#endif
cd0ff491
GFT
3282 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3283 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT
3284 { }
3285};
3286
3287static struct pci_driver jme_driver = {
cd0ff491
GFT
3288 .name = DRV_NAME,
3289 .id_table = jme_pci_tbl,
3290 .probe = jme_init_one,
3291 .remove = __devexit_p(jme_remove_one),
d7699f87 3292#ifdef CONFIG_PM
cd0ff491
GFT
3293 .suspend = jme_suspend,
3294 .resume = jme_resume,
d7699f87 3295#endif /* CONFIG_PM */
a82e368c 3296 .shutdown = jme_shutdown,
d7699f87
GFT
3297};
3298
3bf61c55
GFT
3299static int __init
3300jme_init_module(void)
d7699f87 3301{
937ef75a 3302 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT
3303 return pci_register_driver(&jme_driver);
3304}
3305
3bf61c55
GFT
3306static void __exit
3307jme_cleanup_module(void)
d7699f87
GFT
3308{
3309 pci_unregister_driver(&jme_driver);
3310}
3311
3312module_init(jme_init_module);
3313module_exit(jme_cleanup_module);
3314
3bf61c55 3315MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT
3316MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3317MODULE_LICENSE("GPL");
3318MODULE_VERSION(DRV_VERSION);
3319MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3320