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[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
eacd73f7 42#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720 48static const char ixgbe_driver_string[] =
b4617240 49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 50
ba98898e 51#define DRV_VERSION "2.0.24-k2"
9c8eb720 52const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 53static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 54
55static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 56 [board_82598] = &ixgbe_82598_info,
e8e26350 57 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 74 board_82598 },
0befdb3e
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 78 board_82598 },
8d792cd9
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
80 board_82598 },
c4900be0
DS		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
84 board_82598 },
b95f5fcb
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
88 board_82598 },
2f21bdd3
DS		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
90 board_82598 },
e8e26350
PW		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
92 board_82599 },
1fcf03e6
PWJ		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
94 board_82599 },
e8e26350
PW		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
96 board_82599 },
9a799d71
AK		 97
98 /* required last entry */
99 {0, }
100};
101MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
102
5dd2d332 103#ifdef CONFIG_IXGBE_DCA
bd0362dd 104static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 105 void *p);
bd0362dd
JC		 106static struct notifier_block dca_notifier = {
107 .notifier_call = ixgbe_notify_dca,
108 .next = NULL,
109 .priority = 0
110};
111#endif
112
9a799d71
AK		 113MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
114MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
115MODULE_LICENSE("GPL");
116MODULE_VERSION(DRV_VERSION);
117
118#define DEFAULT_DEBUG_LEVEL_SHIFT 3
119
5eba3699
AV		 120static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
121{
122 u32 ctrl_ext;
123
124 /* Let firmware take over control of h/w */
125 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
126 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 127 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 128}
129
130static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
131{
132 u32 ctrl_ext;
133
134 /* Let firmware know the driver has taken over */
135 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
136 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 137 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 138}
9a799d71 139
e8e26350
PW		 140/*
141 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
142 * @adapter: pointer to adapter struct
143 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
144 * @queue: queue to map the corresponding interrupt to
145 * @msix_vector: the vector to map to the corresponding queue
146 *
147 */
148static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
149 u8 queue, u8 msix_vector)
9a799d71
AK		 150{
151 u32 ivar, index;
e8e26350
PW		 152 struct ixgbe_hw *hw = &adapter->hw;
153 switch (hw->mac.type) {
154 case ixgbe_mac_82598EB:
155 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
156 if (direction == -1)
157 direction = 0;
158 index = (((direction * 64) + queue) >> 2) & 0x1F;
159 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
160 ivar &= ~(0xFF << (8 * (queue & 0x3)));
161 ivar |= (msix_vector << (8 * (queue & 0x3)));
162 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
163 break;
164 case ixgbe_mac_82599EB:
165 if (direction == -1) {
166 /* other causes */
167 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
168 index = ((queue & 1) * 8);
169 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
170 ivar &= ~(0xFF << index);
171 ivar |= (msix_vector << index);
172 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
173 break;
174 } else {
175 /* tx or rx causes */
176 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
177 index = ((16 * (queue & 1)) + (8 * direction));
178 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
179 ivar &= ~(0xFF << index);
180 ivar |= (msix_vector << index);
181 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
182 break;
183 }
184 default:
185 break;
186 }
9a799d71
AK		 187}
188
189static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 190 struct ixgbe_tx_buffer
191 *tx_buffer_info)
9a799d71 192{
44df32c5 193 tx_buffer_info->dma = 0;
9a799d71 194 if (tx_buffer_info->skb) {
44df32c5
AD		 195 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
196 DMA_TO_DEVICE);
9a799d71
AK		 197 dev_kfree_skb_any(tx_buffer_info->skb);
198 tx_buffer_info->skb = NULL;
199 }
44df32c5 200 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 201 /* tx_buffer_info must be completely set up in the transmit path */
202}
203
204static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 205 struct ixgbe_ring *tx_ring,
206 unsigned int eop)
9a799d71 207{
e01c31a5 208 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 209
9a799d71 210 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 211 * check with the clearing of time_stamp and movement of eop */
9a799d71 212 adapter->detect_tx_hung = false;
44df32c5 213 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 214 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
215 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
216 /* detected Tx unit hang */
e01c31a5
JB		 217 union ixgbe_adv_tx_desc *tx_desc;
218 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 219 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 220 " Tx Queue <%d>\n"
221 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 222 " next_to_use <%x>\n"
223 " next_to_clean <%x>\n"
224 "tx_buffer_info[next_to_clean]\n"
225 " time_stamp <%lx>\n"
e01c31a5
JB		 226 " jiffies <%lx>\n",
227 tx_ring->queue_index,
44df32c5
AD		 228 IXGBE_READ_REG(hw, tx_ring->head),
229 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 230 tx_ring->next_to_use, eop,
231 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 232 return true;
233 }
234
235 return false;
236}
237
b4617240
PW		 238#define IXGBE_MAX_TXD_PWR 14
239#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 240
241/* Tx Descriptors needed, worst case */
242#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
243 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
244#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 245 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 246
e01c31a5
JB		 247static void ixgbe_tx_timeout(struct net_device *netdev);
248
9a799d71
AK		 249/**
250 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
251 * @adapter: board private structure
e01c31a5 252 * @tx_ring: tx ring to clean
9a1a69ad
JB		 253 *
254 * returns true if transmit work is done
9a799d71
AK		 255 **/
256static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 257 struct ixgbe_ring *tx_ring)
9a799d71 258{
e01c31a5 259 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 260 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
261 struct ixgbe_tx_buffer *tx_buffer_info;
262 unsigned int i, eop, count = 0;
e01c31a5 263 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 264
265 i = tx_ring->next_to_clean;
12207e49
PWJ		 266 eop = tx_ring->tx_buffer_info[i].next_to_watch;
267 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
268
269 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 270 (count < tx_ring->work_limit)) {
12207e49
PWJ		 271 bool cleaned = false;
272 for ( ; !cleaned; count++) {
273 struct sk_buff *skb;
9a799d71
AK		 274 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
275 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 276 cleaned = (i == eop);
e01c31a5 277 skb = tx_buffer_info->skb;
9a799d71 278
12207e49 279 if (cleaned && skb) {
e092be60 280 unsigned int segs, bytecount;
e01c31a5
JB		 281
282 /* gso_segs is currently only valid for tcp */
e092be60
AV		 283 segs = skb_shinfo(skb)->gso_segs ?: 1;
284 /* multiply data chunks by size of headers */
285 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 286 skb->len;
287 total_packets += segs;
288 total_bytes += bytecount;
e092be60 289 }
e01c31a5 290
9a799d71 291 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 292 tx_buffer_info);
9a799d71 293
12207e49
PWJ		 294 tx_desc->wb.status = 0;
295
9a799d71
AK		 296 i++;
297 if (i == tx_ring->count)
298 i = 0;
e01c31a5 299 }
12207e49
PWJ		 300
301 eop = tx_ring->tx_buffer_info[i].next_to_watch;
302 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
303 }
304
9a799d71
AK		 305 tx_ring->next_to_clean = i;
306
e092be60 307#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 308 if (unlikely(count && netif_carrier_ok(netdev) &&
309 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 310 /* Make sure that anybody stopping the queue after this
311 * sees the new next_to_clean.
312 */
313 smp_mb();
30eba97a
AV		 314 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
315 !test_bit(__IXGBE_DOWN, &adapter->state)) {
316 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 317 ++adapter->restart_queue;
30eba97a 318 }
e092be60 319 }
9a799d71 320
e01c31a5
JB		 321 if (adapter->detect_tx_hung) {
322 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
323 /* schedule immediate reset if we believe we hung */
324 DPRINTK(PROBE, INFO,
325 "tx hang %d detected, resetting adapter\n",
326 adapter->tx_timeout_count + 1);
327 ixgbe_tx_timeout(adapter->netdev);
328 }
329 }
9a799d71 330
e01c31a5 331 /* re-arm the interrupt */
835462fc
NS		 332 if (count >= tx_ring->work_limit) {
333 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
335 tx_ring->v_idx);
336 else if (tx_ring->v_idx & 0xFFFFFFFF)
337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
338 tx_ring->v_idx);
339 else
340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
341 (tx_ring->v_idx >> 32));
342 }
343
9a799d71 344
e01c31a5
JB		 345 tx_ring->total_bytes += total_bytes;
346 tx_ring->total_packets += total_packets;
e01c31a5 347 tx_ring->stats.packets += total_packets;
12207e49 348 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 349 adapter->net_stats.tx_bytes += total_bytes;
350 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 351 return (count < tx_ring->work_limit);
9a799d71
AK		 352}
353
5dd2d332 354#ifdef CONFIG_IXGBE_DCA
bd0362dd 355static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 356 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 357{
358 u32 rxctrl;
359 int cpu = get_cpu();
3a581073 360 int q = rx_ring - adapter->rx_ring;
bd0362dd 361
3a581073 362 if (rx_ring->cpu != cpu) {
bd0362dd 363 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 364 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
365 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
366 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
367 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
368 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
369 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
370 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
371 }
bd0362dd
JC		 372 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
373 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 374 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
375 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 376 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 377 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 378 rx_ring->cpu = cpu;
bd0362dd
JC		 379 }
380 put_cpu();
381}
382
383static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 384 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 385{
386 u32 txctrl;
387 int cpu = get_cpu();
3a581073 388 int q = tx_ring - adapter->tx_ring;
bd0362dd 389
3a581073 390 if (tx_ring->cpu != cpu) {
bd0362dd 391 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 392 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
393 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
394 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
395 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
396 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
397 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
398 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
399 }
bd0362dd
JC		 400 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
401 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 402 tx_ring->cpu = cpu;
bd0362dd
JC		 403 }
404 put_cpu();
405}
406
407static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
408{
409 int i;
410
411 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
412 return;
413
e35ec126
AD		 414 /* always use CB2 mode, difference is masked in the CB driver */
415 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
416
bd0362dd
JC		 417 for (i = 0; i < adapter->num_tx_queues; i++) {
418 adapter->tx_ring[i].cpu = -1;
419 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
420 }
421 for (i = 0; i < adapter->num_rx_queues; i++) {
422 adapter->rx_ring[i].cpu = -1;
423 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
424 }
425}
426
427static int __ixgbe_notify_dca(struct device *dev, void *data)
428{
429 struct net_device *netdev = dev_get_drvdata(dev);
430 struct ixgbe_adapter *adapter = netdev_priv(netdev);
431 unsigned long event = *(unsigned long *)data;
432
433 switch (event) {
434 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 435 /* if we're already enabled, don't do it again */
436 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
437 break;
652f093f 438 if (dca_add_requester(dev) == 0) {
96b0e0f6 439 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 440 ixgbe_setup_dca(adapter);
441 break;
442 }
443 /* Fall Through since DCA is disabled. */
444 case DCA_PROVIDER_REMOVE:
445 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
446 dca_remove_requester(dev);
447 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
448 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
449 }
450 break;
451 }
452
652f093f 453 return 0;
bd0362dd
JC		 454}
455
5dd2d332 456#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 457/**
458 * ixgbe_receive_skb - Send a completed packet up the stack
459 * @adapter: board private structure
460 * @skb: packet to send up
177db6ff
MC		 461 * @status: hardware indication of status of receive
462 * @rx_ring: rx descriptor ring (for a specific queue) to setup
463 * @rx_desc: rx descriptor
9a799d71 464 **/
78b6f4ce 465static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 466 struct sk_buff *skb, u8 status,
fdaff1ce 467 struct ixgbe_ring *ring,
177db6ff 468 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 469{
78b6f4ce
HX		 470 struct ixgbe_adapter *adapter = q_vector->adapter;
471 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 472 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
473 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 474
fdaff1ce 475 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 476 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 477 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 478 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 479 else
78b6f4ce 480 napi_gro_receive(napi, skb);
177db6ff 481 } else {
182ff8df
AD		 482 if (adapter->vlgrp && is_vlan && (tag != 0))
483 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
484 else
485 netif_rx(skb);
9a799d71
AK		 486 }
487}
488
e59bd25d
AV		 489/**
490 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
491 * @adapter: address of board private structure
492 * @status_err: hardware indication of status of receive
493 * @skb: skb currently being received and modified
494 **/
9a799d71 495static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 496 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 497{
498 skb->ip_summed = CHECKSUM_NONE;
499
712744be
JB		 500 /* Rx csum disabled */
501 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 502 return;
e59bd25d
AV		 503
504 /* if IP and error */
505 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
506 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 507 adapter->hw_csum_rx_error++;
508 return;
509 }
e59bd25d
AV		 510
511 if (!(status_err & IXGBE_RXD_STAT_L4CS))
512 return;
513
514 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
515 adapter->hw_csum_rx_error++;
516 return;
517 }
518
9a799d71 519 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 520 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 521 adapter->hw_csum_rx_good++;
522}
523
e8e26350
PW		 524static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
525 struct ixgbe_ring *rx_ring, u32 val)
526{
527 /*
528 * Force memory writes to complete before letting h/w
529 * know there are new descriptors to fetch. (Only
530 * applicable for weak-ordered memory model archs,
531 * such as IA-64).
532 */
533 wmb();
534 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
535}
536
9a799d71
AK		 537/**
538 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
539 * @adapter: address of board private structure
540 **/
541static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 542 struct ixgbe_ring *rx_ring,
543 int cleaned_count)
9a799d71 544{
9a799d71
AK		 545 struct pci_dev *pdev = adapter->pdev;
546 union ixgbe_adv_rx_desc *rx_desc;
3a581073 547 struct ixgbe_rx_buffer *bi;
9a799d71 548 unsigned int i;
e8e26350 549 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 550
551 i = rx_ring->next_to_use;
3a581073 552 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 553
554 while (cleaned_count--) {
555 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
556
762f4c57 557 if (!bi->page_dma &&
3a581073 558 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 559 if (!bi->page) {
762f4c57
JB		 560 bi->page = alloc_page(GFP_ATOMIC);
561 if (!bi->page) {
562 adapter->alloc_rx_page_failed++;
563 goto no_buffers;
564 }
565 bi->page_offset = 0;
566 } else {
567 /* use a half page if we're re-using */
568 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 569 }
762f4c57
JB		 570
571 bi->page_dma = pci_map_page(pdev, bi->page,
572 bi->page_offset,
573 (PAGE_SIZE / 2),
574 PCI_DMA_FROMDEVICE);
9a799d71
AK		 575 }
576
3a581073 577 if (!bi->skb) {
5ecc3614 578 struct sk_buff *skb;
e8e26350 579 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 580
581 if (!skb) {
582 adapter->alloc_rx_buff_failed++;
583 goto no_buffers;
584 }
585
586 /*
587 * Make buffer alignment 2 beyond a 16 byte boundary
588 * this will result in a 16 byte aligned IP header after
589 * the 14 byte MAC header is removed
590 */
591 skb_reserve(skb, NET_IP_ALIGN);
592
3a581073 593 bi->skb = skb;
e8e26350 594 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 595 PCI_DMA_FROMDEVICE);
9a799d71
AK		 596 }
597 /* Refresh the desc even if buffer_addrs didn't change because
598 * each write-back erases this info. */
599 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 600 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
601 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 602 } else {
3a581073 603 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 604 }
605
606 i++;
607 if (i == rx_ring->count)
608 i = 0;
3a581073 609 bi = &rx_ring->rx_buffer_info[i];
9a799d71 610 }
7c6e0a43 611
9a799d71
AK		 612no_buffers:
613 if (rx_ring->next_to_use != i) {
614 rx_ring->next_to_use = i;
615 if (i-- == 0)
616 i = (rx_ring->count - 1);
617
e8e26350 618 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 619 }
620}
621
7c6e0a43
JB		 622static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
623{
624 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
625}
626
627static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
628{
629 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
630}
631
f8212f97
AD		 632static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
633{
634 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
635 IXGBE_RXDADV_RSCCNT_MASK) >>
636 IXGBE_RXDADV_RSCCNT_SHIFT;
637}
638
639/**
640 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
641 * @skb: pointer to the last skb in the rsc queue
642 *
643 * This function changes a queue full of hw rsc buffers into a completed
644 * packet. It uses the ->prev pointers to find the first packet and then
645 * turns it into the frag list owner.
646 **/
647static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
648{
649 unsigned int frag_list_size = 0;
650
651 while (skb->prev) {
652 struct sk_buff *prev = skb->prev;
653 frag_list_size += skb->len;
654 skb->prev = NULL;
655 skb = prev;
656 }
657
658 skb_shinfo(skb)->frag_list = skb->next;
659 skb->next = NULL;
660 skb->len += frag_list_size;
661 skb->data_len += frag_list_size;
662 skb->truesize += frag_list_size;
663 return skb;
664}
665
78b6f4ce 666static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 667 struct ixgbe_ring *rx_ring,
668 int *work_done, int work_to_do)
9a799d71 669{
78b6f4ce 670 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 671 struct pci_dev *pdev = adapter->pdev;
672 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
673 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
674 struct sk_buff *skb;
f8212f97 675 unsigned int i, rsc_count = 0;
7c6e0a43 676 u32 len, staterr;
177db6ff
MC		 677 u16 hdr_info;
678 bool cleaned = false;
9a799d71 679 int cleaned_count = 0;
d2f4fbe2 680 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 681
682 i = rx_ring->next_to_clean;
9a799d71
AK		 683 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
684 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
685 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 686
687 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 688 u32 upper_len = 0;
9a799d71
AK		 689 if (*work_done >= work_to_do)
690 break;
691 (*work_done)++;
692
693 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 694 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
695 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 696 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 697 if (hdr_info & IXGBE_RXDADV_SPH)
698 adapter->rx_hdr_split++;
699 if (len > IXGBE_RX_HDR_SIZE)
700 len = IXGBE_RX_HDR_SIZE;
701 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 702 } else {
9a799d71 703 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 704 }
9a799d71
AK		 705
706 cleaned = true;
707 skb = rx_buffer_info->skb;
708 prefetch(skb->data - NET_IP_ALIGN);
709 rx_buffer_info->skb = NULL;
710
711 if (len && !skb_shinfo(skb)->nr_frags) {
712 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 713 rx_ring->rx_buf_len,
b4617240 714 PCI_DMA_FROMDEVICE);
9a799d71
AK		 715 skb_put(skb, len);
716 }
717
718 if (upper_len) {
719 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 720 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 721 rx_buffer_info->page_dma = 0;
722 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 723 rx_buffer_info->page,
724 rx_buffer_info->page_offset,
725 upper_len);
726
727 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
728 (page_count(rx_buffer_info->page) != 1))
729 rx_buffer_info->page = NULL;
730 else
731 get_page(rx_buffer_info->page);
9a799d71
AK		 732
733 skb->len += upper_len;
734 skb->data_len += upper_len;
735 skb->truesize += upper_len;
736 }
737
738 i++;
739 if (i == rx_ring->count)
740 i = 0;
9a799d71
AK		 741
742 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
743 prefetch(next_rxd);
9a799d71 744 cleaned_count++;
f8212f97
AD		 745
746 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
747 rsc_count = ixgbe_get_rsc_count(rx_desc);
748
749 if (rsc_count) {
750 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
751 IXGBE_RXDADV_NEXTP_SHIFT;
752 next_buffer = &rx_ring->rx_buffer_info[nextp];
753 rx_ring->rsc_count += (rsc_count - 1);
754 } else {
755 next_buffer = &rx_ring->rx_buffer_info[i];
756 }
757
9a799d71 758 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 759 if (skb->prev)
760 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 761 rx_ring->stats.packets++;
762 rx_ring->stats.bytes += skb->len;
763 } else {
f8212f97
AD		 764 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
765 rx_buffer_info->skb = next_buffer->skb;
766 rx_buffer_info->dma = next_buffer->dma;
767 next_buffer->skb = skb;
768 next_buffer->dma = 0;
769 } else {
770 skb->next = next_buffer->skb;
771 skb->next->prev = skb;
772 }
9a799d71
AK		 773 adapter->non_eop_descs++;
774 goto next_desc;
775 }
776
777 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
778 dev_kfree_skb_irq(skb);
779 goto next_desc;
780 }
781
782 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 783
784 /* probably a little skewed due to removing CRC */
785 total_rx_bytes += skb->len;
786 total_rx_packets++;
787
74ce8dd2 788 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 789#ifdef IXGBE_FCOE
790 /* if ddp, not passing to ULD unless for FCP_RSP or error */
791 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
792 if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb))
793 goto next_desc;
794#endif /* IXGBE_FCOE */
fdaff1ce 795 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 796
797next_desc:
798 rx_desc->wb.upper.status_error = 0;
799
800 /* return some buffers to hardware, one at a time is too slow */
801 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
802 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
803 cleaned_count = 0;
804 }
805
806 /* use prefetched values */
807 rx_desc = next_rxd;
f8212f97 808 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 809
810 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 811 }
812
9a799d71
AK		 813 rx_ring->next_to_clean = i;
814 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
815
816 if (cleaned_count)
817 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
818
f494e8fa
AV		 819 rx_ring->total_packets += total_rx_packets;
820 rx_ring->total_bytes += total_rx_bytes;
821 adapter->net_stats.rx_bytes += total_rx_bytes;
822 adapter->net_stats.rx_packets += total_rx_packets;
823
9a799d71
AK		 824 return cleaned;
825}
826
021230d4 827static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 828/**
829 * ixgbe_configure_msix - Configure MSI-X hardware
830 * @adapter: board private structure
831 *
832 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
833 * interrupts.
834 **/
835static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
836{
021230d4
AV		 837 struct ixgbe_q_vector *q_vector;
838 int i, j, q_vectors, v_idx, r_idx;
839 u32 mask;
9a799d71 840
021230d4 841 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 842
4df10466
JB		 843 /*
844 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 845 * corresponding register.
846 */
847 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 848 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 849 /* XXX for_each_bit(...) */
850 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 851 adapter->num_rx_queues);
021230d4
AV		 852
853 for (i = 0; i < q_vector->rxr_count; i++) {
854 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 855 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 856 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 857 adapter->num_rx_queues,
858 r_idx + 1);
021230d4
AV		 859 }
860 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 861 adapter->num_tx_queues);
021230d4
AV		 862
863 for (i = 0; i < q_vector->txr_count; i++) {
864 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 865 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 866 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 867 adapter->num_tx_queues,
868 r_idx + 1);
021230d4
AV		 869 }
870
30efa5a3 871 /* if this is a tx only vector halve the interrupt rate */
021230d4 872 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 873 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 874 else if (q_vector->rxr_count)
30efa5a3
JB		 875 /* rx only */
876 q_vector->eitr = adapter->eitr_param;
021230d4 877
509ee935 878 /*
4df10466 879 * since this is initial set up don't need to call
509ee935
JB		 880 * ixgbe_write_eitr helper
881 */
021230d4 882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 883 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 884 }
885
e8e26350
PW		 886 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
887 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
888 v_idx);
889 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
890 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 891 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
892
41fb9248 893 /* set up to autoclear timer, and the vectors */
021230d4 894 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 895 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 897}
898
f494e8fa
AV		 899enum latency_range {
900 lowest_latency = 0,
901 low_latency = 1,
902 bulk_latency = 2,
903 latency_invalid = 255
904};
905
906/**
907 * ixgbe_update_itr - update the dynamic ITR value based on statistics
908 * @adapter: pointer to adapter
909 * @eitr: eitr setting (ints per sec) to give last timeslice
910 * @itr_setting: current throttle rate in ints/second
911 * @packets: the number of packets during this measurement interval
912 * @bytes: the number of bytes during this measurement interval
913 *
914 * Stores a new ITR value based on packets and byte
915 * counts during the last interrupt. The advantage of per interrupt
916 * computation is faster updates and more accurate ITR for the current
917 * traffic pattern. Constants in this function were computed
918 * based on theoretical maximum wire speed and thresholds were set based
919 * on testing data as well as attempting to minimize response time
920 * while increasing bulk throughput.
921 * this functionality is controlled by the InterruptThrottleRate module
922 * parameter (see ixgbe_param.c)
923 **/
924static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 925 u32 eitr, u8 itr_setting,
926 int packets, int bytes)
f494e8fa
AV		 927{
928 unsigned int retval = itr_setting;
929 u32 timepassed_us;
930 u64 bytes_perint;
931
932 if (packets == 0)
933 goto update_itr_done;
934
935
936 /* simple throttlerate management
937 * 0-20MB/s lowest (100000 ints/s)
938 * 20-100MB/s low (20000 ints/s)
939 * 100-1249MB/s bulk (8000 ints/s)
940 */
941 /* what was last interrupt timeslice? */
942 timepassed_us = 1000000/eitr;
943 bytes_perint = bytes / timepassed_us; /* bytes/usec */
944
945 switch (itr_setting) {
946 case lowest_latency:
947 if (bytes_perint > adapter->eitr_low)
948 retval = low_latency;
949 break;
950 case low_latency:
951 if (bytes_perint > adapter->eitr_high)
952 retval = bulk_latency;
953 else if (bytes_perint <= adapter->eitr_low)
954 retval = lowest_latency;
955 break;
956 case bulk_latency:
957 if (bytes_perint <= adapter->eitr_high)
958 retval = low_latency;
959 break;
960 }
961
962update_itr_done:
963 return retval;
964}
965
509ee935
JB		 966/**
967 * ixgbe_write_eitr - write EITR register in hardware specific way
968 * @adapter: pointer to adapter struct
969 * @v_idx: vector index into q_vector array
970 * @itr_reg: new value to be written in *register* format, not ints/s
971 *
972 * This function is made to be called by ethtool and by the driver
973 * when it needs to update EITR registers at runtime. Hardware
974 * specific quirks/differences are taken care of here.
975 */
976void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
977{
978 struct ixgbe_hw *hw = &adapter->hw;
979 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
980 /* must write high and low 16 bits to reset counter */
981 itr_reg |= (itr_reg << 16);
982 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
983 /*
984 * set the WDIS bit to not clear the timer bits and cause an
985 * immediate assertion of the interrupt
986 */
987 itr_reg |= IXGBE_EITR_CNT_WDIS;
988 }
989 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
990}
991
f494e8fa
AV		 992static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
993{
994 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 995 u32 new_itr;
996 u8 current_itr, ret_itr;
7a921c93 997 int i, r_idx, v_idx = q_vector->v_idx;
f494e8fa
AV		 998 struct ixgbe_ring *rx_ring, *tx_ring;
999
1000 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1001 for (i = 0; i < q_vector->txr_count; i++) {
1002 tx_ring = &(adapter->tx_ring[r_idx]);
1003 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1004 q_vector->tx_itr,
1005 tx_ring->total_packets,
1006 tx_ring->total_bytes);
f494e8fa
AV		 1007 /* if the result for this queue would decrease interrupt
1008 * rate for this vector then use that result */
30efa5a3 1009 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1010 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1011 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1012 r_idx + 1);
f494e8fa
AV		 1013 }
1014
1015 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1016 for (i = 0; i < q_vector->rxr_count; i++) {
1017 rx_ring = &(adapter->rx_ring[r_idx]);
1018 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1019 q_vector->rx_itr,
1020 rx_ring->total_packets,
1021 rx_ring->total_bytes);
f494e8fa
AV		 1022 /* if the result for this queue would decrease interrupt
1023 * rate for this vector then use that result */
30efa5a3 1024 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1025 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1026 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1027 r_idx + 1);
f494e8fa
AV		 1028 }
1029
30efa5a3 1030 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1031
1032 switch (current_itr) {
1033 /* counts and packets in update_itr are dependent on these numbers */
1034 case lowest_latency:
1035 new_itr = 100000;
1036 break;
1037 case low_latency:
1038 new_itr = 20000; /* aka hwitr = ~200 */
1039 break;
1040 case bulk_latency:
1041 default:
1042 new_itr = 8000;
1043 break;
1044 }
1045
1046 if (new_itr != q_vector->eitr) {
1047 u32 itr_reg;
509ee935
JB		 1048
1049 /* save the algorithm value here, not the smoothed one */
1050 q_vector->eitr = new_itr;
f494e8fa
AV		 1051 /* do an exponential smoothing */
1052 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1053 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1054 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 1055 }
1056
1057 return;
1058}
1059
0befdb3e
JB		 1060static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1061{
1062 struct ixgbe_hw *hw = &adapter->hw;
1063
1064 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1065 (eicr & IXGBE_EICR_GPI_SDP1)) {
1066 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1067 /* write to clear the interrupt */
1068 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1069 }
1070}
cf8280ee 1071
e8e26350
PW		 1072static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1073{
1074 struct ixgbe_hw *hw = &adapter->hw;
1075
1076 if (eicr & IXGBE_EICR_GPI_SDP1) {
1077 /* Clear the interrupt */
1078 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1079 schedule_work(&adapter->multispeed_fiber_task);
1080 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1081 /* Clear the interrupt */
1082 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1083 schedule_work(&adapter->sfp_config_module_task);
1084 } else {
1085 /* Interrupt isn't for us... */
1086 return;
1087 }
1088}
1089
cf8280ee
JB		 1090static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1091{
1092 struct ixgbe_hw *hw = &adapter->hw;
1093
1094 adapter->lsc_int++;
1095 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1096 adapter->link_check_timeout = jiffies;
1097 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1098 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1099 schedule_work(&adapter->watchdog_task);
1100 }
1101}
1102
9a799d71
AK		 1103static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1104{
1105 struct net_device *netdev = data;
1106 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1107 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1108 u32 eicr;
1109
1110 /*
1111 * Workaround for Silicon errata. Use clear-by-write instead
1112 * of clear-by-read. Reading with EICS will return the
1113 * interrupt causes without clearing, which later be done
1114 * with the write to EICR.
1115 */
1116 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1117 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1118
cf8280ee
JB		 1119 if (eicr & IXGBE_EICR_LSC)
1120 ixgbe_check_lsc(adapter);
d4f80882 1121
e8e26350
PW		 1122 if (hw->mac.type == ixgbe_mac_82598EB)
1123 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1124
e8e26350
PW		 1125 if (hw->mac.type == ixgbe_mac_82599EB)
1126 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1127 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1128 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1129
1130 return IRQ_HANDLED;
1131}
1132
1133static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1134{
021230d4
AV		 1135 struct ixgbe_q_vector *q_vector = data;
1136 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1137 struct ixgbe_ring *tx_ring;
021230d4
AV		 1138 int i, r_idx;
1139
1140 if (!q_vector->txr_count)
1141 return IRQ_HANDLED;
1142
1143 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1144 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1145 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1146#ifdef CONFIG_IXGBE_DCA
bd0362dd 1147 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1148 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1149#endif
3a581073
JB		 1150 tx_ring->total_bytes = 0;
1151 tx_ring->total_packets = 0;
1152 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1153 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1154 r_idx + 1);
021230d4 1155 }
9a799d71 1156
9a799d71
AK		 1157 return IRQ_HANDLED;
1158}
1159
021230d4
AV		 1160/**
1161 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1162 * @irq: unused
1163 * @data: pointer to our q_vector struct for this interrupt vector
1164 **/
9a799d71
AK		 1165static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1166{
021230d4
AV		 1167 struct ixgbe_q_vector *q_vector = data;
1168 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1169 struct ixgbe_ring *rx_ring;
021230d4 1170 int r_idx;
30efa5a3 1171 int i;
021230d4
AV		 1172
1173 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1174 for (i = 0; i < q_vector->rxr_count; i++) {
1175 rx_ring = &(adapter->rx_ring[r_idx]);
1176 rx_ring->total_bytes = 0;
1177 rx_ring->total_packets = 0;
1178 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1179 r_idx + 1);
1180 }
1181
021230d4
AV		 1182 if (!q_vector->rxr_count)
1183 return IRQ_HANDLED;
1184
30efa5a3 1185 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1186 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1187 /* disable interrupts on this vector only */
835462fc
NS		 1188 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1189 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1190 else if (rx_ring->v_idx & 0xFFFFFFFF)
1191 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1192 else
1193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1194 (rx_ring->v_idx >> 32));
288379f0 1195 napi_schedule(&q_vector->napi);
021230d4
AV		 1196
1197 return IRQ_HANDLED;
1198}
1199
1200static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1201{
1202 ixgbe_msix_clean_rx(irq, data);
1203 ixgbe_msix_clean_tx(irq, data);
9a799d71 1204
9a799d71
AK		 1205 return IRQ_HANDLED;
1206}
1207
835462fc
NS		 1208static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1209 u64 qmask)
1210{
1211 u32 mask;
1212
1213 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1214 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1216 } else {
1217 mask = (qmask & 0xFFFFFFFF);
1218 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1219 mask = (qmask >> 32);
1220 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1221 }
1222 /* skip the flush */
1223}
1224
021230d4
AV		 1225/**
1226 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1227 * @napi: napi struct with our devices info in it
1228 * @budget: amount of work driver is allowed to do this pass, in packets
1229 *
f0848276
JB		 1230 * This function is optimized for cleaning one queue only on a single
1231 * q_vector!!!
021230d4 1232 **/
9a799d71
AK		 1233static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1234{
021230d4 1235 struct ixgbe_q_vector *q_vector =
b4617240 1236 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1237 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1238 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1239 int work_done = 0;
021230d4 1240 long r_idx;
9a799d71 1241
021230d4 1242 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1243 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1244#ifdef CONFIG_IXGBE_DCA
bd0362dd 1245 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1246 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1247#endif
9a799d71 1248
78b6f4ce 1249 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1250
021230d4
AV		 1251 /* If all Rx work done, exit the polling mode */
1252 if (work_done < budget) {
288379f0 1253 napi_complete(napi);
509ee935 1254 if (adapter->itr_setting & 1)
f494e8fa 1255 ixgbe_set_itr_msix(q_vector);
9a799d71 1256 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1257 ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
9a799d71
AK		 1258 }
1259
1260 return work_done;
1261}
1262
f0848276
JB		 1263/**
1264 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1265 * @napi: napi struct with our devices info in it
1266 * @budget: amount of work driver is allowed to do this pass, in packets
1267 *
1268 * This function will clean more than one rx queue associated with a
1269 * q_vector.
1270 **/
1271static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1272{
1273 struct ixgbe_q_vector *q_vector =
1274 container_of(napi, struct ixgbe_q_vector, napi);
1275 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1276 struct ixgbe_ring *rx_ring = NULL;
1277 int work_done = 0, i;
1278 long r_idx;
835462fc 1279 u64 enable_mask = 0;
f0848276
JB		 1280
1281 /* attempt to distribute budget to each queue fairly, but don't allow
1282 * the budget to go below 1 because we'll exit polling */
1283 budget /= (q_vector->rxr_count ?: 1);
1284 budget = max(budget, 1);
1285 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1286 for (i = 0; i < q_vector->rxr_count; i++) {
1287 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1288#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1289 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1290 ixgbe_update_rx_dca(adapter, rx_ring);
1291#endif
78b6f4ce 1292 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1293 enable_mask |= rx_ring->v_idx;
1294 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1295 r_idx + 1);
1296 }
1297
1298 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1299 rx_ring = &(adapter->rx_ring[r_idx]);
1300 /* If all Rx work done, exit the polling mode */
7f821875 1301 if (work_done < budget) {
288379f0 1302 napi_complete(napi);
509ee935 1303 if (adapter->itr_setting & 1)
f0848276
JB		 1304 ixgbe_set_itr_msix(q_vector);
1305 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1306 ixgbe_irq_enable_queues(adapter, enable_mask);
f0848276
JB		 1307 return 0;
1308 }
1309
1310 return work_done;
1311}
021230d4 1312static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1313 int r_idx)
021230d4 1314{
7a921c93
AD		 1315 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1316
1317 set_bit(r_idx, q_vector->rxr_idx);
1318 q_vector->rxr_count++;
c9c7d2e5 1319 a->rx_ring[r_idx].v_idx = (u64)1 << v_idx;
021230d4
AV		 1320}
1321
1322static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1323 int t_idx)
021230d4 1324{
7a921c93
AD		 1325 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1326
1327 set_bit(t_idx, q_vector->txr_idx);
1328 q_vector->txr_count++;
c9c7d2e5 1329 a->tx_ring[t_idx].v_idx = (u64)1 << v_idx;
021230d4
AV		 1330}
1331
9a799d71 1332/**
021230d4
AV		 1333 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1334 * @adapter: board private structure to initialize
1335 * @vectors: allotted vector count for descriptor rings
9a799d71 1336 *
021230d4
AV		 1337 * This function maps descriptor rings to the queue-specific vectors
1338 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1339 * one vector per ring/queue, but on a constrained vector budget, we
1340 * group the rings as "efficiently" as possible. You would add new
1341 * mapping configurations in here.
9a799d71 1342 **/
021230d4 1343static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1344 int vectors)
021230d4
AV		 1345{
1346 int v_start = 0;
1347 int rxr_idx = 0, txr_idx = 0;
1348 int rxr_remaining = adapter->num_rx_queues;
1349 int txr_remaining = adapter->num_tx_queues;
1350 int i, j;
1351 int rqpv, tqpv;
1352 int err = 0;
1353
1354 /* No mapping required if MSI-X is disabled. */
1355 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1356 goto out;
9a799d71 1357
021230d4
AV		 1358 /*
1359 * The ideal configuration...
1360 * We have enough vectors to map one per queue.
1361 */
1362 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1363 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1364 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1365
021230d4
AV		 1366 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1367 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1368
9a799d71 1369 goto out;
021230d4 1370 }
9a799d71 1371
021230d4
AV		 1372 /*
1373 * If we don't have enough vectors for a 1-to-1
1374 * mapping, we'll have to group them so there are
1375 * multiple queues per vector.
1376 */
1377 /* Re-adjusting *qpv takes care of the remainder. */
1378 for (i = v_start; i < vectors; i++) {
1379 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1380 for (j = 0; j < rqpv; j++) {
1381 map_vector_to_rxq(adapter, i, rxr_idx);
1382 rxr_idx++;
1383 rxr_remaining--;
1384 }
1385 }
1386 for (i = v_start; i < vectors; i++) {
1387 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1388 for (j = 0; j < tqpv; j++) {
1389 map_vector_to_txq(adapter, i, txr_idx);
1390 txr_idx++;
1391 txr_remaining--;
9a799d71 1392 }
9a799d71
AK		 1393 }
1394
021230d4
AV		 1395out:
1396 return err;
1397}
1398
1399/**
1400 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1401 * @adapter: board private structure
1402 *
1403 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1404 * interrupts from the kernel.
1405 **/
1406static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1407{
1408 struct net_device *netdev = adapter->netdev;
1409 irqreturn_t (*handler)(int, void *);
1410 int i, vector, q_vectors, err;
cb13fc20 1411 int ri=0, ti=0;
021230d4
AV		 1412
1413 /* Decrement for Other and TCP Timer vectors */
1414 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1415
1416 /* Map the Tx/Rx rings to the vectors we were allotted. */
1417 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1418 if (err)
1419 goto out;
1420
1421#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1422 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1423 &ixgbe_msix_clean_many)
021230d4 1424 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1425 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1426
1427 if(handler == &ixgbe_msix_clean_rx) {
1428 sprintf(adapter->name[vector], "%s-%s-%d",
1429 netdev->name, "rx", ri++);
1430 }
1431 else if(handler == &ixgbe_msix_clean_tx) {
1432 sprintf(adapter->name[vector], "%s-%s-%d",
1433 netdev->name, "tx", ti++);
1434 }
1435 else
1436 sprintf(adapter->name[vector], "%s-%s-%d",
1437 netdev->name, "TxRx", vector);
1438
021230d4 1439 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1440 handler, 0, adapter->name[vector],
7a921c93 1441 adapter->q_vector[vector]);
9a799d71
AK		 1442 if (err) {
1443 DPRINTK(PROBE, ERR,
b4617240
PW		 1444 "request_irq failed for MSIX interrupt "
1445 "Error: %d\n", err);
021230d4 1446 goto free_queue_irqs;
9a799d71 1447 }
9a799d71
AK		 1448 }
1449
021230d4
AV		 1450 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1451 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1452 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1453 if (err) {
1454 DPRINTK(PROBE, ERR,
1455 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1456 goto free_queue_irqs;
9a799d71
AK		 1457 }
1458
9a799d71
AK		 1459 return 0;
1460
021230d4
AV		 1461free_queue_irqs:
1462 for (i = vector - 1; i >= 0; i--)
1463 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1464 adapter->q_vector[i]);
021230d4
AV		 1465 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1466 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1467 kfree(adapter->msix_entries);
1468 adapter->msix_entries = NULL;
021230d4 1469out:
9a799d71
AK		 1470 return err;
1471}
1472
f494e8fa
AV		 1473static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1474{
7a921c93 1475 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1476 u8 current_itr;
1477 u32 new_itr = q_vector->eitr;
1478 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1479 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1480
30efa5a3 1481 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1482 q_vector->tx_itr,
1483 tx_ring->total_packets,
1484 tx_ring->total_bytes);
30efa5a3 1485 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1486 q_vector->rx_itr,
1487 rx_ring->total_packets,
1488 rx_ring->total_bytes);
f494e8fa 1489
30efa5a3 1490 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1491
1492 switch (current_itr) {
1493 /* counts and packets in update_itr are dependent on these numbers */
1494 case lowest_latency:
1495 new_itr = 100000;
1496 break;
1497 case low_latency:
1498 new_itr = 20000; /* aka hwitr = ~200 */
1499 break;
1500 case bulk_latency:
1501 new_itr = 8000;
1502 break;
1503 default:
1504 break;
1505 }
1506
1507 if (new_itr != q_vector->eitr) {
1508 u32 itr_reg;
509ee935
JB		 1509
1510 /* save the algorithm value here, not the smoothed one */
1511 q_vector->eitr = new_itr;
f494e8fa
AV		 1512 /* do an exponential smoothing */
1513 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1514 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1515 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1516 }
1517
1518 return;
1519}
1520
79aefa45
AD		 1521/**
1522 * ixgbe_irq_enable - Enable default interrupt generation settings
1523 * @adapter: board private structure
1524 **/
1525static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1526{
1527 u32 mask;
835462fc
NS		 1528
1529 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1530 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1531 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1532 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1533 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1534 mask |= IXGBE_EIMS_GPI_SDP1;
1535 mask |= IXGBE_EIMS_GPI_SDP2;
1536 }
1537
79aefa45 1538 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1539 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1540 IXGBE_WRITE_FLUSH(&adapter->hw);
1541}
021230d4 1542
9a799d71 1543/**
021230d4 1544 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1545 * @irq: interrupt number
1546 * @data: pointer to a network interface device structure
9a799d71
AK		 1547 **/
1548static irqreturn_t ixgbe_intr(int irq, void *data)
1549{
1550 struct net_device *netdev = data;
1551 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1552 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1553 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1554 u32 eicr;
1555
54037505
DS		 1556 /*
1557 * Workaround for silicon errata. Mask the interrupts
1558 * before the read of EICR.
1559 */
1560 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1561
021230d4
AV		 1562 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1563 * therefore no explict interrupt disable is necessary */
1564 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1565 if (!eicr) {
1566 /* shared interrupt alert!
1567 * make sure interrupts are enabled because the read will
1568 * have disabled interrupts due to EIAM */
1569 ixgbe_irq_enable(adapter);
9a799d71 1570 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1571 }
9a799d71 1572
cf8280ee
JB		 1573 if (eicr & IXGBE_EICR_LSC)
1574 ixgbe_check_lsc(adapter);
021230d4 1575
e8e26350
PW		 1576 if (hw->mac.type == ixgbe_mac_82599EB)
1577 ixgbe_check_sfp_event(adapter, eicr);
1578
0befdb3e
JB		 1579 ixgbe_check_fan_failure(adapter, eicr);
1580
7a921c93 1581 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1582 adapter->tx_ring[0].total_packets = 0;
1583 adapter->tx_ring[0].total_bytes = 0;
1584 adapter->rx_ring[0].total_packets = 0;
1585 adapter->rx_ring[0].total_bytes = 0;
021230d4 1586 /* would disable interrupts here but EIAM disabled it */
7a921c93 1587 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1588 }
1589
1590 return IRQ_HANDLED;
1591}
1592
021230d4
AV		 1593static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1594{
1595 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1596
1597 for (i = 0; i < q_vectors; i++) {
7a921c93 1598 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1599 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1600 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1601 q_vector->rxr_count = 0;
1602 q_vector->txr_count = 0;
1603 }
1604}
1605
9a799d71
AK		 1606/**
1607 * ixgbe_request_irq - initialize interrupts
1608 * @adapter: board private structure
1609 *
1610 * Attempts to configure interrupts using the best available
1611 * capabilities of the hardware and kernel.
1612 **/
021230d4 1613static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1614{
1615 struct net_device *netdev = adapter->netdev;
021230d4 1616 int err;
9a799d71 1617
021230d4
AV		 1618 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1619 err = ixgbe_request_msix_irqs(adapter);
1620 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1621 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1622 netdev->name, netdev);
021230d4
AV		 1623 } else {
1624 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1625 netdev->name, netdev);
9a799d71
AK		 1626 }
1627
9a799d71
AK		 1628 if (err)
1629 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1630
9a799d71
AK		 1631 return err;
1632}
1633
1634static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1635{
1636 struct net_device *netdev = adapter->netdev;
1637
1638 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1639 int i, q_vectors;
9a799d71 1640
021230d4
AV		 1641 q_vectors = adapter->num_msix_vectors;
1642
1643 i = q_vectors - 1;
9a799d71 1644 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1645
021230d4
AV		 1646 i--;
1647 for (; i >= 0; i--) {
1648 free_irq(adapter->msix_entries[i].vector,
7a921c93 1649 adapter->q_vector[i]);
021230d4
AV		 1650 }
1651
1652 ixgbe_reset_q_vectors(adapter);
1653 } else {
1654 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1655 }
1656}
1657
22d5a71b
JB		 1658/**
1659 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1660 * @adapter: board private structure
1661 **/
1662static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1663{
835462fc
NS		 1664 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1665 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1666 } else {
1667 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1668 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1669 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1670 }
1671 IXGBE_WRITE_FLUSH(&adapter->hw);
1672 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1673 int i;
1674 for (i = 0; i < adapter->num_msix_vectors; i++)
1675 synchronize_irq(adapter->msix_entries[i].vector);
1676 } else {
1677 synchronize_irq(adapter->pdev->irq);
1678 }
1679}
1680
9a799d71
AK		 1681/**
1682 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1683 *
1684 **/
1685static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1686{
9a799d71
AK		 1687 struct ixgbe_hw *hw = &adapter->hw;
1688
021230d4 1689 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1690 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1691
e8e26350
PW		 1692 ixgbe_set_ivar(adapter, 0, 0, 0);
1693 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1694
1695 map_vector_to_rxq(adapter, 0, 0);
1696 map_vector_to_txq(adapter, 0, 0);
1697
1698 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1699}
1700
1701/**
3a581073 1702 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1703 * @adapter: board private structure
1704 *
1705 * Configure the Tx unit of the MAC after a reset.
1706 **/
1707static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1708{
12207e49 1709 u64 tdba;
9a799d71 1710 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1711 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1712
1713 /* Setup the HW Tx Head and Tail descriptor pointers */
1714 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1715 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1716 j = ring->reg_idx;
1717 tdba = ring->dma;
1718 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1719 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1720 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1721 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1722 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1723 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1724 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1725 adapter->tx_ring[i].head = IXGBE_TDH(j);
1726 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1727 /* Disable Tx Head Writeback RO bit, since this hoses
1728 * bookkeeping if things aren't delivered in order.
1729 */
e01c31a5 1730 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1731 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1732 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1733 }
e8e26350
PW		 1734 if (hw->mac.type == ixgbe_mac_82599EB) {
1735 /* We enable 8 traffic classes, DCB only */
1736 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1737 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1738 IXGBE_MTQC_8TC_8TQ));
1739 }
9a799d71
AK		 1740}
1741
e8e26350 1742#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1743
1744static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1745{
1746 struct ixgbe_ring *rx_ring;
1747 u32 srrctl;
e8e26350 1748 int queue0 = 0;
3be1adfb 1749 unsigned long mask;
0cefafad 1750 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 1751
e8e26350 1752 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
163de42e 1753 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
0cefafad 1754 int dcb_i = feature[RING_F_DCB].indices;
163de42e
AD		 1755 if (dcb_i == 8)
1756 queue0 = index >> 4;
1757 else if (dcb_i == 4)
1758 queue0 = index >> 5;
1759 else
1760 dev_err(&adapter->pdev->dev, "Invalid DCB "
1761 "configuration\n");
0331a832
YZ		 1762#ifdef IXGBE_FCOE
1763 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1764 struct ixgbe_ring_feature *f;
1765
1766 rx_ring = &adapter->rx_ring[queue0];
1767 f = &adapter->ring_feature[RING_F_FCOE];
1768 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1769 queue0 = f->mask + index -
1770 rx_ring->reg_idx - 1;
1771 }
1772#endif /* IXGBE_FCOE */
163de42e
AD		 1773 } else {
1774 queue0 = index;
1775 }
cc41ac7c 1776 } else {
0cefafad 1777 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb
AD		 1778 queue0 = index & mask;
1779 index = index & mask;
cc41ac7c 1780 }
3be1adfb 1781
cc41ac7c
JB		 1782 rx_ring = &adapter->rx_ring[queue0];
1783
1784 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1785
1786 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1787 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1788
afafd5b0
AD		 1789 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1790 IXGBE_SRRCTL_BSIZEHDR_MASK;
1791
cc41ac7c 1792 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
afafd5b0
AD		 1793#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1794 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1795#else
1796 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1797#endif
cc41ac7c 1798 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1799 } else {
afafd5b0
AD		 1800 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1801 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1802 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1803 }
e8e26350 1804
cc41ac7c
JB		 1805 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1806}
9a799d71 1807
0cefafad
JB		 1808static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1809{
1810 u32 mrqc = 0;
1811 int mask;
1812
1813 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1814 return mrqc;
1815
1816 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1817#ifdef CONFIG_IXGBE_DCB
1818 | IXGBE_FLAG_DCB_ENABLED
1819#endif
1820 );
1821
1822 switch (mask) {
1823 case (IXGBE_FLAG_RSS_ENABLED):
1824 mrqc = IXGBE_MRQC_RSSEN;
1825 break;
1826#ifdef CONFIG_IXGBE_DCB
1827 case (IXGBE_FLAG_DCB_ENABLED):
1828 mrqc = IXGBE_MRQC_RT8TCEN;
1829 break;
1830#endif /* CONFIG_IXGBE_DCB */
1831 default:
1832 break;
1833 }
1834
1835 return mrqc;
1836}
1837
9a799d71 1838/**
3a581073 1839 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1840 * @adapter: board private structure
1841 *
1842 * Configure the Rx unit of the MAC after a reset.
1843 **/
1844static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1845{
1846 u64 rdba;
1847 struct ixgbe_hw *hw = &adapter->hw;
1848 struct net_device *netdev = adapter->netdev;
1849 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1850 int i, j;
9a799d71 1851 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1852 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1853 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1854 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1855 u32 fctrl, hlreg0;
509ee935 1856 u32 reta = 0, mrqc = 0;
cc41ac7c 1857 u32 rdrxctl;
f8212f97 1858 u32 rscctrl;
7c6e0a43 1859 int rx_buf_len;
9a799d71
AK		 1860
1861 /* Decide whether to use packet split mode or not */
762f4c57 1862 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 1863
eacd73f7
YZ		 1864#ifdef IXGBE_FCOE
1865 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1866 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1867#endif /* IXGBE_FCOE */
1868
9a799d71
AK		 1869 /* Set the RX buffer length according to the mode */
1870 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1871 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1872 if (hw->mac.type == ixgbe_mac_82599EB) {
1873 /* PSRTYPE must be initialized in 82599 */
1874 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1875 IXGBE_PSRTYPE_UDPHDR |
1876 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 1877 IXGBE_PSRTYPE_IPV6HDR |
1878 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 1879 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1880 }
9a799d71 1881 } else {
f8212f97
AD		 1882 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1883 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 1884 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1885 else
7c6e0a43 1886 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1887 }
1888
1889 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1890 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1891 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1892 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1893 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1894
1895 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1896 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1897 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1898 else
1899 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1
YZ		 1900#ifdef IXGBE_FCOE
1901 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1902 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1903#endif
9a799d71
AK		 1904 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1905
9a799d71
AK		 1906 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1907 /* disable receives while setting up the descriptors */
1908 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1909 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1910
0cefafad
JB		 1911 /*
1912 * Setup the HW Rx Head and Tail Descriptor Pointers and
1913 * the Base and Length of the Rx Descriptor Ring
1914 */
9a799d71
AK		 1915 for (i = 0; i < adapter->num_rx_queues; i++) {
1916 rdba = adapter->rx_ring[i].dma;
7c6e0a43 1917 j = adapter->rx_ring[i].reg_idx;
284901a9 1918 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 1919 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1920 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1921 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1922 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1923 adapter->rx_ring[i].head = IXGBE_RDH(j);
1924 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1925 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c 1926
63f39bd1
YZ		 1927#ifdef IXGBE_FCOE
1928 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1929 struct ixgbe_ring_feature *f;
1930 f = &adapter->ring_feature[RING_F_FCOE];
1931 if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
1932 (i >= f->mask) && (i < f->mask + f->indices))
1933 adapter->rx_ring[i].rx_buf_len =
1934 IXGBE_FCOE_JUMBO_FRAME_SIZE;
1935 }
1936
1937#endif /* IXGBE_FCOE */
cc41ac7c 1938 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1939 }
1940
e8e26350
PW		 1941 if (hw->mac.type == ixgbe_mac_82598EB) {
1942 /*
1943 * For VMDq support of different descriptor types or
1944 * buffer sizes through the use of multiple SRRCTL
1945 * registers, RDRXCTL.MVMEN must be set to 1
1946 *
1947 * also, the manual doesn't mention it clearly but DCA hints
1948 * will only use queue 0's tags unless this bit is set. Side
1949 * effects of setting this bit are only that SRRCTL must be
1950 * fully programmed [0..15]
1951 */
2a41ff81
JB		 1952 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1953 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1954 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 1955 }
177db6ff 1956
e8e26350 1957 /* Program MRQC for the distribution of queues */
0cefafad 1958 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 1959
021230d4 1960 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1961 /* Fill out redirection table */
021230d4
AV		 1962 for (i = 0, j = 0; i < 128; i++, j++) {
1963 if (j == adapter->ring_feature[RING_F_RSS].indices)
1964 j = 0;
1965 /* reta = 4-byte sliding window of
1966 * 0x00..(indices-1)(indices-1)00..etc. */
1967 reta = (reta << 8) | (j * 0x11);
1968 if ((i & 3) == 3)
1969 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1970 }
1971
1972 /* Fill out hash function seeds */
1973 for (i = 0; i < 10; i++)
7c6e0a43 1974 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 1975
2a41ff81
JB		 1976 if (hw->mac.type == ixgbe_mac_82598EB)
1977 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 1978 /* Perform hash on these packet types */
2a41ff81
JB		 1979 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1980 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1981 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1982 | IXGBE_MRQC_RSS_FIELD_IPV6
1983 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1984 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 1985 }
2a41ff81 1986 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 1987
021230d4
AV		 1988 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1989
1990 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1991 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1992 /* Disable indicating checksum in descriptor, enables
1993 * RSS hash */
9a799d71 1994 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1995 }
021230d4
AV		 1996 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1997 /* Enable IPv4 payload checksum for UDP fragments
1998 * if PCSD is not set */
1999 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2000 }
2001
2002 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2003
2004 if (hw->mac.type == ixgbe_mac_82599EB) {
2005 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2006 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2007 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2008 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2009 }
f8212f97
AD		 2010
2011 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
2012 /* Enable 82599 HW-RSC */
2013 for (i = 0; i < adapter->num_rx_queues; i++) {
2014 j = adapter->rx_ring[i].reg_idx;
2015 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2016 rscctrl |= IXGBE_RSCCTL_RSCEN;
2017 /*
e76678dd
AD		 2018 * we must limit the number of descriptors so that the
2019 * total size of max desc * buf_len is not greater
2020 * than 65535
f8212f97 2021 */
e76678dd
AD		 2022 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2023#if (MAX_SKB_FRAGS > 16)
2024 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2025#elif (MAX_SKB_FRAGS > 8)
f8212f97 2026 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
e76678dd
AD		 2027#elif (MAX_SKB_FRAGS > 4)
2028 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
f8212f97 2029#else
e76678dd 2030 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
f8212f97 2031#endif
e76678dd
AD		 2032 } else {
2033 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2034 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2035 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2036 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2037 else
2038 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2039 }
f8212f97
AD		 2040 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2041 }
2042 /* Disable RSC for ACK packets */
2043 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2044 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2045 }
9a799d71
AK		 2046}
2047
068c89b0
DS		 2048static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2049{
2050 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2051 struct ixgbe_hw *hw = &adapter->hw;
2052
2053 /* add VID to filter table */
2054 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2055}
2056
2057static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2058{
2059 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2060 struct ixgbe_hw *hw = &adapter->hw;
2061
2062 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2063 ixgbe_irq_disable(adapter);
2064
2065 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2066
2067 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2068 ixgbe_irq_enable(adapter);
2069
2070 /* remove VID from filter table */
2071 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2072}
2073
9a799d71 2074static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2075 struct vlan_group *grp)
9a799d71
AK		 2076{
2077 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2078 u32 ctrl;
e8e26350 2079 int i, j;
9a799d71 2080
d4f80882
AV		 2081 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2082 ixgbe_irq_disable(adapter);
9a799d71
AK		 2083 adapter->vlgrp = grp;
2084
2f90b865
AD		 2085 /*
2086 * For a DCB driver, always enable VLAN tag stripping so we can
2087 * still receive traffic from a DCB-enabled host even if we're
2088 * not in DCB mode.
2089 */
2090 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2091 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2092 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2093 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2094 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2095 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2096 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2097 /* enable VLAN tag insert/strip */
2098 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2099 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2100 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2101 for (i = 0; i < adapter->num_rx_queues; i++) {
2102 j = adapter->rx_ring[i].reg_idx;
2103 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2104 ctrl |= IXGBE_RXDCTL_VME;
2105 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2106 }
9a799d71 2107 }
e8e26350 2108 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2109
d4f80882
AV		 2110 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2111 ixgbe_irq_enable(adapter);
9a799d71
AK		 2112}
2113
9a799d71
AK		 2114static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2115{
2116 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2117
2118 if (adapter->vlgrp) {
2119 u16 vid;
2120 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2121 if (!vlan_group_get_device(adapter->vlgrp, vid))
2122 continue;
2123 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2124 }
2125 }
2126}
2127
2c5645cf
CL		 2128static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2129{
2130 struct dev_mc_list *mc_ptr;
2131 u8 *addr = *mc_addr_ptr;
2132 *vmdq = 0;
2133
2134 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2135 if (mc_ptr->next)
2136 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2137 else
2138 *mc_addr_ptr = NULL;
2139
2140 return addr;
2141}
2142
9a799d71 2143/**
2c5645cf 2144 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2145 * @netdev: network interface device structure
2146 *
2c5645cf
CL		 2147 * The set_rx_method entry point is called whenever the unicast/multicast
2148 * address list or the network interface flags are updated. This routine is
2149 * responsible for configuring the hardware for proper unicast, multicast and
2150 * promiscuous mode.
9a799d71 2151 **/
2c5645cf 2152static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2153{
2154 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2155 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2156 u32 fctrl, vlnctrl;
2c5645cf
CL		 2157 u8 *addr_list = NULL;
2158 int addr_count = 0;
9a799d71
AK		 2159
2160 /* Check for Promiscuous and All Multicast modes */
2161
2162 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2163 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2164
2165 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2166 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2167 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2168 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2169 } else {
746b9f02
PM		 2170 if (netdev->flags & IFF_ALLMULTI) {
2171 fctrl |= IXGBE_FCTRL_MPE;
2172 fctrl &= ~IXGBE_FCTRL_UPE;
2173 } else {
2174 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2175 }
3d01625a 2176 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2177 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2178 }
2179
2180 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2181 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2182
2c5645cf
CL		 2183 /* reprogram secondary unicast list */
2184 addr_count = netdev->uc_count;
2185 if (addr_count)
2186 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2187 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2188 ixgbe_addr_list_itr);
9a799d71 2189
2c5645cf
CL		 2190 /* reprogram multicast list */
2191 addr_count = netdev->mc_count;
2192 if (addr_count)
2193 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2194 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2195 ixgbe_addr_list_itr);
9a799d71
AK		 2196}
2197
021230d4
AV		 2198static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2199{
2200 int q_idx;
2201 struct ixgbe_q_vector *q_vector;
2202 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2203
2204 /* legacy and MSI only use one vector */
2205 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2206 q_vectors = 1;
2207
2208 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2209 struct napi_struct *napi;
7a921c93 2210 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2211 if (!q_vector->rxr_count)
2212 continue;
f0848276
JB		 2213 napi = &q_vector->napi;
2214 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2215 (q_vector->rxr_count > 1))
2216 napi->poll = &ixgbe_clean_rxonly_many;
2217
2218 napi_enable(napi);
021230d4
AV		 2219 }
2220}
2221
2222static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2223{
2224 int q_idx;
2225 struct ixgbe_q_vector *q_vector;
2226 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2227
2228 /* legacy and MSI only use one vector */
2229 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2230 q_vectors = 1;
2231
2232 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2233 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2234 if (!q_vector->rxr_count)
2235 continue;
2236 napi_disable(&q_vector->napi);
2237 }
2238}
2239
7a6b6f51 2240#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2241/*
2242 * ixgbe_configure_dcb - Configure DCB hardware
2243 * @adapter: ixgbe adapter struct
2244 *
2245 * This is called by the driver on open to configure the DCB hardware.
2246 * This is also called by the gennetlink interface when reconfiguring
2247 * the DCB state.
2248 */
2249static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2250{
2251 struct ixgbe_hw *hw = &adapter->hw;
2252 u32 txdctl, vlnctrl;
2253 int i, j;
2254
2255 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2256 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2257 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2258
2259 /* reconfigure the hardware */
2260 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2261
2262 for (i = 0; i < adapter->num_tx_queues; i++) {
2263 j = adapter->tx_ring[i].reg_idx;
2264 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2265 /* PThresh workaround for Tx hang with DFP enabled. */
2266 txdctl |= 32;
2267 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2268 }
2269 /* Enable VLAN tag insert/strip */
2270 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2271 if (hw->mac.type == ixgbe_mac_82598EB) {
2272 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2273 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2274 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2275 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2276 vlnctrl |= IXGBE_VLNCTRL_VFE;
2277 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2278 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2279 for (i = 0; i < adapter->num_rx_queues; i++) {
2280 j = adapter->rx_ring[i].reg_idx;
2281 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2282 vlnctrl |= IXGBE_RXDCTL_VME;
2283 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2284 }
2285 }
2f90b865
AD		 2286 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2287}
2288
2289#endif
9a799d71
AK		 2290static void ixgbe_configure(struct ixgbe_adapter *adapter)
2291{
2292 struct net_device *netdev = adapter->netdev;
2293 int i;
2294
2c5645cf 2295 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2296
2297 ixgbe_restore_vlan(adapter);
7a6b6f51 2298#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2299 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2300 netif_set_gso_max_size(netdev, 32768);
2301 ixgbe_configure_dcb(adapter);
2302 } else {
2303 netif_set_gso_max_size(netdev, 65536);
2304 }
2305#else
2306 netif_set_gso_max_size(netdev, 65536);
2307#endif
9a799d71 2308
eacd73f7
YZ		 2309#ifdef IXGBE_FCOE
2310 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2311 ixgbe_configure_fcoe(adapter);
2312
2313#endif /* IXGBE_FCOE */
9a799d71
AK		 2314 ixgbe_configure_tx(adapter);
2315 ixgbe_configure_rx(adapter);
2316 for (i = 0; i < adapter->num_rx_queues; i++)
2317 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2318 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2319}
2320
e8e26350
PW		 2321static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2322{
2323 switch (hw->phy.type) {
2324 case ixgbe_phy_sfp_avago:
2325 case ixgbe_phy_sfp_ftl:
2326 case ixgbe_phy_sfp_intel:
2327 case ixgbe_phy_sfp_unknown:
2328 case ixgbe_phy_tw_tyco:
2329 case ixgbe_phy_tw_unknown:
2330 return true;
2331 default:
2332 return false;
2333 }
2334}
2335
0ecc061d 2336/**
e8e26350
PW		 2337 * ixgbe_sfp_link_config - set up SFP+ link
2338 * @adapter: pointer to private adapter struct
2339 **/
2340static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2341{
2342 struct ixgbe_hw *hw = &adapter->hw;
2343
2344 if (hw->phy.multispeed_fiber) {
2345 /*
2346 * In multispeed fiber setups, the device may not have
2347 * had a physical connection when the driver loaded.
2348 * If that's the case, the initial link configuration
2349 * couldn't get the MAC into 10G or 1G mode, so we'll
2350 * never have a link status change interrupt fire.
2351 * We need to try and force an autonegotiation
2352 * session, then bring up link.
2353 */
2354 hw->mac.ops.setup_sfp(hw);
2355 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2356 schedule_work(&adapter->multispeed_fiber_task);
2357 } else {
2358 /*
2359 * Direct Attach Cu and non-multispeed fiber modules
2360 * still need to be configured properly prior to
2361 * attempting link.
2362 */
2363 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2364 schedule_work(&adapter->sfp_config_module_task);
2365 }
2366}
2367
2368/**
2369 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2370 * @hw: pointer to private hardware struct
2371 *
2372 * Returns 0 on success, negative on failure
2373 **/
e8e26350 2374static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2375{
2376 u32 autoneg;
2377 bool link_up = false;
2378 u32 ret = IXGBE_ERR_LINK_SETUP;
2379
2380 if (hw->mac.ops.check_link)
2381 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2382
2383 if (ret)
2384 goto link_cfg_out;
2385
2386 if (hw->mac.ops.get_link_capabilities)
2387 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2388 &hw->mac.autoneg);
2389 if (ret)
2390 goto link_cfg_out;
2391
2392 if (hw->mac.ops.setup_link_speed)
2393 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2394link_cfg_out:
2395 return ret;
2396}
2397
e8e26350
PW		 2398#define IXGBE_MAX_RX_DESC_POLL 10
2399static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2400 int rxr)
2401{
2402 int j = adapter->rx_ring[rxr].reg_idx;
2403 int k;
2404
2405 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2406 if (IXGBE_READ_REG(&adapter->hw,
2407 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2408 break;
2409 else
2410 msleep(1);
2411 }
2412 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2413 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2414 "not set within the polling period\n", rxr);
2415 }
2416 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2417 (adapter->rx_ring[rxr].count - 1));
2418}
2419
9a799d71
AK		 2420static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2421{
2422 struct net_device *netdev = adapter->netdev;
9a799d71 2423 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2424 int i, j = 0;
e8e26350 2425 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2426 int err;
9a799d71 2427 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2428 u32 txdctl, rxdctl, mhadd;
e8e26350 2429 u32 dmatxctl;
021230d4 2430 u32 gpie;
9a799d71 2431
5eba3699
AV		 2432 ixgbe_get_hw_control(adapter);
2433
021230d4
AV		 2434 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2435 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2436 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2437 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2438 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2439 } else {
2440 /* MSI only */
021230d4 2441 gpie = 0;
9a799d71 2442 }
021230d4
AV		 2443 /* XXX: to interrupt immediately for EICS writes, enable this */
2444 /* gpie |= IXGBE_GPIE_EIMEN; */
2445 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2446 }
2447
021230d4
AV		 2448 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2449 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2450 * specifically only auto mask tx and rx interrupts */
2451 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2452 }
9a799d71 2453
0befdb3e
JB		 2454 /* Enable fan failure interrupt if media type is copper */
2455 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2456 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2457 gpie |= IXGBE_SDP1_GPIEN;
2458 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2459 }
2460
e8e26350
PW		 2461 if (hw->mac.type == ixgbe_mac_82599EB) {
2462 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2463 gpie |= IXGBE_SDP1_GPIEN;
2464 gpie |= IXGBE_SDP2_GPIEN;
2465 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2466 }
2467
63f39bd1
YZ		 2468#ifdef IXGBE_FCOE
2469 /* adjust max frame to be able to do baby jumbo for FCoE */
2470 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2471 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2472 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2473
2474#endif /* IXGBE_FCOE */
021230d4 2475 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2476 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2477 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2478 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2479
2480 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2481 }
2482
2483 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2484 j = adapter->tx_ring[i].reg_idx;
2485 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2486 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2487 txdctl |= (8 << 16);
e8e26350
PW		 2488 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2489 }
2490
2491 if (hw->mac.type == ixgbe_mac_82599EB) {
2492 /* DMATXCTL.EN must be set after all Tx queue config is done */
2493 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2494 dmatxctl |= IXGBE_DMATXCTL_TE;
2495 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2496 }
2497 for (i = 0; i < adapter->num_tx_queues; i++) {
2498 j = adapter->tx_ring[i].reg_idx;
2499 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2500 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2501 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2502 }
2503
e8e26350 2504 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2505 j = adapter->rx_ring[i].reg_idx;
2506 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2507 /* enable PTHRESH=32 descriptors (half the internal cache)
2508 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2509 * this also removes a pesky rx_no_buffer_count increment */
2510 rxdctl |= 0x0020;
9a799d71 2511 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2512 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2513 if (hw->mac.type == ixgbe_mac_82599EB)
2514 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2515 }
2516 /* enable all receives */
2517 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2518 if (hw->mac.type == ixgbe_mac_82598EB)
2519 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2520 else
2521 rxdctl |= IXGBE_RXCTRL_RXEN;
2522 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2523
2524 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2525 ixgbe_configure_msix(adapter);
2526 else
2527 ixgbe_configure_msi_and_legacy(adapter);
2528
2529 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2530 ixgbe_napi_enable_all(adapter);
2531
2532 /* clear any pending interrupts, may auto mask */
2533 IXGBE_READ_REG(hw, IXGBE_EICR);
2534
9a799d71
AK		 2535 ixgbe_irq_enable(adapter);
2536
bf069c97
DS		 2537 /*
2538 * If this adapter has a fan, check to see if we had a failure
2539 * before we enabled the interrupt.
2540 */
2541 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2542 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2543 if (esdp & IXGBE_ESDP_SDP1)
2544 DPRINTK(DRV, CRIT,
2545 "Fan has stopped, replace the adapter\n");
2546 }
2547
e8e26350
PW		 2548 /*
2549 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2550 * arrived before interrupts were enabled. We need to kick off
2551 * the SFP+ module setup first, then try to bring up link.
2552 * If we're not hot-pluggable SFP+, we just need to configure link
2553 * and bring it up.
2554 */
2555 err = hw->phy.ops.identify(hw);
2556 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2557 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2558 ixgbe_down(adapter);
2559 return err;
2560 }
2561
2562 if (ixgbe_is_sfp(hw)) {
2563 ixgbe_sfp_link_config(adapter);
2564 } else {
2565 err = ixgbe_non_sfp_link_config(hw);
2566 if (err)
2567 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2568 }
0ecc061d 2569
1da100bb
PWJ		 2570 /* enable transmits */
2571 netif_tx_start_all_queues(netdev);
2572
9a799d71
AK		 2573 /* bring the link up in the watchdog, this could race with our first
2574 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2575 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2576 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2577 mod_timer(&adapter->watchdog_timer, jiffies);
2578 return 0;
2579}
2580
d4f80882
AV		 2581void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2582{
2583 WARN_ON(in_interrupt());
2584 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2585 msleep(1);
2586 ixgbe_down(adapter);
2587 ixgbe_up(adapter);
2588 clear_bit(__IXGBE_RESETTING, &adapter->state);
2589}
2590
9a799d71
AK		 2591int ixgbe_up(struct ixgbe_adapter *adapter)
2592{
2593 /* hardware has been reset, we need to reload some things */
2594 ixgbe_configure(adapter);
2595
2596 return ixgbe_up_complete(adapter);
2597}
2598
2599void ixgbe_reset(struct ixgbe_adapter *adapter)
2600{
c44ade9e 2601 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2602 int err;
2603
2604 err = hw->mac.ops.init_hw(hw);
2605 if (err && (err != IXGBE_ERR_SFP_NOT_PRESENT))
c44ade9e 2606 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2607
2608 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2609 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2610
2611}
2612
9a799d71
AK		 2613/**
2614 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2615 * @adapter: board private structure
2616 * @rx_ring: ring to free buffers from
2617 **/
2618static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2619 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2620{
2621 struct pci_dev *pdev = adapter->pdev;
2622 unsigned long size;
2623 unsigned int i;
2624
2625 /* Free all the Rx ring sk_buffs */
2626
2627 for (i = 0; i < rx_ring->count; i++) {
2628 struct ixgbe_rx_buffer *rx_buffer_info;
2629
2630 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2631 if (rx_buffer_info->dma) {
2632 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2633 rx_ring->rx_buf_len,
2634 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2635 rx_buffer_info->dma = 0;
2636 }
2637 if (rx_buffer_info->skb) {
f8212f97 2638 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2639 rx_buffer_info->skb = NULL;
f8212f97
AD		 2640 do {
2641 struct sk_buff *this = skb;
2642 skb = skb->prev;
2643 dev_kfree_skb(this);
2644 } while (skb);
9a799d71
AK		 2645 }
2646 if (!rx_buffer_info->page)
2647 continue;
762f4c57
JB		 2648 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2649 PCI_DMA_FROMDEVICE);
9a799d71 2650 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2651 put_page(rx_buffer_info->page);
2652 rx_buffer_info->page = NULL;
762f4c57 2653 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2654 }
2655
2656 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2657 memset(rx_ring->rx_buffer_info, 0, size);
2658
2659 /* Zero out the descriptor ring */
2660 memset(rx_ring->desc, 0, rx_ring->size);
2661
2662 rx_ring->next_to_clean = 0;
2663 rx_ring->next_to_use = 0;
2664
9891ca7c
JB		 2665 if (rx_ring->head)
2666 writel(0, adapter->hw.hw_addr + rx_ring->head);
2667 if (rx_ring->tail)
2668 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2669}
2670
2671/**
2672 * ixgbe_clean_tx_ring - Free Tx Buffers
2673 * @adapter: board private structure
2674 * @tx_ring: ring to be cleaned
2675 **/
2676static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2677 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2678{
2679 struct ixgbe_tx_buffer *tx_buffer_info;
2680 unsigned long size;
2681 unsigned int i;
2682
2683 /* Free all the Tx ring sk_buffs */
2684
2685 for (i = 0; i < tx_ring->count; i++) {
2686 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2687 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2688 }
2689
2690 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2691 memset(tx_ring->tx_buffer_info, 0, size);
2692
2693 /* Zero out the descriptor ring */
2694 memset(tx_ring->desc, 0, tx_ring->size);
2695
2696 tx_ring->next_to_use = 0;
2697 tx_ring->next_to_clean = 0;
2698
9891ca7c
JB		 2699 if (tx_ring->head)
2700 writel(0, adapter->hw.hw_addr + tx_ring->head);
2701 if (tx_ring->tail)
2702 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2703}
2704
2705/**
021230d4 2706 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2707 * @adapter: board private structure
2708 **/
021230d4 2709static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2710{
2711 int i;
2712
021230d4
AV		 2713 for (i = 0; i < adapter->num_rx_queues; i++)
2714 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2715}
2716
2717/**
021230d4 2718 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2719 * @adapter: board private structure
2720 **/
021230d4 2721static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2722{
2723 int i;
2724
021230d4
AV		 2725 for (i = 0; i < adapter->num_tx_queues; i++)
2726 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2727}
2728
2729void ixgbe_down(struct ixgbe_adapter *adapter)
2730{
2731 struct net_device *netdev = adapter->netdev;
7f821875 2732 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2733 u32 rxctrl;
7f821875
JB		 2734 u32 txdctl;
2735 int i, j;
9a799d71
AK		 2736
2737 /* signal that we are down to the interrupt handler */
2738 set_bit(__IXGBE_DOWN, &adapter->state);
2739
2740 /* disable receives */
7f821875
JB		 2741 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2742 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2743
2744 netif_tx_disable(netdev);
2745
7f821875 2746 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2747 msleep(10);
2748
7f821875
JB		 2749 netif_tx_stop_all_queues(netdev);
2750
9a799d71
AK		 2751 ixgbe_irq_disable(adapter);
2752
021230d4 2753 ixgbe_napi_disable_all(adapter);
7f821875 2754
9a799d71 2755 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2756 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2757
7f821875
JB		 2758 /* disable transmits in the hardware now that interrupts are off */
2759 for (i = 0; i < adapter->num_tx_queues; i++) {
2760 j = adapter->tx_ring[i].reg_idx;
2761 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2762 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2763 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2764 }
88512539
PW		 2765 /* Disable the Tx DMA engine on 82599 */
2766 if (hw->mac.type == ixgbe_mac_82599EB)
2767 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2768 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2769 ~IXGBE_DMATXCTL_TE));
7f821875 2770
9a799d71 2771 netif_carrier_off(netdev);
9a799d71 2772
6f4a0e45
PL		 2773 if (!pci_channel_offline(adapter->pdev))
2774 ixgbe_reset(adapter);
9a799d71
AK		 2775 ixgbe_clean_all_tx_rings(adapter);
2776 ixgbe_clean_all_rx_rings(adapter);
2777
5dd2d332 2778#ifdef CONFIG_IXGBE_DCA
96b0e0f6 2779 /* since we reset the hardware DCA settings were cleared */
e35ec126 2780 ixgbe_setup_dca(adapter);
96b0e0f6 2781#endif
9a799d71
AK		 2782}
2783
9a799d71 2784/**
021230d4
AV		 2785 * ixgbe_poll - NAPI Rx polling callback
2786 * @napi: structure for representing this polling device
2787 * @budget: how many packets driver is allowed to clean
2788 *
2789 * This function is used for legacy and MSI, NAPI mode
9a799d71 2790 **/
021230d4 2791static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2792{
9a1a69ad
JB		 2793 struct ixgbe_q_vector *q_vector =
2794 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2795 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2796 int tx_clean_complete, work_done = 0;
9a799d71 2797
5dd2d332 2798#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2799 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2800 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2801 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2802 }
2803#endif
2804
9a1a69ad 2805 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2806 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2807
9a1a69ad 2808 if (!tx_clean_complete)
d2c7ddd6
DM		 2809 work_done = budget;
2810
53e52c72
DM		 2811 /* If budget not fully consumed, exit the polling mode */
2812 if (work_done < budget) {
288379f0 2813 napi_complete(napi);
509ee935 2814 if (adapter->itr_setting & 1)
f494e8fa 2815 ixgbe_set_itr(adapter);
d4f80882 2816 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2817 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2818 }
9a799d71
AK		 2819 return work_done;
2820}
2821
2822/**
2823 * ixgbe_tx_timeout - Respond to a Tx Hang
2824 * @netdev: network interface device structure
2825 **/
2826static void ixgbe_tx_timeout(struct net_device *netdev)
2827{
2828 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2829
2830 /* Do the reset outside of interrupt context */
2831 schedule_work(&adapter->reset_task);
2832}
2833
2834static void ixgbe_reset_task(struct work_struct *work)
2835{
2836 struct ixgbe_adapter *adapter;
2837 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2838
2f90b865
AD		 2839 /* If we're already down or resetting, just bail */
2840 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2841 test_bit(__IXGBE_RESETTING, &adapter->state))
2842 return;
2843
9a799d71
AK		 2844 adapter->tx_timeout_count++;
2845
d4f80882 2846 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2847}
2848
bc97114d
PWJ		 2849#ifdef CONFIG_IXGBE_DCB
2850static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2851{
bc97114d 2852 bool ret = false;
0cefafad 2853 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 2854
0cefafad
JB		 2855 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2856 return ret;
2857
2858 f->mask = 0x7 << 3;
2859 adapter->num_rx_queues = f->indices;
2860 adapter->num_tx_queues = f->indices;
2861 ret = true;
2f90b865 2862
bc97114d
PWJ		 2863 return ret;
2864}
2865#endif
2866
4df10466
JB		 2867/**
2868 * ixgbe_set_rss_queues: Allocate queues for RSS
2869 * @adapter: board private structure to initialize
2870 *
2871 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2872 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2873 *
2874 **/
bc97114d
PWJ		 2875static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2876{
2877 bool ret = false;
0cefafad 2878 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 2879
2880 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 2881 f->mask = 0xF;
2882 adapter->num_rx_queues = f->indices;
2883 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 2884 ret = true;
2885 } else {
bc97114d 2886 ret = false;
b9804972
JB		 2887 }
2888
bc97114d
PWJ		 2889 return ret;
2890}
2891
0331a832
YZ		 2892#ifdef IXGBE_FCOE
2893/**
2894 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
2895 * @adapter: board private structure to initialize
2896 *
2897 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
2898 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
2899 * rx queues out of the max number of rx queues, instead, it is used as the
2900 * index of the first rx queue used by FCoE.
2901 *
2902 **/
2903static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
2904{
2905 bool ret = false;
2906 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
2907
2908 f->indices = min((int)num_online_cpus(), f->indices);
2909 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2910#ifdef CONFIG_IXGBE_DCB
2911 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2912 DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
2913 ixgbe_set_dcb_queues(adapter);
2914 }
2915#endif
2916 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2917 DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
2918 ixgbe_set_rss_queues(adapter);
2919 }
2920 /* adding FCoE rx rings to the end */
2921 f->mask = adapter->num_rx_queues;
2922 adapter->num_rx_queues += f->indices;
2923 if (adapter->num_tx_queues == 0)
2924 adapter->num_tx_queues = f->indices;
2925
2926 ret = true;
2927 }
2928
2929 return ret;
2930}
2931
2932#endif /* IXGBE_FCOE */
4df10466
JB		 2933/*
2934 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2935 * @adapter: board private structure to initialize
2936 *
2937 * This is the top level queue allocation routine. The order here is very
2938 * important, starting with the "most" number of features turned on at once,
2939 * and ending with the smallest set of features. This way large combinations
2940 * can be allocated if they're turned on, and smaller combinations are the
2941 * fallthrough conditions.
2942 *
2943 **/
bc97114d
PWJ		 2944static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2945{
0331a832
YZ		 2946#ifdef IXGBE_FCOE
2947 if (ixgbe_set_fcoe_queues(adapter))
2948 goto done;
2949
2950#endif /* IXGBE_FCOE */
bc97114d
PWJ		 2951#ifdef CONFIG_IXGBE_DCB
2952 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 2953 goto done;
bc97114d
PWJ		 2954
2955#endif
2956 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 2957 goto done;
2958
2959 /* fallback to base case */
2960 adapter->num_rx_queues = 1;
2961 adapter->num_tx_queues = 1;
2962
2963done:
2964 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2965 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 2966}
2967
021230d4 2968static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2969 int vectors)
021230d4
AV		 2970{
2971 int err, vector_threshold;
2972
2973 /* We'll want at least 3 (vector_threshold):
2974 * 1) TxQ[0] Cleanup
2975 * 2) RxQ[0] Cleanup
2976 * 3) Other (Link Status Change, etc.)
2977 * 4) TCP Timer (optional)
2978 */
2979 vector_threshold = MIN_MSIX_COUNT;
2980
2981 /* The more we get, the more we will assign to Tx/Rx Cleanup
2982 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2983 * Right now, we simply care about how many we'll get; we'll
2984 * set them up later while requesting irq's.
2985 */
2986 while (vectors >= vector_threshold) {
2987 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2988 vectors);
021230d4
AV		 2989 if (!err) /* Success in acquiring all requested vectors. */
2990 break;
2991 else if (err < 0)
2992 vectors = 0; /* Nasty failure, quit now */
2993 else /* err == number of vectors we should try again with */
2994 vectors = err;
2995 }
2996
2997 if (vectors < vector_threshold) {
2998 /* Can't allocate enough MSI-X interrupts? Oh well.
2999 * This just means we'll go with either a single MSI
3000 * vector or fall back to legacy interrupts.
3001 */
3002 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3003 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3004 kfree(adapter->msix_entries);
3005 adapter->msix_entries = NULL;
021230d4
AV		 3006 } else {
3007 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3008 /*
3009 * Adjust for only the vectors we'll use, which is minimum
3010 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3011 * vectors we were allocated.
3012 */
3013 adapter->num_msix_vectors = min(vectors,
3014 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3015 }
3016}
3017
021230d4 3018/**
bc97114d 3019 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3020 * @adapter: board private structure to initialize
3021 *
bc97114d
PWJ		 3022 * Cache the descriptor ring offsets for RSS to the assigned rings.
3023 *
021230d4 3024 **/
bc97114d 3025static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3026{
bc97114d
PWJ		 3027 int i;
3028 bool ret = false;
3029
3030 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3031 for (i = 0; i < adapter->num_rx_queues; i++)
3032 adapter->rx_ring[i].reg_idx = i;
3033 for (i = 0; i < adapter->num_tx_queues; i++)
3034 adapter->tx_ring[i].reg_idx = i;
3035 ret = true;
3036 } else {
3037 ret = false;
3038 }
3039
3040 return ret;
3041}
3042
3043#ifdef CONFIG_IXGBE_DCB
3044/**
3045 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3046 * @adapter: board private structure to initialize
3047 *
3048 * Cache the descriptor ring offsets for DCB to the assigned rings.
3049 *
3050 **/
3051static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3052{
3053 int i;
3054 bool ret = false;
3055 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3056
3057 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3058 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3059 /* the number of queues is assumed to be symmetric */
3060 for (i = 0; i < dcb_i; i++) {
3061 adapter->rx_ring[i].reg_idx = i << 3;
3062 adapter->tx_ring[i].reg_idx = i << 2;
3063 }
bc97114d 3064 ret = true;
e8e26350 3065 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3066 if (dcb_i == 8) {
3067 /*
3068 * Tx TC0 starts at: descriptor queue 0
3069 * Tx TC1 starts at: descriptor queue 32
3070 * Tx TC2 starts at: descriptor queue 64
3071 * Tx TC3 starts at: descriptor queue 80
3072 * Tx TC4 starts at: descriptor queue 96
3073 * Tx TC5 starts at: descriptor queue 104
3074 * Tx TC6 starts at: descriptor queue 112
3075 * Tx TC7 starts at: descriptor queue 120
3076 *
3077 * Rx TC0-TC7 are offset by 16 queues each
3078 */
3079 for (i = 0; i < 3; i++) {
3080 adapter->tx_ring[i].reg_idx = i << 5;
3081 adapter->rx_ring[i].reg_idx = i << 4;
3082 }
3083 for ( ; i < 5; i++) {
3084 adapter->tx_ring[i].reg_idx =
3085 ((i + 2) << 4);
3086 adapter->rx_ring[i].reg_idx = i << 4;
3087 }
3088 for ( ; i < dcb_i; i++) {
3089 adapter->tx_ring[i].reg_idx =
3090 ((i + 8) << 3);
3091 adapter->rx_ring[i].reg_idx = i << 4;
3092 }
3093
3094 ret = true;
3095 } else if (dcb_i == 4) {
3096 /*
3097 * Tx TC0 starts at: descriptor queue 0
3098 * Tx TC1 starts at: descriptor queue 64
3099 * Tx TC2 starts at: descriptor queue 96
3100 * Tx TC3 starts at: descriptor queue 112
3101 *
3102 * Rx TC0-TC3 are offset by 32 queues each
3103 */
3104 adapter->tx_ring[0].reg_idx = 0;
3105 adapter->tx_ring[1].reg_idx = 64;
3106 adapter->tx_ring[2].reg_idx = 96;
3107 adapter->tx_ring[3].reg_idx = 112;
3108 for (i = 0 ; i < dcb_i; i++)
3109 adapter->rx_ring[i].reg_idx = i << 5;
3110
3111 ret = true;
3112 } else {
3113 ret = false;
e8e26350 3114 }
bc97114d
PWJ		 3115 } else {
3116 ret = false;
021230d4 3117 }
bc97114d
PWJ		 3118 } else {
3119 ret = false;
021230d4 3120 }
bc97114d
PWJ		 3121
3122 return ret;
3123}
3124#endif
3125
0331a832
YZ		 3126#ifdef IXGBE_FCOE
3127/**
3128 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3129 * @adapter: board private structure to initialize
3130 *
3131 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3132 *
3133 */
3134static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3135{
3136 int i, fcoe_i = 0;
3137 bool ret = false;
3138 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3139
3140 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3141#ifdef CONFIG_IXGBE_DCB
3142 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3143 ixgbe_cache_ring_dcb(adapter);
3144 fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3145 }
3146#endif /* CONFIG_IXGBE_DCB */
3147 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3148 ixgbe_cache_ring_rss(adapter);
3149 fcoe_i = f->mask;
3150 }
3151 for (i = 0; i < f->indices; i++, fcoe_i++)
3152 adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3153 ret = true;
3154 }
3155 return ret;
3156}
3157
3158#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3159/**
3160 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3161 * @adapter: board private structure to initialize
3162 *
3163 * Once we know the feature-set enabled for the device, we'll cache
3164 * the register offset the descriptor ring is assigned to.
3165 *
3166 * Note, the order the various feature calls is important. It must start with
3167 * the "most" features enabled at the same time, then trickle down to the
3168 * least amount of features turned on at once.
3169 **/
3170static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3171{
3172 /* start with default case */
3173 adapter->rx_ring[0].reg_idx = 0;
3174 adapter->tx_ring[0].reg_idx = 0;
3175
0331a832
YZ		 3176#ifdef IXGBE_FCOE
3177 if (ixgbe_cache_ring_fcoe(adapter))
3178 return;
3179
3180#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3181#ifdef CONFIG_IXGBE_DCB
3182 if (ixgbe_cache_ring_dcb(adapter))
3183 return;
3184
3185#endif
3186 if (ixgbe_cache_ring_rss(adapter))
3187 return;
021230d4
AV		 3188}
3189
9a799d71
AK		 3190/**
3191 * ixgbe_alloc_queues - Allocate memory for all rings
3192 * @adapter: board private structure to initialize
3193 *
3194 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3195 * number of queues at compile-time. The polling_netdev array is
3196 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3197 **/
2f90b865 3198static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3199{
3200 int i;
3201
3202 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3203 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3204 if (!adapter->tx_ring)
021230d4 3205 goto err_tx_ring_allocation;
9a799d71
AK		 3206
3207 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3208 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3209 if (!adapter->rx_ring)
3210 goto err_rx_ring_allocation;
9a799d71 3211
021230d4 3212 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3213 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3214 adapter->tx_ring[i].queue_index = i;
3215 }
b9804972 3216
9a799d71 3217 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3218 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3219 adapter->rx_ring[i].queue_index = i;
3220 }
3221
3222 ixgbe_cache_ring_register(adapter);
3223
3224 return 0;
3225
3226err_rx_ring_allocation:
3227 kfree(adapter->tx_ring);
3228err_tx_ring_allocation:
3229 return -ENOMEM;
3230}
3231
3232/**
3233 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3234 * @adapter: board private structure to initialize
3235 *
3236 * Attempt to configure the interrupts using the best available
3237 * capabilities of the hardware and the kernel.
3238 **/
feea6a57 3239static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3240{
8be0e467 3241 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3242 int err = 0;
3243 int vector, v_budget;
3244
3245 /*
3246 * It's easy to be greedy for MSI-X vectors, but it really
3247 * doesn't do us much good if we have a lot more vectors
3248 * than CPU's. So let's be conservative and only ask for
3249 * (roughly) twice the number of vectors as there are CPU's.
3250 */
3251 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3252 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3253
3254 /*
3255 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3256 * hw.mac->max_msix_vectors vectors. With features
3257 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3258 * descriptor queues supported by our device. Thus, we cap it off in
3259 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3260 */
8be0e467 3261 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3262
3263 /* A failure in MSI-X entry allocation isn't fatal, but it does
3264 * mean we disable MSI-X capabilities of the adapter. */
3265 adapter->msix_entries = kcalloc(v_budget,
b4617240 3266 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3267 if (adapter->msix_entries) {
3268 for (vector = 0; vector < v_budget; vector++)
3269 adapter->msix_entries[vector].entry = vector;
021230d4 3270
7a921c93 3271 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3272
7a921c93
AD		 3273 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3274 goto out;
3275 }
021230d4 3276
7a921c93
AD		 3277 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3278 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3279 ixgbe_set_num_queues(adapter);
021230d4 3280
021230d4
AV		 3281 err = pci_enable_msi(adapter->pdev);
3282 if (!err) {
3283 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3284 } else {
3285 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3286 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3287 /* reset err */
3288 err = 0;
3289 }
3290
3291out:
021230d4
AV		 3292 return err;
3293}
3294
7a921c93
AD		 3295/**
3296 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3297 * @adapter: board private structure to initialize
3298 *
3299 * We allocate one q_vector per queue interrupt. If allocation fails we
3300 * return -ENOMEM.
3301 **/
3302static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3303{
3304 int q_idx, num_q_vectors;
3305 struct ixgbe_q_vector *q_vector;
3306 int napi_vectors;
3307 int (*poll)(struct napi_struct *, int);
3308
3309 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3310 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3311 napi_vectors = adapter->num_rx_queues;
3312 poll = &ixgbe_clean_rxonly;
3313 } else {
3314 num_q_vectors = 1;
3315 napi_vectors = 1;
3316 poll = &ixgbe_poll;
3317 }
3318
3319 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3320 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3321 if (!q_vector)
3322 goto err_out;
3323 q_vector->adapter = adapter;
3324 q_vector->v_idx = q_idx;
3325 q_vector->eitr = adapter->eitr_param;
3326 if (q_idx < napi_vectors)
3327 netif_napi_add(adapter->netdev, &q_vector->napi,
3328 (*poll), 64);
3329 adapter->q_vector[q_idx] = q_vector;
3330 }
3331
3332 return 0;
3333
3334err_out:
3335 while (q_idx) {
3336 q_idx--;
3337 q_vector = adapter->q_vector[q_idx];
3338 netif_napi_del(&q_vector->napi);
3339 kfree(q_vector);
3340 adapter->q_vector[q_idx] = NULL;
3341 }
3342 return -ENOMEM;
3343}
3344
3345/**
3346 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3347 * @adapter: board private structure to initialize
3348 *
3349 * This function frees the memory allocated to the q_vectors. In addition if
3350 * NAPI is enabled it will delete any references to the NAPI struct prior
3351 * to freeing the q_vector.
3352 **/
3353static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3354{
3355 int q_idx, num_q_vectors;
3356 int napi_vectors;
3357
3358 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3359 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3360 napi_vectors = adapter->num_rx_queues;
3361 } else {
3362 num_q_vectors = 1;
3363 napi_vectors = 1;
3364 }
3365
3366 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3367 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3368
3369 adapter->q_vector[q_idx] = NULL;
3370 if (q_idx < napi_vectors)
3371 netif_napi_del(&q_vector->napi);
3372 kfree(q_vector);
3373 }
3374}
3375
2f90b865 3376void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3377{
3378 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3379 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3380 pci_disable_msix(adapter->pdev);
3381 kfree(adapter->msix_entries);
3382 adapter->msix_entries = NULL;
3383 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3384 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3385 pci_disable_msi(adapter->pdev);
3386 }
3387 return;
3388}
3389
3390/**
3391 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3392 * @adapter: board private structure to initialize
3393 *
3394 * We determine which interrupt scheme to use based on...
3395 * - Kernel support (MSI, MSI-X)
3396 * - which can be user-defined (via MODULE_PARAM)
3397 * - Hardware queue count (num_*_queues)
3398 * - defined by miscellaneous hardware support/features (RSS, etc.)
3399 **/
2f90b865 3400int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3401{
3402 int err;
3403
3404 /* Number of supported queues */
3405 ixgbe_set_num_queues(adapter);
3406
021230d4
AV		 3407 err = ixgbe_set_interrupt_capability(adapter);
3408 if (err) {
3409 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3410 goto err_set_interrupt;
9a799d71
AK		 3411 }
3412
7a921c93
AD		 3413 err = ixgbe_alloc_q_vectors(adapter);
3414 if (err) {
3415 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3416 "vectors\n");
3417 goto err_alloc_q_vectors;
3418 }
3419
3420 err = ixgbe_alloc_queues(adapter);
3421 if (err) {
3422 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3423 goto err_alloc_queues;
3424 }
3425
021230d4 3426 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3427 "Tx Queue count = %u\n",
3428 (adapter->num_rx_queues > 1) ? "Enabled" :
3429 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3430
3431 set_bit(__IXGBE_DOWN, &adapter->state);
3432
9a799d71 3433 return 0;
021230d4 3434
7a921c93
AD		 3435err_alloc_queues:
3436 ixgbe_free_q_vectors(adapter);
3437err_alloc_q_vectors:
3438 ixgbe_reset_interrupt_capability(adapter);
021230d4 3439err_set_interrupt:
7a921c93
AD		 3440 return err;
3441}
3442
3443/**
3444 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3445 * @adapter: board private structure to clear interrupt scheme on
3446 *
3447 * We go through and clear interrupt specific resources and reset the structure
3448 * to pre-load conditions
3449 **/
3450void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3451{
021230d4
AV		 3452 kfree(adapter->tx_ring);
3453 kfree(adapter->rx_ring);
7a921c93
AD		 3454 adapter->tx_ring = NULL;
3455 adapter->rx_ring = NULL;
3456
3457 ixgbe_free_q_vectors(adapter);
3458 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3459}
3460
c4900be0
DS		 3461/**
3462 * ixgbe_sfp_timer - worker thread to find a missing module
3463 * @data: pointer to our adapter struct
3464 **/
3465static void ixgbe_sfp_timer(unsigned long data)
3466{
3467 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3468
4df10466
JB		 3469 /*
3470 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3471 * delays that sfp+ detection requires
3472 */
3473 schedule_work(&adapter->sfp_task);
3474}
3475
3476/**
3477 * ixgbe_sfp_task - worker thread to find a missing module
3478 * @work: pointer to work_struct containing our data
3479 **/
3480static void ixgbe_sfp_task(struct work_struct *work)
3481{
3482 struct ixgbe_adapter *adapter = container_of(work,
3483 struct ixgbe_adapter,
3484 sfp_task);
3485 struct ixgbe_hw *hw = &adapter->hw;
3486
3487 if ((hw->phy.type == ixgbe_phy_nl) &&
3488 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3489 s32 ret = hw->phy.ops.identify_sfp(hw);
3490 if (ret)
3491 goto reschedule;
3492 ret = hw->phy.ops.reset(hw);
3493 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3494 DPRINTK(PROBE, ERR, "failed to initialize because an "
3495 "unsupported SFP+ module type was detected.\n"
3496 "Reload the driver after installing a "
3497 "supported module.\n");
3498 unregister_netdev(adapter->netdev);
3499 } else {
3500 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3501 hw->phy.sfp_type);
3502 }
3503 /* don't need this routine any more */
3504 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3505 }
3506 return;
3507reschedule:
3508 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3509 mod_timer(&adapter->sfp_timer,
3510 round_jiffies(jiffies + (2 * HZ)));
3511}
3512
9a799d71
AK		 3513/**
3514 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3515 * @adapter: board private structure to initialize
3516 *
3517 * ixgbe_sw_init initializes the Adapter private data structure.
3518 * Fields are initialized based on PCI device information and
3519 * OS network device settings (MTU size).
3520 **/
3521static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3522{
3523 struct ixgbe_hw *hw = &adapter->hw;
3524 struct pci_dev *pdev = adapter->pdev;
021230d4 3525 unsigned int rss;
7a6b6f51 3526#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3527 int j;
3528 struct tc_configuration *tc;
3529#endif
021230d4 3530
c44ade9e
JB		 3531 /* PCI config space info */
3532
3533 hw->vendor_id = pdev->vendor;
3534 hw->device_id = pdev->device;
3535 hw->revision_id = pdev->revision;
3536 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3537 hw->subsystem_device_id = pdev->subsystem_device;
3538
021230d4
AV		 3539 /* Set capability flags */
3540 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3541 adapter->ring_feature[RING_F_RSS].indices = rss;
3542 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3543 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3544 if (hw->mac.type == ixgbe_mac_82598EB) {
3545 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3546 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3547 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3548 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3549 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
f8212f97
AD		 3550 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3551 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
eacd73f7
YZ		 3552#ifdef IXGBE_FCOE
3553 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
0331a832 3554 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
eacd73f7 3555#endif /* IXGBE_FCOE */
f8212f97 3556 }
2f90b865 3557
7a6b6f51 3558#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3559 /* Configure DCB traffic classes */
3560 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3561 tc = &adapter->dcb_cfg.tc_config[j];
3562 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3563 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3564 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3565 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3566 tc->dcb_pfc = pfc_disabled;
3567 }
3568 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3569 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3570 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3571 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3572 adapter->dcb_cfg.round_robin_enable = false;
3573 adapter->dcb_set_bitmap = 0x00;
3574 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3575 adapter->ring_feature[RING_F_DCB].indices);
3576
3577#endif
9a799d71
AK		 3578
3579 /* default flow control settings */
cd7664f6 3580 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3581 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3582#ifdef CONFIG_DCB
3583 adapter->last_lfc_mode = hw->fc.current_mode;
3584#endif
2b9ade93
JB		 3585 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3586 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3587 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3588 hw->fc.send_xon = true;
71fd570b 3589 hw->fc.disable_fc_autoneg = false;
9a799d71 3590
30efa5a3
JB		 3591 /* enable itr by default in dynamic mode */
3592 adapter->itr_setting = 1;
3593 adapter->eitr_param = 20000;
3594
3595 /* set defaults for eitr in MegaBytes */
3596 adapter->eitr_low = 10;
3597 adapter->eitr_high = 20;
3598
3599 /* set default ring sizes */
3600 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3601 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3602
9a799d71 3603 /* initialize eeprom parameters */
c44ade9e 3604 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3605 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3606 return -EIO;
3607 }
3608
021230d4 3609 /* enable rx csum by default */
9a799d71
AK		 3610 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3611
9a799d71
AK		 3612 set_bit(__IXGBE_DOWN, &adapter->state);
3613
3614 return 0;
3615}
3616
3617/**
3618 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3619 * @adapter: board private structure
3a581073 3620 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3621 *
3622 * Return 0 on success, negative on failure
3623 **/
3624int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3625 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3626{
3627 struct pci_dev *pdev = adapter->pdev;
3628 int size;
3629
3a581073
JB		 3630 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3631 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3632 if (!tx_ring->tx_buffer_info)
3633 goto err;
3a581073 3634 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3635
3636 /* round up to nearest 4K */
12207e49 3637 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3638 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3639
3a581073
JB		 3640 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3641 &tx_ring->dma);
e01c31a5
JB		 3642 if (!tx_ring->desc)
3643 goto err;
9a799d71 3644
3a581073
JB		 3645 tx_ring->next_to_use = 0;
3646 tx_ring->next_to_clean = 0;
3647 tx_ring->work_limit = tx_ring->count;
9a799d71 3648 return 0;
e01c31a5
JB		 3649
3650err:
3651 vfree(tx_ring->tx_buffer_info);
3652 tx_ring->tx_buffer_info = NULL;
3653 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3654 "descriptor ring\n");
3655 return -ENOMEM;
9a799d71
AK		 3656}
3657
69888674
AD		 3658/**
3659 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3660 * @adapter: board private structure
3661 *
3662 * If this function returns with an error, then it's possible one or
3663 * more of the rings is populated (while the rest are not). It is the
3664 * callers duty to clean those orphaned rings.
3665 *
3666 * Return 0 on success, negative on failure
3667 **/
3668static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3669{
3670 int i, err = 0;
3671
3672 for (i = 0; i < adapter->num_tx_queues; i++) {
3673 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3674 if (!err)
3675 continue;
3676 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3677 break;
3678 }
3679
3680 return err;
3681}
3682
9a799d71
AK		 3683/**
3684 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3685 * @adapter: board private structure
3a581073 3686 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3687 *
3688 * Returns 0 on success, negative on failure
3689 **/
3690int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3691 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3692{
3693 struct pci_dev *pdev = adapter->pdev;
021230d4 3694 int size;
9a799d71 3695
3a581073
JB		 3696 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3697 rx_ring->rx_buffer_info = vmalloc(size);
3698 if (!rx_ring->rx_buffer_info) {
9a799d71 3699 DPRINTK(PROBE, ERR,
b4617240 3700 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3701 goto alloc_failed;
9a799d71 3702 }
3a581073 3703 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3704
9a799d71 3705 /* Round up to nearest 4K */
3a581073
JB		 3706 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3707 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3708
3a581073 3709 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3710
3a581073 3711 if (!rx_ring->desc) {
9a799d71 3712 DPRINTK(PROBE, ERR,
b4617240 3713 "Memory allocation failed for the rx desc ring\n");
3a581073 3714 vfree(rx_ring->rx_buffer_info);
177db6ff 3715 goto alloc_failed;
9a799d71
AK		 3716 }
3717
3a581073
JB		 3718 rx_ring->next_to_clean = 0;
3719 rx_ring->next_to_use = 0;
9a799d71
AK		 3720
3721 return 0;
177db6ff
MC		 3722
3723alloc_failed:
177db6ff 3724 return -ENOMEM;
9a799d71
AK		 3725}
3726
69888674
AD		 3727/**
3728 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3729 * @adapter: board private structure
3730 *
3731 * If this function returns with an error, then it's possible one or
3732 * more of the rings is populated (while the rest are not). It is the
3733 * callers duty to clean those orphaned rings.
3734 *
3735 * Return 0 on success, negative on failure
3736 **/
3737
3738static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3739{
3740 int i, err = 0;
3741
3742 for (i = 0; i < adapter->num_rx_queues; i++) {
3743 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3744 if (!err)
3745 continue;
3746 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3747 break;
3748 }
3749
3750 return err;
3751}
3752
9a799d71
AK		 3753/**
3754 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3755 * @adapter: board private structure
3756 * @tx_ring: Tx descriptor ring for a specific queue
3757 *
3758 * Free all transmit software resources
3759 **/
c431f97e
JB		 3760void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3761 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3762{
3763 struct pci_dev *pdev = adapter->pdev;
3764
3765 ixgbe_clean_tx_ring(adapter, tx_ring);
3766
3767 vfree(tx_ring->tx_buffer_info);
3768 tx_ring->tx_buffer_info = NULL;
3769
3770 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3771
3772 tx_ring->desc = NULL;
3773}
3774
3775/**
3776 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3777 * @adapter: board private structure
3778 *
3779 * Free all transmit software resources
3780 **/
3781static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3782{
3783 int i;
3784
3785 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 3786 if (adapter->tx_ring[i].desc)
3787 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3788}
3789
3790/**
b4617240 3791 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3792 * @adapter: board private structure
3793 * @rx_ring: ring to clean the resources from
3794 *
3795 * Free all receive software resources
3796 **/
c431f97e
JB		 3797void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3798 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3799{
3800 struct pci_dev *pdev = adapter->pdev;
3801
3802 ixgbe_clean_rx_ring(adapter, rx_ring);
3803
3804 vfree(rx_ring->rx_buffer_info);
3805 rx_ring->rx_buffer_info = NULL;
3806
3807 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3808
3809 rx_ring->desc = NULL;
3810}
3811
3812/**
3813 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3814 * @adapter: board private structure
3815 *
3816 * Free all receive software resources
3817 **/
3818static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3819{
3820 int i;
3821
3822 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 3823 if (adapter->rx_ring[i].desc)
3824 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3825}
3826
9a799d71
AK		 3827/**
3828 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3829 * @netdev: network interface device structure
3830 * @new_mtu: new value for maximum frame size
3831 *
3832 * Returns 0 on success, negative on failure
3833 **/
3834static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3835{
3836 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3837 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3838
42c783c5
JB		 3839 /* MTU < 68 is an error and causes problems on some kernels */
3840 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3841 return -EINVAL;
3842
021230d4 3843 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3844 netdev->mtu, new_mtu);
021230d4 3845 /* must set new MTU before calling down or up */
9a799d71
AK		 3846 netdev->mtu = new_mtu;
3847
d4f80882
AV		 3848 if (netif_running(netdev))
3849 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3850
3851 return 0;
3852}
3853
3854/**
3855 * ixgbe_open - Called when a network interface is made active
3856 * @netdev: network interface device structure
3857 *
3858 * Returns 0 on success, negative value on failure
3859 *
3860 * The open entry point is called when a network interface is made
3861 * active by the system (IFF_UP). At this point all resources needed
3862 * for transmit and receive operations are allocated, the interrupt
3863 * handler is registered with the OS, the watchdog timer is started,
3864 * and the stack is notified that the interface is ready.
3865 **/
3866static int ixgbe_open(struct net_device *netdev)
3867{
3868 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3869 int err;
4bebfaa5
AK		 3870
3871 /* disallow open during test */
3872 if (test_bit(__IXGBE_TESTING, &adapter->state))
3873 return -EBUSY;
9a799d71 3874
54386467
JB		 3875 netif_carrier_off(netdev);
3876
9a799d71
AK		 3877 /* allocate transmit descriptors */
3878 err = ixgbe_setup_all_tx_resources(adapter);
3879 if (err)
3880 goto err_setup_tx;
3881
9a799d71
AK		 3882 /* allocate receive descriptors */
3883 err = ixgbe_setup_all_rx_resources(adapter);
3884 if (err)
3885 goto err_setup_rx;
3886
3887 ixgbe_configure(adapter);
3888
021230d4 3889 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3890 if (err)
3891 goto err_req_irq;
3892
9a799d71
AK		 3893 err = ixgbe_up_complete(adapter);
3894 if (err)
3895 goto err_up;
3896
d55b53ff
JK		 3897 netif_tx_start_all_queues(netdev);
3898
9a799d71
AK		 3899 return 0;
3900
3901err_up:
5eba3699 3902 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3903 ixgbe_free_irq(adapter);
3904err_req_irq:
9a799d71 3905err_setup_rx:
a20a1199 3906 ixgbe_free_all_rx_resources(adapter);
9a799d71 3907err_setup_tx:
a20a1199 3908 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 3909 ixgbe_reset(adapter);
3910
3911 return err;
3912}
3913
3914/**
3915 * ixgbe_close - Disables a network interface
3916 * @netdev: network interface device structure
3917 *
3918 * Returns 0, this is not allowed to fail
3919 *
3920 * The close entry point is called when an interface is de-activated
3921 * by the OS. The hardware is still under the drivers control, but
3922 * needs to be disabled. A global MAC reset is issued to stop the
3923 * hardware, and all transmit and receive resources are freed.
3924 **/
3925static int ixgbe_close(struct net_device *netdev)
3926{
3927 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3928
3929 ixgbe_down(adapter);
3930 ixgbe_free_irq(adapter);
3931
3932 ixgbe_free_all_tx_resources(adapter);
3933 ixgbe_free_all_rx_resources(adapter);
3934
5eba3699 3935 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3936
3937 return 0;
3938}
3939
b3c8b4ba
AD		 3940#ifdef CONFIG_PM
3941static int ixgbe_resume(struct pci_dev *pdev)
3942{
3943 struct net_device *netdev = pci_get_drvdata(pdev);
3944 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3945 u32 err;
3946
3947 pci_set_power_state(pdev, PCI_D0);
3948 pci_restore_state(pdev);
9ce77666 3949
3950 err = pci_enable_device_mem(pdev);
b3c8b4ba 3951 if (err) {
69888674 3952 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3953 "suspend\n");
3954 return err;
3955 }
3956 pci_set_master(pdev);
3957
dd4d8ca6 3958 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 3959
3960 err = ixgbe_init_interrupt_scheme(adapter);
3961 if (err) {
3962 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3963 "device\n");
3964 return err;
3965 }
3966
b3c8b4ba
AD		 3967 ixgbe_reset(adapter);
3968
495dce12
WJP		 3969 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3970
b3c8b4ba
AD		 3971 if (netif_running(netdev)) {
3972 err = ixgbe_open(adapter->netdev);
3973 if (err)
3974 return err;
3975 }
3976
3977 netif_device_attach(netdev);
3978
3979 return 0;
3980}
b3c8b4ba 3981#endif /* CONFIG_PM */
9d8d05ae
RW		 3982
3983static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 3984{
3985 struct net_device *netdev = pci_get_drvdata(pdev);
3986 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3987 struct ixgbe_hw *hw = &adapter->hw;
3988 u32 ctrl, fctrl;
3989 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3990#ifdef CONFIG_PM
3991 int retval = 0;
3992#endif
3993
3994 netif_device_detach(netdev);
3995
3996 if (netif_running(netdev)) {
3997 ixgbe_down(adapter);
3998 ixgbe_free_irq(adapter);
3999 ixgbe_free_all_tx_resources(adapter);
4000 ixgbe_free_all_rx_resources(adapter);
4001 }
7a921c93 4002 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4003
4004#ifdef CONFIG_PM
4005 retval = pci_save_state(pdev);
4006 if (retval)
4007 return retval;
4df10466 4008
b3c8b4ba 4009#endif
e8e26350
PW		 4010 if (wufc) {
4011 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4012
e8e26350
PW		 4013 /* turn on all-multi mode if wake on multicast is enabled */
4014 if (wufc & IXGBE_WUFC_MC) {
4015 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4016 fctrl |= IXGBE_FCTRL_MPE;
4017 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4018 }
4019
4020 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4021 ctrl |= IXGBE_CTRL_GIO_DIS;
4022 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4023
4024 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4025 } else {
4026 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4027 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4028 }
4029
dd4d8ca6
DS		 4030 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4031 pci_wake_from_d3(pdev, true);
4032 else
4033 pci_wake_from_d3(pdev, false);
b3c8b4ba 4034
9d8d05ae
RW		 4035 *enable_wake = !!wufc;
4036
b3c8b4ba
AD		 4037 ixgbe_release_hw_control(adapter);
4038
4039 pci_disable_device(pdev);
4040
9d8d05ae
RW		 4041 return 0;
4042}
4043
4044#ifdef CONFIG_PM
4045static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4046{
4047 int retval;
4048 bool wake;
4049
4050 retval = __ixgbe_shutdown(pdev, &wake);
4051 if (retval)
4052 return retval;
4053
4054 if (wake) {
4055 pci_prepare_to_sleep(pdev);
4056 } else {
4057 pci_wake_from_d3(pdev, false);
4058 pci_set_power_state(pdev, PCI_D3hot);
4059 }
b3c8b4ba
AD		 4060
4061 return 0;
4062}
9d8d05ae 4063#endif /* CONFIG_PM */
b3c8b4ba
AD		 4064
4065static void ixgbe_shutdown(struct pci_dev *pdev)
4066{
9d8d05ae
RW		 4067 bool wake;
4068
4069 __ixgbe_shutdown(pdev, &wake);
4070
4071 if (system_state == SYSTEM_POWER_OFF) {
4072 pci_wake_from_d3(pdev, wake);
4073 pci_set_power_state(pdev, PCI_D3hot);
4074 }
b3c8b4ba
AD		 4075}
4076
9a799d71
AK		 4077/**
4078 * ixgbe_update_stats - Update the board statistics counters.
4079 * @adapter: board private structure
4080 **/
4081void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4082{
4083 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4084 u64 total_mpc = 0;
4085 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4086
d51019a4 4087 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4088 u64 rsc_count = 0;
d51019a4
PW		 4089 for (i = 0; i < 16; i++)
4090 adapter->hw_rx_no_dma_resources +=
4091 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4092 for (i = 0; i < adapter->num_rx_queues; i++)
4093 rsc_count += adapter->rx_ring[i].rsc_count;
4094 adapter->rsc_count = rsc_count;
d51019a4
PW		 4095 }
4096
9a799d71 4097 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4098 for (i = 0; i < 8; i++) {
4099 /* for packet buffers not used, the register should read 0 */
4100 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4101 missed_rx += mpc;
4102 adapter->stats.mpc[i] += mpc;
4103 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4104 if (hw->mac.type == ixgbe_mac_82598EB)
4105 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4106 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4107 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4108 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4109 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4110 if (hw->mac.type == ixgbe_mac_82599EB) {
4111 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4112 IXGBE_PXONRXCNT(i));
4113 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4114 IXGBE_PXOFFRXCNT(i));
4115 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4116 } else {
4117 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4118 IXGBE_PXONRXC(i));
4119 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4120 IXGBE_PXOFFRXC(i));
4121 }
2f90b865
AD		 4122 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4123 IXGBE_PXONTXC(i));
2f90b865 4124 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4125 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4126 }
4127 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4128 /* work around hardware counting issue */
4129 adapter->stats.gprc -= missed_rx;
4130
4131 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 4132 if (hw->mac.type == ixgbe_mac_82599EB) {
4133 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4134 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4135 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4136 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4137 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4138 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4139 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4140 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
6d45522c
YZ		 4141#ifdef IXGBE_FCOE
4142 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4143 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4144 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4145 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4146 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4147 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4148#endif /* IXGBE_FCOE */
e8e26350
PW		 4149 } else {
4150 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4151 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4152 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4153 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4154 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4155 }
9a799d71
AK		 4156 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4157 adapter->stats.bprc += bprc;
4158 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4159 if (hw->mac.type == ixgbe_mac_82598EB)
4160 adapter->stats.mprc -= bprc;
9a799d71
AK		 4161 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4162 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4163 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4164 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4165 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4166 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4167 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4168 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4169 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4170 adapter->stats.lxontxc += lxon;
4171 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4172 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4173 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4174 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4175 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4176 /*
4177 * 82598 errata - tx of flow control packets is included in tx counters
4178 */
4179 xon_off_tot = lxon + lxoff;
4180 adapter->stats.gptc -= xon_off_tot;
4181 adapter->stats.mptc -= xon_off_tot;
4182 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4183 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4184 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4185 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4186 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4187 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4188 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4189 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4190 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4191 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4192 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4193 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4194 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4195
4196 /* Fill out the OS statistics structure */
9a799d71
AK		 4197 adapter->net_stats.multicast = adapter->stats.mprc;
4198
4199 /* Rx Errors */
4200 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4201 adapter->stats.rlec;
9a799d71
AK		 4202 adapter->net_stats.rx_dropped = 0;
4203 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4204 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4205 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4206}
4207
4208/**
4209 * ixgbe_watchdog - Timer Call-back
4210 * @data: pointer to adapter cast into an unsigned long
4211 **/
4212static void ixgbe_watchdog(unsigned long data)
4213{
4214 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 4215 struct ixgbe_hw *hw = &adapter->hw;
4216
4217 /* Do the watchdog outside of interrupt context due to the lovely
4218 * delays that some of the newer hardware requires */
4219 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
22d5a71b
JB		 4220 u64 eics = 0;
4221 int i;
4222
4223 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
c9c7d2e5 4224 eics |= ((u64)1 << i);
22d5a71b 4225
cf8280ee 4226 /* Cause software interrupt to ensure rx rings are cleaned */
22d5a71b
JB		 4227 switch (hw->mac.type) {
4228 case ixgbe_mac_82598EB:
4229 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4230 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4231 } else {
4232 /*
4233 * for legacy and MSI interrupts don't set any
4234 * bits that are enabled for EIAM, because this
4235 * operation would set *both* EIMS and EICS for
4236 * any bit in EIAM
4237 */
4238 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4239 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4240 }
4241 break;
4242 case ixgbe_mac_82599EB:
4243 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
835462fc
NS		 4244 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4245 (u32)(eics & 0xFFFFFFFF));
22d5a71b 4246 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
22d5a71b
JB		 4247 (u32)(eics >> 32));
4248 } else {
4249 /*
4250 * for legacy and MSI interrupts don't set any
4251 * bits that are enabled for EIAM, because this
4252 * operation would set *both* EIMS and EICS for
4253 * any bit in EIAM
4254 */
4255 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4256 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4257 }
4258 break;
4259 default:
4260 break;
cf8280ee
JB		 4261 }
4262 /* Reset the timer */
4263 mod_timer(&adapter->watchdog_timer,
4264 round_jiffies(jiffies + 2 * HZ));
4265 }
9a799d71 4266
cf8280ee
JB		 4267 schedule_work(&adapter->watchdog_task);
4268}
4269
e8e26350
PW		 4270/**
4271 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4272 * @work: pointer to work_struct containing our data
4273 **/
4274static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4275{
4276 struct ixgbe_adapter *adapter = container_of(work,
4277 struct ixgbe_adapter,
4278 multispeed_fiber_task);
4279 struct ixgbe_hw *hw = &adapter->hw;
4280 u32 autoneg;
4281
4282 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4283 if (hw->mac.ops.get_link_capabilities)
4284 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4285 &hw->mac.autoneg);
4286 if (hw->mac.ops.setup_link_speed)
4287 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4288 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4289 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4290}
4291
4292/**
4293 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4294 * @work: pointer to work_struct containing our data
4295 **/
4296static void ixgbe_sfp_config_module_task(struct work_struct *work)
4297{
4298 struct ixgbe_adapter *adapter = container_of(work,
4299 struct ixgbe_adapter,
4300 sfp_config_module_task);
4301 struct ixgbe_hw *hw = &adapter->hw;
4302 u32 err;
4303
4304 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4305 err = hw->phy.ops.identify_sfp(hw);
4306 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4307 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4308 ixgbe_down(adapter);
4309 return;
4310 }
4311 hw->mac.ops.setup_sfp(hw);
4312
8d1c3c07 4313 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4314 /* This will also work for DA Twinax connections */
4315 schedule_work(&adapter->multispeed_fiber_task);
4316 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4317}
4318
cf8280ee 4319/**
69888674
AD		 4320 * ixgbe_watchdog_task - worker thread to bring link up
4321 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4322 **/
4323static void ixgbe_watchdog_task(struct work_struct *work)
4324{
4325 struct ixgbe_adapter *adapter = container_of(work,
4326 struct ixgbe_adapter,
4327 watchdog_task);
4328 struct net_device *netdev = adapter->netdev;
4329 struct ixgbe_hw *hw = &adapter->hw;
4330 u32 link_speed = adapter->link_speed;
4331 bool link_up = adapter->link_up;
bc59fcda
NS		 4332 int i;
4333 struct ixgbe_ring *tx_ring;
4334 int some_tx_pending = 0;
cf8280ee
JB		 4335
4336 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4337
4338 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4339 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4340 if (link_up) {
4341#ifdef CONFIG_DCB
4342 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4343 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4344 hw->mac.ops.setup_fc(hw, i);
4345 } else {
4346 hw->mac.ops.setup_fc(hw, 0);
4347 }
4348#else
4349 hw->mac.ops.setup_fc(hw, 0);
4350#endif
4351 }
4352
cf8280ee
JB		 4353 if (link_up ||
4354 time_after(jiffies, (adapter->link_check_timeout +
4355 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4356 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4357 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4358 }
4359 adapter->link_up = link_up;
4360 adapter->link_speed = link_speed;
4361 }
9a799d71
AK		 4362
4363 if (link_up) {
4364 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4365 bool flow_rx, flow_tx;
4366
4367 if (hw->mac.type == ixgbe_mac_82599EB) {
4368 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4369 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4370 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4371 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4372 } else {
4373 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4374 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4375 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4376 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4377 }
4378
a46e534b
JK		 4379 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4380 "Flow Control: %s\n",
4381 netdev->name,
4382 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4383 "10 Gbps" :
4384 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4385 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4386 ((flow_rx && flow_tx) ? "RX/TX" :
4387 (flow_rx ? "RX" :
4388 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4389
4390 netif_carrier_on(netdev);
9a799d71
AK		 4391 } else {
4392 /* Force detection of hung controller */
4393 adapter->detect_tx_hung = true;
4394 }
4395 } else {
cf8280ee
JB		 4396 adapter->link_up = false;
4397 adapter->link_speed = 0;
9a799d71 4398 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4399 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4400 netdev->name);
9a799d71 4401 netif_carrier_off(netdev);
9a799d71
AK		 4402 }
4403 }
4404
bc59fcda
NS		 4405 if (!netif_carrier_ok(netdev)) {
4406 for (i = 0; i < adapter->num_tx_queues; i++) {
4407 tx_ring = &adapter->tx_ring[i];
4408 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4409 some_tx_pending = 1;
4410 break;
4411 }
4412 }
4413
4414 if (some_tx_pending) {
4415 /* We've lost link, so the controller stops DMA,
4416 * but we've got queued Tx work that's never going
4417 * to get done, so reset controller to flush Tx.
4418 * (Do the reset outside of interrupt context).
4419 */
4420 schedule_work(&adapter->reset_task);
4421 }
4422 }
4423
9a799d71 4424 ixgbe_update_stats(adapter);
cf8280ee 4425 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4426}
4427
9a799d71 4428static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4429 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4430 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4431{
4432 struct ixgbe_adv_tx_context_desc *context_desc;
4433 unsigned int i;
4434 int err;
4435 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4436 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4437 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4438
4439 if (skb_is_gso(skb)) {
4440 if (skb_header_cloned(skb)) {
4441 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4442 if (err)
4443 return err;
4444 }
4445 l4len = tcp_hdrlen(skb);
4446 *hdr_len += l4len;
4447
8327d000 4448 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4449 struct iphdr *iph = ip_hdr(skb);
4450 iph->tot_len = 0;
4451 iph->check = 0;
4452 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4453 iph->daddr, 0,
4454 IPPROTO_TCP,
4455 0);
9a799d71
AK		 4456 adapter->hw_tso_ctxt++;
4457 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4458 ipv6_hdr(skb)->payload_len = 0;
4459 tcp_hdr(skb)->check =
4460 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4461 &ipv6_hdr(skb)->daddr,
4462 0, IPPROTO_TCP, 0);
9a799d71
AK		 4463 adapter->hw_tso6_ctxt++;
4464 }
4465
4466 i = tx_ring->next_to_use;
4467
4468 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4469 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4470
4471 /* VLAN MACLEN IPLEN */
4472 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4473 vlan_macip_lens |=
4474 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4475 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4476 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4477 *hdr_len += skb_network_offset(skb);
4478 vlan_macip_lens |=
4479 (skb_transport_header(skb) - skb_network_header(skb));
4480 *hdr_len +=
4481 (skb_transport_header(skb) - skb_network_header(skb));
4482 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4483 context_desc->seqnum_seed = 0;
4484
4485 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4486 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4487 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4488
8327d000 4489 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4490 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4491 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4492 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4493
4494 /* MSS L4LEN IDX */
9f8cdf4f 4495 mss_l4len_idx =
9a799d71
AK		 4496 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4497 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4498 /* use index 1 for TSO */
4499 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4500 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4501
4502 tx_buffer_info->time_stamp = jiffies;
4503 tx_buffer_info->next_to_watch = i;
4504
4505 i++;
4506 if (i == tx_ring->count)
4507 i = 0;
4508 tx_ring->next_to_use = i;
4509
4510 return true;
4511 }
4512 return false;
4513}
4514
4515static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4516 struct ixgbe_ring *tx_ring,
4517 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4518{
4519 struct ixgbe_adv_tx_context_desc *context_desc;
4520 unsigned int i;
4521 struct ixgbe_tx_buffer *tx_buffer_info;
4522 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4523
4524 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4525 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4526 i = tx_ring->next_to_use;
4527 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4528 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4529
4530 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4531 vlan_macip_lens |=
4532 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4533 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4534 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4535 if (skb->ip_summed == CHECKSUM_PARTIAL)
4536 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4537 skb_network_header(skb));
9a799d71
AK		 4538
4539 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4540 context_desc->seqnum_seed = 0;
4541
4542 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4543 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4544
4545 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4546 switch (skb->protocol) {
09640e63 4547 case cpu_to_be16(ETH_P_IP):
9a799d71 4548 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4549 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4550 type_tucmd_mlhl |=
b4617240 4551 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4552 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4553 type_tucmd_mlhl |=
4554 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4555 break;
09640e63 4556 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4557 /* XXX what about other V6 headers?? */
4558 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4559 type_tucmd_mlhl |=
b4617240 4560 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4561 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4562 type_tucmd_mlhl |=
4563 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4564 break;
41825d71
AK		 4565 default:
4566 if (unlikely(net_ratelimit())) {
4567 DPRINTK(PROBE, WARNING,
4568 "partial checksum but proto=%x!\n",
4569 skb->protocol);
4570 }
4571 break;
4572 }
9a799d71
AK		 4573 }
4574
4575 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4576 /* use index zero for tx checksum offload */
9a799d71
AK		 4577 context_desc->mss_l4len_idx = 0;
4578
4579 tx_buffer_info->time_stamp = jiffies;
4580 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4581
9a799d71
AK		 4582 adapter->hw_csum_tx_good++;
4583 i++;
4584 if (i == tx_ring->count)
4585 i = 0;
4586 tx_ring->next_to_use = i;
4587
4588 return true;
4589 }
9f8cdf4f 4590
9a799d71
AK		 4591 return false;
4592}
4593
4594static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4595 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4596 struct sk_buff *skb, u32 tx_flags,
4597 unsigned int first)
9a799d71
AK		 4598{
4599 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4600 unsigned int len;
4601 unsigned int total = skb->len;
9a799d71
AK		 4602 unsigned int offset = 0, size, count = 0, i;
4603 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4604 unsigned int f;
44df32c5 4605 dma_addr_t *map;
9a799d71
AK		 4606
4607 i = tx_ring->next_to_use;
4608
44df32c5
AD		 4609 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4610 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4611 return 0;
4612 }
4613
4614 map = skb_shinfo(skb)->dma_maps;
4615
eacd73f7
YZ		 4616 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4617 /* excluding fcoe_crc_eof for FCoE */
4618 total -= sizeof(struct fcoe_crc_eof);
4619
4620 len = min(skb_headlen(skb), total);
9a799d71
AK		 4621 while (len) {
4622 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4623 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4624
4625 tx_buffer_info->length = size;
44df32c5 4626 tx_buffer_info->dma = map[0] + offset;
9a799d71
AK		 4627 tx_buffer_info->time_stamp = jiffies;
4628 tx_buffer_info->next_to_watch = i;
4629
4630 len -= size;
eacd73f7 4631 total -= size;
9a799d71
AK		 4632 offset += size;
4633 count++;
44df32c5
AD		 4634
4635 if (len) {
4636 i++;
4637 if (i == tx_ring->count)
4638 i = 0;
4639 }
9a799d71
AK		 4640 }
4641
4642 for (f = 0; f < nr_frags; f++) {
4643 struct skb_frag_struct *frag;
4644
4645 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4646 len = min((unsigned int)frag->size, total);
44df32c5 4647 offset = 0;
9a799d71
AK		 4648
4649 while (len) {
44df32c5
AD		 4650 i++;
4651 if (i == tx_ring->count)
4652 i = 0;
4653
9a799d71
AK		 4654 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4655 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4656
4657 tx_buffer_info->length = size;
44df32c5 4658 tx_buffer_info->dma = map[f + 1] + offset;
9a799d71
AK		 4659 tx_buffer_info->time_stamp = jiffies;
4660 tx_buffer_info->next_to_watch = i;
4661
4662 len -= size;
eacd73f7 4663 total -= size;
9a799d71
AK		 4664 offset += size;
4665 count++;
9a799d71 4666 }
eacd73f7
YZ		 4667 if (total == 0)
4668 break;
9a799d71 4669 }
44df32c5 4670
9a799d71
AK		 4671 tx_ring->tx_buffer_info[i].skb = skb;
4672 tx_ring->tx_buffer_info[first].next_to_watch = i;
4673
4674 return count;
4675}
4676
4677static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4678 struct ixgbe_ring *tx_ring,
4679 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4680{
4681 union ixgbe_adv_tx_desc *tx_desc = NULL;
4682 struct ixgbe_tx_buffer *tx_buffer_info;
4683 u32 olinfo_status = 0, cmd_type_len = 0;
4684 unsigned int i;
4685 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4686
4687 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4688
4689 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4690
4691 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4692 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4693
4694 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4695 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4696
4697 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4698 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4699
4eeae6fd
PW		 4700 /* use index 1 context for tso */
4701 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4702 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4703 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4704 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4705
4706 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4707 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4708 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4709
eacd73f7
YZ		 4710 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4711 olinfo_status |= IXGBE_ADVTXD_CC;
4712 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4713 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4714 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4715 }
4716
9a799d71
AK		 4717 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4718
4719 i = tx_ring->next_to_use;
4720 while (count--) {
4721 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4722 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4723 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4724 tx_desc->read.cmd_type_len =
b4617240 4725 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4726 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4727 i++;
4728 if (i == tx_ring->count)
4729 i = 0;
4730 }
4731
4732 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4733
4734 /*
4735 * Force memory writes to complete before letting h/w
4736 * know there are new descriptors to fetch. (Only
4737 * applicable for weak-ordered memory model archs,
4738 * such as IA-64).
4739 */
4740 wmb();
4741
4742 tx_ring->next_to_use = i;
4743 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4744}
4745
e092be60 4746static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4747 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4748{
4749 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4750
30eba97a 4751 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4752 /* Herbert's original patch had:
4753 * smp_mb__after_netif_stop_queue();
4754 * but since that doesn't exist yet, just open code it. */
4755 smp_mb();
4756
4757 /* We need to check again in a case another CPU has just
4758 * made room available. */
4759 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4760 return -EBUSY;
4761
4762 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4763 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4764 ++adapter->restart_queue;
4765 return 0;
4766}
4767
4768static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4769 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4770{
4771 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4772 return 0;
4773 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4774}
4775
09a3b1f8
SH		 4776static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4777{
4778 struct ixgbe_adapter *adapter = netdev_priv(dev);
4779
4780 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4781 return 0; /* All traffic should default to class 0 */
4782
4783 return skb_tx_hash(dev, skb);
4784}
4785
9a799d71
AK		 4786static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4787{
4788 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4789 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4790 unsigned int first;
4791 unsigned int tx_flags = 0;
30eba97a
AV		 4792 u8 hdr_len = 0;
4793 int r_idx = 0, tso;
9a799d71
AK		 4794 int count = 0;
4795 unsigned int f;
9f8cdf4f 4796
95615d90 4797 r_idx = skb->queue_mapping;
30eba97a 4798 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4799
9f8cdf4f
JB		 4800 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4801 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4802 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4803 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4804 tx_flags |= (skb->queue_mapping << 13);
4805 }
4806 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4807 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4808 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4809 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4810 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4811 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4812 }
eacd73f7
YZ		 4813
4814 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4815 (skb->protocol == htons(ETH_P_FCOE)))
4816 tx_flags |= IXGBE_TX_FLAGS_FCOE;
4817
4818 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 4819 if (skb_is_gso(skb) ||
4820 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 4821 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
4822 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 4823 count++;
4824
9f8cdf4f
JB		 4825 count += TXD_USE_COUNT(skb_headlen(skb));
4826 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4827 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4828
e092be60 4829 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4830 adapter->tx_busy++;
9a799d71
AK		 4831 return NETDEV_TX_BUSY;
4832 }
9a799d71 4833
9a799d71 4834 first = tx_ring->next_to_use;
eacd73f7
YZ		 4835 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4836#ifdef IXGBE_FCOE
4837 /* setup tx offload for FCoE */
4838 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4839 if (tso < 0) {
4840 dev_kfree_skb_any(skb);
4841 return NETDEV_TX_OK;
4842 }
4843 if (tso)
4844 tx_flags |= IXGBE_TX_FLAGS_FSO;
4845#endif /* IXGBE_FCOE */
4846 } else {
4847 if (skb->protocol == htons(ETH_P_IP))
4848 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4849 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4850 if (tso < 0) {
4851 dev_kfree_skb_any(skb);
4852 return NETDEV_TX_OK;
4853 }
9a799d71 4854
eacd73f7
YZ		 4855 if (tso)
4856 tx_flags |= IXGBE_TX_FLAGS_TSO;
4857 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4858 (skb->ip_summed == CHECKSUM_PARTIAL))
4859 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4860 }
9a799d71 4861
eacd73f7 4862 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5
AD		 4863 if (count) {
4864 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4865 hdr_len);
44df32c5 4866 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 4867
44df32c5
AD		 4868 } else {
4869 dev_kfree_skb_any(skb);
4870 tx_ring->tx_buffer_info[first].time_stamp = 0;
4871 tx_ring->next_to_use = first;
4872 }
9a799d71
AK		 4873
4874 return NETDEV_TX_OK;
4875}
4876
4877/**
4878 * ixgbe_get_stats - Get System Network Statistics
4879 * @netdev: network interface device structure
4880 *
4881 * Returns the address of the device statistics structure.
4882 * The statistics are actually updated from the timer callback.
4883 **/
4884static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4885{
4886 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4887
4888 /* only return the current stats */
4889 return &adapter->net_stats;
4890}
4891
4892/**
4893 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4894 * @netdev: network interface device structure
4895 * @p: pointer to an address structure
4896 *
4897 * Returns 0 on success, negative on failure
4898 **/
4899static int ixgbe_set_mac(struct net_device *netdev, void *p)
4900{
4901 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4902 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4903 struct sockaddr *addr = p;
4904
4905 if (!is_valid_ether_addr(addr->sa_data))
4906 return -EADDRNOTAVAIL;
4907
4908 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4909 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4910
b4617240 4911 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4912
4913 return 0;
4914}
4915
6b73e10d
BH		 4916static int
4917ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4918{
4919 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4920 struct ixgbe_hw *hw = &adapter->hw;
4921 u16 value;
4922 int rc;
4923
4924 if (prtad != hw->phy.mdio.prtad)
4925 return -EINVAL;
4926 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4927 if (!rc)
4928 rc = value;
4929 return rc;
4930}
4931
4932static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4933 u16 addr, u16 value)
4934{
4935 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4936 struct ixgbe_hw *hw = &adapter->hw;
4937
4938 if (prtad != hw->phy.mdio.prtad)
4939 return -EINVAL;
4940 return hw->phy.ops.write_reg(hw, addr, devad, value);
4941}
4942
4943static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4944{
4945 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4946
4947 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4948}
4949
0365e6e4
PW		 4950/**
4951 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
4952 * netdev->dev_addr_list
4953 * @netdev: network interface device structure
4954 *
4955 * Returns non-zero on failure
4956 **/
4957static int ixgbe_add_sanmac_netdev(struct net_device *dev)
4958{
4959 int err = 0;
4960 struct ixgbe_adapter *adapter = netdev_priv(dev);
4961 struct ixgbe_mac_info *mac = &adapter->hw.mac;
4962
4963 if (is_valid_ether_addr(mac->san_addr)) {
4964 rtnl_lock();
4965 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4966 rtnl_unlock();
4967 }
4968 return err;
4969}
4970
4971/**
4972 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
4973 * netdev->dev_addr_list
4974 * @netdev: network interface device structure
4975 *
4976 * Returns non-zero on failure
4977 **/
4978static int ixgbe_del_sanmac_netdev(struct net_device *dev)
4979{
4980 int err = 0;
4981 struct ixgbe_adapter *adapter = netdev_priv(dev);
4982 struct ixgbe_mac_info *mac = &adapter->hw.mac;
4983
4984 if (is_valid_ether_addr(mac->san_addr)) {
4985 rtnl_lock();
4986 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4987 rtnl_unlock();
4988 }
4989 return err;
4990}
4991
9a799d71
AK		 4992#ifdef CONFIG_NET_POLL_CONTROLLER
4993/*
4994 * Polling 'interrupt' - used by things like netconsole to send skbs
4995 * without having to re-enable interrupts. It's not called while
4996 * the interrupt routine is executing.
4997 */
4998static void ixgbe_netpoll(struct net_device *netdev)
4999{
5000 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5001
5002 disable_irq(adapter->pdev->irq);
5003 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5004 ixgbe_intr(adapter->pdev->irq, netdev);
5005 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5006 enable_irq(adapter->pdev->irq);
5007}
5008#endif
5009
0edc3527
SH		 5010static const struct net_device_ops ixgbe_netdev_ops = {
5011 .ndo_open = ixgbe_open,
5012 .ndo_stop = ixgbe_close,
00829823 5013 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5014 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5015 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5016 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5017 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5018 .ndo_validate_addr = eth_validate_addr,
5019 .ndo_set_mac_address = ixgbe_set_mac,
5020 .ndo_change_mtu = ixgbe_change_mtu,
5021 .ndo_tx_timeout = ixgbe_tx_timeout,
5022 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5023 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5024 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5025 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5026#ifdef CONFIG_NET_POLL_CONTROLLER
5027 .ndo_poll_controller = ixgbe_netpoll,
5028#endif
332d4a7d
YZ		 5029#ifdef IXGBE_FCOE
5030 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5031 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5032#endif /* IXGBE_FCOE */
0edc3527
SH		 5033};
5034
9a799d71
AK		 5035/**
5036 * ixgbe_probe - Device Initialization Routine
5037 * @pdev: PCI device information struct
5038 * @ent: entry in ixgbe_pci_tbl
5039 *
5040 * Returns 0 on success, negative on failure
5041 *
5042 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5043 * The OS initialization, configuring of the adapter private structure,
5044 * and a hardware reset occur.
5045 **/
5046static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5047 const struct pci_device_id *ent)
9a799d71
AK		 5048{
5049 struct net_device *netdev;
5050 struct ixgbe_adapter *adapter = NULL;
5051 struct ixgbe_hw *hw;
5052 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5053 static int cards_found;
5054 int i, err, pci_using_dac;
eacd73f7
YZ		 5055#ifdef IXGBE_FCOE
5056 u16 device_caps;
5057#endif
c44ade9e 5058 u32 part_num, eec;
9a799d71 5059
9ce77666 5060 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5061 if (err)
5062 return err;
5063
6a35528a
YH		 5064 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5065 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5066 pci_using_dac = 1;
5067 } else {
284901a9 5068 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5069 if (err) {
284901a9 5070 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5071 if (err) {
b4617240
PW		 5072 dev_err(&pdev->dev, "No usable DMA "
5073 "configuration, aborting\n");
9a799d71
AK		 5074 goto err_dma;
5075 }
5076 }
5077 pci_using_dac = 0;
5078 }
5079
9ce77666 5080 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5081 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5082 if (err) {
9ce77666 5083 dev_err(&pdev->dev,
5084 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5085 goto err_pci_reg;
5086 }
5087
6fabd715
PWJ		 5088 err = pci_enable_pcie_error_reporting(pdev);
5089 if (err) {
5090 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5091 "0x%x\n", err);
5092 /* non-fatal, continue */
5093 }
5094
9a799d71 5095 pci_set_master(pdev);
fb3b27bc 5096 pci_save_state(pdev);
9a799d71 5097
30eba97a 5098 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5099 if (!netdev) {
5100 err = -ENOMEM;
5101 goto err_alloc_etherdev;
5102 }
5103
9a799d71
AK		 5104 SET_NETDEV_DEV(netdev, &pdev->dev);
5105
5106 pci_set_drvdata(pdev, netdev);
5107 adapter = netdev_priv(netdev);
5108
5109 adapter->netdev = netdev;
5110 adapter->pdev = pdev;
5111 hw = &adapter->hw;
5112 hw->back = adapter;
5113 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5114
05857980
JK		 5115 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5116 pci_resource_len(pdev, 0));
9a799d71
AK		 5117 if (!hw->hw_addr) {
5118 err = -EIO;
5119 goto err_ioremap;
5120 }
5121
5122 for (i = 1; i <= 5; i++) {
5123 if (pci_resource_len(pdev, i) == 0)
5124 continue;
5125 }
5126
0edc3527 5127 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5128 ixgbe_set_ethtool_ops(netdev);
9a799d71 5129 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5130 strcpy(netdev->name, pci_name(pdev));
5131
9a799d71
AK		 5132 adapter->bd_number = cards_found;
5133
9a799d71
AK		 5134 /* Setup hw api */
5135 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5136 hw->mac.type = ii->mac;
9a799d71 5137
c44ade9e
JB		 5138 /* EEPROM */
5139 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5140 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5141 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5142 if (!(eec & (1 << 8)))
5143 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5144
5145 /* PHY */
5146 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5147 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5148 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5149 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5150 hw->phy.mdio.mmds = 0;
5151 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5152 hw->phy.mdio.dev = netdev;
5153 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5154 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5155
5156 /* set up this timer and work struct before calling get_invariants
5157 * which might start the timer
5158 */
5159 init_timer(&adapter->sfp_timer);
5160 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5161 adapter->sfp_timer.data = (unsigned long) adapter;
5162
5163 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5164
e8e26350
PW		 5165 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5166 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5167
5168 /* a new SFP+ module arrival, called from GPI SDP2 context */
5169 INIT_WORK(&adapter->sfp_config_module_task,
5170 ixgbe_sfp_config_module_task);
5171
8ca783ab 5172 ii->get_invariants(hw);
9a799d71
AK		 5173
5174 /* setup the private structure */
5175 err = ixgbe_sw_init(adapter);
5176 if (err)
5177 goto err_sw_init;
5178
bf069c97
DS		 5179 /*
5180 * If there is a fan on this device and it has failed log the
5181 * failure.
5182 */
5183 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5184 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5185 if (esdp & IXGBE_ESDP_SDP1)
5186 DPRINTK(PROBE, CRIT,
5187 "Fan has stopped, replace the adapter\n");
5188 }
5189
c44ade9e
JB		 5190 /* reset_hw fills in the perm_addr as well */
5191 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5192 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5193 hw->mac.type == ixgbe_mac_82598EB) {
5194 /*
5195 * Start a kernel thread to watch for a module to arrive.
5196 * Only do this for 82598, since 82599 will generate
5197 * interrupts on module arrival.
5198 */
5199 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5200 mod_timer(&adapter->sfp_timer,
5201 round_jiffies(jiffies + (2 * HZ)));
5202 err = 0;
5203 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
04f165ef
PW		 5204 dev_err(&adapter->pdev->dev, "failed to load because an "
5205 "unsupported SFP+ module type was detected.\n");
5206 goto err_sw_init;
5207 } else if (err) {
c44ade9e
JB		 5208 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5209 goto err_sw_init;
5210 }
5211
9a799d71 5212 netdev->features = NETIF_F_SG |
b4617240
PW		 5213 NETIF_F_IP_CSUM |
5214 NETIF_F_HW_VLAN_TX |
5215 NETIF_F_HW_VLAN_RX |
5216 NETIF_F_HW_VLAN_FILTER;
9a799d71 5217
e9990a9c 5218 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5219 netdev->features |= NETIF_F_TSO;
9a799d71 5220 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5221 netdev->features |= NETIF_F_GRO;
ad31c402 5222
45a5ead0
JB		 5223 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5224 netdev->features |= NETIF_F_SCTP_CSUM;
5225
ad31c402
JK		 5226 netdev->vlan_features |= NETIF_F_TSO;
5227 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5228 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 5229 netdev->vlan_features |= NETIF_F_SG;
5230
2f90b865
AD		 5231 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5232 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5233
7a6b6f51 5234#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5235 netdev->dcbnl_ops = &dcbnl_ops;
5236#endif
5237
eacd73f7
YZ		 5238#ifdef IXGBE_FCOE
5239 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5240 if (hw->mac.ops.get_device_caps) {
5241 hw->mac.ops.get_device_caps(hw, &device_caps);
5242 if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5243 netdev->features |= NETIF_F_FCOE_CRC;
5244 netdev->features |= NETIF_F_FSO;
332d4a7d 5245 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
eacd73f7
YZ		 5246 } else {
5247 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5248 }
5249 }
5250 }
5251#endif /* IXGBE_FCOE */
9a799d71
AK		 5252 if (pci_using_dac)
5253 netdev->features |= NETIF_F_HIGHDMA;
5254
f8212f97
AD		 5255 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
5256 netdev->features |= NETIF_F_LRO;
5257
9a799d71 5258 /* make sure the EEPROM is good */
c44ade9e 5259 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5260 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5261 err = -EIO;
5262 goto err_eeprom;
5263 }
5264
5265 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5266 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5267
c44ade9e
JB		 5268 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5269 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5270 err = -EIO;
5271 goto err_eeprom;
5272 }
5273
5274 init_timer(&adapter->watchdog_timer);
5275 adapter->watchdog_timer.function = &ixgbe_watchdog;
5276 adapter->watchdog_timer.data = (unsigned long)adapter;
5277
5278 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5279 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5280
021230d4
AV		 5281 err = ixgbe_init_interrupt_scheme(adapter);
5282 if (err)
5283 goto err_sw_init;
9a799d71 5284
e8e26350
PW		 5285 switch (pdev->device) {
5286 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5287 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5288 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 5289 break;
5290 default:
5291 adapter->wol = 0;
5292 break;
5293 }
5294 device_init_wakeup(&adapter->pdev->dev, true);
5295 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5296
04f165ef
PW		 5297 /* pick up the PCI bus settings for reporting later */
5298 hw->mac.ops.get_bus_info(hw);
5299
9a799d71 5300 /* print bus type/speed/width info */
7c510e4b 5301 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5302 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5303 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5304 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5305 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5306 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5307 "Unknown"),
7c510e4b 5308 netdev->dev_addr);
c44ade9e 5309 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5310 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5311 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5312 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5313 (part_num >> 8), (part_num & 0xff));
5314 else
5315 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5316 hw->mac.type, hw->phy.type,
5317 (part_num >> 8), (part_num & 0xff));
9a799d71 5318
e8e26350 5319 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5320 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5321 "this card is not sufficient for optimal "
5322 "performance.\n");
0c254d86 5323 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5324 "PCI-Express slot is required.\n");
0c254d86
AK		 5325 }
5326
34b0368c
PWJ		 5327 /* save off EEPROM version number */
5328 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5329
9a799d71 5330 /* reset the hardware with the new settings */
c44ade9e
JB		 5331 hw->mac.ops.start_hw(hw);
5332
9a799d71
AK		 5333 strcpy(netdev->name, "eth%d");
5334 err = register_netdev(netdev);
5335 if (err)
5336 goto err_register;
5337
54386467
JB		 5338 /* carrier off reporting is important to ethtool even BEFORE open */
5339 netif_carrier_off(netdev);
5340
5dd2d332 5341#ifdef CONFIG_IXGBE_DCA
652f093f 5342 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5343 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5344 ixgbe_setup_dca(adapter);
5345 }
5346#endif
0365e6e4
PW		 5347 /* add san mac addr to netdev */
5348 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5349
5350 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5351 cards_found++;
5352 return 0;
5353
5354err_register:
5eba3699 5355 ixgbe_release_hw_control(adapter);
7a921c93 5356 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5357err_sw_init:
5358err_eeprom:
c4900be0
DS		 5359 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5360 del_timer_sync(&adapter->sfp_timer);
5361 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5362 cancel_work_sync(&adapter->multispeed_fiber_task);
5363 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5364 iounmap(hw->hw_addr);
5365err_ioremap:
5366 free_netdev(netdev);
5367err_alloc_etherdev:
9ce77666 5368 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5369 IORESOURCE_MEM));
9a799d71
AK		 5370err_pci_reg:
5371err_dma:
5372 pci_disable_device(pdev);
5373 return err;
5374}
5375
5376/**
5377 * ixgbe_remove - Device Removal Routine
5378 * @pdev: PCI device information struct
5379 *
5380 * ixgbe_remove is called by the PCI subsystem to alert the driver
5381 * that it should release a PCI device. The could be caused by a
5382 * Hot-Plug event, or because the driver is going to be removed from
5383 * memory.
5384 **/
5385static void __devexit ixgbe_remove(struct pci_dev *pdev)
5386{
5387 struct net_device *netdev = pci_get_drvdata(pdev);
5388 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5389 int err;
9a799d71
AK		 5390
5391 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5392 /* clear the module not found bit to make sure the worker won't
5393 * reschedule
5394 */
5395 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5396 del_timer_sync(&adapter->watchdog_timer);
5397
c4900be0
DS		 5398 del_timer_sync(&adapter->sfp_timer);
5399 cancel_work_sync(&adapter->watchdog_task);
5400 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5401 cancel_work_sync(&adapter->multispeed_fiber_task);
5402 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5403 flush_scheduled_work();
5404
5dd2d332 5405#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5406 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5407 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5408 dca_remove_requester(&pdev->dev);
5409 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5410 }
5411
5412#endif
332d4a7d
YZ		 5413#ifdef IXGBE_FCOE
5414 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5415 ixgbe_cleanup_fcoe(adapter);
5416
5417#endif /* IXGBE_FCOE */
0365e6e4
PW		 5418
5419 /* remove the added san mac */
5420 ixgbe_del_sanmac_netdev(netdev);
5421
c4900be0
DS		 5422 if (netdev->reg_state == NETREG_REGISTERED)
5423 unregister_netdev(netdev);
9a799d71 5424
7a921c93 5425 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5426
021230d4 5427 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5428
5429 iounmap(adapter->hw.hw_addr);
9ce77666 5430 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5431 IORESOURCE_MEM));
9a799d71 5432
021230d4 5433 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5434
9a799d71
AK		 5435 free_netdev(netdev);
5436
6fabd715
PWJ		 5437 err = pci_disable_pcie_error_reporting(pdev);
5438 if (err)
5439 dev_err(&pdev->dev,
5440 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5441
9a799d71
AK		 5442 pci_disable_device(pdev);
5443}
5444
5445/**
5446 * ixgbe_io_error_detected - called when PCI error is detected
5447 * @pdev: Pointer to PCI device
5448 * @state: The current pci connection state
5449 *
5450 * This function is called after a PCI bus error affecting
5451 * this device has been detected.
5452 */
5453static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5454 pci_channel_state_t state)
9a799d71
AK		 5455{
5456 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5458
5459 netif_device_detach(netdev);
5460
3044b8d1
BL		 5461 if (state == pci_channel_io_perm_failure)
5462 return PCI_ERS_RESULT_DISCONNECT;
5463
9a799d71
AK		 5464 if (netif_running(netdev))
5465 ixgbe_down(adapter);
5466 pci_disable_device(pdev);
5467
b4617240 5468 /* Request a slot reset. */
9a799d71
AK		 5469 return PCI_ERS_RESULT_NEED_RESET;
5470}
5471
5472/**
5473 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5474 * @pdev: Pointer to PCI device
5475 *
5476 * Restart the card from scratch, as if from a cold-boot.
5477 */
5478static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5479{
5480 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5481 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5482 pci_ers_result_t result;
5483 int err;
9a799d71 5484
9ce77666 5485 if (pci_enable_device_mem(pdev)) {
9a799d71 5486 DPRINTK(PROBE, ERR,
b4617240 5487 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5488 result = PCI_ERS_RESULT_DISCONNECT;
5489 } else {
5490 pci_set_master(pdev);
5491 pci_restore_state(pdev);
9a799d71 5492
dd4d8ca6 5493 pci_wake_from_d3(pdev, false);
9a799d71 5494
6fabd715 5495 ixgbe_reset(adapter);
88512539 5496 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5497 result = PCI_ERS_RESULT_RECOVERED;
5498 }
5499
5500 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5501 if (err) {
5502 dev_err(&pdev->dev,
5503 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5504 /* non-fatal, continue */
5505 }
9a799d71 5506
6fabd715 5507 return result;
9a799d71
AK		 5508}
5509
5510/**
5511 * ixgbe_io_resume - called when traffic can start flowing again.
5512 * @pdev: Pointer to PCI device
5513 *
5514 * This callback is called when the error recovery driver tells us that
5515 * its OK to resume normal operation.
5516 */
5517static void ixgbe_io_resume(struct pci_dev *pdev)
5518{
5519 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5520 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5521
5522 if (netif_running(netdev)) {
5523 if (ixgbe_up(adapter)) {
5524 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5525 return;
5526 }
5527 }
5528
5529 netif_device_attach(netdev);
9a799d71
AK		 5530}
5531
5532static struct pci_error_handlers ixgbe_err_handler = {
5533 .error_detected = ixgbe_io_error_detected,
5534 .slot_reset = ixgbe_io_slot_reset,
5535 .resume = ixgbe_io_resume,
5536};
5537
5538static struct pci_driver ixgbe_driver = {
5539 .name = ixgbe_driver_name,
5540 .id_table = ixgbe_pci_tbl,
5541 .probe = ixgbe_probe,
5542 .remove = __devexit_p(ixgbe_remove),
5543#ifdef CONFIG_PM
5544 .suspend = ixgbe_suspend,
5545 .resume = ixgbe_resume,
5546#endif
5547 .shutdown = ixgbe_shutdown,
5548 .err_handler = &ixgbe_err_handler
5549};
5550
5551/**
5552 * ixgbe_init_module - Driver Registration Routine
5553 *
5554 * ixgbe_init_module is the first routine called when the driver is
5555 * loaded. All it does is register with the PCI subsystem.
5556 **/
5557static int __init ixgbe_init_module(void)
5558{
5559 int ret;
5560 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5561 ixgbe_driver_string, ixgbe_driver_version);
5562
5563 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5564
5dd2d332 5565#ifdef CONFIG_IXGBE_DCA
bd0362dd 5566 dca_register_notify(&dca_notifier);
bd0362dd 5567#endif
5dd2d332 5568
9a799d71
AK		 5569 ret = pci_register_driver(&ixgbe_driver);
5570 return ret;
5571}
b4617240 5572
9a799d71
AK		 5573module_init(ixgbe_init_module);
5574
5575/**
5576 * ixgbe_exit_module - Driver Exit Cleanup Routine
5577 *
5578 * ixgbe_exit_module is called just before the driver is removed
5579 * from memory.
5580 **/
5581static void __exit ixgbe_exit_module(void)
5582{
5dd2d332 5583#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5584 dca_unregister_notify(&dca_notifier);
5585#endif
9a799d71
AK		 5586 pci_unregister_driver(&ixgbe_driver);
5587}
bd0362dd 5588
5dd2d332 5589#ifdef CONFIG_IXGBE_DCA
bd0362dd 5590static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5591 void *p)
bd0362dd
JC		 5592{
5593 int ret_val;
5594
5595 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5596 __ixgbe_notify_dca);
bd0362dd
JC		 5597
5598 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5599}
b453368d 5600
5dd2d332 5601#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5602#ifdef DEBUG
5603/**
5604 * ixgbe_get_hw_dev_name - return device name string
5605 * used by hardware layer to print debugging information
5606 **/
5607char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5608{
5609 struct ixgbe_adapter *adapter = hw->back;
5610 return adapter->netdev->name;
5611}
bd0362dd 5612
b453368d 5613#endif
9a799d71
AK		 5614module_exit(ixgbe_exit_module);
5615
5616/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree