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ixgbe: Distribute transmission of FCoE traffic in 82599
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
47
48char ixgbe_driver_name[] = "ixgbe";
9c8eb720 49static const char ixgbe_driver_string[] =
b4617240 50 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 51
bbf50e4d 52#define DRV_VERSION "2.0.37-k2"
9c8eb720 53const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 54static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 57 [board_82598] = &ixgbe_82598_info,
e8e26350 58 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 59};
60
61/* ixgbe_pci_tbl - PCI Device ID Table
62 *
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 73 board_82598 },
9a799d71 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 75 board_82598 },
0befdb3e
JB		 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
77 board_82598 },
3845bec0
PWJ		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
79 board_82598 },
9a799d71 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 81 board_82598 },
8d792cd9
JB		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
83 board_82598 },
c4900be0
DS		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
87 board_82598 },
b95f5fcb
JB		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
89 board_82598 },
c4900be0
DS		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
91 board_82598 },
2f21bdd3
DS		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
93 board_82598 },
e8e26350
PW		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
95 board_82599 },
1fcf03e6
PWJ		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
97 board_82599 },
e8e26350
PW		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
99 board_82599 },
9a799d71
AK		 100
101 /* required last entry */
102 {0, }
103};
104MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
105
5dd2d332 106#ifdef CONFIG_IXGBE_DCA
bd0362dd 107static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 108 void *p);
bd0362dd
JC		 109static struct notifier_block dca_notifier = {
110 .notifier_call = ixgbe_notify_dca,
111 .next = NULL,
112 .priority = 0
113};
114#endif
115
9a799d71
AK		 116MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
117MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
118MODULE_LICENSE("GPL");
119MODULE_VERSION(DRV_VERSION);
120
121#define DEFAULT_DEBUG_LEVEL_SHIFT 3
122
5eba3699
AV		 123static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
124{
125 u32 ctrl_ext;
126
127 /* Let firmware take over control of h/w */
128 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
129 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 130 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 131}
132
133static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
134{
135 u32 ctrl_ext;
136
137 /* Let firmware know the driver has taken over */
138 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
139 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 140 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 141}
9a799d71 142
e8e26350
PW		 143/*
144 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
145 * @adapter: pointer to adapter struct
146 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
147 * @queue: queue to map the corresponding interrupt to
148 * @msix_vector: the vector to map to the corresponding queue
149 *
150 */
151static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
152 u8 queue, u8 msix_vector)
9a799d71
AK		 153{
154 u32 ivar, index;
e8e26350
PW		 155 struct ixgbe_hw *hw = &adapter->hw;
156 switch (hw->mac.type) {
157 case ixgbe_mac_82598EB:
158 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
159 if (direction == -1)
160 direction = 0;
161 index = (((direction * 64) + queue) >> 2) & 0x1F;
162 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
163 ivar &= ~(0xFF << (8 * (queue & 0x3)));
164 ivar |= (msix_vector << (8 * (queue & 0x3)));
165 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
166 break;
167 case ixgbe_mac_82599EB:
168 if (direction == -1) {
169 /* other causes */
170 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
171 index = ((queue & 1) * 8);
172 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
173 ivar &= ~(0xFF << index);
174 ivar |= (msix_vector << index);
175 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
176 break;
177 } else {
178 /* tx or rx causes */
179 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
180 index = ((16 * (queue & 1)) + (8 * direction));
181 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
182 ivar &= ~(0xFF << index);
183 ivar |= (msix_vector << index);
184 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
185 break;
186 }
187 default:
188 break;
189 }
9a799d71
AK		 190}
191
fe49f04a
AD		 192static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
193 u64 qmask)
194{
195 u32 mask;
196
197 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
198 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
200 } else {
201 mask = (qmask & 0xFFFFFFFF);
202 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
203 mask = (qmask >> 32);
204 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
205 }
206}
207
9a799d71 208static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 209 struct ixgbe_tx_buffer
210 *tx_buffer_info)
9a799d71 211{
44df32c5 212 tx_buffer_info->dma = 0;
9a799d71 213 if (tx_buffer_info->skb) {
44df32c5
AD		 214 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
215 DMA_TO_DEVICE);
9a799d71
AK		 216 dev_kfree_skb_any(tx_buffer_info->skb);
217 tx_buffer_info->skb = NULL;
218 }
44df32c5 219 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 220 /* tx_buffer_info must be completely set up in the transmit path */
221}
222
223static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 224 struct ixgbe_ring *tx_ring,
225 unsigned int eop)
9a799d71 226{
e01c31a5 227 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 228
9a799d71 229 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 230 * check with the clearing of time_stamp and movement of eop */
9a799d71 231 adapter->detect_tx_hung = false;
44df32c5 232 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 233 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
234 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
235 /* detected Tx unit hang */
e01c31a5
JB		 236 union ixgbe_adv_tx_desc *tx_desc;
237 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 238 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 239 " Tx Queue <%d>\n"
240 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 241 " next_to_use <%x>\n"
242 " next_to_clean <%x>\n"
243 "tx_buffer_info[next_to_clean]\n"
244 " time_stamp <%lx>\n"
e01c31a5
JB		 245 " jiffies <%lx>\n",
246 tx_ring->queue_index,
44df32c5
AD		 247 IXGBE_READ_REG(hw, tx_ring->head),
248 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 249 tx_ring->next_to_use, eop,
250 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 251 return true;
252 }
253
254 return false;
255}
256
b4617240
PW		 257#define IXGBE_MAX_TXD_PWR 14
258#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 259
260/* Tx Descriptors needed, worst case */
261#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
262 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
263#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 264 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 265
e01c31a5
JB		 266static void ixgbe_tx_timeout(struct net_device *netdev);
267
9a799d71
AK		 268/**
269 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 270 * @q_vector: structure containing interrupt and ring information
e01c31a5 271 * @tx_ring: tx ring to clean
9a799d71 272 **/
fe49f04a 273static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 274 struct ixgbe_ring *tx_ring)
9a799d71 275{
fe49f04a 276 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 277 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 278 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
279 struct ixgbe_tx_buffer *tx_buffer_info;
280 unsigned int i, eop, count = 0;
e01c31a5 281 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 282
283 i = tx_ring->next_to_clean;
12207e49
PWJ		 284 eop = tx_ring->tx_buffer_info[i].next_to_watch;
285 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
286
287 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 288 (count < tx_ring->work_limit)) {
12207e49
PWJ		 289 bool cleaned = false;
290 for ( ; !cleaned; count++) {
291 struct sk_buff *skb;
9a799d71
AK		 292 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
293 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 294 cleaned = (i == eop);
e01c31a5 295 skb = tx_buffer_info->skb;
9a799d71 296
12207e49 297 if (cleaned && skb) {
e092be60 298 unsigned int segs, bytecount;
3d8fd385 299 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 300
301 /* gso_segs is currently only valid for tcp */
e092be60 302 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 303#ifdef IXGBE_FCOE
304 /* adjust for FCoE Sequence Offload */
305 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
306 && (skb->protocol == htons(ETH_P_FCOE)) &&
307 skb_is_gso(skb)) {
308 hlen = skb_transport_offset(skb) +
309 sizeof(struct fc_frame_header) +
310 sizeof(struct fcoe_crc_eof);
311 segs = DIV_ROUND_UP(skb->len - hlen,
312 skb_shinfo(skb)->gso_size);
313 }
314#endif /* IXGBE_FCOE */
e092be60 315 /* multiply data chunks by size of headers */
3d8fd385 316 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 317 total_packets += segs;
318 total_bytes += bytecount;
e092be60 319 }
e01c31a5 320
9a799d71 321 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 322 tx_buffer_info);
9a799d71 323
12207e49
PWJ		 324 tx_desc->wb.status = 0;
325
9a799d71
AK		 326 i++;
327 if (i == tx_ring->count)
328 i = 0;
e01c31a5 329 }
12207e49
PWJ		 330
331 eop = tx_ring->tx_buffer_info[i].next_to_watch;
332 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
333 }
334
9a799d71
AK		 335 tx_ring->next_to_clean = i;
336
e092be60 337#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 338 if (unlikely(count && netif_carrier_ok(netdev) &&
339 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 340 /* Make sure that anybody stopping the queue after this
341 * sees the new next_to_clean.
342 */
343 smp_mb();
30eba97a
AV		 344 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
345 !test_bit(__IXGBE_DOWN, &adapter->state)) {
346 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 347 ++adapter->restart_queue;
30eba97a 348 }
e092be60 349 }
9a799d71 350
e01c31a5
JB		 351 if (adapter->detect_tx_hung) {
352 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
353 /* schedule immediate reset if we believe we hung */
354 DPRINTK(PROBE, INFO,
355 "tx hang %d detected, resetting adapter\n",
356 adapter->tx_timeout_count + 1);
357 ixgbe_tx_timeout(adapter->netdev);
358 }
359 }
9a799d71 360
e01c31a5 361 /* re-arm the interrupt */
fe49f04a
AD		 362 if (count >= tx_ring->work_limit)
363 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 364
e01c31a5
JB		 365 tx_ring->total_bytes += total_bytes;
366 tx_ring->total_packets += total_packets;
e01c31a5 367 tx_ring->stats.packets += total_packets;
12207e49 368 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 369 adapter->net_stats.tx_bytes += total_bytes;
370 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 371 return (count < tx_ring->work_limit);
9a799d71
AK		 372}
373
5dd2d332 374#ifdef CONFIG_IXGBE_DCA
bd0362dd 375static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 376 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 377{
378 u32 rxctrl;
379 int cpu = get_cpu();
3a581073 380 int q = rx_ring - adapter->rx_ring;
bd0362dd 381
3a581073 382 if (rx_ring->cpu != cpu) {
bd0362dd 383 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 384 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
385 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
386 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
387 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
388 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
389 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
390 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
391 }
bd0362dd
JC		 392 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
393 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 394 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
395 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 396 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 398 rx_ring->cpu = cpu;
bd0362dd
JC		 399 }
400 put_cpu();
401}
402
403static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 404 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 405{
406 u32 txctrl;
407 int cpu = get_cpu();
3a581073 408 int q = tx_ring - adapter->tx_ring;
bd0362dd 409
3a581073 410 if (tx_ring->cpu != cpu) {
bd0362dd 411 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 412 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
413 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
414 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
415 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
416 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
417 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
418 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
419 }
bd0362dd
JC		 420 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 422 tx_ring->cpu = cpu;
bd0362dd
JC		 423 }
424 put_cpu();
425}
426
427static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
428{
429 int i;
430
431 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
432 return;
433
e35ec126
AD		 434 /* always use CB2 mode, difference is masked in the CB driver */
435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
436
bd0362dd
JC		 437 for (i = 0; i < adapter->num_tx_queues; i++) {
438 adapter->tx_ring[i].cpu = -1;
439 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
440 }
441 for (i = 0; i < adapter->num_rx_queues; i++) {
442 adapter->rx_ring[i].cpu = -1;
443 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
444 }
445}
446
447static int __ixgbe_notify_dca(struct device *dev, void *data)
448{
449 struct net_device *netdev = dev_get_drvdata(dev);
450 struct ixgbe_adapter *adapter = netdev_priv(netdev);
451 unsigned long event = *(unsigned long *)data;
452
453 switch (event) {
454 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 455 /* if we're already enabled, don't do it again */
456 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
457 break;
652f093f 458 if (dca_add_requester(dev) == 0) {
96b0e0f6 459 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 460 ixgbe_setup_dca(adapter);
461 break;
462 }
463 /* Fall Through since DCA is disabled. */
464 case DCA_PROVIDER_REMOVE:
465 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
466 dca_remove_requester(dev);
467 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
469 }
470 break;
471 }
472
652f093f 473 return 0;
bd0362dd
JC		 474}
475
5dd2d332 476#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 477/**
478 * ixgbe_receive_skb - Send a completed packet up the stack
479 * @adapter: board private structure
480 * @skb: packet to send up
177db6ff
MC		 481 * @status: hardware indication of status of receive
482 * @rx_ring: rx descriptor ring (for a specific queue) to setup
483 * @rx_desc: rx descriptor
9a799d71 484 **/
78b6f4ce 485static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 486 struct sk_buff *skb, u8 status,
fdaff1ce 487 struct ixgbe_ring *ring,
177db6ff 488 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 489{
78b6f4ce
HX		 490 struct ixgbe_adapter *adapter = q_vector->adapter;
491 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 492 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
493 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 494
fdaff1ce 495 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 496 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 497 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 498 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 499 else
78b6f4ce 500 napi_gro_receive(napi, skb);
177db6ff 501 } else {
8a62babf 502 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 503 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
504 else
505 netif_rx(skb);
9a799d71
AK		 506 }
507}
508
e59bd25d
AV		 509/**
510 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
511 * @adapter: address of board private structure
512 * @status_err: hardware indication of status of receive
513 * @skb: skb currently being received and modified
514 **/
9a799d71 515static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 516 union ixgbe_adv_rx_desc *rx_desc,
517 struct sk_buff *skb)
9a799d71 518{
8bae1b2b
DS		 519 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
520
9a799d71
AK		 521 skb->ip_summed = CHECKSUM_NONE;
522
712744be
JB		 523 /* Rx csum disabled */
524 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 525 return;
e59bd25d
AV		 526
527 /* if IP and error */
528 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
529 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 530 adapter->hw_csum_rx_error++;
531 return;
532 }
e59bd25d
AV		 533
534 if (!(status_err & IXGBE_RXD_STAT_L4CS))
535 return;
536
537 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 538 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
539
540 /*
541 * 82599 errata, UDP frames with a 0 checksum can be marked as
542 * checksum errors.
543 */
544 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
545 (adapter->hw.mac.type == ixgbe_mac_82599EB))
546 return;
547
e59bd25d
AV		 548 adapter->hw_csum_rx_error++;
549 return;
550 }
551
9a799d71 552 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 553 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 554 adapter->hw_csum_rx_good++;
555}
556
e8e26350
PW		 557static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
558 struct ixgbe_ring *rx_ring, u32 val)
559{
560 /*
561 * Force memory writes to complete before letting h/w
562 * know there are new descriptors to fetch. (Only
563 * applicable for weak-ordered memory model archs,
564 * such as IA-64).
565 */
566 wmb();
567 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
568}
569
9a799d71
AK		 570/**
571 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
572 * @adapter: address of board private structure
573 **/
574static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 575 struct ixgbe_ring *rx_ring,
576 int cleaned_count)
9a799d71 577{
9a799d71
AK		 578 struct pci_dev *pdev = adapter->pdev;
579 union ixgbe_adv_rx_desc *rx_desc;
3a581073 580 struct ixgbe_rx_buffer *bi;
9a799d71 581 unsigned int i;
9a799d71
AK		 582
583 i = rx_ring->next_to_use;
3a581073 584 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 585
586 while (cleaned_count--) {
587 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
588
762f4c57 589 if (!bi->page_dma &&
6e455b89 590 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 591 if (!bi->page) {
762f4c57
JB		 592 bi->page = alloc_page(GFP_ATOMIC);
593 if (!bi->page) {
594 adapter->alloc_rx_page_failed++;
595 goto no_buffers;
596 }
597 bi->page_offset = 0;
598 } else {
599 /* use a half page if we're re-using */
600 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 601 }
762f4c57
JB		 602
603 bi->page_dma = pci_map_page(pdev, bi->page,
604 bi->page_offset,
605 (PAGE_SIZE / 2),
606 PCI_DMA_FROMDEVICE);
9a799d71
AK		 607 }
608
3a581073 609 if (!bi->skb) {
5ecc3614 610 struct sk_buff *skb;
4f57ca6e
JB		 611 skb = netdev_alloc_skb(adapter->netdev,
612 (rx_ring->rx_buf_len +
613 NET_IP_ALIGN));
9a799d71
AK		 614
615 if (!skb) {
616 adapter->alloc_rx_buff_failed++;
617 goto no_buffers;
618 }
619
620 /*
621 * Make buffer alignment 2 beyond a 16 byte boundary
622 * this will result in a 16 byte aligned IP header after
623 * the 14 byte MAC header is removed
624 */
625 skb_reserve(skb, NET_IP_ALIGN);
626
3a581073 627 bi->skb = skb;
4f57ca6e
JB		 628 bi->dma = pci_map_single(pdev, skb->data,
629 rx_ring->rx_buf_len,
3a581073 630 PCI_DMA_FROMDEVICE);
9a799d71
AK		 631 }
632 /* Refresh the desc even if buffer_addrs didn't change because
633 * each write-back erases this info. */
6e455b89 634 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 635 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
636 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 637 } else {
3a581073 638 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 639 }
640
641 i++;
642 if (i == rx_ring->count)
643 i = 0;
3a581073 644 bi = &rx_ring->rx_buffer_info[i];
9a799d71 645 }
7c6e0a43 646
9a799d71
AK		 647no_buffers:
648 if (rx_ring->next_to_use != i) {
649 rx_ring->next_to_use = i;
650 if (i-- == 0)
651 i = (rx_ring->count - 1);
652
e8e26350 653 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 654 }
655}
656
7c6e0a43
JB		 657static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
658{
659 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
660}
661
662static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
663{
664 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
665}
666
f8212f97
AD		 667static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
668{
669 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
670 IXGBE_RXDADV_RSCCNT_MASK) >>
671 IXGBE_RXDADV_RSCCNT_SHIFT;
672}
673
674/**
675 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
676 * @skb: pointer to the last skb in the rsc queue
677 *
678 * This function changes a queue full of hw rsc buffers into a completed
679 * packet. It uses the ->prev pointers to find the first packet and then
680 * turns it into the frag list owner.
681 **/
682static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
683{
684 unsigned int frag_list_size = 0;
685
686 while (skb->prev) {
687 struct sk_buff *prev = skb->prev;
688 frag_list_size += skb->len;
689 skb->prev = NULL;
690 skb = prev;
691 }
692
693 skb_shinfo(skb)->frag_list = skb->next;
694 skb->next = NULL;
695 skb->len += frag_list_size;
696 skb->data_len += frag_list_size;
697 skb->truesize += frag_list_size;
698 return skb;
699}
700
78b6f4ce 701static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 702 struct ixgbe_ring *rx_ring,
703 int *work_done, int work_to_do)
9a799d71 704{
78b6f4ce 705 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 706 struct pci_dev *pdev = adapter->pdev;
707 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
708 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
709 struct sk_buff *skb;
f8212f97 710 unsigned int i, rsc_count = 0;
7c6e0a43 711 u32 len, staterr;
177db6ff
MC		 712 u16 hdr_info;
713 bool cleaned = false;
9a799d71 714 int cleaned_count = 0;
d2f4fbe2 715 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 716#ifdef IXGBE_FCOE
717 int ddp_bytes = 0;
718#endif /* IXGBE_FCOE */
9a799d71
AK		 719
720 i = rx_ring->next_to_clean;
9a799d71
AK		 721 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
722 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
723 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 724
725 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 726 u32 upper_len = 0;
9a799d71
AK		 727 if (*work_done >= work_to_do)
728 break;
729 (*work_done)++;
730
6e455b89 731 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 732 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
733 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 734 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 735 if (hdr_info & IXGBE_RXDADV_SPH)
736 adapter->rx_hdr_split++;
737 if (len > IXGBE_RX_HDR_SIZE)
738 len = IXGBE_RX_HDR_SIZE;
739 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 740 } else {
9a799d71 741 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 742 }
9a799d71
AK		 743
744 cleaned = true;
745 skb = rx_buffer_info->skb;
746 prefetch(skb->data - NET_IP_ALIGN);
747 rx_buffer_info->skb = NULL;
748
21fa4e66 749 if (rx_buffer_info->dma) {
9a799d71 750 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 751 rx_ring->rx_buf_len,
b4617240 752 PCI_DMA_FROMDEVICE);
4f57ca6e 753 rx_buffer_info->dma = 0;
9a799d71
AK		 754 skb_put(skb, len);
755 }
756
757 if (upper_len) {
758 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 759 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 760 rx_buffer_info->page_dma = 0;
761 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 762 rx_buffer_info->page,
763 rx_buffer_info->page_offset,
764 upper_len);
765
766 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
767 (page_count(rx_buffer_info->page) != 1))
768 rx_buffer_info->page = NULL;
769 else
770 get_page(rx_buffer_info->page);
9a799d71
AK		 771
772 skb->len += upper_len;
773 skb->data_len += upper_len;
774 skb->truesize += upper_len;
775 }
776
777 i++;
778 if (i == rx_ring->count)
779 i = 0;
9a799d71
AK		 780
781 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
782 prefetch(next_rxd);
9a799d71 783 cleaned_count++;
f8212f97 784
0c19d6af 785 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 786 rsc_count = ixgbe_get_rsc_count(rx_desc);
787
788 if (rsc_count) {
789 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
790 IXGBE_RXDADV_NEXTP_SHIFT;
791 next_buffer = &rx_ring->rx_buffer_info[nextp];
792 rx_ring->rsc_count += (rsc_count - 1);
793 } else {
794 next_buffer = &rx_ring->rx_buffer_info[i];
795 }
796
9a799d71 797 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 798 if (skb->prev)
799 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 800 rx_ring->stats.packets++;
801 rx_ring->stats.bytes += skb->len;
802 } else {
6e455b89 803 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 804 rx_buffer_info->skb = next_buffer->skb;
805 rx_buffer_info->dma = next_buffer->dma;
806 next_buffer->skb = skb;
807 next_buffer->dma = 0;
808 } else {
809 skb->next = next_buffer->skb;
810 skb->next->prev = skb;
811 }
9a799d71
AK		 812 adapter->non_eop_descs++;
813 goto next_desc;
814 }
815
816 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
817 dev_kfree_skb_irq(skb);
818 goto next_desc;
819 }
820
8bae1b2b 821 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 822
823 /* probably a little skewed due to removing CRC */
824 total_rx_bytes += skb->len;
825 total_rx_packets++;
826
74ce8dd2 827 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 828#ifdef IXGBE_FCOE
829 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 830 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
831 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
832 if (!ddp_bytes)
332d4a7d 833 goto next_desc;
3d8fd385 834 }
332d4a7d 835#endif /* IXGBE_FCOE */
fdaff1ce 836 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 837
838next_desc:
839 rx_desc->wb.upper.status_error = 0;
840
841 /* return some buffers to hardware, one at a time is too slow */
842 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
843 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
844 cleaned_count = 0;
845 }
846
847 /* use prefetched values */
848 rx_desc = next_rxd;
f8212f97 849 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 850
851 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 852 }
853
9a799d71
AK		 854 rx_ring->next_to_clean = i;
855 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
856
857 if (cleaned_count)
858 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
859
3d8fd385
YZ		 860#ifdef IXGBE_FCOE
861 /* include DDPed FCoE data */
862 if (ddp_bytes > 0) {
863 unsigned int mss;
864
865 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
866 sizeof(struct fc_frame_header) -
867 sizeof(struct fcoe_crc_eof);
868 if (mss > 512)
869 mss &= ~511;
870 total_rx_bytes += ddp_bytes;
871 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
872 }
873#endif /* IXGBE_FCOE */
874
f494e8fa
AV		 875 rx_ring->total_packets += total_rx_packets;
876 rx_ring->total_bytes += total_rx_bytes;
877 adapter->net_stats.rx_bytes += total_rx_bytes;
878 adapter->net_stats.rx_packets += total_rx_packets;
879
9a799d71
AK		 880 return cleaned;
881}
882
021230d4 883static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 884/**
885 * ixgbe_configure_msix - Configure MSI-X hardware
886 * @adapter: board private structure
887 *
888 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
889 * interrupts.
890 **/
891static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
892{
021230d4
AV		 893 struct ixgbe_q_vector *q_vector;
894 int i, j, q_vectors, v_idx, r_idx;
895 u32 mask;
9a799d71 896
021230d4 897 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 898
4df10466
JB		 899 /*
900 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 901 * corresponding register.
902 */
903 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 904 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 905 /* XXX for_each_bit(...) */
906 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 907 adapter->num_rx_queues);
021230d4
AV		 908
909 for (i = 0; i < q_vector->rxr_count; i++) {
910 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 911 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 912 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 913 adapter->num_rx_queues,
914 r_idx + 1);
021230d4
AV		 915 }
916 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 917 adapter->num_tx_queues);
021230d4
AV		 918
919 for (i = 0; i < q_vector->txr_count; i++) {
920 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 921 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 922 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 923 adapter->num_tx_queues,
924 r_idx + 1);
021230d4
AV		 925 }
926
30efa5a3 927 /* if this is a tx only vector halve the interrupt rate */
021230d4 928 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 929 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 930 else if (q_vector->rxr_count)
30efa5a3
JB		 931 /* rx only */
932 q_vector->eitr = adapter->eitr_param;
021230d4 933
fe49f04a 934 ixgbe_write_eitr(q_vector);
9a799d71
AK		 935 }
936
e8e26350
PW		 937 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
938 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
939 v_idx);
940 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
941 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 942 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
943
41fb9248 944 /* set up to autoclear timer, and the vectors */
021230d4 945 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 946 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 947 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 948}
949
f494e8fa
AV		 950enum latency_range {
951 lowest_latency = 0,
952 low_latency = 1,
953 bulk_latency = 2,
954 latency_invalid = 255
955};
956
957/**
958 * ixgbe_update_itr - update the dynamic ITR value based on statistics
959 * @adapter: pointer to adapter
960 * @eitr: eitr setting (ints per sec) to give last timeslice
961 * @itr_setting: current throttle rate in ints/second
962 * @packets: the number of packets during this measurement interval
963 * @bytes: the number of bytes during this measurement interval
964 *
965 * Stores a new ITR value based on packets and byte
966 * counts during the last interrupt. The advantage of per interrupt
967 * computation is faster updates and more accurate ITR for the current
968 * traffic pattern. Constants in this function were computed
969 * based on theoretical maximum wire speed and thresholds were set based
970 * on testing data as well as attempting to minimize response time
971 * while increasing bulk throughput.
972 * this functionality is controlled by the InterruptThrottleRate module
973 * parameter (see ixgbe_param.c)
974 **/
975static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 976 u32 eitr, u8 itr_setting,
977 int packets, int bytes)
f494e8fa
AV		 978{
979 unsigned int retval = itr_setting;
980 u32 timepassed_us;
981 u64 bytes_perint;
982
983 if (packets == 0)
984 goto update_itr_done;
985
986
987 /* simple throttlerate management
988 * 0-20MB/s lowest (100000 ints/s)
989 * 20-100MB/s low (20000 ints/s)
990 * 100-1249MB/s bulk (8000 ints/s)
991 */
992 /* what was last interrupt timeslice? */
993 timepassed_us = 1000000/eitr;
994 bytes_perint = bytes / timepassed_us; /* bytes/usec */
995
996 switch (itr_setting) {
997 case lowest_latency:
998 if (bytes_perint > adapter->eitr_low)
999 retval = low_latency;
1000 break;
1001 case low_latency:
1002 if (bytes_perint > adapter->eitr_high)
1003 retval = bulk_latency;
1004 else if (bytes_perint <= adapter->eitr_low)
1005 retval = lowest_latency;
1006 break;
1007 case bulk_latency:
1008 if (bytes_perint <= adapter->eitr_high)
1009 retval = low_latency;
1010 break;
1011 }
1012
1013update_itr_done:
1014 return retval;
1015}
1016
509ee935
JB		 1017/**
1018 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1019 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1020 *
1021 * This function is made to be called by ethtool and by the driver
1022 * when it needs to update EITR registers at runtime. Hardware
1023 * specific quirks/differences are taken care of here.
1024 */
fe49f04a 1025void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1026{
fe49f04a 1027 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1028 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1029 int v_idx = q_vector->v_idx;
1030 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1031
509ee935
JB		 1032 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1033 /* must write high and low 16 bits to reset counter */
1034 itr_reg |= (itr_reg << 16);
1035 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1036 /*
1037 * set the WDIS bit to not clear the timer bits and cause an
1038 * immediate assertion of the interrupt
1039 */
1040 itr_reg |= IXGBE_EITR_CNT_WDIS;
1041 }
1042 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1043}
1044
f494e8fa
AV		 1045static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1046{
1047 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1048 u32 new_itr;
1049 u8 current_itr, ret_itr;
fe49f04a 1050 int i, r_idx;
f494e8fa
AV		 1051 struct ixgbe_ring *rx_ring, *tx_ring;
1052
1053 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1054 for (i = 0; i < q_vector->txr_count; i++) {
1055 tx_ring = &(adapter->tx_ring[r_idx]);
1056 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1057 q_vector->tx_itr,
1058 tx_ring->total_packets,
1059 tx_ring->total_bytes);
f494e8fa
AV		 1060 /* if the result for this queue would decrease interrupt
1061 * rate for this vector then use that result */
30efa5a3 1062 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1063 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1064 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1065 r_idx + 1);
f494e8fa
AV		 1066 }
1067
1068 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1069 for (i = 0; i < q_vector->rxr_count; i++) {
1070 rx_ring = &(adapter->rx_ring[r_idx]);
1071 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1072 q_vector->rx_itr,
1073 rx_ring->total_packets,
1074 rx_ring->total_bytes);
f494e8fa
AV		 1075 /* if the result for this queue would decrease interrupt
1076 * rate for this vector then use that result */
30efa5a3 1077 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1078 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1079 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1080 r_idx + 1);
f494e8fa
AV		 1081 }
1082
30efa5a3 1083 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1084
1085 switch (current_itr) {
1086 /* counts and packets in update_itr are dependent on these numbers */
1087 case lowest_latency:
1088 new_itr = 100000;
1089 break;
1090 case low_latency:
1091 new_itr = 20000; /* aka hwitr = ~200 */
1092 break;
1093 case bulk_latency:
1094 default:
1095 new_itr = 8000;
1096 break;
1097 }
1098
1099 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1100 /* do an exponential smoothing */
1101 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1102
1103 /* save the algorithm value here, not the smoothed one */
1104 q_vector->eitr = new_itr;
fe49f04a
AD		 1105
1106 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1107 }
1108
1109 return;
1110}
1111
0befdb3e
JB		 1112static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1113{
1114 struct ixgbe_hw *hw = &adapter->hw;
1115
1116 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1117 (eicr & IXGBE_EICR_GPI_SDP1)) {
1118 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1119 /* write to clear the interrupt */
1120 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1121 }
1122}
cf8280ee 1123
e8e26350
PW		 1124static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1125{
1126 struct ixgbe_hw *hw = &adapter->hw;
1127
1128 if (eicr & IXGBE_EICR_GPI_SDP1) {
1129 /* Clear the interrupt */
1130 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1131 schedule_work(&adapter->multispeed_fiber_task);
1132 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1133 /* Clear the interrupt */
1134 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1135 schedule_work(&adapter->sfp_config_module_task);
1136 } else {
1137 /* Interrupt isn't for us... */
1138 return;
1139 }
1140}
1141
cf8280ee
JB		 1142static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1143{
1144 struct ixgbe_hw *hw = &adapter->hw;
1145
1146 adapter->lsc_int++;
1147 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1148 adapter->link_check_timeout = jiffies;
1149 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1150 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1151 schedule_work(&adapter->watchdog_task);
1152 }
1153}
1154
9a799d71
AK		 1155static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1156{
1157 struct net_device *netdev = data;
1158 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1159 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1160 u32 eicr;
1161
1162 /*
1163 * Workaround for Silicon errata. Use clear-by-write instead
1164 * of clear-by-read. Reading with EICS will return the
1165 * interrupt causes without clearing, which later be done
1166 * with the write to EICR.
1167 */
1168 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1169 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1170
cf8280ee
JB		 1171 if (eicr & IXGBE_EICR_LSC)
1172 ixgbe_check_lsc(adapter);
d4f80882 1173
e8e26350
PW		 1174 if (hw->mac.type == ixgbe_mac_82598EB)
1175 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1176
c4cf55e5 1177 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1178 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1179
1180 /* Handle Flow Director Full threshold interrupt */
1181 if (eicr & IXGBE_EICR_FLOW_DIR) {
1182 int i;
1183 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1184 /* Disable transmits before FDIR Re-initialization */
1185 netif_tx_stop_all_queues(netdev);
1186 for (i = 0; i < adapter->num_tx_queues; i++) {
1187 struct ixgbe_ring *tx_ring =
1188 &adapter->tx_ring[i];
1189 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1190 &tx_ring->reinit_state))
1191 schedule_work(&adapter->fdir_reinit_task);
1192 }
1193 }
1194 }
d4f80882
AV		 1195 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1196 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1197
1198 return IRQ_HANDLED;
1199}
1200
fe49f04a
AD		 1201static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1202 u64 qmask)
1203{
1204 u32 mask;
1205
1206 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1207 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1208 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1209 } else {
1210 mask = (qmask & 0xFFFFFFFF);
1211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1212 mask = (qmask >> 32);
1213 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1214 }
1215 /* skip the flush */
1216}
1217
1218static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1219 u64 qmask)
1220{
1221 u32 mask;
1222
1223 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1224 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1225 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1226 } else {
1227 mask = (qmask & 0xFFFFFFFF);
1228 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1229 mask = (qmask >> 32);
1230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1231 }
1232 /* skip the flush */
1233}
1234
9a799d71
AK		 1235static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1236{
021230d4
AV		 1237 struct ixgbe_q_vector *q_vector = data;
1238 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1239 struct ixgbe_ring *tx_ring;
021230d4
AV		 1240 int i, r_idx;
1241
1242 if (!q_vector->txr_count)
1243 return IRQ_HANDLED;
1244
1245 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1246 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1247 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1248 tx_ring->total_bytes = 0;
1249 tx_ring->total_packets = 0;
021230d4 1250 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1251 r_idx + 1);
021230d4 1252 }
9a799d71 1253
91281fd3
AD		 1254 /* disable interrupts on this vector only */
1255 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1256 napi_schedule(&q_vector->napi);
1257
9a799d71
AK		 1258 return IRQ_HANDLED;
1259}
1260
021230d4
AV		 1261/**
1262 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1263 * @irq: unused
1264 * @data: pointer to our q_vector struct for this interrupt vector
1265 **/
9a799d71
AK		 1266static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1267{
021230d4
AV		 1268 struct ixgbe_q_vector *q_vector = data;
1269 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1270 struct ixgbe_ring *rx_ring;
021230d4 1271 int r_idx;
30efa5a3 1272 int i;
021230d4
AV		 1273
1274 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1275 for (i = 0; i < q_vector->rxr_count; i++) {
1276 rx_ring = &(adapter->rx_ring[r_idx]);
1277 rx_ring->total_bytes = 0;
1278 rx_ring->total_packets = 0;
1279 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1280 r_idx + 1);
1281 }
1282
021230d4
AV		 1283 if (!q_vector->rxr_count)
1284 return IRQ_HANDLED;
1285
30efa5a3 1286 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1287 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1288 /* disable interrupts on this vector only */
fe49f04a 1289 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
288379f0 1290 napi_schedule(&q_vector->napi);
021230d4
AV		 1291
1292 return IRQ_HANDLED;
1293}
1294
1295static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1296{
91281fd3
AD		 1297 struct ixgbe_q_vector *q_vector = data;
1298 struct ixgbe_adapter *adapter = q_vector->adapter;
1299 struct ixgbe_ring *ring;
1300 int r_idx;
1301 int i;
1302
1303 if (!q_vector->txr_count && !q_vector->rxr_count)
1304 return IRQ_HANDLED;
1305
1306 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1307 for (i = 0; i < q_vector->txr_count; i++) {
1308 ring = &(adapter->tx_ring[r_idx]);
1309 ring->total_bytes = 0;
1310 ring->total_packets = 0;
1311 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1312 r_idx + 1);
1313 }
1314
1315 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1316 for (i = 0; i < q_vector->rxr_count; i++) {
1317 ring = &(adapter->rx_ring[r_idx]);
1318 ring->total_bytes = 0;
1319 ring->total_packets = 0;
1320 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1321 r_idx + 1);
1322 }
1323
1324 /* disable interrupts on this vector only */
1325 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1326 napi_schedule(&q_vector->napi);
9a799d71 1327
9a799d71
AK		 1328 return IRQ_HANDLED;
1329}
1330
021230d4
AV		 1331/**
1332 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1333 * @napi: napi struct with our devices info in it
1334 * @budget: amount of work driver is allowed to do this pass, in packets
1335 *
f0848276
JB		 1336 * This function is optimized for cleaning one queue only on a single
1337 * q_vector!!!
021230d4 1338 **/
9a799d71
AK		 1339static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1340{
021230d4 1341 struct ixgbe_q_vector *q_vector =
b4617240 1342 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1343 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1344 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1345 int work_done = 0;
021230d4 1346 long r_idx;
9a799d71 1347
021230d4 1348 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1349 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1350#ifdef CONFIG_IXGBE_DCA
bd0362dd 1351 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1352 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1353#endif
9a799d71 1354
78b6f4ce 1355 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1356
021230d4
AV		 1357 /* If all Rx work done, exit the polling mode */
1358 if (work_done < budget) {
288379f0 1359 napi_complete(napi);
509ee935 1360 if (adapter->itr_setting & 1)
f494e8fa 1361 ixgbe_set_itr_msix(q_vector);
9a799d71 1362 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1363 ixgbe_irq_enable_queues(adapter,
1364 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1365 }
1366
1367 return work_done;
1368}
1369
f0848276 1370/**
91281fd3 1371 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1372 * @napi: napi struct with our devices info in it
1373 * @budget: amount of work driver is allowed to do this pass, in packets
1374 *
1375 * This function will clean more than one rx queue associated with a
1376 * q_vector.
1377 **/
91281fd3 1378static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1379{
1380 struct ixgbe_q_vector *q_vector =
1381 container_of(napi, struct ixgbe_q_vector, napi);
1382 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1383 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1384 int work_done = 0, i;
1385 long r_idx;
91281fd3
AD		 1386 bool tx_clean_complete = true;
1387
1388 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1389 for (i = 0; i < q_vector->txr_count; i++) {
1390 ring = &(adapter->tx_ring[r_idx]);
1391#ifdef CONFIG_IXGBE_DCA
1392 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1393 ixgbe_update_tx_dca(adapter, ring);
1394#endif
1395 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1396 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1397 r_idx + 1);
1398 }
f0848276
JB		 1399
1400 /* attempt to distribute budget to each queue fairly, but don't allow
1401 * the budget to go below 1 because we'll exit polling */
1402 budget /= (q_vector->rxr_count ?: 1);
1403 budget = max(budget, 1);
1404 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1405 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1406 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1407#ifdef CONFIG_IXGBE_DCA
f0848276 1408 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1409 ixgbe_update_rx_dca(adapter, ring);
f0848276 1410#endif
91281fd3 1411 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1412 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1413 r_idx + 1);
1414 }
1415
1416 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1417 ring = &(adapter->rx_ring[r_idx]);
f0848276 1418 /* If all Rx work done, exit the polling mode */
7f821875 1419 if (work_done < budget) {
288379f0 1420 napi_complete(napi);
509ee935 1421 if (adapter->itr_setting & 1)
f0848276
JB		 1422 ixgbe_set_itr_msix(q_vector);
1423 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1424 ixgbe_irq_enable_queues(adapter,
1425 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1426 return 0;
1427 }
1428
1429 return work_done;
1430}
91281fd3
AD		 1431
1432/**
1433 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1434 * @napi: napi struct with our devices info in it
1435 * @budget: amount of work driver is allowed to do this pass, in packets
1436 *
1437 * This function is optimized for cleaning one queue only on a single
1438 * q_vector!!!
1439 **/
1440static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1441{
1442 struct ixgbe_q_vector *q_vector =
1443 container_of(napi, struct ixgbe_q_vector, napi);
1444 struct ixgbe_adapter *adapter = q_vector->adapter;
1445 struct ixgbe_ring *tx_ring = NULL;
1446 int work_done = 0;
1447 long r_idx;
1448
1449 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1450 tx_ring = &(adapter->tx_ring[r_idx]);
1451#ifdef CONFIG_IXGBE_DCA
1452 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1453 ixgbe_update_tx_dca(adapter, tx_ring);
1454#endif
1455
1456 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1457 work_done = budget;
1458
1459 /* If all Rx work done, exit the polling mode */
1460 if (work_done < budget) {
1461 napi_complete(napi);
1462 if (adapter->itr_setting & 1)
1463 ixgbe_set_itr_msix(q_vector);
1464 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1465 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1466 }
1467
1468 return work_done;
1469}
1470
021230d4 1471static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1472 int r_idx)
021230d4 1473{
7a921c93
AD		 1474 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1475
1476 set_bit(r_idx, q_vector->rxr_idx);
1477 q_vector->rxr_count++;
021230d4
AV		 1478}
1479
1480static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1481 int t_idx)
021230d4 1482{
7a921c93
AD		 1483 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1484
1485 set_bit(t_idx, q_vector->txr_idx);
1486 q_vector->txr_count++;
021230d4
AV		 1487}
1488
9a799d71 1489/**
021230d4
AV		 1490 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1491 * @adapter: board private structure to initialize
1492 * @vectors: allotted vector count for descriptor rings
9a799d71 1493 *
021230d4
AV		 1494 * This function maps descriptor rings to the queue-specific vectors
1495 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1496 * one vector per ring/queue, but on a constrained vector budget, we
1497 * group the rings as "efficiently" as possible. You would add new
1498 * mapping configurations in here.
9a799d71 1499 **/
021230d4 1500static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1501 int vectors)
021230d4
AV		 1502{
1503 int v_start = 0;
1504 int rxr_idx = 0, txr_idx = 0;
1505 int rxr_remaining = adapter->num_rx_queues;
1506 int txr_remaining = adapter->num_tx_queues;
1507 int i, j;
1508 int rqpv, tqpv;
1509 int err = 0;
1510
1511 /* No mapping required if MSI-X is disabled. */
1512 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1513 goto out;
9a799d71 1514
021230d4
AV		 1515 /*
1516 * The ideal configuration...
1517 * We have enough vectors to map one per queue.
1518 */
1519 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1520 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1521 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1522
021230d4
AV		 1523 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1524 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1525
9a799d71 1526 goto out;
021230d4 1527 }
9a799d71 1528
021230d4
AV		 1529 /*
1530 * If we don't have enough vectors for a 1-to-1
1531 * mapping, we'll have to group them so there are
1532 * multiple queues per vector.
1533 */
1534 /* Re-adjusting *qpv takes care of the remainder. */
1535 for (i = v_start; i < vectors; i++) {
1536 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1537 for (j = 0; j < rqpv; j++) {
1538 map_vector_to_rxq(adapter, i, rxr_idx);
1539 rxr_idx++;
1540 rxr_remaining--;
1541 }
1542 }
1543 for (i = v_start; i < vectors; i++) {
1544 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1545 for (j = 0; j < tqpv; j++) {
1546 map_vector_to_txq(adapter, i, txr_idx);
1547 txr_idx++;
1548 txr_remaining--;
9a799d71 1549 }
9a799d71
AK		 1550 }
1551
021230d4
AV		 1552out:
1553 return err;
1554}
1555
1556/**
1557 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1558 * @adapter: board private structure
1559 *
1560 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1561 * interrupts from the kernel.
1562 **/
1563static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1564{
1565 struct net_device *netdev = adapter->netdev;
1566 irqreturn_t (*handler)(int, void *);
1567 int i, vector, q_vectors, err;
cb13fc20 1568 int ri=0, ti=0;
021230d4
AV		 1569
1570 /* Decrement for Other and TCP Timer vectors */
1571 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1572
1573 /* Map the Tx/Rx rings to the vectors we were allotted. */
1574 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1575 if (err)
1576 goto out;
1577
1578#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1579 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1580 &ixgbe_msix_clean_many)
021230d4 1581 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1582 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1583
1584 if(handler == &ixgbe_msix_clean_rx) {
1585 sprintf(adapter->name[vector], "%s-%s-%d",
1586 netdev->name, "rx", ri++);
1587 }
1588 else if(handler == &ixgbe_msix_clean_tx) {
1589 sprintf(adapter->name[vector], "%s-%s-%d",
1590 netdev->name, "tx", ti++);
1591 }
1592 else
1593 sprintf(adapter->name[vector], "%s-%s-%d",
1594 netdev->name, "TxRx", vector);
1595
021230d4 1596 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1597 handler, 0, adapter->name[vector],
7a921c93 1598 adapter->q_vector[vector]);
9a799d71
AK		 1599 if (err) {
1600 DPRINTK(PROBE, ERR,
b4617240
PW		 1601 "request_irq failed for MSIX interrupt "
1602 "Error: %d\n", err);
021230d4 1603 goto free_queue_irqs;
9a799d71 1604 }
9a799d71
AK		 1605 }
1606
021230d4
AV		 1607 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1608 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1609 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1610 if (err) {
1611 DPRINTK(PROBE, ERR,
1612 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1613 goto free_queue_irqs;
9a799d71
AK		 1614 }
1615
9a799d71
AK		 1616 return 0;
1617
021230d4
AV		 1618free_queue_irqs:
1619 for (i = vector - 1; i >= 0; i--)
1620 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1621 adapter->q_vector[i]);
021230d4
AV		 1622 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1623 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1624 kfree(adapter->msix_entries);
1625 adapter->msix_entries = NULL;
021230d4 1626out:
9a799d71
AK		 1627 return err;
1628}
1629
f494e8fa
AV		 1630static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1631{
7a921c93 1632 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1633 u8 current_itr;
1634 u32 new_itr = q_vector->eitr;
1635 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1636 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1637
30efa5a3 1638 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1639 q_vector->tx_itr,
1640 tx_ring->total_packets,
1641 tx_ring->total_bytes);
30efa5a3 1642 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1643 q_vector->rx_itr,
1644 rx_ring->total_packets,
1645 rx_ring->total_bytes);
f494e8fa 1646
30efa5a3 1647 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1648
1649 switch (current_itr) {
1650 /* counts and packets in update_itr are dependent on these numbers */
1651 case lowest_latency:
1652 new_itr = 100000;
1653 break;
1654 case low_latency:
1655 new_itr = 20000; /* aka hwitr = ~200 */
1656 break;
1657 case bulk_latency:
1658 new_itr = 8000;
1659 break;
1660 default:
1661 break;
1662 }
1663
1664 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1665 /* do an exponential smoothing */
1666 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1667
1668 /* save the algorithm value here, not the smoothed one */
1669 q_vector->eitr = new_itr;
fe49f04a
AD		 1670
1671 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1672 }
1673
1674 return;
1675}
1676
79aefa45
AD		 1677/**
1678 * ixgbe_irq_enable - Enable default interrupt generation settings
1679 * @adapter: board private structure
1680 **/
1681static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1682{
1683 u32 mask;
835462fc
NS		 1684
1685 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1686 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1687 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1688 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1689 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1690 mask |= IXGBE_EIMS_GPI_SDP1;
1691 mask |= IXGBE_EIMS_GPI_SDP2;
1692 }
c4cf55e5
PWJ		 1693 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1694 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1695 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1696
79aefa45 1697 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1698 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1699 IXGBE_WRITE_FLUSH(&adapter->hw);
1700}
021230d4 1701
9a799d71 1702/**
021230d4 1703 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1704 * @irq: interrupt number
1705 * @data: pointer to a network interface device structure
9a799d71
AK		 1706 **/
1707static irqreturn_t ixgbe_intr(int irq, void *data)
1708{
1709 struct net_device *netdev = data;
1710 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1711 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1712 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1713 u32 eicr;
1714
54037505
DS		 1715 /*
1716 * Workaround for silicon errata. Mask the interrupts
1717 * before the read of EICR.
1718 */
1719 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1720
021230d4
AV		 1721 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1722 * therefore no explict interrupt disable is necessary */
1723 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1724 if (!eicr) {
1725 /* shared interrupt alert!
1726 * make sure interrupts are enabled because the read will
1727 * have disabled interrupts due to EIAM */
1728 ixgbe_irq_enable(adapter);
9a799d71 1729 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1730 }
9a799d71 1731
cf8280ee
JB		 1732 if (eicr & IXGBE_EICR_LSC)
1733 ixgbe_check_lsc(adapter);
021230d4 1734
e8e26350
PW		 1735 if (hw->mac.type == ixgbe_mac_82599EB)
1736 ixgbe_check_sfp_event(adapter, eicr);
1737
0befdb3e
JB		 1738 ixgbe_check_fan_failure(adapter, eicr);
1739
7a921c93 1740 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1741 adapter->tx_ring[0].total_packets = 0;
1742 adapter->tx_ring[0].total_bytes = 0;
1743 adapter->rx_ring[0].total_packets = 0;
1744 adapter->rx_ring[0].total_bytes = 0;
021230d4 1745 /* would disable interrupts here but EIAM disabled it */
7a921c93 1746 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1747 }
1748
1749 return IRQ_HANDLED;
1750}
1751
021230d4
AV		 1752static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1753{
1754 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1755
1756 for (i = 0; i < q_vectors; i++) {
7a921c93 1757 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1758 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1759 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1760 q_vector->rxr_count = 0;
1761 q_vector->txr_count = 0;
1762 }
1763}
1764
9a799d71
AK		 1765/**
1766 * ixgbe_request_irq - initialize interrupts
1767 * @adapter: board private structure
1768 *
1769 * Attempts to configure interrupts using the best available
1770 * capabilities of the hardware and kernel.
1771 **/
021230d4 1772static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1773{
1774 struct net_device *netdev = adapter->netdev;
021230d4 1775 int err;
9a799d71 1776
021230d4
AV		 1777 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1778 err = ixgbe_request_msix_irqs(adapter);
1779 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1780 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1781 netdev->name, netdev);
021230d4
AV		 1782 } else {
1783 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1784 netdev->name, netdev);
9a799d71
AK		 1785 }
1786
9a799d71
AK		 1787 if (err)
1788 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1789
9a799d71
AK		 1790 return err;
1791}
1792
1793static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1794{
1795 struct net_device *netdev = adapter->netdev;
1796
1797 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1798 int i, q_vectors;
9a799d71 1799
021230d4
AV		 1800 q_vectors = adapter->num_msix_vectors;
1801
1802 i = q_vectors - 1;
9a799d71 1803 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1804
021230d4
AV		 1805 i--;
1806 for (; i >= 0; i--) {
1807 free_irq(adapter->msix_entries[i].vector,
7a921c93 1808 adapter->q_vector[i]);
021230d4
AV		 1809 }
1810
1811 ixgbe_reset_q_vectors(adapter);
1812 } else {
1813 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1814 }
1815}
1816
22d5a71b
JB		 1817/**
1818 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1819 * @adapter: board private structure
1820 **/
1821static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1822{
835462fc
NS		 1823 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1825 } else {
1826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1828 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1829 }
1830 IXGBE_WRITE_FLUSH(&adapter->hw);
1831 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1832 int i;
1833 for (i = 0; i < adapter->num_msix_vectors; i++)
1834 synchronize_irq(adapter->msix_entries[i].vector);
1835 } else {
1836 synchronize_irq(adapter->pdev->irq);
1837 }
1838}
1839
9a799d71
AK		 1840/**
1841 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1842 *
1843 **/
1844static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1845{
9a799d71
AK		 1846 struct ixgbe_hw *hw = &adapter->hw;
1847
021230d4 1848 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1849 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1850
e8e26350
PW		 1851 ixgbe_set_ivar(adapter, 0, 0, 0);
1852 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1853
1854 map_vector_to_rxq(adapter, 0, 0);
1855 map_vector_to_txq(adapter, 0, 0);
1856
1857 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1858}
1859
1860/**
3a581073 1861 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1862 * @adapter: board private structure
1863 *
1864 * Configure the Tx unit of the MAC after a reset.
1865 **/
1866static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1867{
12207e49 1868 u64 tdba;
9a799d71 1869 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1870 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1871
1872 /* Setup the HW Tx Head and Tail descriptor pointers */
1873 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1874 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1875 j = ring->reg_idx;
1876 tdba = ring->dma;
1877 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1878 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1879 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1880 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1881 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1882 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1883 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1884 adapter->tx_ring[i].head = IXGBE_TDH(j);
1885 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1886 /* Disable Tx Head Writeback RO bit, since this hoses
1887 * bookkeeping if things aren't delivered in order.
1888 */
e01c31a5 1889 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1890 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1891 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1892 }
e8e26350
PW		 1893 if (hw->mac.type == ixgbe_mac_82599EB) {
1894 /* We enable 8 traffic classes, DCB only */
1895 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1896 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1897 IXGBE_MTQC_8TC_8TQ));
1898 }
9a799d71
AK		 1899}
1900
e8e26350 1901#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 1902
a6616b42
YZ		 1903static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1904 struct ixgbe_ring *rx_ring)
cc41ac7c 1905{
cc41ac7c 1906 u32 srrctl;
a6616b42 1907 int index;
0cefafad 1908 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 1909
a6616b42
YZ		 1910 index = rx_ring->reg_idx;
1911 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1912 unsigned long mask;
0cefafad 1913 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 1914 index = index & mask;
cc41ac7c 1915 }
cc41ac7c
JB		 1916 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1917
1918 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1919 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1920
afafd5b0
AD		 1921 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1922 IXGBE_SRRCTL_BSIZEHDR_MASK;
1923
6e455b89 1924 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 1925#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1926 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1927#else
1928 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1929#endif
cc41ac7c 1930 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1931 } else {
afafd5b0
AD		 1932 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1933 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1934 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1935 }
e8e26350 1936
cc41ac7c
JB		 1937 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1938}
9a799d71 1939
0cefafad
JB		 1940static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1941{
1942 u32 mrqc = 0;
1943 int mask;
1944
1945 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1946 return mrqc;
1947
1948 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1949#ifdef CONFIG_IXGBE_DCB
1950 | IXGBE_FLAG_DCB_ENABLED
1951#endif
1952 );
1953
1954 switch (mask) {
1955 case (IXGBE_FLAG_RSS_ENABLED):
1956 mrqc = IXGBE_MRQC_RSSEN;
1957 break;
1958#ifdef CONFIG_IXGBE_DCB
1959 case (IXGBE_FLAG_DCB_ENABLED):
1960 mrqc = IXGBE_MRQC_RT8TCEN;
1961 break;
1962#endif /* CONFIG_IXGBE_DCB */
1963 default:
1964 break;
1965 }
1966
1967 return mrqc;
1968}
1969
9a799d71 1970/**
3a581073 1971 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1972 * @adapter: board private structure
1973 *
1974 * Configure the Rx unit of the MAC after a reset.
1975 **/
1976static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1977{
1978 u64 rdba;
1979 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 1980 struct ixgbe_ring *rx_ring;
9a799d71
AK		 1981 struct net_device *netdev = adapter->netdev;
1982 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1983 int i, j;
9a799d71 1984 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1985 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1986 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1987 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1988 u32 fctrl, hlreg0;
509ee935 1989 u32 reta = 0, mrqc = 0;
cc41ac7c 1990 u32 rdrxctl;
f8212f97 1991 u32 rscctrl;
7c6e0a43 1992 int rx_buf_len;
9a799d71
AK		 1993
1994 /* Decide whether to use packet split mode or not */
762f4c57 1995 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1996
1997 /* Set the RX buffer length according to the mode */
1998 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1999 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2000 if (hw->mac.type == ixgbe_mac_82599EB) {
2001 /* PSRTYPE must be initialized in 82599 */
2002 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2003 IXGBE_PSRTYPE_UDPHDR |
2004 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2005 IXGBE_PSRTYPE_IPV6HDR |
2006 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 2007 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2008 }
9a799d71 2009 } else {
0c19d6af 2010 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2011 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2012 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2013 else
7c6e0a43 2014 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2015 }
2016
2017 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2018 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2019 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2020 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2021 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2022
2023 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2024 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2025 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2026 else
2027 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2028#ifdef IXGBE_FCOE
f34c5c82 2029 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2030 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2031#endif
9a799d71
AK		 2032 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2033
9a799d71
AK		 2034 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2035 /* disable receives while setting up the descriptors */
2036 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2037 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2038
0cefafad
JB		 2039 /*
2040 * Setup the HW Rx Head and Tail Descriptor Pointers and
2041 * the Base and Length of the Rx Descriptor Ring
2042 */
9a799d71 2043 for (i = 0; i < adapter->num_rx_queues; i++) {
a6616b42
YZ		 2044 rx_ring = &adapter->rx_ring[i];
2045 rdba = rx_ring->dma;
2046 j = rx_ring->reg_idx;
284901a9 2047 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2048 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2049 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2050 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2051 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2052 rx_ring->head = IXGBE_RDH(j);
2053 rx_ring->tail = IXGBE_RDT(j);
2054 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2055
6e455b89
YZ		 2056 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2057 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2058
63f39bd1 2059#ifdef IXGBE_FCOE
f34c5c82 2060 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2061 struct ixgbe_ring_feature *f;
2062 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2063 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2064 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2065 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2066 rx_ring->rx_buf_len =
2067 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2068 }
63f39bd1
YZ		 2069 }
2070
2071#endif /* IXGBE_FCOE */
a6616b42 2072 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2073 }
2074
e8e26350
PW		 2075 if (hw->mac.type == ixgbe_mac_82598EB) {
2076 /*
2077 * For VMDq support of different descriptor types or
2078 * buffer sizes through the use of multiple SRRCTL
2079 * registers, RDRXCTL.MVMEN must be set to 1
2080 *
2081 * also, the manual doesn't mention it clearly but DCA hints
2082 * will only use queue 0's tags unless this bit is set. Side
2083 * effects of setting this bit are only that SRRCTL must be
2084 * fully programmed [0..15]
2085 */
2a41ff81
JB		 2086 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2087 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2088 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2089 }
177db6ff 2090
e8e26350 2091 /* Program MRQC for the distribution of queues */
0cefafad 2092 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2093
021230d4 2094 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2095 /* Fill out redirection table */
021230d4
AV		 2096 for (i = 0, j = 0; i < 128; i++, j++) {
2097 if (j == adapter->ring_feature[RING_F_RSS].indices)
2098 j = 0;
2099 /* reta = 4-byte sliding window of
2100 * 0x00..(indices-1)(indices-1)00..etc. */
2101 reta = (reta << 8) | (j * 0x11);
2102 if ((i & 3) == 3)
2103 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2104 }
2105
2106 /* Fill out hash function seeds */
2107 for (i = 0; i < 10; i++)
7c6e0a43 2108 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2109
2a41ff81
JB		 2110 if (hw->mac.type == ixgbe_mac_82598EB)
2111 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2112 /* Perform hash on these packet types */
2a41ff81
JB		 2113 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2114 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2115 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2116 | IXGBE_MRQC_RSS_FIELD_IPV6
2117 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2118 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2119 }
2a41ff81 2120 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2121
021230d4
AV		 2122 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2123
2124 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2125 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2126 /* Disable indicating checksum in descriptor, enables
2127 * RSS hash */
9a799d71 2128 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2129 }
021230d4
AV		 2130 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2131 /* Enable IPv4 payload checksum for UDP fragments
2132 * if PCSD is not set */
2133 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2134 }
2135
2136 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2137
2138 if (hw->mac.type == ixgbe_mac_82599EB) {
2139 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2140 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2141 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2142 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2143 }
f8212f97 2144
0c19d6af 2145 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97
AD		 2146 /* Enable 82599 HW-RSC */
2147 for (i = 0; i < adapter->num_rx_queues; i++) {
6e455b89
YZ		 2148 rx_ring = &adapter->rx_ring[i];
2149 j = rx_ring->reg_idx;
f8212f97
AD		 2150 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2151 rscctrl |= IXGBE_RSCCTL_RSCEN;
2152 /*
e76678dd
AD		 2153 * we must limit the number of descriptors so that the
2154 * total size of max desc * buf_len is not greater
2155 * than 65535
f8212f97 2156 */
6e455b89 2157 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
e76678dd
AD		 2158#if (MAX_SKB_FRAGS > 16)
2159 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2160#elif (MAX_SKB_FRAGS > 8)
f8212f97 2161 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
e76678dd
AD		 2162#elif (MAX_SKB_FRAGS > 4)
2163 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
f8212f97 2164#else
e76678dd 2165 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
f8212f97 2166#endif
e76678dd
AD		 2167 } else {
2168 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2169 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2170 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2171 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2172 else
2173 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2174 }
f8212f97
AD		 2175 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2176 }
2177 /* Disable RSC for ACK packets */
2178 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2179 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2180 }
9a799d71
AK		 2181}
2182
068c89b0
DS		 2183static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2184{
2185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2186 struct ixgbe_hw *hw = &adapter->hw;
2187
2188 /* add VID to filter table */
2189 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2190}
2191
2192static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2193{
2194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2195 struct ixgbe_hw *hw = &adapter->hw;
2196
2197 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2198 ixgbe_irq_disable(adapter);
2199
2200 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2201
2202 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2203 ixgbe_irq_enable(adapter);
2204
2205 /* remove VID from filter table */
2206 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2207}
2208
9a799d71 2209static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2210 struct vlan_group *grp)
9a799d71
AK		 2211{
2212 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2213 u32 ctrl;
e8e26350 2214 int i, j;
9a799d71 2215
d4f80882
AV		 2216 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2217 ixgbe_irq_disable(adapter);
9a799d71
AK		 2218 adapter->vlgrp = grp;
2219
2f90b865
AD		 2220 /*
2221 * For a DCB driver, always enable VLAN tag stripping so we can
2222 * still receive traffic from a DCB-enabled host even if we're
2223 * not in DCB mode.
2224 */
2225 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2226 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2227 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2228 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2230 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2231 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2232 /* enable VLAN tag insert/strip */
2233 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2234 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2235 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2236 for (i = 0; i < adapter->num_rx_queues; i++) {
2237 j = adapter->rx_ring[i].reg_idx;
2238 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2239 ctrl |= IXGBE_RXDCTL_VME;
2240 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2241 }
9a799d71 2242 }
e8e26350 2243 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2244
d4f80882
AV		 2245 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2246 ixgbe_irq_enable(adapter);
9a799d71
AK		 2247}
2248
9a799d71
AK		 2249static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2250{
2251 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2252
2253 if (adapter->vlgrp) {
2254 u16 vid;
2255 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2256 if (!vlan_group_get_device(adapter->vlgrp, vid))
2257 continue;
2258 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2259 }
2260 }
2261}
2262
2c5645cf
CL		 2263static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2264{
2265 struct dev_mc_list *mc_ptr;
2266 u8 *addr = *mc_addr_ptr;
2267 *vmdq = 0;
2268
2269 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2270 if (mc_ptr->next)
2271 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2272 else
2273 *mc_addr_ptr = NULL;
2274
2275 return addr;
2276}
2277
9a799d71 2278/**
2c5645cf 2279 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2280 * @netdev: network interface device structure
2281 *
2c5645cf
CL		 2282 * The set_rx_method entry point is called whenever the unicast/multicast
2283 * address list or the network interface flags are updated. This routine is
2284 * responsible for configuring the hardware for proper unicast, multicast and
2285 * promiscuous mode.
9a799d71 2286 **/
2c5645cf 2287static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2288{
2289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2290 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2291 u32 fctrl, vlnctrl;
2c5645cf
CL		 2292 u8 *addr_list = NULL;
2293 int addr_count = 0;
9a799d71
AK		 2294
2295 /* Check for Promiscuous and All Multicast modes */
2296
2297 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2298 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2299
2300 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2301 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2302 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2303 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2304 } else {
746b9f02
PM		 2305 if (netdev->flags & IFF_ALLMULTI) {
2306 fctrl |= IXGBE_FCTRL_MPE;
2307 fctrl &= ~IXGBE_FCTRL_UPE;
2308 } else {
2309 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2310 }
3d01625a 2311 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2312 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2313 }
2314
2315 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2316 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2317
2c5645cf 2318 /* reprogram secondary unicast list */
31278e71 2319 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
9a799d71 2320
2c5645cf
CL		 2321 /* reprogram multicast list */
2322 addr_count = netdev->mc_count;
2323 if (addr_count)
2324 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2325 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2326 ixgbe_addr_list_itr);
9a799d71
AK		 2327}
2328
021230d4
AV		 2329static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2330{
2331 int q_idx;
2332 struct ixgbe_q_vector *q_vector;
2333 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2334
2335 /* legacy and MSI only use one vector */
2336 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2337 q_vectors = 1;
2338
2339 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2340 struct napi_struct *napi;
7a921c93 2341 q_vector = adapter->q_vector[q_idx];
f0848276 2342 napi = &q_vector->napi;
91281fd3
AD		 2343 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2344 if (!q_vector->rxr_count || !q_vector->txr_count) {
2345 if (q_vector->txr_count == 1)
2346 napi->poll = &ixgbe_clean_txonly;
2347 else if (q_vector->rxr_count == 1)
2348 napi->poll = &ixgbe_clean_rxonly;
2349 }
2350 }
f0848276
JB		 2351
2352 napi_enable(napi);
021230d4
AV		 2353 }
2354}
2355
2356static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2357{
2358 int q_idx;
2359 struct ixgbe_q_vector *q_vector;
2360 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2361
2362 /* legacy and MSI only use one vector */
2363 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2364 q_vectors = 1;
2365
2366 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2367 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2368 napi_disable(&q_vector->napi);
2369 }
2370}
2371
7a6b6f51 2372#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2373/*
2374 * ixgbe_configure_dcb - Configure DCB hardware
2375 * @adapter: ixgbe adapter struct
2376 *
2377 * This is called by the driver on open to configure the DCB hardware.
2378 * This is also called by the gennetlink interface when reconfiguring
2379 * the DCB state.
2380 */
2381static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2382{
2383 struct ixgbe_hw *hw = &adapter->hw;
2384 u32 txdctl, vlnctrl;
2385 int i, j;
2386
2387 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2388 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2389 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2390
2391 /* reconfigure the hardware */
2392 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2393
2394 for (i = 0; i < adapter->num_tx_queues; i++) {
2395 j = adapter->tx_ring[i].reg_idx;
2396 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2397 /* PThresh workaround for Tx hang with DFP enabled. */
2398 txdctl |= 32;
2399 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2400 }
2401 /* Enable VLAN tag insert/strip */
2402 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2403 if (hw->mac.type == ixgbe_mac_82598EB) {
2404 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2405 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2406 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2407 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2408 vlnctrl |= IXGBE_VLNCTRL_VFE;
2409 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2410 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2411 for (i = 0; i < adapter->num_rx_queues; i++) {
2412 j = adapter->rx_ring[i].reg_idx;
2413 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2414 vlnctrl |= IXGBE_RXDCTL_VME;
2415 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2416 }
2417 }
2f90b865
AD		 2418 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2419}
2420
2421#endif
9a799d71
AK		 2422static void ixgbe_configure(struct ixgbe_adapter *adapter)
2423{
2424 struct net_device *netdev = adapter->netdev;
c4cf55e5 2425 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2426 int i;
2427
2c5645cf 2428 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2429
2430 ixgbe_restore_vlan(adapter);
7a6b6f51 2431#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2432 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2433 netif_set_gso_max_size(netdev, 32768);
2434 ixgbe_configure_dcb(adapter);
2435 } else {
2436 netif_set_gso_max_size(netdev, 65536);
2437 }
2438#else
2439 netif_set_gso_max_size(netdev, 65536);
2440#endif
9a799d71 2441
eacd73f7
YZ		 2442#ifdef IXGBE_FCOE
2443 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2444 ixgbe_configure_fcoe(adapter);
2445
2446#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2447 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2448 for (i = 0; i < adapter->num_tx_queues; i++)
2449 adapter->tx_ring[i].atr_sample_rate =
2450 adapter->atr_sample_rate;
2451 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2452 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2453 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2454 }
2455
9a799d71
AK		 2456 ixgbe_configure_tx(adapter);
2457 ixgbe_configure_rx(adapter);
2458 for (i = 0; i < adapter->num_rx_queues; i++)
2459 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2460 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2461}
2462
e8e26350
PW		 2463static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2464{
2465 switch (hw->phy.type) {
2466 case ixgbe_phy_sfp_avago:
2467 case ixgbe_phy_sfp_ftl:
2468 case ixgbe_phy_sfp_intel:
2469 case ixgbe_phy_sfp_unknown:
2470 case ixgbe_phy_tw_tyco:
2471 case ixgbe_phy_tw_unknown:
2472 return true;
2473 default:
2474 return false;
2475 }
2476}
2477
0ecc061d 2478/**
e8e26350
PW		 2479 * ixgbe_sfp_link_config - set up SFP+ link
2480 * @adapter: pointer to private adapter struct
2481 **/
2482static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2483{
2484 struct ixgbe_hw *hw = &adapter->hw;
2485
2486 if (hw->phy.multispeed_fiber) {
2487 /*
2488 * In multispeed fiber setups, the device may not have
2489 * had a physical connection when the driver loaded.
2490 * If that's the case, the initial link configuration
2491 * couldn't get the MAC into 10G or 1G mode, so we'll
2492 * never have a link status change interrupt fire.
2493 * We need to try and force an autonegotiation
2494 * session, then bring up link.
2495 */
2496 hw->mac.ops.setup_sfp(hw);
2497 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2498 schedule_work(&adapter->multispeed_fiber_task);
2499 } else {
2500 /*
2501 * Direct Attach Cu and non-multispeed fiber modules
2502 * still need to be configured properly prior to
2503 * attempting link.
2504 */
2505 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2506 schedule_work(&adapter->sfp_config_module_task);
2507 }
2508}
2509
2510/**
2511 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2512 * @hw: pointer to private hardware struct
2513 *
2514 * Returns 0 on success, negative on failure
2515 **/
e8e26350 2516static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2517{
2518 u32 autoneg;
8620a103 2519 bool negotiation, link_up = false;
0ecc061d
PWJ		 2520 u32 ret = IXGBE_ERR_LINK_SETUP;
2521
2522 if (hw->mac.ops.check_link)
2523 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2524
2525 if (ret)
2526 goto link_cfg_out;
2527
2528 if (hw->mac.ops.get_link_capabilities)
8620a103 2529 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2530 if (ret)
2531 goto link_cfg_out;
2532
8620a103
MC		 2533 if (hw->mac.ops.setup_link)
2534 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2535link_cfg_out:
2536 return ret;
2537}
2538
e8e26350
PW		 2539#define IXGBE_MAX_RX_DESC_POLL 10
2540static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2541 int rxr)
2542{
2543 int j = adapter->rx_ring[rxr].reg_idx;
2544 int k;
2545
2546 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2547 if (IXGBE_READ_REG(&adapter->hw,
2548 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2549 break;
2550 else
2551 msleep(1);
2552 }
2553 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2554 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2555 "not set within the polling period\n", rxr);
2556 }
2557 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2558 (adapter->rx_ring[rxr].count - 1));
2559}
2560
9a799d71
AK		 2561static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2562{
2563 struct net_device *netdev = adapter->netdev;
9a799d71 2564 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2565 int i, j = 0;
e8e26350 2566 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2567 int err;
9a799d71 2568 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2569 u32 txdctl, rxdctl, mhadd;
e8e26350 2570 u32 dmatxctl;
021230d4 2571 u32 gpie;
9a799d71 2572
5eba3699
AV		 2573 ixgbe_get_hw_control(adapter);
2574
021230d4
AV		 2575 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2576 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2577 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2578 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2579 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2580 } else {
2581 /* MSI only */
021230d4 2582 gpie = 0;
9a799d71 2583 }
021230d4
AV		 2584 /* XXX: to interrupt immediately for EICS writes, enable this */
2585 /* gpie |= IXGBE_GPIE_EIMEN; */
2586 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2587 }
2588
021230d4
AV		 2589 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2590 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2591 * specifically only auto mask tx and rx interrupts */
2592 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2593 }
9a799d71 2594
0befdb3e
JB		 2595 /* Enable fan failure interrupt if media type is copper */
2596 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2597 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2598 gpie |= IXGBE_SDP1_GPIEN;
2599 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2600 }
2601
e8e26350
PW		 2602 if (hw->mac.type == ixgbe_mac_82599EB) {
2603 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2604 gpie |= IXGBE_SDP1_GPIEN;
2605 gpie |= IXGBE_SDP2_GPIEN;
2606 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2607 }
2608
63f39bd1
YZ		 2609#ifdef IXGBE_FCOE
2610 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2611 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2612 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2613 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2614
2615#endif /* IXGBE_FCOE */
021230d4 2616 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2617 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2618 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2619 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2620
2621 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2622 }
2623
2624 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2625 j = adapter->tx_ring[i].reg_idx;
2626 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2627 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2628 txdctl |= (8 << 16);
e8e26350
PW		 2629 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2630 }
2631
2632 if (hw->mac.type == ixgbe_mac_82599EB) {
2633 /* DMATXCTL.EN must be set after all Tx queue config is done */
2634 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2635 dmatxctl |= IXGBE_DMATXCTL_TE;
2636 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2637 }
2638 for (i = 0; i < adapter->num_tx_queues; i++) {
2639 j = adapter->tx_ring[i].reg_idx;
2640 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2641 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2642 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2643 }
2644
e8e26350 2645 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2646 j = adapter->rx_ring[i].reg_idx;
2647 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2648 /* enable PTHRESH=32 descriptors (half the internal cache)
2649 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2650 * this also removes a pesky rx_no_buffer_count increment */
2651 rxdctl |= 0x0020;
9a799d71 2652 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2653 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2654 if (hw->mac.type == ixgbe_mac_82599EB)
2655 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2656 }
2657 /* enable all receives */
2658 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2659 if (hw->mac.type == ixgbe_mac_82598EB)
2660 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2661 else
2662 rxdctl |= IXGBE_RXCTRL_RXEN;
2663 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2664
2665 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2666 ixgbe_configure_msix(adapter);
2667 else
2668 ixgbe_configure_msi_and_legacy(adapter);
2669
2670 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2671 ixgbe_napi_enable_all(adapter);
2672
2673 /* clear any pending interrupts, may auto mask */
2674 IXGBE_READ_REG(hw, IXGBE_EICR);
2675
9a799d71
AK		 2676 ixgbe_irq_enable(adapter);
2677
bf069c97
DS		 2678 /*
2679 * If this adapter has a fan, check to see if we had a failure
2680 * before we enabled the interrupt.
2681 */
2682 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2683 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2684 if (esdp & IXGBE_ESDP_SDP1)
2685 DPRINTK(DRV, CRIT,
2686 "Fan has stopped, replace the adapter\n");
2687 }
2688
e8e26350
PW		 2689 /*
2690 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2691 * arrived before interrupts were enabled but after probe. Such
2692 * devices wouldn't have their type identified yet. We need to
2693 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2694 * If we're not hot-pluggable SFP+, we just need to configure link
2695 * and bring it up.
2696 */
19343de2
DS		 2697 if (hw->phy.type == ixgbe_phy_unknown) {
2698 err = hw->phy.ops.identify(hw);
2699 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2700 /*
2701 * Take the device down and schedule the sfp tasklet
2702 * which will unregister_netdev and log it.
2703 */
19343de2 2704 ixgbe_down(adapter);
5da43c1a 2705 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2706 return err;
2707 }
e8e26350
PW		 2708 }
2709
2710 if (ixgbe_is_sfp(hw)) {
2711 ixgbe_sfp_link_config(adapter);
2712 } else {
2713 err = ixgbe_non_sfp_link_config(hw);
2714 if (err)
2715 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2716 }
0ecc061d 2717
c4cf55e5
PWJ		 2718 for (i = 0; i < adapter->num_tx_queues; i++)
2719 set_bit(__IXGBE_FDIR_INIT_DONE,
2720 &(adapter->tx_ring[i].reinit_state));
2721
1da100bb
PWJ		 2722 /* enable transmits */
2723 netif_tx_start_all_queues(netdev);
2724
9a799d71
AK		 2725 /* bring the link up in the watchdog, this could race with our first
2726 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2727 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2728 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2729 mod_timer(&adapter->watchdog_timer, jiffies);
2730 return 0;
2731}
2732
d4f80882
AV		 2733void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2734{
2735 WARN_ON(in_interrupt());
2736 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2737 msleep(1);
2738 ixgbe_down(adapter);
2739 ixgbe_up(adapter);
2740 clear_bit(__IXGBE_RESETTING, &adapter->state);
2741}
2742
9a799d71
AK		 2743int ixgbe_up(struct ixgbe_adapter *adapter)
2744{
2745 /* hardware has been reset, we need to reload some things */
2746 ixgbe_configure(adapter);
2747
2748 return ixgbe_up_complete(adapter);
2749}
2750
2751void ixgbe_reset(struct ixgbe_adapter *adapter)
2752{
c44ade9e 2753 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2754 int err;
2755
2756 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2757 switch (err) {
2758 case 0:
2759 case IXGBE_ERR_SFP_NOT_PRESENT:
2760 break;
2761 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2762 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2763 break;
794caeb2
PWJ		 2764 case IXGBE_ERR_EEPROM_VERSION:
2765 /* We are running on a pre-production device, log a warning */
2766 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2767 "adapter/LOM. Please be aware there may be issues "
2768 "associated with your hardware. If you are "
2769 "experiencing problems please contact your Intel or "
2770 "hardware representative who provided you with this "
2771 "hardware.\n");
2772 break;
da4dd0f7
PWJ		 2773 default:
2774 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2775 }
9a799d71
AK		 2776
2777 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2778 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2779}
2780
9a799d71
AK		 2781/**
2782 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2783 * @adapter: board private structure
2784 * @rx_ring: ring to free buffers from
2785 **/
2786static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2787 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2788{
2789 struct pci_dev *pdev = adapter->pdev;
2790 unsigned long size;
2791 unsigned int i;
2792
2793 /* Free all the Rx ring sk_buffs */
2794
2795 for (i = 0; i < rx_ring->count; i++) {
2796 struct ixgbe_rx_buffer *rx_buffer_info;
2797
2798 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2799 if (rx_buffer_info->dma) {
2800 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2801 rx_ring->rx_buf_len,
2802 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2803 rx_buffer_info->dma = 0;
2804 }
2805 if (rx_buffer_info->skb) {
f8212f97 2806 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2807 rx_buffer_info->skb = NULL;
f8212f97
AD		 2808 do {
2809 struct sk_buff *this = skb;
2810 skb = skb->prev;
2811 dev_kfree_skb(this);
2812 } while (skb);
9a799d71
AK		 2813 }
2814 if (!rx_buffer_info->page)
2815 continue;
4f57ca6e
JB		 2816 if (rx_buffer_info->page_dma) {
2817 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2818 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2819 rx_buffer_info->page_dma = 0;
2820 }
9a799d71
AK		 2821 put_page(rx_buffer_info->page);
2822 rx_buffer_info->page = NULL;
762f4c57 2823 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2824 }
2825
2826 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2827 memset(rx_ring->rx_buffer_info, 0, size);
2828
2829 /* Zero out the descriptor ring */
2830 memset(rx_ring->desc, 0, rx_ring->size);
2831
2832 rx_ring->next_to_clean = 0;
2833 rx_ring->next_to_use = 0;
2834
9891ca7c
JB		 2835 if (rx_ring->head)
2836 writel(0, adapter->hw.hw_addr + rx_ring->head);
2837 if (rx_ring->tail)
2838 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2839}
2840
2841/**
2842 * ixgbe_clean_tx_ring - Free Tx Buffers
2843 * @adapter: board private structure
2844 * @tx_ring: ring to be cleaned
2845 **/
2846static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2847 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2848{
2849 struct ixgbe_tx_buffer *tx_buffer_info;
2850 unsigned long size;
2851 unsigned int i;
2852
2853 /* Free all the Tx ring sk_buffs */
2854
2855 for (i = 0; i < tx_ring->count; i++) {
2856 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2857 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2858 }
2859
2860 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2861 memset(tx_ring->tx_buffer_info, 0, size);
2862
2863 /* Zero out the descriptor ring */
2864 memset(tx_ring->desc, 0, tx_ring->size);
2865
2866 tx_ring->next_to_use = 0;
2867 tx_ring->next_to_clean = 0;
2868
9891ca7c
JB		 2869 if (tx_ring->head)
2870 writel(0, adapter->hw.hw_addr + tx_ring->head);
2871 if (tx_ring->tail)
2872 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2873}
2874
2875/**
021230d4 2876 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2877 * @adapter: board private structure
2878 **/
021230d4 2879static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2880{
2881 int i;
2882
021230d4
AV		 2883 for (i = 0; i < adapter->num_rx_queues; i++)
2884 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2885}
2886
2887/**
021230d4 2888 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2889 * @adapter: board private structure
2890 **/
021230d4 2891static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2892{
2893 int i;
2894
021230d4
AV		 2895 for (i = 0; i < adapter->num_tx_queues; i++)
2896 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2897}
2898
2899void ixgbe_down(struct ixgbe_adapter *adapter)
2900{
2901 struct net_device *netdev = adapter->netdev;
7f821875 2902 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2903 u32 rxctrl;
7f821875
JB		 2904 u32 txdctl;
2905 int i, j;
9a799d71
AK		 2906
2907 /* signal that we are down to the interrupt handler */
2908 set_bit(__IXGBE_DOWN, &adapter->state);
2909
2910 /* disable receives */
7f821875
JB		 2911 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2912 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2913
2914 netif_tx_disable(netdev);
2915
7f821875 2916 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2917 msleep(10);
2918
7f821875
JB		 2919 netif_tx_stop_all_queues(netdev);
2920
9a799d71
AK		 2921 ixgbe_irq_disable(adapter);
2922
021230d4 2923 ixgbe_napi_disable_all(adapter);
7f821875 2924
9a799d71 2925 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2926 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2927
c4cf55e5
PWJ		 2928 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2929 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2930 cancel_work_sync(&adapter->fdir_reinit_task);
2931
7f821875
JB		 2932 /* disable transmits in the hardware now that interrupts are off */
2933 for (i = 0; i < adapter->num_tx_queues; i++) {
2934 j = adapter->tx_ring[i].reg_idx;
2935 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2936 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2937 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2938 }
88512539
PW		 2939 /* Disable the Tx DMA engine on 82599 */
2940 if (hw->mac.type == ixgbe_mac_82599EB)
2941 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2942 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2943 ~IXGBE_DMATXCTL_TE));
7f821875 2944
9a799d71 2945 netif_carrier_off(netdev);
9a799d71 2946
6f4a0e45
PL		 2947 if (!pci_channel_offline(adapter->pdev))
2948 ixgbe_reset(adapter);
9a799d71
AK		 2949 ixgbe_clean_all_tx_rings(adapter);
2950 ixgbe_clean_all_rx_rings(adapter);
2951
5dd2d332 2952#ifdef CONFIG_IXGBE_DCA
96b0e0f6 2953 /* since we reset the hardware DCA settings were cleared */
e35ec126 2954 ixgbe_setup_dca(adapter);
96b0e0f6 2955#endif
9a799d71
AK		 2956}
2957
9a799d71 2958/**
021230d4
AV		 2959 * ixgbe_poll - NAPI Rx polling callback
2960 * @napi: structure for representing this polling device
2961 * @budget: how many packets driver is allowed to clean
2962 *
2963 * This function is used for legacy and MSI, NAPI mode
9a799d71 2964 **/
021230d4 2965static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2966{
9a1a69ad
JB		 2967 struct ixgbe_q_vector *q_vector =
2968 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2969 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2970 int tx_clean_complete, work_done = 0;
9a799d71 2971
5dd2d332 2972#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2974 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2975 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2976 }
2977#endif
2978
fe49f04a 2979 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 2980 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2981
9a1a69ad 2982 if (!tx_clean_complete)
d2c7ddd6
DM		 2983 work_done = budget;
2984
53e52c72
DM		 2985 /* If budget not fully consumed, exit the polling mode */
2986 if (work_done < budget) {
288379f0 2987 napi_complete(napi);
509ee935 2988 if (adapter->itr_setting & 1)
f494e8fa 2989 ixgbe_set_itr(adapter);
d4f80882 2990 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2991 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2992 }
9a799d71
AK		 2993 return work_done;
2994}
2995
2996/**
2997 * ixgbe_tx_timeout - Respond to a Tx Hang
2998 * @netdev: network interface device structure
2999 **/
3000static void ixgbe_tx_timeout(struct net_device *netdev)
3001{
3002 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3003
3004 /* Do the reset outside of interrupt context */
3005 schedule_work(&adapter->reset_task);
3006}
3007
3008static void ixgbe_reset_task(struct work_struct *work)
3009{
3010 struct ixgbe_adapter *adapter;
3011 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3012
2f90b865
AD		 3013 /* If we're already down or resetting, just bail */
3014 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3015 test_bit(__IXGBE_RESETTING, &adapter->state))
3016 return;
3017
9a799d71
AK		 3018 adapter->tx_timeout_count++;
3019
d4f80882 3020 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3021}
3022
bc97114d
PWJ		 3023#ifdef CONFIG_IXGBE_DCB
3024static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3025{
bc97114d 3026 bool ret = false;
0cefafad 3027 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3028
0cefafad
JB		 3029 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3030 return ret;
3031
3032 f->mask = 0x7 << 3;
3033 adapter->num_rx_queues = f->indices;
3034 adapter->num_tx_queues = f->indices;
3035 ret = true;
2f90b865 3036
bc97114d
PWJ		 3037 return ret;
3038}
3039#endif
3040
4df10466
JB		 3041/**
3042 * ixgbe_set_rss_queues: Allocate queues for RSS
3043 * @adapter: board private structure to initialize
3044 *
3045 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3046 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3047 *
3048 **/
bc97114d
PWJ		 3049static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3050{
3051 bool ret = false;
0cefafad 3052 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3053
3054 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3055 f->mask = 0xF;
3056 adapter->num_rx_queues = f->indices;
3057 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3058 ret = true;
3059 } else {
bc97114d 3060 ret = false;
b9804972
JB		 3061 }
3062
bc97114d
PWJ		 3063 return ret;
3064}
3065
c4cf55e5
PWJ		 3066/**
3067 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3068 * @adapter: board private structure to initialize
3069 *
3070 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3071 * to the original CPU that initiated the Tx session. This runs in addition
3072 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3073 * Rx load across CPUs using RSS.
3074 *
3075 **/
3076static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3077{
3078 bool ret = false;
3079 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3080
3081 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3082 f_fdir->mask = 0;
3083
3084 /* Flow Director must have RSS enabled */
3085 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3086 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3087 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3088 adapter->num_tx_queues = f_fdir->indices;
3089 adapter->num_rx_queues = f_fdir->indices;
3090 ret = true;
3091 } else {
3092 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3093 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3094 }
3095 return ret;
3096}
3097
0331a832
YZ		 3098#ifdef IXGBE_FCOE
3099/**
3100 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3101 * @adapter: board private structure to initialize
3102 *
3103 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3104 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3105 * rx queues out of the max number of rx queues, instead, it is used as the
3106 * index of the first rx queue used by FCoE.
3107 *
3108 **/
3109static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3110{
3111 bool ret = false;
3112 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3113
3114 f->indices = min((int)num_online_cpus(), f->indices);
3115 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3116 adapter->num_rx_queues = 1;
3117 adapter->num_tx_queues = 1;
0331a832
YZ		 3118#ifdef CONFIG_IXGBE_DCB
3119 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3120 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3121 ixgbe_set_dcb_queues(adapter);
3122 }
3123#endif
3124 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3125 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3126 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3127 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3128 ixgbe_set_fdir_queues(adapter);
3129 else
3130 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3131 }
3132 /* adding FCoE rx rings to the end */
3133 f->mask = adapter->num_rx_queues;
3134 adapter->num_rx_queues += f->indices;
8de8b2e6 3135 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3136
3137 ret = true;
3138 }
3139
3140 return ret;
3141}
3142
3143#endif /* IXGBE_FCOE */
4df10466
JB		 3144/*
3145 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3146 * @adapter: board private structure to initialize
3147 *
3148 * This is the top level queue allocation routine. The order here is very
3149 * important, starting with the "most" number of features turned on at once,
3150 * and ending with the smallest set of features. This way large combinations
3151 * can be allocated if they're turned on, and smaller combinations are the
3152 * fallthrough conditions.
3153 *
3154 **/
bc97114d
PWJ		 3155static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3156{
0331a832
YZ		 3157#ifdef IXGBE_FCOE
3158 if (ixgbe_set_fcoe_queues(adapter))
3159 goto done;
3160
3161#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3162#ifdef CONFIG_IXGBE_DCB
3163 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3164 goto done;
bc97114d
PWJ		 3165
3166#endif
c4cf55e5
PWJ		 3167 if (ixgbe_set_fdir_queues(adapter))
3168 goto done;
3169
bc97114d 3170 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3171 goto done;
3172
3173 /* fallback to base case */
3174 adapter->num_rx_queues = 1;
3175 adapter->num_tx_queues = 1;
3176
3177done:
3178 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3179 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3180}
3181
021230d4 3182static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3183 int vectors)
021230d4
AV		 3184{
3185 int err, vector_threshold;
3186
3187 /* We'll want at least 3 (vector_threshold):
3188 * 1) TxQ[0] Cleanup
3189 * 2) RxQ[0] Cleanup
3190 * 3) Other (Link Status Change, etc.)
3191 * 4) TCP Timer (optional)
3192 */
3193 vector_threshold = MIN_MSIX_COUNT;
3194
3195 /* The more we get, the more we will assign to Tx/Rx Cleanup
3196 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3197 * Right now, we simply care about how many we'll get; we'll
3198 * set them up later while requesting irq's.
3199 */
3200 while (vectors >= vector_threshold) {
3201 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3202 vectors);
021230d4
AV		 3203 if (!err) /* Success in acquiring all requested vectors. */
3204 break;
3205 else if (err < 0)
3206 vectors = 0; /* Nasty failure, quit now */
3207 else /* err == number of vectors we should try again with */
3208 vectors = err;
3209 }
3210
3211 if (vectors < vector_threshold) {
3212 /* Can't allocate enough MSI-X interrupts? Oh well.
3213 * This just means we'll go with either a single MSI
3214 * vector or fall back to legacy interrupts.
3215 */
3216 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3217 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3218 kfree(adapter->msix_entries);
3219 adapter->msix_entries = NULL;
021230d4
AV		 3220 } else {
3221 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3222 /*
3223 * Adjust for only the vectors we'll use, which is minimum
3224 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3225 * vectors we were allocated.
3226 */
3227 adapter->num_msix_vectors = min(vectors,
3228 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3229 }
3230}
3231
021230d4 3232/**
bc97114d 3233 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3234 * @adapter: board private structure to initialize
3235 *
bc97114d
PWJ		 3236 * Cache the descriptor ring offsets for RSS to the assigned rings.
3237 *
021230d4 3238 **/
bc97114d 3239static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3240{
bc97114d
PWJ		 3241 int i;
3242 bool ret = false;
3243
3244 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3245 for (i = 0; i < adapter->num_rx_queues; i++)
3246 adapter->rx_ring[i].reg_idx = i;
3247 for (i = 0; i < adapter->num_tx_queues; i++)
3248 adapter->tx_ring[i].reg_idx = i;
3249 ret = true;
3250 } else {
3251 ret = false;
3252 }
3253
3254 return ret;
3255}
3256
3257#ifdef CONFIG_IXGBE_DCB
3258/**
3259 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3260 * @adapter: board private structure to initialize
3261 *
3262 * Cache the descriptor ring offsets for DCB to the assigned rings.
3263 *
3264 **/
3265static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3266{
3267 int i;
3268 bool ret = false;
3269 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3270
3271 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3272 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3273 /* the number of queues is assumed to be symmetric */
3274 for (i = 0; i < dcb_i; i++) {
3275 adapter->rx_ring[i].reg_idx = i << 3;
3276 adapter->tx_ring[i].reg_idx = i << 2;
3277 }
bc97114d 3278 ret = true;
e8e26350 3279 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3280 if (dcb_i == 8) {
3281 /*
3282 * Tx TC0 starts at: descriptor queue 0
3283 * Tx TC1 starts at: descriptor queue 32
3284 * Tx TC2 starts at: descriptor queue 64
3285 * Tx TC3 starts at: descriptor queue 80
3286 * Tx TC4 starts at: descriptor queue 96
3287 * Tx TC5 starts at: descriptor queue 104
3288 * Tx TC6 starts at: descriptor queue 112
3289 * Tx TC7 starts at: descriptor queue 120
3290 *
3291 * Rx TC0-TC7 are offset by 16 queues each
3292 */
3293 for (i = 0; i < 3; i++) {
3294 adapter->tx_ring[i].reg_idx = i << 5;
3295 adapter->rx_ring[i].reg_idx = i << 4;
3296 }
3297 for ( ; i < 5; i++) {
3298 adapter->tx_ring[i].reg_idx =
3299 ((i + 2) << 4);
3300 adapter->rx_ring[i].reg_idx = i << 4;
3301 }
3302 for ( ; i < dcb_i; i++) {
3303 adapter->tx_ring[i].reg_idx =
3304 ((i + 8) << 3);
3305 adapter->rx_ring[i].reg_idx = i << 4;
3306 }
3307
3308 ret = true;
3309 } else if (dcb_i == 4) {
3310 /*
3311 * Tx TC0 starts at: descriptor queue 0
3312 * Tx TC1 starts at: descriptor queue 64
3313 * Tx TC2 starts at: descriptor queue 96
3314 * Tx TC3 starts at: descriptor queue 112
3315 *
3316 * Rx TC0-TC3 are offset by 32 queues each
3317 */
3318 adapter->tx_ring[0].reg_idx = 0;
3319 adapter->tx_ring[1].reg_idx = 64;
3320 adapter->tx_ring[2].reg_idx = 96;
3321 adapter->tx_ring[3].reg_idx = 112;
3322 for (i = 0 ; i < dcb_i; i++)
3323 adapter->rx_ring[i].reg_idx = i << 5;
3324
3325 ret = true;
3326 } else {
3327 ret = false;
e8e26350 3328 }
bc97114d
PWJ		 3329 } else {
3330 ret = false;
021230d4 3331 }
bc97114d
PWJ		 3332 } else {
3333 ret = false;
021230d4 3334 }
bc97114d
PWJ		 3335
3336 return ret;
3337}
3338#endif
3339
c4cf55e5
PWJ		 3340/**
3341 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3342 * @adapter: board private structure to initialize
3343 *
3344 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3345 *
3346 **/
3347static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3348{
3349 int i;
3350 bool ret = false;
3351
3352 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3353 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3354 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3355 for (i = 0; i < adapter->num_rx_queues; i++)
3356 adapter->rx_ring[i].reg_idx = i;
3357 for (i = 0; i < adapter->num_tx_queues; i++)
3358 adapter->tx_ring[i].reg_idx = i;
3359 ret = true;
3360 }
3361
3362 return ret;
3363}
3364
0331a832
YZ		 3365#ifdef IXGBE_FCOE
3366/**
3367 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3368 * @adapter: board private structure to initialize
3369 *
3370 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3371 *
3372 */
3373static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3374{
8de8b2e6 3375 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3376 bool ret = false;
3377 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3378
3379 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3380#ifdef CONFIG_IXGBE_DCB
3381 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3382 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3383
0331a832 3384 ixgbe_cache_ring_dcb(adapter);
8de8b2e6
YZ		 3385 /* find out queues in TC for FCoE */
3386 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3387 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3388 /*
3389 * In 82599, the number of Tx queues for each traffic
3390 * class for both 8-TC and 4-TC modes are:
3391 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3392 * 8 TCs: 32 32 16 16 8 8 8 8
3393 * 4 TCs: 64 64 32 32
3394 * We have max 8 queues for FCoE, where 8 the is
3395 * FCoE redirection table size. If TC for FCoE is
3396 * less than or equal to TC3, we have enough queues
3397 * to add max of 8 queues for FCoE, so we start FCoE
3398 * tx descriptor from the next one, i.e., reg_idx + 1.
3399 * If TC for FCoE is above TC3, implying 8 TC mode,
3400 * and we need 8 for FCoE, we have to take all queues
3401 * in that traffic class for FCoE.
3402 */
3403 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3404 fcoe_tx_i--;
0331a832
YZ		 3405 }
3406#endif /* CONFIG_IXGBE_DCB */
3407 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3408 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3409 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3410 ixgbe_cache_ring_fdir(adapter);
3411 else
3412 ixgbe_cache_ring_rss(adapter);
3413
8de8b2e6
YZ		 3414 fcoe_rx_i = f->mask;
3415 fcoe_tx_i = f->mask;
3416 }
3417 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3418 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3419 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
0331a832 3420 }
0331a832
YZ		 3421 ret = true;
3422 }
3423 return ret;
3424}
3425
3426#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3427/**
3428 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3429 * @adapter: board private structure to initialize
3430 *
3431 * Once we know the feature-set enabled for the device, we'll cache
3432 * the register offset the descriptor ring is assigned to.
3433 *
3434 * Note, the order the various feature calls is important. It must start with
3435 * the "most" features enabled at the same time, then trickle down to the
3436 * least amount of features turned on at once.
3437 **/
3438static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3439{
3440 /* start with default case */
3441 adapter->rx_ring[0].reg_idx = 0;
3442 adapter->tx_ring[0].reg_idx = 0;
3443
0331a832
YZ		 3444#ifdef IXGBE_FCOE
3445 if (ixgbe_cache_ring_fcoe(adapter))
3446 return;
3447
3448#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3449#ifdef CONFIG_IXGBE_DCB
3450 if (ixgbe_cache_ring_dcb(adapter))
3451 return;
3452
3453#endif
c4cf55e5
PWJ		 3454 if (ixgbe_cache_ring_fdir(adapter))
3455 return;
3456
bc97114d
PWJ		 3457 if (ixgbe_cache_ring_rss(adapter))
3458 return;
021230d4
AV		 3459}
3460
9a799d71
AK		 3461/**
3462 * ixgbe_alloc_queues - Allocate memory for all rings
3463 * @adapter: board private structure to initialize
3464 *
3465 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3466 * number of queues at compile-time. The polling_netdev array is
3467 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3468 **/
2f90b865 3469static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3470{
3471 int i;
3472
3473 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3474 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3475 if (!adapter->tx_ring)
021230d4 3476 goto err_tx_ring_allocation;
9a799d71
AK		 3477
3478 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3479 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3480 if (!adapter->rx_ring)
3481 goto err_rx_ring_allocation;
9a799d71 3482
021230d4 3483 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3484 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3485 adapter->tx_ring[i].queue_index = i;
3486 }
b9804972 3487
9a799d71 3488 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3489 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3490 adapter->rx_ring[i].queue_index = i;
3491 }
3492
3493 ixgbe_cache_ring_register(adapter);
3494
3495 return 0;
3496
3497err_rx_ring_allocation:
3498 kfree(adapter->tx_ring);
3499err_tx_ring_allocation:
3500 return -ENOMEM;
3501}
3502
3503/**
3504 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3505 * @adapter: board private structure to initialize
3506 *
3507 * Attempt to configure the interrupts using the best available
3508 * capabilities of the hardware and the kernel.
3509 **/
feea6a57 3510static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3511{
8be0e467 3512 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3513 int err = 0;
3514 int vector, v_budget;
3515
3516 /*
3517 * It's easy to be greedy for MSI-X vectors, but it really
3518 * doesn't do us much good if we have a lot more vectors
3519 * than CPU's. So let's be conservative and only ask for
3520 * (roughly) twice the number of vectors as there are CPU's.
3521 */
3522 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3523 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3524
3525 /*
3526 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3527 * hw.mac->max_msix_vectors vectors. With features
3528 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3529 * descriptor queues supported by our device. Thus, we cap it off in
3530 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3531 */
8be0e467 3532 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3533
3534 /* A failure in MSI-X entry allocation isn't fatal, but it does
3535 * mean we disable MSI-X capabilities of the adapter. */
3536 adapter->msix_entries = kcalloc(v_budget,
b4617240 3537 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3538 if (adapter->msix_entries) {
3539 for (vector = 0; vector < v_budget; vector++)
3540 adapter->msix_entries[vector].entry = vector;
021230d4 3541
7a921c93 3542 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3543
7a921c93
AD		 3544 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3545 goto out;
3546 }
021230d4 3547
7a921c93
AD		 3548 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3549 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3550 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3551 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3552 adapter->atr_sample_rate = 0;
7a921c93 3553 ixgbe_set_num_queues(adapter);
021230d4 3554
021230d4
AV		 3555 err = pci_enable_msi(adapter->pdev);
3556 if (!err) {
3557 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3558 } else {
3559 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3560 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3561 /* reset err */
3562 err = 0;
3563 }
3564
3565out:
021230d4
AV		 3566 return err;
3567}
3568
7a921c93
AD		 3569/**
3570 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3571 * @adapter: board private structure to initialize
3572 *
3573 * We allocate one q_vector per queue interrupt. If allocation fails we
3574 * return -ENOMEM.
3575 **/
3576static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3577{
3578 int q_idx, num_q_vectors;
3579 struct ixgbe_q_vector *q_vector;
3580 int napi_vectors;
3581 int (*poll)(struct napi_struct *, int);
3582
3583 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3584 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3585 napi_vectors = adapter->num_rx_queues;
91281fd3 3586 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3587 } else {
3588 num_q_vectors = 1;
3589 napi_vectors = 1;
3590 poll = &ixgbe_poll;
3591 }
3592
3593 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3594 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3595 if (!q_vector)
3596 goto err_out;
3597 q_vector->adapter = adapter;
7a921c93 3598 q_vector->eitr = adapter->eitr_param;
fe49f04a 3599 q_vector->v_idx = q_idx;
91281fd3 3600 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3601 adapter->q_vector[q_idx] = q_vector;
3602 }
3603
3604 return 0;
3605
3606err_out:
3607 while (q_idx) {
3608 q_idx--;
3609 q_vector = adapter->q_vector[q_idx];
3610 netif_napi_del(&q_vector->napi);
3611 kfree(q_vector);
3612 adapter->q_vector[q_idx] = NULL;
3613 }
3614 return -ENOMEM;
3615}
3616
3617/**
3618 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3619 * @adapter: board private structure to initialize
3620 *
3621 * This function frees the memory allocated to the q_vectors. In addition if
3622 * NAPI is enabled it will delete any references to the NAPI struct prior
3623 * to freeing the q_vector.
3624 **/
3625static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3626{
3627 int q_idx, num_q_vectors;
7a921c93 3628
91281fd3 3629 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3630 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3631 else
7a921c93 3632 num_q_vectors = 1;
7a921c93
AD		 3633
3634 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3635 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3636 adapter->q_vector[q_idx] = NULL;
91281fd3 3637 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3638 kfree(q_vector);
3639 }
3640}
3641
7b25cdba 3642static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3643{
3644 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3645 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3646 pci_disable_msix(adapter->pdev);
3647 kfree(adapter->msix_entries);
3648 adapter->msix_entries = NULL;
3649 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3650 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3651 pci_disable_msi(adapter->pdev);
3652 }
3653 return;
3654}
3655
3656/**
3657 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3658 * @adapter: board private structure to initialize
3659 *
3660 * We determine which interrupt scheme to use based on...
3661 * - Kernel support (MSI, MSI-X)
3662 * - which can be user-defined (via MODULE_PARAM)
3663 * - Hardware queue count (num_*_queues)
3664 * - defined by miscellaneous hardware support/features (RSS, etc.)
3665 **/
2f90b865 3666int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3667{
3668 int err;
3669
3670 /* Number of supported queues */
3671 ixgbe_set_num_queues(adapter);
3672
021230d4
AV		 3673 err = ixgbe_set_interrupt_capability(adapter);
3674 if (err) {
3675 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3676 goto err_set_interrupt;
9a799d71
AK		 3677 }
3678
7a921c93
AD		 3679 err = ixgbe_alloc_q_vectors(adapter);
3680 if (err) {
3681 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3682 "vectors\n");
3683 goto err_alloc_q_vectors;
3684 }
3685
3686 err = ixgbe_alloc_queues(adapter);
3687 if (err) {
3688 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3689 goto err_alloc_queues;
3690 }
3691
021230d4 3692 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3693 "Tx Queue count = %u\n",
3694 (adapter->num_rx_queues > 1) ? "Enabled" :
3695 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3696
3697 set_bit(__IXGBE_DOWN, &adapter->state);
3698
9a799d71 3699 return 0;
021230d4 3700
7a921c93
AD		 3701err_alloc_queues:
3702 ixgbe_free_q_vectors(adapter);
3703err_alloc_q_vectors:
3704 ixgbe_reset_interrupt_capability(adapter);
021230d4 3705err_set_interrupt:
7a921c93
AD		 3706 return err;
3707}
3708
3709/**
3710 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3711 * @adapter: board private structure to clear interrupt scheme on
3712 *
3713 * We go through and clear interrupt specific resources and reset the structure
3714 * to pre-load conditions
3715 **/
3716void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3717{
021230d4
AV		 3718 kfree(adapter->tx_ring);
3719 kfree(adapter->rx_ring);
7a921c93
AD		 3720 adapter->tx_ring = NULL;
3721 adapter->rx_ring = NULL;
3722
3723 ixgbe_free_q_vectors(adapter);
3724 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3725}
3726
c4900be0
DS		 3727/**
3728 * ixgbe_sfp_timer - worker thread to find a missing module
3729 * @data: pointer to our adapter struct
3730 **/
3731static void ixgbe_sfp_timer(unsigned long data)
3732{
3733 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3734
4df10466
JB		 3735 /*
3736 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3737 * delays that sfp+ detection requires
3738 */
3739 schedule_work(&adapter->sfp_task);
3740}
3741
3742/**
3743 * ixgbe_sfp_task - worker thread to find a missing module
3744 * @work: pointer to work_struct containing our data
3745 **/
3746static void ixgbe_sfp_task(struct work_struct *work)
3747{
3748 struct ixgbe_adapter *adapter = container_of(work,
3749 struct ixgbe_adapter,
3750 sfp_task);
3751 struct ixgbe_hw *hw = &adapter->hw;
3752
3753 if ((hw->phy.type == ixgbe_phy_nl) &&
3754 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3755 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 3756 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 3757 goto reschedule;
3758 ret = hw->phy.ops.reset(hw);
3759 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 3760 dev_err(&adapter->pdev->dev, "failed to initialize "
3761 "because an unsupported SFP+ module type "
3762 "was detected.\n"
3763 "Reload the driver after installing a "
3764 "supported module.\n");
c4900be0
DS		 3765 unregister_netdev(adapter->netdev);
3766 } else {
3767 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3768 hw->phy.sfp_type);
3769 }
3770 /* don't need this routine any more */
3771 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3772 }
3773 return;
3774reschedule:
3775 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3776 mod_timer(&adapter->sfp_timer,
3777 round_jiffies(jiffies + (2 * HZ)));
3778}
3779
9a799d71
AK		 3780/**
3781 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3782 * @adapter: board private structure to initialize
3783 *
3784 * ixgbe_sw_init initializes the Adapter private data structure.
3785 * Fields are initialized based on PCI device information and
3786 * OS network device settings (MTU size).
3787 **/
3788static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3789{
3790 struct ixgbe_hw *hw = &adapter->hw;
3791 struct pci_dev *pdev = adapter->pdev;
021230d4 3792 unsigned int rss;
7a6b6f51 3793#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3794 int j;
3795 struct tc_configuration *tc;
3796#endif
021230d4 3797
c44ade9e
JB		 3798 /* PCI config space info */
3799
3800 hw->vendor_id = pdev->vendor;
3801 hw->device_id = pdev->device;
3802 hw->revision_id = pdev->revision;
3803 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3804 hw->subsystem_device_id = pdev->subsystem_device;
3805
021230d4
AV		 3806 /* Set capability flags */
3807 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3808 adapter->ring_feature[RING_F_RSS].indices = rss;
3809 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3810 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3811 if (hw->mac.type == ixgbe_mac_82598EB) {
3812 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3813 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3814 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3815 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3816 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 3817 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3818 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 3819 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3820 adapter->ring_feature[RING_F_FDIR].indices =
3821 IXGBE_MAX_FDIR_INDICES;
3822 adapter->atr_sample_rate = 20;
3823 adapter->fdir_pballoc = 0;
eacd73f7 3824#ifdef IXGBE_FCOE
0d551589
YZ		 3825 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3826 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3827 adapter->ring_feature[RING_F_FCOE].indices = 0;
6ee16520
YZ		 3828 /* Default traffic class to use for FCoE */
3829 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
eacd73f7 3830#endif /* IXGBE_FCOE */
f8212f97 3831 }
2f90b865 3832
7a6b6f51 3833#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3834 /* Configure DCB traffic classes */
3835 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3836 tc = &adapter->dcb_cfg.tc_config[j];
3837 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3838 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3839 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3840 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3841 tc->dcb_pfc = pfc_disabled;
3842 }
3843 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3844 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3845 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3846 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3847 adapter->dcb_cfg.round_robin_enable = false;
3848 adapter->dcb_set_bitmap = 0x00;
3849 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3850 adapter->ring_feature[RING_F_DCB].indices);
3851
3852#endif
9a799d71
AK		 3853
3854 /* default flow control settings */
cd7664f6 3855 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3856 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3857#ifdef CONFIG_DCB
3858 adapter->last_lfc_mode = hw->fc.current_mode;
3859#endif
2b9ade93
JB		 3860 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3861 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3862 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3863 hw->fc.send_xon = true;
71fd570b 3864 hw->fc.disable_fc_autoneg = false;
9a799d71 3865
30efa5a3
JB		 3866 /* enable itr by default in dynamic mode */
3867 adapter->itr_setting = 1;
3868 adapter->eitr_param = 20000;
3869
3870 /* set defaults for eitr in MegaBytes */
3871 adapter->eitr_low = 10;
3872 adapter->eitr_high = 20;
3873
3874 /* set default ring sizes */
3875 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3876 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3877
9a799d71 3878 /* initialize eeprom parameters */
c44ade9e 3879 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3880 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3881 return -EIO;
3882 }
3883
021230d4 3884 /* enable rx csum by default */
9a799d71
AK		 3885 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3886
9a799d71
AK		 3887 set_bit(__IXGBE_DOWN, &adapter->state);
3888
3889 return 0;
3890}
3891
3892/**
3893 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3894 * @adapter: board private structure
3a581073 3895 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3896 *
3897 * Return 0 on success, negative on failure
3898 **/
3899int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3900 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3901{
3902 struct pci_dev *pdev = adapter->pdev;
3903 int size;
3904
3a581073
JB		 3905 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3906 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3907 if (!tx_ring->tx_buffer_info)
3908 goto err;
3a581073 3909 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3910
3911 /* round up to nearest 4K */
12207e49 3912 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3913 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3914
3a581073
JB		 3915 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3916 &tx_ring->dma);
e01c31a5
JB		 3917 if (!tx_ring->desc)
3918 goto err;
9a799d71 3919
3a581073
JB		 3920 tx_ring->next_to_use = 0;
3921 tx_ring->next_to_clean = 0;
3922 tx_ring->work_limit = tx_ring->count;
9a799d71 3923 return 0;
e01c31a5
JB		 3924
3925err:
3926 vfree(tx_ring->tx_buffer_info);
3927 tx_ring->tx_buffer_info = NULL;
3928 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3929 "descriptor ring\n");
3930 return -ENOMEM;
9a799d71
AK		 3931}
3932
69888674
AD		 3933/**
3934 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3935 * @adapter: board private structure
3936 *
3937 * If this function returns with an error, then it's possible one or
3938 * more of the rings is populated (while the rest are not). It is the
3939 * callers duty to clean those orphaned rings.
3940 *
3941 * Return 0 on success, negative on failure
3942 **/
3943static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3944{
3945 int i, err = 0;
3946
3947 for (i = 0; i < adapter->num_tx_queues; i++) {
3948 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3949 if (!err)
3950 continue;
3951 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3952 break;
3953 }
3954
3955 return err;
3956}
3957
9a799d71
AK		 3958/**
3959 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3960 * @adapter: board private structure
3a581073 3961 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3962 *
3963 * Returns 0 on success, negative on failure
3964 **/
3965int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3966 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3967{
3968 struct pci_dev *pdev = adapter->pdev;
021230d4 3969 int size;
9a799d71 3970
3a581073
JB		 3971 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3972 rx_ring->rx_buffer_info = vmalloc(size);
3973 if (!rx_ring->rx_buffer_info) {
9a799d71 3974 DPRINTK(PROBE, ERR,
b4617240 3975 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3976 goto alloc_failed;
9a799d71 3977 }
3a581073 3978 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3979
9a799d71 3980 /* Round up to nearest 4K */
3a581073
JB		 3981 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3982 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3983
3a581073 3984 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3985
3a581073 3986 if (!rx_ring->desc) {
9a799d71 3987 DPRINTK(PROBE, ERR,
b4617240 3988 "Memory allocation failed for the rx desc ring\n");
3a581073 3989 vfree(rx_ring->rx_buffer_info);
177db6ff 3990 goto alloc_failed;
9a799d71
AK		 3991 }
3992
3a581073
JB		 3993 rx_ring->next_to_clean = 0;
3994 rx_ring->next_to_use = 0;
9a799d71
AK		 3995
3996 return 0;
177db6ff
MC		 3997
3998alloc_failed:
177db6ff 3999 return -ENOMEM;
9a799d71
AK		 4000}
4001
69888674
AD		 4002/**
4003 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4004 * @adapter: board private structure
4005 *
4006 * If this function returns with an error, then it's possible one or
4007 * more of the rings is populated (while the rest are not). It is the
4008 * callers duty to clean those orphaned rings.
4009 *
4010 * Return 0 on success, negative on failure
4011 **/
4012
4013static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4014{
4015 int i, err = 0;
4016
4017 for (i = 0; i < adapter->num_rx_queues; i++) {
4018 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4019 if (!err)
4020 continue;
4021 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4022 break;
4023 }
4024
4025 return err;
4026}
4027
9a799d71
AK		 4028/**
4029 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4030 * @adapter: board private structure
4031 * @tx_ring: Tx descriptor ring for a specific queue
4032 *
4033 * Free all transmit software resources
4034 **/
c431f97e
JB		 4035void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4036 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4037{
4038 struct pci_dev *pdev = adapter->pdev;
4039
4040 ixgbe_clean_tx_ring(adapter, tx_ring);
4041
4042 vfree(tx_ring->tx_buffer_info);
4043 tx_ring->tx_buffer_info = NULL;
4044
4045 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4046
4047 tx_ring->desc = NULL;
4048}
4049
4050/**
4051 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4052 * @adapter: board private structure
4053 *
4054 * Free all transmit software resources
4055 **/
4056static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4057{
4058 int i;
4059
4060 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4061 if (adapter->tx_ring[i].desc)
4062 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4063}
4064
4065/**
b4617240 4066 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4067 * @adapter: board private structure
4068 * @rx_ring: ring to clean the resources from
4069 *
4070 * Free all receive software resources
4071 **/
c431f97e
JB		 4072void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4073 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4074{
4075 struct pci_dev *pdev = adapter->pdev;
4076
4077 ixgbe_clean_rx_ring(adapter, rx_ring);
4078
4079 vfree(rx_ring->rx_buffer_info);
4080 rx_ring->rx_buffer_info = NULL;
4081
4082 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4083
4084 rx_ring->desc = NULL;
4085}
4086
4087/**
4088 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4089 * @adapter: board private structure
4090 *
4091 * Free all receive software resources
4092 **/
4093static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4094{
4095 int i;
4096
4097 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4098 if (adapter->rx_ring[i].desc)
4099 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4100}
4101
9a799d71
AK		 4102/**
4103 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4104 * @netdev: network interface device structure
4105 * @new_mtu: new value for maximum frame size
4106 *
4107 * Returns 0 on success, negative on failure
4108 **/
4109static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4110{
4111 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4112 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4113
42c783c5
JB		 4114 /* MTU < 68 is an error and causes problems on some kernels */
4115 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4116 return -EINVAL;
4117
021230d4 4118 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4119 netdev->mtu, new_mtu);
021230d4 4120 /* must set new MTU before calling down or up */
9a799d71
AK		 4121 netdev->mtu = new_mtu;
4122
d4f80882
AV		 4123 if (netif_running(netdev))
4124 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4125
4126 return 0;
4127}
4128
4129/**
4130 * ixgbe_open - Called when a network interface is made active
4131 * @netdev: network interface device structure
4132 *
4133 * Returns 0 on success, negative value on failure
4134 *
4135 * The open entry point is called when a network interface is made
4136 * active by the system (IFF_UP). At this point all resources needed
4137 * for transmit and receive operations are allocated, the interrupt
4138 * handler is registered with the OS, the watchdog timer is started,
4139 * and the stack is notified that the interface is ready.
4140 **/
4141static int ixgbe_open(struct net_device *netdev)
4142{
4143 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4144 int err;
4bebfaa5
AK		 4145
4146 /* disallow open during test */
4147 if (test_bit(__IXGBE_TESTING, &adapter->state))
4148 return -EBUSY;
9a799d71 4149
54386467
JB		 4150 netif_carrier_off(netdev);
4151
9a799d71
AK		 4152 /* allocate transmit descriptors */
4153 err = ixgbe_setup_all_tx_resources(adapter);
4154 if (err)
4155 goto err_setup_tx;
4156
9a799d71
AK		 4157 /* allocate receive descriptors */
4158 err = ixgbe_setup_all_rx_resources(adapter);
4159 if (err)
4160 goto err_setup_rx;
4161
4162 ixgbe_configure(adapter);
4163
021230d4 4164 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4165 if (err)
4166 goto err_req_irq;
4167
9a799d71
AK		 4168 err = ixgbe_up_complete(adapter);
4169 if (err)
4170 goto err_up;
4171
d55b53ff
JK		 4172 netif_tx_start_all_queues(netdev);
4173
9a799d71
AK		 4174 return 0;
4175
4176err_up:
5eba3699 4177 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4178 ixgbe_free_irq(adapter);
4179err_req_irq:
9a799d71 4180err_setup_rx:
a20a1199 4181 ixgbe_free_all_rx_resources(adapter);
9a799d71 4182err_setup_tx:
a20a1199 4183 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4184 ixgbe_reset(adapter);
4185
4186 return err;
4187}
4188
4189/**
4190 * ixgbe_close - Disables a network interface
4191 * @netdev: network interface device structure
4192 *
4193 * Returns 0, this is not allowed to fail
4194 *
4195 * The close entry point is called when an interface is de-activated
4196 * by the OS. The hardware is still under the drivers control, but
4197 * needs to be disabled. A global MAC reset is issued to stop the
4198 * hardware, and all transmit and receive resources are freed.
4199 **/
4200static int ixgbe_close(struct net_device *netdev)
4201{
4202 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4203
4204 ixgbe_down(adapter);
4205 ixgbe_free_irq(adapter);
4206
4207 ixgbe_free_all_tx_resources(adapter);
4208 ixgbe_free_all_rx_resources(adapter);
4209
5eba3699 4210 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4211
4212 return 0;
4213}
4214
b3c8b4ba
AD		 4215#ifdef CONFIG_PM
4216static int ixgbe_resume(struct pci_dev *pdev)
4217{
4218 struct net_device *netdev = pci_get_drvdata(pdev);
4219 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4220 u32 err;
4221
4222 pci_set_power_state(pdev, PCI_D0);
4223 pci_restore_state(pdev);
9ce77666 4224
4225 err = pci_enable_device_mem(pdev);
b3c8b4ba 4226 if (err) {
69888674 4227 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4228 "suspend\n");
4229 return err;
4230 }
4231 pci_set_master(pdev);
4232
dd4d8ca6 4233 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4234
4235 err = ixgbe_init_interrupt_scheme(adapter);
4236 if (err) {
4237 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4238 "device\n");
4239 return err;
4240 }
4241
b3c8b4ba
AD		 4242 ixgbe_reset(adapter);
4243
495dce12
WJP		 4244 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4245
b3c8b4ba
AD		 4246 if (netif_running(netdev)) {
4247 err = ixgbe_open(adapter->netdev);
4248 if (err)
4249 return err;
4250 }
4251
4252 netif_device_attach(netdev);
4253
4254 return 0;
4255}
b3c8b4ba 4256#endif /* CONFIG_PM */
9d8d05ae
RW		 4257
4258static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4259{
4260 struct net_device *netdev = pci_get_drvdata(pdev);
4261 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4262 struct ixgbe_hw *hw = &adapter->hw;
4263 u32 ctrl, fctrl;
4264 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4265#ifdef CONFIG_PM
4266 int retval = 0;
4267#endif
4268
4269 netif_device_detach(netdev);
4270
4271 if (netif_running(netdev)) {
4272 ixgbe_down(adapter);
4273 ixgbe_free_irq(adapter);
4274 ixgbe_free_all_tx_resources(adapter);
4275 ixgbe_free_all_rx_resources(adapter);
4276 }
7a921c93 4277 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4278
4279#ifdef CONFIG_PM
4280 retval = pci_save_state(pdev);
4281 if (retval)
4282 return retval;
4df10466 4283
b3c8b4ba 4284#endif
e8e26350
PW		 4285 if (wufc) {
4286 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4287
e8e26350
PW		 4288 /* turn on all-multi mode if wake on multicast is enabled */
4289 if (wufc & IXGBE_WUFC_MC) {
4290 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4291 fctrl |= IXGBE_FCTRL_MPE;
4292 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4293 }
4294
4295 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4296 ctrl |= IXGBE_CTRL_GIO_DIS;
4297 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4298
4299 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4300 } else {
4301 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4302 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4303 }
4304
dd4d8ca6
DS		 4305 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4306 pci_wake_from_d3(pdev, true);
4307 else
4308 pci_wake_from_d3(pdev, false);
b3c8b4ba 4309
9d8d05ae
RW		 4310 *enable_wake = !!wufc;
4311
b3c8b4ba
AD		 4312 ixgbe_release_hw_control(adapter);
4313
4314 pci_disable_device(pdev);
4315
9d8d05ae
RW		 4316 return 0;
4317}
4318
4319#ifdef CONFIG_PM
4320static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4321{
4322 int retval;
4323 bool wake;
4324
4325 retval = __ixgbe_shutdown(pdev, &wake);
4326 if (retval)
4327 return retval;
4328
4329 if (wake) {
4330 pci_prepare_to_sleep(pdev);
4331 } else {
4332 pci_wake_from_d3(pdev, false);
4333 pci_set_power_state(pdev, PCI_D3hot);
4334 }
b3c8b4ba
AD		 4335
4336 return 0;
4337}
9d8d05ae 4338#endif /* CONFIG_PM */
b3c8b4ba
AD		 4339
4340static void ixgbe_shutdown(struct pci_dev *pdev)
4341{
9d8d05ae
RW		 4342 bool wake;
4343
4344 __ixgbe_shutdown(pdev, &wake);
4345
4346 if (system_state == SYSTEM_POWER_OFF) {
4347 pci_wake_from_d3(pdev, wake);
4348 pci_set_power_state(pdev, PCI_D3hot);
4349 }
b3c8b4ba
AD		 4350}
4351
9a799d71
AK		 4352/**
4353 * ixgbe_update_stats - Update the board statistics counters.
4354 * @adapter: board private structure
4355 **/
4356void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4357{
4358 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4359 u64 total_mpc = 0;
4360 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4361
d51019a4 4362 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4363 u64 rsc_count = 0;
d51019a4
PW		 4364 for (i = 0; i < 16; i++)
4365 adapter->hw_rx_no_dma_resources +=
4366 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4367 for (i = 0; i < adapter->num_rx_queues; i++)
4368 rsc_count += adapter->rx_ring[i].rsc_count;
4369 adapter->rsc_count = rsc_count;
d51019a4
PW		 4370 }
4371
9a799d71 4372 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4373 for (i = 0; i < 8; i++) {
4374 /* for packet buffers not used, the register should read 0 */
4375 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4376 missed_rx += mpc;
4377 adapter->stats.mpc[i] += mpc;
4378 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4379 if (hw->mac.type == ixgbe_mac_82598EB)
4380 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4381 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4382 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4383 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4384 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4385 if (hw->mac.type == ixgbe_mac_82599EB) {
4386 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4387 IXGBE_PXONRXCNT(i));
4388 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4389 IXGBE_PXOFFRXCNT(i));
4390 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4391 } else {
4392 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4393 IXGBE_PXONRXC(i));
4394 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4395 IXGBE_PXOFFRXC(i));
4396 }
2f90b865
AD		 4397 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4398 IXGBE_PXONTXC(i));
2f90b865 4399 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4400 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4401 }
4402 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4403 /* work around hardware counting issue */
4404 adapter->stats.gprc -= missed_rx;
4405
4406 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 4407 if (hw->mac.type == ixgbe_mac_82599EB) {
4408 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4409 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4410 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4411 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4412 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4413 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4414 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4415 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4416 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4417 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4418#ifdef IXGBE_FCOE
4419 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4420 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4421 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4422 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4423 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4424 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4425#endif /* IXGBE_FCOE */
e8e26350
PW		 4426 } else {
4427 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4428 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4429 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4430 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4431 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4432 }
9a799d71
AK		 4433 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4434 adapter->stats.bprc += bprc;
4435 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4436 if (hw->mac.type == ixgbe_mac_82598EB)
4437 adapter->stats.mprc -= bprc;
9a799d71
AK		 4438 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4439 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4440 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4441 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4442 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4443 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4444 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4445 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4446 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4447 adapter->stats.lxontxc += lxon;
4448 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4449 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4450 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4451 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4452 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4453 /*
4454 * 82598 errata - tx of flow control packets is included in tx counters
4455 */
4456 xon_off_tot = lxon + lxoff;
4457 adapter->stats.gptc -= xon_off_tot;
4458 adapter->stats.mptc -= xon_off_tot;
4459 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4460 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4461 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4462 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4463 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4464 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4465 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4466 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4467 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4468 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4469 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4470 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4471 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4472
4473 /* Fill out the OS statistics structure */
9a799d71
AK		 4474 adapter->net_stats.multicast = adapter->stats.mprc;
4475
4476 /* Rx Errors */
4477 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4478 adapter->stats.rlec;
9a799d71
AK		 4479 adapter->net_stats.rx_dropped = 0;
4480 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4481 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4482 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4483}
4484
4485/**
4486 * ixgbe_watchdog - Timer Call-back
4487 * @data: pointer to adapter cast into an unsigned long
4488 **/
4489static void ixgbe_watchdog(unsigned long data)
4490{
4491 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4492 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4493 u64 eics = 0;
4494 int i;
cf8280ee 4495
fe49f04a
AD		 4496 /*
4497 * Do the watchdog outside of interrupt context due to the lovely
4498 * delays that some of the newer hardware requires
4499 */
22d5a71b 4500
fe49f04a
AD		 4501 if (test_bit(__IXGBE_DOWN, &adapter->state))
4502 goto watchdog_short_circuit;
22d5a71b 4503
fe49f04a
AD		 4504 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4505 /*
4506 * for legacy and MSI interrupts don't set any bits
4507 * that are enabled for EIAM, because this operation
4508 * would set *both* EIMS and EICS for any bit in EIAM
4509 */
4510 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4511 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4512 goto watchdog_reschedule;
4513 }
4514
4515 /* get one bit for every active tx/rx interrupt vector */
4516 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4517 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4518 if (qv->rxr_count || qv->txr_count)
4519 eics |= ((u64)1 << i);
cf8280ee 4520 }
9a799d71 4521
fe49f04a
AD		 4522 /* Cause software interrupt to ensure rx rings are cleaned */
4523 ixgbe_irq_rearm_queues(adapter, eics);
4524
4525watchdog_reschedule:
4526 /* Reset the timer */
4527 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4528
4529watchdog_short_circuit:
cf8280ee
JB		 4530 schedule_work(&adapter->watchdog_task);
4531}
4532
e8e26350
PW		 4533/**
4534 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4535 * @work: pointer to work_struct containing our data
4536 **/
4537static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4538{
4539 struct ixgbe_adapter *adapter = container_of(work,
4540 struct ixgbe_adapter,
4541 multispeed_fiber_task);
4542 struct ixgbe_hw *hw = &adapter->hw;
4543 u32 autoneg;
8620a103 4544 bool negotiation;
e8e26350
PW		 4545
4546 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4547 autoneg = hw->phy.autoneg_advertised;
4548 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 4549 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4550 if (hw->mac.ops.setup_link)
4551 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 4552 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4553 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4554}
4555
4556/**
4557 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4558 * @work: pointer to work_struct containing our data
4559 **/
4560static void ixgbe_sfp_config_module_task(struct work_struct *work)
4561{
4562 struct ixgbe_adapter *adapter = container_of(work,
4563 struct ixgbe_adapter,
4564 sfp_config_module_task);
4565 struct ixgbe_hw *hw = &adapter->hw;
4566 u32 err;
4567
4568 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4569
4570 /* Time for electrical oscillations to settle down */
4571 msleep(100);
e8e26350 4572 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4573
e8e26350 4574 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4575 dev_err(&adapter->pdev->dev, "failed to initialize because "
4576 "an unsupported SFP+ module type was detected.\n"
4577 "Reload the driver after installing a supported "
4578 "module.\n");
63d6e1d8 4579 unregister_netdev(adapter->netdev);
e8e26350
PW		 4580 return;
4581 }
4582 hw->mac.ops.setup_sfp(hw);
4583
8d1c3c07 4584 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4585 /* This will also work for DA Twinax connections */
4586 schedule_work(&adapter->multispeed_fiber_task);
4587 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4588}
4589
c4cf55e5
PWJ		 4590/**
4591 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4592 * @work: pointer to work_struct containing our data
4593 **/
4594static void ixgbe_fdir_reinit_task(struct work_struct *work)
4595{
4596 struct ixgbe_adapter *adapter = container_of(work,
4597 struct ixgbe_adapter,
4598 fdir_reinit_task);
4599 struct ixgbe_hw *hw = &adapter->hw;
4600 int i;
4601
4602 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4603 for (i = 0; i < adapter->num_tx_queues; i++)
4604 set_bit(__IXGBE_FDIR_INIT_DONE,
4605 &(adapter->tx_ring[i].reinit_state));
4606 } else {
4607 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4608 "ignored adding FDIR ATR filters \n");
4609 }
4610 /* Done FDIR Re-initialization, enable transmits */
4611 netif_tx_start_all_queues(adapter->netdev);
4612}
4613
cf8280ee 4614/**
69888674
AD		 4615 * ixgbe_watchdog_task - worker thread to bring link up
4616 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4617 **/
4618static void ixgbe_watchdog_task(struct work_struct *work)
4619{
4620 struct ixgbe_adapter *adapter = container_of(work,
4621 struct ixgbe_adapter,
4622 watchdog_task);
4623 struct net_device *netdev = adapter->netdev;
4624 struct ixgbe_hw *hw = &adapter->hw;
4625 u32 link_speed = adapter->link_speed;
4626 bool link_up = adapter->link_up;
bc59fcda
NS		 4627 int i;
4628 struct ixgbe_ring *tx_ring;
4629 int some_tx_pending = 0;
cf8280ee
JB		 4630
4631 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4632
4633 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4634 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4635 if (link_up) {
4636#ifdef CONFIG_DCB
4637 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4638 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4639 hw->mac.ops.fc_enable(hw, i);
264857b8 4640 } else {
620fa036 4641 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4642 }
4643#else
620fa036 4644 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4645#endif
4646 }
4647
cf8280ee
JB		 4648 if (link_up ||
4649 time_after(jiffies, (adapter->link_check_timeout +
4650 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4651 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4652 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4653 }
4654 adapter->link_up = link_up;
4655 adapter->link_speed = link_speed;
4656 }
9a799d71
AK		 4657
4658 if (link_up) {
4659 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4660 bool flow_rx, flow_tx;
4661
4662 if (hw->mac.type == ixgbe_mac_82599EB) {
4663 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4664 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 4665 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4666 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 4667 } else {
4668 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4669 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 4670 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4671 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 4672 }
4673
a46e534b
JK		 4674 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4675 "Flow Control: %s\n",
4676 netdev->name,
4677 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4678 "10 Gbps" :
4679 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4680 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4681 ((flow_rx && flow_tx) ? "RX/TX" :
4682 (flow_rx ? "RX" :
4683 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4684
4685 netif_carrier_on(netdev);
9a799d71
AK		 4686 } else {
4687 /* Force detection of hung controller */
4688 adapter->detect_tx_hung = true;
4689 }
4690 } else {
cf8280ee
JB		 4691 adapter->link_up = false;
4692 adapter->link_speed = 0;
9a799d71 4693 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4694 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4695 netdev->name);
9a799d71 4696 netif_carrier_off(netdev);
9a799d71
AK		 4697 }
4698 }
4699
bc59fcda
NS		 4700 if (!netif_carrier_ok(netdev)) {
4701 for (i = 0; i < adapter->num_tx_queues; i++) {
4702 tx_ring = &adapter->tx_ring[i];
4703 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4704 some_tx_pending = 1;
4705 break;
4706 }
4707 }
4708
4709 if (some_tx_pending) {
4710 /* We've lost link, so the controller stops DMA,
4711 * but we've got queued Tx work that's never going
4712 * to get done, so reset controller to flush Tx.
4713 * (Do the reset outside of interrupt context).
4714 */
4715 schedule_work(&adapter->reset_task);
4716 }
4717 }
4718
9a799d71 4719 ixgbe_update_stats(adapter);
cf8280ee 4720 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4721}
4722
9a799d71 4723static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4724 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4725 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4726{
4727 struct ixgbe_adv_tx_context_desc *context_desc;
4728 unsigned int i;
4729 int err;
4730 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4731 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4732 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4733
4734 if (skb_is_gso(skb)) {
4735 if (skb_header_cloned(skb)) {
4736 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4737 if (err)
4738 return err;
4739 }
4740 l4len = tcp_hdrlen(skb);
4741 *hdr_len += l4len;
4742
8327d000 4743 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4744 struct iphdr *iph = ip_hdr(skb);
4745 iph->tot_len = 0;
4746 iph->check = 0;
4747 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4748 iph->daddr, 0,
4749 IPPROTO_TCP,
4750 0);
9a799d71
AK		 4751 adapter->hw_tso_ctxt++;
4752 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4753 ipv6_hdr(skb)->payload_len = 0;
4754 tcp_hdr(skb)->check =
4755 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4756 &ipv6_hdr(skb)->daddr,
4757 0, IPPROTO_TCP, 0);
9a799d71
AK		 4758 adapter->hw_tso6_ctxt++;
4759 }
4760
4761 i = tx_ring->next_to_use;
4762
4763 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4764 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4765
4766 /* VLAN MACLEN IPLEN */
4767 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4768 vlan_macip_lens |=
4769 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4770 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4771 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4772 *hdr_len += skb_network_offset(skb);
4773 vlan_macip_lens |=
4774 (skb_transport_header(skb) - skb_network_header(skb));
4775 *hdr_len +=
4776 (skb_transport_header(skb) - skb_network_header(skb));
4777 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4778 context_desc->seqnum_seed = 0;
4779
4780 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4781 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4782 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4783
8327d000 4784 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4785 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4786 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4787 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4788
4789 /* MSS L4LEN IDX */
9f8cdf4f 4790 mss_l4len_idx =
9a799d71
AK		 4791 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4792 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4793 /* use index 1 for TSO */
4794 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4795 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4796
4797 tx_buffer_info->time_stamp = jiffies;
4798 tx_buffer_info->next_to_watch = i;
4799
4800 i++;
4801 if (i == tx_ring->count)
4802 i = 0;
4803 tx_ring->next_to_use = i;
4804
4805 return true;
4806 }
4807 return false;
4808}
4809
4810static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4811 struct ixgbe_ring *tx_ring,
4812 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4813{
4814 struct ixgbe_adv_tx_context_desc *context_desc;
4815 unsigned int i;
4816 struct ixgbe_tx_buffer *tx_buffer_info;
4817 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4818
4819 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4820 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4821 i = tx_ring->next_to_use;
4822 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4823 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4824
4825 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4826 vlan_macip_lens |=
4827 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4828 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4829 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4830 if (skb->ip_summed == CHECKSUM_PARTIAL)
4831 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4832 skb_network_header(skb));
9a799d71
AK		 4833
4834 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4835 context_desc->seqnum_seed = 0;
4836
4837 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4838 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4839
4840 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4841 switch (skb->protocol) {
09640e63 4842 case cpu_to_be16(ETH_P_IP):
9a799d71 4843 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4844 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4845 type_tucmd_mlhl |=
b4617240 4846 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4847 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4848 type_tucmd_mlhl |=
4849 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4850 break;
09640e63 4851 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4852 /* XXX what about other V6 headers?? */
4853 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4854 type_tucmd_mlhl |=
b4617240 4855 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4856 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4857 type_tucmd_mlhl |=
4858 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4859 break;
41825d71
AK		 4860 default:
4861 if (unlikely(net_ratelimit())) {
4862 DPRINTK(PROBE, WARNING,
4863 "partial checksum but proto=%x!\n",
4864 skb->protocol);
4865 }
4866 break;
4867 }
9a799d71
AK		 4868 }
4869
4870 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4871 /* use index zero for tx checksum offload */
9a799d71
AK		 4872 context_desc->mss_l4len_idx = 0;
4873
4874 tx_buffer_info->time_stamp = jiffies;
4875 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4876
9a799d71
AK		 4877 adapter->hw_csum_tx_good++;
4878 i++;
4879 if (i == tx_ring->count)
4880 i = 0;
4881 tx_ring->next_to_use = i;
4882
4883 return true;
4884 }
9f8cdf4f 4885
9a799d71
AK		 4886 return false;
4887}
4888
4889static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4890 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4891 struct sk_buff *skb, u32 tx_flags,
4892 unsigned int first)
9a799d71
AK		 4893{
4894 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4895 unsigned int len;
4896 unsigned int total = skb->len;
9a799d71
AK		 4897 unsigned int offset = 0, size, count = 0, i;
4898 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4899 unsigned int f;
44df32c5 4900 dma_addr_t *map;
9a799d71
AK		 4901
4902 i = tx_ring->next_to_use;
4903
44df32c5
AD		 4904 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4905 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4906 return 0;
4907 }
4908
4909 map = skb_shinfo(skb)->dma_maps;
4910
eacd73f7
YZ		 4911 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4912 /* excluding fcoe_crc_eof for FCoE */
4913 total -= sizeof(struct fcoe_crc_eof);
4914
4915 len = min(skb_headlen(skb), total);
9a799d71
AK		 4916 while (len) {
4917 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4918 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4919
4920 tx_buffer_info->length = size;
042a53a9 4921 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
9a799d71
AK		 4922 tx_buffer_info->time_stamp = jiffies;
4923 tx_buffer_info->next_to_watch = i;
4924
4925 len -= size;
eacd73f7 4926 total -= size;
9a799d71
AK		 4927 offset += size;
4928 count++;
44df32c5
AD		 4929
4930 if (len) {
4931 i++;
4932 if (i == tx_ring->count)
4933 i = 0;
4934 }
9a799d71
AK		 4935 }
4936
4937 for (f = 0; f < nr_frags; f++) {
4938 struct skb_frag_struct *frag;
4939
4940 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4941 len = min((unsigned int)frag->size, total);
44df32c5 4942 offset = 0;
9a799d71
AK		 4943
4944 while (len) {
44df32c5
AD		 4945 i++;
4946 if (i == tx_ring->count)
4947 i = 0;
4948
9a799d71
AK		 4949 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4950 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4951
4952 tx_buffer_info->length = size;
042a53a9 4953 tx_buffer_info->dma = map[f] + offset;
9a799d71
AK		 4954 tx_buffer_info->time_stamp = jiffies;
4955 tx_buffer_info->next_to_watch = i;
4956
4957 len -= size;
eacd73f7 4958 total -= size;
9a799d71
AK		 4959 offset += size;
4960 count++;
9a799d71 4961 }
eacd73f7
YZ		 4962 if (total == 0)
4963 break;
9a799d71 4964 }
44df32c5 4965
9a799d71
AK		 4966 tx_ring->tx_buffer_info[i].skb = skb;
4967 tx_ring->tx_buffer_info[first].next_to_watch = i;
4968
4969 return count;
4970}
4971
4972static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4973 struct ixgbe_ring *tx_ring,
4974 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4975{
4976 union ixgbe_adv_tx_desc *tx_desc = NULL;
4977 struct ixgbe_tx_buffer *tx_buffer_info;
4978 u32 olinfo_status = 0, cmd_type_len = 0;
4979 unsigned int i;
4980 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4981
4982 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4983
4984 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4985
4986 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4987 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4988
4989 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4990 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4991
4992 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4993 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4994
4eeae6fd
PW		 4995 /* use index 1 context for tso */
4996 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4997 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4998 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4999 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5000
5001 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5002 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5003 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5004
eacd73f7
YZ		 5005 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5006 olinfo_status |= IXGBE_ADVTXD_CC;
5007 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5008 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5009 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5010 }
5011
9a799d71
AK		 5012 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5013
5014 i = tx_ring->next_to_use;
5015 while (count--) {
5016 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5017 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5018 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5019 tx_desc->read.cmd_type_len =
b4617240 5020 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5021 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5022 i++;
5023 if (i == tx_ring->count)
5024 i = 0;
5025 }
5026
5027 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5028
5029 /*
5030 * Force memory writes to complete before letting h/w
5031 * know there are new descriptors to fetch. (Only
5032 * applicable for weak-ordered memory model archs,
5033 * such as IA-64).
5034 */
5035 wmb();
5036
5037 tx_ring->next_to_use = i;
5038 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5039}
5040
c4cf55e5
PWJ		 5041static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5042 int queue, u32 tx_flags)
5043{
5044 /* Right now, we support IPv4 only */
5045 struct ixgbe_atr_input atr_input;
5046 struct tcphdr *th;
5047 struct udphdr *uh;
5048 struct iphdr *iph = ip_hdr(skb);
5049 struct ethhdr *eth = (struct ethhdr *)skb->data;
5050 u16 vlan_id, src_port, dst_port, flex_bytes;
5051 u32 src_ipv4_addr, dst_ipv4_addr;
5052 u8 l4type = 0;
5053
5054 /* check if we're UDP or TCP */
5055 if (iph->protocol == IPPROTO_TCP) {
5056 th = tcp_hdr(skb);
5057 src_port = th->source;
5058 dst_port = th->dest;
5059 l4type |= IXGBE_ATR_L4TYPE_TCP;
5060 /* l4type IPv4 type is 0, no need to assign */
5061 } else if(iph->protocol == IPPROTO_UDP) {
5062 uh = udp_hdr(skb);
5063 src_port = uh->source;
5064 dst_port = uh->dest;
5065 l4type |= IXGBE_ATR_L4TYPE_UDP;
5066 /* l4type IPv4 type is 0, no need to assign */
5067 } else {
5068 /* Unsupported L4 header, just bail here */
5069 return;
5070 }
5071
5072 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5073
5074 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5075 IXGBE_TX_FLAGS_VLAN_SHIFT;
5076 src_ipv4_addr = iph->saddr;
5077 dst_ipv4_addr = iph->daddr;
5078 flex_bytes = eth->h_proto;
5079
5080 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5081 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5082 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5083 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5084 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5085 /* src and dst are inverted, think how the receiver sees them */
5086 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5087 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5088
5089 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5090 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5091}
5092
e092be60 5093static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5094 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5095{
5096 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5097
30eba97a 5098 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5099 /* Herbert's original patch had:
5100 * smp_mb__after_netif_stop_queue();
5101 * but since that doesn't exist yet, just open code it. */
5102 smp_mb();
5103
5104 /* We need to check again in a case another CPU has just
5105 * made room available. */
5106 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5107 return -EBUSY;
5108
5109 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5110 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5111 ++adapter->restart_queue;
5112 return 0;
5113}
5114
5115static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5116 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5117{
5118 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5119 return 0;
5120 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5121}
5122
09a3b1f8
SH		 5123static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5124{
5125 struct ixgbe_adapter *adapter = netdev_priv(dev);
5126
c4cf55e5
PWJ		 5127 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5128 return smp_processor_id();
5129
09a3b1f8 5130 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5131 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5132
5133 return skb_tx_hash(dev, skb);
5134}
5135
3b29a56d
SH		 5136static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5137 struct net_device *netdev)
9a799d71
AK		 5138{
5139 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5140 struct ixgbe_ring *tx_ring;
9a799d71
AK		 5141 unsigned int first;
5142 unsigned int tx_flags = 0;
30eba97a
AV		 5143 u8 hdr_len = 0;
5144 int r_idx = 0, tso;
9a799d71
AK		 5145 int count = 0;
5146 unsigned int f;
9f8cdf4f 5147
9f8cdf4f
JB		 5148 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5149 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5150 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5151 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5152 tx_flags |= (skb->queue_mapping << 13);
5153 }
5154 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5155 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5156 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865
LL		 5157 if (skb->priority != TC_PRIO_CONTROL) {
5158 tx_flags |= (skb->queue_mapping << 13);
5159 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5160 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5161 } else {
5162 skb->queue_mapping =
5163 adapter->ring_feature[RING_F_DCB].indices-1;
5164 }
9a799d71 5165 }
eacd73f7 5166
60127865
LL		 5167 r_idx = skb->queue_mapping;
5168 tx_ring = &adapter->tx_ring[r_idx];
5169
eacd73f7 5170 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5171 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5172 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0
YZ		 5173#ifdef IXGBE_FCOE
5174 r_idx = smp_processor_id();
5175 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5176 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5177 tx_ring = &adapter->tx_ring[r_idx];
5178#endif
5179 }
eacd73f7 5180 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5181 if (skb_is_gso(skb) ||
5182 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5183 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5184 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5185 count++;
5186
9f8cdf4f
JB		 5187 count += TXD_USE_COUNT(skb_headlen(skb));
5188 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5189 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5190
e092be60 5191 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5192 adapter->tx_busy++;
9a799d71
AK		 5193 return NETDEV_TX_BUSY;
5194 }
9a799d71 5195
9a799d71 5196 first = tx_ring->next_to_use;
eacd73f7
YZ		 5197 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5198#ifdef IXGBE_FCOE
5199 /* setup tx offload for FCoE */
5200 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5201 if (tso < 0) {
5202 dev_kfree_skb_any(skb);
5203 return NETDEV_TX_OK;
5204 }
5205 if (tso)
5206 tx_flags |= IXGBE_TX_FLAGS_FSO;
5207#endif /* IXGBE_FCOE */
5208 } else {
5209 if (skb->protocol == htons(ETH_P_IP))
5210 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5211 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5212 if (tso < 0) {
5213 dev_kfree_skb_any(skb);
5214 return NETDEV_TX_OK;
5215 }
9a799d71 5216
eacd73f7
YZ		 5217 if (tso)
5218 tx_flags |= IXGBE_TX_FLAGS_TSO;
5219 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5220 (skb->ip_summed == CHECKSUM_PARTIAL))
5221 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5222 }
9a799d71 5223
eacd73f7 5224 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5225 if (count) {
c4cf55e5
PWJ		 5226 /* add the ATR filter if ATR is on */
5227 if (tx_ring->atr_sample_rate) {
5228 ++tx_ring->atr_count;
5229 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5230 test_bit(__IXGBE_FDIR_INIT_DONE,
5231 &tx_ring->reinit_state)) {
5232 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5233 tx_flags);
5234 tx_ring->atr_count = 0;
5235 }
5236 }
44df32c5
AD		 5237 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5238 hdr_len);
44df32c5 5239 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5240
44df32c5
AD		 5241 } else {
5242 dev_kfree_skb_any(skb);
5243 tx_ring->tx_buffer_info[first].time_stamp = 0;
5244 tx_ring->next_to_use = first;
5245 }
9a799d71
AK		 5246
5247 return NETDEV_TX_OK;
5248}
5249
5250/**
5251 * ixgbe_get_stats - Get System Network Statistics
5252 * @netdev: network interface device structure
5253 *
5254 * Returns the address of the device statistics structure.
5255 * The statistics are actually updated from the timer callback.
5256 **/
5257static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5258{
5259 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5260
5261 /* only return the current stats */
5262 return &adapter->net_stats;
5263}
5264
5265/**
5266 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5267 * @netdev: network interface device structure
5268 * @p: pointer to an address structure
5269 *
5270 * Returns 0 on success, negative on failure
5271 **/
5272static int ixgbe_set_mac(struct net_device *netdev, void *p)
5273{
5274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5275 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5276 struct sockaddr *addr = p;
5277
5278 if (!is_valid_ether_addr(addr->sa_data))
5279 return -EADDRNOTAVAIL;
5280
5281 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5282 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5283
b4617240 5284 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 5285
5286 return 0;
5287}
5288
6b73e10d
BH		 5289static int
5290ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5291{
5292 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5293 struct ixgbe_hw *hw = &adapter->hw;
5294 u16 value;
5295 int rc;
5296
5297 if (prtad != hw->phy.mdio.prtad)
5298 return -EINVAL;
5299 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5300 if (!rc)
5301 rc = value;
5302 return rc;
5303}
5304
5305static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5306 u16 addr, u16 value)
5307{
5308 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5309 struct ixgbe_hw *hw = &adapter->hw;
5310
5311 if (prtad != hw->phy.mdio.prtad)
5312 return -EINVAL;
5313 return hw->phy.ops.write_reg(hw, addr, devad, value);
5314}
5315
5316static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5317{
5318 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5319
5320 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5321}
5322
0365e6e4
PW		 5323/**
5324 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5325 * netdev->dev_addrs
0365e6e4
PW		 5326 * @netdev: network interface device structure
5327 *
5328 * Returns non-zero on failure
5329 **/
5330static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5331{
5332 int err = 0;
5333 struct ixgbe_adapter *adapter = netdev_priv(dev);
5334 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5335
5336 if (is_valid_ether_addr(mac->san_addr)) {
5337 rtnl_lock();
5338 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5339 rtnl_unlock();
5340 }
5341 return err;
5342}
5343
5344/**
5345 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5346 * netdev->dev_addrs
0365e6e4
PW		 5347 * @netdev: network interface device structure
5348 *
5349 * Returns non-zero on failure
5350 **/
5351static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5352{
5353 int err = 0;
5354 struct ixgbe_adapter *adapter = netdev_priv(dev);
5355 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5356
5357 if (is_valid_ether_addr(mac->san_addr)) {
5358 rtnl_lock();
5359 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5360 rtnl_unlock();
5361 }
5362 return err;
5363}
5364
9a799d71
AK		 5365#ifdef CONFIG_NET_POLL_CONTROLLER
5366/*
5367 * Polling 'interrupt' - used by things like netconsole to send skbs
5368 * without having to re-enable interrupts. It's not called while
5369 * the interrupt routine is executing.
5370 */
5371static void ixgbe_netpoll(struct net_device *netdev)
5372{
5373 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5374 int i;
9a799d71 5375
9a799d71 5376 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5377 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5378 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5379 for (i = 0; i < num_q_vectors; i++) {
5380 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5381 ixgbe_msix_clean_many(0, q_vector);
5382 }
5383 } else {
5384 ixgbe_intr(adapter->pdev->irq, netdev);
5385 }
9a799d71 5386 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5387}
5388#endif
5389
0edc3527
SH		 5390static const struct net_device_ops ixgbe_netdev_ops = {
5391 .ndo_open = ixgbe_open,
5392 .ndo_stop = ixgbe_close,
00829823 5393 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5394 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5395 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5396 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5397 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5398 .ndo_validate_addr = eth_validate_addr,
5399 .ndo_set_mac_address = ixgbe_set_mac,
5400 .ndo_change_mtu = ixgbe_change_mtu,
5401 .ndo_tx_timeout = ixgbe_tx_timeout,
5402 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5403 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5404 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5405 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5406#ifdef CONFIG_NET_POLL_CONTROLLER
5407 .ndo_poll_controller = ixgbe_netpoll,
5408#endif
332d4a7d
YZ		 5409#ifdef IXGBE_FCOE
5410 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5411 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5412 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5413 .ndo_fcoe_disable = ixgbe_fcoe_disable,
332d4a7d 5414#endif /* IXGBE_FCOE */
0edc3527
SH		 5415};
5416
9a799d71
AK		 5417/**
5418 * ixgbe_probe - Device Initialization Routine
5419 * @pdev: PCI device information struct
5420 * @ent: entry in ixgbe_pci_tbl
5421 *
5422 * Returns 0 on success, negative on failure
5423 *
5424 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5425 * The OS initialization, configuring of the adapter private structure,
5426 * and a hardware reset occur.
5427 **/
5428static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5429 const struct pci_device_id *ent)
9a799d71
AK		 5430{
5431 struct net_device *netdev;
5432 struct ixgbe_adapter *adapter = NULL;
5433 struct ixgbe_hw *hw;
5434 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5435 static int cards_found;
5436 int i, err, pci_using_dac;
eacd73f7
YZ		 5437#ifdef IXGBE_FCOE
5438 u16 device_caps;
5439#endif
c44ade9e 5440 u32 part_num, eec;
9a799d71 5441
9ce77666 5442 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5443 if (err)
5444 return err;
5445
6a35528a
YH		 5446 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5447 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5448 pci_using_dac = 1;
5449 } else {
284901a9 5450 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5451 if (err) {
284901a9 5452 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5453 if (err) {
b4617240
PW		 5454 dev_err(&pdev->dev, "No usable DMA "
5455 "configuration, aborting\n");
9a799d71
AK		 5456 goto err_dma;
5457 }
5458 }
5459 pci_using_dac = 0;
5460 }
5461
9ce77666 5462 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5463 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5464 if (err) {
9ce77666 5465 dev_err(&pdev->dev,
5466 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5467 goto err_pci_reg;
5468 }
5469
6fabd715
PWJ		 5470 err = pci_enable_pcie_error_reporting(pdev);
5471 if (err) {
5472 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5473 "0x%x\n", err);
5474 /* non-fatal, continue */
5475 }
5476
9a799d71 5477 pci_set_master(pdev);
fb3b27bc 5478 pci_save_state(pdev);
9a799d71 5479
30eba97a 5480 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5481 if (!netdev) {
5482 err = -ENOMEM;
5483 goto err_alloc_etherdev;
5484 }
5485
9a799d71
AK		 5486 SET_NETDEV_DEV(netdev, &pdev->dev);
5487
5488 pci_set_drvdata(pdev, netdev);
5489 adapter = netdev_priv(netdev);
5490
5491 adapter->netdev = netdev;
5492 adapter->pdev = pdev;
5493 hw = &adapter->hw;
5494 hw->back = adapter;
5495 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5496
05857980
JK		 5497 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5498 pci_resource_len(pdev, 0));
9a799d71
AK		 5499 if (!hw->hw_addr) {
5500 err = -EIO;
5501 goto err_ioremap;
5502 }
5503
5504 for (i = 1; i <= 5; i++) {
5505 if (pci_resource_len(pdev, i) == 0)
5506 continue;
5507 }
5508
0edc3527 5509 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5510 ixgbe_set_ethtool_ops(netdev);
9a799d71 5511 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5512 strcpy(netdev->name, pci_name(pdev));
5513
9a799d71
AK		 5514 adapter->bd_number = cards_found;
5515
9a799d71
AK		 5516 /* Setup hw api */
5517 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5518 hw->mac.type = ii->mac;
9a799d71 5519
c44ade9e
JB		 5520 /* EEPROM */
5521 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5522 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5523 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5524 if (!(eec & (1 << 8)))
5525 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5526
5527 /* PHY */
5528 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5529 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5530 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5531 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5532 hw->phy.mdio.mmds = 0;
5533 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5534 hw->phy.mdio.dev = netdev;
5535 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5536 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5537
5538 /* set up this timer and work struct before calling get_invariants
5539 * which might start the timer
5540 */
5541 init_timer(&adapter->sfp_timer);
5542 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5543 adapter->sfp_timer.data = (unsigned long) adapter;
5544
5545 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5546
e8e26350
PW		 5547 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5548 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5549
5550 /* a new SFP+ module arrival, called from GPI SDP2 context */
5551 INIT_WORK(&adapter->sfp_config_module_task,
5552 ixgbe_sfp_config_module_task);
5553
8ca783ab 5554 ii->get_invariants(hw);
9a799d71
AK		 5555
5556 /* setup the private structure */
5557 err = ixgbe_sw_init(adapter);
5558 if (err)
5559 goto err_sw_init;
5560
bf069c97
DS		 5561 /*
5562 * If there is a fan on this device and it has failed log the
5563 * failure.
5564 */
5565 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5566 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5567 if (esdp & IXGBE_ESDP_SDP1)
5568 DPRINTK(PROBE, CRIT,
5569 "Fan has stopped, replace the adapter\n");
5570 }
5571
c44ade9e
JB		 5572 /* reset_hw fills in the perm_addr as well */
5573 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5574 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5575 hw->mac.type == ixgbe_mac_82598EB) {
5576 /*
5577 * Start a kernel thread to watch for a module to arrive.
5578 * Only do this for 82598, since 82599 will generate
5579 * interrupts on module arrival.
5580 */
5581 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5582 mod_timer(&adapter->sfp_timer,
5583 round_jiffies(jiffies + (2 * HZ)));
5584 err = 0;
5585 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5586 dev_err(&adapter->pdev->dev, "failed to initialize because "
5587 "an unsupported SFP+ module type was detected.\n"
5588 "Reload the driver after installing a supported "
5589 "module.\n");
04f165ef
PW		 5590 goto err_sw_init;
5591 } else if (err) {
c44ade9e
JB		 5592 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5593 goto err_sw_init;
5594 }
5595
9a799d71 5596 netdev->features = NETIF_F_SG |
b4617240
PW		 5597 NETIF_F_IP_CSUM |
5598 NETIF_F_HW_VLAN_TX |
5599 NETIF_F_HW_VLAN_RX |
5600 NETIF_F_HW_VLAN_FILTER;
9a799d71 5601
e9990a9c 5602 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5603 netdev->features |= NETIF_F_TSO;
9a799d71 5604 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5605 netdev->features |= NETIF_F_GRO;
ad31c402 5606
45a5ead0
JB		 5607 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5608 netdev->features |= NETIF_F_SCTP_CSUM;
5609
ad31c402
JK		 5610 netdev->vlan_features |= NETIF_F_TSO;
5611 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5612 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 5613 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 5614 netdev->vlan_features |= NETIF_F_SG;
5615
2f90b865
AD		 5616 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5617 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5618
7a6b6f51 5619#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5620 netdev->dcbnl_ops = &dcbnl_ops;
5621#endif
5622
eacd73f7 5623#ifdef IXGBE_FCOE
0d551589 5624 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 5625 if (hw->mac.ops.get_device_caps) {
5626 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 5627 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5628 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 5629 }
5630 }
5631#endif /* IXGBE_FCOE */
9a799d71
AK		 5632 if (pci_using_dac)
5633 netdev->features |= NETIF_F_HIGHDMA;
5634
0c19d6af 5635 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 5636 netdev->features |= NETIF_F_LRO;
5637
9a799d71 5638 /* make sure the EEPROM is good */
c44ade9e 5639 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5640 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5641 err = -EIO;
5642 goto err_eeprom;
5643 }
5644
5645 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5646 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5647
c44ade9e
JB		 5648 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5649 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5650 err = -EIO;
5651 goto err_eeprom;
5652 }
5653
5654 init_timer(&adapter->watchdog_timer);
5655 adapter->watchdog_timer.function = &ixgbe_watchdog;
5656 adapter->watchdog_timer.data = (unsigned long)adapter;
5657
5658 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5659 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5660
021230d4
AV		 5661 err = ixgbe_init_interrupt_scheme(adapter);
5662 if (err)
5663 goto err_sw_init;
9a799d71 5664
e8e26350
PW		 5665 switch (pdev->device) {
5666 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5667 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5668 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5669 /* Enable ACPI wakeup in GRC */
5670 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5671 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5672 break;
5673 default:
5674 adapter->wol = 0;
5675 break;
5676 }
e8e26350
PW		 5677 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5678
04f165ef
PW		 5679 /* pick up the PCI bus settings for reporting later */
5680 hw->mac.ops.get_bus_info(hw);
5681
9a799d71 5682 /* print bus type/speed/width info */
7c510e4b 5683 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5684 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5685 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5686 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5687 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5688 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5689 "Unknown"),
7c510e4b 5690 netdev->dev_addr);
c44ade9e 5691 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5692 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5693 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5694 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5695 (part_num >> 8), (part_num & 0xff));
5696 else
5697 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5698 hw->mac.type, hw->phy.type,
5699 (part_num >> 8), (part_num & 0xff));
9a799d71 5700
e8e26350 5701 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5702 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5703 "this card is not sufficient for optimal "
5704 "performance.\n");
0c254d86 5705 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5706 "PCI-Express slot is required.\n");
0c254d86
AK		 5707 }
5708
34b0368c
PWJ		 5709 /* save off EEPROM version number */
5710 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5711
9a799d71 5712 /* reset the hardware with the new settings */
794caeb2 5713 err = hw->mac.ops.start_hw(hw);
c44ade9e 5714
794caeb2
PWJ		 5715 if (err == IXGBE_ERR_EEPROM_VERSION) {
5716 /* We are running on a pre-production device, log a warning */
5717 dev_warn(&pdev->dev, "This device is a pre-production "
5718 "adapter/LOM. Please be aware there may be issues "
5719 "associated with your hardware. If you are "
5720 "experiencing problems please contact your Intel or "
5721 "hardware representative who provided you with this "
5722 "hardware.\n");
5723 }
9a799d71
AK		 5724 strcpy(netdev->name, "eth%d");
5725 err = register_netdev(netdev);
5726 if (err)
5727 goto err_register;
5728
54386467
JB		 5729 /* carrier off reporting is important to ethtool even BEFORE open */
5730 netif_carrier_off(netdev);
5731
c4cf55e5
PWJ		 5732 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5733 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5734 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5735
5dd2d332 5736#ifdef CONFIG_IXGBE_DCA
652f093f 5737 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5738 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5739 ixgbe_setup_dca(adapter);
5740 }
5741#endif
0365e6e4
PW		 5742 /* add san mac addr to netdev */
5743 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5744
5745 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5746 cards_found++;
5747 return 0;
5748
5749err_register:
5eba3699 5750 ixgbe_release_hw_control(adapter);
7a921c93 5751 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5752err_sw_init:
5753err_eeprom:
c4900be0
DS		 5754 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5755 del_timer_sync(&adapter->sfp_timer);
5756 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5757 cancel_work_sync(&adapter->multispeed_fiber_task);
5758 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5759 iounmap(hw->hw_addr);
5760err_ioremap:
5761 free_netdev(netdev);
5762err_alloc_etherdev:
9ce77666 5763 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5764 IORESOURCE_MEM));
9a799d71
AK		 5765err_pci_reg:
5766err_dma:
5767 pci_disable_device(pdev);
5768 return err;
5769}
5770
5771/**
5772 * ixgbe_remove - Device Removal Routine
5773 * @pdev: PCI device information struct
5774 *
5775 * ixgbe_remove is called by the PCI subsystem to alert the driver
5776 * that it should release a PCI device. The could be caused by a
5777 * Hot-Plug event, or because the driver is going to be removed from
5778 * memory.
5779 **/
5780static void __devexit ixgbe_remove(struct pci_dev *pdev)
5781{
5782 struct net_device *netdev = pci_get_drvdata(pdev);
5783 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5784 int err;
9a799d71
AK		 5785
5786 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5787 /* clear the module not found bit to make sure the worker won't
5788 * reschedule
5789 */
5790 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5791 del_timer_sync(&adapter->watchdog_timer);
5792
c4900be0
DS		 5793 del_timer_sync(&adapter->sfp_timer);
5794 cancel_work_sync(&adapter->watchdog_task);
5795 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5796 cancel_work_sync(&adapter->multispeed_fiber_task);
5797 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 5798 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5799 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5800 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 5801 flush_scheduled_work();
5802
5dd2d332 5803#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5804 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5805 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5806 dca_remove_requester(&pdev->dev);
5807 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5808 }
5809
5810#endif
332d4a7d
YZ		 5811#ifdef IXGBE_FCOE
5812 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5813 ixgbe_cleanup_fcoe(adapter);
5814
5815#endif /* IXGBE_FCOE */
0365e6e4
PW		 5816
5817 /* remove the added san mac */
5818 ixgbe_del_sanmac_netdev(netdev);
5819
c4900be0
DS		 5820 if (netdev->reg_state == NETREG_REGISTERED)
5821 unregister_netdev(netdev);
9a799d71 5822
7a921c93 5823 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5824
021230d4 5825 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5826
5827 iounmap(adapter->hw.hw_addr);
9ce77666 5828 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5829 IORESOURCE_MEM));
9a799d71 5830
021230d4 5831 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5832
9a799d71
AK		 5833 free_netdev(netdev);
5834
6fabd715
PWJ		 5835 err = pci_disable_pcie_error_reporting(pdev);
5836 if (err)
5837 dev_err(&pdev->dev,
5838 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5839
9a799d71
AK		 5840 pci_disable_device(pdev);
5841}
5842
5843/**
5844 * ixgbe_io_error_detected - called when PCI error is detected
5845 * @pdev: Pointer to PCI device
5846 * @state: The current pci connection state
5847 *
5848 * This function is called after a PCI bus error affecting
5849 * this device has been detected.
5850 */
5851static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5852 pci_channel_state_t state)
9a799d71
AK		 5853{
5854 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5855 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5856
5857 netif_device_detach(netdev);
5858
3044b8d1
BL		 5859 if (state == pci_channel_io_perm_failure)
5860 return PCI_ERS_RESULT_DISCONNECT;
5861
9a799d71
AK		 5862 if (netif_running(netdev))
5863 ixgbe_down(adapter);
5864 pci_disable_device(pdev);
5865
b4617240 5866 /* Request a slot reset. */
9a799d71
AK		 5867 return PCI_ERS_RESULT_NEED_RESET;
5868}
5869
5870/**
5871 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5872 * @pdev: Pointer to PCI device
5873 *
5874 * Restart the card from scratch, as if from a cold-boot.
5875 */
5876static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5877{
5878 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5880 pci_ers_result_t result;
5881 int err;
9a799d71 5882
9ce77666 5883 if (pci_enable_device_mem(pdev)) {
9a799d71 5884 DPRINTK(PROBE, ERR,
b4617240 5885 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5886 result = PCI_ERS_RESULT_DISCONNECT;
5887 } else {
5888 pci_set_master(pdev);
5889 pci_restore_state(pdev);
9a799d71 5890
dd4d8ca6 5891 pci_wake_from_d3(pdev, false);
9a799d71 5892
6fabd715 5893 ixgbe_reset(adapter);
88512539 5894 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5895 result = PCI_ERS_RESULT_RECOVERED;
5896 }
5897
5898 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5899 if (err) {
5900 dev_err(&pdev->dev,
5901 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5902 /* non-fatal, continue */
5903 }
9a799d71 5904
6fabd715 5905 return result;
9a799d71
AK		 5906}
5907
5908/**
5909 * ixgbe_io_resume - called when traffic can start flowing again.
5910 * @pdev: Pointer to PCI device
5911 *
5912 * This callback is called when the error recovery driver tells us that
5913 * its OK to resume normal operation.
5914 */
5915static void ixgbe_io_resume(struct pci_dev *pdev)
5916{
5917 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5918 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5919
5920 if (netif_running(netdev)) {
5921 if (ixgbe_up(adapter)) {
5922 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5923 return;
5924 }
5925 }
5926
5927 netif_device_attach(netdev);
9a799d71
AK		 5928}
5929
5930static struct pci_error_handlers ixgbe_err_handler = {
5931 .error_detected = ixgbe_io_error_detected,
5932 .slot_reset = ixgbe_io_slot_reset,
5933 .resume = ixgbe_io_resume,
5934};
5935
5936static struct pci_driver ixgbe_driver = {
5937 .name = ixgbe_driver_name,
5938 .id_table = ixgbe_pci_tbl,
5939 .probe = ixgbe_probe,
5940 .remove = __devexit_p(ixgbe_remove),
5941#ifdef CONFIG_PM
5942 .suspend = ixgbe_suspend,
5943 .resume = ixgbe_resume,
5944#endif
5945 .shutdown = ixgbe_shutdown,
5946 .err_handler = &ixgbe_err_handler
5947};
5948
5949/**
5950 * ixgbe_init_module - Driver Registration Routine
5951 *
5952 * ixgbe_init_module is the first routine called when the driver is
5953 * loaded. All it does is register with the PCI subsystem.
5954 **/
5955static int __init ixgbe_init_module(void)
5956{
5957 int ret;
5958 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5959 ixgbe_driver_string, ixgbe_driver_version);
5960
5961 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5962
5dd2d332 5963#ifdef CONFIG_IXGBE_DCA
bd0362dd 5964 dca_register_notify(&dca_notifier);
bd0362dd 5965#endif
5dd2d332 5966
9a799d71
AK		 5967 ret = pci_register_driver(&ixgbe_driver);
5968 return ret;
5969}
b4617240 5970
9a799d71
AK		 5971module_init(ixgbe_init_module);
5972
5973/**
5974 * ixgbe_exit_module - Driver Exit Cleanup Routine
5975 *
5976 * ixgbe_exit_module is called just before the driver is removed
5977 * from memory.
5978 **/
5979static void __exit ixgbe_exit_module(void)
5980{
5dd2d332 5981#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5982 dca_unregister_notify(&dca_notifier);
5983#endif
9a799d71
AK		 5984 pci_unregister_driver(&ixgbe_driver);
5985}
bd0362dd 5986
5dd2d332 5987#ifdef CONFIG_IXGBE_DCA
bd0362dd 5988static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5989 void *p)
bd0362dd
JC		 5990{
5991 int ret_val;
5992
5993 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5994 __ixgbe_notify_dca);
bd0362dd
JC		 5995
5996 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5997}
b453368d 5998
5dd2d332 5999#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6000#ifdef DEBUG
6001/**
6002 * ixgbe_get_hw_dev_name - return device name string
6003 * used by hardware layer to print debugging information
6004 **/
6005char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6006{
6007 struct ixgbe_adapter *adapter = hw->back;
6008 return adapter->netdev->name;
6009}
bd0362dd 6010
b453368d 6011#endif
9a799d71
AK		 6012module_exit(ixgbe_exit_module);
6013
6014/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree