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3c59x: Handle pci_enable_device() failure while resuming
[net-next-2.6.git] / drivers / net / 3c59x.c
CommitLineData
1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/slab.h>
81#include <linux/interrupt.h>
82#include <linux/pci.h>
83#include <linux/mii.h>
84#include <linux/init.h>
85#include <linux/netdevice.h>
86#include <linux/etherdevice.h>
87#include <linux/skbuff.h>
88#include <linux/ethtool.h>
89#include <linux/highmem.h>
90#include <linux/eisa.h>
91#include <linux/bitops.h>
ff5688ae 92#include <linux/jiffies.h>
1da177e4
LT		 93#include <asm/irq.h> /* For NR_IRQS only. */
94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static char version[] __devinitdata =
106DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_1,
239
240 CH_3C905B_2,
241 CH_3C905B_FX,
242 CH_3C905C,
243 CH_3C9202,
244 CH_3C980,
245 CH_3C9805,
246
247 CH_3CSOHO100_TX,
248 CH_3C555,
249 CH_3C556,
250 CH_3C556B,
251 CH_3C575,
252
253 CH_3C575_1,
254 CH_3CCFE575,
255 CH_3CCFE575CT,
256 CH_3CCFE656,
257 CH_3CCFEM656,
258
259 CH_3CCFEM656_1,
260 CH_3C450,
261 CH_3C920,
262 CH_3C982A,
263 CH_3C982B,
264
265 CH_905BT4,
266 CH_920B_EMB_WNM,
267};
268
269
270/* note: this array directly indexed by above enums, and MUST
271 * be kept in sync with both the enums above, and the PCI device
272 * table below
273 */
274static struct vortex_chip_info {
275 const char *name;
276 int flags;
277 int drv_flags;
278 int io_size;
279} vortex_info_tbl[] __devinitdata = {
280 {"3c590 Vortex 10Mbps",
1f1bd5fc 281 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 282 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 283 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 284 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 285 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 286 {"3c595 Vortex 100baseTx",
1f1bd5fc 287 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 288 {"3c595 Vortex 100baseT4",
1f1bd5fc 289 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 290
291 {"3c595 Vortex 100base-MII",
1f1bd5fc 292 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 293 {"3c900 Boomerang 10baseT",
1f1bd5fc 294 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 295 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 296 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 297 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 298 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 299 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 300 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 301
302 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 303 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 304 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 305 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 306 {"3c905 Boomerang 100baseTx",
1f1bd5fc 307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 308 {"3c905 Boomerang 100baseT4",
1f1bd5fc 309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 310 {"3c905B Cyclone 100baseTx",
1f1bd5fc 311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 312
313 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 315 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 316 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 317 {"3c905C Tornado",
1f1bd5fc 318 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 319 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 320 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 321 {"3c980 Cyclone",
1f1bd5fc 322 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 323
324 {"3c980C Python-T",
1f1bd5fc 325 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 326 {"3cSOHO100-TX Hurricane",
1f1bd5fc 327 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 328 {"3c555 Laptop Hurricane",
1f1bd5fc 329 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 330 {"3c556 Laptop Tornado",
1f1bd5fc 331 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 332 HAS_HWCKSM, 128, },
333 {"3c556B Laptop Hurricane",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
336
337 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 338 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 339 {"3c575 Boomerang CardBus",
1f1bd5fc 340 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 341 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 342 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 343 INVERT_LED_PWR|HAS_HWCKSM, 128, },
344 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 346 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
347 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 INVERT_LED_PWR|HAS_HWCKSM, 128, },
350
351 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 352 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 353 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 355 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
357 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 359 {"3c920 Tornado",
1f1bd5fc 360 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 361 {"3c982 Hydra Dual Port A",
1f1bd5fc 362 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 363
364 {"3c982 Hydra Dual Port B",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 366 {"3c905B-T4",
1f1bd5fc 367 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 368 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 369 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 370
371 {NULL,}, /* NULL terminated list. */
372};
373
374
375static struct pci_device_id vortex_pci_tbl[] = {
376 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
377 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
378 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
379 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
380 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
381
382 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
383 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
384 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
385 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
386 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
387
388 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
393
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
395 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
396 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
397 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
398 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
399 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
400
401 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
402 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
403 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
404 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
405 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
406
407 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
408 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
409 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
410 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
411 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
412
413 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
414 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
415 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
416 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
417 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
418
419 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
420 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
421
422 {0,} /* 0 terminated list. */
423};
424MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
425
426
427/* Operational definitions.
428 These are not used by other compilation units and thus are not
429 exported in a ".h" file.
430
431 First the windows. There are eight register windows, with the command
432 and status registers available in each.
433 */
62afe595 434#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 435#define EL3_CMD 0x0e
436#define EL3_STATUS 0x0e
437
438/* The top five bits written to EL3_CMD are a command, the lower
439 11 bits are the parameter, if applicable.
440 Note that 11 parameters bits was fine for ethernet, but the new chip
441 can handle FDDI length frames (~4500 octets) and now parameters count
442 32-bit 'Dwords' rather than octets. */
443
444enum vortex_cmd {
445 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
446 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
447 UpStall = 6<<11, UpUnstall = (6<<11)+1,
448 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
449 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
450 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
451 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
452 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
453 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
454 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
455
456/* The SetRxFilter command accepts the following classes: */
457enum RxFilter {
458 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
459
460/* Bits in the general status register. */
461enum vortex_status {
462 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
463 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
464 IntReq = 0x0040, StatsFull = 0x0080,
465 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
466 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
467 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
468};
469
470/* Register window 1 offsets, the window used in normal operation.
471 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
472enum Window1 {
473 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
474 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
475 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
476};
477enum Window0 {
478 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
479 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
480 IntrStatus=0x0E, /* Valid in all windows. */
481};
482enum Win0_EEPROM_bits {
483 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
484 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
485 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
486};
487/* EEPROM locations. */
488enum eeprom_offset {
489 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
490 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
491 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
492 DriverTune=13, Checksum=15};
493
494enum Window2 { /* Window 2. */
495 Wn2_ResetOptions=12,
496};
497enum Window3 { /* Window 3: MAC/config bits. */
498 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
499};
500
501#define BFEXT(value, offset, bitcount) \
502 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
503
504#define BFINS(lhs, rhs, offset, bitcount) \
505 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
506 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
507
508#define RAM_SIZE(v) BFEXT(v, 0, 3)
509#define RAM_WIDTH(v) BFEXT(v, 3, 1)
510#define RAM_SPEED(v) BFEXT(v, 4, 2)
511#define ROM_SIZE(v) BFEXT(v, 6, 2)
512#define RAM_SPLIT(v) BFEXT(v, 16, 2)
513#define XCVR(v) BFEXT(v, 20, 4)
514#define AUTOSELECT(v) BFEXT(v, 24, 1)
515
516enum Window4 { /* Window 4: Xcvr/media bits. */
517 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
518};
519enum Win4_Media_bits {
520 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
521 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
522 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
523 Media_LnkBeat = 0x0800,
524};
525enum Window7 { /* Window 7: Bus Master control. */
526 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
527 Wn7_MasterStatus = 12,
528};
529/* Boomerang bus master control registers. */
530enum MasterCtrl {
531 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
532 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
533};
534
535/* The Rx and Tx descriptor lists.
536 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
537 alignment contraint on tx_ring[] and rx_ring[]. */
538#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
539#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
540struct boom_rx_desc {
541 u32 next; /* Last entry points to 0. */
542 s32 status;
543 u32 addr; /* Up to 63 addr/len pairs possible. */
544 s32 length; /* Set LAST_FRAG to indicate last pair. */
545};
546/* Values for the Rx status entry. */
547enum rx_desc_status {
548 RxDComplete=0x00008000, RxDError=0x4000,
549 /* See boomerang_rx() for actual error bits */
550 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
551 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
552};
553
554#ifdef MAX_SKB_FRAGS
555#define DO_ZEROCOPY 1
556#else
557#define DO_ZEROCOPY 0
558#endif
559
560struct boom_tx_desc {
561 u32 next; /* Last entry points to 0. */
562 s32 status; /* bits 0:12 length, others see below. */
563#if DO_ZEROCOPY
564 struct {
565 u32 addr;
566 s32 length;
567 } frag[1+MAX_SKB_FRAGS];
568#else
569 u32 addr;
570 s32 length;
571#endif
572};
573
574/* Values for the Tx status entry. */
575enum tx_desc_status {
576 CRCDisable=0x2000, TxDComplete=0x8000,
577 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
578 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
579};
580
581/* Chip features we care about in vp->capabilities, read from the EEPROM. */
582enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
583
584struct vortex_extra_stats {
8d1d0340
SK		 585 unsigned long tx_deferred;
586 unsigned long tx_max_collisions;
587 unsigned long tx_multiple_collisions;
588 unsigned long tx_single_collisions;
589 unsigned long rx_bad_ssd;
1da177e4
LT		 590};
591
592struct vortex_private {
593 /* The Rx and Tx rings should be quad-word-aligned. */
594 struct boom_rx_desc* rx_ring;
595 struct boom_tx_desc* tx_ring;
596 dma_addr_t rx_ring_dma;
597 dma_addr_t tx_ring_dma;
598 /* The addresses of transmit- and receive-in-place skbuffs. */
599 struct sk_buff* rx_skbuff[RX_RING_SIZE];
600 struct sk_buff* tx_skbuff[TX_RING_SIZE];
601 unsigned int cur_rx, cur_tx; /* The next free ring entry */
602 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
603 struct net_device_stats stats; /* Generic stats */
604 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
605 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
606 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
607
608 /* PCI configuration space information. */
609 struct device *gendev;
62afe595
JL		 610 void __iomem *ioaddr; /* IO address space */
611 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 612
613 /* Some values here only for performance evaluation and path-coverage */
614 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
615 int card_idx;
616
617 /* The remainder are related to chip state, mostly media selection. */
618 struct timer_list timer; /* Media selection timer. */
619 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
620 int options; /* User-settable misc. driver options. */
621 unsigned int media_override:4, /* Passed-in media type. */
622 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 623 full_duplex:1, autoselect:1,
1da177e4
LT		 624 bus_master:1, /* Vortex can only do a fragment bus-m. */
625 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
626 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
627 partner_flow_ctrl:1, /* Partner supports flow control */
628 has_nway:1,
629 enable_wol:1, /* Wake-on-LAN is enabled */
630 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
631 open:1,
632 medialock:1,
633 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
634 large_frames:1; /* accept large frames */
635 int drv_flags;
636 u16 status_enable;
637 u16 intr_enable;
638 u16 available_media; /* From Wn3_Options. */
639 u16 capabilities, info1, info2; /* Various, from EEPROM. */
640 u16 advertising; /* NWay media advertisement */
641 unsigned char phys[2]; /* MII device addresses. */
642 u16 deferred; /* Resend these interrupts when we
643 * bale from the ISR */
644 u16 io_size; /* Size of PCI region (for release_region) */
645 spinlock_t lock; /* Serialise access to device & its vortex_private */
646 struct mii_if_info mii; /* MII lib hooks/info */
647};
648
649#ifdef CONFIG_PCI
650#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
651#else
652#define DEVICE_PCI(dev) NULL
653#endif
654
655#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
656
657#ifdef CONFIG_EISA
658#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
659#else
660#define DEVICE_EISA(dev) NULL
661#endif
662
663#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
664
665/* The action to take with a media selection timer tick.
666 Note that we deviate from the 3Com order by checking 10base2 before AUI.
667 */
668enum xcvr_types {
669 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
670 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
671};
672
f71e1309 673static const struct media_table {
1da177e4
LT		 674 char *name;
675 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
676 mask:8, /* The transceiver-present bit in Wn3_Config.*/
677 next:8; /* The media type to try next. */
678 int wait; /* Time before we check media status. */
679} media_tbl[] = {
680 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
681 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
682 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
683 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
684 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
685 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
686 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
687 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
688 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
689 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
691};
692
693static struct {
694 const char str[ETH_GSTRING_LEN];
695} ethtool_stats_keys[] = {
696 { "tx_deferred" },
8d1d0340 697 { "tx_max_collisions" },
1da177e4 698 { "tx_multiple_collisions" },
8d1d0340 699 { "tx_single_collisions" },
1da177e4
LT		 700 { "rx_bad_ssd" },
701};
702
703/* number of ETHTOOL_GSTATS u64's */
8d1d0340 704#define VORTEX_NUM_STATS 5
1da177e4 705
62afe595 706static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4
LT		 707 int chip_idx, int card_idx);
708static void vortex_up(struct net_device *dev);
709static void vortex_down(struct net_device *dev, int final);
710static int vortex_open(struct net_device *dev);
62afe595 711static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 712static int mdio_read(struct net_device *dev, int phy_id, int location);
713static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
714static void vortex_timer(unsigned long arg);
715static void rx_oom_timer(unsigned long arg);
716static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
717static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
718static int vortex_rx(struct net_device *dev);
719static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 720static irqreturn_t vortex_interrupt(int irq, void *dev_id);
721static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 722static int vortex_close(struct net_device *dev);
723static void dump_tx_ring(struct net_device *dev);
62afe595 724static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 725static struct net_device_stats *vortex_get_stats(struct net_device *dev);
726static void set_rx_mode(struct net_device *dev);
727#ifdef CONFIG_PCI
728static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
729#endif
730static void vortex_tx_timeout(struct net_device *dev);
731static void acpi_set_WOL(struct net_device *dev);
7282d491 732static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 733static void set_8021q_mode(struct net_device *dev, int enable);
734
1da177e4
LT		 735/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
736/* Option count limit only -- unlimited interfaces are supported. */
737#define MAX_UNITS 8
9954ab7f
JL		 738static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
739static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
740static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
741static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
742static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 743static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 744static int global_options = -1;
745static int global_full_duplex = -1;
746static int global_enable_wol = -1;
900fd17d 747static int global_use_mmio = -1;
1da177e4 748
1da177e4
LT		 749/* Variables to work-around the Compaq PCI BIOS32 problem. */
750static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
751static struct net_device *compaq_net_device;
752
753static int vortex_cards_found;
754
755module_param(debug, int, 0);
756module_param(global_options, int, 0);
757module_param_array(options, int, NULL, 0);
758module_param(global_full_duplex, int, 0);
759module_param_array(full_duplex, int, NULL, 0);
760module_param_array(hw_checksums, int, NULL, 0);
761module_param_array(flow_ctrl, int, NULL, 0);
762module_param(global_enable_wol, int, 0);
763module_param_array(enable_wol, int, NULL, 0);
764module_param(rx_copybreak, int, 0);
765module_param(max_interrupt_work, int, 0);
766module_param(compaq_ioaddr, int, 0);
767module_param(compaq_irq, int, 0);
768module_param(compaq_device_id, int, 0);
769module_param(watchdog, int, 0);
900fd17d
JL		 770module_param(global_use_mmio, int, 0);
771module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 772MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
773MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
774MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
775MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 776MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 777MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
778MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
779MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 780MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 781MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
782MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
783MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
784MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
785MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
786MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 787MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
788MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 789
790#ifdef CONFIG_NET_POLL_CONTROLLER
791static void poll_vortex(struct net_device *dev)
792{
793 struct vortex_private *vp = netdev_priv(dev);
794 unsigned long flags;
0d38ff1d 795 local_irq_save(flags);
7d12e780 796 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 797 local_irq_restore(flags);
6aa20a22 798}
1da177e4
LT		 799#endif
800
801#ifdef CONFIG_PM
802
a880c4cd 803static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 804{
805 struct net_device *dev = pci_get_drvdata(pdev);
806
807 if (dev && dev->priv) {
808 if (netif_running(dev)) {
809 netif_device_detach(dev);
810 vortex_down(dev, 1);
811 }
5b039e68
RW		 812 pci_save_state(pdev);
813 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
814 free_irq(dev->irq, dev);
815 pci_disable_device(pdev);
816 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 817 }
818 return 0;
819}
820
a880c4cd 821static int vortex_resume(struct pci_dev *pdev)
1da177e4
LT		 822{
823 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 824 struct vortex_private *vp = netdev_priv(dev);
e1265153 825 int err;
1da177e4 826
5b039e68
RW		 827 if (dev && vp) {
828 pci_set_power_state(pdev, PCI_D0);
829 pci_restore_state(pdev);
e1265153
DM		 830 err = pci_enable_device(pdev);
831 if (err) {
832 printk(KERN_WARNING "%s: Could not enable device \n",
833 dev->name);
834 return err;
835 }
5b039e68
RW		 836 pci_set_master(pdev);
837 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 838 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
5b039e68
RW		 839 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
840 pci_disable_device(pdev);
841 return -EBUSY;
842 }
1da177e4
LT		 843 if (netif_running(dev)) {
844 vortex_up(dev);
845 netif_device_attach(dev);
846 }
847 }
848 return 0;
849}
850
851#endif /* CONFIG_PM */
852
853#ifdef CONFIG_EISA
854static struct eisa_device_id vortex_eisa_ids[] = {
855 { "TCM5920", CH_3C592 },
856 { "TCM5970", CH_3C597 },
857 { "" }
858};
07563c71 859MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 860
a880c4cd
SK		 861static int vortex_eisa_probe(struct device *device);
862static int vortex_eisa_remove(struct device *device);
1da177e4
LT		 863
864static struct eisa_driver vortex_eisa_driver = {
865 .id_table = vortex_eisa_ids,
866 .driver = {
867 .name = "3c59x",
868 .probe = vortex_eisa_probe,
869 .remove = vortex_eisa_remove
870 }
871};
872
a880c4cd 873static int vortex_eisa_probe(struct device *device)
1da177e4 874{
62afe595 875 void __iomem *ioaddr;
1da177e4
LT		 876 struct eisa_device *edev;
877
a880c4cd 878 edev = to_eisa_device(device);
1da177e4 879
62afe595 880 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 881 return -EBUSY;
882
62afe595
JL		 883 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
884
885 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 886 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 887 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 888 return -ENODEV;
889 }
890
891 vortex_cards_found++;
892
893 return 0;
894}
895
a880c4cd 896static int vortex_eisa_remove(struct device *device)
1da177e4
LT		 897{
898 struct eisa_device *edev;
899 struct net_device *dev;
900 struct vortex_private *vp;
62afe595 901 void __iomem *ioaddr;
1da177e4 902
a880c4cd
SK		 903 edev = to_eisa_device(device);
904 dev = eisa_get_drvdata(edev);
1da177e4
LT		 905
906 if (!dev) {
907 printk("vortex_eisa_remove called for Compaq device!\n");
908 BUG();
909 }
910
911 vp = netdev_priv(dev);
62afe595 912 ioaddr = vp->ioaddr;
6aa20a22 913
a880c4cd
SK		 914 unregister_netdev(dev);
915 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
916 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 917
a880c4cd 918 free_netdev(dev);
1da177e4
LT		 919 return 0;
920}
921#endif
922
923/* returns count found (>= 0), or negative on error */
a880c4cd 924static int __init vortex_eisa_init(void)
1da177e4
LT		 925{
926 int eisa_found = 0;
927 int orig_cards_found = vortex_cards_found;
928
929#ifdef CONFIG_EISA
c2f6fabb
BH		 930 int err;
931
932 err = eisa_driver_register (&vortex_eisa_driver);
933 if (!err) {
934 /*
935 * Because of the way EISA bus is probed, we cannot assume
936 * any device have been found when we exit from
937 * eisa_driver_register (the bus root driver may not be
938 * initialized yet). So we blindly assume something was
939 * found, and let the sysfs magic happend...
940 */
941 eisa_found = 1;
1da177e4
LT		 942 }
943#endif
6aa20a22 944
1da177e4
LT		 945 /* Special code to work-around the Compaq PCI BIOS32 problem. */
946 if (compaq_ioaddr) {
62afe595
JL		 947 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
948 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 949 }
950
951 return vortex_cards_found - orig_cards_found + eisa_found;
952}
953
954/* returns count (>= 0), or negative on error */
a880c4cd 955static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 956 const struct pci_device_id *ent)
957{
900fd17d
JL		 958 int rc, unit, pci_bar;
959 struct vortex_chip_info *vci;
960 void __iomem *ioaddr;
1da177e4 961
6aa20a22 962 /* wake up and enable device */
a880c4cd 963 rc = pci_enable_device(pdev);
1da177e4
LT		 964 if (rc < 0)
965 goto out;
966
900fd17d
JL		 967 unit = vortex_cards_found;
968
969 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
970 /* Determine the default if the user didn't override us */
971 vci = &vortex_info_tbl[ent->driver_data];
972 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
973 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
974 pci_bar = use_mmio[unit] ? 1 : 0;
975 else
976 pci_bar = global_use_mmio ? 1 : 0;
977
978 ioaddr = pci_iomap(pdev, pci_bar, 0);
979 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
980 ioaddr = pci_iomap(pdev, 0, 0);
981
982 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
983 ent->driver_data, unit);
1da177e4 984 if (rc < 0) {
a880c4cd 985 pci_disable_device(pdev);
1da177e4
LT		 986 goto out;
987 }
988
989 vortex_cards_found++;
990
991out:
992 return rc;
993}
994
995/*
996 * Start up the PCI/EISA device which is described by *gendev.
997 * Return 0 on success.
998 *
999 * NOTE: pdev can be NULL, for the case of a Compaq device
1000 */
1001static int __devinit vortex_probe1(struct device *gendev,
62afe595 1002 void __iomem *ioaddr, int irq,
1da177e4
LT		 1003 int chip_idx, int card_idx)
1004{
1005 struct vortex_private *vp;
1006 int option;
1007 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1008 int i, step;
1009 struct net_device *dev;
1010 static int printed_version;
1011 int retval, print_info;
1012 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1013 char *print_name = "3c59x";
1014 struct pci_dev *pdev = NULL;
1015 struct eisa_device *edev = NULL;
1016
1017 if (!printed_version) {
1018 printk (version);
1019 printed_version = 1;
1020 }
1021
1022 if (gendev) {
1023 if ((pdev = DEVICE_PCI(gendev))) {
1024 print_name = pci_name(pdev);
1025 }
1026
1027 if ((edev = DEVICE_EISA(gendev))) {
1028 print_name = edev->dev.bus_id;
1029 }
1030 }
1031
1032 dev = alloc_etherdev(sizeof(*vp));
1033 retval = -ENOMEM;
1034 if (!dev) {
1035 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1036 goto out;
1037 }
1038 SET_MODULE_OWNER(dev);
1039 SET_NETDEV_DEV(dev, gendev);
1040 vp = netdev_priv(dev);
1041
1042 option = global_options;
1043
1044 /* The lower four bits are the media type. */
1045 if (dev->mem_start) {
1046 /*
1047 * The 'options' param is passed in as the third arg to the
1048 * LILO 'ether=' argument for non-modular use
1049 */
1050 option = dev->mem_start;
1051 }
1052 else if (card_idx < MAX_UNITS) {
1053 if (options[card_idx] >= 0)
1054 option = options[card_idx];
1055 }
1056
1057 if (option > 0) {
1058 if (option & 0x8000)
1059 vortex_debug = 7;
1060 if (option & 0x4000)
1061 vortex_debug = 2;
1062 if (option & 0x0400)
1063 vp->enable_wol = 1;
1064 }
1065
1066 print_info = (vortex_debug > 1);
1067 if (print_info)
1068 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1069
61238602 1070 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1071 print_name,
1072 pdev ? "PCI" : "EISA",
1073 vci->name,
1074 ioaddr);
1075
62afe595 1076 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1077 dev->irq = irq;
1078 dev->mtu = mtu;
62afe595 1079 vp->ioaddr = ioaddr;
1da177e4
LT		 1080 vp->large_frames = mtu > 1500;
1081 vp->drv_flags = vci->drv_flags;
1082 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1083 vp->io_size = vci->io_size;
1084 vp->card_idx = card_idx;
1085
1086 /* module list only for Compaq device */
1087 if (gendev == NULL) {
1088 compaq_net_device = dev;
1089 }
1090
1091 /* PCI-only startup logic */
1092 if (pdev) {
1093 /* EISA resources already marked, so only PCI needs to do this here */
1094 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1095 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1096 vp->must_free_region = 1;
1097
6aa20a22 1098 /* enable bus-mastering if necessary */
1da177e4 1099 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1100 pci_set_master(pdev);
1da177e4
LT		 1101
1102 if (vci->drv_flags & IS_VORTEX) {
1103 u8 pci_latency;
1104 u8 new_latency = 248;
1105
1106 /* Check the PCI latency value. On the 3c590 series the latency timer
1107 must be set to the maximum value to avoid data corruption that occurs
1108 when the timer expires during a transfer. This bug exists the Vortex
1109 chip only. */
1110 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1111 if (pci_latency < new_latency) {
1112 printk(KERN_INFO "%s: Overriding PCI latency"
1113 " timer (CFLT) setting of %d, new value is %d.\n",
1114 print_name, pci_latency, new_latency);
1115 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1116 }
1117 }
1118 }
1119
1120 spin_lock_init(&vp->lock);
1121 vp->gendev = gendev;
1122 vp->mii.dev = dev;
1123 vp->mii.mdio_read = mdio_read;
1124 vp->mii.mdio_write = mdio_write;
1125 vp->mii.phy_id_mask = 0x1f;
1126 vp->mii.reg_num_mask = 0x1f;
1127
1128 /* Makes sure rings are at least 16 byte aligned. */
1129 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1130 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1131 &vp->rx_ring_dma);
1132 retval = -ENOMEM;
1133 if (vp->rx_ring == 0)
1134 goto free_region;
1135
1136 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1137 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1138
1139 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1140 * instead of a module list */
1da177e4
LT		 1141 if (pdev)
1142 pci_set_drvdata(pdev, dev);
1143 if (edev)
a880c4cd 1144 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1145
1146 vp->media_override = 7;
1147 if (option >= 0) {
1148 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1149 if (vp->media_override != 7)
1150 vp->medialock = 1;
1151 vp->full_duplex = (option & 0x200) ? 1 : 0;
1152 vp->bus_master = (option & 16) ? 1 : 0;
1153 }
1154
1155 if (global_full_duplex > 0)
1156 vp->full_duplex = 1;
1157 if (global_enable_wol > 0)
1158 vp->enable_wol = 1;
1159
1160 if (card_idx < MAX_UNITS) {
1161 if (full_duplex[card_idx] > 0)
1162 vp->full_duplex = 1;
1163 if (flow_ctrl[card_idx] > 0)
1164 vp->flow_ctrl = 1;
1165 if (enable_wol[card_idx] > 0)
1166 vp->enable_wol = 1;
1167 }
1168
125d5ce8 1169 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1170 vp->options = option;
1171 /* Read the station address from the EEPROM. */
1172 EL3WINDOW(0);
1173 {
1174 int base;
1175
1176 if (vci->drv_flags & EEPROM_8BIT)
1177 base = 0x230;
1178 else if (vci->drv_flags & EEPROM_OFFSET)
1179 base = EEPROM_Read + 0x30;
1180 else
1181 base = EEPROM_Read;
1182
1183 for (i = 0; i < 0x40; i++) {
1184 int timer;
62afe595 1185 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1186 /* Pause for at least 162 us. for the read to take place. */
1187 for (timer = 10; timer >= 0; timer--) {
1188 udelay(162);
62afe595 1189 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1190 break;
1191 }
62afe595 1192 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1193 }
1194 }
1195 for (i = 0; i < 0x18; i++)
1196 checksum ^= eeprom[i];
1197 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1198 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1199 while (i < 0x21)
1200 checksum ^= eeprom[i++];
1201 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1202 }
1203 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1204 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1205 for (i = 0; i < 3; i++)
1206 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1207 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1208 if (print_info) {
1209 for (i = 0; i < 6; i++)
1210 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1211 }
1212 /* Unfortunately an all zero eeprom passes the checksum and this
1213 gets found in the wild in failure cases. Crypto is hard 8) */
1214 if (!is_valid_ether_addr(dev->dev_addr)) {
1215 retval = -EINVAL;
1216 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1217 goto free_ring; /* With every pack */
1218 }
1219 EL3WINDOW(2);
1220 for (i = 0; i < 6; i++)
62afe595 1221 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1222
1da177e4
LT		 1223 if (print_info)
1224 printk(", IRQ %d\n", dev->irq);
1225 /* Tell them about an invalid IRQ. */
1226 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1227 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1228 dev->irq);
1da177e4
LT		 1229
1230 EL3WINDOW(4);
62afe595 1231 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1232 if (print_info) {
1233 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1234 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1235 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1236 }
1237
1238
1239 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1240 unsigned short n;
1241
62afe595
JL		 1242 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1243 if (!vp->cb_fn_base) {
1da177e4 1244 retval = -ENOMEM;
62afe595 1245 goto free_ring;
1da177e4 1246 }
62afe595 1247
1da177e4 1248 if (print_info) {
7c7459d1
GKH		 1249 printk(KERN_INFO "%s: CardBus functions mapped "
1250 "%16.16llx->%p\n",
1251 print_name,
1252 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1253 vp->cb_fn_base);
1da177e4
LT		 1254 }
1255 EL3WINDOW(2);
1256
62afe595 1257 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1258 if (vp->drv_flags & INVERT_LED_PWR)
1259 n |= 0x10;
1260 if (vp->drv_flags & INVERT_MII_PWR)
1261 n |= 0x4000;
62afe595 1262 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1263 if (vp->drv_flags & WNO_XCVR_PWR) {
1264 EL3WINDOW(0);
62afe595 1265 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1266 }
1267 }
1268
1269 /* Extract our information from the EEPROM data. */
1270 vp->info1 = eeprom[13];
1271 vp->info2 = eeprom[15];
1272 vp->capabilities = eeprom[16];
1273
1274 if (vp->info1 & 0x8000) {
1275 vp->full_duplex = 1;
1276 if (print_info)
1277 printk(KERN_INFO "Full duplex capable\n");
1278 }
1279
1280 {
f71e1309 1281 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1282 unsigned int config;
1283 EL3WINDOW(3);
62afe595 1284 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1285 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1286 vp->available_media = 0x40;
62afe595 1287 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1288 if (print_info) {
1289 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1290 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1291 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1292 8 << RAM_SIZE(config),
1293 RAM_WIDTH(config) ? "word" : "byte",
1294 ram_split[RAM_SPLIT(config)],
1295 AUTOSELECT(config) ? "autoselect/" : "",
1296 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1297 media_tbl[XCVR(config)].name);
1298 }
1299 vp->default_media = XCVR(config);
1300 if (vp->default_media == XCVR_NWAY)
1301 vp->has_nway = 1;
1302 vp->autoselect = AUTOSELECT(config);
1303 }
1304
1305 if (vp->media_override != 7) {
1306 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1307 print_name, vp->media_override,
1308 media_tbl[vp->media_override].name);
1309 dev->if_port = vp->media_override;
1310 } else
1311 dev->if_port = vp->default_media;
1312
1313 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1314 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1315 int phy, phy_idx = 0;
1316 EL3WINDOW(4);
1317 mii_preamble_required++;
1318 if (vp->drv_flags & EXTRA_PREAMBLE)
1319 mii_preamble_required++;
1320 mdio_sync(ioaddr, 32);
106427e6 1321 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1322 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1323 int mii_status, phyx;
1324
1325 /*
1326 * For the 3c905CX we look at index 24 first, because it bogusly
1327 * reports an external PHY at all indices
1328 */
1329 if (phy == 0)
1330 phyx = 24;
1331 else if (phy <= 24)
1332 phyx = phy - 1;
1333 else
1334 phyx = phy;
106427e6 1335 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1336 if (mii_status && mii_status != 0xffff) {
1337 vp->phys[phy_idx++] = phyx;
1338 if (print_info) {
1339 printk(KERN_INFO " MII transceiver found at address %d,"
1340 " status %4x.\n", phyx, mii_status);
1341 }
1342 if ((mii_status & 0x0040) == 0)
1343 mii_preamble_required++;
1344 }
1345 }
1346 mii_preamble_required--;
1347 if (phy_idx == 0) {
1348 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1349 vp->phys[0] = 24;
1350 } else {
106427e6 1351 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1352 if (vp->full_duplex) {
1353 /* Only advertise the FD media types. */
1354 vp->advertising &= ~0x02A0;
1355 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1356 }
1357 }
1358 vp->mii.phy_id = vp->phys[0];
1359 }
1360
1361 if (vp->capabilities & CapBusMaster) {
1362 vp->full_bus_master_tx = 1;
1363 if (print_info) {
1364 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1365 (vp->info2 & 1) ? "early" : "whole-frame" );
1366 }
1367 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1368 vp->bus_master = 0; /* AKPM: vortex only */
1369 }
1370
1371 /* The 3c59x-specific entries in the device structure. */
1372 dev->open = vortex_open;
1373 if (vp->full_bus_master_tx) {
1374 dev->hard_start_xmit = boomerang_start_xmit;
1375 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1376 if (card_idx < MAX_UNITS &&
1377 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1378 hw_checksums[card_idx] == 1)) {
d311b0d3 1379 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4
LT		 1380 }
1381 } else {
1382 dev->hard_start_xmit = vortex_start_xmit;
1383 }
1384
1385 if (print_info) {
1386 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1387 print_name,
1388 (dev->features & NETIF_F_SG) ? "en":"dis",
1389 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1390 }
1391
1392 dev->stop = vortex_close;
1393 dev->get_stats = vortex_get_stats;
1394#ifdef CONFIG_PCI
1395 dev->do_ioctl = vortex_ioctl;
1396#endif
1397 dev->ethtool_ops = &vortex_ethtool_ops;
1398 dev->set_multicast_list = set_rx_mode;
1399 dev->tx_timeout = vortex_tx_timeout;
1400 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1401#ifdef CONFIG_NET_POLL_CONTROLLER
6aa20a22 1402 dev->poll_controller = poll_vortex;
1da177e4
LT		 1403#endif
1404 if (pdev) {
1405 vp->pm_state_valid = 1;
1406 pci_save_state(VORTEX_PCI(vp));
1407 acpi_set_WOL(dev);
1408 }
1409 retval = register_netdev(dev);
1410 if (retval == 0)
1411 return 0;
1412
1413free_ring:
1414 pci_free_consistent(pdev,
1415 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1416 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1417 vp->rx_ring,
1418 vp->rx_ring_dma);
1419free_region:
1420 if (vp->must_free_region)
62afe595 1421 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1422 free_netdev(dev);
1423 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1424out:
1425 return retval;
1426}
1427
1428static void
1429issue_and_wait(struct net_device *dev, int cmd)
1430{
62afe595
JL		 1431 struct vortex_private *vp = netdev_priv(dev);
1432 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1433 int i;
1434
62afe595 1435 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1436 for (i = 0; i < 2000; i++) {
62afe595 1437 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1438 return;
1439 }
1440
1441 /* OK, that didn't work. Do it the slow way. One second */
1442 for (i = 0; i < 100000; i++) {
62afe595 1443 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1444 if (vortex_debug > 1)
1445 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1446 dev->name, cmd, i * 10);
1447 return;
1448 }
1449 udelay(10);
1450 }
1451 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1452 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1453}
1454
125d5ce8
SK		 1455static void
1456vortex_set_duplex(struct net_device *dev)
1457{
1458 struct vortex_private *vp = netdev_priv(dev);
1459 void __iomem *ioaddr = vp->ioaddr;
1460
1461 printk(KERN_INFO "%s: setting %s-duplex.\n",
1462 dev->name, (vp->full_duplex) ? "full" : "half");
1463
1464 EL3WINDOW(3);
1465 /* Set the full-duplex bit. */
1466 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1467 (vp->large_frames ? 0x40 : 0) |
1468 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1469 0x100 : 0),
1470 ioaddr + Wn3_MAC_Ctrl);
125d5ce8
SK		 1471}
1472
1473static void vortex_check_media(struct net_device *dev, unsigned int init)
1474{
1475 struct vortex_private *vp = netdev_priv(dev);
1476 unsigned int ok_to_print = 0;
1477
1478 if (vortex_debug > 3)
1479 ok_to_print = 1;
1480
1481 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1482 vp->full_duplex = vp->mii.full_duplex;
1483 vortex_set_duplex(dev);
1484 } else if (init) {
1485 vortex_set_duplex(dev);
1486 }
1487}
1488
1da177e4
LT		 1489static void
1490vortex_up(struct net_device *dev)
1491{
1da177e4 1492 struct vortex_private *vp = netdev_priv(dev);
62afe595 1493 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1494 unsigned int config;
09ce3512 1495 int i, mii_reg1, mii_reg5;
1da177e4
LT		 1496
1497 if (VORTEX_PCI(vp)) {
1498 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1499 if (vp->pm_state_valid)
1500 pci_restore_state(VORTEX_PCI(vp));
1da177e4
LT		 1501 pci_enable_device(VORTEX_PCI(vp));
1502 }
1503
1504 /* Before initializing select the active media port. */
1505 EL3WINDOW(3);
62afe595 1506 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1507
1508 if (vp->media_override != 7) {
1509 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1510 dev->name, vp->media_override,
1511 media_tbl[vp->media_override].name);
1512 dev->if_port = vp->media_override;
1513 } else if (vp->autoselect) {
1514 if (vp->has_nway) {
1515 if (vortex_debug > 1)
1516 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1517 dev->name, dev->if_port);
1518 dev->if_port = XCVR_NWAY;
1519 } else {
1520 /* Find first available media type, starting with 100baseTx. */
1521 dev->if_port = XCVR_100baseTx;
1522 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1523 dev->if_port = media_tbl[dev->if_port].next;
1524 if (vortex_debug > 1)
1525 printk(KERN_INFO "%s: first available media type: %s\n",
1526 dev->name, media_tbl[dev->if_port].name);
1527 }
1528 } else {
1529 dev->if_port = vp->default_media;
1530 if (vortex_debug > 1)
1531 printk(KERN_INFO "%s: using default media %s\n",
1532 dev->name, media_tbl[dev->if_port].name);
1533 }
1534
1535 init_timer(&vp->timer);
1536 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1537 vp->timer.data = (unsigned long)dev;
1538 vp->timer.function = vortex_timer; /* timer handler */
1539 add_timer(&vp->timer);
1540
1541 init_timer(&vp->rx_oom_timer);
1542 vp->rx_oom_timer.data = (unsigned long)dev;
1543 vp->rx_oom_timer.function = rx_oom_timer;
1544
1545 if (vortex_debug > 1)
1546 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1547 dev->name, media_tbl[dev->if_port].name);
1548
125d5ce8 1549 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1550 config = BFINS(config, dev->if_port, 20, 4);
1551 if (vortex_debug > 6)
1552 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1553 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1554
1555 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1556 EL3WINDOW(4);
09ce3512
SK		 1557 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1558 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1559 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1560
125d5ce8 1561 vortex_check_media(dev, 1);
1da177e4 1562 }
125d5ce8
SK		 1563 else
1564 vortex_set_duplex(dev);
1da177e4 1565
09ce3512
SK		 1566 issue_and_wait(dev, TxReset);
1567 /*
1568 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1569 */
1570 issue_and_wait(dev, RxReset|0x04);
1571
1da177e4 1572
62afe595 1573 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1574
1575 if (vortex_debug > 1) {
1576 EL3WINDOW(4);
1577 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1578 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1579 }
1580
1581 /* Set the station address and mask in window 2 each time opened. */
1582 EL3WINDOW(2);
1583 for (i = 0; i < 6; i++)
62afe595 1584 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1585 for (; i < 12; i+=2)
62afe595 1586 iowrite16(0, ioaddr + i);
1da177e4
LT		 1587
1588 if (vp->cb_fn_base) {
62afe595 1589 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1590 if (vp->drv_flags & INVERT_LED_PWR)
1591 n |= 0x10;
1592 if (vp->drv_flags & INVERT_MII_PWR)
1593 n |= 0x4000;
62afe595 1594 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1595 }
1596
1597 if (dev->if_port == XCVR_10base2)
1598 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1599 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1600 if (dev->if_port != XCVR_NWAY) {
1601 EL3WINDOW(4);
62afe595 1602 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1603 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1604 }
1605
1606 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1607 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1608 EL3WINDOW(6);
1609 for (i = 0; i < 10; i++)
62afe595
JL		 1610 ioread8(ioaddr + i);
1611 ioread16(ioaddr + 10);
1612 ioread16(ioaddr + 12);
1da177e4
LT		 1613 /* New: On the Vortex we must also clear the BadSSD counter. */
1614 EL3WINDOW(4);
62afe595 1615 ioread8(ioaddr + 12);
1da177e4 1616 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1617 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1618
1619 /* Switch to register set 7 for normal use. */
1620 EL3WINDOW(7);
1621
1622 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1623 vp->cur_rx = vp->dirty_rx = 0;
1624 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1625 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1626 iowrite32(0x0020, ioaddr + PktStatus);
1627 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1628 }
1629 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1630 vp->cur_tx = vp->dirty_tx = 0;
1631 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1632 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1633 /* Clear the Rx, Tx rings. */
1634 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1635 vp->rx_ring[i].status = 0;
1636 for (i = 0; i < TX_RING_SIZE; i++)
1637 vp->tx_skbuff[i] = NULL;
62afe595 1638 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1639 }
1640 /* Set receiver mode: presumably accept b-case and phys addr only. */
1641 set_rx_mode(dev);
1642 /* enable 802.1q tagged frames */
1643 set_8021q_mode(dev, 1);
62afe595 1644 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1645
62afe595
JL		 1646 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1647 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1648 /* Allow status bits to be seen. */
1649 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1650 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1651 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1652 (vp->bus_master ? DMADone : 0);
1653 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1654 (vp->full_bus_master_rx ? 0 : RxComplete) |
1655 StatsFull | HostError | TxComplete | IntReq
1656 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1657 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1658 /* Ack all pending events, and set active indicator mask. */
62afe595 1659 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1660 ioaddr + EL3_CMD);
62afe595 1661 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1662 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1663 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4
LT		 1664 netif_start_queue (dev);
1665}
1666
1667static int
1668vortex_open(struct net_device *dev)
1669{
1670 struct vortex_private *vp = netdev_priv(dev);
1671 int i;
1672 int retval;
1673
1674 /* Use the now-standard shared IRQ implementation. */
1675 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1676 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1da177e4
LT		 1677 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1678 goto out;
1679 }
1680
1681 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1682 if (vortex_debug > 2)
1683 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1684 for (i = 0; i < RX_RING_SIZE; i++) {
1685 struct sk_buff *skb;
1686 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1687 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1688 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1689 skb = dev_alloc_skb(PKT_BUF_SZ);
1690 vp->rx_skbuff[i] = skb;
1691 if (skb == NULL)
1692 break; /* Bad news! */
1693 skb->dev = dev; /* Mark as being used by this device. */
1694 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1695 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1696 }
1697 if (i != RX_RING_SIZE) {
1698 int j;
1699 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1700 for (j = 0; j < i; j++) {
1701 if (vp->rx_skbuff[j]) {
1702 dev_kfree_skb(vp->rx_skbuff[j]);
1703 vp->rx_skbuff[j] = NULL;
1704 }
1705 }
1706 retval = -ENOMEM;
1707 goto out_free_irq;
1708 }
1709 /* Wrap the ring. */
1710 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1711 }
1712
1713 vortex_up(dev);
1714 return 0;
1715
1716out_free_irq:
1717 free_irq(dev->irq, dev);
1718out:
1719 if (vortex_debug > 1)
1720 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1721 return retval;
1722}
1723
1724static void
1725vortex_timer(unsigned long data)
1726{
1727 struct net_device *dev = (struct net_device *)data;
1728 struct vortex_private *vp = netdev_priv(dev);
62afe595 1729 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1730 int next_tick = 60*HZ;
1731 int ok = 0;
125d5ce8 1732 int media_status, old_window;
1da177e4
LT		 1733
1734 if (vortex_debug > 2) {
1735 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1736 dev->name, media_tbl[dev->if_port].name);
1737 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1738 }
1739
0a9da4bd 1740 disable_irq_lockdep(dev->irq);
62afe595 1741 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1742 EL3WINDOW(4);
62afe595 1743 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1744 switch (dev->if_port) {
1745 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1746 if (media_status & Media_LnkBeat) {
1747 netif_carrier_on(dev);
1748 ok = 1;
1749 if (vortex_debug > 1)
1750 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1751 dev->name, media_tbl[dev->if_port].name, media_status);
1752 } else {
1753 netif_carrier_off(dev);
1754 if (vortex_debug > 1) {
1755 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1756 dev->name, media_tbl[dev->if_port].name, media_status);
1757 }
1758 }
1759 break;
1760 case XCVR_MII: case XCVR_NWAY:
1761 {
1da177e4 1762 ok = 1;
125d5ce8
SK		 1763 spin_lock_bh(&vp->lock);
1764 vortex_check_media(dev, 0);
1da177e4
LT		 1765 spin_unlock_bh(&vp->lock);
1766 }
1767 break;
1768 default: /* Other media types handled by Tx timeouts. */
1769 if (vortex_debug > 1)
1770 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1771 dev->name, media_tbl[dev->if_port].name, media_status);
1772 ok = 1;
1773 }
b4ff6450
SK		 1774
1775 if (!netif_carrier_ok(dev))
1776 next_tick = 5*HZ;
1777
e94d10eb
SK		 1778 if (vp->medialock)
1779 goto leave_media_alone;
1780
a880c4cd 1781 if (!ok) {
1da177e4
LT		 1782 unsigned int config;
1783
1784 do {
1785 dev->if_port = media_tbl[dev->if_port].next;
1786 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1787 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1788 dev->if_port = vp->default_media;
1789 if (vortex_debug > 1)
1790 printk(KERN_DEBUG "%s: Media selection failing, using default "
1791 "%s port.\n",
1792 dev->name, media_tbl[dev->if_port].name);
1793 } else {
1794 if (vortex_debug > 1)
1795 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1796 "%s port.\n",
1797 dev->name, media_tbl[dev->if_port].name);
1798 next_tick = media_tbl[dev->if_port].wait;
1799 }
62afe595 1800 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1801 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1802
1803 EL3WINDOW(3);
62afe595 1804 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1805 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1806 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1807
62afe595 1808 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1809 ioaddr + EL3_CMD);
1810 if (vortex_debug > 1)
1811 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1812 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1813 }
1da177e4
LT		 1814
1815leave_media_alone:
1816 if (vortex_debug > 2)
1817 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1818 dev->name, media_tbl[dev->if_port].name);
1819
e94d10eb 1820 EL3WINDOW(old_window);
0a9da4bd 1821 enable_irq_lockdep(dev->irq);
1da177e4
LT		 1822 mod_timer(&vp->timer, RUN_AT(next_tick));
1823 if (vp->deferred)
62afe595 1824 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1825 return;
1826}
1827
1828static void vortex_tx_timeout(struct net_device *dev)
1829{
1830 struct vortex_private *vp = netdev_priv(dev);
62afe595 1831 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1832
1833 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1834 dev->name, ioread8(ioaddr + TxStatus),
1835 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1836 EL3WINDOW(4);
1837 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 1838 ioread16(ioaddr + Wn4_NetDiag),
1839 ioread16(ioaddr + Wn4_Media),
1840 ioread32(ioaddr + PktStatus),
1841 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 1842 /* Slight code bloat to be user friendly. */
62afe595 1843 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 1844 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1845 " network cable problem?\n", dev->name);
62afe595 1846 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 1847 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1848 " IRQ blocked by another device?\n", dev->name);
1849 /* Bad idea here.. but we might as well handle a few events. */
1850 {
1851 /*
1852 * Block interrupts because vortex_interrupt does a bare spin_lock()
1853 */
1854 unsigned long flags;
1855 local_irq_save(flags);
1856 if (vp->full_bus_master_tx)
7d12e780 1857 boomerang_interrupt(dev->irq, dev);
1da177e4 1858 else
7d12e780 1859 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1860 local_irq_restore(flags);
1861 }
1862 }
1863
1864 if (vortex_debug > 0)
1865 dump_tx_ring(dev);
1866
1867 issue_and_wait(dev, TxReset);
1868
1869 vp->stats.tx_errors++;
1870 if (vp->full_bus_master_tx) {
1871 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1872 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1873 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1874 ioaddr + DownListPtr);
1875 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1876 netif_wake_queue (dev);
1877 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1878 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1879 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 1880 } else {
1881 vp->stats.tx_dropped++;
1882 netif_wake_queue(dev);
1883 }
6aa20a22 1884
1da177e4 1885 /* Issue Tx Enable */
62afe595 1886 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 1887 dev->trans_start = jiffies;
6aa20a22 1888
1da177e4
LT		 1889 /* Switch to register set 7 for normal use. */
1890 EL3WINDOW(7);
1891}
1892
1893/*
1894 * Handle uncommon interrupt sources. This is a separate routine to minimize
1895 * the cache impact.
1896 */
1897static void
1898vortex_error(struct net_device *dev, int status)
1899{
1900 struct vortex_private *vp = netdev_priv(dev);
62afe595 1901 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1902 int do_tx_reset = 0, reset_mask = 0;
1903 unsigned char tx_status = 0;
1904
1905 if (vortex_debug > 2) {
1906 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1907 }
1908
1909 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1910 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 1911 /* Presumably a tx-timeout. We must merely re-enable. */
1912 if (vortex_debug > 2
1913 || (tx_status != 0x88 && vortex_debug > 0)) {
1914 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1915 dev->name, tx_status);
1916 if (tx_status == 0x82) {
1917 printk(KERN_ERR "Probably a duplex mismatch. See "
1918 "Documentation/networking/vortex.txt\n");
1919 }
1920 dump_tx_ring(dev);
1921 }
1922 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
1923 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
0000754c 1924 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1925 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1926 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1927 do_tx_reset = 1;
0000754c
AM		 1928 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1929 do_tx_reset = 1;
1930 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1931 } else { /* Merely re-enable the transmitter. */
62afe595 1932 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1933 }
1934 }
1935
1936 if (status & RxEarly) { /* Rx early is unused. */
1937 vortex_rx(dev);
62afe595 1938 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1939 }
1940 if (status & StatsFull) { /* Empty statistics. */
1941 static int DoneDidThat;
1942 if (vortex_debug > 4)
1943 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1944 update_stats(ioaddr, dev);
1945 /* HACK: Disable statistics as an interrupt source. */
1946 /* This occurs when we have the wrong media type! */
1947 if (DoneDidThat == 0 &&
62afe595 1948 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 1949 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1950 "stats as an interrupt source.\n", dev->name);
1951 EL3WINDOW(5);
62afe595 1952 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 1953 vp->intr_enable &= ~StatsFull;
1954 EL3WINDOW(7);
1955 DoneDidThat++;
1956 }
1957 }
1958 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 1959 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1960 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 1961 }
1962 if (status & HostError) {
1963 u16 fifo_diag;
1964 EL3WINDOW(4);
62afe595 1965 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 1966 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1967 dev->name, fifo_diag);
1968 /* Adapter failure requires Tx/Rx reset and reinit. */
1969 if (vp->full_bus_master_tx) {
62afe595 1970 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 1971 /* 0x80000000 PCI master abort. */
1972 /* 0x40000000 PCI target abort. */
1973 if (vortex_debug)
1974 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1975
1976 /* In this case, blow the card away */
1977 /* Must not enter D3 or we can't legally issue the reset! */
1978 vortex_down(dev, 0);
1979 issue_and_wait(dev, TotalReset | 0xff);
1980 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
1981 } else if (fifo_diag & 0x0400)
1982 do_tx_reset = 1;
1983 if (fifo_diag & 0x3000) {
1984 /* Reset Rx fifo and upload logic */
1985 issue_and_wait(dev, RxReset|0x07);
1986 /* Set the Rx filter to the current state. */
1987 set_rx_mode(dev);
1988 /* enable 802.1q VLAN tagged frames */
1989 set_8021q_mode(dev, 1);
62afe595
JL		 1990 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
1991 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 1992 }
1993 }
1994
1995 if (do_tx_reset) {
1996 issue_and_wait(dev, TxReset|reset_mask);
62afe595 1997 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1998 if (!vp->full_bus_master_tx)
1999 netif_wake_queue(dev);
2000 }
2001}
2002
2003static int
2004vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2005{
2006 struct vortex_private *vp = netdev_priv(dev);
62afe595 2007 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2008
2009 /* Put out the doubleword header... */
62afe595 2010 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2011 if (vp->bus_master) {
2012 /* Set the bus-master controller to transfer the packet. */
2013 int len = (skb->len + 3) & ~3;
a880c4cd 2014 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2015 ioaddr + Wn7_MasterAddr);
62afe595 2016 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2017 vp->tx_skb = skb;
62afe595 2018 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2019 /* netif_wake_queue() will be called at the DMADone interrupt. */
2020 } else {
2021 /* ... and the packet rounded to a doubleword. */
62afe595 2022 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2023 dev_kfree_skb (skb);
62afe595 2024 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2025 netif_start_queue (dev); /* AKPM: redundant? */
2026 } else {
2027 /* Interrupt us when the FIFO has room for max-sized packet. */
2028 netif_stop_queue(dev);
62afe595 2029 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2030 }
2031 }
2032
2033 dev->trans_start = jiffies;
2034
2035 /* Clear the Tx status stack. */
2036 {
2037 int tx_status;
2038 int i = 32;
2039
62afe595 2040 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2041 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2042 if (vortex_debug > 2)
2043 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2044 dev->name, tx_status);
2045 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2046 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2047 if (tx_status & 0x30) {
2048 issue_and_wait(dev, TxReset);
2049 }
62afe595 2050 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2051 }
62afe595 2052 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2053 }
2054 }
2055 return 0;
2056}
2057
2058static int
2059boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2060{
2061 struct vortex_private *vp = netdev_priv(dev);
62afe595 2062 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2063 /* Calculate the next Tx descriptor entry. */
2064 int entry = vp->cur_tx % TX_RING_SIZE;
2065 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2066 unsigned long flags;
2067
2068 if (vortex_debug > 6) {
2069 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2070 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2071 dev->name, vp->cur_tx);
1da177e4
LT		 2072 }
2073
2074 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2075 if (vortex_debug > 0)
2076 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2077 dev->name);
2078 netif_stop_queue(dev);
2079 return 1;
2080 }
2081
2082 vp->tx_skbuff[entry] = skb;
2083
2084 vp->tx_ring[entry].next = 0;
2085#if DO_ZEROCOPY
84fa7933 2086 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2087 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2088 else
2089 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2090
2091 if (!skb_shinfo(skb)->nr_frags) {
2092 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2093 skb->len, PCI_DMA_TODEVICE));
2094 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2095 } else {
2096 int i;
2097
2098 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2099 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2100 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2101
2102 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2103 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2104
2105 vp->tx_ring[entry].frag[i+1].addr =
2106 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2107 (void*)page_address(frag->page) + frag->page_offset,
2108 frag->size, PCI_DMA_TODEVICE));
2109
2110 if (i == skb_shinfo(skb)->nr_frags-1)
2111 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2112 else
2113 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2114 }
2115 }
2116#else
2117 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2118 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2119 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2120#endif
2121
2122 spin_lock_irqsave(&vp->lock, flags);
2123 /* Wait for the stall to complete. */
2124 issue_and_wait(dev, DownStall);
2125 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2126 if (ioread32(ioaddr + DownListPtr) == 0) {
2127 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2128 vp->queued_packet++;
2129 }
2130
2131 vp->cur_tx++;
2132 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2133 netif_stop_queue (dev);
2134 } else { /* Clear previous interrupt enable. */
2135#if defined(tx_interrupt_mitigation)
2136 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2137 * were selected, this would corrupt DN_COMPLETE. No?
2138 */
2139 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2140#endif
2141 }
62afe595 2142 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2143 spin_unlock_irqrestore(&vp->lock, flags);
2144 dev->trans_start = jiffies;
2145 return 0;
2146}
2147
2148/* The interrupt handler does all of the Rx thread work and cleans up
2149 after the Tx thread. */
2150
2151/*
2152 * This is the ISR for the vortex series chips.
2153 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2154 */
2155
2156static irqreturn_t
7d12e780 2157vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2158{
2159 struct net_device *dev = dev_id;
2160 struct vortex_private *vp = netdev_priv(dev);
62afe595 2161 void __iomem *ioaddr;
1da177e4
LT		 2162 int status;
2163 int work_done = max_interrupt_work;
2164 int handled = 0;
2165
62afe595 2166 ioaddr = vp->ioaddr;
1da177e4
LT		 2167 spin_lock(&vp->lock);
2168
62afe595 2169 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2170
2171 if (vortex_debug > 6)
2172 printk("vortex_interrupt(). status=0x%4x\n", status);
2173
2174 if ((status & IntLatch) == 0)
2175 goto handler_exit; /* No interrupt: shared IRQs cause this */
2176 handled = 1;
2177
2178 if (status & IntReq) {
2179 status |= vp->deferred;
2180 vp->deferred = 0;
2181 }
2182
2183 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2184 goto handler_exit;
2185
2186 if (vortex_debug > 4)
2187 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2188 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2189
2190 do {
2191 if (vortex_debug > 5)
2192 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2193 dev->name, status);
2194 if (status & RxComplete)
2195 vortex_rx(dev);
2196
2197 if (status & TxAvailable) {
2198 if (vortex_debug > 5)
2199 printk(KERN_DEBUG " TX room bit was handled.\n");
2200 /* There's room in the FIFO for a full-sized packet. */
62afe595 2201 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2202 netif_wake_queue (dev);
2203 }
2204
2205 if (status & DMADone) {
62afe595
JL		 2206 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2207 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2208 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2209 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2210 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2211 /*
2212 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2213 * insufficient FIFO room, the TxAvailable test will succeed and call
2214 * netif_wake_queue()
2215 */
2216 netif_wake_queue(dev);
2217 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2218 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2219 netif_stop_queue(dev);
2220 }
2221 }
2222 }
2223 /* Check for all uncommon interrupts at once. */
2224 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2225 if (status == 0xffff)
2226 break;
2227 vortex_error(dev, status);
2228 }
2229
2230 if (--work_done < 0) {
2231 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2232 "%4.4x.\n", dev->name, status);
2233 /* Disable all pending interrupts. */
2234 do {
2235 vp->deferred |= status;
62afe595 2236 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2237 ioaddr + EL3_CMD);
62afe595
JL		 2238 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2239 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2240 /* The timer will reenable interrupts. */
2241 mod_timer(&vp->timer, jiffies + 1*HZ);
2242 break;
2243 }
2244 /* Acknowledge the IRQ. */
62afe595
JL		 2245 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2246 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2247
2248 if (vortex_debug > 4)
2249 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2250 dev->name, status);
2251handler_exit:
2252 spin_unlock(&vp->lock);
2253 return IRQ_RETVAL(handled);
2254}
2255
2256/*
2257 * This is the ISR for the boomerang series chips.
2258 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2259 */
2260
2261static irqreturn_t
7d12e780 2262boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2263{
2264 struct net_device *dev = dev_id;
2265 struct vortex_private *vp = netdev_priv(dev);
62afe595 2266 void __iomem *ioaddr;
1da177e4
LT		 2267 int status;
2268 int work_done = max_interrupt_work;
2269
62afe595 2270 ioaddr = vp->ioaddr;
1da177e4
LT		 2271
2272 /*
2273 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2274 * and boomerang_start_xmit
2275 */
2276 spin_lock(&vp->lock);
2277
62afe595 2278 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2279
2280 if (vortex_debug > 6)
2281 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2282
2283 if ((status & IntLatch) == 0)
2284 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2285
2286 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2287 if (vortex_debug > 1)
2288 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2289 goto handler_exit;
2290 }
2291
2292 if (status & IntReq) {
2293 status |= vp->deferred;
2294 vp->deferred = 0;
2295 }
2296
2297 if (vortex_debug > 4)
2298 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2299 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2300 do {
2301 if (vortex_debug > 5)
2302 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2303 dev->name, status);
2304 if (status & UpComplete) {
62afe595 2305 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2306 if (vortex_debug > 5)
2307 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2308 boomerang_rx(dev);
2309 }
2310
2311 if (status & DownComplete) {
2312 unsigned int dirty_tx = vp->dirty_tx;
2313
62afe595 2314 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2315 while (vp->cur_tx - dirty_tx > 0) {
2316 int entry = dirty_tx % TX_RING_SIZE;
2317#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2318 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2319 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2320 break; /* It still hasn't been processed. */
2321#else
2322 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2323 break; /* It still hasn't been processed. */
2324#endif
6aa20a22 2325
1da177e4
LT		 2326 if (vp->tx_skbuff[entry]) {
2327 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2328#if DO_ZEROCOPY
1da177e4
LT		 2329 int i;
2330 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2331 pci_unmap_single(VORTEX_PCI(vp),
2332 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2333 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2334 PCI_DMA_TODEVICE);
2335#else
2336 pci_unmap_single(VORTEX_PCI(vp),
2337 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2338#endif
2339 dev_kfree_skb_irq(skb);
2340 vp->tx_skbuff[entry] = NULL;
2341 } else {
2342 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2343 }
2344 /* vp->stats.tx_packets++; Counted below. */
2345 dirty_tx++;
2346 }
2347 vp->dirty_tx = dirty_tx;
2348 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2349 if (vortex_debug > 6)
2350 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2351 netif_wake_queue (dev);
2352 }
2353 }
2354
2355 /* Check for all uncommon interrupts at once. */
2356 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2357 vortex_error(dev, status);
2358
2359 if (--work_done < 0) {
2360 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2361 "%4.4x.\n", dev->name, status);
2362 /* Disable all pending interrupts. */
2363 do {
2364 vp->deferred |= status;
62afe595 2365 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2366 ioaddr + EL3_CMD);
62afe595
JL		 2367 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2368 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2369 /* The timer will reenable interrupts. */
2370 mod_timer(&vp->timer, jiffies + 1*HZ);
2371 break;
2372 }
2373 /* Acknowledge the IRQ. */
62afe595 2374 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2375 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2376 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2377
62afe595 2378 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2379
2380 if (vortex_debug > 4)
2381 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2382 dev->name, status);
2383handler_exit:
2384 spin_unlock(&vp->lock);
2385 return IRQ_HANDLED;
2386}
2387
2388static int vortex_rx(struct net_device *dev)
2389{
2390 struct vortex_private *vp = netdev_priv(dev);
62afe595 2391 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2392 int i;
2393 short rx_status;
2394
2395 if (vortex_debug > 5)
2396 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2397 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2398 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2399 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2400 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2401 if (vortex_debug > 2)
2402 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2403 vp->stats.rx_errors++;
2404 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2405 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2406 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2407 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2408 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2409 } else {
2410 /* The packet length: up to 4.5K!. */
2411 int pkt_len = rx_status & 0x1fff;
2412 struct sk_buff *skb;
2413
2414 skb = dev_alloc_skb(pkt_len + 5);
2415 if (vortex_debug > 4)
2416 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2417 pkt_len, rx_status);
2418 if (skb != NULL) {
2419 skb->dev = dev;
2420 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2421 /* 'skb_put()' points to the start of sk_buff data area. */
2422 if (vp->bus_master &&
62afe595 2423 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2424 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2425 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2426 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2427 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2428 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2429 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2430 ;
2431 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2432 } else {
62afe595
JL		 2433 ioread32_rep(ioaddr + RX_FIFO,
2434 skb_put(skb, pkt_len),
2435 (pkt_len + 3) >> 2);
1da177e4 2436 }
62afe595 2437 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2438 skb->protocol = eth_type_trans(skb, dev);
2439 netif_rx(skb);
2440 dev->last_rx = jiffies;
2441 vp->stats.rx_packets++;
2442 /* Wait a limited time to go to next packet. */
2443 for (i = 200; i >= 0; i--)
62afe595 2444 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2445 break;
2446 continue;
2447 } else if (vortex_debug > 0)
2448 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2449 "size %d.\n", dev->name, pkt_len);
35b30674 2450 vp->stats.rx_dropped++;
1da177e4 2451 }
1da177e4
LT		 2452 issue_and_wait(dev, RxDiscard);
2453 }
2454
2455 return 0;
2456}
2457
2458static int
2459boomerang_rx(struct net_device *dev)
2460{
2461 struct vortex_private *vp = netdev_priv(dev);
2462 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2463 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2464 int rx_status;
2465 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2466
2467 if (vortex_debug > 5)
62afe595 2468 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2469
2470 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2471 if (--rx_work_limit < 0)
2472 break;
2473 if (rx_status & RxDError) { /* Error, update stats. */
2474 unsigned char rx_error = rx_status >> 16;
2475 if (vortex_debug > 2)
2476 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2477 vp->stats.rx_errors++;
2478 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2479 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2480 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2481 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2482 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2483 } else {
2484 /* The packet length: up to 4.5K!. */
2485 int pkt_len = rx_status & 0x1fff;
2486 struct sk_buff *skb;
2487 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2488
2489 if (vortex_debug > 4)
2490 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2491 pkt_len, rx_status);
2492
2493 /* Check if the packet is long enough to just accept without
2494 copying to a properly sized skbuff. */
2495 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2496 skb->dev = dev;
2497 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2498 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2499 /* 'skb_put()' points to the start of sk_buff data area. */
2500 memcpy(skb_put(skb, pkt_len),
689be439 2501 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2502 pkt_len);
2503 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2504 vp->rx_copy++;
2505 } else {
2506 /* Pass up the skbuff already on the Rx ring. */
2507 skb = vp->rx_skbuff[entry];
2508 vp->rx_skbuff[entry] = NULL;
2509 skb_put(skb, pkt_len);
2510 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2511 vp->rx_nocopy++;
2512 }
2513 skb->protocol = eth_type_trans(skb, dev);
2514 { /* Use hardware checksum info. */
2515 int csum_bits = rx_status & 0xee000000;
2516 if (csum_bits &&
2517 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2518 csum_bits == (IPChksumValid | UDPChksumValid))) {
2519 skb->ip_summed = CHECKSUM_UNNECESSARY;
2520 vp->rx_csumhits++;
2521 }
2522 }
2523 netif_rx(skb);
2524 dev->last_rx = jiffies;
2525 vp->stats.rx_packets++;
2526 }
2527 entry = (++vp->cur_rx) % RX_RING_SIZE;
2528 }
2529 /* Refill the Rx ring buffers. */
2530 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2531 struct sk_buff *skb;
2532 entry = vp->dirty_rx % RX_RING_SIZE;
2533 if (vp->rx_skbuff[entry] == NULL) {
2534 skb = dev_alloc_skb(PKT_BUF_SZ);
2535 if (skb == NULL) {
2536 static unsigned long last_jif;
ff5688ae 2537 if (time_after(jiffies, last_jif + 10 * HZ)) {
1da177e4
LT		 2538 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2539 last_jif = jiffies;
2540 }
2541 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2542 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2543 break; /* Bad news! */
2544 }
2545 skb->dev = dev; /* Mark as being used by this device. */
2546 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2547 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2548 vp->rx_skbuff[entry] = skb;
2549 }
2550 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2551 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2552 }
2553 return 0;
2554}
2555
2556/*
2557 * If we've hit a total OOM refilling the Rx ring we poll once a second
2558 * for some memory. Otherwise there is no way to restart the rx process.
2559 */
2560static void
2561rx_oom_timer(unsigned long arg)
2562{
2563 struct net_device *dev = (struct net_device *)arg;
2564 struct vortex_private *vp = netdev_priv(dev);
2565
2566 spin_lock_irq(&vp->lock);
2567 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2568 boomerang_rx(dev);
2569 if (vortex_debug > 1) {
2570 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2571 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2572 }
2573 spin_unlock_irq(&vp->lock);
2574}
2575
2576static void
2577vortex_down(struct net_device *dev, int final_down)
2578{
2579 struct vortex_private *vp = netdev_priv(dev);
62afe595 2580 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2581
2582 netif_stop_queue (dev);
2583
2584 del_timer_sync(&vp->rx_oom_timer);
2585 del_timer_sync(&vp->timer);
2586
2587 /* Turn off statistics ASAP. We update vp->stats below. */
62afe595 2588 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2589
2590 /* Disable the receiver and transmitter. */
62afe595
JL		 2591 iowrite16(RxDisable, ioaddr + EL3_CMD);
2592 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2593
2594 /* Disable receiving 802.1q tagged frames */
2595 set_8021q_mode(dev, 0);
2596
2597 if (dev->if_port == XCVR_10base2)
2598 /* Turn off thinnet power. Green! */
62afe595 2599 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2600
62afe595 2601 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2602
2603 update_stats(ioaddr, dev);
2604 if (vp->full_bus_master_rx)
62afe595 2605 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2606 if (vp->full_bus_master_tx)
62afe595 2607 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2608
2609 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2610 vp->pm_state_valid = 1;
1da177e4
LT		 2611 pci_save_state(VORTEX_PCI(vp));
2612 acpi_set_WOL(dev);
2613 }
2614}
2615
2616static int
2617vortex_close(struct net_device *dev)
2618{
2619 struct vortex_private *vp = netdev_priv(dev);
62afe595 2620 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2621 int i;
2622
2623 if (netif_device_present(dev))
2624 vortex_down(dev, 1);
2625
2626 if (vortex_debug > 1) {
2627 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2628 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2629 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2630 " tx_queued %d Rx pre-checksummed %d.\n",
2631 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2632 }
2633
2634#if DO_ZEROCOPY
32fb5f06
JL		 2635 if (vp->rx_csumhits &&
2636 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2637 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2638 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2639 "not using them!\n", dev->name);
1da177e4
LT		 2640 }
2641#endif
6aa20a22 2642
1da177e4
LT		 2643 free_irq(dev->irq, dev);
2644
2645 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2646 for (i = 0; i < RX_RING_SIZE; i++)
2647 if (vp->rx_skbuff[i]) {
2648 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2649 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2650 dev_kfree_skb(vp->rx_skbuff[i]);
2651 vp->rx_skbuff[i] = NULL;
2652 }
2653 }
2654 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2655 for (i = 0; i < TX_RING_SIZE; i++) {
2656 if (vp->tx_skbuff[i]) {
2657 struct sk_buff *skb = vp->tx_skbuff[i];
2658#if DO_ZEROCOPY
2659 int k;
2660
2661 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2662 pci_unmap_single(VORTEX_PCI(vp),
2663 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2664 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2665 PCI_DMA_TODEVICE);
2666#else
2667 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2668#endif
2669 dev_kfree_skb(skb);
2670 vp->tx_skbuff[i] = NULL;
2671 }
2672 }
2673 }
2674
2675 return 0;
2676}
2677
2678static void
2679dump_tx_ring(struct net_device *dev)
2680{
2681 if (vortex_debug > 0) {
2682 struct vortex_private *vp = netdev_priv(dev);
62afe595 2683 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2684
1da177e4
LT		 2685 if (vp->full_bus_master_tx) {
2686 int i;
62afe595 2687 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2688
2689 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2690 vp->full_bus_master_tx,
2691 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2692 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2693 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2694 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2695 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2696 issue_and_wait(dev, DownStall);
2697 for (i = 0; i < TX_RING_SIZE; i++) {
2698 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2699 &vp->tx_ring[i],
2700#if DO_ZEROCOPY
2701 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2702#else
2703 le32_to_cpu(vp->tx_ring[i].length),
2704#endif
2705 le32_to_cpu(vp->tx_ring[i].status));
2706 }
2707 if (!stalled)
62afe595 2708 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2709 }
2710 }
2711}
2712
2713static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2714{
2715 struct vortex_private *vp = netdev_priv(dev);
62afe595 2716 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2717 unsigned long flags;
2718
2719 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2720 spin_lock_irqsave (&vp->lock, flags);
62afe595 2721 update_stats(ioaddr, dev);
1da177e4
LT		 2722 spin_unlock_irqrestore (&vp->lock, flags);
2723 }
2724 return &vp->stats;
2725}
2726
2727/* Update statistics.
2728 Unlike with the EL3 we need not worry about interrupts changing
2729 the window setting from underneath us, but we must still guard
2730 against a race condition with a StatsUpdate interrupt updating the
2731 table. This is done by checking that the ASM (!) code generated uses
2732 atomic updates with '+='.
2733 */
62afe595 2734static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2735{
2736 struct vortex_private *vp = netdev_priv(dev);
62afe595 2737 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2738
2739 if (old_window == 0xffff) /* Chip suspended or ejected. */
2740 return;
2741 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2742 /* Switch to the stats window, and read everything. */
2743 EL3WINDOW(6);
62afe595
JL		 2744 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2745 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
62afe595
JL		 2746 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2747 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2748 vp->stats.tx_packets += ioread8(ioaddr + 6);
2749 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2750 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2751 /* Don't bother with register 9, an extension of registers 6&7.
2752 If we do use the 6&7 values the atomic update assumption above
2753 is invalid. */
62afe595
JL		 2754 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2755 vp->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2756 /* Extra stats for get_ethtool_stats() */
62afe595 2757 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2758 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2759 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2760 EL3WINDOW(4);
62afe595 2761 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2762
8d1d0340
SK		 2763 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2764 + vp->xstats.tx_single_collisions
2765 + vp->xstats.tx_max_collisions;
2766
1da177e4 2767 {
62afe595 2768 u8 up = ioread8(ioaddr + 13);
1da177e4
LT		 2769 vp->stats.rx_bytes += (up & 0x0f) << 16;
2770 vp->stats.tx_bytes += (up & 0xf0) << 12;
2771 }
2772
2773 EL3WINDOW(old_window >> 13);
2774 return;
2775}
2776
2777static int vortex_nway_reset(struct net_device *dev)
2778{
2779 struct vortex_private *vp = netdev_priv(dev);
62afe595 2780 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2781 unsigned long flags;
2782 int rc;
2783
2784 spin_lock_irqsave(&vp->lock, flags);
2785 EL3WINDOW(4);
2786 rc = mii_nway_restart(&vp->mii);
2787 spin_unlock_irqrestore(&vp->lock, flags);
2788 return rc;
2789}
2790
1da177e4
LT		 2791static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2792{
2793 struct vortex_private *vp = netdev_priv(dev);
62afe595 2794 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2795 unsigned long flags;
2796 int rc;
2797
2798 spin_lock_irqsave(&vp->lock, flags);
2799 EL3WINDOW(4);
2800 rc = mii_ethtool_gset(&vp->mii, cmd);
2801 spin_unlock_irqrestore(&vp->lock, flags);
2802 return rc;
2803}
2804
2805static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2806{
2807 struct vortex_private *vp = netdev_priv(dev);
62afe595 2808 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2809 unsigned long flags;
2810 int rc;
2811
2812 spin_lock_irqsave(&vp->lock, flags);
2813 EL3WINDOW(4);
2814 rc = mii_ethtool_sset(&vp->mii, cmd);
2815 spin_unlock_irqrestore(&vp->lock, flags);
2816 return rc;
2817}
2818
2819static u32 vortex_get_msglevel(struct net_device *dev)
2820{
2821 return vortex_debug;
2822}
2823
2824static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2825{
2826 vortex_debug = dbg;
2827}
2828
2829static int vortex_get_stats_count(struct net_device *dev)
2830{
2831 return VORTEX_NUM_STATS;
2832}
2833
2834static void vortex_get_ethtool_stats(struct net_device *dev,
2835 struct ethtool_stats *stats, u64 *data)
2836{
2837 struct vortex_private *vp = netdev_priv(dev);
62afe595 2838 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2839 unsigned long flags;
2840
2841 spin_lock_irqsave(&vp->lock, flags);
62afe595 2842 update_stats(ioaddr, dev);
1da177e4
LT		 2843 spin_unlock_irqrestore(&vp->lock, flags);
2844
2845 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2846 data[1] = vp->xstats.tx_max_collisions;
2847 data[2] = vp->xstats.tx_multiple_collisions;
2848 data[3] = vp->xstats.tx_single_collisions;
2849 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2850}
2851
2852
2853static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2854{
2855 switch (stringset) {
2856 case ETH_SS_STATS:
2857 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2858 break;
2859 default:
2860 WARN_ON(1);
2861 break;
2862 }
2863}
2864
2865static void vortex_get_drvinfo(struct net_device *dev,
2866 struct ethtool_drvinfo *info)
2867{
2868 struct vortex_private *vp = netdev_priv(dev);
2869
2870 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2871 if (VORTEX_PCI(vp)) {
2872 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2873 } else {
2874 if (VORTEX_EISA(vp))
2875 sprintf(info->bus_info, vp->gendev->bus_id);
2876 else
2877 sprintf(info->bus_info, "EISA 0x%lx %d",
2878 dev->base_addr, dev->irq);
2879 }
2880}
2881
7282d491 2882static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2883 .get_drvinfo = vortex_get_drvinfo,
2884 .get_strings = vortex_get_strings,
2885 .get_msglevel = vortex_get_msglevel,
2886 .set_msglevel = vortex_set_msglevel,
2887 .get_ethtool_stats = vortex_get_ethtool_stats,
2888 .get_stats_count = vortex_get_stats_count,
2889 .get_settings = vortex_get_settings,
2890 .set_settings = vortex_set_settings,
373a6887 2891 .get_link = ethtool_op_get_link,
1da177e4 2892 .nway_reset = vortex_nway_reset,
a880c4cd 2893 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 2894};
2895
2896#ifdef CONFIG_PCI
2897/*
2898 * Must power the device up to do MDIO operations
2899 */
2900static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2901{
2902 int err;
2903 struct vortex_private *vp = netdev_priv(dev);
62afe595 2904 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2905 unsigned long flags;
2906 int state = 0;
2907
2908 if(VORTEX_PCI(vp))
2909 state = VORTEX_PCI(vp)->current_state;
2910
2911 /* The kernel core really should have pci_get_power_state() */
2912
2913 if(state != 0)
2914 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2915 spin_lock_irqsave(&vp->lock, flags);
2916 EL3WINDOW(4);
2917 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2918 spin_unlock_irqrestore(&vp->lock, flags);
2919 if(state != 0)
2920 pci_set_power_state(VORTEX_PCI(vp), state);
2921
2922 return err;
2923}
2924#endif
2925
2926
2927/* Pre-Cyclone chips have no documented multicast filter, so the only
2928 multicast setting is to receive all multicast frames. At least
2929 the chip has a very clean way to set the mode, unlike many others. */
2930static void set_rx_mode(struct net_device *dev)
2931{
62afe595
JL		 2932 struct vortex_private *vp = netdev_priv(dev);
2933 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2934 int new_mode;
2935
2936 if (dev->flags & IFF_PROMISC) {
d5b20697 2937 if (vortex_debug > 3)
1da177e4
LT		 2938 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2939 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2940 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2941 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2942 } else
2943 new_mode = SetRxFilter | RxStation | RxBroadcast;
2944
62afe595 2945 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2946}
2947
2948#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2949/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2950 Note that this must be done after each RxReset due to some backwards
2951 compatibility logic in the Cyclone and Tornado ASICs */
2952
2953/* The Ethernet Type used for 802.1q tagged frames */
2954#define VLAN_ETHER_TYPE 0x8100
2955
2956static void set_8021q_mode(struct net_device *dev, int enable)
2957{
2958 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 2959 void __iomem *ioaddr = vp->ioaddr;
2960 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2961 int mac_ctrl;
2962
2963 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2964 /* cyclone and tornado chipsets can recognize 802.1q
2965 * tagged frames and treat them correctly */
2966
2967 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2968 if (enable)
2969 max_pkt_size += 4; /* 802.1Q VLAN tag */
2970
2971 EL3WINDOW(3);
62afe595 2972 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 2973
2974 /* set VlanEtherType to let the hardware checksumming
2975 treat tagged frames correctly */
2976 EL3WINDOW(7);
62afe595 2977 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 2978 } else {
2979 /* on older cards we have to enable large frames */
2980
2981 vp->large_frames = dev->mtu > 1500 || enable;
2982
2983 EL3WINDOW(3);
62afe595 2984 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2985 if (vp->large_frames)
2986 mac_ctrl |= 0x40;
2987 else
2988 mac_ctrl &= ~0x40;
62afe595 2989 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2990 }
2991
2992 EL3WINDOW(old_window);
2993}
2994#else
2995
2996static void set_8021q_mode(struct net_device *dev, int enable)
2997{
2998}
2999
3000
3001#endif
3002
3003/* MII transceiver control section.
3004 Read and write the MII registers using software-generated serial
3005 MDIO protocol. See the MII specifications or DP83840A data sheet
3006 for details. */
3007
3008/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3009 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3010 "overclocking" issues. */
62afe595 3011#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3012
3013#define MDIO_SHIFT_CLK 0x01
3014#define MDIO_DIR_WRITE 0x04
3015#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3016#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3017#define MDIO_DATA_READ 0x02
3018#define MDIO_ENB_IN 0x00
3019
3020/* Generate the preamble required for initial synchronization and
3021 a few older transceivers. */
62afe595 3022static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3023{
62afe595 3024 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3025
3026 /* Establish sync by sending at least 32 logic ones. */
3027 while (-- bits >= 0) {
62afe595 3028 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3029 mdio_delay();
62afe595 3030 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3031 mdio_delay();
3032 }
3033}
3034
3035static int mdio_read(struct net_device *dev, int phy_id, int location)
3036{
3037 int i;
62afe595
JL		 3038 struct vortex_private *vp = netdev_priv(dev);
3039 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3040 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3041 unsigned int retval = 0;
62afe595 3042 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3043
3044 if (mii_preamble_required)
3045 mdio_sync(ioaddr, 32);
3046
3047 /* Shift the read command bits out. */
3048 for (i = 14; i >= 0; i--) {
3049 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3050 iowrite16(dataval, mdio_addr);
1da177e4 3051 mdio_delay();
62afe595 3052 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3053 mdio_delay();
3054 }
3055 /* Read the two transition, 16 data, and wire-idle bits. */
3056 for (i = 19; i > 0; i--) {
62afe595 3057 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3058 mdio_delay();
62afe595
JL		 3059 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3060 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3061 mdio_delay();
3062 }
3063 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3064}
3065
3066static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3067{
62afe595
JL		 3068 struct vortex_private *vp = netdev_priv(dev);
3069 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3070 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3071 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3072 int i;
3073
3074 if (mii_preamble_required)
3075 mdio_sync(ioaddr, 32);
3076
3077 /* Shift the command bits out. */
3078 for (i = 31; i >= 0; i--) {
3079 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3080 iowrite16(dataval, mdio_addr);
1da177e4 3081 mdio_delay();
62afe595 3082 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3083 mdio_delay();
3084 }
3085 /* Leave the interface idle. */
3086 for (i = 1; i >= 0; i--) {
62afe595 3087 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3088 mdio_delay();
62afe595 3089 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3090 mdio_delay();
3091 }
3092 return;
3093}
a880c4cd 3094
1da177e4
LT		 3095/* ACPI: Advanced Configuration and Power Interface. */
3096/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3097static void acpi_set_WOL(struct net_device *dev)
3098{
3099 struct vortex_private *vp = netdev_priv(dev);
62afe595 3100 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3101
3102 if (vp->enable_wol) {
3103 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3104 EL3WINDOW(7);
62afe595 3105 iowrite16(2, ioaddr + 0x0c);
1da177e4 3106 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3107 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3108 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 3109
3110 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3c8fad18
DR		 3111
3112 /* Change the power state to D3; RxEnable doesn't take effect. */
3113 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3114 }
1da177e4
LT		 3115}
3116
3117
a880c4cd 3118static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3119{
3120 struct net_device *dev = pci_get_drvdata(pdev);
3121 struct vortex_private *vp;
3122
3123 if (!dev) {
3124 printk("vortex_remove_one called for Compaq device!\n");
3125 BUG();
3126 }
3127
3128 vp = netdev_priv(dev);
3129
62afe595
JL		 3130 if (vp->cb_fn_base)
3131 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3132
1da177e4
LT		 3133 unregister_netdev(dev);
3134
3135 if (VORTEX_PCI(vp)) {
3136 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3137 if (vp->pm_state_valid)
3138 pci_restore_state(VORTEX_PCI(vp));
3139 pci_disable_device(VORTEX_PCI(vp));
3140 }
3141 /* Should really use issue_and_wait() here */
62afe595
JL		 3142 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3143 vp->ioaddr + EL3_CMD);
3144
3145 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3146
3147 pci_free_consistent(pdev,
3148 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3149 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3150 vp->rx_ring,
3151 vp->rx_ring_dma);
3152 if (vp->must_free_region)
3153 release_region(dev->base_addr, vp->io_size);
3154 free_netdev(dev);
3155}
3156
3157
3158static struct pci_driver vortex_driver = {
3159 .name = "3c59x",
3160 .probe = vortex_init_one,
3161 .remove = __devexit_p(vortex_remove_one),
3162 .id_table = vortex_pci_tbl,
3163#ifdef CONFIG_PM
3164 .suspend = vortex_suspend,
3165 .resume = vortex_resume,
3166#endif
3167};
3168
3169
3170static int vortex_have_pci;
3171static int vortex_have_eisa;
3172
3173
a880c4cd 3174static int __init vortex_init(void)
1da177e4
LT		 3175{
3176 int pci_rc, eisa_rc;
3177
29917620 3178 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3179 eisa_rc = vortex_eisa_init();
3180
3181 if (pci_rc == 0)
3182 vortex_have_pci = 1;
3183 if (eisa_rc > 0)
3184 vortex_have_eisa = 1;
3185
3186 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3187}
3188
3189
a880c4cd 3190static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3191{
3192 struct vortex_private *vp;
62afe595 3193 void __iomem *ioaddr;
1da177e4
LT		 3194
3195#ifdef CONFIG_EISA
3196 /* Take care of the EISA devices */
a880c4cd 3197 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3198#endif
6aa20a22 3199
1da177e4
LT		 3200 if (compaq_net_device) {
3201 vp = compaq_net_device->priv;
62afe595
JL		 3202 ioaddr = ioport_map(compaq_net_device->base_addr,
3203 VORTEX_TOTAL_SIZE);
1da177e4 3204
a880c4cd
SK		 3205 unregister_netdev(compaq_net_device);
3206 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3207 release_region(compaq_net_device->base_addr,
3208 VORTEX_TOTAL_SIZE);
1da177e4 3209
a880c4cd 3210 free_netdev(compaq_net_device);
1da177e4
LT		 3211 }
3212}
3213
3214
a880c4cd 3215static void __exit vortex_cleanup(void)
1da177e4
LT		 3216{
3217 if (vortex_have_pci)
a880c4cd 3218 pci_unregister_driver(&vortex_driver);
1da177e4 3219 if (vortex_have_eisa)
a880c4cd 3220 vortex_eisa_cleanup();
1da177e4
LT		 3221}
3222
3223
3224module_init(vortex_init);
3225module_exit(vortex_cleanup);
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