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[net-next-2.6.git] / drivers / net / 3c59x.c
CommitLineData
1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/slab.h>
81#include <linux/interrupt.h>
82#include <linux/pci.h>
83#include <linux/mii.h>
84#include <linux/init.h>
85#include <linux/netdevice.h>
86#include <linux/etherdevice.h>
87#include <linux/skbuff.h>
88#include <linux/ethtool.h>
89#include <linux/highmem.h>
90#include <linux/eisa.h>
91#include <linux/bitops.h>
ff5688ae 92#include <linux/jiffies.h>
1da177e4
LT		 93#include <asm/irq.h> /* For NR_IRQS only. */
94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static char version[] __devinitdata =
2c2a8c53 106DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_1,
239
240 CH_3C905B_2,
241 CH_3C905B_FX,
242 CH_3C905C,
243 CH_3C9202,
244 CH_3C980,
245 CH_3C9805,
246
247 CH_3CSOHO100_TX,
248 CH_3C555,
249 CH_3C556,
250 CH_3C556B,
251 CH_3C575,
252
253 CH_3C575_1,
254 CH_3CCFE575,
255 CH_3CCFE575CT,
256 CH_3CCFE656,
257 CH_3CCFEM656,
258
259 CH_3CCFEM656_1,
260 CH_3C450,
261 CH_3C920,
262 CH_3C982A,
263 CH_3C982B,
264
265 CH_905BT4,
266 CH_920B_EMB_WNM,
267};
268
269
270/* note: this array directly indexed by above enums, and MUST
271 * be kept in sync with both the enums above, and the PCI device
272 * table below
273 */
274static struct vortex_chip_info {
275 const char *name;
276 int flags;
277 int drv_flags;
278 int io_size;
279} vortex_info_tbl[] __devinitdata = {
280 {"3c590 Vortex 10Mbps",
1f1bd5fc 281 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 282 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 283 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 284 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 285 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 286 {"3c595 Vortex 100baseTx",
1f1bd5fc 287 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 288 {"3c595 Vortex 100baseT4",
1f1bd5fc 289 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 290
291 {"3c595 Vortex 100base-MII",
1f1bd5fc 292 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 293 {"3c900 Boomerang 10baseT",
1f1bd5fc 294 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 295 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 296 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 297 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 298 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 299 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 300 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 301
302 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 303 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 304 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 305 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 306 {"3c905 Boomerang 100baseTx",
1f1bd5fc 307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 308 {"3c905 Boomerang 100baseT4",
1f1bd5fc 309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 310 {"3c905B Cyclone 100baseTx",
1f1bd5fc 311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 312
313 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 315 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 316 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 317 {"3c905C Tornado",
1f1bd5fc 318 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 319 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 320 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 321 {"3c980 Cyclone",
1f1bd5fc 322 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 323
324 {"3c980C Python-T",
1f1bd5fc 325 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 326 {"3cSOHO100-TX Hurricane",
1f1bd5fc 327 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 328 {"3c555 Laptop Hurricane",
1f1bd5fc 329 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 330 {"3c556 Laptop Tornado",
1f1bd5fc 331 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 332 HAS_HWCKSM, 128, },
333 {"3c556B Laptop Hurricane",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
336
337 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 338 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 339 {"3c575 Boomerang CardBus",
1f1bd5fc 340 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 341 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 342 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 343 INVERT_LED_PWR|HAS_HWCKSM, 128, },
344 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 346 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
347 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 INVERT_LED_PWR|HAS_HWCKSM, 128, },
350
351 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 352 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 353 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 355 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
357 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 359 {"3c920 Tornado",
1f1bd5fc 360 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 361 {"3c982 Hydra Dual Port A",
1f1bd5fc 362 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 363
364 {"3c982 Hydra Dual Port B",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 366 {"3c905B-T4",
1f1bd5fc 367 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 368 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 369 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 370
371 {NULL,}, /* NULL terminated list. */
372};
373
374
375static struct pci_device_id vortex_pci_tbl[] = {
376 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
377 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
378 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
379 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
380 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
381
382 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
383 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
384 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
385 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
386 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
387
388 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
393
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
395 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
396 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
397 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
398 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
399 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
400
401 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
402 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
403 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
404 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
405 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
406
407 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
408 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
409 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
410 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
411 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
412
413 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
414 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
415 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
416 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
417 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
418
419 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
420 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
421
422 {0,} /* 0 terminated list. */
423};
424MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
425
426
427/* Operational definitions.
428 These are not used by other compilation units and thus are not
429 exported in a ".h" file.
430
431 First the windows. There are eight register windows, with the command
432 and status registers available in each.
433 */
62afe595 434#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 435#define EL3_CMD 0x0e
436#define EL3_STATUS 0x0e
437
438/* The top five bits written to EL3_CMD are a command, the lower
439 11 bits are the parameter, if applicable.
440 Note that 11 parameters bits was fine for ethernet, but the new chip
441 can handle FDDI length frames (~4500 octets) and now parameters count
442 32-bit 'Dwords' rather than octets. */
443
444enum vortex_cmd {
445 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
446 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
447 UpStall = 6<<11, UpUnstall = (6<<11)+1,
448 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
449 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
450 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
451 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
452 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
453 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
454 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
455
456/* The SetRxFilter command accepts the following classes: */
457enum RxFilter {
458 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
459
460/* Bits in the general status register. */
461enum vortex_status {
462 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
463 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
464 IntReq = 0x0040, StatsFull = 0x0080,
465 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
466 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
467 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
468};
469
470/* Register window 1 offsets, the window used in normal operation.
471 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
472enum Window1 {
473 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
474 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
475 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
476};
477enum Window0 {
478 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
479 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
480 IntrStatus=0x0E, /* Valid in all windows. */
481};
482enum Win0_EEPROM_bits {
483 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
484 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
485 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
486};
487/* EEPROM locations. */
488enum eeprom_offset {
489 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
490 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
491 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
492 DriverTune=13, Checksum=15};
493
494enum Window2 { /* Window 2. */
495 Wn2_ResetOptions=12,
496};
497enum Window3 { /* Window 3: MAC/config bits. */
498 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
499};
500
501#define BFEXT(value, offset, bitcount) \
502 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
503
504#define BFINS(lhs, rhs, offset, bitcount) \
505 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
506 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
507
508#define RAM_SIZE(v) BFEXT(v, 0, 3)
509#define RAM_WIDTH(v) BFEXT(v, 3, 1)
510#define RAM_SPEED(v) BFEXT(v, 4, 2)
511#define ROM_SIZE(v) BFEXT(v, 6, 2)
512#define RAM_SPLIT(v) BFEXT(v, 16, 2)
513#define XCVR(v) BFEXT(v, 20, 4)
514#define AUTOSELECT(v) BFEXT(v, 24, 1)
515
516enum Window4 { /* Window 4: Xcvr/media bits. */
517 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
518};
519enum Win4_Media_bits {
520 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
521 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
522 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
523 Media_LnkBeat = 0x0800,
524};
525enum Window7 { /* Window 7: Bus Master control. */
526 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
527 Wn7_MasterStatus = 12,
528};
529/* Boomerang bus master control registers. */
530enum MasterCtrl {
531 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
532 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
533};
534
535/* The Rx and Tx descriptor lists.
536 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
537 alignment contraint on tx_ring[] and rx_ring[]. */
538#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
539#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
540struct boom_rx_desc {
541 u32 next; /* Last entry points to 0. */
542 s32 status;
543 u32 addr; /* Up to 63 addr/len pairs possible. */
544 s32 length; /* Set LAST_FRAG to indicate last pair. */
545};
546/* Values for the Rx status entry. */
547enum rx_desc_status {
548 RxDComplete=0x00008000, RxDError=0x4000,
549 /* See boomerang_rx() for actual error bits */
550 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
551 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
552};
553
554#ifdef MAX_SKB_FRAGS
555#define DO_ZEROCOPY 1
556#else
557#define DO_ZEROCOPY 0
558#endif
559
560struct boom_tx_desc {
561 u32 next; /* Last entry points to 0. */
562 s32 status; /* bits 0:12 length, others see below. */
563#if DO_ZEROCOPY
564 struct {
565 u32 addr;
566 s32 length;
567 } frag[1+MAX_SKB_FRAGS];
568#else
569 u32 addr;
570 s32 length;
571#endif
572};
573
574/* Values for the Tx status entry. */
575enum tx_desc_status {
576 CRCDisable=0x2000, TxDComplete=0x8000,
577 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
578 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
579};
580
581/* Chip features we care about in vp->capabilities, read from the EEPROM. */
582enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
583
584struct vortex_extra_stats {
8d1d0340
SK		 585 unsigned long tx_deferred;
586 unsigned long tx_max_collisions;
587 unsigned long tx_multiple_collisions;
588 unsigned long tx_single_collisions;
589 unsigned long rx_bad_ssd;
1da177e4
LT		 590};
591
592struct vortex_private {
593 /* The Rx and Tx rings should be quad-word-aligned. */
594 struct boom_rx_desc* rx_ring;
595 struct boom_tx_desc* tx_ring;
596 dma_addr_t rx_ring_dma;
597 dma_addr_t tx_ring_dma;
598 /* The addresses of transmit- and receive-in-place skbuffs. */
599 struct sk_buff* rx_skbuff[RX_RING_SIZE];
600 struct sk_buff* tx_skbuff[TX_RING_SIZE];
601 unsigned int cur_rx, cur_tx; /* The next free ring entry */
602 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
603 struct net_device_stats stats; /* Generic stats */
604 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
605 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
606 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
607
608 /* PCI configuration space information. */
609 struct device *gendev;
62afe595
JL		 610 void __iomem *ioaddr; /* IO address space */
611 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 612
613 /* Some values here only for performance evaluation and path-coverage */
614 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
615 int card_idx;
616
617 /* The remainder are related to chip state, mostly media selection. */
618 struct timer_list timer; /* Media selection timer. */
619 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
620 int options; /* User-settable misc. driver options. */
621 unsigned int media_override:4, /* Passed-in media type. */
622 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 623 full_duplex:1, autoselect:1,
1da177e4
LT		 624 bus_master:1, /* Vortex can only do a fragment bus-m. */
625 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
626 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
627 partner_flow_ctrl:1, /* Partner supports flow control */
628 has_nway:1,
629 enable_wol:1, /* Wake-on-LAN is enabled */
630 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
631 open:1,
632 medialock:1,
633 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
634 large_frames:1; /* accept large frames */
635 int drv_flags;
636 u16 status_enable;
637 u16 intr_enable;
638 u16 available_media; /* From Wn3_Options. */
639 u16 capabilities, info1, info2; /* Various, from EEPROM. */
640 u16 advertising; /* NWay media advertisement */
641 unsigned char phys[2]; /* MII device addresses. */
642 u16 deferred; /* Resend these interrupts when we
643 * bale from the ISR */
644 u16 io_size; /* Size of PCI region (for release_region) */
645 spinlock_t lock; /* Serialise access to device & its vortex_private */
646 struct mii_if_info mii; /* MII lib hooks/info */
647};
648
649#ifdef CONFIG_PCI
650#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
651#else
652#define DEVICE_PCI(dev) NULL
653#endif
654
655#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
656
657#ifdef CONFIG_EISA
658#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
659#else
660#define DEVICE_EISA(dev) NULL
661#endif
662
663#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
664
665/* The action to take with a media selection timer tick.
666 Note that we deviate from the 3Com order by checking 10base2 before AUI.
667 */
668enum xcvr_types {
669 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
670 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
671};
672
f71e1309 673static const struct media_table {
1da177e4
LT		 674 char *name;
675 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
676 mask:8, /* The transceiver-present bit in Wn3_Config.*/
677 next:8; /* The media type to try next. */
678 int wait; /* Time before we check media status. */
679} media_tbl[] = {
680 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
681 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
682 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
683 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
684 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
685 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
686 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
687 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
688 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
689 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
691};
692
693static struct {
694 const char str[ETH_GSTRING_LEN];
695} ethtool_stats_keys[] = {
696 { "tx_deferred" },
8d1d0340 697 { "tx_max_collisions" },
1da177e4 698 { "tx_multiple_collisions" },
8d1d0340 699 { "tx_single_collisions" },
1da177e4
LT		 700 { "rx_bad_ssd" },
701};
702
703/* number of ETHTOOL_GSTATS u64's */
8d1d0340 704#define VORTEX_NUM_STATS 5
1da177e4 705
62afe595 706static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4
LT		 707 int chip_idx, int card_idx);
708static void vortex_up(struct net_device *dev);
709static void vortex_down(struct net_device *dev, int final);
710static int vortex_open(struct net_device *dev);
62afe595 711static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 712static int mdio_read(struct net_device *dev, int phy_id, int location);
713static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
714static void vortex_timer(unsigned long arg);
715static void rx_oom_timer(unsigned long arg);
716static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
717static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
718static int vortex_rx(struct net_device *dev);
719static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 720static irqreturn_t vortex_interrupt(int irq, void *dev_id);
721static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 722static int vortex_close(struct net_device *dev);
723static void dump_tx_ring(struct net_device *dev);
62afe595 724static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 725static struct net_device_stats *vortex_get_stats(struct net_device *dev);
726static void set_rx_mode(struct net_device *dev);
727#ifdef CONFIG_PCI
728static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
729#endif
730static void vortex_tx_timeout(struct net_device *dev);
731static void acpi_set_WOL(struct net_device *dev);
7282d491 732static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 733static void set_8021q_mode(struct net_device *dev, int enable);
734
1da177e4
LT		 735/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
736/* Option count limit only -- unlimited interfaces are supported. */
737#define MAX_UNITS 8
9954ab7f
JL		 738static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
739static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
740static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
741static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
742static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 743static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 744static int global_options = -1;
745static int global_full_duplex = -1;
746static int global_enable_wol = -1;
900fd17d 747static int global_use_mmio = -1;
1da177e4 748
1da177e4
LT		 749/* Variables to work-around the Compaq PCI BIOS32 problem. */
750static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
751static struct net_device *compaq_net_device;
752
753static int vortex_cards_found;
754
755module_param(debug, int, 0);
756module_param(global_options, int, 0);
757module_param_array(options, int, NULL, 0);
758module_param(global_full_duplex, int, 0);
759module_param_array(full_duplex, int, NULL, 0);
760module_param_array(hw_checksums, int, NULL, 0);
761module_param_array(flow_ctrl, int, NULL, 0);
762module_param(global_enable_wol, int, 0);
763module_param_array(enable_wol, int, NULL, 0);
764module_param(rx_copybreak, int, 0);
765module_param(max_interrupt_work, int, 0);
766module_param(compaq_ioaddr, int, 0);
767module_param(compaq_irq, int, 0);
768module_param(compaq_device_id, int, 0);
769module_param(watchdog, int, 0);
900fd17d
JL		 770module_param(global_use_mmio, int, 0);
771module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 772MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
773MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
774MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
775MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 776MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 777MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
778MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
779MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 780MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 781MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
782MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
783MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
784MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
785MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
786MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 787MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
788MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 789
790#ifdef CONFIG_NET_POLL_CONTROLLER
791static void poll_vortex(struct net_device *dev)
792{
793 struct vortex_private *vp = netdev_priv(dev);
794 unsigned long flags;
0d38ff1d 795 local_irq_save(flags);
7d12e780 796 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 797 local_irq_restore(flags);
6aa20a22 798}
1da177e4
LT		 799#endif
800
801#ifdef CONFIG_PM
802
a880c4cd 803static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 804{
805 struct net_device *dev = pci_get_drvdata(pdev);
806
807 if (dev && dev->priv) {
808 if (netif_running(dev)) {
809 netif_device_detach(dev);
810 vortex_down(dev, 1);
811 }
5b039e68
RW		 812 pci_save_state(pdev);
813 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
814 free_irq(dev->irq, dev);
815 pci_disable_device(pdev);
816 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 817 }
818 return 0;
819}
820
a880c4cd 821static int vortex_resume(struct pci_dev *pdev)
1da177e4
LT		 822{
823 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 824 struct vortex_private *vp = netdev_priv(dev);
e1265153 825 int err;
1da177e4 826
5b039e68
RW		 827 if (dev && vp) {
828 pci_set_power_state(pdev, PCI_D0);
829 pci_restore_state(pdev);
e1265153
DM		 830 err = pci_enable_device(pdev);
831 if (err) {
832 printk(KERN_WARNING "%s: Could not enable device \n",
833 dev->name);
834 return err;
835 }
5b039e68
RW		 836 pci_set_master(pdev);
837 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 838 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
5b039e68
RW		 839 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
840 pci_disable_device(pdev);
841 return -EBUSY;
842 }
1da177e4
LT		 843 if (netif_running(dev)) {
844 vortex_up(dev);
845 netif_device_attach(dev);
846 }
847 }
848 return 0;
849}
850
851#endif /* CONFIG_PM */
852
853#ifdef CONFIG_EISA
854static struct eisa_device_id vortex_eisa_ids[] = {
855 { "TCM5920", CH_3C592 },
856 { "TCM5970", CH_3C597 },
857 { "" }
858};
07563c71 859MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 860
95c408a9 861static int __init vortex_eisa_probe(struct device *device)
1da177e4 862{
62afe595 863 void __iomem *ioaddr;
1da177e4
LT		 864 struct eisa_device *edev;
865
a880c4cd 866 edev = to_eisa_device(device);
1da177e4 867
62afe595 868 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 869 return -EBUSY;
870
62afe595
JL		 871 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
872
873 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 874 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 875 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 876 return -ENODEV;
877 }
878
879 vortex_cards_found++;
880
881 return 0;
882}
883
95c408a9 884static int __devexit vortex_eisa_remove(struct device *device)
1da177e4
LT		 885{
886 struct eisa_device *edev;
887 struct net_device *dev;
888 struct vortex_private *vp;
62afe595 889 void __iomem *ioaddr;
1da177e4 890
a880c4cd
SK		 891 edev = to_eisa_device(device);
892 dev = eisa_get_drvdata(edev);
1da177e4
LT		 893
894 if (!dev) {
895 printk("vortex_eisa_remove called for Compaq device!\n");
896 BUG();
897 }
898
899 vp = netdev_priv(dev);
62afe595 900 ioaddr = vp->ioaddr;
6aa20a22 901
a880c4cd
SK		 902 unregister_netdev(dev);
903 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
904 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 905
a880c4cd 906 free_netdev(dev);
1da177e4
LT		 907 return 0;
908}
95c408a9
RB		 909
910static struct eisa_driver vortex_eisa_driver = {
911 .id_table = vortex_eisa_ids,
912 .driver = {
913 .name = "3c59x",
914 .probe = vortex_eisa_probe,
915 .remove = __devexit_p(vortex_eisa_remove)
916 }
917};
918
919#endif /* CONFIG_EISA */
1da177e4
LT		 920
921/* returns count found (>= 0), or negative on error */
a880c4cd 922static int __init vortex_eisa_init(void)
1da177e4
LT		 923{
924 int eisa_found = 0;
925 int orig_cards_found = vortex_cards_found;
926
927#ifdef CONFIG_EISA
c2f6fabb
BH		 928 int err;
929
930 err = eisa_driver_register (&vortex_eisa_driver);
931 if (!err) {
932 /*
933 * Because of the way EISA bus is probed, we cannot assume
934 * any device have been found when we exit from
935 * eisa_driver_register (the bus root driver may not be
936 * initialized yet). So we blindly assume something was
937 * found, and let the sysfs magic happend...
938 */
939 eisa_found = 1;
1da177e4
LT		 940 }
941#endif
6aa20a22 942
1da177e4
LT		 943 /* Special code to work-around the Compaq PCI BIOS32 problem. */
944 if (compaq_ioaddr) {
62afe595
JL		 945 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
946 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 947 }
948
949 return vortex_cards_found - orig_cards_found + eisa_found;
950}
951
952/* returns count (>= 0), or negative on error */
a880c4cd 953static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 954 const struct pci_device_id *ent)
955{
900fd17d
JL		 956 int rc, unit, pci_bar;
957 struct vortex_chip_info *vci;
958 void __iomem *ioaddr;
1da177e4 959
6aa20a22 960 /* wake up and enable device */
a880c4cd 961 rc = pci_enable_device(pdev);
1da177e4
LT		 962 if (rc < 0)
963 goto out;
964
900fd17d
JL		 965 unit = vortex_cards_found;
966
967 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
968 /* Determine the default if the user didn't override us */
969 vci = &vortex_info_tbl[ent->driver_data];
970 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
971 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
972 pci_bar = use_mmio[unit] ? 1 : 0;
973 else
974 pci_bar = global_use_mmio ? 1 : 0;
975
976 ioaddr = pci_iomap(pdev, pci_bar, 0);
977 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
978 ioaddr = pci_iomap(pdev, 0, 0);
979
980 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
981 ent->driver_data, unit);
1da177e4 982 if (rc < 0) {
a880c4cd 983 pci_disable_device(pdev);
1da177e4
LT		 984 goto out;
985 }
986
987 vortex_cards_found++;
988
989out:
990 return rc;
991}
992
993/*
994 * Start up the PCI/EISA device which is described by *gendev.
995 * Return 0 on success.
996 *
997 * NOTE: pdev can be NULL, for the case of a Compaq device
998 */
999static int __devinit vortex_probe1(struct device *gendev,
62afe595 1000 void __iomem *ioaddr, int irq,
1da177e4
LT		 1001 int chip_idx, int card_idx)
1002{
1003 struct vortex_private *vp;
1004 int option;
1005 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1006 int i, step;
1007 struct net_device *dev;
1008 static int printed_version;
1009 int retval, print_info;
1010 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1011 char *print_name = "3c59x";
1012 struct pci_dev *pdev = NULL;
1013 struct eisa_device *edev = NULL;
1014
1015 if (!printed_version) {
1016 printk (version);
1017 printed_version = 1;
1018 }
1019
1020 if (gendev) {
1021 if ((pdev = DEVICE_PCI(gendev))) {
1022 print_name = pci_name(pdev);
1023 }
1024
1025 if ((edev = DEVICE_EISA(gendev))) {
1026 print_name = edev->dev.bus_id;
1027 }
1028 }
1029
1030 dev = alloc_etherdev(sizeof(*vp));
1031 retval = -ENOMEM;
1032 if (!dev) {
1033 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1034 goto out;
1035 }
1036 SET_MODULE_OWNER(dev);
1037 SET_NETDEV_DEV(dev, gendev);
1038 vp = netdev_priv(dev);
1039
1040 option = global_options;
1041
1042 /* The lower four bits are the media type. */
1043 if (dev->mem_start) {
1044 /*
1045 * The 'options' param is passed in as the third arg to the
1046 * LILO 'ether=' argument for non-modular use
1047 */
1048 option = dev->mem_start;
1049 }
1050 else if (card_idx < MAX_UNITS) {
1051 if (options[card_idx] >= 0)
1052 option = options[card_idx];
1053 }
1054
1055 if (option > 0) {
1056 if (option & 0x8000)
1057 vortex_debug = 7;
1058 if (option & 0x4000)
1059 vortex_debug = 2;
1060 if (option & 0x0400)
1061 vp->enable_wol = 1;
1062 }
1063
1064 print_info = (vortex_debug > 1);
1065 if (print_info)
1066 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1067
61238602 1068 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1069 print_name,
1070 pdev ? "PCI" : "EISA",
1071 vci->name,
1072 ioaddr);
1073
62afe595 1074 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1075 dev->irq = irq;
1076 dev->mtu = mtu;
62afe595 1077 vp->ioaddr = ioaddr;
1da177e4
LT		 1078 vp->large_frames = mtu > 1500;
1079 vp->drv_flags = vci->drv_flags;
1080 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1081 vp->io_size = vci->io_size;
1082 vp->card_idx = card_idx;
1083
1084 /* module list only for Compaq device */
1085 if (gendev == NULL) {
1086 compaq_net_device = dev;
1087 }
1088
1089 /* PCI-only startup logic */
1090 if (pdev) {
1091 /* EISA resources already marked, so only PCI needs to do this here */
1092 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1093 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1094 vp->must_free_region = 1;
1095
6aa20a22 1096 /* enable bus-mastering if necessary */
1da177e4 1097 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1098 pci_set_master(pdev);
1da177e4
LT		 1099
1100 if (vci->drv_flags & IS_VORTEX) {
1101 u8 pci_latency;
1102 u8 new_latency = 248;
1103
1104 /* Check the PCI latency value. On the 3c590 series the latency timer
1105 must be set to the maximum value to avoid data corruption that occurs
1106 when the timer expires during a transfer. This bug exists the Vortex
1107 chip only. */
1108 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1109 if (pci_latency < new_latency) {
1110 printk(KERN_INFO "%s: Overriding PCI latency"
1111 " timer (CFLT) setting of %d, new value is %d.\n",
1112 print_name, pci_latency, new_latency);
1113 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1114 }
1115 }
1116 }
1117
1118 spin_lock_init(&vp->lock);
1119 vp->gendev = gendev;
1120 vp->mii.dev = dev;
1121 vp->mii.mdio_read = mdio_read;
1122 vp->mii.mdio_write = mdio_write;
1123 vp->mii.phy_id_mask = 0x1f;
1124 vp->mii.reg_num_mask = 0x1f;
1125
1126 /* Makes sure rings are at least 16 byte aligned. */
1127 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1128 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1129 &vp->rx_ring_dma);
1130 retval = -ENOMEM;
1131 if (vp->rx_ring == 0)
1132 goto free_region;
1133
1134 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1135 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1136
1137 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1138 * instead of a module list */
1da177e4
LT		 1139 if (pdev)
1140 pci_set_drvdata(pdev, dev);
1141 if (edev)
a880c4cd 1142 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1143
1144 vp->media_override = 7;
1145 if (option >= 0) {
1146 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1147 if (vp->media_override != 7)
1148 vp->medialock = 1;
1149 vp->full_duplex = (option & 0x200) ? 1 : 0;
1150 vp->bus_master = (option & 16) ? 1 : 0;
1151 }
1152
1153 if (global_full_duplex > 0)
1154 vp->full_duplex = 1;
1155 if (global_enable_wol > 0)
1156 vp->enable_wol = 1;
1157
1158 if (card_idx < MAX_UNITS) {
1159 if (full_duplex[card_idx] > 0)
1160 vp->full_duplex = 1;
1161 if (flow_ctrl[card_idx] > 0)
1162 vp->flow_ctrl = 1;
1163 if (enable_wol[card_idx] > 0)
1164 vp->enable_wol = 1;
1165 }
1166
125d5ce8 1167 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1168 vp->options = option;
1169 /* Read the station address from the EEPROM. */
1170 EL3WINDOW(0);
1171 {
1172 int base;
1173
1174 if (vci->drv_flags & EEPROM_8BIT)
1175 base = 0x230;
1176 else if (vci->drv_flags & EEPROM_OFFSET)
1177 base = EEPROM_Read + 0x30;
1178 else
1179 base = EEPROM_Read;
1180
1181 for (i = 0; i < 0x40; i++) {
1182 int timer;
62afe595 1183 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1184 /* Pause for at least 162 us. for the read to take place. */
1185 for (timer = 10; timer >= 0; timer--) {
1186 udelay(162);
62afe595 1187 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1188 break;
1189 }
62afe595 1190 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1191 }
1192 }
1193 for (i = 0; i < 0x18; i++)
1194 checksum ^= eeprom[i];
1195 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1196 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1197 while (i < 0x21)
1198 checksum ^= eeprom[i++];
1199 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1200 }
1201 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1202 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1203 for (i = 0; i < 3; i++)
1204 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1205 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1206 if (print_info) {
1207 for (i = 0; i < 6; i++)
1208 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1209 }
1210 /* Unfortunately an all zero eeprom passes the checksum and this
1211 gets found in the wild in failure cases. Crypto is hard 8) */
1212 if (!is_valid_ether_addr(dev->dev_addr)) {
1213 retval = -EINVAL;
1214 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1215 goto free_ring; /* With every pack */
1216 }
1217 EL3WINDOW(2);
1218 for (i = 0; i < 6; i++)
62afe595 1219 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1220
1da177e4
LT		 1221 if (print_info)
1222 printk(", IRQ %d\n", dev->irq);
1223 /* Tell them about an invalid IRQ. */
1224 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1225 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1226 dev->irq);
1da177e4
LT		 1227
1228 EL3WINDOW(4);
62afe595 1229 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1230 if (print_info) {
1231 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1232 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1233 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1234 }
1235
1236
1237 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1238 unsigned short n;
1239
62afe595
JL		 1240 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1241 if (!vp->cb_fn_base) {
1da177e4 1242 retval = -ENOMEM;
62afe595 1243 goto free_ring;
1da177e4 1244 }
62afe595 1245
1da177e4 1246 if (print_info) {
7c7459d1
GKH		 1247 printk(KERN_INFO "%s: CardBus functions mapped "
1248 "%16.16llx->%p\n",
1249 print_name,
1250 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1251 vp->cb_fn_base);
1da177e4
LT		 1252 }
1253 EL3WINDOW(2);
1254
62afe595 1255 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1256 if (vp->drv_flags & INVERT_LED_PWR)
1257 n |= 0x10;
1258 if (vp->drv_flags & INVERT_MII_PWR)
1259 n |= 0x4000;
62afe595 1260 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1261 if (vp->drv_flags & WNO_XCVR_PWR) {
1262 EL3WINDOW(0);
62afe595 1263 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1264 }
1265 }
1266
1267 /* Extract our information from the EEPROM data. */
1268 vp->info1 = eeprom[13];
1269 vp->info2 = eeprom[15];
1270 vp->capabilities = eeprom[16];
1271
1272 if (vp->info1 & 0x8000) {
1273 vp->full_duplex = 1;
1274 if (print_info)
1275 printk(KERN_INFO "Full duplex capable\n");
1276 }
1277
1278 {
f71e1309 1279 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1280 unsigned int config;
1281 EL3WINDOW(3);
62afe595 1282 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1283 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1284 vp->available_media = 0x40;
62afe595 1285 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1286 if (print_info) {
1287 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1288 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1289 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1290 8 << RAM_SIZE(config),
1291 RAM_WIDTH(config) ? "word" : "byte",
1292 ram_split[RAM_SPLIT(config)],
1293 AUTOSELECT(config) ? "autoselect/" : "",
1294 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1295 media_tbl[XCVR(config)].name);
1296 }
1297 vp->default_media = XCVR(config);
1298 if (vp->default_media == XCVR_NWAY)
1299 vp->has_nway = 1;
1300 vp->autoselect = AUTOSELECT(config);
1301 }
1302
1303 if (vp->media_override != 7) {
1304 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1305 print_name, vp->media_override,
1306 media_tbl[vp->media_override].name);
1307 dev->if_port = vp->media_override;
1308 } else
1309 dev->if_port = vp->default_media;
1310
1311 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1312 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1313 int phy, phy_idx = 0;
1314 EL3WINDOW(4);
1315 mii_preamble_required++;
1316 if (vp->drv_flags & EXTRA_PREAMBLE)
1317 mii_preamble_required++;
1318 mdio_sync(ioaddr, 32);
106427e6 1319 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1320 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1321 int mii_status, phyx;
1322
1323 /*
1324 * For the 3c905CX we look at index 24 first, because it bogusly
1325 * reports an external PHY at all indices
1326 */
1327 if (phy == 0)
1328 phyx = 24;
1329 else if (phy <= 24)
1330 phyx = phy - 1;
1331 else
1332 phyx = phy;
106427e6 1333 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1334 if (mii_status && mii_status != 0xffff) {
1335 vp->phys[phy_idx++] = phyx;
1336 if (print_info) {
1337 printk(KERN_INFO " MII transceiver found at address %d,"
1338 " status %4x.\n", phyx, mii_status);
1339 }
1340 if ((mii_status & 0x0040) == 0)
1341 mii_preamble_required++;
1342 }
1343 }
1344 mii_preamble_required--;
1345 if (phy_idx == 0) {
1346 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1347 vp->phys[0] = 24;
1348 } else {
106427e6 1349 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1350 if (vp->full_duplex) {
1351 /* Only advertise the FD media types. */
1352 vp->advertising &= ~0x02A0;
1353 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1354 }
1355 }
1356 vp->mii.phy_id = vp->phys[0];
1357 }
1358
1359 if (vp->capabilities & CapBusMaster) {
1360 vp->full_bus_master_tx = 1;
1361 if (print_info) {
1362 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1363 (vp->info2 & 1) ? "early" : "whole-frame" );
1364 }
1365 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1366 vp->bus_master = 0; /* AKPM: vortex only */
1367 }
1368
1369 /* The 3c59x-specific entries in the device structure. */
1370 dev->open = vortex_open;
1371 if (vp->full_bus_master_tx) {
1372 dev->hard_start_xmit = boomerang_start_xmit;
1373 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1374 if (card_idx < MAX_UNITS &&
1375 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1376 hw_checksums[card_idx] == 1)) {
d311b0d3 1377 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4
LT		 1378 }
1379 } else {
1380 dev->hard_start_xmit = vortex_start_xmit;
1381 }
1382
1383 if (print_info) {
1384 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1385 print_name,
1386 (dev->features & NETIF_F_SG) ? "en":"dis",
1387 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1388 }
1389
1390 dev->stop = vortex_close;
1391 dev->get_stats = vortex_get_stats;
1392#ifdef CONFIG_PCI
1393 dev->do_ioctl = vortex_ioctl;
1394#endif
1395 dev->ethtool_ops = &vortex_ethtool_ops;
1396 dev->set_multicast_list = set_rx_mode;
1397 dev->tx_timeout = vortex_tx_timeout;
1398 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1399#ifdef CONFIG_NET_POLL_CONTROLLER
6aa20a22 1400 dev->poll_controller = poll_vortex;
1da177e4
LT		 1401#endif
1402 if (pdev) {
1403 vp->pm_state_valid = 1;
1404 pci_save_state(VORTEX_PCI(vp));
1405 acpi_set_WOL(dev);
1406 }
1407 retval = register_netdev(dev);
1408 if (retval == 0)
1409 return 0;
1410
1411free_ring:
1412 pci_free_consistent(pdev,
1413 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1414 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1415 vp->rx_ring,
1416 vp->rx_ring_dma);
1417free_region:
1418 if (vp->must_free_region)
62afe595 1419 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1420 free_netdev(dev);
1421 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1422out:
1423 return retval;
1424}
1425
1426static void
1427issue_and_wait(struct net_device *dev, int cmd)
1428{
62afe595
JL		 1429 struct vortex_private *vp = netdev_priv(dev);
1430 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1431 int i;
1432
62afe595 1433 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1434 for (i = 0; i < 2000; i++) {
62afe595 1435 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1436 return;
1437 }
1438
1439 /* OK, that didn't work. Do it the slow way. One second */
1440 for (i = 0; i < 100000; i++) {
62afe595 1441 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1442 if (vortex_debug > 1)
1443 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1444 dev->name, cmd, i * 10);
1445 return;
1446 }
1447 udelay(10);
1448 }
1449 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1450 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1451}
1452
125d5ce8
SK		 1453static void
1454vortex_set_duplex(struct net_device *dev)
1455{
1456 struct vortex_private *vp = netdev_priv(dev);
1457 void __iomem *ioaddr = vp->ioaddr;
1458
1459 printk(KERN_INFO "%s: setting %s-duplex.\n",
1460 dev->name, (vp->full_duplex) ? "full" : "half");
1461
1462 EL3WINDOW(3);
1463 /* Set the full-duplex bit. */
1464 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1465 (vp->large_frames ? 0x40 : 0) |
1466 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1467 0x100 : 0),
1468 ioaddr + Wn3_MAC_Ctrl);
125d5ce8
SK		 1469}
1470
1471static void vortex_check_media(struct net_device *dev, unsigned int init)
1472{
1473 struct vortex_private *vp = netdev_priv(dev);
1474 unsigned int ok_to_print = 0;
1475
1476 if (vortex_debug > 3)
1477 ok_to_print = 1;
1478
1479 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1480 vp->full_duplex = vp->mii.full_duplex;
1481 vortex_set_duplex(dev);
1482 } else if (init) {
1483 vortex_set_duplex(dev);
1484 }
1485}
1486
1da177e4
LT		 1487static void
1488vortex_up(struct net_device *dev)
1489{
1da177e4 1490 struct vortex_private *vp = netdev_priv(dev);
62afe595 1491 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1492 unsigned int config;
09ce3512 1493 int i, mii_reg1, mii_reg5;
1da177e4
LT		 1494
1495 if (VORTEX_PCI(vp)) {
1496 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1497 if (vp->pm_state_valid)
1498 pci_restore_state(VORTEX_PCI(vp));
1da177e4
LT		 1499 pci_enable_device(VORTEX_PCI(vp));
1500 }
1501
1502 /* Before initializing select the active media port. */
1503 EL3WINDOW(3);
62afe595 1504 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1505
1506 if (vp->media_override != 7) {
1507 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1508 dev->name, vp->media_override,
1509 media_tbl[vp->media_override].name);
1510 dev->if_port = vp->media_override;
1511 } else if (vp->autoselect) {
1512 if (vp->has_nway) {
1513 if (vortex_debug > 1)
1514 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1515 dev->name, dev->if_port);
1516 dev->if_port = XCVR_NWAY;
1517 } else {
1518 /* Find first available media type, starting with 100baseTx. */
1519 dev->if_port = XCVR_100baseTx;
1520 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1521 dev->if_port = media_tbl[dev->if_port].next;
1522 if (vortex_debug > 1)
1523 printk(KERN_INFO "%s: first available media type: %s\n",
1524 dev->name, media_tbl[dev->if_port].name);
1525 }
1526 } else {
1527 dev->if_port = vp->default_media;
1528 if (vortex_debug > 1)
1529 printk(KERN_INFO "%s: using default media %s\n",
1530 dev->name, media_tbl[dev->if_port].name);
1531 }
1532
1533 init_timer(&vp->timer);
1534 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1535 vp->timer.data = (unsigned long)dev;
1536 vp->timer.function = vortex_timer; /* timer handler */
1537 add_timer(&vp->timer);
1538
1539 init_timer(&vp->rx_oom_timer);
1540 vp->rx_oom_timer.data = (unsigned long)dev;
1541 vp->rx_oom_timer.function = rx_oom_timer;
1542
1543 if (vortex_debug > 1)
1544 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1545 dev->name, media_tbl[dev->if_port].name);
1546
125d5ce8 1547 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1548 config = BFINS(config, dev->if_port, 20, 4);
1549 if (vortex_debug > 6)
1550 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1551 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1552
1553 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1554 EL3WINDOW(4);
09ce3512
SK		 1555 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1556 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1557 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1558
125d5ce8 1559 vortex_check_media(dev, 1);
1da177e4 1560 }
125d5ce8
SK		 1561 else
1562 vortex_set_duplex(dev);
1da177e4 1563
09ce3512
SK		 1564 issue_and_wait(dev, TxReset);
1565 /*
1566 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1567 */
1568 issue_and_wait(dev, RxReset|0x04);
1569
1da177e4 1570
62afe595 1571 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1572
1573 if (vortex_debug > 1) {
1574 EL3WINDOW(4);
1575 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1576 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1577 }
1578
1579 /* Set the station address and mask in window 2 each time opened. */
1580 EL3WINDOW(2);
1581 for (i = 0; i < 6; i++)
62afe595 1582 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1583 for (; i < 12; i+=2)
62afe595 1584 iowrite16(0, ioaddr + i);
1da177e4
LT		 1585
1586 if (vp->cb_fn_base) {
62afe595 1587 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1588 if (vp->drv_flags & INVERT_LED_PWR)
1589 n |= 0x10;
1590 if (vp->drv_flags & INVERT_MII_PWR)
1591 n |= 0x4000;
62afe595 1592 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1593 }
1594
1595 if (dev->if_port == XCVR_10base2)
1596 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1597 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1598 if (dev->if_port != XCVR_NWAY) {
1599 EL3WINDOW(4);
62afe595 1600 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1601 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1602 }
1603
1604 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1605 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1606 EL3WINDOW(6);
1607 for (i = 0; i < 10; i++)
62afe595
JL		 1608 ioread8(ioaddr + i);
1609 ioread16(ioaddr + 10);
1610 ioread16(ioaddr + 12);
1da177e4
LT		 1611 /* New: On the Vortex we must also clear the BadSSD counter. */
1612 EL3WINDOW(4);
62afe595 1613 ioread8(ioaddr + 12);
1da177e4 1614 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1615 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1616
1617 /* Switch to register set 7 for normal use. */
1618 EL3WINDOW(7);
1619
1620 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1621 vp->cur_rx = vp->dirty_rx = 0;
1622 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1623 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1624 iowrite32(0x0020, ioaddr + PktStatus);
1625 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1626 }
1627 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1628 vp->cur_tx = vp->dirty_tx = 0;
1629 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1630 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1631 /* Clear the Rx, Tx rings. */
1632 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1633 vp->rx_ring[i].status = 0;
1634 for (i = 0; i < TX_RING_SIZE; i++)
1635 vp->tx_skbuff[i] = NULL;
62afe595 1636 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1637 }
1638 /* Set receiver mode: presumably accept b-case and phys addr only. */
1639 set_rx_mode(dev);
1640 /* enable 802.1q tagged frames */
1641 set_8021q_mode(dev, 1);
62afe595 1642 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1643
62afe595
JL		 1644 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1645 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1646 /* Allow status bits to be seen. */
1647 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1648 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1649 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1650 (vp->bus_master ? DMADone : 0);
1651 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1652 (vp->full_bus_master_rx ? 0 : RxComplete) |
1653 StatsFull | HostError | TxComplete | IntReq
1654 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1655 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1656 /* Ack all pending events, and set active indicator mask. */
62afe595 1657 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1658 ioaddr + EL3_CMD);
62afe595 1659 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1660 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1661 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4
LT		 1662 netif_start_queue (dev);
1663}
1664
1665static int
1666vortex_open(struct net_device *dev)
1667{
1668 struct vortex_private *vp = netdev_priv(dev);
1669 int i;
1670 int retval;
1671
1672 /* Use the now-standard shared IRQ implementation. */
1673 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1674 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1da177e4
LT		 1675 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1676 goto out;
1677 }
1678
1679 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1680 if (vortex_debug > 2)
1681 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1682 for (i = 0; i < RX_RING_SIZE; i++) {
1683 struct sk_buff *skb;
1684 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1685 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1686 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1687 skb = dev_alloc_skb(PKT_BUF_SZ);
1688 vp->rx_skbuff[i] = skb;
1689 if (skb == NULL)
1690 break; /* Bad news! */
1691 skb->dev = dev; /* Mark as being used by this device. */
1692 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1693 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1694 }
1695 if (i != RX_RING_SIZE) {
1696 int j;
1697 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1698 for (j = 0; j < i; j++) {
1699 if (vp->rx_skbuff[j]) {
1700 dev_kfree_skb(vp->rx_skbuff[j]);
1701 vp->rx_skbuff[j] = NULL;
1702 }
1703 }
1704 retval = -ENOMEM;
1705 goto out_free_irq;
1706 }
1707 /* Wrap the ring. */
1708 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1709 }
1710
1711 vortex_up(dev);
1712 return 0;
1713
1714out_free_irq:
1715 free_irq(dev->irq, dev);
1716out:
1717 if (vortex_debug > 1)
1718 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1719 return retval;
1720}
1721
1722static void
1723vortex_timer(unsigned long data)
1724{
1725 struct net_device *dev = (struct net_device *)data;
1726 struct vortex_private *vp = netdev_priv(dev);
62afe595 1727 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1728 int next_tick = 60*HZ;
1729 int ok = 0;
125d5ce8 1730 int media_status, old_window;
1da177e4
LT		 1731
1732 if (vortex_debug > 2) {
1733 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1734 dev->name, media_tbl[dev->if_port].name);
1735 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1736 }
1737
0a9da4bd 1738 disable_irq_lockdep(dev->irq);
62afe595 1739 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1740 EL3WINDOW(4);
62afe595 1741 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1742 switch (dev->if_port) {
1743 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1744 if (media_status & Media_LnkBeat) {
1745 netif_carrier_on(dev);
1746 ok = 1;
1747 if (vortex_debug > 1)
1748 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1749 dev->name, media_tbl[dev->if_port].name, media_status);
1750 } else {
1751 netif_carrier_off(dev);
1752 if (vortex_debug > 1) {
1753 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1754 dev->name, media_tbl[dev->if_port].name, media_status);
1755 }
1756 }
1757 break;
1758 case XCVR_MII: case XCVR_NWAY:
1759 {
1da177e4 1760 ok = 1;
125d5ce8
SK		 1761 spin_lock_bh(&vp->lock);
1762 vortex_check_media(dev, 0);
1da177e4
LT		 1763 spin_unlock_bh(&vp->lock);
1764 }
1765 break;
1766 default: /* Other media types handled by Tx timeouts. */
1767 if (vortex_debug > 1)
1768 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1769 dev->name, media_tbl[dev->if_port].name, media_status);
1770 ok = 1;
1771 }
b4ff6450
SK		 1772
1773 if (!netif_carrier_ok(dev))
1774 next_tick = 5*HZ;
1775
e94d10eb
SK		 1776 if (vp->medialock)
1777 goto leave_media_alone;
1778
a880c4cd 1779 if (!ok) {
1da177e4
LT		 1780 unsigned int config;
1781
1782 do {
1783 dev->if_port = media_tbl[dev->if_port].next;
1784 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1785 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1786 dev->if_port = vp->default_media;
1787 if (vortex_debug > 1)
1788 printk(KERN_DEBUG "%s: Media selection failing, using default "
1789 "%s port.\n",
1790 dev->name, media_tbl[dev->if_port].name);
1791 } else {
1792 if (vortex_debug > 1)
1793 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1794 "%s port.\n",
1795 dev->name, media_tbl[dev->if_port].name);
1796 next_tick = media_tbl[dev->if_port].wait;
1797 }
62afe595 1798 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1799 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1800
1801 EL3WINDOW(3);
62afe595 1802 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1803 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1804 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1805
62afe595 1806 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1807 ioaddr + EL3_CMD);
1808 if (vortex_debug > 1)
1809 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1810 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1811 }
1da177e4
LT		 1812
1813leave_media_alone:
1814 if (vortex_debug > 2)
1815 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1816 dev->name, media_tbl[dev->if_port].name);
1817
e94d10eb 1818 EL3WINDOW(old_window);
0a9da4bd 1819 enable_irq_lockdep(dev->irq);
1da177e4
LT		 1820 mod_timer(&vp->timer, RUN_AT(next_tick));
1821 if (vp->deferred)
62afe595 1822 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1823 return;
1824}
1825
1826static void vortex_tx_timeout(struct net_device *dev)
1827{
1828 struct vortex_private *vp = netdev_priv(dev);
62afe595 1829 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1830
1831 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1832 dev->name, ioread8(ioaddr + TxStatus),
1833 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1834 EL3WINDOW(4);
1835 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 1836 ioread16(ioaddr + Wn4_NetDiag),
1837 ioread16(ioaddr + Wn4_Media),
1838 ioread32(ioaddr + PktStatus),
1839 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 1840 /* Slight code bloat to be user friendly. */
62afe595 1841 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 1842 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1843 " network cable problem?\n", dev->name);
62afe595 1844 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 1845 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1846 " IRQ blocked by another device?\n", dev->name);
1847 /* Bad idea here.. but we might as well handle a few events. */
1848 {
1849 /*
1850 * Block interrupts because vortex_interrupt does a bare spin_lock()
1851 */
1852 unsigned long flags;
1853 local_irq_save(flags);
1854 if (vp->full_bus_master_tx)
7d12e780 1855 boomerang_interrupt(dev->irq, dev);
1da177e4 1856 else
7d12e780 1857 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1858 local_irq_restore(flags);
1859 }
1860 }
1861
1862 if (vortex_debug > 0)
1863 dump_tx_ring(dev);
1864
1865 issue_and_wait(dev, TxReset);
1866
1867 vp->stats.tx_errors++;
1868 if (vp->full_bus_master_tx) {
1869 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1870 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1871 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1872 ioaddr + DownListPtr);
1873 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1874 netif_wake_queue (dev);
1875 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1876 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1877 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 1878 } else {
1879 vp->stats.tx_dropped++;
1880 netif_wake_queue(dev);
1881 }
6aa20a22 1882
1da177e4 1883 /* Issue Tx Enable */
62afe595 1884 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 1885 dev->trans_start = jiffies;
6aa20a22 1886
1da177e4
LT		 1887 /* Switch to register set 7 for normal use. */
1888 EL3WINDOW(7);
1889}
1890
1891/*
1892 * Handle uncommon interrupt sources. This is a separate routine to minimize
1893 * the cache impact.
1894 */
1895static void
1896vortex_error(struct net_device *dev, int status)
1897{
1898 struct vortex_private *vp = netdev_priv(dev);
62afe595 1899 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1900 int do_tx_reset = 0, reset_mask = 0;
1901 unsigned char tx_status = 0;
1902
1903 if (vortex_debug > 2) {
1904 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1905 }
1906
1907 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1908 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 1909 /* Presumably a tx-timeout. We must merely re-enable. */
1910 if (vortex_debug > 2
1911 || (tx_status != 0x88 && vortex_debug > 0)) {
1912 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1913 dev->name, tx_status);
1914 if (tx_status == 0x82) {
1915 printk(KERN_ERR "Probably a duplex mismatch. See "
1916 "Documentation/networking/vortex.txt\n");
1917 }
1918 dump_tx_ring(dev);
1919 }
1920 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
1921 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
0000754c 1922 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1923 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1924 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1925 do_tx_reset = 1;
0000754c
AM		 1926 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1927 do_tx_reset = 1;
1928 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1929 } else { /* Merely re-enable the transmitter. */
62afe595 1930 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1931 }
1932 }
1933
1934 if (status & RxEarly) { /* Rx early is unused. */
1935 vortex_rx(dev);
62afe595 1936 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1937 }
1938 if (status & StatsFull) { /* Empty statistics. */
1939 static int DoneDidThat;
1940 if (vortex_debug > 4)
1941 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1942 update_stats(ioaddr, dev);
1943 /* HACK: Disable statistics as an interrupt source. */
1944 /* This occurs when we have the wrong media type! */
1945 if (DoneDidThat == 0 &&
62afe595 1946 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 1947 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1948 "stats as an interrupt source.\n", dev->name);
1949 EL3WINDOW(5);
62afe595 1950 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 1951 vp->intr_enable &= ~StatsFull;
1952 EL3WINDOW(7);
1953 DoneDidThat++;
1954 }
1955 }
1956 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 1957 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1958 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 1959 }
1960 if (status & HostError) {
1961 u16 fifo_diag;
1962 EL3WINDOW(4);
62afe595 1963 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 1964 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1965 dev->name, fifo_diag);
1966 /* Adapter failure requires Tx/Rx reset and reinit. */
1967 if (vp->full_bus_master_tx) {
62afe595 1968 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 1969 /* 0x80000000 PCI master abort. */
1970 /* 0x40000000 PCI target abort. */
1971 if (vortex_debug)
1972 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1973
1974 /* In this case, blow the card away */
1975 /* Must not enter D3 or we can't legally issue the reset! */
1976 vortex_down(dev, 0);
1977 issue_and_wait(dev, TotalReset | 0xff);
1978 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
1979 } else if (fifo_diag & 0x0400)
1980 do_tx_reset = 1;
1981 if (fifo_diag & 0x3000) {
1982 /* Reset Rx fifo and upload logic */
1983 issue_and_wait(dev, RxReset|0x07);
1984 /* Set the Rx filter to the current state. */
1985 set_rx_mode(dev);
1986 /* enable 802.1q VLAN tagged frames */
1987 set_8021q_mode(dev, 1);
62afe595
JL		 1988 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
1989 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 1990 }
1991 }
1992
1993 if (do_tx_reset) {
1994 issue_and_wait(dev, TxReset|reset_mask);
62afe595 1995 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1996 if (!vp->full_bus_master_tx)
1997 netif_wake_queue(dev);
1998 }
1999}
2000
2001static int
2002vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2003{
2004 struct vortex_private *vp = netdev_priv(dev);
62afe595 2005 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2006
2007 /* Put out the doubleword header... */
62afe595 2008 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2009 if (vp->bus_master) {
2010 /* Set the bus-master controller to transfer the packet. */
2011 int len = (skb->len + 3) & ~3;
a880c4cd 2012 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2013 ioaddr + Wn7_MasterAddr);
62afe595 2014 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2015 vp->tx_skb = skb;
62afe595 2016 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2017 /* netif_wake_queue() will be called at the DMADone interrupt. */
2018 } else {
2019 /* ... and the packet rounded to a doubleword. */
62afe595 2020 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2021 dev_kfree_skb (skb);
62afe595 2022 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2023 netif_start_queue (dev); /* AKPM: redundant? */
2024 } else {
2025 /* Interrupt us when the FIFO has room for max-sized packet. */
2026 netif_stop_queue(dev);
62afe595 2027 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2028 }
2029 }
2030
2031 dev->trans_start = jiffies;
2032
2033 /* Clear the Tx status stack. */
2034 {
2035 int tx_status;
2036 int i = 32;
2037
62afe595 2038 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2039 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2040 if (vortex_debug > 2)
2041 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2042 dev->name, tx_status);
2043 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2044 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2045 if (tx_status & 0x30) {
2046 issue_and_wait(dev, TxReset);
2047 }
62afe595 2048 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2049 }
62afe595 2050 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2051 }
2052 }
2053 return 0;
2054}
2055
2056static int
2057boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2058{
2059 struct vortex_private *vp = netdev_priv(dev);
62afe595 2060 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2061 /* Calculate the next Tx descriptor entry. */
2062 int entry = vp->cur_tx % TX_RING_SIZE;
2063 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2064 unsigned long flags;
2065
2066 if (vortex_debug > 6) {
2067 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2068 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2069 dev->name, vp->cur_tx);
1da177e4
LT		 2070 }
2071
2072 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2073 if (vortex_debug > 0)
2074 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2075 dev->name);
2076 netif_stop_queue(dev);
2077 return 1;
2078 }
2079
2080 vp->tx_skbuff[entry] = skb;
2081
2082 vp->tx_ring[entry].next = 0;
2083#if DO_ZEROCOPY
84fa7933 2084 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2085 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2086 else
2087 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2088
2089 if (!skb_shinfo(skb)->nr_frags) {
2090 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2091 skb->len, PCI_DMA_TODEVICE));
2092 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2093 } else {
2094 int i;
2095
2096 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2097 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2098 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2099
2100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2101 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2102
2103 vp->tx_ring[entry].frag[i+1].addr =
2104 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2105 (void*)page_address(frag->page) + frag->page_offset,
2106 frag->size, PCI_DMA_TODEVICE));
2107
2108 if (i == skb_shinfo(skb)->nr_frags-1)
2109 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2110 else
2111 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2112 }
2113 }
2114#else
2115 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2116 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2117 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2118#endif
2119
2120 spin_lock_irqsave(&vp->lock, flags);
2121 /* Wait for the stall to complete. */
2122 issue_and_wait(dev, DownStall);
2123 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2124 if (ioread32(ioaddr + DownListPtr) == 0) {
2125 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2126 vp->queued_packet++;
2127 }
2128
2129 vp->cur_tx++;
2130 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2131 netif_stop_queue (dev);
2132 } else { /* Clear previous interrupt enable. */
2133#if defined(tx_interrupt_mitigation)
2134 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2135 * were selected, this would corrupt DN_COMPLETE. No?
2136 */
2137 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2138#endif
2139 }
62afe595 2140 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2141 spin_unlock_irqrestore(&vp->lock, flags);
2142 dev->trans_start = jiffies;
2143 return 0;
2144}
2145
2146/* The interrupt handler does all of the Rx thread work and cleans up
2147 after the Tx thread. */
2148
2149/*
2150 * This is the ISR for the vortex series chips.
2151 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2152 */
2153
2154static irqreturn_t
7d12e780 2155vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2156{
2157 struct net_device *dev = dev_id;
2158 struct vortex_private *vp = netdev_priv(dev);
62afe595 2159 void __iomem *ioaddr;
1da177e4
LT		 2160 int status;
2161 int work_done = max_interrupt_work;
2162 int handled = 0;
2163
62afe595 2164 ioaddr = vp->ioaddr;
1da177e4
LT		 2165 spin_lock(&vp->lock);
2166
62afe595 2167 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2168
2169 if (vortex_debug > 6)
2170 printk("vortex_interrupt(). status=0x%4x\n", status);
2171
2172 if ((status & IntLatch) == 0)
2173 goto handler_exit; /* No interrupt: shared IRQs cause this */
2174 handled = 1;
2175
2176 if (status & IntReq) {
2177 status |= vp->deferred;
2178 vp->deferred = 0;
2179 }
2180
2181 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2182 goto handler_exit;
2183
2184 if (vortex_debug > 4)
2185 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2186 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2187
2188 do {
2189 if (vortex_debug > 5)
2190 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2191 dev->name, status);
2192 if (status & RxComplete)
2193 vortex_rx(dev);
2194
2195 if (status & TxAvailable) {
2196 if (vortex_debug > 5)
2197 printk(KERN_DEBUG " TX room bit was handled.\n");
2198 /* There's room in the FIFO for a full-sized packet. */
62afe595 2199 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2200 netif_wake_queue (dev);
2201 }
2202
2203 if (status & DMADone) {
62afe595
JL		 2204 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2205 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2206 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2207 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2208 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2209 /*
2210 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2211 * insufficient FIFO room, the TxAvailable test will succeed and call
2212 * netif_wake_queue()
2213 */
2214 netif_wake_queue(dev);
2215 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2216 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2217 netif_stop_queue(dev);
2218 }
2219 }
2220 }
2221 /* Check for all uncommon interrupts at once. */
2222 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2223 if (status == 0xffff)
2224 break;
2225 vortex_error(dev, status);
2226 }
2227
2228 if (--work_done < 0) {
2229 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2230 "%4.4x.\n", dev->name, status);
2231 /* Disable all pending interrupts. */
2232 do {
2233 vp->deferred |= status;
62afe595 2234 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2235 ioaddr + EL3_CMD);
62afe595
JL		 2236 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2237 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2238 /* The timer will reenable interrupts. */
2239 mod_timer(&vp->timer, jiffies + 1*HZ);
2240 break;
2241 }
2242 /* Acknowledge the IRQ. */
62afe595
JL		 2243 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2244 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2245
2246 if (vortex_debug > 4)
2247 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2248 dev->name, status);
2249handler_exit:
2250 spin_unlock(&vp->lock);
2251 return IRQ_RETVAL(handled);
2252}
2253
2254/*
2255 * This is the ISR for the boomerang series chips.
2256 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2257 */
2258
2259static irqreturn_t
7d12e780 2260boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2261{
2262 struct net_device *dev = dev_id;
2263 struct vortex_private *vp = netdev_priv(dev);
62afe595 2264 void __iomem *ioaddr;
1da177e4
LT		 2265 int status;
2266 int work_done = max_interrupt_work;
2267
62afe595 2268 ioaddr = vp->ioaddr;
1da177e4
LT		 2269
2270 /*
2271 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2272 * and boomerang_start_xmit
2273 */
2274 spin_lock(&vp->lock);
2275
62afe595 2276 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2277
2278 if (vortex_debug > 6)
2279 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2280
2281 if ((status & IntLatch) == 0)
2282 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2283
2284 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2285 if (vortex_debug > 1)
2286 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2287 goto handler_exit;
2288 }
2289
2290 if (status & IntReq) {
2291 status |= vp->deferred;
2292 vp->deferred = 0;
2293 }
2294
2295 if (vortex_debug > 4)
2296 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2297 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2298 do {
2299 if (vortex_debug > 5)
2300 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2301 dev->name, status);
2302 if (status & UpComplete) {
62afe595 2303 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2304 if (vortex_debug > 5)
2305 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2306 boomerang_rx(dev);
2307 }
2308
2309 if (status & DownComplete) {
2310 unsigned int dirty_tx = vp->dirty_tx;
2311
62afe595 2312 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2313 while (vp->cur_tx - dirty_tx > 0) {
2314 int entry = dirty_tx % TX_RING_SIZE;
2315#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2316 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2317 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2318 break; /* It still hasn't been processed. */
2319#else
2320 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2321 break; /* It still hasn't been processed. */
2322#endif
6aa20a22 2323
1da177e4
LT		 2324 if (vp->tx_skbuff[entry]) {
2325 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2326#if DO_ZEROCOPY
1da177e4
LT		 2327 int i;
2328 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2329 pci_unmap_single(VORTEX_PCI(vp),
2330 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2331 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2332 PCI_DMA_TODEVICE);
2333#else
2334 pci_unmap_single(VORTEX_PCI(vp),
2335 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2336#endif
2337 dev_kfree_skb_irq(skb);
2338 vp->tx_skbuff[entry] = NULL;
2339 } else {
2340 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2341 }
2342 /* vp->stats.tx_packets++; Counted below. */
2343 dirty_tx++;
2344 }
2345 vp->dirty_tx = dirty_tx;
2346 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2347 if (vortex_debug > 6)
2348 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2349 netif_wake_queue (dev);
2350 }
2351 }
2352
2353 /* Check for all uncommon interrupts at once. */
2354 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2355 vortex_error(dev, status);
2356
2357 if (--work_done < 0) {
2358 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2359 "%4.4x.\n", dev->name, status);
2360 /* Disable all pending interrupts. */
2361 do {
2362 vp->deferred |= status;
62afe595 2363 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2364 ioaddr + EL3_CMD);
62afe595
JL		 2365 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2366 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2367 /* The timer will reenable interrupts. */
2368 mod_timer(&vp->timer, jiffies + 1*HZ);
2369 break;
2370 }
2371 /* Acknowledge the IRQ. */
62afe595 2372 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2373 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2374 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2375
62afe595 2376 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2377
2378 if (vortex_debug > 4)
2379 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2380 dev->name, status);
2381handler_exit:
2382 spin_unlock(&vp->lock);
2383 return IRQ_HANDLED;
2384}
2385
2386static int vortex_rx(struct net_device *dev)
2387{
2388 struct vortex_private *vp = netdev_priv(dev);
62afe595 2389 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2390 int i;
2391 short rx_status;
2392
2393 if (vortex_debug > 5)
2394 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2395 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2396 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2397 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2398 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2399 if (vortex_debug > 2)
2400 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2401 vp->stats.rx_errors++;
2402 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2403 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2404 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2405 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2406 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2407 } else {
2408 /* The packet length: up to 4.5K!. */
2409 int pkt_len = rx_status & 0x1fff;
2410 struct sk_buff *skb;
2411
2412 skb = dev_alloc_skb(pkt_len + 5);
2413 if (vortex_debug > 4)
2414 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2415 pkt_len, rx_status);
2416 if (skb != NULL) {
1da177e4
LT		 2417 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2418 /* 'skb_put()' points to the start of sk_buff data area. */
2419 if (vp->bus_master &&
62afe595 2420 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2421 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2422 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2423 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2424 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2425 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2426 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2427 ;
2428 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2429 } else {
62afe595
JL		 2430 ioread32_rep(ioaddr + RX_FIFO,
2431 skb_put(skb, pkt_len),
2432 (pkt_len + 3) >> 2);
1da177e4 2433 }
62afe595 2434 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2435 skb->protocol = eth_type_trans(skb, dev);
2436 netif_rx(skb);
2437 dev->last_rx = jiffies;
2438 vp->stats.rx_packets++;
2439 /* Wait a limited time to go to next packet. */
2440 for (i = 200; i >= 0; i--)
62afe595 2441 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2442 break;
2443 continue;
2444 } else if (vortex_debug > 0)
2445 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2446 "size %d.\n", dev->name, pkt_len);
35b30674 2447 vp->stats.rx_dropped++;
1da177e4 2448 }
1da177e4
LT		 2449 issue_and_wait(dev, RxDiscard);
2450 }
2451
2452 return 0;
2453}
2454
2455static int
2456boomerang_rx(struct net_device *dev)
2457{
2458 struct vortex_private *vp = netdev_priv(dev);
2459 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2460 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2461 int rx_status;
2462 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2463
2464 if (vortex_debug > 5)
62afe595 2465 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2466
2467 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2468 if (--rx_work_limit < 0)
2469 break;
2470 if (rx_status & RxDError) { /* Error, update stats. */
2471 unsigned char rx_error = rx_status >> 16;
2472 if (vortex_debug > 2)
2473 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2474 vp->stats.rx_errors++;
2475 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2476 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2477 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2478 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2479 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2480 } else {
2481 /* The packet length: up to 4.5K!. */
2482 int pkt_len = rx_status & 0x1fff;
2483 struct sk_buff *skb;
2484 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2485
2486 if (vortex_debug > 4)
2487 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2488 pkt_len, rx_status);
2489
2490 /* Check if the packet is long enough to just accept without
2491 copying to a properly sized skbuff. */
2492 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
1da177e4
LT		 2493 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2494 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2495 /* 'skb_put()' points to the start of sk_buff data area. */
2496 memcpy(skb_put(skb, pkt_len),
689be439 2497 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2498 pkt_len);
2499 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2500 vp->rx_copy++;
2501 } else {
2502 /* Pass up the skbuff already on the Rx ring. */
2503 skb = vp->rx_skbuff[entry];
2504 vp->rx_skbuff[entry] = NULL;
2505 skb_put(skb, pkt_len);
2506 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2507 vp->rx_nocopy++;
2508 }
2509 skb->protocol = eth_type_trans(skb, dev);
2510 { /* Use hardware checksum info. */
2511 int csum_bits = rx_status & 0xee000000;
2512 if (csum_bits &&
2513 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2514 csum_bits == (IPChksumValid | UDPChksumValid))) {
2515 skb->ip_summed = CHECKSUM_UNNECESSARY;
2516 vp->rx_csumhits++;
2517 }
2518 }
2519 netif_rx(skb);
2520 dev->last_rx = jiffies;
2521 vp->stats.rx_packets++;
2522 }
2523 entry = (++vp->cur_rx) % RX_RING_SIZE;
2524 }
2525 /* Refill the Rx ring buffers. */
2526 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2527 struct sk_buff *skb;
2528 entry = vp->dirty_rx % RX_RING_SIZE;
2529 if (vp->rx_skbuff[entry] == NULL) {
2530 skb = dev_alloc_skb(PKT_BUF_SZ);
2531 if (skb == NULL) {
2532 static unsigned long last_jif;
ff5688ae 2533 if (time_after(jiffies, last_jif + 10 * HZ)) {
1da177e4
LT		 2534 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2535 last_jif = jiffies;
2536 }
2537 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2538 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2539 break; /* Bad news! */
2540 }
2541 skb->dev = dev; /* Mark as being used by this device. */
2542 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2543 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2544 vp->rx_skbuff[entry] = skb;
2545 }
2546 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2547 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2548 }
2549 return 0;
2550}
2551
2552/*
2553 * If we've hit a total OOM refilling the Rx ring we poll once a second
2554 * for some memory. Otherwise there is no way to restart the rx process.
2555 */
2556static void
2557rx_oom_timer(unsigned long arg)
2558{
2559 struct net_device *dev = (struct net_device *)arg;
2560 struct vortex_private *vp = netdev_priv(dev);
2561
2562 spin_lock_irq(&vp->lock);
2563 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2564 boomerang_rx(dev);
2565 if (vortex_debug > 1) {
2566 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2567 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2568 }
2569 spin_unlock_irq(&vp->lock);
2570}
2571
2572static void
2573vortex_down(struct net_device *dev, int final_down)
2574{
2575 struct vortex_private *vp = netdev_priv(dev);
62afe595 2576 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2577
2578 netif_stop_queue (dev);
2579
2580 del_timer_sync(&vp->rx_oom_timer);
2581 del_timer_sync(&vp->timer);
2582
2583 /* Turn off statistics ASAP. We update vp->stats below. */
62afe595 2584 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2585
2586 /* Disable the receiver and transmitter. */
62afe595
JL		 2587 iowrite16(RxDisable, ioaddr + EL3_CMD);
2588 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2589
2590 /* Disable receiving 802.1q tagged frames */
2591 set_8021q_mode(dev, 0);
2592
2593 if (dev->if_port == XCVR_10base2)
2594 /* Turn off thinnet power. Green! */
62afe595 2595 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2596
62afe595 2597 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2598
2599 update_stats(ioaddr, dev);
2600 if (vp->full_bus_master_rx)
62afe595 2601 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2602 if (vp->full_bus_master_tx)
62afe595 2603 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2604
2605 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2606 vp->pm_state_valid = 1;
1da177e4
LT		 2607 pci_save_state(VORTEX_PCI(vp));
2608 acpi_set_WOL(dev);
2609 }
2610}
2611
2612static int
2613vortex_close(struct net_device *dev)
2614{
2615 struct vortex_private *vp = netdev_priv(dev);
62afe595 2616 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2617 int i;
2618
2619 if (netif_device_present(dev))
2620 vortex_down(dev, 1);
2621
2622 if (vortex_debug > 1) {
2623 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2624 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2625 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2626 " tx_queued %d Rx pre-checksummed %d.\n",
2627 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2628 }
2629
2630#if DO_ZEROCOPY
32fb5f06
JL		 2631 if (vp->rx_csumhits &&
2632 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2633 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2634 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2635 "not using them!\n", dev->name);
1da177e4
LT		 2636 }
2637#endif
6aa20a22 2638
1da177e4
LT		 2639 free_irq(dev->irq, dev);
2640
2641 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2642 for (i = 0; i < RX_RING_SIZE; i++)
2643 if (vp->rx_skbuff[i]) {
2644 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2645 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2646 dev_kfree_skb(vp->rx_skbuff[i]);
2647 vp->rx_skbuff[i] = NULL;
2648 }
2649 }
2650 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2651 for (i = 0; i < TX_RING_SIZE; i++) {
2652 if (vp->tx_skbuff[i]) {
2653 struct sk_buff *skb = vp->tx_skbuff[i];
2654#if DO_ZEROCOPY
2655 int k;
2656
2657 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2658 pci_unmap_single(VORTEX_PCI(vp),
2659 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2660 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2661 PCI_DMA_TODEVICE);
2662#else
2663 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2664#endif
2665 dev_kfree_skb(skb);
2666 vp->tx_skbuff[i] = NULL;
2667 }
2668 }
2669 }
2670
2671 return 0;
2672}
2673
2674static void
2675dump_tx_ring(struct net_device *dev)
2676{
2677 if (vortex_debug > 0) {
2678 struct vortex_private *vp = netdev_priv(dev);
62afe595 2679 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2680
1da177e4
LT		 2681 if (vp->full_bus_master_tx) {
2682 int i;
62afe595 2683 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2684
2685 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2686 vp->full_bus_master_tx,
2687 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2688 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2689 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2690 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2691 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2692 issue_and_wait(dev, DownStall);
2693 for (i = 0; i < TX_RING_SIZE; i++) {
2694 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2695 &vp->tx_ring[i],
2696#if DO_ZEROCOPY
2697 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2698#else
2699 le32_to_cpu(vp->tx_ring[i].length),
2700#endif
2701 le32_to_cpu(vp->tx_ring[i].status));
2702 }
2703 if (!stalled)
62afe595 2704 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2705 }
2706 }
2707}
2708
2709static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2710{
2711 struct vortex_private *vp = netdev_priv(dev);
62afe595 2712 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2713 unsigned long flags;
2714
2715 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2716 spin_lock_irqsave (&vp->lock, flags);
62afe595 2717 update_stats(ioaddr, dev);
1da177e4
LT		 2718 spin_unlock_irqrestore (&vp->lock, flags);
2719 }
2720 return &vp->stats;
2721}
2722
2723/* Update statistics.
2724 Unlike with the EL3 we need not worry about interrupts changing
2725 the window setting from underneath us, but we must still guard
2726 against a race condition with a StatsUpdate interrupt updating the
2727 table. This is done by checking that the ASM (!) code generated uses
2728 atomic updates with '+='.
2729 */
62afe595 2730static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2731{
2732 struct vortex_private *vp = netdev_priv(dev);
62afe595 2733 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2734
2735 if (old_window == 0xffff) /* Chip suspended or ejected. */
2736 return;
2737 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2738 /* Switch to the stats window, and read everything. */
2739 EL3WINDOW(6);
62afe595
JL		 2740 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2741 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
62afe595
JL		 2742 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2743 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2744 vp->stats.tx_packets += ioread8(ioaddr + 6);
2745 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2746 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2747 /* Don't bother with register 9, an extension of registers 6&7.
2748 If we do use the 6&7 values the atomic update assumption above
2749 is invalid. */
62afe595
JL		 2750 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2751 vp->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2752 /* Extra stats for get_ethtool_stats() */
62afe595 2753 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2754 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2755 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2756 EL3WINDOW(4);
62afe595 2757 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2758
8d1d0340
SK		 2759 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2760 + vp->xstats.tx_single_collisions
2761 + vp->xstats.tx_max_collisions;
2762
1da177e4 2763 {
62afe595 2764 u8 up = ioread8(ioaddr + 13);
1da177e4
LT		 2765 vp->stats.rx_bytes += (up & 0x0f) << 16;
2766 vp->stats.tx_bytes += (up & 0xf0) << 12;
2767 }
2768
2769 EL3WINDOW(old_window >> 13);
2770 return;
2771}
2772
2773static int vortex_nway_reset(struct net_device *dev)
2774{
2775 struct vortex_private *vp = netdev_priv(dev);
62afe595 2776 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2777 unsigned long flags;
2778 int rc;
2779
2780 spin_lock_irqsave(&vp->lock, flags);
2781 EL3WINDOW(4);
2782 rc = mii_nway_restart(&vp->mii);
2783 spin_unlock_irqrestore(&vp->lock, flags);
2784 return rc;
2785}
2786
1da177e4
LT		 2787static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2788{
2789 struct vortex_private *vp = netdev_priv(dev);
62afe595 2790 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2791 unsigned long flags;
2792 int rc;
2793
2794 spin_lock_irqsave(&vp->lock, flags);
2795 EL3WINDOW(4);
2796 rc = mii_ethtool_gset(&vp->mii, cmd);
2797 spin_unlock_irqrestore(&vp->lock, flags);
2798 return rc;
2799}
2800
2801static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2802{
2803 struct vortex_private *vp = netdev_priv(dev);
62afe595 2804 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2805 unsigned long flags;
2806 int rc;
2807
2808 spin_lock_irqsave(&vp->lock, flags);
2809 EL3WINDOW(4);
2810 rc = mii_ethtool_sset(&vp->mii, cmd);
2811 spin_unlock_irqrestore(&vp->lock, flags);
2812 return rc;
2813}
2814
2815static u32 vortex_get_msglevel(struct net_device *dev)
2816{
2817 return vortex_debug;
2818}
2819
2820static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2821{
2822 vortex_debug = dbg;
2823}
2824
2825static int vortex_get_stats_count(struct net_device *dev)
2826{
2827 return VORTEX_NUM_STATS;
2828}
2829
2830static void vortex_get_ethtool_stats(struct net_device *dev,
2831 struct ethtool_stats *stats, u64 *data)
2832{
2833 struct vortex_private *vp = netdev_priv(dev);
62afe595 2834 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2835 unsigned long flags;
2836
2837 spin_lock_irqsave(&vp->lock, flags);
62afe595 2838 update_stats(ioaddr, dev);
1da177e4
LT		 2839 spin_unlock_irqrestore(&vp->lock, flags);
2840
2841 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2842 data[1] = vp->xstats.tx_max_collisions;
2843 data[2] = vp->xstats.tx_multiple_collisions;
2844 data[3] = vp->xstats.tx_single_collisions;
2845 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2846}
2847
2848
2849static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2850{
2851 switch (stringset) {
2852 case ETH_SS_STATS:
2853 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2854 break;
2855 default:
2856 WARN_ON(1);
2857 break;
2858 }
2859}
2860
2861static void vortex_get_drvinfo(struct net_device *dev,
2862 struct ethtool_drvinfo *info)
2863{
2864 struct vortex_private *vp = netdev_priv(dev);
2865
2866 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2867 if (VORTEX_PCI(vp)) {
2868 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2869 } else {
2870 if (VORTEX_EISA(vp))
2871 sprintf(info->bus_info, vp->gendev->bus_id);
2872 else
2873 sprintf(info->bus_info, "EISA 0x%lx %d",
2874 dev->base_addr, dev->irq);
2875 }
2876}
2877
7282d491 2878static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2879 .get_drvinfo = vortex_get_drvinfo,
2880 .get_strings = vortex_get_strings,
2881 .get_msglevel = vortex_get_msglevel,
2882 .set_msglevel = vortex_set_msglevel,
2883 .get_ethtool_stats = vortex_get_ethtool_stats,
2884 .get_stats_count = vortex_get_stats_count,
2885 .get_settings = vortex_get_settings,
2886 .set_settings = vortex_set_settings,
373a6887 2887 .get_link = ethtool_op_get_link,
1da177e4 2888 .nway_reset = vortex_nway_reset,
a880c4cd 2889 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 2890};
2891
2892#ifdef CONFIG_PCI
2893/*
2894 * Must power the device up to do MDIO operations
2895 */
2896static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2897{
2898 int err;
2899 struct vortex_private *vp = netdev_priv(dev);
62afe595 2900 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2901 unsigned long flags;
2902 int state = 0;
2903
2904 if(VORTEX_PCI(vp))
2905 state = VORTEX_PCI(vp)->current_state;
2906
2907 /* The kernel core really should have pci_get_power_state() */
2908
2909 if(state != 0)
2910 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2911 spin_lock_irqsave(&vp->lock, flags);
2912 EL3WINDOW(4);
2913 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2914 spin_unlock_irqrestore(&vp->lock, flags);
2915 if(state != 0)
2916 pci_set_power_state(VORTEX_PCI(vp), state);
2917
2918 return err;
2919}
2920#endif
2921
2922
2923/* Pre-Cyclone chips have no documented multicast filter, so the only
2924 multicast setting is to receive all multicast frames. At least
2925 the chip has a very clean way to set the mode, unlike many others. */
2926static void set_rx_mode(struct net_device *dev)
2927{
62afe595
JL		 2928 struct vortex_private *vp = netdev_priv(dev);
2929 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2930 int new_mode;
2931
2932 if (dev->flags & IFF_PROMISC) {
d5b20697 2933 if (vortex_debug > 3)
1da177e4
LT		 2934 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2935 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2936 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2937 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2938 } else
2939 new_mode = SetRxFilter | RxStation | RxBroadcast;
2940
62afe595 2941 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2942}
2943
2944#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2945/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2946 Note that this must be done after each RxReset due to some backwards
2947 compatibility logic in the Cyclone and Tornado ASICs */
2948
2949/* The Ethernet Type used for 802.1q tagged frames */
2950#define VLAN_ETHER_TYPE 0x8100
2951
2952static void set_8021q_mode(struct net_device *dev, int enable)
2953{
2954 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 2955 void __iomem *ioaddr = vp->ioaddr;
2956 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2957 int mac_ctrl;
2958
2959 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2960 /* cyclone and tornado chipsets can recognize 802.1q
2961 * tagged frames and treat them correctly */
2962
2963 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2964 if (enable)
2965 max_pkt_size += 4; /* 802.1Q VLAN tag */
2966
2967 EL3WINDOW(3);
62afe595 2968 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 2969
2970 /* set VlanEtherType to let the hardware checksumming
2971 treat tagged frames correctly */
2972 EL3WINDOW(7);
62afe595 2973 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 2974 } else {
2975 /* on older cards we have to enable large frames */
2976
2977 vp->large_frames = dev->mtu > 1500 || enable;
2978
2979 EL3WINDOW(3);
62afe595 2980 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2981 if (vp->large_frames)
2982 mac_ctrl |= 0x40;
2983 else
2984 mac_ctrl &= ~0x40;
62afe595 2985 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 2986 }
2987
2988 EL3WINDOW(old_window);
2989}
2990#else
2991
2992static void set_8021q_mode(struct net_device *dev, int enable)
2993{
2994}
2995
2996
2997#endif
2998
2999/* MII transceiver control section.
3000 Read and write the MII registers using software-generated serial
3001 MDIO protocol. See the MII specifications or DP83840A data sheet
3002 for details. */
3003
3004/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3005 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3006 "overclocking" issues. */
62afe595 3007#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3008
3009#define MDIO_SHIFT_CLK 0x01
3010#define MDIO_DIR_WRITE 0x04
3011#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3012#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3013#define MDIO_DATA_READ 0x02
3014#define MDIO_ENB_IN 0x00
3015
3016/* Generate the preamble required for initial synchronization and
3017 a few older transceivers. */
62afe595 3018static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3019{
62afe595 3020 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3021
3022 /* Establish sync by sending at least 32 logic ones. */
3023 while (-- bits >= 0) {
62afe595 3024 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3025 mdio_delay();
62afe595 3026 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3027 mdio_delay();
3028 }
3029}
3030
3031static int mdio_read(struct net_device *dev, int phy_id, int location)
3032{
3033 int i;
62afe595
JL		 3034 struct vortex_private *vp = netdev_priv(dev);
3035 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3036 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3037 unsigned int retval = 0;
62afe595 3038 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3039
3040 if (mii_preamble_required)
3041 mdio_sync(ioaddr, 32);
3042
3043 /* Shift the read command bits out. */
3044 for (i = 14; i >= 0; i--) {
3045 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3046 iowrite16(dataval, mdio_addr);
1da177e4 3047 mdio_delay();
62afe595 3048 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3049 mdio_delay();
3050 }
3051 /* Read the two transition, 16 data, and wire-idle bits. */
3052 for (i = 19; i > 0; i--) {
62afe595 3053 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3054 mdio_delay();
62afe595
JL		 3055 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3056 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3057 mdio_delay();
3058 }
3059 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3060}
3061
3062static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3063{
62afe595
JL		 3064 struct vortex_private *vp = netdev_priv(dev);
3065 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3066 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3067 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3068 int i;
3069
3070 if (mii_preamble_required)
3071 mdio_sync(ioaddr, 32);
3072
3073 /* Shift the command bits out. */
3074 for (i = 31; i >= 0; i--) {
3075 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3076 iowrite16(dataval, mdio_addr);
1da177e4 3077 mdio_delay();
62afe595 3078 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3079 mdio_delay();
3080 }
3081 /* Leave the interface idle. */
3082 for (i = 1; i >= 0; i--) {
62afe595 3083 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3084 mdio_delay();
62afe595 3085 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3086 mdio_delay();
3087 }
3088 return;
3089}
a880c4cd 3090
1da177e4
LT		 3091/* ACPI: Advanced Configuration and Power Interface. */
3092/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3093static void acpi_set_WOL(struct net_device *dev)
3094{
3095 struct vortex_private *vp = netdev_priv(dev);
62afe595 3096 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3097
3098 if (vp->enable_wol) {
3099 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3100 EL3WINDOW(7);
62afe595 3101 iowrite16(2, ioaddr + 0x0c);
1da177e4 3102 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3103 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3104 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 3105
3106 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3c8fad18
DR		 3107
3108 /* Change the power state to D3; RxEnable doesn't take effect. */
3109 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3110 }
1da177e4
LT		 3111}
3112
3113
a880c4cd 3114static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3115{
3116 struct net_device *dev = pci_get_drvdata(pdev);
3117 struct vortex_private *vp;
3118
3119 if (!dev) {
3120 printk("vortex_remove_one called for Compaq device!\n");
3121 BUG();
3122 }
3123
3124 vp = netdev_priv(dev);
3125
62afe595
JL		 3126 if (vp->cb_fn_base)
3127 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3128
1da177e4
LT		 3129 unregister_netdev(dev);
3130
3131 if (VORTEX_PCI(vp)) {
3132 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3133 if (vp->pm_state_valid)
3134 pci_restore_state(VORTEX_PCI(vp));
3135 pci_disable_device(VORTEX_PCI(vp));
3136 }
3137 /* Should really use issue_and_wait() here */
62afe595
JL		 3138 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3139 vp->ioaddr + EL3_CMD);
3140
3141 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3142
3143 pci_free_consistent(pdev,
3144 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3145 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3146 vp->rx_ring,
3147 vp->rx_ring_dma);
3148 if (vp->must_free_region)
3149 release_region(dev->base_addr, vp->io_size);
3150 free_netdev(dev);
3151}
3152
3153
3154static struct pci_driver vortex_driver = {
3155 .name = "3c59x",
3156 .probe = vortex_init_one,
3157 .remove = __devexit_p(vortex_remove_one),
3158 .id_table = vortex_pci_tbl,
3159#ifdef CONFIG_PM
3160 .suspend = vortex_suspend,
3161 .resume = vortex_resume,
3162#endif
3163};
3164
3165
3166static int vortex_have_pci;
3167static int vortex_have_eisa;
3168
3169
a880c4cd 3170static int __init vortex_init(void)
1da177e4
LT		 3171{
3172 int pci_rc, eisa_rc;
3173
29917620 3174 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3175 eisa_rc = vortex_eisa_init();
3176
3177 if (pci_rc == 0)
3178 vortex_have_pci = 1;
3179 if (eisa_rc > 0)
3180 vortex_have_eisa = 1;
3181
3182 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3183}
3184
3185
a880c4cd 3186static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3187{
3188 struct vortex_private *vp;
62afe595 3189 void __iomem *ioaddr;
1da177e4
LT		 3190
3191#ifdef CONFIG_EISA
3192 /* Take care of the EISA devices */
a880c4cd 3193 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3194#endif
6aa20a22 3195
1da177e4
LT		 3196 if (compaq_net_device) {
3197 vp = compaq_net_device->priv;
62afe595
JL		 3198 ioaddr = ioport_map(compaq_net_device->base_addr,
3199 VORTEX_TOTAL_SIZE);
1da177e4 3200
a880c4cd
SK		 3201 unregister_netdev(compaq_net_device);
3202 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3203 release_region(compaq_net_device->base_addr,
3204 VORTEX_TOTAL_SIZE);
1da177e4 3205
a880c4cd 3206 free_netdev(compaq_net_device);
1da177e4
LT		 3207 }
3208}
3209
3210
a880c4cd 3211static void __exit vortex_cleanup(void)
1da177e4
LT		 3212{
3213 if (vortex_have_pci)
a880c4cd 3214 pci_unregister_driver(&vortex_driver);
1da177e4 3215 if (vortex_have_eisa)
a880c4cd 3216 vortex_eisa_cleanup();
1da177e4
LT		 3217}
3218
3219
3220module_init(vortex_init);
3221module_exit(vortex_cleanup);
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