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jme: Fix unmap error (Causing system freeze)
[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT		 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
2e582300 25#include <linux/version.h>
937ef75a
JP		 26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
d7699f87
GFT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
4330c2f2 38#include <linux/delay.h>
29bdd921 39#include <linux/spinlock.h>
8c198884
GFT		 40#include <linux/in.h>
41#include <linux/ip.h>
79ce639c
GFT		 42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
42b1055e 45#include <linux/if_vlan.h>
38d1bc09 46#include <linux/slab.h>
3b70a6fa 47#include <net/ip6_checksum.h>
d7699f87
GFT		 48#include "jme.h"
49
cd0ff491
GFT		 50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 61
6d06d88c 62#ifndef JME_NEW_PM_API
3d12cc1b
GFT		 63static void
64jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
65{
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
67 pci_enable_wake(jme->pdev, PCI_D1, enable);
68 pci_enable_wake(jme->pdev, PCI_D2, enable);
69 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
70 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
71#else
72 pci_pme_active(jme->pdev, enable);
73#endif
74}
6d06d88c 75#endif
3d12cc1b 76
3bf61c55
GFT		 77static int
78jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 79{
80 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 81 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 82
186fc259 83read_again:
cd0ff491 84 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 85 smi_phy_addr(phy) |
86 smi_reg_addr(reg));
d7699f87
GFT		 87
88 wmb();
cd0ff491 89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 90 udelay(20);
b3821cc5
GFT		 91 val = jread32(jme, JME_SMI);
92 if ((val & SMI_OP_REQ) == 0)
3bf61c55 93 break;
cd0ff491 94 }
d7699f87 95
cd0ff491 96 if (i == 0) {
937ef75a 97 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 98 return 0;
cd0ff491 99 }
d7699f87 100
cd0ff491 101 if (again--)
186fc259
GFT		 102 goto read_again;
103
cd0ff491 104 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 105}
106
3bf61c55
GFT		 107static void
108jme_mdio_write(struct net_device *netdev,
109 int phy, int reg, int val)
d7699f87
GFT		 110{
111 struct jme_adapter *jme = netdev_priv(netdev);
112 int i;
113
3bf61c55
GFT		 114 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
115 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
116 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 117
118 wmb();
cdcdc9eb
GFT		 119 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
120 udelay(20);
8d27293f 121 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 122 break;
123 }
d7699f87 124
3bf61c55 125 if (i == 0)
937ef75a 126 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT		 127}
128
cd0ff491 129static inline void
3bf61c55 130jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 131{
cd0ff491 132 u32 val;
3bf61c55
GFT		 133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
8c198884
GFT		 136 MII_ADVERTISE, ADVERTISE_ALL |
137 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 138
cd0ff491 139 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 140 jme_mdio_write(jme->dev,
141 jme->mii_if.phy_id,
142 MII_CTRL1000,
143 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 144
fcf45b4c
GFT		 145 val = jme_mdio_read(jme->dev,
146 jme->mii_if.phy_id,
147 MII_BMCR);
148
149 jme_mdio_write(jme->dev,
150 jme->mii_if.phy_id,
151 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT		 152}
153
b3821cc5
GFT		 154static void
155jme_setup_wakeup_frame(struct jme_adapter *jme,
a4181cd4 156 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 157{
158 int i;
159
160 /*
161 * Setup CRC pattern
162 */
163 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
164 wmb();
165 jwrite32(jme, JME_WFODP, crc);
166 wmb();
167
168 /*
169 * Setup Mask
170 */
cd0ff491 171 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 172 jwrite32(jme, JME_WFOI,
173 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
174 (fnr & WFOI_FRAME_SEL));
175 wmb();
176 jwrite32(jme, JME_WFODP, mask[i]);
177 wmb();
178 }
179}
3bf61c55 180
dc4185bd
GFT		 181static inline void
182jme_mac_rxclk_off(struct jme_adapter *jme)
183{
184 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
185 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
186}
187
188static inline void
189jme_mac_rxclk_on(struct jme_adapter *jme)
190{
191 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
192 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
193}
194
195static inline void
196jme_mac_txclk_off(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_mac_txclk_on(struct jme_adapter *jme)
204{
205 u32 speed = jme->reg_ghc & GHC_SPEED;
206 if (speed == GHC_SPEED_1000M)
207 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
208 else
209 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
210 jwrite32f(jme, JME_GHC, jme->reg_ghc);
211}
212
213static inline void
214jme_reset_ghc_speed(struct jme_adapter *jme)
215{
216 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_reset_250A2_workaround(struct jme_adapter *jme)
222{
223 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
224 GPREG1_RSSPATCH);
225 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
226}
227
228static inline void
229jme_assert_ghc_reset(struct jme_adapter *jme)
230{
231 jme->reg_ghc |= GHC_SWRST;
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
233}
234
235static inline void
236jme_clear_ghc_reset(struct jme_adapter *jme)
237{
238 jme->reg_ghc &= ~GHC_SWRST;
239 jwrite32f(jme, JME_GHC, jme->reg_ghc);
240}
241
cd0ff491 242static inline void
3bf61c55
GFT		 243jme_reset_mac_processor(struct jme_adapter *jme)
244{
a4181cd4 245 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT		 246 u32 crc = 0xCDCDCDCD;
247 u32 gpreg0;
b3821cc5
GFT		 248 int i;
249
dc4185bd
GFT		 250 jme_reset_ghc_speed(jme);
251 jme_reset_250A2_workaround(jme);
252
253 jme_mac_rxclk_on(jme);
254 jme_mac_txclk_on(jme);
255 udelay(1);
256 jme_assert_ghc_reset(jme);
257 udelay(1);
258 jme_mac_rxclk_off(jme);
259 jme_mac_txclk_off(jme);
260 udelay(1);
261 jme_clear_ghc_reset(jme);
262 udelay(1);
263 jme_mac_rxclk_on(jme);
264 jme_mac_txclk_on(jme);
265 udelay(1);
266 jme_mac_rxclk_off(jme);
267 jme_mac_txclk_off(jme);
cd0ff491
GFT		 268
269 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
270 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
271 jwrite32(jme, JME_RXQDC, 0x00000000);
272 jwrite32(jme, JME_RXNDA, 0x00000000);
273 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
274 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
275 jwrite32(jme, JME_TXQDC, 0x00000000);
276 jwrite32(jme, JME_TXNDA, 0x00000000);
277
4330c2f2
GFT		 278 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
279 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 280 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 281 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 282 if (jme->fpgaver)
cdcdc9eb
GFT		 283 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
284 else
285 gpreg0 = GPREG0_DEFAULT;
286 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT		 287}
288
289static inline void
3bf61c55 290jme_clear_pm(struct jme_adapter *jme)
d7699f87 291{
3d12cc1b 292 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
d7699f87
GFT		 293}
294
3bf61c55
GFT		 295static int
296jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 297{
cd0ff491 298 u32 val;
d7699f87
GFT		 299 int i;
300
301 val = jread32(jme, JME_SMBCSR);
302
cd0ff491 303 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 304 val |= SMBCSR_CNACK;
305 jwrite32(jme, JME_SMBCSR, val);
306 val |= SMBCSR_RELOAD;
307 jwrite32(jme, JME_SMBCSR, val);
308 mdelay(12);
309
cd0ff491 310 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 311 mdelay(1);
312 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
313 break;
314 }
315
cd0ff491 316 if (i == 0) {
937ef75a 317 pr_err("eeprom reload timeout\n");
d7699f87
GFT		 318 return -EIO;
319 }
320 }
3bf61c55 321
d7699f87
GFT		 322 return 0;
323}
324
3bf61c55
GFT		 325static void
326jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 327{
328 struct jme_adapter *jme = netdev_priv(netdev);
329 unsigned char macaddr[6];
cd0ff491 330 u32 val;
d7699f87 331
cd0ff491 332 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 333 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 334 macaddr[0] = (val >> 0) & 0xFF;
335 macaddr[1] = (val >> 8) & 0xFF;
336 macaddr[2] = (val >> 16) & 0xFF;
337 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 338 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 339 macaddr[4] = (val >> 0) & 0xFF;
340 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 341 memcpy(netdev->dev_addr, macaddr, 6);
342 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 343}
344
cd0ff491 345static inline void
3bf61c55
GFT		 346jme_set_rx_pcc(struct jme_adapter *jme, int p)
347{
cd0ff491 348 switch (p) {
192570e0
GFT		 349 case PCC_OFF:
350 jwrite32(jme, JME_PCCRX0,
351 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
352 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
353 break;
3bf61c55
GFT		 354 case PCC_P1:
355 jwrite32(jme, JME_PCCRX0,
356 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
357 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
358 break;
359 case PCC_P2:
360 jwrite32(jme, JME_PCCRX0,
361 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
362 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
363 break;
364 case PCC_P3:
365 jwrite32(jme, JME_PCCRX0,
366 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
367 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
368 break;
369 default:
370 break;
371 }
192570e0 372 wmb();
3bf61c55 373
cd0ff491 374 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
7ca9ebee 375 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 376}
377
fcf45b4c 378static void
3bf61c55 379jme_start_irq(struct jme_adapter *jme)
d7699f87 380{
3bf61c55
GFT		 381 register struct dynpcc_info *dpi = &(jme->dpi);
382
383 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 384 dpi->cur = PCC_P1;
385 dpi->attempt = PCC_P1;
386 dpi->cnt = 0;
387
388 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 389 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
390 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 391 PCCTXQ0_EN
392 );
393
d7699f87
GFT		 394 /*
395 * Enable Interrupts
396 */
397 jwrite32(jme, JME_IENS, INTR_ENABLE);
398}
399
cd0ff491 400static inline void
3bf61c55 401jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 402{
403 /*
404 * Disable Interrupts
405 */
cd0ff491 406 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 407}
408
cd0ff491 409static u32
cdcdc9eb
GFT		 410jme_linkstat_from_phy(struct jme_adapter *jme)
411{
cd0ff491 412 u32 phylink, bmsr;
cdcdc9eb
GFT		 413
414 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
415 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 416 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 417 phylink |= PHY_LINK_AUTONEG_COMPLETE;
418
419 return phylink;
420}
421
cd0ff491 422static inline void
55d19799 423jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT		 424{
425 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
426}
427
428static inline void
55d19799 429jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT		 430{
431 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
432}
433
fcf45b4c
GFT		 434static int
435jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 436{
437 struct jme_adapter *jme = netdev_priv(netdev);
dc4185bd 438 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 439 char linkmsg[64];
fcf45b4c 440 int rc = 0;
d7699f87 441
b3821cc5 442 linkmsg[0] = '\0';
cdcdc9eb 443
cd0ff491 444 if (jme->fpgaver)
cdcdc9eb
GFT		 445 phylink = jme_linkstat_from_phy(jme);
446 else
447 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 448
cd0ff491
GFT		 449 if (phylink & PHY_LINK_UP) {
450 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 451 /*
452 * If we did not enable AN
453 * Speed/Duplex Info should be obtained from SMI
454 */
455 phylink = PHY_LINK_UP;
456
457 bmcr = jme_mdio_read(jme->dev,
458 jme->mii_if.phy_id,
459 MII_BMCR);
460
461 phylink |= ((bmcr & BMCR_SPEED1000) &&
462 (bmcr & BMCR_SPEED100) == 0) ?
463 PHY_LINK_SPEED_1000M :
464 (bmcr & BMCR_SPEED100) ?
465 PHY_LINK_SPEED_100M :
466 PHY_LINK_SPEED_10M;
467
468 phylink |= (bmcr & BMCR_FULLDPLX) ?
469 PHY_LINK_DUPLEX : 0;
79ce639c 470
b3821cc5 471 strcat(linkmsg, "Forced: ");
cd0ff491 472 } else {
8c198884
GFT		 473 /*
474 * Keep polling for speed/duplex resolve complete
475 */
cd0ff491 476 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 477 --cnt) {
478
479 udelay(1);
8c198884 480
cd0ff491 481 if (jme->fpgaver)
cdcdc9eb
GFT		 482 phylink = jme_linkstat_from_phy(jme);
483 else
484 phylink = jread32(jme, JME_PHY_LINK);
8c198884 485 }
cd0ff491 486 if (!cnt)
937ef75a 487 pr_err("Waiting speed resolve timeout\n");
79ce639c 488
b3821cc5 489 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 490 }
491
cd0ff491 492 if (jme->phylink == phylink) {
fcf45b4c
GFT		 493 rc = 1;
494 goto out;
495 }
cd0ff491 496 if (testonly)
fcf45b4c
GFT		 497 goto out;
498
499 jme->phylink = phylink;
500
dc4185bd
GFT		 501 /*
502 * The speed/duplex setting of jme->reg_ghc already cleared
503 * by jme_reset_mac_processor()
504 */
cd0ff491
GFT		 505 switch (phylink & PHY_LINK_SPEED_MASK) {
506 case PHY_LINK_SPEED_10M:
dc4185bd 507 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 508 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 509 break;
510 case PHY_LINK_SPEED_100M:
dc4185bd 511 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 512 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 513 break;
514 case PHY_LINK_SPEED_1000M:
dc4185bd 515 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 516 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 517 break;
518 default:
519 break;
d7699f87 520 }
d7699f87 521
cd0ff491 522 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 523 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
809b2798 524 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
dc4185bd 525 jme->reg_ghc |= GHC_DPX;
cd0ff491 526 } else {
d7699f87 527 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 528 TXMCS_BACKOFF |
529 TXMCS_CARRIERSENSE |
530 TXMCS_COLLISION);
809b2798 531 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 532 }
7ee473a3 533
dc4185bd
GFT		 534 jwrite32(jme, JME_GHC, jme->reg_ghc);
535
7ee473a3 536 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
dc4185bd
GFT		 537 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
538 GPREG1_RSSPATCH);
7ee473a3 539 if (!(phylink & PHY_LINK_DUPLEX))
dc4185bd 540 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
7ee473a3
GFT		 541 switch (phylink & PHY_LINK_SPEED_MASK) {
542 case PHY_LINK_SPEED_10M:
55d19799 543 jme_set_phyfifo_8level(jme);
dc4185bd 544 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 545 break;
546 case PHY_LINK_SPEED_100M:
55d19799 547 jme_set_phyfifo_5level(jme);
dc4185bd 548 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 549 break;
550 case PHY_LINK_SPEED_1000M:
55d19799 551 jme_set_phyfifo_8level(jme);
7ee473a3
GFT		 552 break;
553 default:
554 break;
555 }
556 }
dc4185bd 557 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 558
3b70a6fa
GFT		 559 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
560 "Full-Duplex, " :
561 "Half-Duplex, ");
562 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
563 "MDI-X" :
564 "MDI");
937ef75a 565 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT		 566 netif_carrier_on(netdev);
567 } else {
568 if (testonly)
fcf45b4c
GFT		 569 goto out;
570
937ef75a 571 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 572 jme->phylink = 0;
cd0ff491 573 netif_carrier_off(netdev);
d7699f87 574 }
fcf45b4c
GFT		 575
576out:
577 return rc;
d7699f87
GFT		 578}
579
3bf61c55
GFT		 580static int
581jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 582{
d7699f87
GFT		 583 struct jme_ring *txring = &(jme->txring[0]);
584
585 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 586 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
587 &(txring->dmaalloc),
588 GFP_ATOMIC);
fcf45b4c 589
0ede469c
GFT		 590 if (!txring->alloc)
591 goto err_set_null;
d7699f87
GFT		 592
593 /*
594 * 16 Bytes align
595 */
cd0ff491 596 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 597 RING_DESC_ALIGN);
4330c2f2 598 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 599 txring->next_to_use = 0;
cdcdc9eb 600 atomic_set(&txring->next_to_clean, 0);
b3821cc5 601 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 602
0ede469c
GFT		 603 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
604 jme->tx_ring_size, GFP_ATOMIC);
605 if (unlikely(!(txring->bufinf)))
606 goto err_free_txring;
607
d7699f87 608 /*
b3821cc5 609 * Initialize Transmit Descriptors
d7699f87 610 */
b3821cc5 611 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 612 memset(txring->bufinf, 0,
b3821cc5 613 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 614
615 return 0;
0ede469c
GFT		 616
617err_free_txring:
618 dma_free_coherent(&(jme->pdev->dev),
619 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
620 txring->alloc,
621 txring->dmaalloc);
622
623err_set_null:
624 txring->desc = NULL;
625 txring->dmaalloc = 0;
626 txring->dma = 0;
627 txring->bufinf = NULL;
628
629 return -ENOMEM;
d7699f87
GFT		 630}
631
3bf61c55
GFT		 632static void
633jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 634{
635 int i;
636 struct jme_ring *txring = &(jme->txring[0]);
0ede469c 637 struct jme_buffer_info *txbi;
d7699f87 638
cd0ff491 639 if (txring->alloc) {
0ede469c
GFT		 640 if (txring->bufinf) {
641 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
642 txbi = txring->bufinf + i;
643 if (txbi->skb) {
644 dev_kfree_skb(txbi->skb);
645 txbi->skb = NULL;
646 }
647 txbi->mapping = 0;
648 txbi->len = 0;
649 txbi->nr_desc = 0;
650 txbi->start_xmit = 0;
d7699f87 651 }
0ede469c 652 kfree(txring->bufinf);
d7699f87
GFT		 653 }
654
655 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 656 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 657 txring->alloc,
658 txring->dmaalloc);
3bf61c55
GFT		 659
660 txring->alloc = NULL;
661 txring->desc = NULL;
662 txring->dmaalloc = 0;
663 txring->dma = 0;
0ede469c 664 txring->bufinf = NULL;
d7699f87 665 }
3bf61c55 666 txring->next_to_use = 0;
cdcdc9eb 667 atomic_set(&txring->next_to_clean, 0);
79ce639c 668 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 669}
670
cd0ff491 671static inline void
3bf61c55 672jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 673{
674 /*
675 * Select Queue 0
676 */
677 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 678 wmb();
d7699f87
GFT		 679
680 /*
681 * Setup TX Queue 0 DMA Bass Address
682 */
fcf45b4c 683 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 684 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 685 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 686
687 /*
688 * Setup TX Descptor Count
689 */
b3821cc5 690 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 691
692 /*
693 * Enable TX Engine
694 */
695 wmb();
dc4185bd 696 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT		 697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
d7699f87 699
dc4185bd
GFT		 700 /*
701 * Start clock for TX MAC Processor
702 */
703 jme_mac_txclk_on(jme);
d7699f87
GFT		 704}
705
cd0ff491 706static inline void
29bdd921
GFT		 707jme_restart_tx_engine(struct jme_adapter *jme)
708{
709 /*
710 * Restart TX Engine
711 */
712 jwrite32(jme, JME_TXCS, jme->reg_txcs |
713 TXCS_SELECT_QUEUE0 |
714 TXCS_ENABLE);
715}
716
cd0ff491 717static inline void
3bf61c55 718jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 719{
720 int i;
cd0ff491 721 u32 val;
d7699f87
GFT		 722
723 /*
724 * Disable TX Engine
725 */
fcf45b4c 726 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 727 wmb();
d7699f87
GFT		 728
729 val = jread32(jme, JME_TXCS);
cd0ff491 730 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 731 mdelay(1);
d7699f87 732 val = jread32(jme, JME_TXCS);
cd0ff491 733 rmb();
d7699f87
GFT		 734 }
735
cd0ff491 736 if (!i)
937ef75a 737 pr_err("Disable TX engine timeout\n");
dc4185bd
GFT		 738
739 /*
740 * Stop clock for TX MAC Processor
741 */
742 jme_mac_txclk_off(jme);
d7699f87
GFT		 743}
744
3bf61c55
GFT		 745static void
746jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 747{
0ede469c 748 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 749 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 750 struct jme_buffer_info *rxbi = rxring->bufinf;
751 rxdesc += i;
752 rxbi += i;
753
754 rxdesc->dw[0] = 0;
755 rxdesc->dw[1] = 0;
3bf61c55 756 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 757 rxdesc->desc1.bufaddrl = cpu_to_le32(
758 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 759 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 760 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 761 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 762 wmb();
3bf61c55 763 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 764}
765
3bf61c55
GFT		 766static int
767jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 768{
769 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 770 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 771 struct sk_buff *skb;
1eef180c 772 dma_addr_t mapping;
4330c2f2 773
79ce639c
GFT		 774 skb = netdev_alloc_skb(jme->dev,
775 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 776 if (unlikely(!skb))
4330c2f2 777 return -ENOMEM;
3b70a6fa
GFT		 778#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
779 skb->dev = jme->dev;
780#endif
3bf61c55 781
1eef180c
GFT		 782 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
783 offset_in_page(skb->data), skb_tailroom(skb),
784 PCI_DMA_FROMDEVICE);
785 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
786 dev_kfree_skb(skb);
787 return -ENOMEM;
788 }
789
790 if (likely(rxbi->mapping))
791 pci_unmap_page(jme->pdev, rxbi->mapping,
792 rxbi->len, PCI_DMA_FROMDEVICE);
793
4330c2f2 794 rxbi->skb = skb;
3bf61c55 795 rxbi->len = skb_tailroom(skb);
1eef180c 796 rxbi->mapping = mapping;
4330c2f2
GFT		 797 return 0;
798}
799
3bf61c55
GFT		 800static void
801jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 802{
803 struct jme_ring *rxring = &(jme->rxring[0]);
804 struct jme_buffer_info *rxbi = rxring->bufinf;
805 rxbi += i;
806
cd0ff491 807 if (rxbi->skb) {
b3821cc5 808 pci_unmap_page(jme->pdev,
4330c2f2 809 rxbi->mapping,
3bf61c55 810 rxbi->len,
4330c2f2
GFT		 811 PCI_DMA_FROMDEVICE);
812 dev_kfree_skb(rxbi->skb);
813 rxbi->skb = NULL;
814 rxbi->mapping = 0;
3bf61c55 815 rxbi->len = 0;
4330c2f2
GFT		 816 }
817}
818
3bf61c55
GFT		 819static void
820jme_free_rx_resources(struct jme_adapter *jme)
821{
822 int i;
823 struct jme_ring *rxring = &(jme->rxring[0]);
824
cd0ff491 825 if (rxring->alloc) {
0ede469c
GFT		 826 if (rxring->bufinf) {
827 for (i = 0 ; i < jme->rx_ring_size ; ++i)
828 jme_free_rx_buf(jme, i);
829 kfree(rxring->bufinf);
830 }
3bf61c55
GFT		 831
832 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 833 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 834 rxring->alloc,
835 rxring->dmaalloc);
836 rxring->alloc = NULL;
837 rxring->desc = NULL;
838 rxring->dmaalloc = 0;
839 rxring->dma = 0;
0ede469c 840 rxring->bufinf = NULL;
3bf61c55
GFT		 841 }
842 rxring->next_to_use = 0;
cdcdc9eb 843 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 844}
845
846static int
847jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 848{
849 int i;
850 struct jme_ring *rxring = &(jme->rxring[0]);
851
852 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 853 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
854 &(rxring->dmaalloc),
855 GFP_ATOMIC);
0ede469c
GFT		 856 if (!rxring->alloc)
857 goto err_set_null;
d7699f87
GFT		 858
859 /*
860 * 16 Bytes align
861 */
cd0ff491 862 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 863 RING_DESC_ALIGN);
4330c2f2 864 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 865 rxring->next_to_use = 0;
cdcdc9eb 866 atomic_set(&rxring->next_to_clean, 0);
d7699f87 867
0ede469c
GFT		 868 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
869 jme->rx_ring_size, GFP_ATOMIC);
870 if (unlikely(!(rxring->bufinf)))
871 goto err_free_rxring;
872
d7699f87
GFT		 873 /*
874 * Initiallize Receive Descriptors
875 */
0ede469c
GFT		 876 memset(rxring->bufinf, 0,
877 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 878 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
879 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 880 jme_free_rx_resources(jme);
881 return -ENOMEM;
882 }
d7699f87
GFT		 883
884 jme_set_clean_rxdesc(jme, i);
885 }
886
d7699f87 887 return 0;
0ede469c
GFT		 888
889err_free_rxring:
890 dma_free_coherent(&(jme->pdev->dev),
891 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
892 rxring->alloc,
893 rxring->dmaalloc);
894err_set_null:
895 rxring->desc = NULL;
896 rxring->dmaalloc = 0;
897 rxring->dma = 0;
898 rxring->bufinf = NULL;
899
900 return -ENOMEM;
d7699f87
GFT		 901}
902
cd0ff491 903static inline void
3bf61c55 904jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 905{
cd0ff491
GFT		 906 /*
907 * Select Queue 0
908 */
909 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
910 RXCS_QUEUESEL_Q0);
911 wmb();
912
d7699f87
GFT		 913 /*
914 * Setup RX DMA Bass Address
915 */
0ede469c 916 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 917 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
0ede469c 918 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 919
920 /*
b3821cc5 921 * Setup RX Descriptor Count
d7699f87 922 */
b3821cc5 923 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 924
3bf61c55 925 /*
d7699f87
GFT		 926 * Setup Unicast Filter
927 */
e523cd89 928 jme_set_unicastaddr(jme->dev);
d7699f87
GFT		 929 jme_set_multi(jme->dev);
930
931 /*
932 * Enable RX Engine
933 */
934 wmb();
dc4185bd 935 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 936 RXCS_QUEUESEL_Q0 |
937 RXCS_ENABLE |
938 RXCS_QST);
dc4185bd
GFT		 939
940 /*
941 * Start clock for RX MAC Processor
942 */
943 jme_mac_rxclk_on(jme);
d7699f87
GFT		 944}
945
cd0ff491 946static inline void
3bf61c55 947jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 948{
949 /*
3bf61c55 950 * Start RX Engine
4330c2f2 951 */
79ce639c 952 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 953 RXCS_QUEUESEL_Q0 |
954 RXCS_ENABLE |
955 RXCS_QST);
956}
957
cd0ff491 958static inline void
3bf61c55 959jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 960{
961 int i;
cd0ff491 962 u32 val;
d7699f87
GFT		 963
964 /*
965 * Disable RX Engine
966 */
29bdd921 967 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 968 wmb();
d7699f87
GFT		 969
970 val = jread32(jme, JME_RXCS);
cd0ff491 971 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 972 mdelay(1);
d7699f87 973 val = jread32(jme, JME_RXCS);
cd0ff491 974 rmb();
d7699f87
GFT		 975 }
976
cd0ff491 977 if (!i)
937ef75a 978 pr_err("Disable RX engine timeout\n");
d7699f87 979
dc4185bd
GFT		 980 /*
981 * Stop clock for RX MAC Processor
982 */
983 jme_mac_rxclk_off(jme);
d7699f87
GFT		 984}
985
93f698ca
GFT		 986static u16
987jme_udpsum(struct sk_buff *skb)
988{
989 u16 csum = 0xFFFFu;
65ff9ddf
GFT		 990#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
991 struct iphdr *iph;
992 int iphlen;
993 struct udphdr *udph;
994#endif
93f698ca
GFT		 995
996 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
997 return csum;
998 if (skb->protocol != htons(ETH_P_IP))
999 return csum;
65ff9ddf
GFT		 1000#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1001 iph = (struct iphdr *)skb_pull(skb, ETH_HLEN);
1002 iphlen = (iph->ihl << 2);
1003 if ((iph->protocol != IPPROTO_UDP) ||
1004 (skb->len < (iphlen + sizeof(struct udphdr)))) {
1005 skb_push(skb, ETH_HLEN);
1006 return csum;
1007 }
1008 udph = (struct udphdr *)skb_pull(skb, iphlen);
1009 csum = udph->check;
1010 skb_push(skb, iphlen);
1011 skb_push(skb, ETH_HLEN);
1012#else
93f698ca
GFT		 1013 skb_set_network_header(skb, ETH_HLEN);
1014 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
1015 (skb->len < (ETH_HLEN +
1016 (ip_hdr(skb)->ihl << 2) +
1017 sizeof(struct udphdr)))) {
1018 skb_reset_network_header(skb);
1019 return csum;
1020 }
1021 skb_set_transport_header(skb,
1022 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
1023 csum = udp_hdr(skb)->check;
1024 skb_reset_transport_header(skb);
1025 skb_reset_network_header(skb);
65ff9ddf 1026#endif
93f698ca
GFT		 1027
1028 return csum;
1029}
1030
192570e0 1031static int
93f698ca 1032jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
192570e0 1033{
cd0ff491 1034 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 1035 return false;
1036
0ede469c
GFT		 1037 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1038 == RXWBFLAG_TCPON)) {
1039 if (flags & RXWBFLAG_IPV4)
7ca9ebee 1040 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
0ede469c 1041 return false;
192570e0
GFT		 1042 }
1043
0ede469c 1044 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
93f698ca 1045 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
0ede469c 1046 if (flags & RXWBFLAG_IPV4)
937ef75a 1047 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
0ede469c 1048 return false;
192570e0
GFT		 1049 }
1050
0ede469c
GFT		 1051 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1052 == RXWBFLAG_IPV4)) {
937ef75a 1053 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
0ede469c 1054 return false;
192570e0
GFT		 1055 }
1056
1057 return true;
1058}
1059
3bf61c55 1060static void
42b1055e 1061jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 1062{
d7699f87 1063 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1064 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 1065 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 1066 struct sk_buff *skb;
3bf61c55 1067 int framesize;
d7699f87 1068
3bf61c55
GFT		 1069 rxdesc += idx;
1070 rxbi += idx;
d7699f87 1071
3bf61c55
GFT		 1072 skb = rxbi->skb;
1073 pci_dma_sync_single_for_cpu(jme->pdev,
1074 rxbi->mapping,
1075 rxbi->len,
1076 PCI_DMA_FROMDEVICE);
1077
cd0ff491 1078 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 1079 pci_dma_sync_single_for_device(jme->pdev,
1080 rxbi->mapping,
1081 rxbi->len,
1082 PCI_DMA_FROMDEVICE);
1083
1084 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1085 } else {
3bf61c55
GFT		 1086 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1087 - RX_PREPAD_SIZE;
1088
1089 skb_reserve(skb, RX_PREPAD_SIZE);
1090 skb_put(skb, framesize);
1091 skb->protocol = eth_type_trans(skb, jme->dev);
1092
93f698ca 1093 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
8c198884 1094 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1095 else
614c0bfd 1096#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
29bdd921 1097 skb->ip_summed = CHECKSUM_NONE;
08f5fcfa
ED		 1098#else
1099 skb_checksum_none_assert(skb);
1100#endif
8c198884 1101
3b70a6fa 1102 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 1103 if (jme->vlgrp) {
cdcdc9eb 1104 jme->jme_vlan_rx(skb, jme->vlgrp,
3b70a6fa 1105 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 1106 NET_STAT(jme).rx_bytes += 4;
7ca9ebee 1107 } else {
7ca9ebee 1108 dev_kfree_skb(skb);
b3821cc5 1109 }
cd0ff491 1110 } else {
cdcdc9eb 1111 jme->jme_rx(skb);
b3821cc5 1112 }
3bf61c55 1113
3b70a6fa
GFT		 1114 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1115 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 1116 ++(NET_STAT(jme).multicast);
1117
3bf61c55
GFT		 1118 NET_STAT(jme).rx_bytes += framesize;
1119 ++(NET_STAT(jme).rx_packets);
1120 }
1121
1122 jme_set_clean_rxdesc(jme, idx);
1123
1124}
1125
1126static int
1127jme_process_receive(struct jme_adapter *jme, int limit)
1128{
1129 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1130 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1131 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1132
cd0ff491 1133 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 1134 goto out_inc;
1135
cd0ff491 1136 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 1137 goto out_inc;
1138
cd0ff491 1139 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 1140 goto out_inc;
1141
cdcdc9eb 1142 i = atomic_read(&rxring->next_to_clean);
0ede469c 1143 while (limit > 0) {
3bf61c55
GFT		 1144 rxdesc = rxring->desc;
1145 rxdesc += i;
1146
3b70a6fa 1147 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 1148 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1149 goto out;
0ede469c 1150 --limit;
d7699f87 1151
9134abda 1152 rmb();
4330c2f2
GFT		 1153 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1154
cd0ff491 1155 if (unlikely(desccnt > 1 ||
192570e0 1156 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1157
cd0ff491 1158 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1159 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1160 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1161 ++(NET_STAT(jme).rx_fifo_errors);
1162 else
1163 ++(NET_STAT(jme).rx_errors);
4330c2f2 1164
cd0ff491 1165 if (desccnt > 1)
3bf61c55 1166 limit -= desccnt - 1;
4330c2f2 1167
cd0ff491 1168 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1169 jme_set_clean_rxdesc(jme, j);
b3821cc5 1170 j = (j + 1) & (mask);
4330c2f2 1171 }
3bf61c55 1172
cd0ff491 1173 } else {
42b1055e 1174 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1175 }
4330c2f2 1176
b3821cc5 1177 i = (i + desccnt) & (mask);
3bf61c55 1178 }
4330c2f2 1179
3bf61c55 1180out:
cdcdc9eb 1181 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1182
192570e0
GFT		 1183out_inc:
1184 atomic_inc(&jme->rx_cleaning);
1185
3bf61c55 1186 return limit > 0 ? limit : 0;
4330c2f2 1187
3bf61c55 1188}
d7699f87 1189
79ce639c
GFT		 1190static void
1191jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1192{
cd0ff491 1193 if (likely(atmp == dpi->cur)) {
192570e0 1194 dpi->cnt = 0;
79ce639c 1195 return;
192570e0 1196 }
79ce639c 1197
cd0ff491 1198 if (dpi->attempt == atmp) {
79ce639c 1199 ++(dpi->cnt);
cd0ff491 1200 } else {
79ce639c
GFT		 1201 dpi->attempt = atmp;
1202 dpi->cnt = 0;
1203 }
1204
1205}
1206
1207static void
1208jme_dynamic_pcc(struct jme_adapter *jme)
1209{
1210 register struct dynpcc_info *dpi = &(jme->dpi);
1211
cd0ff491 1212 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1213 jme_attempt_pcc(dpi, PCC_P3);
7ca9ebee
GFT		 1214 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1215 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT		 1216 jme_attempt_pcc(dpi, PCC_P2);
1217 else
1218 jme_attempt_pcc(dpi, PCC_P1);
1219
cd0ff491
GFT		 1220 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1221 if (dpi->attempt < dpi->cur)
1222 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1223 jme_set_rx_pcc(jme, dpi->attempt);
1224 dpi->cur = dpi->attempt;
1225 dpi->cnt = 0;
1226 }
1227}
1228
1229static void
1230jme_start_pcc_timer(struct jme_adapter *jme)
1231{
1232 struct dynpcc_info *dpi = &(jme->dpi);
1233 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1234 dpi->last_pkts = NET_STAT(jme).rx_packets;
1235 dpi->intr_cnt = 0;
1236 jwrite32(jme, JME_TMCSR,
1237 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1238}
1239
cd0ff491 1240static inline void
29bdd921
GFT		 1241jme_stop_pcc_timer(struct jme_adapter *jme)
1242{
1243 jwrite32(jme, JME_TMCSR, 0);
1244}
1245
cd0ff491
GFT		 1246static void
1247jme_shutdown_nic(struct jme_adapter *jme)
1248{
1249 u32 phylink;
1250
1251 phylink = jme_linkstat_from_phy(jme);
1252
1253 if (!(phylink & PHY_LINK_UP)) {
1254 /*
1255 * Disable all interrupt before issue timer
1256 */
1257 jme_stop_irq(jme);
1258 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1259 }
1260}
1261
79ce639c
GFT		 1262static void
1263jme_pcc_tasklet(unsigned long arg)
1264{
cd0ff491 1265 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1266 struct net_device *netdev = jme->dev;
1267
cd0ff491
GFT		 1268 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1269 jme_shutdown_nic(jme);
1270 return;
1271 }
29bdd921 1272
cd0ff491 1273 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1274 (atomic_read(&jme->link_changing) != 1)
1275 )) {
1276 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1277 return;
1278 }
29bdd921 1279
cd0ff491 1280 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1281 jme_dynamic_pcc(jme);
1282
79ce639c
GFT		 1283 jme_start_pcc_timer(jme);
1284}
1285
cd0ff491 1286static inline void
192570e0
GFT		 1287jme_polling_mode(struct jme_adapter *jme)
1288{
1289 jme_set_rx_pcc(jme, PCC_OFF);
1290}
1291
cd0ff491 1292static inline void
192570e0
GFT		 1293jme_interrupt_mode(struct jme_adapter *jme)
1294{
1295 jme_set_rx_pcc(jme, PCC_P1);
1296}
1297
cd0ff491
GFT		 1298static inline int
1299jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1300{
1301 u32 apmc;
1302 apmc = jread32(jme, JME_APMC);
1303 return apmc & JME_APMC_PSEUDO_HP_EN;
1304}
1305
1306static void
1307jme_start_shutdown_timer(struct jme_adapter *jme)
1308{
1309 u32 apmc;
1310
1311 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1312 apmc &= ~JME_APMC_EPIEN_CTRL;
1313 if (!no_extplug) {
1314 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1315 wmb();
1316 }
1317 jwrite32f(jme, JME_APMC, apmc);
1318
1319 jwrite32f(jme, JME_TIMER2, 0);
1320 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1321 jwrite32(jme, JME_TMCSR,
1322 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1323}
1324
1325static void
1326jme_stop_shutdown_timer(struct jme_adapter *jme)
1327{
1328 u32 apmc;
1329
1330 jwrite32f(jme, JME_TMCSR, 0);
1331 jwrite32f(jme, JME_TIMER2, 0);
1332 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1333
1334 apmc = jread32(jme, JME_APMC);
1335 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1336 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1337 wmb();
1338 jwrite32f(jme, JME_APMC, apmc);
1339}
1340
3bf61c55
GFT		 1341static void
1342jme_link_change_tasklet(unsigned long arg)
1343{
cd0ff491 1344 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1345 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1346 int rc;
1347
cd0ff491
GFT		 1348 while (!atomic_dec_and_test(&jme->link_changing)) {
1349 atomic_inc(&jme->link_changing);
937ef75a 1350 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
58c92f28 1351 while (atomic_read(&jme->link_changing) != 1)
937ef75a 1352 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1353 }
fcf45b4c 1354
cd0ff491 1355 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1356 goto out;
1357
29bdd921 1358 jme->old_mtu = netdev->mtu;
fcf45b4c 1359 netif_stop_queue(netdev);
cd0ff491
GFT		 1360 if (jme_pseudo_hotplug_enabled(jme))
1361 jme_stop_shutdown_timer(jme);
1362
1363 jme_stop_pcc_timer(jme);
1364 tasklet_disable(&jme->txclean_task);
1365 tasklet_disable(&jme->rxclean_task);
1366 tasklet_disable(&jme->rxempty_task);
1367
1368 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT		 1369 jme_disable_rx_engine(jme);
1370 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1371 jme_reset_mac_processor(jme);
1372 jme_free_rx_resources(jme);
1373 jme_free_tx_resources(jme);
192570e0 1374
cd0ff491 1375 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1376 jme_polling_mode(jme);
cd0ff491
GFT		 1377
1378 netif_carrier_off(netdev);
fcf45b4c
GFT		 1379 }
1380
1381 jme_check_link(netdev, 0);
cd0ff491 1382 if (netif_carrier_ok(netdev)) {
fcf45b4c 1383 rc = jme_setup_rx_resources(jme);
cd0ff491 1384 if (rc) {
937ef75a 1385 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1386 goto out_enable_tasklet;
fcf45b4c
GFT		 1387 }
1388
fcf45b4c 1389 rc = jme_setup_tx_resources(jme);
cd0ff491 1390 if (rc) {
937ef75a 1391 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT		 1392 goto err_out_free_rx_resources;
1393 }
1394
1395 jme_enable_rx_engine(jme);
1396 jme_enable_tx_engine(jme);
1397
1398 netif_start_queue(netdev);
192570e0 1399
cd0ff491 1400 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1401 jme_interrupt_mode(jme);
192570e0 1402
79ce639c 1403 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1404 } else if (jme_pseudo_hotplug_enabled(jme)) {
1405 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1406 }
1407
cd0ff491 1408 goto out_enable_tasklet;
fcf45b4c
GFT		 1409
1410err_out_free_rx_resources:
1411 jme_free_rx_resources(jme);
cd0ff491
GFT		 1412out_enable_tasklet:
1413 tasklet_enable(&jme->txclean_task);
1414 tasklet_hi_enable(&jme->rxclean_task);
1415 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1416out:
1417 atomic_inc(&jme->link_changing);
3bf61c55 1418}
d7699f87 1419
3bf61c55
GFT		 1420static void
1421jme_rx_clean_tasklet(unsigned long arg)
1422{
cd0ff491 1423 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1424 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1425
192570e0
GFT		 1426 jme_process_receive(jme, jme->rx_ring_size);
1427 ++(dpi->intr_cnt);
42b1055e 1428
192570e0 1429}
fcf45b4c 1430
192570e0 1431static int
cdcdc9eb 1432jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1433{
cdcdc9eb 1434 struct jme_adapter *jme = jme_napi_priv(holder);
3b70a6fa 1435 DECLARE_NETDEV
192570e0 1436 int rest;
fcf45b4c 1437
cdcdc9eb 1438 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1439
cd0ff491 1440 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1441 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1442 ++(NET_STAT(jme).rx_dropped);
1443 jme_restart_rx_engine(jme);
1444 }
1445 atomic_inc(&jme->rx_empty);
1446
cd0ff491 1447 if (rest) {
cdcdc9eb 1448 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1449 jme_interrupt_mode(jme);
1450 }
1451
cdcdc9eb
GFT		 1452 JME_NAPI_WEIGHT_SET(budget, rest);
1453 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1454}
1455
1456static void
1457jme_rx_empty_tasklet(unsigned long arg)
1458{
cd0ff491 1459 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1460
cd0ff491 1461 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1462 return;
1463
cd0ff491 1464 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1465 return;
1466
7ca9ebee 1467 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1468
fcf45b4c 1469 jme_rx_clean_tasklet(arg);
cdcdc9eb 1470
cd0ff491 1471 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1472 atomic_dec(&jme->rx_empty);
1473 ++(NET_STAT(jme).rx_dropped);
1474 jme_restart_rx_engine(jme);
1475 }
1476 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1477}
1478
b3821cc5
GFT		 1479static void
1480jme_wake_queue_if_stopped(struct jme_adapter *jme)
1481{
0ede469c 1482 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1483
1484 smp_wmb();
cd0ff491 1485 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1486 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
937ef75a 1487 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1488 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1489 }
1490
1491}
1492
3bf61c55
GFT		 1493static void
1494jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1495{
cd0ff491 1496 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1497 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1498 struct txdesc *txdesc = txring->desc;
3bf61c55 1499 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1500 int i, j, cnt = 0, max, err, mask;
3bf61c55 1501
937ef75a 1502 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT		 1503
1504 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1505 goto out;
1506
cd0ff491 1507 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1508 goto out;
1509
cd0ff491 1510 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1511 goto out;
1512
b3821cc5
GFT		 1513 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1514 mask = jme->tx_ring_mask;
3bf61c55 1515
cd0ff491 1516 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1517
1518 ctxbi = txbi + i;
1519
cd0ff491 1520 if (likely(ctxbi->skb &&
b3821cc5 1521 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1522
cd0ff491 1523 tx_dbg(jme, "txclean: %d+%d@%lu\n",
937ef75a 1524 i, ctxbi->nr_desc, jiffies);
3bf61c55 1525
cd0ff491 1526 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1527
cd0ff491 1528 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1529 ttxbi = txbi + ((i + j) & (mask));
1530 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1531
b3821cc5 1532 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1533 ttxbi->mapping,
1534 ttxbi->len,
1535 PCI_DMA_TODEVICE);
1536
3bf61c55
GFT		 1537 ttxbi->mapping = 0;
1538 ttxbi->len = 0;
1539 }
1540
1541 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1542
1543 cnt += ctxbi->nr_desc;
1544
cd0ff491 1545 if (unlikely(err)) {
8c198884 1546 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1547 } else {
8c198884 1548 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1549 NET_STAT(jme).tx_bytes += ctxbi->len;
1550 }
1551
1552 ctxbi->skb = NULL;
1553 ctxbi->len = 0;
cdcdc9eb 1554 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1555
1556 } else {
3bf61c55
GFT		 1557 break;
1558 }
1559
b3821cc5 1560 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1561
1562 ctxbi->nr_desc = 0;
d7699f87
GFT		 1563 }
1564
937ef75a 1565 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1566 atomic_set(&txring->next_to_clean, i);
79ce639c 1567 atomic_add(cnt, &txring->nr_free);
3bf61c55 1568
b3821cc5
GFT		 1569 jme_wake_queue_if_stopped(jme);
1570
fcf45b4c
GFT		 1571out:
1572 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1573}
1574
79ce639c 1575static void
cd0ff491 1576jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1577{
3bf61c55
GFT		 1578 /*
1579 * Disable interrupt
1580 */
1581 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1582
cd0ff491 1583 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1584 /*
1585 * Link change event is critical
1586 * all other events are ignored
1587 */
1588 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1589 tasklet_schedule(&jme->linkch_task);
29bdd921 1590 goto out_reenable;
fcf45b4c 1591 }
d7699f87 1592
cd0ff491 1593 if (intrstat & INTR_TMINTR) {
47220951 1594 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1595 tasklet_schedule(&jme->pcc_task);
47220951 1596 }
79ce639c 1597
cd0ff491 1598 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1599 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1600 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1601 }
1602
cd0ff491 1603 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1604 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1605 INTR_PCCRX0 |
1606 INTR_RX0EMP)) |
1607 INTR_RX0);
1608 }
d7699f87 1609
cd0ff491
GFT		 1610 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1611 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1612 atomic_inc(&jme->rx_empty);
1613
cd0ff491
GFT		 1614 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1615 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1616 jme_polling_mode(jme);
cdcdc9eb 1617 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1618 }
1619 }
cd0ff491
GFT		 1620 } else {
1621 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1622 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1623 tasklet_hi_schedule(&jme->rxempty_task);
1624 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1625 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1626 }
4330c2f2 1627 }
d7699f87 1628
29bdd921 1629out_reenable:
3bf61c55 1630 /*
fcf45b4c 1631 * Re-enable interrupt
3bf61c55 1632 */
fcf45b4c 1633 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1634}
1635
3b70a6fa
GFT		 1636#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1637static irqreturn_t
1638jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1639#else
79ce639c
GFT		 1640static irqreturn_t
1641jme_intr(int irq, void *dev_id)
3b70a6fa 1642#endif
79ce639c 1643{
cd0ff491
GFT		 1644 struct net_device *netdev = dev_id;
1645 struct jme_adapter *jme = netdev_priv(netdev);
1646 u32 intrstat;
79ce639c
GFT		 1647
1648 intrstat = jread32(jme, JME_IEVE);
1649
1650 /*
1651 * Check if it's really an interrupt for us
1652 */
7ee473a3 1653 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1654 return IRQ_NONE;
79ce639c
GFT		 1655
1656 /*
1657 * Check if the device still exist
1658 */
cd0ff491
GFT		 1659 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1660 return IRQ_NONE;
79ce639c
GFT		 1661
1662 jme_intr_msi(jme, intrstat);
1663
cd0ff491 1664 return IRQ_HANDLED;
d7699f87
GFT		 1665}
1666
3b70a6fa
GFT		 1667#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1668static irqreturn_t
1669jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1670#else
79ce639c
GFT		 1671static irqreturn_t
1672jme_msi(int irq, void *dev_id)
3b70a6fa 1673#endif
79ce639c 1674{
cd0ff491
GFT		 1675 struct net_device *netdev = dev_id;
1676 struct jme_adapter *jme = netdev_priv(netdev);
1677 u32 intrstat;
79ce639c 1678
0ede469c 1679 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1680
1681 jme_intr_msi(jme, intrstat);
1682
cd0ff491 1683 return IRQ_HANDLED;
79ce639c
GFT		 1684}
1685
79ce639c
GFT		 1686static void
1687jme_reset_link(struct jme_adapter *jme)
1688{
1689 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1690}
1691
fcf45b4c
GFT		 1692static void
1693jme_restart_an(struct jme_adapter *jme)
1694{
cd0ff491 1695 u32 bmcr;
fcf45b4c 1696
cd0ff491 1697 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1698 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1699 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1700 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1701 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1702}
1703
1704static int
1705jme_request_irq(struct jme_adapter *jme)
1706{
1707 int rc;
cd0ff491 1708 struct net_device *netdev = jme->dev;
3b70a6fa
GFT		 1709#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1710 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1711 int irq_flags = SA_SHIRQ;
1712#else
cd0ff491
GFT		 1713 irq_handler_t handler = jme_intr;
1714 int irq_flags = IRQF_SHARED;
3b70a6fa 1715#endif
cd0ff491
GFT		 1716
1717 if (!pci_enable_msi(jme->pdev)) {
1718 set_bit(JME_FLAG_MSI, &jme->flags);
1719 handler = jme_msi;
1720 irq_flags = 0;
1721 }
1722
1723 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1724 netdev);
1725 if (rc) {
937ef75a
JP		 1726 netdev_err(netdev,
1727 "Unable to request %s interrupt (return: %d)\n",
1728 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1729 rc);
79ce639c 1730
cd0ff491
GFT		 1731 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1732 pci_disable_msi(jme->pdev);
1733 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1734 }
cd0ff491 1735 } else {
79ce639c
GFT		 1736 netdev->irq = jme->pdev->irq;
1737 }
1738
cd0ff491 1739 return rc;
79ce639c
GFT		 1740}
1741
1742static void
1743jme_free_irq(struct jme_adapter *jme)
1744{
cd0ff491
GFT		 1745 free_irq(jme->pdev->irq, jme->dev);
1746 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1747 pci_disable_msi(jme->pdev);
1748 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1749 jme->dev->irq = jme->pdev->irq;
cd0ff491 1750 }
fcf45b4c
GFT		 1751}
1752
ed457bcc
GFT		 1753static inline void
1754jme_new_phy_on(struct jme_adapter *jme)
1755{
1756 u32 reg;
1757
1758 reg = jread32(jme, JME_PHY_PWR);
1759 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1760 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1761 jwrite32(jme, JME_PHY_PWR, reg);
1762
1763 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1764 reg &= ~PE1_GPREG0_PBG;
1765 reg |= PE1_GPREG0_ENBG;
1766 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1767}
1768
1769static inline void
1770jme_new_phy_off(struct jme_adapter *jme)
1771{
1772 u32 reg;
1773
1774 reg = jread32(jme, JME_PHY_PWR);
1775 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1776 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1777 jwrite32(jme, JME_PHY_PWR, reg);
1778
1779 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1780 reg &= ~PE1_GPREG0_PBG;
1781 reg |= PE1_GPREG0_PDD3COLD;
1782 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1783}
1784
e58b908e
GFT		 1785static inline void
1786jme_phy_on(struct jme_adapter *jme)
1787{
1788 u32 bmcr;
1789
1790 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1791 bmcr &= ~BMCR_PDOWN;
1792 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
ed457bcc
GFT		 1793
1794 if (new_phy_power_ctrl(jme->chip_main_rev))
1795 jme_new_phy_on(jme);
1796}
1797
1798static inline void
1799jme_phy_off(struct jme_adapter *jme)
1800{
1801 u32 bmcr;
1802
1803 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1804 bmcr |= BMCR_PDOWN;
1805 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1806
1807 if (new_phy_power_ctrl(jme->chip_main_rev))
1808 jme_new_phy_off(jme);
e58b908e
GFT		 1809}
1810
3bf61c55
GFT		 1811static int
1812jme_open(struct net_device *netdev)
d7699f87
GFT		 1813{
1814 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1815 int rc;
79ce639c 1816
42b1055e 1817 jme_clear_pm(jme);
cdcdc9eb 1818 JME_NAPI_ENABLE(jme);
d7699f87 1819
0ede469c 1820 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1821 tasklet_enable(&jme->txclean_task);
1822 tasklet_hi_enable(&jme->rxclean_task);
1823 tasklet_hi_enable(&jme->rxempty_task);
1824
79ce639c 1825 rc = jme_request_irq(jme);
cd0ff491 1826 if (rc)
4330c2f2 1827 goto err_out;
79ce639c 1828
d7699f87 1829 jme_start_irq(jme);
42b1055e 1830
ed457bcc
GFT		 1831 jme_phy_on(jme);
1832 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1833 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 1834 else
42b1055e
GFT		 1835 jme_reset_phy_processor(jme);
1836
29bdd921 1837 jme_reset_link(jme);
d7699f87
GFT		 1838
1839 return 0;
1840
d7699f87
GFT		 1841err_out:
1842 netif_stop_queue(netdev);
1843 netif_carrier_off(netdev);
4330c2f2 1844 return rc;
d7699f87
GFT		 1845}
1846
42b1055e
GFT		 1847static void
1848jme_set_100m_half(struct jme_adapter *jme)
1849{
cd0ff491 1850 u32 bmcr, tmp;
42b1055e 1851
a82e368c 1852 jme_phy_on(jme);
42b1055e
GFT		 1853 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1854 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1855 BMCR_SPEED1000 | BMCR_FULLDPLX);
1856 tmp |= BMCR_SPEED100;
1857
1858 if (bmcr != tmp)
1859 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1860
cd0ff491 1861 if (jme->fpgaver)
cdcdc9eb
GFT		 1862 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1863 else
1864 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1865}
1866
47220951
GFT		 1867#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1868static void
1869jme_wait_link(struct jme_adapter *jme)
1870{
cd0ff491 1871 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1872
1873 mdelay(1000);
1874 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1875 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1876 mdelay(10);
1877 phylink = jme_linkstat_from_phy(jme);
1878 }
1879}
1880
a82e368c
GFT		 1881static void
1882jme_powersave_phy(struct jme_adapter *jme)
1883{
1884 if (jme->reg_pmcs) {
1885 jme_set_100m_half(jme);
a82e368c
GFT		 1886 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1887 jme_wait_link(jme);
61891ee4 1888 jme_clear_pm(jme);
a82e368c
GFT		 1889 } else {
1890 jme_phy_off(jme);
1891 }
1892}
1893
3bf61c55
GFT		 1894static int
1895jme_close(struct net_device *netdev)
d7699f87
GFT		 1896{
1897 struct jme_adapter *jme = netdev_priv(netdev);
1898
1899 netif_stop_queue(netdev);
1900 netif_carrier_off(netdev);
1901
1902 jme_stop_irq(jme);
79ce639c 1903 jme_free_irq(jme);
d7699f87 1904
cdcdc9eb 1905 JME_NAPI_DISABLE(jme);
192570e0 1906
0ede469c
GFT		 1907 tasklet_disable(&jme->linkch_task);
1908 tasklet_disable(&jme->txclean_task);
1909 tasklet_disable(&jme->rxclean_task);
1910 tasklet_disable(&jme->rxempty_task);
8c198884 1911
cd0ff491
GFT		 1912 jme_disable_rx_engine(jme);
1913 jme_disable_tx_engine(jme);
8c198884 1914 jme_reset_mac_processor(jme);
d7699f87
GFT		 1915 jme_free_rx_resources(jme);
1916 jme_free_tx_resources(jme);
42b1055e 1917 jme->phylink = 0;
b3821cc5
GFT		 1918 jme_phy_off(jme);
1919
1920 return 0;
1921}
1922
1923static int
1924jme_alloc_txdesc(struct jme_adapter *jme,
1925 struct sk_buff *skb)
1926{
0ede469c 1927 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1928 int idx, nr_alloc, mask = jme->tx_ring_mask;
1929
1930 idx = txring->next_to_use;
1931 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1932
cd0ff491 1933 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 1934 return -1;
1935
1936 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1937
b3821cc5
GFT		 1938 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1939
1940 return idx;
1941}
1942
1943static void
1944jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1945 struct txdesc *txdesc,
b3821cc5
GFT		 1946 struct jme_buffer_info *txbi,
1947 struct page *page,
cd0ff491
GFT		 1948 u32 page_offset,
1949 u32 len,
1950 u8 hidma)
b3821cc5
GFT		 1951{
1952 dma_addr_t dmaaddr;
1953
1954 dmaaddr = pci_map_page(pdev,
1955 page,
1956 page_offset,
1957 len,
1958 PCI_DMA_TODEVICE);
1959
1960 pci_dma_sync_single_for_device(pdev,
1961 dmaaddr,
1962 len,
1963 PCI_DMA_TODEVICE);
1964
1965 txdesc->dw[0] = 0;
1966 txdesc->dw[1] = 0;
1967 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1968 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 1969 txdesc->desc2.datalen = cpu_to_le16(len);
1970 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1971 txdesc->desc2.bufaddrl = cpu_to_le32(
1972 (__u64)dmaaddr & 0xFFFFFFFFUL);
1973
1974 txbi->mapping = dmaaddr;
1975 txbi->len = len;
1976}
1977
1978static void
1979jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1980{
0ede469c 1981 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1982 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1983 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1984 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT		 1985 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1986 int mask = jme->tx_ring_mask;
1987 struct skb_frag_struct *frag;
cd0ff491 1988 u32 len;
b3821cc5 1989
cd0ff491
GFT		 1990 for (i = 0 ; i < nr_frags ; ++i) {
1991 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 1992 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1993 ctxbi = txbi + ((idx + i + 2) & (mask));
1994
1995 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1996 frag->page_offset, frag->size, hidma);
42b1055e 1997 }
b3821cc5 1998
cd0ff491 1999 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 2000 ctxdesc = txdesc + ((idx + 1) & (mask));
2001 ctxbi = txbi + ((idx + 1) & (mask));
2002 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2003 offset_in_page(skb->data), len, hidma);
2004
2005}
2006
2007static int
2008jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2009{
3b70a6fa 2010 if (unlikely(
0ede469c 2011#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 2012 skb_shinfo(skb)->tso_size
2013#else
2014 skb_shinfo(skb)->gso_size
2015#endif
2016 && skb_header_cloned(skb) &&
b3821cc5
GFT		 2017 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2018 dev_kfree_skb(skb);
2019 return -1;
2020 }
2021
2022 return 0;
2023}
2024
2025static int
3b70a6fa 2026jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 2027{
0ede469c 2028#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 2029 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2030#else
2031 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2032#endif
cd0ff491 2033 if (*mss) {
b3821cc5
GFT		 2034 *flags |= TXFLAG_LSEN;
2035
cd0ff491 2036 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 2037 struct iphdr *iph = ip_hdr(skb);
2038
2039 iph->check = 0;
cd0ff491 2040 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 2041 iph->daddr, 0,
2042 IPPROTO_TCP,
2043 0);
cd0ff491 2044 } else {
b3821cc5
GFT		 2045 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2046
cd0ff491 2047 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 2048 &ip6h->daddr, 0,
2049 IPPROTO_TCP,
2050 0);
2051 }
2052
2053 return 0;
2054 }
2055
2056 return 1;
2057}
2058
2059static void
cd0ff491 2060jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 2061{
3b70a6fa
GFT		 2062#ifdef CHECKSUM_PARTIAL
2063 if (skb->ip_summed == CHECKSUM_PARTIAL)
2064#else
2065 if (skb->ip_summed == CHECKSUM_HW)
2066#endif
2067 {
cd0ff491 2068 u8 ip_proto;
b3821cc5 2069
3b70a6fa
GFT		 2070#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2071 if (skb->protocol == htons(ETH_P_IP))
2072 ip_proto = ip_hdr(skb)->protocol;
2073 else if (skb->protocol == htons(ETH_P_IPV6))
2074 ip_proto = ipv6_hdr(skb)->nexthdr;
2075 else
2076 ip_proto = 0;
2077#else
b3821cc5 2078 switch (skb->protocol) {
cd0ff491 2079 case htons(ETH_P_IP):
b3821cc5
GFT		 2080 ip_proto = ip_hdr(skb)->protocol;
2081 break;
cd0ff491 2082 case htons(ETH_P_IPV6):
b3821cc5
GFT		 2083 ip_proto = ipv6_hdr(skb)->nexthdr;
2084 break;
2085 default:
2086 ip_proto = 0;
2087 break;
2088 }
3b70a6fa 2089#endif
b3821cc5 2090
cd0ff491 2091 switch (ip_proto) {
b3821cc5
GFT		 2092 case IPPROTO_TCP:
2093 *flags |= TXFLAG_TCPCS;
2094 break;
2095 case IPPROTO_UDP:
2096 *flags |= TXFLAG_UDPCS;
2097 break;
2098 default:
937ef75a 2099 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT		 2100 break;
2101 }
2102 }
2103}
2104
cd0ff491 2105static inline void
3b70a6fa 2106jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2107{
cd0ff491 2108 if (vlan_tx_tag_present(skb)) {
b3821cc5 2109 *flags |= TXFLAG_TAGON;
3b70a6fa 2110 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2111 }
b3821cc5
GFT		 2112}
2113
2114static int
3b70a6fa 2115jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2116{
0ede469c 2117 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2118 struct txdesc *txdesc;
b3821cc5 2119 struct jme_buffer_info *txbi;
cd0ff491 2120 u8 flags;
b3821cc5 2121
cd0ff491 2122 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 2123 txbi = txring->bufinf + idx;
2124
2125 txdesc->dw[0] = 0;
2126 txdesc->dw[1] = 0;
2127 txdesc->dw[2] = 0;
2128 txdesc->dw[3] = 0;
2129 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2130 /*
2131 * Set OWN bit at final.
2132 * When kernel transmit faster than NIC.
2133 * And NIC trying to send this descriptor before we tell
2134 * it to start sending this TX queue.
2135 * Other fields are already filled correctly.
2136 */
2137 wmb();
2138 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 2139 /*
2140 * Set checksum flags while not tso
2141 */
2142 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2143 jme_tx_csum(jme, skb, &flags);
b3821cc5 2144 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
3b70a6fa 2145 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 2146 txdesc->desc1.flags = flags;
2147 /*
2148 * Set tx buffer info after telling NIC to send
2149 * For better tx_clean timing
2150 */
2151 wmb();
2152 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2153 txbi->skb = skb;
2154 txbi->len = skb->len;
cd0ff491
GFT		 2155 txbi->start_xmit = jiffies;
2156 if (!txbi->start_xmit)
8d27293f 2157 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 2158
2159 return 0;
2160}
2161
b3821cc5
GFT		 2162static void
2163jme_stop_queue_if_full(struct jme_adapter *jme)
2164{
0ede469c 2165 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 2166 struct jme_buffer_info *txbi = txring->bufinf;
2167 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2168
cd0ff491 2169 txbi += idx;
b3821cc5
GFT		 2170
2171 smp_wmb();
cd0ff491 2172 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2173 netif_stop_queue(jme->dev);
937ef75a 2174 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2175 smp_wmb();
cd0ff491
GFT		 2176 if (atomic_read(&txring->nr_free)
2177 >= (jme->tx_wake_threshold)) {
b3821cc5 2178 netif_wake_queue(jme->dev);
937ef75a 2179 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT		 2180 }
2181 }
2182
cd0ff491 2183 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 2184 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2185 txbi->skb)) {
2186 netif_stop_queue(jme->dev);
e3b96dc9
GFT		 2187 netif_info(jme, tx_queued, jme->dev,
2188 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2189 }
b3821cc5
GFT		 2190}
2191
3bf61c55
GFT		 2192/*
2193 * This function is already protected by netif_tx_lock()
2194 */
cd0ff491 2195
7ca9ebee 2196#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
3bf61c55 2197static int
7ca9ebee
GFT		 2198#else
2199static netdev_tx_t
2200#endif
3bf61c55 2201jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2202{
cd0ff491 2203 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2204 int idx;
d7699f87 2205
cd0ff491 2206 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 2207 ++(NET_STAT(jme).tx_dropped);
2208 return NETDEV_TX_OK;
2209 }
2210
2211 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2212
cd0ff491 2213 if (unlikely(idx < 0)) {
b3821cc5 2214 netif_stop_queue(netdev);
937ef75a
JP		 2215 netif_err(jme, tx_err, jme->dev,
2216 "BUG! Tx ring full when queue awake!\n");
d7699f87 2217
cd0ff491 2218 return NETDEV_TX_BUSY;
b3821cc5
GFT		 2219 }
2220
3b70a6fa 2221 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2222
4330c2f2
GFT		 2223 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2224 TXCS_SELECT_QUEUE0 |
2225 TXCS_QUEUE0S |
2226 TXCS_ENABLE);
0ede469c 2227#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
d7699f87 2228 netdev->trans_start = jiffies;
0ede469c 2229#endif
d7699f87 2230
937ef75a
JP		 2231 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2232 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT		 2233 jme_stop_queue_if_full(jme);
2234
cd0ff491 2235 return NETDEV_TX_OK;
d7699f87
GFT		 2236}
2237
e523cd89
GFT		 2238static void
2239jme_set_unicastaddr(struct net_device *netdev)
2240{
2241 struct jme_adapter *jme = netdev_priv(netdev);
2242 u32 val;
2243
2244 val = (netdev->dev_addr[3] & 0xff) << 24 |
2245 (netdev->dev_addr[2] & 0xff) << 16 |
2246 (netdev->dev_addr[1] & 0xff) << 8 |
2247 (netdev->dev_addr[0] & 0xff);
2248 jwrite32(jme, JME_RXUMA_LO, val);
2249 val = (netdev->dev_addr[5] & 0xff) << 8 |
2250 (netdev->dev_addr[4] & 0xff);
2251 jwrite32(jme, JME_RXUMA_HI, val);
2252}
2253
3bf61c55
GFT		 2254static int
2255jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2256{
cd0ff491 2257 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2258 struct sockaddr *addr = p;
d7699f87 2259
cd0ff491 2260 if (netif_running(netdev))
d7699f87
GFT		 2261 return -EBUSY;
2262
cd0ff491 2263 spin_lock_bh(&jme->macaddr_lock);
d7699f87 2264 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
e523cd89 2265 jme_set_unicastaddr(netdev);
cd0ff491 2266 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 2267
2268 return 0;
2269}
2270
3bf61c55
GFT		 2271static void
2272jme_set_multi(struct net_device *netdev)
d7699f87 2273{
3bf61c55 2274 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2275 u32 mc_hash[2] = {};
7ca9ebee 2276#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
d7699f87 2277 int i;
7ca9ebee 2278#endif
d7699f87 2279
cd0ff491 2280 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2281
2282 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2283
cd0ff491 2284 if (netdev->flags & IFF_PROMISC) {
8c198884 2285 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2286 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2287 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2288 } else if (netdev->flags & IFF_MULTICAST) {
8e14c278 2289#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
3bf61c55 2290 struct dev_mc_list *mclist;
8e14c278
JP		 2291#else
2292 struct netdev_hw_addr *ha;
2293#endif
3bf61c55 2294 int bit_nr;
d7699f87 2295
8c198884 2296 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
7ca9ebee 2297#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
3bf61c55
GFT		 2298 for (i = 0, mclist = netdev->mc_list;
2299 mclist && i < netdev->mc_count;
2300 ++i, mclist = mclist->next) {
8e14c278 2301#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
7ca9ebee 2302 netdev_for_each_mc_addr(mclist, netdev) {
8e14c278
JP		 2303#else
2304 netdev_for_each_mc_addr(ha, netdev) {
7ca9ebee 2305#endif
8e14c278 2306#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
cd0ff491 2307 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
8e14c278
JP		 2308#else
2309 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2310#endif
cd0ff491
GFT		 2311 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2312 }
d7699f87 2313
4330c2f2
GFT		 2314 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2315 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2316 }
2317
d7699f87 2318 wmb();
8c198884
GFT		 2319 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2320
cd0ff491 2321 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2322}
2323
3bf61c55 2324static int
8c198884 2325jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2326{
cd0ff491 2327 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2328
cd0ff491 2329 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2330 return 0;
2331
cd0ff491
GFT		 2332 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2333 ((new_mtu) < IPV6_MIN_MTU))
2334 return -EINVAL;
79ce639c 2335
cd0ff491 2336 if (new_mtu > 4000) {
79ce639c
GFT		 2337 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2338 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2339 jme_restart_rx_engine(jme);
cd0ff491 2340 } else {
79ce639c
GFT		 2341 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2342 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2343 jme_restart_rx_engine(jme);
2344 }
2345
cd0ff491 2346 if (new_mtu > 1900) {
1a0b42f4
MM		 2347 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2348 NETIF_F_TSO | NETIF_F_TSO6);
cd0ff491
GFT		 2349 } else {
2350 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
1a0b42f4 2351 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491 2352 if (test_bit(JME_FLAG_TSO, &jme->flags))
1a0b42f4 2353 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT		 2354 }
2355
cd0ff491
GFT		 2356 netdev->mtu = new_mtu;
2357 jme_reset_link(jme);
79ce639c
GFT		 2358
2359 return 0;
d7699f87
GFT		 2360}
2361
8c198884
GFT		 2362static void
2363jme_tx_timeout(struct net_device *netdev)
2364{
cd0ff491 2365 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2366
cdcdc9eb
GFT		 2367 jme->phylink = 0;
2368 jme_reset_phy_processor(jme);
cd0ff491 2369 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2370 jme_set_settings(netdev, &jme->old_ecmd);
2371
8c198884 2372 /*
cdcdc9eb 2373 * Force to Reset the link again
8c198884 2374 */
29bdd921 2375 jme_reset_link(jme);
8c198884
GFT		 2376}
2377
1e5ebebc
GFT		 2378static inline void jme_pause_rx(struct jme_adapter *jme)
2379{
2380 atomic_dec(&jme->link_changing);
2381
2382 jme_set_rx_pcc(jme, PCC_OFF);
2383 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2384 JME_NAPI_DISABLE(jme);
2385 } else {
2386 tasklet_disable(&jme->rxclean_task);
2387 tasklet_disable(&jme->rxempty_task);
2388 }
2389}
2390
2391static inline void jme_resume_rx(struct jme_adapter *jme)
2392{
2393 struct dynpcc_info *dpi = &(jme->dpi);
2394
2395 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2396 JME_NAPI_ENABLE(jme);
2397 } else {
2398 tasklet_hi_enable(&jme->rxclean_task);
2399 tasklet_hi_enable(&jme->rxempty_task);
2400 }
2401 dpi->cur = PCC_P1;
2402 dpi->attempt = PCC_P1;
2403 dpi->cnt = 0;
2404 jme_set_rx_pcc(jme, PCC_P1);
2405
2406 atomic_inc(&jme->link_changing);
2407}
2408
42b1055e
GFT		 2409static void
2410jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2411{
2412 struct jme_adapter *jme = netdev_priv(netdev);
2413
1e5ebebc 2414 jme_pause_rx(jme);
42b1055e 2415 jme->vlgrp = grp;
1e5ebebc 2416 jme_resume_rx(jme);
42b1055e
GFT		 2417}
2418
7ca9ebee
GFT		 2419#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2420static void
2421jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2422{
2423 struct jme_adapter *jme = netdev_priv(netdev);
2424
7ca9ebee 2425 if(jme->vlgrp) {
1e5ebebc 2426 jme_pause_rx(jme);
7ca9ebee
GFT		 2427#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2428 jme->vlgrp->vlan_devices[vid] = NULL;
2429#else
2430 vlan_group_set_device(jme->vlgrp, vid, NULL);
2431#endif
1e5ebebc 2432 jme_resume_rx(jme);
7ca9ebee 2433 }
7ca9ebee
GFT		 2434}
2435#endif
2436
3bf61c55
GFT		 2437static void
2438jme_get_drvinfo(struct net_device *netdev,
2439 struct ethtool_drvinfo *info)
d7699f87 2440{
cd0ff491 2441 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2442
cd0ff491
GFT		 2443 strcpy(info->driver, DRV_NAME);
2444 strcpy(info->version, DRV_VERSION);
2445 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT		 2446}
2447
8c198884
GFT		 2448static int
2449jme_get_regs_len(struct net_device *netdev)
2450{
cd0ff491 2451 return JME_REG_LEN;
8c198884
GFT		 2452}
2453
2454static void
cd0ff491 2455mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2456{
2457 int i;
2458
cd0ff491 2459 for (i = 0 ; i < len ; i += 4)
79ce639c 2460 p[i >> 2] = jread32(jme, reg + i);
186fc259 2461}
8c198884 2462
186fc259 2463static void
cd0ff491 2464mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2465{
2466 int i;
cd0ff491 2467 u16 *p16 = (u16 *)p;
186fc259 2468
cd0ff491 2469 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2470 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2471}
2472
2473static void
2474jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2475{
cd0ff491
GFT		 2476 struct jme_adapter *jme = netdev_priv(netdev);
2477 u32 *p32 = (u32 *)p;
8c198884 2478
186fc259 2479 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2480
2481 regs->version = 1;
2482 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2483
2484 p32 += 0x100 >> 2;
2485 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2486
2487 p32 += 0x100 >> 2;
2488 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2489
2490 p32 += 0x100 >> 2;
2491 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2492
186fc259
GFT		 2493 p32 += 0x100 >> 2;
2494 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2495}
2496
2497static int
2498jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2499{
2500 struct jme_adapter *jme = netdev_priv(netdev);
2501
8c198884
GFT		 2502 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2503 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2504
cd0ff491 2505 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2506 ecmd->use_adaptive_rx_coalesce = false;
2507 ecmd->rx_coalesce_usecs = 0;
2508 ecmd->rx_max_coalesced_frames = 0;
2509 return 0;
2510 }
2511
2512 ecmd->use_adaptive_rx_coalesce = true;
2513
cd0ff491 2514 switch (jme->dpi.cur) {
8c198884
GFT		 2515 case PCC_P1:
2516 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2517 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2518 break;
2519 case PCC_P2:
2520 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2521 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2522 break;
2523 case PCC_P3:
2524 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2525 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2526 break;
2527 default:
2528 break;
2529 }
2530
2531 return 0;
2532}
2533
192570e0
GFT		 2534static int
2535jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2536{
2537 struct jme_adapter *jme = netdev_priv(netdev);
2538 struct dynpcc_info *dpi = &(jme->dpi);
2539
cd0ff491 2540 if (netif_running(netdev))
cdcdc9eb
GFT		 2541 return -EBUSY;
2542
7ca9ebee
GFT		 2543 if (ecmd->use_adaptive_rx_coalesce &&
2544 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2545 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2546 jme->jme_rx = netif_rx;
2547 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT		 2548 dpi->cur = PCC_P1;
2549 dpi->attempt = PCC_P1;
2550 dpi->cnt = 0;
2551 jme_set_rx_pcc(jme, PCC_P1);
2552 jme_interrupt_mode(jme);
7ca9ebee
GFT		 2553 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2554 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2555 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2556 jme->jme_rx = netif_receive_skb;
2557 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT		 2558 jme_interrupt_mode(jme);
2559 }
2560
2561 return 0;
2562}
2563
8c198884
GFT		 2564static void
2565jme_get_pauseparam(struct net_device *netdev,
2566 struct ethtool_pauseparam *ecmd)
2567{
2568 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2569 u32 val;
8c198884
GFT		 2570
2571 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2572 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2573
cd0ff491
GFT		 2574 spin_lock_bh(&jme->phy_lock);
2575 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2576 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2577
2578 ecmd->autoneg =
2579 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2580}
2581
2582static int
2583jme_set_pauseparam(struct net_device *netdev,
2584 struct ethtool_pauseparam *ecmd)
2585{
2586 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2587 u32 val;
8c198884 2588
cd0ff491 2589 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2590 (ecmd->tx_pause != 0)) {
2591
cd0ff491 2592 if (ecmd->tx_pause)
8c198884
GFT		 2593 jme->reg_txpfc |= TXPFC_PF_EN;
2594 else
2595 jme->reg_txpfc &= ~TXPFC_PF_EN;
2596
2597 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2598 }
2599
cd0ff491
GFT		 2600 spin_lock_bh(&jme->rxmcs_lock);
2601 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2602 (ecmd->rx_pause != 0)) {
2603
cd0ff491 2604 if (ecmd->rx_pause)
8c198884
GFT		 2605 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2606 else
2607 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2608
2609 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2610 }
cd0ff491 2611 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2612
cd0ff491
GFT		 2613 spin_lock_bh(&jme->phy_lock);
2614 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2615 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2616 (ecmd->autoneg != 0)) {
2617
cd0ff491 2618 if (ecmd->autoneg)
8c198884
GFT		 2619 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2620 else
2621 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2622
b3821cc5
GFT		 2623 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2624 MII_ADVERTISE, val);
8c198884 2625 }
cd0ff491 2626 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2627
2628 return 0;
2629}
2630
29bdd921
GFT		 2631static void
2632jme_get_wol(struct net_device *netdev,
2633 struct ethtool_wolinfo *wol)
2634{
2635 struct jme_adapter *jme = netdev_priv(netdev);
2636
2637 wol->supported = WAKE_MAGIC | WAKE_PHY;
2638
2639 wol->wolopts = 0;
2640
cd0ff491 2641 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2642 wol->wolopts |= WAKE_PHY;
2643
cd0ff491 2644 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2645 wol->wolopts |= WAKE_MAGIC;
2646
2647}
2648
2649static int
2650jme_set_wol(struct net_device *netdev,
2651 struct ethtool_wolinfo *wol)
2652{
2653 struct jme_adapter *jme = netdev_priv(netdev);
2654
cd0ff491 2655 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2656 WAKE_UCAST |
2657 WAKE_MCAST |
2658 WAKE_BCAST |
2659 WAKE_ARP))
2660 return -EOPNOTSUPP;
2661
2662 jme->reg_pmcs = 0;
2663
cd0ff491 2664 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2665 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2666
cd0ff491 2667 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2668 jme->reg_pmcs |= PMCS_MFEN;
2669
cd0ff491 2670 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3d12cc1b
GFT		 2671#ifndef JME_NEW_PM_API
2672 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2673#endif
7370b85a 2674#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3d12cc1b 2675 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
7370b85a 2676#endif
e3b96dc9 2677
29bdd921
GFT		 2678 return 0;
2679}
b3821cc5 2680
3bf61c55
GFT		 2681static int
2682jme_get_settings(struct net_device *netdev,
2683 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2684{
2685 struct jme_adapter *jme = netdev_priv(netdev);
2686 int rc;
8c198884 2687
cd0ff491 2688 spin_lock_bh(&jme->phy_lock);
d7699f87 2689 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2690 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2691 return rc;
2692}
2693
3bf61c55
GFT		 2694static int
2695jme_set_settings(struct net_device *netdev,
2696 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2697{
2698 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2699 int rc, fdc = 0;
fcf45b4c 2700
8588b84b
DD		 2701 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2702 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2703 return -EINVAL;
2704
e6b41b51
GFT		 2705 /*
2706 * Check If user changed duplex only while force_media.
2707 * Hardware would not generate link change interrupt.
2708 */
cd0ff491 2709 if (jme->mii_if.force_media &&
79ce639c
GFT		 2710 ecmd->autoneg != AUTONEG_ENABLE &&
2711 (jme->mii_if.full_duplex != ecmd->duplex))
2712 fdc = 1;
2713
cd0ff491 2714 spin_lock_bh(&jme->phy_lock);
d7699f87 2715 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2716 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2717
cd0ff491 2718 if (!rc) {
e6b41b51
GFT		 2719 if (fdc)
2720 jme_reset_link(jme);
29bdd921 2721 jme->old_ecmd = *ecmd;
aa1e7189
GFT		 2722 set_bit(JME_FLAG_SSET, &jme->flags);
2723 }
2724
2725 return rc;
2726}
2727
2728static int
2729jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2730{
2731 int rc;
2732 struct jme_adapter *jme = netdev_priv(netdev);
2733 struct mii_ioctl_data *mii_data = if_mii(rq);
2734 unsigned int duplex_chg;
2735
2736 if (cmd == SIOCSMIIREG) {
2737 u16 val = mii_data->val_in;
2738 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2739 (val & BMCR_SPEED1000))
2740 return -EINVAL;
2741 }
2742
2743 spin_lock_bh(&jme->phy_lock);
2744 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2745 spin_unlock_bh(&jme->phy_lock);
2746
2747 if (!rc && (cmd == SIOCSMIIREG)) {
2748 if (duplex_chg)
2749 jme_reset_link(jme);
2750 jme_get_settings(netdev, &jme->old_ecmd);
2751 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2752 }
2753
d7699f87
GFT		 2754 return rc;
2755}
2756
cd0ff491 2757static u32
3bf61c55
GFT		 2758jme_get_link(struct net_device *netdev)
2759{
d7699f87
GFT		 2760 struct jme_adapter *jme = netdev_priv(netdev);
2761 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2762}
2763
8c198884 2764static u32
cd0ff491
GFT		 2765jme_get_msglevel(struct net_device *netdev)
2766{
2767 struct jme_adapter *jme = netdev_priv(netdev);
2768 return jme->msg_enable;
2769}
2770
2771static void
2772jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2773{
cd0ff491
GFT		 2774 struct jme_adapter *jme = netdev_priv(netdev);
2775 jme->msg_enable = value;
2776}
8c198884 2777
cd0ff491
GFT		 2778static u32
2779jme_get_rx_csum(struct net_device *netdev)
2780{
2781 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2782 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2783}
2784
2785static int
2786jme_set_rx_csum(struct net_device *netdev, u32 on)
2787{
cd0ff491 2788 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2789
cd0ff491
GFT		 2790 spin_lock_bh(&jme->rxmcs_lock);
2791 if (on)
8c198884
GFT		 2792 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2793 else
2794 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2795 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2796 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2797
2798 return 0;
2799}
2800
2801static int
2802jme_set_tx_csum(struct net_device *netdev, u32 on)
2803{
cd0ff491 2804 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2805
cd0ff491
GFT		 2806 if (on) {
2807 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2808 if (netdev->mtu <= 1900)
1a0b42f4
MM		 2809 netdev->features |=
2810 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491
GFT		 2811 } else {
2812 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
1a0b42f4
MM		 2813 netdev->features &=
2814 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
b3821cc5 2815 }
8c198884
GFT		 2816
2817 return 0;
2818}
2819
b3821cc5
GFT		 2820static int
2821jme_set_tso(struct net_device *netdev, u32 on)
2822{
cd0ff491 2823 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2824
cd0ff491
GFT		 2825 if (on) {
2826 set_bit(JME_FLAG_TSO, &jme->flags);
2827 if (netdev->mtu <= 1900)
1a0b42f4 2828 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT		 2829 } else {
2830 clear_bit(JME_FLAG_TSO, &jme->flags);
1a0b42f4 2831 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT		 2832 }
2833
cd0ff491 2834 return 0;
b3821cc5
GFT		 2835}
2836
8c198884
GFT		 2837static int
2838jme_nway_reset(struct net_device *netdev)
2839{
cd0ff491 2840 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2841 jme_restart_an(jme);
2842 return 0;
2843}
2844
cd0ff491 2845static u8
186fc259
GFT		 2846jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2847{
cd0ff491 2848 u32 val;
186fc259
GFT		 2849 int to;
2850
2851 val = jread32(jme, JME_SMBCSR);
2852 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2853 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2854 msleep(1);
2855 val = jread32(jme, JME_SMBCSR);
2856 }
cd0ff491 2857 if (!to) {
937ef75a 2858 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2859 return 0xFF;
2860 }
2861
2862 jwrite32(jme, JME_SMBINTF,
2863 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2864 SMBINTF_HWRWN_READ |
2865 SMBINTF_HWCMD);
2866
2867 val = jread32(jme, JME_SMBINTF);
2868 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2869 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2870 msleep(1);
2871 val = jread32(jme, JME_SMBINTF);
2872 }
cd0ff491 2873 if (!to) {
937ef75a 2874 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2875 return 0xFF;
2876 }
2877
2878 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2879}
2880
2881static void
cd0ff491 2882jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2883{
cd0ff491 2884 u32 val;
186fc259
GFT		 2885 int to;
2886
2887 val = jread32(jme, JME_SMBCSR);
2888 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2889 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2890 msleep(1);
2891 val = jread32(jme, JME_SMBCSR);
2892 }
cd0ff491 2893 if (!to) {
937ef75a 2894 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2895 return;
2896 }
2897
2898 jwrite32(jme, JME_SMBINTF,
2899 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2900 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2901 SMBINTF_HWRWN_WRITE |
2902 SMBINTF_HWCMD);
2903
2904 val = jread32(jme, JME_SMBINTF);
2905 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2906 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2907 msleep(1);
2908 val = jread32(jme, JME_SMBINTF);
2909 }
cd0ff491 2910 if (!to) {
937ef75a 2911 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2912 return;
2913 }
2914
2915 mdelay(2);
2916}
2917
2918static int
2919jme_get_eeprom_len(struct net_device *netdev)
2920{
cd0ff491
GFT		 2921 struct jme_adapter *jme = netdev_priv(netdev);
2922 u32 val;
186fc259 2923 val = jread32(jme, JME_SMBCSR);
cd0ff491 2924 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 2925}
2926
2927static int
2928jme_get_eeprom(struct net_device *netdev,
2929 struct ethtool_eeprom *eeprom, u8 *data)
2930{
cd0ff491 2931 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2932 int i, offset = eeprom->offset, len = eeprom->len;
2933
2934 /*
8d27293f 2935 * ethtool will check the boundary for us
186fc259
GFT		 2936 */
2937 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2938 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2939 data[i] = jme_smb_read(jme, i + offset);
2940
2941 return 0;
2942}
2943
2944static int
2945jme_set_eeprom(struct net_device *netdev,
2946 struct ethtool_eeprom *eeprom, u8 *data)
2947{
cd0ff491 2948 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2949 int i, offset = eeprom->offset, len = eeprom->len;
2950
2951 if (eeprom->magic != JME_EEPROM_MAGIC)
2952 return -EINVAL;
2953
2954 /*
8d27293f 2955 * ethtool will check the boundary for us
186fc259 2956 */
cd0ff491 2957 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2958 jme_smb_write(jme, i + offset, data[i]);
2959
2960 return 0;
2961}
2962
3b70a6fa
GFT		 2963#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2964static struct ethtool_ops jme_ethtool_ops = {
2965#else
d7699f87 2966static const struct ethtool_ops jme_ethtool_ops = {
3b70a6fa 2967#endif
cd0ff491 2968 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 2969 .get_regs_len = jme_get_regs_len,
2970 .get_regs = jme_get_regs,
2971 .get_coalesce = jme_get_coalesce,
192570e0 2972 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 2973 .get_pauseparam = jme_get_pauseparam,
2974 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 2975 .get_wol = jme_get_wol,
2976 .set_wol = jme_set_wol,
d7699f87
GFT		 2977 .get_settings = jme_get_settings,
2978 .set_settings = jme_set_settings,
2979 .get_link = jme_get_link,
cd0ff491
GFT		 2980 .get_msglevel = jme_get_msglevel,
2981 .set_msglevel = jme_set_msglevel,
8c198884
GFT		 2982 .get_rx_csum = jme_get_rx_csum,
2983 .set_rx_csum = jme_set_rx_csum,
2984 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT		 2985 .set_tso = jme_set_tso,
2986 .set_sg = ethtool_op_set_sg,
8c198884 2987 .nway_reset = jme_nway_reset,
186fc259
GFT		 2988 .get_eeprom_len = jme_get_eeprom_len,
2989 .get_eeprom = jme_get_eeprom,
2990 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 2991};
2992
3bf61c55
GFT		 2993static int
2994jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2995{
3b70a6fa 2996 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 2997#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2998 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2999#else
3000 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
3001#endif
3002 )
3003#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3004 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3005#else
cd0ff491 3006 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
0ede469c 3007#endif
3bf61c55
GFT		 3008 return 1;
3009
3b70a6fa 3010 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 3011#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3012 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
3013#else
3014 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
3015#endif
3016 )
3017#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3018 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
3019#else
cd0ff491 3020 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
0ede469c 3021#endif
8c198884
GFT		 3022 return 1;
3023
0ede469c
GFT		 3024#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3025 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
3026 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3027#else
cd0ff491
GFT		 3028 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3029 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
0ede469c 3030#endif
3bf61c55
GFT		 3031 return 0;
3032
3033 return -1;
3034}
3035
cd0ff491 3036static inline void
cdcdc9eb
GFT		 3037jme_phy_init(struct jme_adapter *jme)
3038{
cd0ff491 3039 u16 reg26;
cdcdc9eb
GFT		 3040
3041 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3042 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3043}
3044
cd0ff491 3045static inline void
cdcdc9eb 3046jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 3047{
cd0ff491 3048 u32 chipmode;
cdcdc9eb
GFT		 3049
3050 chipmode = jread32(jme, JME_CHIPMODE);
3051
3052 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 3053 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
98ef18f1
GFT		 3054 jme->chip_main_rev = jme->chiprev & 0xF;
3055 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT		 3056}
3057
3b70a6fa
GFT		 3058#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3059static const struct net_device_ops jme_netdev_ops = {
3060 .ndo_open = jme_open,
3061 .ndo_stop = jme_close,
3062 .ndo_validate_addr = eth_validate_addr,
aa1e7189 3063 .ndo_do_ioctl = jme_ioctl,
3b70a6fa
GFT		 3064 .ndo_start_xmit = jme_start_xmit,
3065 .ndo_set_mac_address = jme_set_macaddr,
3066 .ndo_set_multicast_list = jme_set_multi,
3067 .ndo_change_mtu = jme_change_mtu,
3068 .ndo_tx_timeout = jme_tx_timeout,
3069 .ndo_vlan_rx_register = jme_vlan_rx_register,
3070};
3071#endif
3072
3bf61c55
GFT		 3073static int __devinit
3074jme_init_one(struct pci_dev *pdev,
3075 const struct pci_device_id *ent)
3076{
cdcdc9eb 3077 int rc = 0, using_dac, i;
d7699f87
GFT		 3078 struct net_device *netdev;
3079 struct jme_adapter *jme;
cd0ff491
GFT		 3080 u16 bmcr, bmsr;
3081 u32 apmc;
d7699f87
GFT		 3082
3083 /*
3084 * set up PCI device basics
3085 */
4330c2f2 3086 rc = pci_enable_device(pdev);
cd0ff491 3087 if (rc) {
937ef75a 3088 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT		 3089 goto err_out;
3090 }
d7699f87 3091
3bf61c55 3092 using_dac = jme_pci_dma64(pdev);
cd0ff491 3093 if (using_dac < 0) {
937ef75a 3094 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT		 3095 rc = -EIO;
3096 goto err_out_disable_pdev;
3097 }
3098
cd0ff491 3099 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
937ef75a 3100 pr_err("No PCI resource region found\n");
4330c2f2
GFT		 3101 rc = -ENOMEM;
3102 goto err_out_disable_pdev;
3103 }
d7699f87 3104
4330c2f2 3105 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 3106 if (rc) {
937ef75a 3107 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT		 3108 goto err_out_disable_pdev;
3109 }
d7699f87
GFT		 3110
3111 pci_set_master(pdev);
3112
3113 /*
3114 * alloc and init net device
3115 */
3bf61c55 3116 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 3117 if (!netdev) {
937ef75a 3118 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT		 3119 rc = -ENOMEM;
3120 goto err_out_release_regions;
d7699f87 3121 }
3b70a6fa
GFT		 3122#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3123 netdev->netdev_ops = &jme_netdev_ops;
3124#else
d7699f87
GFT		 3125 netdev->open = jme_open;
3126 netdev->stop = jme_close;
aa1e7189 3127 netdev->do_ioctl = jme_ioctl;
d7699f87 3128 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT		 3129 netdev->set_mac_address = jme_set_macaddr;
3130 netdev->set_multicast_list = jme_set_multi;
3131 netdev->change_mtu = jme_change_mtu;
8c198884 3132 netdev->tx_timeout = jme_tx_timeout;
42b1055e 3133 netdev->vlan_rx_register = jme_vlan_rx_register;
7ca9ebee
GFT		 3134#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3135 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3136#endif
3bf61c55 3137 NETDEV_GET_STATS(netdev, &jme_get_stats);
3b70a6fa
GFT		 3138#endif
3139 netdev->ethtool_ops = &jme_ethtool_ops;
3140 netdev->watchdog_timeo = TX_TIMEOUT;
1a0b42f4
MM		 3141 netdev->features = NETIF_F_IP_CSUM |
3142 NETIF_F_IPV6_CSUM |
b3821cc5
GFT		 3143 NETIF_F_SG |
3144 NETIF_F_TSO |
3145 NETIF_F_TSO6 |
42b1055e
GFT		 3146 NETIF_F_HW_VLAN_TX |
3147 NETIF_F_HW_VLAN_RX;
cd0ff491 3148 if (using_dac)
8c198884 3149 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 3150
3151 SET_NETDEV_DEV(netdev, &pdev->dev);
3152 pci_set_drvdata(pdev, netdev);
3153
3154 /*
3155 * init adapter info
3156 */
3157 jme = netdev_priv(netdev);
3158 jme->pdev = pdev;
3159 jme->dev = netdev;
cdcdc9eb
GFT		 3160 jme->jme_rx = netif_rx;
3161 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 3162 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 3163 jme->phylink = 0;
b3821cc5 3164 jme->tx_ring_size = 1 << 10;
0ede469c 3165 jme->tx_ring_mask = jme->tx_ring_size - 1;
b3821cc5
GFT		 3166 jme->tx_wake_threshold = 1 << 9;
3167 jme->rx_ring_size = 1 << 9;
3168 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 3169 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 3170 jme->regs = ioremap(pci_resource_start(pdev, 0),
3171 pci_resource_len(pdev, 0));
4330c2f2 3172 if (!(jme->regs)) {
937ef75a 3173 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT		 3174 rc = -ENOMEM;
3175 goto err_out_free_netdev;
3176 }
4330c2f2 3177
cd0ff491
GFT		 3178 if (no_pseudohp) {
3179 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3180 jwrite32(jme, JME_APMC, apmc);
3181 } else if (force_pseudohp) {
3182 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3183 jwrite32(jme, JME_APMC, apmc);
3184 }
3185
cdcdc9eb 3186 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 3187
d7699f87 3188 spin_lock_init(&jme->phy_lock);
fcf45b4c 3189 spin_lock_init(&jme->macaddr_lock);
8c198884 3190 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 3191
fcf45b4c
GFT		 3192 atomic_set(&jme->link_changing, 1);
3193 atomic_set(&jme->rx_cleaning, 1);
3194 atomic_set(&jme->tx_cleaning, 1);
192570e0 3195 atomic_set(&jme->rx_empty, 1);
fcf45b4c 3196
79ce639c 3197 tasklet_init(&jme->pcc_task,
7ca9ebee 3198 jme_pcc_tasklet,
79ce639c 3199 (unsigned long) jme);
4330c2f2 3200 tasklet_init(&jme->linkch_task,
7ca9ebee 3201 jme_link_change_tasklet,
4330c2f2
GFT		 3202 (unsigned long) jme);
3203 tasklet_init(&jme->txclean_task,
7ca9ebee 3204 jme_tx_clean_tasklet,
4330c2f2
GFT		 3205 (unsigned long) jme);
3206 tasklet_init(&jme->rxclean_task,
7ca9ebee 3207 jme_rx_clean_tasklet,
4330c2f2 3208 (unsigned long) jme);
fcf45b4c 3209 tasklet_init(&jme->rxempty_task,
7ca9ebee 3210 jme_rx_empty_tasklet,
fcf45b4c 3211 (unsigned long) jme);
0ede469c 3212 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 3213 tasklet_disable_nosync(&jme->txclean_task);
3214 tasklet_disable_nosync(&jme->rxclean_task);
3215 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 3216 jme->dpi.cur = PCC_P1;
3217
cd0ff491 3218 jme->reg_ghc = 0;
79ce639c 3219 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 3220 jme->reg_rxmcs = RXMCS_DEFAULT;
3221 jme->reg_txpfc = 0;
47220951 3222 jme->reg_pmcs = PMCS_MFEN;
dc4185bd 3223 jme->reg_gpreg1 = GPREG1_DEFAULT;
cd0ff491
GFT		 3224 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3225 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 3226
fcf45b4c
GFT		 3227 /*
3228 * Get Max Read Req Size from PCI Config Space
3229 */
cd0ff491
GFT		 3230 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3231 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3232 switch (jme->mrrs) {
3233 case MRRS_128B:
3234 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3235 break;
3236 case MRRS_256B:
3237 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3238 break;
3239 default:
3240 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3241 break;
cd54cf32 3242 }
fcf45b4c 3243
d7699f87 3244 /*
cdcdc9eb 3245 * Must check before reset_mac_processor
d7699f87 3246 */
cdcdc9eb
GFT		 3247 jme_check_hw_ver(jme);
3248 jme->mii_if.dev = netdev;
cd0ff491 3249 if (jme->fpgaver) {
cdcdc9eb 3250 jme->mii_if.phy_id = 0;
cd0ff491 3251 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 3252 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3253 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3254 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 3255 jme->mii_if.phy_id = i;
3256 break;
3257 }
3258 }
3259
cd0ff491 3260 if (!jme->mii_if.phy_id) {
cdcdc9eb 3261 rc = -EIO;
937ef75a
JP		 3262 pr_err("Can not find phy_id\n");
3263 goto err_out_unmap;
cdcdc9eb
GFT		 3264 }
3265
3266 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3267 } else {
cdcdc9eb
GFT		 3268 jme->mii_if.phy_id = 1;
3269 }
cd0ff491 3270 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 3271 jme->mii_if.supports_gmii = true;
3272 else
3273 jme->mii_if.supports_gmii = false;
aa1e7189
GFT		 3274 jme->mii_if.phy_id_mask = 0x1F;
3275 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT		 3276 jme->mii_if.mdio_read = jme_mdio_read;
3277 jme->mii_if.mdio_write = jme_mdio_write;
3278
61891ee4
GFT		 3279 jme_clear_pm(jme);
3280 pci_set_power_state(jme->pdev, PCI_D0);
3281#ifndef JME_NEW_PM_API
3282 jme_pci_wakeup_enable(jme, true);
3283#endif
3284#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
e3b96dc9 3285 device_set_wakeup_enable(&pdev->dev, true);
61891ee4
GFT		 3286#endif
3287
55d19799 3288 jme_set_phyfifo_5level(jme);
711edd99 3289#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
98ef18f1 3290 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
711edd99
SS		 3291#else
3292 jme->pcirev = pdev->revision;
3293#endif
cd0ff491 3294 if (!jme->fpgaver)
cdcdc9eb 3295 jme_phy_init(jme);
42b1055e 3296 jme_phy_off(jme);
cdcdc9eb
GFT		 3297
3298 /*
3299 * Reset MAC processor and reload EEPROM for MAC Address
3300 */
d7699f87 3301 jme_reset_mac_processor(jme);
4330c2f2 3302 rc = jme_reload_eeprom(jme);
cd0ff491 3303 if (rc) {
937ef75a 3304 pr_err("Reload eeprom for reading MAC Address error\n");
0ede469c 3305 goto err_out_unmap;
4330c2f2 3306 }
d7699f87
GFT		 3307 jme_load_macaddr(netdev);
3308
d7699f87
GFT		 3309 /*
3310 * Tell stack that we are not ready to work until open()
3311 */
3312 netif_carrier_off(netdev);
d7699f87 3313
4330c2f2 3314 rc = register_netdev(netdev);
cd0ff491 3315 if (rc) {
937ef75a 3316 pr_err("Cannot register net device\n");
0ede469c 3317 goto err_out_unmap;
4330c2f2 3318 }
d7699f87 3319
98ef18f1 3320 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
937ef75a 3321 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
7ca9ebee
GFT		 3322 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3323 "JMC250 Gigabit Ethernet" :
3324 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3325 "JMC260 Fast Ethernet" : "Unknown",
3326 (jme->fpgaver != 0) ? " (FPGA)" : "",
3327 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
98ef18f1 3328 jme->pcirev,
937ef75a
JP		 3329 netdev->dev_addr[0],
3330 netdev->dev_addr[1],
3331 netdev->dev_addr[2],
3332 netdev->dev_addr[3],
3333 netdev->dev_addr[4],
3334 netdev->dev_addr[5]);
d7699f87
GFT		 3335
3336 return 0;
3337
3338err_out_unmap:
3339 iounmap(jme->regs);
3340err_out_free_netdev:
3341 pci_set_drvdata(pdev, NULL);
3342 free_netdev(netdev);
4330c2f2
GFT		 3343err_out_release_regions:
3344 pci_release_regions(pdev);
d7699f87 3345err_out_disable_pdev:
cd0ff491 3346 pci_disable_device(pdev);
d7699f87 3347err_out:
4330c2f2 3348 return rc;
d7699f87
GFT		 3349}
3350
3bf61c55
GFT		 3351static void __devexit
3352jme_remove_one(struct pci_dev *pdev)
3353{
d7699f87
GFT		 3354 struct net_device *netdev = pci_get_drvdata(pdev);
3355 struct jme_adapter *jme = netdev_priv(netdev);
3356
3357 unregister_netdev(netdev);
3358 iounmap(jme->regs);
3359 pci_set_drvdata(pdev, NULL);
3360 free_netdev(netdev);
3361 pci_release_regions(pdev);
3362 pci_disable_device(pdev);
3363
3364}
3365
a82e368c
GFT		 3366static void
3367jme_shutdown(struct pci_dev *pdev)
3368{
3369 struct net_device *netdev = pci_get_drvdata(pdev);
3370 struct jme_adapter *jme = netdev_priv(netdev);
3371
61891ee4
GFT		 3372 jme_powersave_phy(jme);
3373#ifndef JME_NEW_PM_API
3374 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3375#endif
3d12cc1b 3376#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
61891ee4 3377 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
a82e368c
GFT		 3378#endif
3379}
3380
fda5634a
GFT		 3381#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3382 #ifdef CONFIG_PM
3383 #define JME_HAVE_PM
3384 #endif
3385#else
3386 #ifdef CONFIG_PM_SLEEP
3387 #define JME_HAVE_PM
3388 #endif
3389#endif
3390
3391#ifdef JME_HAVE_PM
29bdd921 3392static int
3d12cc1b 3393#ifdef JME_NEW_PM_API
7370b85a 3394jme_suspend(struct device *dev)
3d12cc1b
GFT		 3395#else
3396jme_suspend(struct pci_dev *pdev, pm_message_t state)
7370b85a 3397#endif
29bdd921 3398{
3d12cc1b 3399#ifdef JME_NEW_PM_API
7370b85a
RW		 3400 struct pci_dev *pdev = to_pci_dev(dev);
3401#endif
29bdd921
GFT		 3402 struct net_device *netdev = pci_get_drvdata(pdev);
3403 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 3404
3405 atomic_dec(&jme->link_changing);
3406
3407 netif_device_detach(netdev);
3408 netif_stop_queue(netdev);
3409 jme_stop_irq(jme);
29bdd921 3410
cd0ff491
GFT		 3411 tasklet_disable(&jme->txclean_task);
3412 tasklet_disable(&jme->rxclean_task);
3413 tasklet_disable(&jme->rxempty_task);
3414
cd0ff491
GFT		 3415 if (netif_carrier_ok(netdev)) {
3416 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 3417 jme_polling_mode(jme);
3418
29bdd921 3419 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 3420 jme_disable_rx_engine(jme);
3421 jme_disable_tx_engine(jme);
29bdd921
GFT		 3422 jme_reset_mac_processor(jme);
3423 jme_free_rx_resources(jme);
3424 jme_free_tx_resources(jme);
3425 netif_carrier_off(netdev);
3426 jme->phylink = 0;
3427 }
3428
cd0ff491
GFT		 3429 tasklet_enable(&jme->txclean_task);
3430 tasklet_hi_enable(&jme->rxclean_task);
3431 tasklet_hi_enable(&jme->rxempty_task);
29bdd921 3432
a82e368c 3433 jme_powersave_phy(jme);
3d12cc1b 3434#ifndef JME_NEW_PM_API
7370b85a 3435 pci_save_state(pdev);
61891ee4 3436 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
a82e368c 3437 pci_set_power_state(pdev, PCI_D3hot);
7370b85a 3438#endif
29bdd921
GFT		 3439
3440 return 0;
3441}
3442
3443static int
3d12cc1b 3444#ifdef JME_NEW_PM_API
7370b85a 3445jme_resume(struct device *dev)
3d12cc1b
GFT		 3446#else
3447jme_resume(struct pci_dev *pdev)
7370b85a 3448#endif
29bdd921 3449{
3d12cc1b 3450#ifdef JME_NEW_PM_API
7370b85a
RW		 3451 struct pci_dev *pdev = to_pci_dev(dev);
3452#endif
29bdd921
GFT		 3453 struct net_device *netdev = pci_get_drvdata(pdev);
3454 struct jme_adapter *jme = netdev_priv(netdev);
3455
3456 jme_clear_pm(jme);
3d12cc1b
GFT		 3457#ifndef JME_NEW_PM_API
3458 pci_set_power_state(pdev, PCI_D0);
29bdd921 3459 pci_restore_state(pdev);
7370b85a 3460#endif
29bdd921 3461
ed457bcc
GFT		 3462 jme_phy_on(jme);
3463 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3464 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 3465 else
29bdd921
GFT		 3466 jme_reset_phy_processor(jme);
3467
29bdd921
GFT		 3468 jme_start_irq(jme);
3469 netif_device_attach(netdev);
3470
3471 atomic_inc(&jme->link_changing);
3472
3473 jme_reset_link(jme);
3474
3475 return 0;
3476}
7370b85a 3477
e3b96dc9 3478#ifdef JME_NEW_PM_API
7370b85a
RW		 3479static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3480#define JME_PM_OPS (&jme_pm_ops)
3481#endif
3482
3483#else
3484
e3b96dc9 3485#ifdef JME_NEW_PM_API
7370b85a
RW		 3486#define JME_PM_OPS NULL
3487#endif
7ee473a3 3488#endif
29bdd921 3489
7ca9ebee 3490#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
d7699f87 3491static struct pci_device_id jme_pci_tbl[] = {
7ca9ebee
GFT		 3492#else
3493static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3494#endif
cd0ff491
GFT		 3495 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3496 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3497 { }
3498};
3499
3500static struct pci_driver jme_driver = {
cd0ff491
GFT		 3501 .name = DRV_NAME,
3502 .id_table = jme_pci_tbl,
3503 .probe = jme_init_one,
3504 .remove = __devexit_p(jme_remove_one),
a82e368c 3505 .shutdown = jme_shutdown,
e3b96dc9 3506#ifndef JME_NEW_PM_API
7370b85a
RW		 3507 .suspend = jme_suspend,
3508 .resume = jme_resume
3509#else
3510 .driver.pm = JME_PM_OPS,
3511#endif
d7699f87
GFT		 3512};
3513
3bf61c55
GFT		 3514static int __init
3515jme_init_module(void)
d7699f87 3516{
937ef75a 3517 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3518 return pci_register_driver(&jme_driver);
3519}
3520
3bf61c55
GFT		 3521static void __exit
3522jme_cleanup_module(void)
d7699f87
GFT		 3523{
3524 pci_unregister_driver(&jme_driver);
3525}
3526
3527module_init(jme_init_module);
3528module_exit(jme_cleanup_module);
3529
3bf61c55 3530MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3531MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3532MODULE_LICENSE("GPL");
3533MODULE_VERSION(DRV_VERSION);
3534MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3535
JMicron Ethernet Linux driver