]> bbs.cooldavid.org Git - jme.git/blame - jme.c
git://bbs.cooldavid.org / jme.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix compile warning
[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
d3d584f5 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
d7699f87 7 *
3bf61c55
GFT		 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
d7699f87
GFT		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
2e582300 25#include <linux/version.h>
937ef75a
JP		 26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
d7699f87
GFT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
4330c2f2 38#include <linux/delay.h>
29bdd921 39#include <linux/spinlock.h>
8c198884
GFT		 40#include <linux/in.h>
41#include <linux/ip.h>
79ce639c
GFT		 42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
42b1055e 45#include <linux/if_vlan.h>
38d1bc09 46#include <linux/slab.h>
3b70a6fa 47#include <net/ip6_checksum.h>
d7699f87
GFT		 48#include "jme.h"
49
cd0ff491
GFT		 50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
4330c2f2 61
6d06d88c 62#ifndef JME_NEW_PM_API
3d12cc1b
GFT		 63static void
64jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
65{
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
67 pci_enable_wake(jme->pdev, PCI_D1, enable);
68 pci_enable_wake(jme->pdev, PCI_D2, enable);
69 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
70 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
71#else
72 pci_pme_active(jme->pdev, enable);
73#endif
74}
6d06d88c 75#endif
3d12cc1b 76
3bf61c55
GFT		 77static int
78jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 79{
80 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 81 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
d7699f87 82
186fc259 83read_again:
cd0ff491 84 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 85 smi_phy_addr(phy) |
86 smi_reg_addr(reg));
d7699f87
GFT		 87
88 wmb();
cd0ff491 89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
cdcdc9eb 90 udelay(20);
b3821cc5
GFT		 91 val = jread32(jme, JME_SMI);
92 if ((val & SMI_OP_REQ) == 0)
3bf61c55 93 break;
cd0ff491 94 }
d7699f87 95
cd0ff491 96 if (i == 0) {
937ef75a 97 pr_err("phy(%d) read timeout : %d\n", phy, reg);
3bf61c55 98 return 0;
cd0ff491 99 }
d7699f87 100
cd0ff491 101 if (again--)
186fc259
GFT		 102 goto read_again;
103
cd0ff491 104 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
d7699f87
GFT		 105}
106
3bf61c55
GFT		 107static void
108jme_mdio_write(struct net_device *netdev,
109 int phy, int reg, int val)
d7699f87
GFT		 110{
111 struct jme_adapter *jme = netdev_priv(netdev);
112 int i;
113
3bf61c55
GFT		 114 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
115 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
116 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 117
118 wmb();
cdcdc9eb
GFT		 119 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
120 udelay(20);
8d27293f 121 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
3bf61c55
GFT		 122 break;
123 }
d7699f87 124
3bf61c55 125 if (i == 0)
937ef75a 126 pr_err("phy(%d) write timeout : %d\n", phy, reg);
d7699f87
GFT		 127}
128
cd0ff491 129static inline void
3bf61c55 130jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 131{
cd0ff491 132 u32 val;
3bf61c55
GFT		 133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
8c198884
GFT		 136 MII_ADVERTISE, ADVERTISE_ALL |
137 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55 138
cd0ff491 139 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 140 jme_mdio_write(jme->dev,
141 jme->mii_if.phy_id,
142 MII_CTRL1000,
143 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3bf61c55 144
fcf45b4c
GFT		 145 val = jme_mdio_read(jme->dev,
146 jme->mii_if.phy_id,
147 MII_BMCR);
148
149 jme_mdio_write(jme->dev,
150 jme->mii_if.phy_id,
151 MII_BMCR, val | BMCR_RESET);
3bf61c55
GFT		 152}
153
b3821cc5
GFT		 154static void
155jme_setup_wakeup_frame(struct jme_adapter *jme,
a4181cd4 156 const u32 *mask, u32 crc, int fnr)
b3821cc5
GFT		 157{
158 int i;
159
160 /*
161 * Setup CRC pattern
162 */
163 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
164 wmb();
165 jwrite32(jme, JME_WFODP, crc);
166 wmb();
167
168 /*
169 * Setup Mask
170 */
cd0ff491 171 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
b3821cc5
GFT		 172 jwrite32(jme, JME_WFOI,
173 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
174 (fnr & WFOI_FRAME_SEL));
175 wmb();
176 jwrite32(jme, JME_WFODP, mask[i]);
177 wmb();
178 }
179}
3bf61c55 180
dc4185bd
GFT		 181static inline void
182jme_mac_rxclk_off(struct jme_adapter *jme)
183{
184 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
185 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
186}
187
188static inline void
189jme_mac_rxclk_on(struct jme_adapter *jme)
190{
191 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
192 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
193}
194
195static inline void
196jme_mac_txclk_off(struct jme_adapter *jme)
197{
198 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
200}
201
202static inline void
203jme_mac_txclk_on(struct jme_adapter *jme)
204{
205 u32 speed = jme->reg_ghc & GHC_SPEED;
206 if (speed == GHC_SPEED_1000M)
207 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
208 else
209 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
210 jwrite32f(jme, JME_GHC, jme->reg_ghc);
211}
212
213static inline void
214jme_reset_ghc_speed(struct jme_adapter *jme)
215{
216 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218}
219
220static inline void
221jme_reset_250A2_workaround(struct jme_adapter *jme)
222{
223 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
224 GPREG1_RSSPATCH);
225 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
226}
227
228static inline void
229jme_assert_ghc_reset(struct jme_adapter *jme)
230{
231 jme->reg_ghc |= GHC_SWRST;
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
233}
234
235static inline void
236jme_clear_ghc_reset(struct jme_adapter *jme)
237{
238 jme->reg_ghc &= ~GHC_SWRST;
239 jwrite32f(jme, JME_GHC, jme->reg_ghc);
240}
241
cd0ff491 242static inline void
3bf61c55
GFT		 243jme_reset_mac_processor(struct jme_adapter *jme)
244{
a4181cd4 245 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
cd0ff491
GFT		 246 u32 crc = 0xCDCDCDCD;
247 u32 gpreg0;
b3821cc5
GFT		 248 int i;
249
dc4185bd
GFT		 250 jme_reset_ghc_speed(jme);
251 jme_reset_250A2_workaround(jme);
252
253 jme_mac_rxclk_on(jme);
254 jme_mac_txclk_on(jme);
255 udelay(1);
256 jme_assert_ghc_reset(jme);
257 udelay(1);
258 jme_mac_rxclk_off(jme);
259 jme_mac_txclk_off(jme);
260 udelay(1);
261 jme_clear_ghc_reset(jme);
262 udelay(1);
263 jme_mac_rxclk_on(jme);
264 jme_mac_txclk_on(jme);
265 udelay(1);
266 jme_mac_rxclk_off(jme);
267 jme_mac_txclk_off(jme);
cd0ff491
GFT		 268
269 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
270 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
271 jwrite32(jme, JME_RXQDC, 0x00000000);
272 jwrite32(jme, JME_RXNDA, 0x00000000);
273 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
274 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
275 jwrite32(jme, JME_TXQDC, 0x00000000);
276 jwrite32(jme, JME_TXNDA, 0x00000000);
277
4330c2f2
GFT		 278 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
279 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
cd0ff491 280 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
b3821cc5 281 jme_setup_wakeup_frame(jme, mask, crc, i);
cd0ff491 282 if (jme->fpgaver)
cdcdc9eb
GFT		 283 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
284 else
285 gpreg0 = GPREG0_DEFAULT;
286 jwrite32(jme, JME_GPREG0, gpreg0);
cd0ff491
GFT		 287}
288
289static inline void
3bf61c55 290jme_clear_pm(struct jme_adapter *jme)
d7699f87 291{
3d12cc1b 292 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
d7699f87
GFT		 293}
294
3bf61c55
GFT		 295static int
296jme_reload_eeprom(struct jme_adapter *jme)
d7699f87 297{
cd0ff491 298 u32 val;
d7699f87
GFT		 299 int i;
300
301 val = jread32(jme, JME_SMBCSR);
302
cd0ff491 303 if (val & SMBCSR_EEPROMD) {
d7699f87
GFT		 304 val |= SMBCSR_CNACK;
305 jwrite32(jme, JME_SMBCSR, val);
306 val |= SMBCSR_RELOAD;
307 jwrite32(jme, JME_SMBCSR, val);
308 mdelay(12);
309
cd0ff491 310 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
d7699f87
GFT		 311 mdelay(1);
312 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
313 break;
314 }
315
cd0ff491 316 if (i == 0) {
937ef75a 317 pr_err("eeprom reload timeout\n");
d7699f87
GFT		 318 return -EIO;
319 }
320 }
3bf61c55 321
d7699f87
GFT		 322 return 0;
323}
324
3bf61c55
GFT		 325static void
326jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 327{
328 struct jme_adapter *jme = netdev_priv(netdev);
329 unsigned char macaddr[6];
cd0ff491 330 u32 val;
d7699f87 331
cd0ff491 332 spin_lock_bh(&jme->macaddr_lock);
4330c2f2 333 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 334 macaddr[0] = (val >> 0) & 0xFF;
335 macaddr[1] = (val >> 8) & 0xFF;
336 macaddr[2] = (val >> 16) & 0xFF;
337 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 338 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 339 macaddr[4] = (val >> 0) & 0xFF;
340 macaddr[5] = (val >> 8) & 0xFF;
cd0ff491
GFT		 341 memcpy(netdev->dev_addr, macaddr, 6);
342 spin_unlock_bh(&jme->macaddr_lock);
3bf61c55
GFT		 343}
344
cd0ff491 345static inline void
3bf61c55
GFT		 346jme_set_rx_pcc(struct jme_adapter *jme, int p)
347{
cd0ff491 348 switch (p) {
192570e0
GFT		 349 case PCC_OFF:
350 jwrite32(jme, JME_PCCRX0,
351 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
352 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
353 break;
3bf61c55
GFT		 354 case PCC_P1:
355 jwrite32(jme, JME_PCCRX0,
356 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
357 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
358 break;
359 case PCC_P2:
360 jwrite32(jme, JME_PCCRX0,
361 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
362 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
363 break;
364 case PCC_P3:
365 jwrite32(jme, JME_PCCRX0,
366 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
367 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
368 break;
369 default:
370 break;
371 }
192570e0 372 wmb();
3bf61c55 373
cd0ff491 374 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
7ca9ebee 375 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 376}
377
fcf45b4c 378static void
3bf61c55 379jme_start_irq(struct jme_adapter *jme)
d7699f87 380{
3bf61c55
GFT		 381 register struct dynpcc_info *dpi = &(jme->dpi);
382
383 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 384 dpi->cur = PCC_P1;
385 dpi->attempt = PCC_P1;
386 dpi->cnt = 0;
387
388 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 389 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
390 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 391 PCCTXQ0_EN
392 );
393
d7699f87
GFT		 394 /*
395 * Enable Interrupts
396 */
397 jwrite32(jme, JME_IENS, INTR_ENABLE);
398}
399
cd0ff491 400static inline void
3bf61c55 401jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 402{
403 /*
404 * Disable Interrupts
405 */
cd0ff491 406 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87
GFT		 407}
408
cd0ff491 409static u32
cdcdc9eb
GFT		 410jme_linkstat_from_phy(struct jme_adapter *jme)
411{
cd0ff491 412 u32 phylink, bmsr;
cdcdc9eb
GFT		 413
414 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
415 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
cd0ff491 416 if (bmsr & BMSR_ANCOMP)
cdcdc9eb
GFT		 417 phylink |= PHY_LINK_AUTONEG_COMPLETE;
418
419 return phylink;
420}
421
cd0ff491 422static inline void
55d19799 423jme_set_phyfifo_5level(struct jme_adapter *jme)
cd0ff491
GFT		 424{
425 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
426}
427
428static inline void
55d19799 429jme_set_phyfifo_8level(struct jme_adapter *jme)
cd0ff491
GFT		 430{
431 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
432}
433
fcf45b4c
GFT		 434static int
435jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 436{
437 struct jme_adapter *jme = netdev_priv(netdev);
dc4185bd 438 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 439 char linkmsg[64];
fcf45b4c 440 int rc = 0;
d7699f87 441
b3821cc5 442 linkmsg[0] = '\0';
cdcdc9eb 443
cd0ff491 444 if (jme->fpgaver)
cdcdc9eb
GFT		 445 phylink = jme_linkstat_from_phy(jme);
446 else
447 phylink = jread32(jme, JME_PHY_LINK);
d7699f87 448
cd0ff491
GFT		 449 if (phylink & PHY_LINK_UP) {
450 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
8c198884
GFT		 451 /*
452 * If we did not enable AN
453 * Speed/Duplex Info should be obtained from SMI
454 */
455 phylink = PHY_LINK_UP;
456
457 bmcr = jme_mdio_read(jme->dev,
458 jme->mii_if.phy_id,
459 MII_BMCR);
460
461 phylink |= ((bmcr & BMCR_SPEED1000) &&
462 (bmcr & BMCR_SPEED100) == 0) ?
463 PHY_LINK_SPEED_1000M :
464 (bmcr & BMCR_SPEED100) ?
465 PHY_LINK_SPEED_100M :
466 PHY_LINK_SPEED_10M;
467
468 phylink |= (bmcr & BMCR_FULLDPLX) ?
469 PHY_LINK_DUPLEX : 0;
79ce639c 470
b3821cc5 471 strcat(linkmsg, "Forced: ");
cd0ff491 472 } else {
8c198884
GFT		 473 /*
474 * Keep polling for speed/duplex resolve complete
475 */
cd0ff491 476 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
8c198884
GFT		 477 --cnt) {
478
479 udelay(1);
8c198884 480
cd0ff491 481 if (jme->fpgaver)
cdcdc9eb
GFT		 482 phylink = jme_linkstat_from_phy(jme);
483 else
484 phylink = jread32(jme, JME_PHY_LINK);
8c198884 485 }
cd0ff491 486 if (!cnt)
937ef75a 487 pr_err("Waiting speed resolve timeout\n");
79ce639c 488
b3821cc5 489 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 490 }
491
cd0ff491 492 if (jme->phylink == phylink) {
fcf45b4c
GFT		 493 rc = 1;
494 goto out;
495 }
cd0ff491 496 if (testonly)
fcf45b4c
GFT		 497 goto out;
498
499 jme->phylink = phylink;
500
dc4185bd
GFT		 501 /*
502 * The speed/duplex setting of jme->reg_ghc already cleared
503 * by jme_reset_mac_processor()
504 */
cd0ff491
GFT		 505 switch (phylink & PHY_LINK_SPEED_MASK) {
506 case PHY_LINK_SPEED_10M:
dc4185bd 507 jme->reg_ghc |= GHC_SPEED_10M;
cd0ff491 508 strcat(linkmsg, "10 Mbps, ");
cd0ff491
GFT		 509 break;
510 case PHY_LINK_SPEED_100M:
dc4185bd 511 jme->reg_ghc |= GHC_SPEED_100M;
cd0ff491 512 strcat(linkmsg, "100 Mbps, ");
cd0ff491
GFT		 513 break;
514 case PHY_LINK_SPEED_1000M:
dc4185bd 515 jme->reg_ghc |= GHC_SPEED_1000M;
cd0ff491 516 strcat(linkmsg, "1000 Mbps, ");
cd0ff491
GFT		 517 break;
518 default:
519 break;
d7699f87 520 }
d7699f87 521
cd0ff491 522 if (phylink & PHY_LINK_DUPLEX) {
d7699f87 523 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
809b2798 524 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
dc4185bd 525 jme->reg_ghc |= GHC_DPX;
cd0ff491 526 } else {
d7699f87 527 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 528 TXMCS_BACKOFF |
529 TXMCS_CARRIERSENSE |
530 TXMCS_COLLISION);
809b2798 531 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
8c198884 532 }
7ee473a3 533
dc4185bd
GFT		 534 jwrite32(jme, JME_GHC, jme->reg_ghc);
535
7ee473a3 536 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
dc4185bd
GFT		 537 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
538 GPREG1_RSSPATCH);
7ee473a3 539 if (!(phylink & PHY_LINK_DUPLEX))
dc4185bd 540 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
7ee473a3
GFT		 541 switch (phylink & PHY_LINK_SPEED_MASK) {
542 case PHY_LINK_SPEED_10M:
55d19799 543 jme_set_phyfifo_8level(jme);
dc4185bd 544 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 545 break;
546 case PHY_LINK_SPEED_100M:
55d19799 547 jme_set_phyfifo_5level(jme);
dc4185bd 548 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
7ee473a3
GFT		 549 break;
550 case PHY_LINK_SPEED_1000M:
55d19799 551 jme_set_phyfifo_8level(jme);
7ee473a3
GFT		 552 break;
553 default:
554 break;
555 }
556 }
dc4185bd 557 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
fcf45b4c 558
3b70a6fa
GFT		 559 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
560 "Full-Duplex, " :
561 "Half-Duplex, ");
562 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
563 "MDI-X" :
564 "MDI");
937ef75a 565 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
cd0ff491
GFT		 566 netif_carrier_on(netdev);
567 } else {
568 if (testonly)
fcf45b4c
GFT		 569 goto out;
570
937ef75a 571 netif_info(jme, link, jme->dev, "Link is down\n");
fcf45b4c 572 jme->phylink = 0;
cd0ff491 573 netif_carrier_off(netdev);
d7699f87 574 }
fcf45b4c
GFT		 575
576out:
577 return rc;
d7699f87
GFT		 578}
579
3bf61c55
GFT		 580static int
581jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 582{
d7699f87
GFT		 583 struct jme_ring *txring = &(jme->txring[0]);
584
585 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 586 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
587 &(txring->dmaalloc),
588 GFP_ATOMIC);
fcf45b4c 589
0ede469c
GFT		 590 if (!txring->alloc)
591 goto err_set_null;
d7699f87
GFT		 592
593 /*
594 * 16 Bytes align
595 */
cd0ff491 596 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
3bf61c55 597 RING_DESC_ALIGN);
4330c2f2 598 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87 599 txring->next_to_use = 0;
cdcdc9eb 600 atomic_set(&txring->next_to_clean, 0);
b3821cc5 601 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87 602
0ede469c
GFT		 603 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
604 jme->tx_ring_size, GFP_ATOMIC);
605 if (unlikely(!(txring->bufinf)))
606 goto err_free_txring;
607
d7699f87 608 /*
b3821cc5 609 * Initialize Transmit Descriptors
d7699f87 610 */
b3821cc5 611 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 612 memset(txring->bufinf, 0,
b3821cc5 613 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 614
615 return 0;
0ede469c
GFT		 616
617err_free_txring:
618 dma_free_coherent(&(jme->pdev->dev),
619 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
620 txring->alloc,
621 txring->dmaalloc);
622
623err_set_null:
624 txring->desc = NULL;
625 txring->dmaalloc = 0;
626 txring->dma = 0;
627 txring->bufinf = NULL;
628
629 return -ENOMEM;
d7699f87
GFT		 630}
631
3bf61c55
GFT		 632static void
633jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 634{
635 int i;
636 struct jme_ring *txring = &(jme->txring[0]);
0ede469c 637 struct jme_buffer_info *txbi;
d7699f87 638
cd0ff491 639 if (txring->alloc) {
0ede469c
GFT		 640 if (txring->bufinf) {
641 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
642 txbi = txring->bufinf + i;
643 if (txbi->skb) {
644 dev_kfree_skb(txbi->skb);
645 txbi->skb = NULL;
646 }
647 txbi->mapping = 0;
648 txbi->len = 0;
649 txbi->nr_desc = 0;
650 txbi->start_xmit = 0;
d7699f87 651 }
0ede469c 652 kfree(txring->bufinf);
d7699f87
GFT		 653 }
654
655 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 656 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 657 txring->alloc,
658 txring->dmaalloc);
3bf61c55
GFT		 659
660 txring->alloc = NULL;
661 txring->desc = NULL;
662 txring->dmaalloc = 0;
663 txring->dma = 0;
0ede469c 664 txring->bufinf = NULL;
d7699f87 665 }
3bf61c55 666 txring->next_to_use = 0;
cdcdc9eb 667 atomic_set(&txring->next_to_clean, 0);
79ce639c 668 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 669}
670
cd0ff491 671static inline void
3bf61c55 672jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 673{
674 /*
675 * Select Queue 0
676 */
677 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
cd0ff491 678 wmb();
d7699f87
GFT		 679
680 /*
681 * Setup TX Queue 0 DMA Bass Address
682 */
fcf45b4c 683 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 684 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 685 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 686
687 /*
688 * Setup TX Descptor Count
689 */
b3821cc5 690 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 691
692 /*
693 * Enable TX Engine
694 */
695 wmb();
dc4185bd 696 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
4330c2f2
GFT		 697 TXCS_SELECT_QUEUE0 |
698 TXCS_ENABLE);
d7699f87 699
dc4185bd
GFT		 700 /*
701 * Start clock for TX MAC Processor
702 */
703 jme_mac_txclk_on(jme);
d7699f87
GFT		 704}
705
cd0ff491 706static inline void
29bdd921
GFT		 707jme_restart_tx_engine(struct jme_adapter *jme)
708{
709 /*
710 * Restart TX Engine
711 */
712 jwrite32(jme, JME_TXCS, jme->reg_txcs |
713 TXCS_SELECT_QUEUE0 |
714 TXCS_ENABLE);
715}
716
cd0ff491 717static inline void
3bf61c55 718jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 719{
720 int i;
cd0ff491 721 u32 val;
d7699f87
GFT		 722
723 /*
724 * Disable TX Engine
725 */
fcf45b4c 726 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
cd0ff491 727 wmb();
d7699f87
GFT		 728
729 val = jread32(jme, JME_TXCS);
cd0ff491 730 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
fcf45b4c 731 mdelay(1);
d7699f87 732 val = jread32(jme, JME_TXCS);
cd0ff491 733 rmb();
d7699f87
GFT		 734 }
735
cd0ff491 736 if (!i)
937ef75a 737 pr_err("Disable TX engine timeout\n");
dc4185bd
GFT		 738
739 /*
740 * Stop clock for TX MAC Processor
741 */
742 jme_mac_txclk_off(jme);
d7699f87
GFT		 743}
744
3bf61c55
GFT		 745static void
746jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87 747{
0ede469c 748 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 749 register struct rxdesc *rxdesc = rxring->desc;
4330c2f2
GFT		 750 struct jme_buffer_info *rxbi = rxring->bufinf;
751 rxdesc += i;
752 rxbi += i;
753
754 rxdesc->dw[0] = 0;
755 rxdesc->dw[1] = 0;
3bf61c55 756 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 757 rxdesc->desc1.bufaddrl = cpu_to_le32(
758 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55 759 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
cd0ff491 760 if (jme->dev->features & NETIF_F_HIGHDMA)
3bf61c55 761 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 762 wmb();
3bf61c55 763 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 764}
765
3bf61c55
GFT		 766static int
767jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 768{
769 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 770 struct jme_buffer_info *rxbi = rxring->bufinf + i;
cd0ff491 771 struct sk_buff *skb;
4330c2f2 772
79ce639c
GFT		 773 skb = netdev_alloc_skb(jme->dev,
774 jme->dev->mtu + RX_EXTRA_LEN);
cd0ff491 775 if (unlikely(!skb))
4330c2f2 776 return -ENOMEM;
3b70a6fa
GFT		 777#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
778 skb->dev = jme->dev;
779#endif
3bf61c55 780
4330c2f2 781 rxbi->skb = skb;
3bf61c55 782 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT		 783 rxbi->mapping = pci_map_page(jme->pdev,
784 virt_to_page(skb->data),
785 offset_in_page(skb->data),
786 rxbi->len,
787 PCI_DMA_FROMDEVICE);
4330c2f2
GFT		 788
789 return 0;
790}
791
3bf61c55
GFT		 792static void
793jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 794{
795 struct jme_ring *rxring = &(jme->rxring[0]);
796 struct jme_buffer_info *rxbi = rxring->bufinf;
797 rxbi += i;
798
cd0ff491 799 if (rxbi->skb) {
b3821cc5 800 pci_unmap_page(jme->pdev,
4330c2f2 801 rxbi->mapping,
3bf61c55 802 rxbi->len,
4330c2f2
GFT		 803 PCI_DMA_FROMDEVICE);
804 dev_kfree_skb(rxbi->skb);
805 rxbi->skb = NULL;
806 rxbi->mapping = 0;
3bf61c55 807 rxbi->len = 0;
4330c2f2
GFT		 808 }
809}
810
3bf61c55
GFT		 811static void
812jme_free_rx_resources(struct jme_adapter *jme)
813{
814 int i;
815 struct jme_ring *rxring = &(jme->rxring[0]);
816
cd0ff491 817 if (rxring->alloc) {
0ede469c
GFT		 818 if (rxring->bufinf) {
819 for (i = 0 ; i < jme->rx_ring_size ; ++i)
820 jme_free_rx_buf(jme, i);
821 kfree(rxring->bufinf);
822 }
3bf61c55
GFT		 823
824 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 825 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 826 rxring->alloc,
827 rxring->dmaalloc);
828 rxring->alloc = NULL;
829 rxring->desc = NULL;
830 rxring->dmaalloc = 0;
831 rxring->dma = 0;
0ede469c 832 rxring->bufinf = NULL;
3bf61c55
GFT		 833 }
834 rxring->next_to_use = 0;
cdcdc9eb 835 atomic_set(&rxring->next_to_clean, 0);
3bf61c55
GFT		 836}
837
838static int
839jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 840{
841 int i;
842 struct jme_ring *rxring = &(jme->rxring[0]);
843
844 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 845 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
846 &(rxring->dmaalloc),
847 GFP_ATOMIC);
0ede469c
GFT		 848 if (!rxring->alloc)
849 goto err_set_null;
d7699f87
GFT		 850
851 /*
852 * 16 Bytes align
853 */
cd0ff491 854 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
3bf61c55 855 RING_DESC_ALIGN);
4330c2f2 856 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87 857 rxring->next_to_use = 0;
cdcdc9eb 858 atomic_set(&rxring->next_to_clean, 0);
d7699f87 859
0ede469c
GFT		 860 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
861 jme->rx_ring_size, GFP_ATOMIC);
862 if (unlikely(!(rxring->bufinf)))
863 goto err_free_rxring;
864
d7699f87
GFT		 865 /*
866 * Initiallize Receive Descriptors
867 */
0ede469c
GFT		 868 memset(rxring->bufinf, 0,
869 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
cd0ff491
GFT		 870 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
871 if (unlikely(jme_make_new_rx_buf(jme, i))) {
3bf61c55
GFT		 872 jme_free_rx_resources(jme);
873 return -ENOMEM;
874 }
d7699f87
GFT		 875
876 jme_set_clean_rxdesc(jme, i);
877 }
878
d7699f87 879 return 0;
0ede469c
GFT		 880
881err_free_rxring:
882 dma_free_coherent(&(jme->pdev->dev),
883 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
884 rxring->alloc,
885 rxring->dmaalloc);
886err_set_null:
887 rxring->desc = NULL;
888 rxring->dmaalloc = 0;
889 rxring->dma = 0;
890 rxring->bufinf = NULL;
891
892 return -ENOMEM;
d7699f87
GFT		 893}
894
cd0ff491 895static inline void
3bf61c55 896jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 897{
cd0ff491
GFT		 898 /*
899 * Select Queue 0
900 */
901 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
902 RXCS_QUEUESEL_Q0);
903 wmb();
904
d7699f87
GFT		 905 /*
906 * Setup RX DMA Bass Address
907 */
0ede469c 908 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
3bf61c55 909 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
0ede469c 910 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
d7699f87
GFT		 911
912 /*
b3821cc5 913 * Setup RX Descriptor Count
d7699f87 914 */
b3821cc5 915 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 916
3bf61c55 917 /*
d7699f87
GFT		 918 * Setup Unicast Filter
919 */
e523cd89 920 jme_set_unicastaddr(jme->dev);
d7699f87
GFT		 921 jme_set_multi(jme->dev);
922
923 /*
924 * Enable RX Engine
925 */
926 wmb();
dc4185bd 927 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 928 RXCS_QUEUESEL_Q0 |
929 RXCS_ENABLE |
930 RXCS_QST);
dc4185bd
GFT		 931
932 /*
933 * Start clock for RX MAC Processor
934 */
935 jme_mac_rxclk_on(jme);
d7699f87
GFT		 936}
937
cd0ff491 938static inline void
3bf61c55 939jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 940{
941 /*
3bf61c55 942 * Start RX Engine
4330c2f2 943 */
79ce639c 944 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 945 RXCS_QUEUESEL_Q0 |
946 RXCS_ENABLE |
947 RXCS_QST);
948}
949
cd0ff491 950static inline void
3bf61c55 951jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 952{
953 int i;
cd0ff491 954 u32 val;
d7699f87
GFT		 955
956 /*
957 * Disable RX Engine
958 */
29bdd921 959 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
cd0ff491 960 wmb();
d7699f87
GFT		 961
962 val = jread32(jme, JME_RXCS);
cd0ff491 963 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
29bdd921 964 mdelay(1);
d7699f87 965 val = jread32(jme, JME_RXCS);
cd0ff491 966 rmb();
d7699f87
GFT		 967 }
968
cd0ff491 969 if (!i)
937ef75a 970 pr_err("Disable RX engine timeout\n");
d7699f87 971
dc4185bd
GFT		 972 /*
973 * Stop clock for RX MAC Processor
974 */
975 jme_mac_rxclk_off(jme);
d7699f87
GFT		 976}
977
93f698ca
GFT		 978static u16
979jme_udpsum(struct sk_buff *skb)
980{
981 u16 csum = 0xFFFFu;
982
983 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
984 return csum;
985 if (skb->protocol != htons(ETH_P_IP))
986 return csum;
987 skb_set_network_header(skb, ETH_HLEN);
988 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
989 (skb->len < (ETH_HLEN +
990 (ip_hdr(skb)->ihl << 2) +
991 sizeof(struct udphdr)))) {
992 skb_reset_network_header(skb);
993 return csum;
994 }
995 skb_set_transport_header(skb,
996 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
997 csum = udp_hdr(skb)->check;
998 skb_reset_transport_header(skb);
999 skb_reset_network_header(skb);
1000
1001 return csum;
1002}
1003
192570e0 1004static int
93f698ca 1005jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
192570e0 1006{
cd0ff491 1007 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
192570e0
GFT		 1008 return false;
1009
0ede469c
GFT		 1010 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1011 == RXWBFLAG_TCPON)) {
1012 if (flags & RXWBFLAG_IPV4)
7ca9ebee 1013 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
0ede469c 1014 return false;
192570e0
GFT		 1015 }
1016
0ede469c 1017 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
93f698ca 1018 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
0ede469c 1019 if (flags & RXWBFLAG_IPV4)
937ef75a 1020 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
0ede469c 1021 return false;
192570e0
GFT		 1022 }
1023
0ede469c
GFT		 1024 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1025 == RXWBFLAG_IPV4)) {
937ef75a 1026 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
0ede469c 1027 return false;
192570e0
GFT		 1028 }
1029
1030 return true;
1031}
1032
3bf61c55 1033static void
42b1055e 1034jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 1035{
d7699f87 1036 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1037 struct rxdesc *rxdesc = rxring->desc;
3bf61c55 1038 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 1039 struct sk_buff *skb;
3bf61c55 1040 int framesize;
d7699f87 1041
3bf61c55
GFT		 1042 rxdesc += idx;
1043 rxbi += idx;
d7699f87 1044
3bf61c55
GFT		 1045 skb = rxbi->skb;
1046 pci_dma_sync_single_for_cpu(jme->pdev,
1047 rxbi->mapping,
1048 rxbi->len,
1049 PCI_DMA_FROMDEVICE);
1050
cd0ff491 1051 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
3bf61c55
GFT		 1052 pci_dma_sync_single_for_device(jme->pdev,
1053 rxbi->mapping,
1054 rxbi->len,
1055 PCI_DMA_FROMDEVICE);
1056
1057 ++(NET_STAT(jme).rx_dropped);
cd0ff491 1058 } else {
3bf61c55
GFT		 1059 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1060 - RX_PREPAD_SIZE;
1061
1062 skb_reserve(skb, RX_PREPAD_SIZE);
1063 skb_put(skb, framesize);
1064 skb->protocol = eth_type_trans(skb, jme->dev);
1065
93f698ca 1066 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
8c198884 1067 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921 1068 else
614c0bfd 1069#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
29bdd921 1070 skb->ip_summed = CHECKSUM_NONE;
08f5fcfa
ED		 1071#else
1072 skb_checksum_none_assert(skb);
1073#endif
8c198884 1074
3b70a6fa 1075 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
cd0ff491 1076 if (jme->vlgrp) {
cdcdc9eb 1077 jme->jme_vlan_rx(skb, jme->vlgrp,
3b70a6fa 1078 le16_to_cpu(rxdesc->descwb.vlan));
b3821cc5 1079 NET_STAT(jme).rx_bytes += 4;
7ca9ebee 1080 } else {
7ca9ebee 1081 dev_kfree_skb(skb);
b3821cc5 1082 }
cd0ff491 1083 } else {
cdcdc9eb 1084 jme->jme_rx(skb);
b3821cc5 1085 }
3bf61c55 1086
3b70a6fa
GFT		 1087 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1088 cpu_to_le16(RXWBFLAG_DEST_MUL))
3bf61c55
GFT		 1089 ++(NET_STAT(jme).multicast);
1090
3bf61c55
GFT		 1091 NET_STAT(jme).rx_bytes += framesize;
1092 ++(NET_STAT(jme).rx_packets);
1093 }
1094
1095 jme_set_clean_rxdesc(jme, idx);
1096
1097}
1098
1099static int
1100jme_process_receive(struct jme_adapter *jme, int limit)
1101{
1102 struct jme_ring *rxring = &(jme->rxring[0]);
cd0ff491 1103 struct rxdesc *rxdesc = rxring->desc;
b3821cc5 1104 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 1105
cd0ff491 1106 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
192570e0
GFT		 1107 goto out_inc;
1108
cd0ff491 1109 if (unlikely(atomic_read(&jme->link_changing) != 1))
192570e0
GFT		 1110 goto out_inc;
1111
cd0ff491 1112 if (unlikely(!netif_carrier_ok(jme->dev)))
192570e0
GFT		 1113 goto out_inc;
1114
cdcdc9eb 1115 i = atomic_read(&rxring->next_to_clean);
0ede469c 1116 while (limit > 0) {
3bf61c55
GFT		 1117 rxdesc = rxring->desc;
1118 rxdesc += i;
1119
3b70a6fa 1120 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
3bf61c55
GFT		 1121 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1122 goto out;
0ede469c 1123 --limit;
d7699f87 1124
9134abda 1125 rmb();
4330c2f2
GFT		 1126 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1127
cd0ff491 1128 if (unlikely(desccnt > 1 ||
192570e0 1129 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 1130
cd0ff491 1131 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
3bf61c55 1132 ++(NET_STAT(jme).rx_crc_errors);
cd0ff491 1133 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
3bf61c55
GFT		 1134 ++(NET_STAT(jme).rx_fifo_errors);
1135 else
1136 ++(NET_STAT(jme).rx_errors);
4330c2f2 1137
cd0ff491 1138 if (desccnt > 1)
3bf61c55 1139 limit -= desccnt - 1;
4330c2f2 1140
cd0ff491 1141 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 1142 jme_set_clean_rxdesc(jme, j);
b3821cc5 1143 j = (j + 1) & (mask);
4330c2f2 1144 }
3bf61c55 1145
cd0ff491 1146 } else {
42b1055e 1147 jme_alloc_and_feed_skb(jme, i);
3bf61c55 1148 }
4330c2f2 1149
b3821cc5 1150 i = (i + desccnt) & (mask);
3bf61c55 1151 }
4330c2f2 1152
3bf61c55 1153out:
cdcdc9eb 1154 atomic_set(&rxring->next_to_clean, i);
4330c2f2 1155
192570e0
GFT		 1156out_inc:
1157 atomic_inc(&jme->rx_cleaning);
1158
3bf61c55 1159 return limit > 0 ? limit : 0;
4330c2f2 1160
3bf61c55 1161}
d7699f87 1162
79ce639c
GFT		 1163static void
1164jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1165{
cd0ff491 1166 if (likely(atmp == dpi->cur)) {
192570e0 1167 dpi->cnt = 0;
79ce639c 1168 return;
192570e0 1169 }
79ce639c 1170
cd0ff491 1171 if (dpi->attempt == atmp) {
79ce639c 1172 ++(dpi->cnt);
cd0ff491 1173 } else {
79ce639c
GFT		 1174 dpi->attempt = atmp;
1175 dpi->cnt = 0;
1176 }
1177
1178}
1179
1180static void
1181jme_dynamic_pcc(struct jme_adapter *jme)
1182{
1183 register struct dynpcc_info *dpi = &(jme->dpi);
1184
cd0ff491 1185 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
79ce639c 1186 jme_attempt_pcc(dpi, PCC_P3);
7ca9ebee
GFT		 1187 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1188 dpi->intr_cnt > PCC_INTR_THRESHOLD)
79ce639c
GFT		 1189 jme_attempt_pcc(dpi, PCC_P2);
1190 else
1191 jme_attempt_pcc(dpi, PCC_P1);
1192
cd0ff491
GFT		 1193 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1194 if (dpi->attempt < dpi->cur)
1195 tasklet_schedule(&jme->rxclean_task);
79ce639c
GFT		 1196 jme_set_rx_pcc(jme, dpi->attempt);
1197 dpi->cur = dpi->attempt;
1198 dpi->cnt = 0;
1199 }
1200}
1201
1202static void
1203jme_start_pcc_timer(struct jme_adapter *jme)
1204{
1205 struct dynpcc_info *dpi = &(jme->dpi);
1206 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1207 dpi->last_pkts = NET_STAT(jme).rx_packets;
1208 dpi->intr_cnt = 0;
1209 jwrite32(jme, JME_TMCSR,
1210 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1211}
1212
cd0ff491 1213static inline void
29bdd921
GFT		 1214jme_stop_pcc_timer(struct jme_adapter *jme)
1215{
1216 jwrite32(jme, JME_TMCSR, 0);
1217}
1218
cd0ff491
GFT		 1219static void
1220jme_shutdown_nic(struct jme_adapter *jme)
1221{
1222 u32 phylink;
1223
1224 phylink = jme_linkstat_from_phy(jme);
1225
1226 if (!(phylink & PHY_LINK_UP)) {
1227 /*
1228 * Disable all interrupt before issue timer
1229 */
1230 jme_stop_irq(jme);
1231 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1232 }
1233}
1234
79ce639c
GFT		 1235static void
1236jme_pcc_tasklet(unsigned long arg)
1237{
cd0ff491 1238 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c
GFT		 1239 struct net_device *netdev = jme->dev;
1240
cd0ff491
GFT		 1241 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1242 jme_shutdown_nic(jme);
1243 return;
1244 }
29bdd921 1245
cd0ff491 1246 if (unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1247 (atomic_read(&jme->link_changing) != 1)
1248 )) {
1249 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1250 return;
1251 }
29bdd921 1252
cd0ff491 1253 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
192570e0
GFT		 1254 jme_dynamic_pcc(jme);
1255
79ce639c
GFT		 1256 jme_start_pcc_timer(jme);
1257}
1258
cd0ff491 1259static inline void
192570e0
GFT		 1260jme_polling_mode(struct jme_adapter *jme)
1261{
1262 jme_set_rx_pcc(jme, PCC_OFF);
1263}
1264
cd0ff491 1265static inline void
192570e0
GFT		 1266jme_interrupt_mode(struct jme_adapter *jme)
1267{
1268 jme_set_rx_pcc(jme, PCC_P1);
1269}
1270
cd0ff491
GFT		 1271static inline int
1272jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1273{
1274 u32 apmc;
1275 apmc = jread32(jme, JME_APMC);
1276 return apmc & JME_APMC_PSEUDO_HP_EN;
1277}
1278
1279static void
1280jme_start_shutdown_timer(struct jme_adapter *jme)
1281{
1282 u32 apmc;
1283
1284 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1285 apmc &= ~JME_APMC_EPIEN_CTRL;
1286 if (!no_extplug) {
1287 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1288 wmb();
1289 }
1290 jwrite32f(jme, JME_APMC, apmc);
1291
1292 jwrite32f(jme, JME_TIMER2, 0);
1293 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1294 jwrite32(jme, JME_TMCSR,
1295 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1296}
1297
1298static void
1299jme_stop_shutdown_timer(struct jme_adapter *jme)
1300{
1301 u32 apmc;
1302
1303 jwrite32f(jme, JME_TMCSR, 0);
1304 jwrite32f(jme, JME_TIMER2, 0);
1305 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1306
1307 apmc = jread32(jme, JME_APMC);
1308 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1309 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1310 wmb();
1311 jwrite32f(jme, JME_APMC, apmc);
1312}
1313
3bf61c55
GFT		 1314static void
1315jme_link_change_tasklet(unsigned long arg)
1316{
cd0ff491 1317 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1318 struct net_device *netdev = jme->dev;
fcf45b4c
GFT		 1319 int rc;
1320
cd0ff491
GFT		 1321 while (!atomic_dec_and_test(&jme->link_changing)) {
1322 atomic_inc(&jme->link_changing);
937ef75a 1323 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
58c92f28 1324 while (atomic_read(&jme->link_changing) != 1)
937ef75a 1325 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
cd0ff491 1326 }
fcf45b4c 1327
cd0ff491 1328 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1329 goto out;
1330
29bdd921 1331 jme->old_mtu = netdev->mtu;
fcf45b4c 1332 netif_stop_queue(netdev);
cd0ff491
GFT		 1333 if (jme_pseudo_hotplug_enabled(jme))
1334 jme_stop_shutdown_timer(jme);
1335
1336 jme_stop_pcc_timer(jme);
1337 tasklet_disable(&jme->txclean_task);
1338 tasklet_disable(&jme->rxclean_task);
1339 tasklet_disable(&jme->rxempty_task);
1340
1341 if (netif_carrier_ok(netdev)) {
cd0ff491
GFT		 1342 jme_disable_rx_engine(jme);
1343 jme_disable_tx_engine(jme);
fcf45b4c
GFT		 1344 jme_reset_mac_processor(jme);
1345 jme_free_rx_resources(jme);
1346 jme_free_tx_resources(jme);
192570e0 1347
cd0ff491 1348 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1349 jme_polling_mode(jme);
cd0ff491
GFT		 1350
1351 netif_carrier_off(netdev);
fcf45b4c
GFT		 1352 }
1353
1354 jme_check_link(netdev, 0);
cd0ff491 1355 if (netif_carrier_ok(netdev)) {
fcf45b4c 1356 rc = jme_setup_rx_resources(jme);
cd0ff491 1357 if (rc) {
937ef75a 1358 pr_err("Allocating resources for RX error, Device STOPPED!\n");
cd0ff491 1359 goto out_enable_tasklet;
fcf45b4c
GFT		 1360 }
1361
fcf45b4c 1362 rc = jme_setup_tx_resources(jme);
cd0ff491 1363 if (rc) {
937ef75a 1364 pr_err("Allocating resources for TX error, Device STOPPED!\n");
fcf45b4c
GFT		 1365 goto err_out_free_rx_resources;
1366 }
1367
1368 jme_enable_rx_engine(jme);
1369 jme_enable_tx_engine(jme);
1370
1371 netif_start_queue(netdev);
192570e0 1372
cd0ff491 1373 if (test_bit(JME_FLAG_POLL, &jme->flags))
192570e0 1374 jme_interrupt_mode(jme);
192570e0 1375
79ce639c 1376 jme_start_pcc_timer(jme);
cd0ff491
GFT		 1377 } else if (jme_pseudo_hotplug_enabled(jme)) {
1378 jme_start_shutdown_timer(jme);
fcf45b4c
GFT		 1379 }
1380
cd0ff491 1381 goto out_enable_tasklet;
fcf45b4c
GFT		 1382
1383err_out_free_rx_resources:
1384 jme_free_rx_resources(jme);
cd0ff491
GFT		 1385out_enable_tasklet:
1386 tasklet_enable(&jme->txclean_task);
1387 tasklet_hi_enable(&jme->rxclean_task);
1388 tasklet_hi_enable(&jme->rxempty_task);
fcf45b4c
GFT		 1389out:
1390 atomic_inc(&jme->link_changing);
3bf61c55 1391}
d7699f87 1392
3bf61c55
GFT		 1393static void
1394jme_rx_clean_tasklet(unsigned long arg)
1395{
cd0ff491 1396 struct jme_adapter *jme = (struct jme_adapter *)arg;
79ce639c 1397 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1398
192570e0
GFT		 1399 jme_process_receive(jme, jme->rx_ring_size);
1400 ++(dpi->intr_cnt);
42b1055e 1401
192570e0 1402}
fcf45b4c 1403
192570e0 1404static int
cdcdc9eb 1405jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
192570e0 1406{
cdcdc9eb 1407 struct jme_adapter *jme = jme_napi_priv(holder);
3b70a6fa 1408 DECLARE_NETDEV
192570e0 1409 int rest;
fcf45b4c 1410
cdcdc9eb 1411 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
fcf45b4c 1412
cd0ff491 1413 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb 1414 atomic_dec(&jme->rx_empty);
192570e0
GFT		 1415 ++(NET_STAT(jme).rx_dropped);
1416 jme_restart_rx_engine(jme);
1417 }
1418 atomic_inc(&jme->rx_empty);
1419
cd0ff491 1420 if (rest) {
cdcdc9eb 1421 JME_RX_COMPLETE(netdev, holder);
192570e0
GFT		 1422 jme_interrupt_mode(jme);
1423 }
1424
cdcdc9eb
GFT		 1425 JME_NAPI_WEIGHT_SET(budget, rest);
1426 return JME_NAPI_WEIGHT_VAL(budget) - rest;
fcf45b4c
GFT		 1427}
1428
1429static void
1430jme_rx_empty_tasklet(unsigned long arg)
1431{
cd0ff491 1432 struct jme_adapter *jme = (struct jme_adapter *)arg;
fcf45b4c 1433
cd0ff491 1434 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1435 return;
1436
cd0ff491 1437 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1438 return;
1439
7ca9ebee 1440 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
29bdd921 1441
fcf45b4c 1442 jme_rx_clean_tasklet(arg);
cdcdc9eb 1443
cd0ff491 1444 while (atomic_read(&jme->rx_empty) > 0) {
cdcdc9eb
GFT		 1445 atomic_dec(&jme->rx_empty);
1446 ++(NET_STAT(jme).rx_dropped);
1447 jme_restart_rx_engine(jme);
1448 }
1449 atomic_inc(&jme->rx_empty);
4330c2f2
GFT		 1450}
1451
b3821cc5
GFT		 1452static void
1453jme_wake_queue_if_stopped(struct jme_adapter *jme)
1454{
0ede469c 1455 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1456
1457 smp_wmb();
cd0ff491 1458 if (unlikely(netif_queue_stopped(jme->dev) &&
b3821cc5 1459 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
937ef75a 1460 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
b3821cc5 1461 netif_wake_queue(jme->dev);
b3821cc5
GFT		 1462 }
1463
1464}
1465
3bf61c55
GFT		 1466static void
1467jme_tx_clean_tasklet(unsigned long arg)
4330c2f2 1468{
cd0ff491 1469 struct jme_adapter *jme = (struct jme_adapter *)arg;
3bf61c55 1470 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1471 struct txdesc *txdesc = txring->desc;
3bf61c55 1472 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1473 int i, j, cnt = 0, max, err, mask;
3bf61c55 1474
937ef75a 1475 tx_dbg(jme, "Into txclean\n");
cd0ff491
GFT		 1476
1477 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1478 goto out;
1479
cd0ff491 1480 if (unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1481 goto out;
1482
cd0ff491 1483 if (unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1484 goto out;
1485
b3821cc5
GFT		 1486 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1487 mask = jme->tx_ring_mask;
3bf61c55 1488
cd0ff491 1489 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
3bf61c55
GFT		 1490
1491 ctxbi = txbi + i;
1492
cd0ff491 1493 if (likely(ctxbi->skb &&
b3821cc5 1494 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884 1495
cd0ff491 1496 tx_dbg(jme, "txclean: %d+%d@%lu\n",
937ef75a 1497 i, ctxbi->nr_desc, jiffies);
3bf61c55 1498
cd0ff491 1499 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55 1500
cd0ff491 1501 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1502 ttxbi = txbi + ((i + j) & (mask));
1503 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1504
b3821cc5 1505 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1506 ttxbi->mapping,
1507 ttxbi->len,
1508 PCI_DMA_TODEVICE);
1509
3bf61c55
GFT		 1510 ttxbi->mapping = 0;
1511 ttxbi->len = 0;
1512 }
1513
1514 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1515
1516 cnt += ctxbi->nr_desc;
1517
cd0ff491 1518 if (unlikely(err)) {
8c198884 1519 ++(NET_STAT(jme).tx_carrier_errors);
cd0ff491 1520 } else {
8c198884 1521 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1522 NET_STAT(jme).tx_bytes += ctxbi->len;
1523 }
1524
1525 ctxbi->skb = NULL;
1526 ctxbi->len = 0;
cdcdc9eb 1527 ctxbi->start_xmit = 0;
cd0ff491
GFT		 1528
1529 } else {
3bf61c55
GFT		 1530 break;
1531 }
1532
b3821cc5 1533 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1534
1535 ctxbi->nr_desc = 0;
d7699f87
GFT		 1536 }
1537
937ef75a 1538 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
cdcdc9eb 1539 atomic_set(&txring->next_to_clean, i);
79ce639c 1540 atomic_add(cnt, &txring->nr_free);
3bf61c55 1541
b3821cc5
GFT		 1542 jme_wake_queue_if_stopped(jme);
1543
fcf45b4c
GFT		 1544out:
1545 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1546}
1547
79ce639c 1548static void
cd0ff491 1549jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
d7699f87 1550{
3bf61c55
GFT		 1551 /*
1552 * Disable interrupt
1553 */
1554 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1555
cd0ff491 1556 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
47220951
GFT		 1557 /*
1558 * Link change event is critical
1559 * all other events are ignored
1560 */
1561 jwrite32(jme, JME_IEVE, intrstat);
3bf61c55 1562 tasklet_schedule(&jme->linkch_task);
29bdd921 1563 goto out_reenable;
fcf45b4c 1564 }
d7699f87 1565
cd0ff491 1566 if (intrstat & INTR_TMINTR) {
47220951 1567 jwrite32(jme, JME_IEVE, INTR_TMINTR);
79ce639c 1568 tasklet_schedule(&jme->pcc_task);
47220951 1569 }
79ce639c 1570
cd0ff491 1571 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
47220951 1572 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
4330c2f2 1573 tasklet_schedule(&jme->txclean_task);
47220951
GFT		 1574 }
1575
cd0ff491 1576 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
47220951
GFT		 1577 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1578 INTR_PCCRX0 |
1579 INTR_RX0EMP)) |
1580 INTR_RX0);
1581 }
d7699f87 1582
cd0ff491
GFT		 1583 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1584 if (intrstat & INTR_RX0EMP)
192570e0
GFT		 1585 atomic_inc(&jme->rx_empty);
1586
cd0ff491
GFT		 1587 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1588 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
192570e0 1589 jme_polling_mode(jme);
cdcdc9eb 1590 JME_RX_SCHEDULE(jme);
192570e0
GFT		 1591 }
1592 }
cd0ff491
GFT		 1593 } else {
1594 if (intrstat & INTR_RX0EMP) {
cdcdc9eb 1595 atomic_inc(&jme->rx_empty);
cd0ff491
GFT		 1596 tasklet_hi_schedule(&jme->rxempty_task);
1597 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1598 tasklet_hi_schedule(&jme->rxclean_task);
cdcdc9eb 1599 }
4330c2f2 1600 }
d7699f87 1601
29bdd921 1602out_reenable:
3bf61c55 1603 /*
fcf45b4c 1604 * Re-enable interrupt
3bf61c55 1605 */
fcf45b4c 1606 jwrite32f(jme, JME_IENS, INTR_ENABLE);
79ce639c
GFT		 1607}
1608
3b70a6fa
GFT		 1609#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1610static irqreturn_t
1611jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1612#else
79ce639c
GFT		 1613static irqreturn_t
1614jme_intr(int irq, void *dev_id)
3b70a6fa 1615#endif
79ce639c 1616{
cd0ff491
GFT		 1617 struct net_device *netdev = dev_id;
1618 struct jme_adapter *jme = netdev_priv(netdev);
1619 u32 intrstat;
79ce639c
GFT		 1620
1621 intrstat = jread32(jme, JME_IEVE);
1622
1623 /*
1624 * Check if it's really an interrupt for us
1625 */
7ee473a3 1626 if (unlikely((intrstat & INTR_ENABLE) == 0))
29bdd921 1627 return IRQ_NONE;
79ce639c
GFT		 1628
1629 /*
1630 * Check if the device still exist
1631 */
cd0ff491
GFT		 1632 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1633 return IRQ_NONE;
79ce639c
GFT		 1634
1635 jme_intr_msi(jme, intrstat);
1636
cd0ff491 1637 return IRQ_HANDLED;
d7699f87
GFT		 1638}
1639
3b70a6fa
GFT		 1640#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1641static irqreturn_t
1642jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1643#else
79ce639c
GFT		 1644static irqreturn_t
1645jme_msi(int irq, void *dev_id)
3b70a6fa 1646#endif
79ce639c 1647{
cd0ff491
GFT		 1648 struct net_device *netdev = dev_id;
1649 struct jme_adapter *jme = netdev_priv(netdev);
1650 u32 intrstat;
79ce639c 1651
0ede469c 1652 intrstat = jread32(jme, JME_IEVE);
79ce639c
GFT		 1653
1654 jme_intr_msi(jme, intrstat);
1655
cd0ff491 1656 return IRQ_HANDLED;
79ce639c
GFT		 1657}
1658
79ce639c
GFT		 1659static void
1660jme_reset_link(struct jme_adapter *jme)
1661{
1662 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1663}
1664
fcf45b4c
GFT		 1665static void
1666jme_restart_an(struct jme_adapter *jme)
1667{
cd0ff491 1668 u32 bmcr;
fcf45b4c 1669
cd0ff491 1670 spin_lock_bh(&jme->phy_lock);
fcf45b4c
GFT		 1671 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1672 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1673 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
cd0ff491 1674 spin_unlock_bh(&jme->phy_lock);
79ce639c
GFT		 1675}
1676
1677static int
1678jme_request_irq(struct jme_adapter *jme)
1679{
1680 int rc;
cd0ff491 1681 struct net_device *netdev = jme->dev;
3b70a6fa
GFT		 1682#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1683 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1684 int irq_flags = SA_SHIRQ;
1685#else
cd0ff491
GFT		 1686 irq_handler_t handler = jme_intr;
1687 int irq_flags = IRQF_SHARED;
3b70a6fa 1688#endif
cd0ff491
GFT		 1689
1690 if (!pci_enable_msi(jme->pdev)) {
1691 set_bit(JME_FLAG_MSI, &jme->flags);
1692 handler = jme_msi;
1693 irq_flags = 0;
1694 }
1695
1696 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1697 netdev);
1698 if (rc) {
937ef75a
JP		 1699 netdev_err(netdev,
1700 "Unable to request %s interrupt (return: %d)\n",
1701 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1702 rc);
79ce639c 1703
cd0ff491
GFT		 1704 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1705 pci_disable_msi(jme->pdev);
1706 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1707 }
cd0ff491 1708 } else {
79ce639c
GFT		 1709 netdev->irq = jme->pdev->irq;
1710 }
1711
cd0ff491 1712 return rc;
79ce639c
GFT		 1713}
1714
1715static void
1716jme_free_irq(struct jme_adapter *jme)
1717{
cd0ff491
GFT		 1718 free_irq(jme->pdev->irq, jme->dev);
1719 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1720 pci_disable_msi(jme->pdev);
1721 clear_bit(JME_FLAG_MSI, &jme->flags);
79ce639c 1722 jme->dev->irq = jme->pdev->irq;
cd0ff491 1723 }
fcf45b4c
GFT		 1724}
1725
ed457bcc
GFT		 1726static inline void
1727jme_new_phy_on(struct jme_adapter *jme)
1728{
1729 u32 reg;
1730
1731 reg = jread32(jme, JME_PHY_PWR);
1732 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1733 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1734 jwrite32(jme, JME_PHY_PWR, reg);
1735
1736 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1737 reg &= ~PE1_GPREG0_PBG;
1738 reg |= PE1_GPREG0_ENBG;
1739 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1740}
1741
1742static inline void
1743jme_new_phy_off(struct jme_adapter *jme)
1744{
1745 u32 reg;
1746
1747 reg = jread32(jme, JME_PHY_PWR);
1748 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1749 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1750 jwrite32(jme, JME_PHY_PWR, reg);
1751
1752 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1753 reg &= ~PE1_GPREG0_PBG;
1754 reg |= PE1_GPREG0_PDD3COLD;
1755 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1756}
1757
e58b908e
GFT		 1758static inline void
1759jme_phy_on(struct jme_adapter *jme)
1760{
1761 u32 bmcr;
1762
1763 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1764 bmcr &= ~BMCR_PDOWN;
1765 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
ed457bcc
GFT		 1766
1767 if (new_phy_power_ctrl(jme->chip_main_rev))
1768 jme_new_phy_on(jme);
1769}
1770
1771static inline void
1772jme_phy_off(struct jme_adapter *jme)
1773{
1774 u32 bmcr;
1775
1776 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1777 bmcr |= BMCR_PDOWN;
1778 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1779
1780 if (new_phy_power_ctrl(jme->chip_main_rev))
1781 jme_new_phy_off(jme);
e58b908e
GFT		 1782}
1783
3bf61c55
GFT		 1784static int
1785jme_open(struct net_device *netdev)
d7699f87
GFT		 1786{
1787 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 1788 int rc;
79ce639c 1789
42b1055e 1790 jme_clear_pm(jme);
cdcdc9eb 1791 JME_NAPI_ENABLE(jme);
d7699f87 1792
0ede469c 1793 tasklet_enable(&jme->linkch_task);
cd0ff491
GFT		 1794 tasklet_enable(&jme->txclean_task);
1795 tasklet_hi_enable(&jme->rxclean_task);
1796 tasklet_hi_enable(&jme->rxempty_task);
1797
79ce639c 1798 rc = jme_request_irq(jme);
cd0ff491 1799 if (rc)
4330c2f2 1800 goto err_out;
79ce639c 1801
d7699f87 1802 jme_start_irq(jme);
42b1055e 1803
ed457bcc
GFT		 1804 jme_phy_on(jme);
1805 if (test_bit(JME_FLAG_SSET, &jme->flags))
42b1055e 1806 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 1807 else
42b1055e
GFT		 1808 jme_reset_phy_processor(jme);
1809
29bdd921 1810 jme_reset_link(jme);
d7699f87
GFT		 1811
1812 return 0;
1813
d7699f87
GFT		 1814err_out:
1815 netif_stop_queue(netdev);
1816 netif_carrier_off(netdev);
4330c2f2 1817 return rc;
d7699f87
GFT		 1818}
1819
42b1055e
GFT		 1820static void
1821jme_set_100m_half(struct jme_adapter *jme)
1822{
cd0ff491 1823 u32 bmcr, tmp;
42b1055e 1824
a82e368c 1825 jme_phy_on(jme);
42b1055e
GFT		 1826 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1827 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1828 BMCR_SPEED1000 | BMCR_FULLDPLX);
1829 tmp |= BMCR_SPEED100;
1830
1831 if (bmcr != tmp)
1832 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1833
cd0ff491 1834 if (jme->fpgaver)
cdcdc9eb
GFT		 1835 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1836 else
1837 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
42b1055e
GFT		 1838}
1839
47220951
GFT		 1840#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1841static void
1842jme_wait_link(struct jme_adapter *jme)
1843{
cd0ff491 1844 u32 phylink, to = JME_WAIT_LINK_TIME;
47220951
GFT		 1845
1846 mdelay(1000);
1847 phylink = jme_linkstat_from_phy(jme);
cd0ff491 1848 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
47220951
GFT		 1849 mdelay(10);
1850 phylink = jme_linkstat_from_phy(jme);
1851 }
1852}
1853
a82e368c
GFT		 1854static void
1855jme_powersave_phy(struct jme_adapter *jme)
1856{
1857 if (jme->reg_pmcs) {
1858 jme_set_100m_half(jme);
a82e368c
GFT		 1859 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1860 jme_wait_link(jme);
61891ee4 1861 jme_clear_pm(jme);
a82e368c
GFT		 1862 } else {
1863 jme_phy_off(jme);
1864 }
1865}
1866
3bf61c55
GFT		 1867static int
1868jme_close(struct net_device *netdev)
d7699f87
GFT		 1869{
1870 struct jme_adapter *jme = netdev_priv(netdev);
1871
1872 netif_stop_queue(netdev);
1873 netif_carrier_off(netdev);
1874
1875 jme_stop_irq(jme);
79ce639c 1876 jme_free_irq(jme);
d7699f87 1877
cdcdc9eb 1878 JME_NAPI_DISABLE(jme);
192570e0 1879
0ede469c
GFT		 1880 tasklet_disable(&jme->linkch_task);
1881 tasklet_disable(&jme->txclean_task);
1882 tasklet_disable(&jme->rxclean_task);
1883 tasklet_disable(&jme->rxempty_task);
8c198884 1884
cd0ff491
GFT		 1885 jme_disable_rx_engine(jme);
1886 jme_disable_tx_engine(jme);
8c198884 1887 jme_reset_mac_processor(jme);
d7699f87
GFT		 1888 jme_free_rx_resources(jme);
1889 jme_free_tx_resources(jme);
42b1055e 1890 jme->phylink = 0;
b3821cc5
GFT		 1891 jme_phy_off(jme);
1892
1893 return 0;
1894}
1895
1896static int
1897jme_alloc_txdesc(struct jme_adapter *jme,
1898 struct sk_buff *skb)
1899{
0ede469c 1900 struct jme_ring *txring = &(jme->txring[0]);
b3821cc5
GFT		 1901 int idx, nr_alloc, mask = jme->tx_ring_mask;
1902
1903 idx = txring->next_to_use;
1904 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1905
cd0ff491 1906 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
b3821cc5
GFT		 1907 return -1;
1908
1909 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1910
b3821cc5
GFT		 1911 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1912
1913 return idx;
1914}
1915
1916static void
1917jme_fill_tx_map(struct pci_dev *pdev,
cd0ff491 1918 struct txdesc *txdesc,
b3821cc5
GFT		 1919 struct jme_buffer_info *txbi,
1920 struct page *page,
cd0ff491
GFT		 1921 u32 page_offset,
1922 u32 len,
1923 u8 hidma)
b3821cc5
GFT		 1924{
1925 dma_addr_t dmaaddr;
1926
1927 dmaaddr = pci_map_page(pdev,
1928 page,
1929 page_offset,
1930 len,
1931 PCI_DMA_TODEVICE);
1932
1933 pci_dma_sync_single_for_device(pdev,
1934 dmaaddr,
1935 len,
1936 PCI_DMA_TODEVICE);
1937
1938 txdesc->dw[0] = 0;
1939 txdesc->dw[1] = 0;
1940 txdesc->desc2.flags = TXFLAG_OWN;
cd0ff491 1941 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
b3821cc5
GFT		 1942 txdesc->desc2.datalen = cpu_to_le16(len);
1943 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1944 txdesc->desc2.bufaddrl = cpu_to_le32(
1945 (__u64)dmaaddr & 0xFFFFFFFFUL);
1946
1947 txbi->mapping = dmaaddr;
1948 txbi->len = len;
1949}
1950
1951static void
1952jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1953{
0ede469c 1954 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 1955 struct txdesc *txdesc = txring->desc, *ctxdesc;
b3821cc5 1956 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
cd0ff491 1957 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
b3821cc5
GFT		 1958 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1959 int mask = jme->tx_ring_mask;
1960 struct skb_frag_struct *frag;
cd0ff491 1961 u32 len;
b3821cc5 1962
cd0ff491
GFT		 1963 for (i = 0 ; i < nr_frags ; ++i) {
1964 frag = &skb_shinfo(skb)->frags[i];
b3821cc5
GFT		 1965 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1966 ctxbi = txbi + ((idx + i + 2) & (mask));
1967
1968 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1969 frag->page_offset, frag->size, hidma);
42b1055e 1970 }
b3821cc5 1971
cd0ff491 1972 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
b3821cc5
GFT		 1973 ctxdesc = txdesc + ((idx + 1) & (mask));
1974 ctxbi = txbi + ((idx + 1) & (mask));
1975 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1976 offset_in_page(skb->data), len, hidma);
1977
1978}
1979
1980static int
1981jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1982{
3b70a6fa 1983 if (unlikely(
0ede469c 1984#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 1985 skb_shinfo(skb)->tso_size
1986#else
1987 skb_shinfo(skb)->gso_size
1988#endif
1989 && skb_header_cloned(skb) &&
b3821cc5
GFT		 1990 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1991 dev_kfree_skb(skb);
1992 return -1;
1993 }
1994
1995 return 0;
1996}
1997
1998static int
3b70a6fa 1999jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
b3821cc5 2000{
0ede469c 2001#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
3b70a6fa
GFT		 2002 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2003#else
2004 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2005#endif
cd0ff491 2006 if (*mss) {
b3821cc5
GFT		 2007 *flags |= TXFLAG_LSEN;
2008
cd0ff491 2009 if (skb->protocol == htons(ETH_P_IP)) {
b3821cc5
GFT		 2010 struct iphdr *iph = ip_hdr(skb);
2011
2012 iph->check = 0;
cd0ff491 2013 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b3821cc5
GFT		 2014 iph->daddr, 0,
2015 IPPROTO_TCP,
2016 0);
cd0ff491 2017 } else {
b3821cc5
GFT		 2018 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2019
cd0ff491 2020 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
b3821cc5
GFT		 2021 &ip6h->daddr, 0,
2022 IPPROTO_TCP,
2023 0);
2024 }
2025
2026 return 0;
2027 }
2028
2029 return 1;
2030}
2031
2032static void
cd0ff491 2033jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
b3821cc5 2034{
3b70a6fa
GFT		 2035#ifdef CHECKSUM_PARTIAL
2036 if (skb->ip_summed == CHECKSUM_PARTIAL)
2037#else
2038 if (skb->ip_summed == CHECKSUM_HW)
2039#endif
2040 {
cd0ff491 2041 u8 ip_proto;
b3821cc5 2042
3b70a6fa
GFT		 2043#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2044 if (skb->protocol == htons(ETH_P_IP))
2045 ip_proto = ip_hdr(skb)->protocol;
2046 else if (skb->protocol == htons(ETH_P_IPV6))
2047 ip_proto = ipv6_hdr(skb)->nexthdr;
2048 else
2049 ip_proto = 0;
2050#else
b3821cc5 2051 switch (skb->protocol) {
cd0ff491 2052 case htons(ETH_P_IP):
b3821cc5
GFT		 2053 ip_proto = ip_hdr(skb)->protocol;
2054 break;
cd0ff491 2055 case htons(ETH_P_IPV6):
b3821cc5
GFT		 2056 ip_proto = ipv6_hdr(skb)->nexthdr;
2057 break;
2058 default:
2059 ip_proto = 0;
2060 break;
2061 }
3b70a6fa 2062#endif
b3821cc5 2063
cd0ff491 2064 switch (ip_proto) {
b3821cc5
GFT		 2065 case IPPROTO_TCP:
2066 *flags |= TXFLAG_TCPCS;
2067 break;
2068 case IPPROTO_UDP:
2069 *flags |= TXFLAG_UDPCS;
2070 break;
2071 default:
937ef75a 2072 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
b3821cc5
GFT		 2073 break;
2074 }
2075 }
2076}
2077
cd0ff491 2078static inline void
3b70a6fa 2079jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
b3821cc5 2080{
cd0ff491 2081 if (vlan_tx_tag_present(skb)) {
b3821cc5 2082 *flags |= TXFLAG_TAGON;
3b70a6fa 2083 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
42b1055e 2084 }
b3821cc5
GFT		 2085}
2086
2087static int
3b70a6fa 2088jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
b3821cc5 2089{
0ede469c 2090 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491 2091 struct txdesc *txdesc;
b3821cc5 2092 struct jme_buffer_info *txbi;
cd0ff491 2093 u8 flags;
b3821cc5 2094
cd0ff491 2095 txdesc = (struct txdesc *)txring->desc + idx;
b3821cc5
GFT		 2096 txbi = txring->bufinf + idx;
2097
2098 txdesc->dw[0] = 0;
2099 txdesc->dw[1] = 0;
2100 txdesc->dw[2] = 0;
2101 txdesc->dw[3] = 0;
2102 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2103 /*
2104 * Set OWN bit at final.
2105 * When kernel transmit faster than NIC.
2106 * And NIC trying to send this descriptor before we tell
2107 * it to start sending this TX queue.
2108 * Other fields are already filled correctly.
2109 */
2110 wmb();
2111 flags = TXFLAG_OWN | TXFLAG_INT;
cd0ff491
GFT		 2112 /*
2113 * Set checksum flags while not tso
2114 */
2115 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2116 jme_tx_csum(jme, skb, &flags);
b3821cc5 2117 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
3b70a6fa 2118 jme_map_tx_skb(jme, skb, idx);
b3821cc5
GFT		 2119 txdesc->desc1.flags = flags;
2120 /*
2121 * Set tx buffer info after telling NIC to send
2122 * For better tx_clean timing
2123 */
2124 wmb();
2125 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2126 txbi->skb = skb;
2127 txbi->len = skb->len;
cd0ff491
GFT		 2128 txbi->start_xmit = jiffies;
2129 if (!txbi->start_xmit)
8d27293f 2130 txbi->start_xmit = (0UL-1);
d7699f87
GFT		 2131
2132 return 0;
2133}
2134
b3821cc5
GFT		 2135static void
2136jme_stop_queue_if_full(struct jme_adapter *jme)
2137{
0ede469c 2138 struct jme_ring *txring = &(jme->txring[0]);
cd0ff491
GFT		 2139 struct jme_buffer_info *txbi = txring->bufinf;
2140 int idx = atomic_read(&txring->next_to_clean);
cdcdc9eb 2141
cd0ff491 2142 txbi += idx;
b3821cc5
GFT		 2143
2144 smp_wmb();
cd0ff491 2145 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
b3821cc5 2146 netif_stop_queue(jme->dev);
937ef75a 2147 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
b3821cc5 2148 smp_wmb();
cd0ff491
GFT		 2149 if (atomic_read(&txring->nr_free)
2150 >= (jme->tx_wake_threshold)) {
b3821cc5 2151 netif_wake_queue(jme->dev);
937ef75a 2152 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
b3821cc5
GFT		 2153 }
2154 }
2155
cd0ff491 2156 if (unlikely(txbi->start_xmit &&
cdcdc9eb
GFT		 2157 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2158 txbi->skb)) {
2159 netif_stop_queue(jme->dev);
e3b96dc9
GFT		 2160 netif_info(jme, tx_queued, jme->dev,
2161 "TX Queue Stopped %d@%lu\n", idx, jiffies);
cdcdc9eb 2162 }
b3821cc5
GFT		 2163}
2164
3bf61c55
GFT		 2165/*
2166 * This function is already protected by netif_tx_lock()
2167 */
cd0ff491 2168
7ca9ebee 2169#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
3bf61c55 2170static int
7ca9ebee
GFT		 2171#else
2172static netdev_tx_t
2173#endif
3bf61c55 2174jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87 2175{
cd0ff491 2176 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2177 int idx;
d7699f87 2178
cd0ff491 2179 if (unlikely(jme_expand_header(jme, skb))) {
b3821cc5
GFT		 2180 ++(NET_STAT(jme).tx_dropped);
2181 return NETDEV_TX_OK;
2182 }
2183
2184 idx = jme_alloc_txdesc(jme, skb);
79ce639c 2185
cd0ff491 2186 if (unlikely(idx < 0)) {
b3821cc5 2187 netif_stop_queue(netdev);
937ef75a
JP		 2188 netif_err(jme, tx_err, jme->dev,
2189 "BUG! Tx ring full when queue awake!\n");
d7699f87 2190
cd0ff491 2191 return NETDEV_TX_BUSY;
b3821cc5
GFT		 2192 }
2193
3b70a6fa 2194 jme_fill_tx_desc(jme, skb, idx);
b3821cc5 2195
4330c2f2
GFT		 2196 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2197 TXCS_SELECT_QUEUE0 |
2198 TXCS_QUEUE0S |
2199 TXCS_ENABLE);
0ede469c 2200#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
d7699f87 2201 netdev->trans_start = jiffies;
0ede469c 2202#endif
d7699f87 2203
937ef75a
JP		 2204 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2205 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
b3821cc5
GFT		 2206 jme_stop_queue_if_full(jme);
2207
cd0ff491 2208 return NETDEV_TX_OK;
d7699f87
GFT		 2209}
2210
e523cd89
GFT		 2211static void
2212jme_set_unicastaddr(struct net_device *netdev)
2213{
2214 struct jme_adapter *jme = netdev_priv(netdev);
2215 u32 val;
2216
2217 val = (netdev->dev_addr[3] & 0xff) << 24 |
2218 (netdev->dev_addr[2] & 0xff) << 16 |
2219 (netdev->dev_addr[1] & 0xff) << 8 |
2220 (netdev->dev_addr[0] & 0xff);
2221 jwrite32(jme, JME_RXUMA_LO, val);
2222 val = (netdev->dev_addr[5] & 0xff) << 8 |
2223 (netdev->dev_addr[4] & 0xff);
2224 jwrite32(jme, JME_RXUMA_HI, val);
2225}
2226
3bf61c55
GFT		 2227static int
2228jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87 2229{
cd0ff491 2230 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2231 struct sockaddr *addr = p;
d7699f87 2232
cd0ff491 2233 if (netif_running(netdev))
d7699f87
GFT		 2234 return -EBUSY;
2235
cd0ff491 2236 spin_lock_bh(&jme->macaddr_lock);
d7699f87 2237 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
e523cd89 2238 jme_set_unicastaddr(netdev);
cd0ff491 2239 spin_unlock_bh(&jme->macaddr_lock);
d7699f87
GFT		 2240
2241 return 0;
2242}
2243
3bf61c55
GFT		 2244static void
2245jme_set_multi(struct net_device *netdev)
d7699f87 2246{
3bf61c55 2247 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2248 u32 mc_hash[2] = {};
7ca9ebee 2249#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
d7699f87 2250 int i;
7ca9ebee 2251#endif
d7699f87 2252
cd0ff491 2253 spin_lock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2254
2255 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 2256
cd0ff491 2257 if (netdev->flags & IFF_PROMISC) {
8c198884 2258 jme->reg_rxmcs |= RXMCS_ALLFRAME;
cd0ff491 2259 } else if (netdev->flags & IFF_ALLMULTI) {
8c198884 2260 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
cd0ff491 2261 } else if (netdev->flags & IFF_MULTICAST) {
8e14c278 2262#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
3bf61c55 2263 struct dev_mc_list *mclist;
8e14c278
JP		 2264#else
2265 struct netdev_hw_addr *ha;
2266#endif
3bf61c55 2267 int bit_nr;
d7699f87 2268
8c198884 2269 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
7ca9ebee 2270#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
3bf61c55
GFT		 2271 for (i = 0, mclist = netdev->mc_list;
2272 mclist && i < netdev->mc_count;
2273 ++i, mclist = mclist->next) {
8e14c278 2274#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
7ca9ebee 2275 netdev_for_each_mc_addr(mclist, netdev) {
8e14c278
JP		 2276#else
2277 netdev_for_each_mc_addr(ha, netdev) {
7ca9ebee 2278#endif
8e14c278 2279#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
cd0ff491 2280 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
8e14c278
JP		 2281#else
2282 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2283#endif
cd0ff491
GFT		 2284 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2285 }
d7699f87 2286
4330c2f2
GFT		 2287 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2288 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 2289 }
2290
d7699f87 2291 wmb();
8c198884
GFT		 2292 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2293
cd0ff491 2294 spin_unlock_bh(&jme->rxmcs_lock);
d7699f87
GFT		 2295}
2296
3bf61c55 2297static int
8c198884 2298jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 2299{
cd0ff491 2300 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2301
cd0ff491 2302 if (new_mtu == jme->old_mtu)
29bdd921
GFT		 2303 return 0;
2304
cd0ff491
GFT		 2305 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2306 ((new_mtu) < IPV6_MIN_MTU))
2307 return -EINVAL;
79ce639c 2308
cd0ff491 2309 if (new_mtu > 4000) {
79ce639c
GFT		 2310 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2311 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2312 jme_restart_rx_engine(jme);
cd0ff491 2313 } else {
79ce639c
GFT		 2314 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2315 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2316 jme_restart_rx_engine(jme);
2317 }
2318
cd0ff491 2319 if (new_mtu > 1900) {
1a0b42f4
MM		 2320 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2321 NETIF_F_TSO | NETIF_F_TSO6);
cd0ff491
GFT		 2322 } else {
2323 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
1a0b42f4 2324 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491 2325 if (test_bit(JME_FLAG_TSO, &jme->flags))
1a0b42f4 2326 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT		 2327 }
2328
cd0ff491
GFT		 2329 netdev->mtu = new_mtu;
2330 jme_reset_link(jme);
79ce639c
GFT		 2331
2332 return 0;
d7699f87
GFT		 2333}
2334
8c198884
GFT		 2335static void
2336jme_tx_timeout(struct net_device *netdev)
2337{
cd0ff491 2338 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 2339
cdcdc9eb
GFT		 2340 jme->phylink = 0;
2341 jme_reset_phy_processor(jme);
cd0ff491 2342 if (test_bit(JME_FLAG_SSET, &jme->flags))
cdcdc9eb
GFT		 2343 jme_set_settings(netdev, &jme->old_ecmd);
2344
8c198884 2345 /*
cdcdc9eb 2346 * Force to Reset the link again
8c198884 2347 */
29bdd921 2348 jme_reset_link(jme);
8c198884
GFT		 2349}
2350
1e5ebebc
GFT		 2351static inline void jme_pause_rx(struct jme_adapter *jme)
2352{
2353 atomic_dec(&jme->link_changing);
2354
2355 jme_set_rx_pcc(jme, PCC_OFF);
2356 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2357 JME_NAPI_DISABLE(jme);
2358 } else {
2359 tasklet_disable(&jme->rxclean_task);
2360 tasklet_disable(&jme->rxempty_task);
2361 }
2362}
2363
2364static inline void jme_resume_rx(struct jme_adapter *jme)
2365{
2366 struct dynpcc_info *dpi = &(jme->dpi);
2367
2368 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2369 JME_NAPI_ENABLE(jme);
2370 } else {
2371 tasklet_hi_enable(&jme->rxclean_task);
2372 tasklet_hi_enable(&jme->rxempty_task);
2373 }
2374 dpi->cur = PCC_P1;
2375 dpi->attempt = PCC_P1;
2376 dpi->cnt = 0;
2377 jme_set_rx_pcc(jme, PCC_P1);
2378
2379 atomic_inc(&jme->link_changing);
2380}
2381
42b1055e
GFT		 2382static void
2383jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2384{
2385 struct jme_adapter *jme = netdev_priv(netdev);
2386
1e5ebebc 2387 jme_pause_rx(jme);
42b1055e 2388 jme->vlgrp = grp;
1e5ebebc 2389 jme_resume_rx(jme);
42b1055e
GFT		 2390}
2391
7ca9ebee
GFT		 2392#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2393static void
2394jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2395{
2396 struct jme_adapter *jme = netdev_priv(netdev);
2397
7ca9ebee 2398 if(jme->vlgrp) {
1e5ebebc 2399 jme_pause_rx(jme);
7ca9ebee
GFT		 2400#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2401 jme->vlgrp->vlan_devices[vid] = NULL;
2402#else
2403 vlan_group_set_device(jme->vlgrp, vid, NULL);
2404#endif
1e5ebebc 2405 jme_resume_rx(jme);
7ca9ebee 2406 }
7ca9ebee
GFT		 2407}
2408#endif
2409
3bf61c55
GFT		 2410static void
2411jme_get_drvinfo(struct net_device *netdev,
2412 struct ethtool_drvinfo *info)
d7699f87 2413{
cd0ff491 2414 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 2415
cd0ff491
GFT		 2416 strcpy(info->driver, DRV_NAME);
2417 strcpy(info->version, DRV_VERSION);
2418 strcpy(info->bus_info, pci_name(jme->pdev));
d7699f87
GFT		 2419}
2420
8c198884
GFT		 2421static int
2422jme_get_regs_len(struct net_device *netdev)
2423{
cd0ff491 2424 return JME_REG_LEN;
8c198884
GFT		 2425}
2426
2427static void
cd0ff491 2428mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
8c198884
GFT		 2429{
2430 int i;
2431
cd0ff491 2432 for (i = 0 ; i < len ; i += 4)
79ce639c 2433 p[i >> 2] = jread32(jme, reg + i);
186fc259 2434}
8c198884 2435
186fc259 2436static void
cd0ff491 2437mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
186fc259
GFT		 2438{
2439 int i;
cd0ff491 2440 u16 *p16 = (u16 *)p;
186fc259 2441
cd0ff491 2442 for (i = 0 ; i < reg_nr ; ++i)
186fc259 2443 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
8c198884
GFT		 2444}
2445
2446static void
2447jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2448{
cd0ff491
GFT		 2449 struct jme_adapter *jme = netdev_priv(netdev);
2450 u32 *p32 = (u32 *)p;
8c198884 2451
186fc259 2452 memset(p, 0xFF, JME_REG_LEN);
8c198884
GFT		 2453
2454 regs->version = 1;
2455 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2456
2457 p32 += 0x100 >> 2;
2458 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2459
2460 p32 += 0x100 >> 2;
2461 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2462
2463 p32 += 0x100 >> 2;
2464 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2465
186fc259
GFT		 2466 p32 += 0x100 >> 2;
2467 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
8c198884
GFT		 2468}
2469
2470static int
2471jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2472{
2473 struct jme_adapter *jme = netdev_priv(netdev);
2474
8c198884
GFT		 2475 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2476 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2477
cd0ff491 2478 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
cdcdc9eb
GFT		 2479 ecmd->use_adaptive_rx_coalesce = false;
2480 ecmd->rx_coalesce_usecs = 0;
2481 ecmd->rx_max_coalesced_frames = 0;
2482 return 0;
2483 }
2484
2485 ecmd->use_adaptive_rx_coalesce = true;
2486
cd0ff491 2487 switch (jme->dpi.cur) {
8c198884
GFT		 2488 case PCC_P1:
2489 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2490 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2491 break;
2492 case PCC_P2:
2493 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2494 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2495 break;
2496 case PCC_P3:
2497 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2498 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2499 break;
2500 default:
2501 break;
2502 }
2503
2504 return 0;
2505}
2506
192570e0
GFT		 2507static int
2508jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2509{
2510 struct jme_adapter *jme = netdev_priv(netdev);
2511 struct dynpcc_info *dpi = &(jme->dpi);
2512
cd0ff491 2513 if (netif_running(netdev))
cdcdc9eb
GFT		 2514 return -EBUSY;
2515
7ca9ebee
GFT		 2516 if (ecmd->use_adaptive_rx_coalesce &&
2517 test_bit(JME_FLAG_POLL, &jme->flags)) {
cd0ff491 2518 clear_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2519 jme->jme_rx = netif_rx;
2520 jme->jme_vlan_rx = vlan_hwaccel_rx;
192570e0
GFT		 2521 dpi->cur = PCC_P1;
2522 dpi->attempt = PCC_P1;
2523 dpi->cnt = 0;
2524 jme_set_rx_pcc(jme, PCC_P1);
2525 jme_interrupt_mode(jme);
7ca9ebee
GFT		 2526 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2527 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
cd0ff491 2528 set_bit(JME_FLAG_POLL, &jme->flags);
cdcdc9eb
GFT		 2529 jme->jme_rx = netif_receive_skb;
2530 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
192570e0
GFT		 2531 jme_interrupt_mode(jme);
2532 }
2533
2534 return 0;
2535}
2536
8c198884
GFT		 2537static void
2538jme_get_pauseparam(struct net_device *netdev,
2539 struct ethtool_pauseparam *ecmd)
2540{
2541 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2542 u32 val;
8c198884
GFT		 2543
2544 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2545 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2546
cd0ff491
GFT		 2547 spin_lock_bh(&jme->phy_lock);
2548 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2549 spin_unlock_bh(&jme->phy_lock);
b3821cc5
GFT		 2550
2551 ecmd->autoneg =
2552 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2553}
2554
2555static int
2556jme_set_pauseparam(struct net_device *netdev,
2557 struct ethtool_pauseparam *ecmd)
2558{
2559 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2560 u32 val;
8c198884 2561
cd0ff491 2562 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
8c198884
GFT		 2563 (ecmd->tx_pause != 0)) {
2564
cd0ff491 2565 if (ecmd->tx_pause)
8c198884
GFT		 2566 jme->reg_txpfc |= TXPFC_PF_EN;
2567 else
2568 jme->reg_txpfc &= ~TXPFC_PF_EN;
2569
2570 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2571 }
2572
cd0ff491
GFT		 2573 spin_lock_bh(&jme->rxmcs_lock);
2574 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
8c198884
GFT		 2575 (ecmd->rx_pause != 0)) {
2576
cd0ff491 2577 if (ecmd->rx_pause)
8c198884
GFT		 2578 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2579 else
2580 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2581
2582 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2583 }
cd0ff491 2584 spin_unlock_bh(&jme->rxmcs_lock);
8c198884 2585
cd0ff491
GFT		 2586 spin_lock_bh(&jme->phy_lock);
2587 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2588 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
8c198884
GFT		 2589 (ecmd->autoneg != 0)) {
2590
cd0ff491 2591 if (ecmd->autoneg)
8c198884
GFT		 2592 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2593 else
2594 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2595
b3821cc5
GFT		 2596 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2597 MII_ADVERTISE, val);
8c198884 2598 }
cd0ff491 2599 spin_unlock_bh(&jme->phy_lock);
8c198884
GFT		 2600
2601 return 0;
2602}
2603
29bdd921
GFT		 2604static void
2605jme_get_wol(struct net_device *netdev,
2606 struct ethtool_wolinfo *wol)
2607{
2608 struct jme_adapter *jme = netdev_priv(netdev);
2609
2610 wol->supported = WAKE_MAGIC | WAKE_PHY;
2611
2612 wol->wolopts = 0;
2613
cd0ff491 2614 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
29bdd921
GFT		 2615 wol->wolopts |= WAKE_PHY;
2616
cd0ff491 2617 if (jme->reg_pmcs & PMCS_MFEN)
29bdd921
GFT		 2618 wol->wolopts |= WAKE_MAGIC;
2619
2620}
2621
2622static int
2623jme_set_wol(struct net_device *netdev,
2624 struct ethtool_wolinfo *wol)
2625{
2626 struct jme_adapter *jme = netdev_priv(netdev);
2627
cd0ff491 2628 if (wol->wolopts & (WAKE_MAGICSECURE |
29bdd921
GFT		 2629 WAKE_UCAST |
2630 WAKE_MCAST |
2631 WAKE_BCAST |
2632 WAKE_ARP))
2633 return -EOPNOTSUPP;
2634
2635 jme->reg_pmcs = 0;
2636
cd0ff491 2637 if (wol->wolopts & WAKE_PHY)
29bdd921
GFT		 2638 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2639
cd0ff491 2640 if (wol->wolopts & WAKE_MAGIC)
29bdd921
GFT		 2641 jme->reg_pmcs |= PMCS_MFEN;
2642
cd0ff491 2643 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3d12cc1b
GFT		 2644#ifndef JME_NEW_PM_API
2645 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2646#endif
7370b85a 2647#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3d12cc1b 2648 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
7370b85a 2649#endif
e3b96dc9 2650
29bdd921
GFT		 2651 return 0;
2652}
b3821cc5 2653
3bf61c55
GFT		 2654static int
2655jme_get_settings(struct net_device *netdev,
2656 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2657{
2658 struct jme_adapter *jme = netdev_priv(netdev);
2659 int rc;
8c198884 2660
cd0ff491 2661 spin_lock_bh(&jme->phy_lock);
d7699f87 2662 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
cd0ff491 2663 spin_unlock_bh(&jme->phy_lock);
d7699f87
GFT		 2664 return rc;
2665}
2666
3bf61c55
GFT		 2667static int
2668jme_set_settings(struct net_device *netdev,
2669 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2670{
2671 struct jme_adapter *jme = netdev_priv(netdev);
cd0ff491 2672 int rc, fdc = 0;
fcf45b4c 2673
8588b84b
DD		 2674 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2675 && ecmd->autoneg != AUTONEG_ENABLE)
8c198884
GFT		 2676 return -EINVAL;
2677
e6b41b51
GFT		 2678 /*
2679 * Check If user changed duplex only while force_media.
2680 * Hardware would not generate link change interrupt.
2681 */
cd0ff491 2682 if (jme->mii_if.force_media &&
79ce639c
GFT		 2683 ecmd->autoneg != AUTONEG_ENABLE &&
2684 (jme->mii_if.full_duplex != ecmd->duplex))
2685 fdc = 1;
2686
cd0ff491 2687 spin_lock_bh(&jme->phy_lock);
d7699f87 2688 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
cd0ff491 2689 spin_unlock_bh(&jme->phy_lock);
fcf45b4c 2690
cd0ff491 2691 if (!rc) {
e6b41b51
GFT		 2692 if (fdc)
2693 jme_reset_link(jme);
29bdd921 2694 jme->old_ecmd = *ecmd;
aa1e7189
GFT		 2695 set_bit(JME_FLAG_SSET, &jme->flags);
2696 }
2697
2698 return rc;
2699}
2700
2701static int
2702jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2703{
2704 int rc;
2705 struct jme_adapter *jme = netdev_priv(netdev);
2706 struct mii_ioctl_data *mii_data = if_mii(rq);
2707 unsigned int duplex_chg;
2708
2709 if (cmd == SIOCSMIIREG) {
2710 u16 val = mii_data->val_in;
2711 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2712 (val & BMCR_SPEED1000))
2713 return -EINVAL;
2714 }
2715
2716 spin_lock_bh(&jme->phy_lock);
2717 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2718 spin_unlock_bh(&jme->phy_lock);
2719
2720 if (!rc && (cmd == SIOCSMIIREG)) {
2721 if (duplex_chg)
2722 jme_reset_link(jme);
2723 jme_get_settings(netdev, &jme->old_ecmd);
2724 set_bit(JME_FLAG_SSET, &jme->flags);
29bdd921
GFT		 2725 }
2726
d7699f87
GFT		 2727 return rc;
2728}
2729
cd0ff491 2730static u32
3bf61c55
GFT		 2731jme_get_link(struct net_device *netdev)
2732{
d7699f87
GFT		 2733 struct jme_adapter *jme = netdev_priv(netdev);
2734 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2735}
2736
8c198884 2737static u32
cd0ff491
GFT		 2738jme_get_msglevel(struct net_device *netdev)
2739{
2740 struct jme_adapter *jme = netdev_priv(netdev);
2741 return jme->msg_enable;
2742}
2743
2744static void
2745jme_set_msglevel(struct net_device *netdev, u32 value)
8c198884 2746{
cd0ff491
GFT		 2747 struct jme_adapter *jme = netdev_priv(netdev);
2748 jme->msg_enable = value;
2749}
8c198884 2750
cd0ff491
GFT		 2751static u32
2752jme_get_rx_csum(struct net_device *netdev)
2753{
2754 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2755 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2756}
2757
2758static int
2759jme_set_rx_csum(struct net_device *netdev, u32 on)
2760{
cd0ff491 2761 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2762
cd0ff491
GFT		 2763 spin_lock_bh(&jme->rxmcs_lock);
2764 if (on)
8c198884
GFT		 2765 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2766 else
2767 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2768 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
cd0ff491 2769 spin_unlock_bh(&jme->rxmcs_lock);
8c198884
GFT		 2770
2771 return 0;
2772}
2773
2774static int
2775jme_set_tx_csum(struct net_device *netdev, u32 on)
2776{
cd0ff491 2777 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2778
cd0ff491
GFT		 2779 if (on) {
2780 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2781 if (netdev->mtu <= 1900)
1a0b42f4
MM		 2782 netdev->features |=
2783 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
cd0ff491
GFT		 2784 } else {
2785 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
1a0b42f4
MM		 2786 netdev->features &=
2787 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
b3821cc5 2788 }
8c198884
GFT		 2789
2790 return 0;
2791}
2792
b3821cc5
GFT		 2793static int
2794jme_set_tso(struct net_device *netdev, u32 on)
2795{
cd0ff491 2796 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 2797
cd0ff491
GFT		 2798 if (on) {
2799 set_bit(JME_FLAG_TSO, &jme->flags);
2800 if (netdev->mtu <= 1900)
1a0b42f4 2801 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
cd0ff491
GFT		 2802 } else {
2803 clear_bit(JME_FLAG_TSO, &jme->flags);
1a0b42f4 2804 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
b3821cc5
GFT		 2805 }
2806
cd0ff491 2807 return 0;
b3821cc5
GFT		 2808}
2809
8c198884
GFT		 2810static int
2811jme_nway_reset(struct net_device *netdev)
2812{
cd0ff491 2813 struct jme_adapter *jme = netdev_priv(netdev);
8c198884
GFT		 2814 jme_restart_an(jme);
2815 return 0;
2816}
2817
cd0ff491 2818static u8
186fc259
GFT		 2819jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2820{
cd0ff491 2821 u32 val;
186fc259
GFT		 2822 int to;
2823
2824 val = jread32(jme, JME_SMBCSR);
2825 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2826 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2827 msleep(1);
2828 val = jread32(jme, JME_SMBCSR);
2829 }
cd0ff491 2830 if (!to) {
937ef75a 2831 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2832 return 0xFF;
2833 }
2834
2835 jwrite32(jme, JME_SMBINTF,
2836 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2837 SMBINTF_HWRWN_READ |
2838 SMBINTF_HWCMD);
2839
2840 val = jread32(jme, JME_SMBINTF);
2841 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2842 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2843 msleep(1);
2844 val = jread32(jme, JME_SMBINTF);
2845 }
cd0ff491 2846 if (!to) {
937ef75a 2847 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2848 return 0xFF;
2849 }
2850
2851 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2852}
2853
2854static void
cd0ff491 2855jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
186fc259 2856{
cd0ff491 2857 u32 val;
186fc259
GFT		 2858 int to;
2859
2860 val = jread32(jme, JME_SMBCSR);
2861 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2862 while ((val & SMBCSR_BUSY) && --to) {
186fc259
GFT		 2863 msleep(1);
2864 val = jread32(jme, JME_SMBCSR);
2865 }
cd0ff491 2866 if (!to) {
937ef75a 2867 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2868 return;
2869 }
2870
2871 jwrite32(jme, JME_SMBINTF,
2872 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2873 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2874 SMBINTF_HWRWN_WRITE |
2875 SMBINTF_HWCMD);
2876
2877 val = jread32(jme, JME_SMBINTF);
2878 to = JME_SMB_BUSY_TIMEOUT;
cd0ff491 2879 while ((val & SMBINTF_HWCMD) && --to) {
186fc259
GFT		 2880 msleep(1);
2881 val = jread32(jme, JME_SMBINTF);
2882 }
cd0ff491 2883 if (!to) {
937ef75a 2884 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
186fc259
GFT		 2885 return;
2886 }
2887
2888 mdelay(2);
2889}
2890
2891static int
2892jme_get_eeprom_len(struct net_device *netdev)
2893{
cd0ff491
GFT		 2894 struct jme_adapter *jme = netdev_priv(netdev);
2895 u32 val;
186fc259 2896 val = jread32(jme, JME_SMBCSR);
cd0ff491 2897 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
186fc259
GFT		 2898}
2899
2900static int
2901jme_get_eeprom(struct net_device *netdev,
2902 struct ethtool_eeprom *eeprom, u8 *data)
2903{
cd0ff491 2904 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2905 int i, offset = eeprom->offset, len = eeprom->len;
2906
2907 /*
8d27293f 2908 * ethtool will check the boundary for us
186fc259
GFT		 2909 */
2910 eeprom->magic = JME_EEPROM_MAGIC;
cd0ff491 2911 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2912 data[i] = jme_smb_read(jme, i + offset);
2913
2914 return 0;
2915}
2916
2917static int
2918jme_set_eeprom(struct net_device *netdev,
2919 struct ethtool_eeprom *eeprom, u8 *data)
2920{
cd0ff491 2921 struct jme_adapter *jme = netdev_priv(netdev);
186fc259
GFT		 2922 int i, offset = eeprom->offset, len = eeprom->len;
2923
2924 if (eeprom->magic != JME_EEPROM_MAGIC)
2925 return -EINVAL;
2926
2927 /*
8d27293f 2928 * ethtool will check the boundary for us
186fc259 2929 */
cd0ff491 2930 for (i = 0 ; i < len ; ++i)
186fc259
GFT		 2931 jme_smb_write(jme, i + offset, data[i]);
2932
2933 return 0;
2934}
2935
3b70a6fa
GFT		 2936#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2937static struct ethtool_ops jme_ethtool_ops = {
2938#else
d7699f87 2939static const struct ethtool_ops jme_ethtool_ops = {
3b70a6fa 2940#endif
cd0ff491 2941 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 2942 .get_regs_len = jme_get_regs_len,
2943 .get_regs = jme_get_regs,
2944 .get_coalesce = jme_get_coalesce,
192570e0 2945 .set_coalesce = jme_set_coalesce,
cd0ff491
GFT		 2946 .get_pauseparam = jme_get_pauseparam,
2947 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 2948 .get_wol = jme_get_wol,
2949 .set_wol = jme_set_wol,
d7699f87
GFT		 2950 .get_settings = jme_get_settings,
2951 .set_settings = jme_set_settings,
2952 .get_link = jme_get_link,
cd0ff491
GFT		 2953 .get_msglevel = jme_get_msglevel,
2954 .set_msglevel = jme_set_msglevel,
8c198884
GFT		 2955 .get_rx_csum = jme_get_rx_csum,
2956 .set_rx_csum = jme_set_rx_csum,
2957 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT		 2958 .set_tso = jme_set_tso,
2959 .set_sg = ethtool_op_set_sg,
8c198884 2960 .nway_reset = jme_nway_reset,
186fc259
GFT		 2961 .get_eeprom_len = jme_get_eeprom_len,
2962 .get_eeprom = jme_get_eeprom,
2963 .set_eeprom = jme_set_eeprom,
d7699f87
GFT		 2964};
2965
3bf61c55
GFT		 2966static int
2967jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2968{
3b70a6fa 2969 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 2970#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2971 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2972#else
2973 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2974#endif
2975 )
2976#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2977 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2978#else
cd0ff491 2979 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
0ede469c 2980#endif
3bf61c55
GFT		 2981 return 1;
2982
3b70a6fa 2983 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
0ede469c
GFT		 2984#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2985 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2986#else
2987 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2988#endif
2989 )
2990#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2991 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2992#else
cd0ff491 2993 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
0ede469c 2994#endif
8c198884
GFT		 2995 return 1;
2996
0ede469c
GFT		 2997#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2998 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2999 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3000#else
cd0ff491
GFT		 3001 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3002 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
0ede469c 3003#endif
3bf61c55
GFT		 3004 return 0;
3005
3006 return -1;
3007}
3008
cd0ff491 3009static inline void
cdcdc9eb
GFT		 3010jme_phy_init(struct jme_adapter *jme)
3011{
cd0ff491 3012 u16 reg26;
cdcdc9eb
GFT		 3013
3014 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3015 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3016}
3017
cd0ff491 3018static inline void
cdcdc9eb 3019jme_check_hw_ver(struct jme_adapter *jme)
42b1055e 3020{
cd0ff491 3021 u32 chipmode;
cdcdc9eb
GFT		 3022
3023 chipmode = jread32(jme, JME_CHIPMODE);
3024
3025 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
58c92f28 3026 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
98ef18f1
GFT		 3027 jme->chip_main_rev = jme->chiprev & 0xF;
3028 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
42b1055e
GFT		 3029}
3030
3b70a6fa
GFT		 3031#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3032static const struct net_device_ops jme_netdev_ops = {
3033 .ndo_open = jme_open,
3034 .ndo_stop = jme_close,
3035 .ndo_validate_addr = eth_validate_addr,
aa1e7189 3036 .ndo_do_ioctl = jme_ioctl,
3b70a6fa
GFT		 3037 .ndo_start_xmit = jme_start_xmit,
3038 .ndo_set_mac_address = jme_set_macaddr,
3039 .ndo_set_multicast_list = jme_set_multi,
3040 .ndo_change_mtu = jme_change_mtu,
3041 .ndo_tx_timeout = jme_tx_timeout,
3042 .ndo_vlan_rx_register = jme_vlan_rx_register,
3043};
3044#endif
3045
3bf61c55
GFT		 3046static int __devinit
3047jme_init_one(struct pci_dev *pdev,
3048 const struct pci_device_id *ent)
3049{
cdcdc9eb 3050 int rc = 0, using_dac, i;
d7699f87
GFT		 3051 struct net_device *netdev;
3052 struct jme_adapter *jme;
cd0ff491
GFT		 3053 u16 bmcr, bmsr;
3054 u32 apmc;
d7699f87
GFT		 3055
3056 /*
3057 * set up PCI device basics
3058 */
4330c2f2 3059 rc = pci_enable_device(pdev);
cd0ff491 3060 if (rc) {
937ef75a 3061 pr_err("Cannot enable PCI device\n");
4330c2f2
GFT		 3062 goto err_out;
3063 }
d7699f87 3064
3bf61c55 3065 using_dac = jme_pci_dma64(pdev);
cd0ff491 3066 if (using_dac < 0) {
937ef75a 3067 pr_err("Cannot set PCI DMA Mask\n");
3bf61c55
GFT		 3068 rc = -EIO;
3069 goto err_out_disable_pdev;
3070 }
3071
cd0ff491 3072 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
937ef75a 3073 pr_err("No PCI resource region found\n");
4330c2f2
GFT		 3074 rc = -ENOMEM;
3075 goto err_out_disable_pdev;
3076 }
d7699f87 3077
4330c2f2 3078 rc = pci_request_regions(pdev, DRV_NAME);
cd0ff491 3079 if (rc) {
937ef75a 3080 pr_err("Cannot obtain PCI resource region\n");
4330c2f2
GFT		 3081 goto err_out_disable_pdev;
3082 }
d7699f87
GFT		 3083
3084 pci_set_master(pdev);
3085
3086 /*
3087 * alloc and init net device
3088 */
3bf61c55 3089 netdev = alloc_etherdev(sizeof(*jme));
cd0ff491 3090 if (!netdev) {
937ef75a 3091 pr_err("Cannot allocate netdev structure\n");
4330c2f2
GFT		 3092 rc = -ENOMEM;
3093 goto err_out_release_regions;
d7699f87 3094 }
3b70a6fa
GFT		 3095#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3096 netdev->netdev_ops = &jme_netdev_ops;
3097#else
d7699f87
GFT		 3098 netdev->open = jme_open;
3099 netdev->stop = jme_close;
aa1e7189 3100 netdev->do_ioctl = jme_ioctl;
d7699f87 3101 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT		 3102 netdev->set_mac_address = jme_set_macaddr;
3103 netdev->set_multicast_list = jme_set_multi;
3104 netdev->change_mtu = jme_change_mtu;
8c198884 3105 netdev->tx_timeout = jme_tx_timeout;
42b1055e 3106 netdev->vlan_rx_register = jme_vlan_rx_register;
7ca9ebee
GFT		 3107#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3108 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3109#endif
3bf61c55 3110 NETDEV_GET_STATS(netdev, &jme_get_stats);
3b70a6fa
GFT		 3111#endif
3112 netdev->ethtool_ops = &jme_ethtool_ops;
3113 netdev->watchdog_timeo = TX_TIMEOUT;
1a0b42f4
MM		 3114 netdev->features = NETIF_F_IP_CSUM |
3115 NETIF_F_IPV6_CSUM |
b3821cc5
GFT		 3116 NETIF_F_SG |
3117 NETIF_F_TSO |
3118 NETIF_F_TSO6 |
42b1055e
GFT		 3119 NETIF_F_HW_VLAN_TX |
3120 NETIF_F_HW_VLAN_RX;
cd0ff491 3121 if (using_dac)
8c198884 3122 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 3123
3124 SET_NETDEV_DEV(netdev, &pdev->dev);
3125 pci_set_drvdata(pdev, netdev);
3126
3127 /*
3128 * init adapter info
3129 */
3130 jme = netdev_priv(netdev);
3131 jme->pdev = pdev;
3132 jme->dev = netdev;
cdcdc9eb
GFT		 3133 jme->jme_rx = netif_rx;
3134 jme->jme_vlan_rx = vlan_hwaccel_rx;
29bdd921 3135 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 3136 jme->phylink = 0;
b3821cc5 3137 jme->tx_ring_size = 1 << 10;
0ede469c 3138 jme->tx_ring_mask = jme->tx_ring_size - 1;
b3821cc5
GFT		 3139 jme->tx_wake_threshold = 1 << 9;
3140 jme->rx_ring_size = 1 << 9;
3141 jme->rx_ring_mask = jme->rx_ring_size - 1;
cd0ff491 3142 jme->msg_enable = JME_DEF_MSG_ENABLE;
d7699f87
GFT		 3143 jme->regs = ioremap(pci_resource_start(pdev, 0),
3144 pci_resource_len(pdev, 0));
4330c2f2 3145 if (!(jme->regs)) {
937ef75a 3146 pr_err("Mapping PCI resource region error\n");
d7699f87
GFT		 3147 rc = -ENOMEM;
3148 goto err_out_free_netdev;
3149 }
4330c2f2 3150
cd0ff491
GFT		 3151 if (no_pseudohp) {
3152 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3153 jwrite32(jme, JME_APMC, apmc);
3154 } else if (force_pseudohp) {
3155 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3156 jwrite32(jme, JME_APMC, apmc);
3157 }
3158
cdcdc9eb 3159 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
192570e0 3160
d7699f87 3161 spin_lock_init(&jme->phy_lock);
fcf45b4c 3162 spin_lock_init(&jme->macaddr_lock);
8c198884 3163 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 3164
fcf45b4c
GFT		 3165 atomic_set(&jme->link_changing, 1);
3166 atomic_set(&jme->rx_cleaning, 1);
3167 atomic_set(&jme->tx_cleaning, 1);
192570e0 3168 atomic_set(&jme->rx_empty, 1);
fcf45b4c 3169
79ce639c 3170 tasklet_init(&jme->pcc_task,
7ca9ebee 3171 jme_pcc_tasklet,
79ce639c 3172 (unsigned long) jme);
4330c2f2 3173 tasklet_init(&jme->linkch_task,
7ca9ebee 3174 jme_link_change_tasklet,
4330c2f2
GFT		 3175 (unsigned long) jme);
3176 tasklet_init(&jme->txclean_task,
7ca9ebee 3177 jme_tx_clean_tasklet,
4330c2f2
GFT		 3178 (unsigned long) jme);
3179 tasklet_init(&jme->rxclean_task,
7ca9ebee 3180 jme_rx_clean_tasklet,
4330c2f2 3181 (unsigned long) jme);
fcf45b4c 3182 tasklet_init(&jme->rxempty_task,
7ca9ebee 3183 jme_rx_empty_tasklet,
fcf45b4c 3184 (unsigned long) jme);
0ede469c 3185 tasklet_disable_nosync(&jme->linkch_task);
cd0ff491
GFT		 3186 tasklet_disable_nosync(&jme->txclean_task);
3187 tasklet_disable_nosync(&jme->rxclean_task);
3188 tasklet_disable_nosync(&jme->rxempty_task);
8c198884
GFT		 3189 jme->dpi.cur = PCC_P1;
3190
cd0ff491 3191 jme->reg_ghc = 0;
79ce639c 3192 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 3193 jme->reg_rxmcs = RXMCS_DEFAULT;
3194 jme->reg_txpfc = 0;
47220951 3195 jme->reg_pmcs = PMCS_MFEN;
dc4185bd 3196 jme->reg_gpreg1 = GPREG1_DEFAULT;
cd0ff491
GFT		 3197 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3198 set_bit(JME_FLAG_TSO, &jme->flags);
192570e0 3199
fcf45b4c
GFT		 3200 /*
3201 * Get Max Read Req Size from PCI Config Space
3202 */
cd0ff491
GFT		 3203 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3204 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3205 switch (jme->mrrs) {
3206 case MRRS_128B:
3207 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3208 break;
3209 case MRRS_256B:
3210 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3211 break;
3212 default:
3213 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3214 break;
cd54cf32 3215 }
fcf45b4c 3216
d7699f87 3217 /*
cdcdc9eb 3218 * Must check before reset_mac_processor
d7699f87 3219 */
cdcdc9eb
GFT		 3220 jme_check_hw_ver(jme);
3221 jme->mii_if.dev = netdev;
cd0ff491 3222 if (jme->fpgaver) {
cdcdc9eb 3223 jme->mii_if.phy_id = 0;
cd0ff491 3224 for (i = 1 ; i < 32 ; ++i) {
cdcdc9eb
GFT		 3225 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3226 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
cd0ff491 3227 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
cdcdc9eb
GFT		 3228 jme->mii_if.phy_id = i;
3229 break;
3230 }
3231 }
3232
cd0ff491 3233 if (!jme->mii_if.phy_id) {
cdcdc9eb 3234 rc = -EIO;
937ef75a
JP		 3235 pr_err("Can not find phy_id\n");
3236 goto err_out_unmap;
cdcdc9eb
GFT		 3237 }
3238
3239 jme->reg_ghc |= GHC_LINK_POLL;
cd0ff491 3240 } else {
cdcdc9eb
GFT		 3241 jme->mii_if.phy_id = 1;
3242 }
cd0ff491 3243 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
8d27293f
GFT		 3244 jme->mii_if.supports_gmii = true;
3245 else
3246 jme->mii_if.supports_gmii = false;
aa1e7189
GFT		 3247 jme->mii_if.phy_id_mask = 0x1F;
3248 jme->mii_if.reg_num_mask = 0x1F;
cdcdc9eb
GFT		 3249 jme->mii_if.mdio_read = jme_mdio_read;
3250 jme->mii_if.mdio_write = jme_mdio_write;
3251
61891ee4
GFT		 3252 jme_clear_pm(jme);
3253 pci_set_power_state(jme->pdev, PCI_D0);
3254#ifndef JME_NEW_PM_API
3255 jme_pci_wakeup_enable(jme, true);
3256#endif
3257#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
e3b96dc9 3258 device_set_wakeup_enable(&pdev->dev, true);
61891ee4
GFT		 3259#endif
3260
55d19799 3261 jme_set_phyfifo_5level(jme);
711edd99 3262#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
98ef18f1 3263 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
711edd99
SS		 3264#else
3265 jme->pcirev = pdev->revision;
3266#endif
cd0ff491 3267 if (!jme->fpgaver)
cdcdc9eb 3268 jme_phy_init(jme);
42b1055e 3269 jme_phy_off(jme);
cdcdc9eb
GFT		 3270
3271 /*
3272 * Reset MAC processor and reload EEPROM for MAC Address
3273 */
d7699f87 3274 jme_reset_mac_processor(jme);
4330c2f2 3275 rc = jme_reload_eeprom(jme);
cd0ff491 3276 if (rc) {
937ef75a 3277 pr_err("Reload eeprom for reading MAC Address error\n");
0ede469c 3278 goto err_out_unmap;
4330c2f2 3279 }
d7699f87
GFT		 3280 jme_load_macaddr(netdev);
3281
d7699f87
GFT		 3282 /*
3283 * Tell stack that we are not ready to work until open()
3284 */
3285 netif_carrier_off(netdev);
d7699f87 3286
4330c2f2 3287 rc = register_netdev(netdev);
cd0ff491 3288 if (rc) {
937ef75a 3289 pr_err("Cannot register net device\n");
0ede469c 3290 goto err_out_unmap;
4330c2f2 3291 }
d7699f87 3292
98ef18f1 3293 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
937ef75a 3294 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
7ca9ebee
GFT		 3295 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3296 "JMC250 Gigabit Ethernet" :
3297 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3298 "JMC260 Fast Ethernet" : "Unknown",
3299 (jme->fpgaver != 0) ? " (FPGA)" : "",
3300 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
98ef18f1 3301 jme->pcirev,
937ef75a
JP		 3302 netdev->dev_addr[0],
3303 netdev->dev_addr[1],
3304 netdev->dev_addr[2],
3305 netdev->dev_addr[3],
3306 netdev->dev_addr[4],
3307 netdev->dev_addr[5]);
d7699f87
GFT		 3308
3309 return 0;
3310
3311err_out_unmap:
3312 iounmap(jme->regs);
3313err_out_free_netdev:
3314 pci_set_drvdata(pdev, NULL);
3315 free_netdev(netdev);
4330c2f2
GFT		 3316err_out_release_regions:
3317 pci_release_regions(pdev);
d7699f87 3318err_out_disable_pdev:
cd0ff491 3319 pci_disable_device(pdev);
d7699f87 3320err_out:
4330c2f2 3321 return rc;
d7699f87
GFT		 3322}
3323
3bf61c55
GFT		 3324static void __devexit
3325jme_remove_one(struct pci_dev *pdev)
3326{
d7699f87
GFT		 3327 struct net_device *netdev = pci_get_drvdata(pdev);
3328 struct jme_adapter *jme = netdev_priv(netdev);
3329
3330 unregister_netdev(netdev);
3331 iounmap(jme->regs);
3332 pci_set_drvdata(pdev, NULL);
3333 free_netdev(netdev);
3334 pci_release_regions(pdev);
3335 pci_disable_device(pdev);
3336
3337}
3338
a82e368c
GFT		 3339static void
3340jme_shutdown(struct pci_dev *pdev)
3341{
3342 struct net_device *netdev = pci_get_drvdata(pdev);
3343 struct jme_adapter *jme = netdev_priv(netdev);
3344
61891ee4
GFT		 3345 jme_powersave_phy(jme);
3346#ifndef JME_NEW_PM_API
3347 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3348#endif
3d12cc1b 3349#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
61891ee4 3350 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
a82e368c
GFT		 3351#endif
3352}
3353
fda5634a
GFT		 3354#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3355 #ifdef CONFIG_PM
3356 #define JME_HAVE_PM
3357 #endif
3358#else
3359 #ifdef CONFIG_PM_SLEEP
3360 #define JME_HAVE_PM
3361 #endif
3362#endif
3363
3364#ifdef JME_HAVE_PM
29bdd921 3365static int
3d12cc1b 3366#ifdef JME_NEW_PM_API
7370b85a 3367jme_suspend(struct device *dev)
3d12cc1b
GFT		 3368#else
3369jme_suspend(struct pci_dev *pdev, pm_message_t state)
7370b85a 3370#endif
29bdd921 3371{
3d12cc1b 3372#ifdef JME_NEW_PM_API
7370b85a
RW		 3373 struct pci_dev *pdev = to_pci_dev(dev);
3374#endif
29bdd921
GFT		 3375 struct net_device *netdev = pci_get_drvdata(pdev);
3376 struct jme_adapter *jme = netdev_priv(netdev);
29bdd921
GFT		 3377
3378 atomic_dec(&jme->link_changing);
3379
3380 netif_device_detach(netdev);
3381 netif_stop_queue(netdev);
3382 jme_stop_irq(jme);
29bdd921 3383
cd0ff491
GFT		 3384 tasklet_disable(&jme->txclean_task);
3385 tasklet_disable(&jme->rxclean_task);
3386 tasklet_disable(&jme->rxempty_task);
3387
cd0ff491
GFT		 3388 if (netif_carrier_ok(netdev)) {
3389 if (test_bit(JME_FLAG_POLL, &jme->flags))
47220951
GFT		 3390 jme_polling_mode(jme);
3391
29bdd921 3392 jme_stop_pcc_timer(jme);
cd0ff491
GFT		 3393 jme_disable_rx_engine(jme);
3394 jme_disable_tx_engine(jme);
29bdd921
GFT		 3395 jme_reset_mac_processor(jme);
3396 jme_free_rx_resources(jme);
3397 jme_free_tx_resources(jme);
3398 netif_carrier_off(netdev);
3399 jme->phylink = 0;
3400 }
3401
cd0ff491
GFT		 3402 tasklet_enable(&jme->txclean_task);
3403 tasklet_hi_enable(&jme->rxclean_task);
3404 tasklet_hi_enable(&jme->rxempty_task);
29bdd921 3405
a82e368c 3406 jme_powersave_phy(jme);
3d12cc1b 3407#ifndef JME_NEW_PM_API
7370b85a 3408 pci_save_state(pdev);
61891ee4 3409 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
a82e368c 3410 pci_set_power_state(pdev, PCI_D3hot);
7370b85a 3411#endif
29bdd921
GFT		 3412
3413 return 0;
3414}
3415
3416static int
3d12cc1b 3417#ifdef JME_NEW_PM_API
7370b85a 3418jme_resume(struct device *dev)
3d12cc1b
GFT		 3419#else
3420jme_resume(struct pci_dev *pdev)
7370b85a 3421#endif
29bdd921 3422{
3d12cc1b 3423#ifdef JME_NEW_PM_API
7370b85a
RW		 3424 struct pci_dev *pdev = to_pci_dev(dev);
3425#endif
29bdd921
GFT		 3426 struct net_device *netdev = pci_get_drvdata(pdev);
3427 struct jme_adapter *jme = netdev_priv(netdev);
3428
3429 jme_clear_pm(jme);
3d12cc1b
GFT		 3430#ifndef JME_NEW_PM_API
3431 pci_set_power_state(pdev, PCI_D0);
29bdd921 3432 pci_restore_state(pdev);
7370b85a 3433#endif
29bdd921 3434
ed457bcc
GFT		 3435 jme_phy_on(jme);
3436 if (test_bit(JME_FLAG_SSET, &jme->flags))
29bdd921 3437 jme_set_settings(netdev, &jme->old_ecmd);
ed457bcc 3438 else
29bdd921
GFT		 3439 jme_reset_phy_processor(jme);
3440
29bdd921
GFT		 3441 jme_start_irq(jme);
3442 netif_device_attach(netdev);
3443
3444 atomic_inc(&jme->link_changing);
3445
3446 jme_reset_link(jme);
3447
3448 return 0;
3449}
7370b85a 3450
e3b96dc9 3451#ifdef JME_NEW_PM_API
7370b85a
RW		 3452static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3453#define JME_PM_OPS (&jme_pm_ops)
3454#endif
3455
3456#else
3457
e3b96dc9 3458#ifdef JME_NEW_PM_API
7370b85a
RW		 3459#define JME_PM_OPS NULL
3460#endif
7ee473a3 3461#endif
29bdd921 3462
7ca9ebee 3463#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
d7699f87 3464static struct pci_device_id jme_pci_tbl[] = {
7ca9ebee
GFT		 3465#else
3466static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3467#endif
cd0ff491
GFT		 3468 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3469 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
d7699f87
GFT		 3470 { }
3471};
3472
3473static struct pci_driver jme_driver = {
cd0ff491
GFT		 3474 .name = DRV_NAME,
3475 .id_table = jme_pci_tbl,
3476 .probe = jme_init_one,
3477 .remove = __devexit_p(jme_remove_one),
a82e368c 3478 .shutdown = jme_shutdown,
e3b96dc9 3479#ifndef JME_NEW_PM_API
7370b85a
RW		 3480 .suspend = jme_suspend,
3481 .resume = jme_resume
3482#else
3483 .driver.pm = JME_PM_OPS,
3484#endif
d7699f87
GFT		 3485};
3486
3bf61c55
GFT		 3487static int __init
3488jme_init_module(void)
d7699f87 3489{
937ef75a 3490 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
d7699f87
GFT		 3491 return pci_register_driver(&jme_driver);
3492}
3493
3bf61c55
GFT		 3494static void __exit
3495jme_cleanup_module(void)
d7699f87
GFT		 3496{
3497 pci_unregister_driver(&jme_driver);
3498}
3499
3500module_init(jme_init_module);
3501module_exit(jme_cleanup_module);
3502
3bf61c55 3503MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 3504MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3505MODULE_LICENSE("GPL");
3506MODULE_VERSION(DRV_VERSION);
3507MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3508
JMicron Ethernet Linux driver