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[jme.git] / jme.c
CommitLineData
d7699f87
GFT		 1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
3bf61c55
GFT		 7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
d7699f87
GFT		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
79ce639c 24/*
b3821cc5 25 * TODO:
4330c2f2
GFT		 26 * - Implement MSI-X.
27 * Along with multiple RX queue, for CPU load balancing.
b3821cc5 28 * - Decode register dump for ethtool.
d7699f87
GFT		 29 */
30
4330c2f2 31#include <linux/version.h>
d7699f87
GFT		 32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/ethtool.h>
38#include <linux/mii.h>
39#include <linux/crc32.h>
4330c2f2 40#include <linux/delay.h>
29bdd921 41#include <linux/spinlock.h>
8c198884
GFT		 42#include <linux/in.h>
43#include <linux/ip.h>
79ce639c
GFT		 44#include <linux/ipv6.h>
45#include <linux/tcp.h>
46#include <linux/udp.h>
42b1055e 47#include <linux/if_vlan.h>
d7699f87
GFT		 48#include "jme.h"
49
4330c2f2 50#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3bf61c55
GFT		 51static struct net_device_stats *
52jme_get_stats(struct net_device *netdev)
4330c2f2
GFT		 53{
54 struct jme_adapter *jme = netdev_priv(netdev);
55 return &jme->stats;
56}
57#endif
58
3bf61c55
GFT		 59static int
60jme_mdio_read(struct net_device *netdev, int phy, int reg)
d7699f87
GFT		 61{
62 struct jme_adapter *jme = netdev_priv(netdev);
63 int i, val;
64
65 jwrite32(jme, JME_SMI, SMI_OP_REQ |
3bf61c55
GFT		 66 smi_phy_addr(phy) |
67 smi_reg_addr(reg));
d7699f87
GFT		 68
69 wmb();
79ce639c 70 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
3bf61c55 71 udelay(1);
b3821cc5
GFT		 72 val = jread32(jme, JME_SMI);
73 if ((val & SMI_OP_REQ) == 0)
3bf61c55 74 break;
d7699f87
GFT		 75 }
76
77 if (i == 0) {
3bf61c55
GFT		 78 jeprintk(netdev->name, "phy read timeout : %d\n", reg);
79 return 0;
d7699f87
GFT		 80 }
81
3bf61c55 82 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
d7699f87
GFT		 83}
84
3bf61c55
GFT		 85static void
86jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
d7699f87
GFT		 88{
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
3bf61c55
GFT		 92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
d7699f87
GFT		 95
96 wmb();
3bf61c55
GFT		 97 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
98 udelay(1);
b3821cc5
GFT		 99 val = jread32(jme, JME_SMI);
100 if ((val & SMI_OP_REQ) == 0)
3bf61c55
GFT		 101 break;
102 }
d7699f87 103
3bf61c55
GFT		 104 if (i == 0)
105 jeprintk(netdev->name, "phy write timeout : %d\n", reg);
d7699f87 106
3bf61c55 107 return;
d7699f87
GFT		 108}
109
3bf61c55
GFT		 110__always_inline static void
111jme_reset_phy_processor(struct jme_adapter *jme)
d7699f87 112{
fcf45b4c 113 __u32 val;
3bf61c55
GFT		 114
115 jme_mdio_write(jme->dev,
116 jme->mii_if.phy_id,
8c198884
GFT		 117 MII_ADVERTISE, ADVERTISE_ALL |
118 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3bf61c55
GFT		 119
120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
124
fcf45b4c
GFT		 125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
3bf61c55
GFT		 133 return;
134}
135
b3821cc5
GFT		 136static void
137jme_setup_wakeup_frame(struct jme_adapter *jme,
138 __u32 *mask, __u32 crc, int fnr)
139{
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for(i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161}
3bf61c55
GFT		 162
163__always_inline static void
164jme_reset_mac_processor(struct jme_adapter *jme)
165{
b3821cc5
GFT		 166 __u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0,0,0,0};
167 __u32 crc = 0xCDCDCDCD;
168 int i;
169
3bf61c55 170 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
d7699f87 171 udelay(2);
3bf61c55 172 jwrite32(jme, JME_GHC, jme->reg_ghc);
4330c2f2
GFT		 173 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
174 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
b3821cc5
GFT		 175 for(i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
176 jme_setup_wakeup_frame(jme, mask, crc, i);
4330c2f2
GFT		 177 jwrite32(jme, JME_GPREG0, GPREG0_DEFAULT);
178 jwrite32(jme, JME_GPREG1, 0);
d7699f87
GFT		 179}
180
3bf61c55
GFT		 181__always_inline static void
182jme_clear_pm(struct jme_adapter *jme)
d7699f87 183{
29bdd921 184 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
4330c2f2 185 pci_set_power_state(jme->pdev, PCI_D0);
42b1055e 186 pci_enable_wake(jme->pdev, PCI_D0, false);
d7699f87
GFT		 187}
188
3bf61c55
GFT		 189static int
190jme_reload_eeprom(struct jme_adapter *jme)
d7699f87
GFT		 191{
192 __u32 val;
193 int i;
194
195 val = jread32(jme, JME_SMBCSR);
196
197 if(val & SMBCSR_EEPROMD)
198 {
199 val |= SMBCSR_CNACK;
200 jwrite32(jme, JME_SMBCSR, val);
201 val |= SMBCSR_RELOAD;
202 jwrite32(jme, JME_SMBCSR, val);
203 mdelay(12);
204
205 for (i = JME_SMB_TIMEOUT; i > 0; --i)
206 {
207 mdelay(1);
208 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
209 break;
210 }
211
212 if(i == 0) {
4330c2f2 213 jeprintk(jme->dev->name, "eeprom reload timeout\n");
d7699f87
GFT		 214 return -EIO;
215 }
216 }
217 else
218 return -EIO;
3bf61c55 219
d7699f87
GFT		 220 return 0;
221}
222
3bf61c55
GFT		 223static void
224jme_load_macaddr(struct net_device *netdev)
d7699f87
GFT		 225{
226 struct jme_adapter *jme = netdev_priv(netdev);
227 unsigned char macaddr[6];
228 __u32 val;
229
fcf45b4c 230 spin_lock(&jme->macaddr_lock);
4330c2f2 231 val = jread32(jme, JME_RXUMA_LO);
d7699f87
GFT		 232 macaddr[0] = (val >> 0) & 0xFF;
233 macaddr[1] = (val >> 8) & 0xFF;
234 macaddr[2] = (val >> 16) & 0xFF;
235 macaddr[3] = (val >> 24) & 0xFF;
4330c2f2 236 val = jread32(jme, JME_RXUMA_HI);
d7699f87
GFT		 237 macaddr[4] = (val >> 0) & 0xFF;
238 macaddr[5] = (val >> 8) & 0xFF;
239 memcpy(netdev->dev_addr, macaddr, 6);
fcf45b4c 240 spin_unlock(&jme->macaddr_lock);
3bf61c55
GFT		 241}
242
fcf45b4c 243__always_inline static void
3bf61c55
GFT		 244jme_set_rx_pcc(struct jme_adapter *jme, int p)
245{
246 switch(p) {
192570e0
GFT		 247 case PCC_OFF:
248 jwrite32(jme, JME_PCCRX0,
249 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
250 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
251 break;
3bf61c55
GFT		 252 case PCC_P1:
253 jwrite32(jme, JME_PCCRX0,
254 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
255 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
256 break;
257 case PCC_P2:
258 jwrite32(jme, JME_PCCRX0,
259 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
260 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
261 break;
262 case PCC_P3:
263 jwrite32(jme, JME_PCCRX0,
264 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
265 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
266 break;
267 default:
268 break;
269 }
192570e0 270 wmb();
3bf61c55 271
192570e0
GFT		 272 if(!(jme->flags & JME_FLAG_POLL))
273 dprintk(jme->dev->name, "Switched to PCC_P%d\n", p);
d7699f87
GFT		 274}
275
fcf45b4c 276static void
3bf61c55 277jme_start_irq(struct jme_adapter *jme)
d7699f87 278{
3bf61c55
GFT		 279 register struct dynpcc_info *dpi = &(jme->dpi);
280
281 jme_set_rx_pcc(jme, PCC_P1);
3bf61c55
GFT		 282 dpi->cur = PCC_P1;
283 dpi->attempt = PCC_P1;
284 dpi->cnt = 0;
285
286 jwrite32(jme, JME_PCCTX,
8c198884
GFT		 287 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
288 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
3bf61c55
GFT		 289 PCCTXQ0_EN
290 );
291
d7699f87
GFT		 292 /*
293 * Enable Interrupts
294 */
295 jwrite32(jme, JME_IENS, INTR_ENABLE);
296}
297
3bf61c55
GFT		 298__always_inline static void
299jme_stop_irq(struct jme_adapter *jme)
d7699f87
GFT		 300{
301 /*
302 * Disable Interrupts
303 */
304 jwrite32(jme, JME_IENC, INTR_ENABLE);
305}
306
4330c2f2 307
3bf61c55
GFT		 308__always_inline static void
309jme_enable_shadow(struct jme_adapter *jme)
4330c2f2
GFT		 310{
311 jwrite32(jme,
312 JME_SHBA_LO,
313 ((__u32)jme->shadow_dma & ~((__u32)0x1F)) | SHBA_POSTEN);
314}
315
3bf61c55
GFT		 316__always_inline static void
317jme_disable_shadow(struct jme_adapter *jme)
4330c2f2
GFT		 318{
319 jwrite32(jme, JME_SHBA_LO, 0x0);
320}
321
fcf45b4c
GFT		 322static int
323jme_check_link(struct net_device *netdev, int testonly)
d7699f87
GFT		 324{
325 struct jme_adapter *jme = netdev_priv(netdev);
8c198884 326 __u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
79ce639c 327 char linkmsg[64];
fcf45b4c 328 int rc = 0;
d7699f87 329
b3821cc5 330 linkmsg[0] = '\0';
d7699f87
GFT		 331 phylink = jread32(jme, JME_PHY_LINK);
332
333 if (phylink & PHY_LINK_UP) {
8c198884
GFT		 334 if(!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
335 /*
336 * If we did not enable AN
337 * Speed/Duplex Info should be obtained from SMI
338 */
339 phylink = PHY_LINK_UP;
340
341 bmcr = jme_mdio_read(jme->dev,
342 jme->mii_if.phy_id,
343 MII_BMCR);
344
79ce639c 345
8c198884
GFT		 346 phylink |= ((bmcr & BMCR_SPEED1000) &&
347 (bmcr & BMCR_SPEED100) == 0) ?
348 PHY_LINK_SPEED_1000M :
349 (bmcr & BMCR_SPEED100) ?
350 PHY_LINK_SPEED_100M :
351 PHY_LINK_SPEED_10M;
352
353 phylink |= (bmcr & BMCR_FULLDPLX) ?
354 PHY_LINK_DUPLEX : 0;
79ce639c 355
b3821cc5 356 strcat(linkmsg, "Forced: ");
8c198884
GFT		 357 }
358 else {
359 /*
360 * Keep polling for speed/duplex resolve complete
361 */
362 while(!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
363 --cnt) {
364
365 udelay(1);
366 phylink = jread32(jme, JME_PHY_LINK);
367
368 }
369
370 if(!cnt)
371 jeprintk(netdev->name,
372 "Waiting speed resolve timeout.\n");
79ce639c 373
b3821cc5 374 strcat(linkmsg, "ANed: ");
d7699f87
GFT		 375 }
376
fcf45b4c
GFT		 377 if(jme->phylink == phylink) {
378 rc = 1;
379 goto out;
380 }
381 if(testonly)
382 goto out;
383
384 jme->phylink = phylink;
385
d7699f87
GFT		 386 switch(phylink & PHY_LINK_SPEED_MASK) {
387 case PHY_LINK_SPEED_10M:
388 ghc = GHC_SPEED_10M;
b3821cc5 389 strcat(linkmsg, "10 Mbps, ");
d7699f87
GFT		 390 break;
391 case PHY_LINK_SPEED_100M:
392 ghc = GHC_SPEED_100M;
b3821cc5 393 strcat(linkmsg, "100 Mbps, ");
d7699f87
GFT		 394 break;
395 case PHY_LINK_SPEED_1000M:
396 ghc = GHC_SPEED_1000M;
b3821cc5 397 strcat(linkmsg, "1000 Mbps, ");
d7699f87
GFT		 398 break;
399 default:
400 ghc = 0;
401 break;
402 }
403 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
fcf45b4c 404
d7699f87 405 strcat(linkmsg, (phylink &PHY_LINK_DUPLEX) ?
fcf45b4c
GFT		 406 "Full-Duplex, " :
407 "Half-Duplex, ");
408
409 if(phylink & PHY_LINK_MDI_STAT)
fcf45b4c 410 strcat(linkmsg, "MDI-X");
8c198884
GFT		 411 else
412 strcat(linkmsg, "MDI");
d7699f87
GFT		 413
414 if(phylink & PHY_LINK_DUPLEX)
415 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
8c198884 416 else {
d7699f87 417 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
3bf61c55
GFT		 418 TXMCS_BACKOFF |
419 TXMCS_CARRIERSENSE |
420 TXMCS_COLLISION);
8c198884
GFT		 421 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
422 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
423 TXTRHD_TXREN |
424 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
425 }
d7699f87 426
fcf45b4c
GFT		 427 jme->reg_ghc = ghc;
428 jwrite32(jme, JME_GHC, ghc);
429
4330c2f2 430 jprintk(netdev->name, "Link is up at %s.\n", linkmsg);
d7699f87
GFT		 431 netif_carrier_on(netdev);
432 }
433 else {
fcf45b4c
GFT		 434 if(testonly)
435 goto out;
436
4330c2f2 437 jprintk(netdev->name, "Link is down.\n");
fcf45b4c 438 jme->phylink = 0;
d7699f87
GFT		 439 netif_carrier_off(netdev);
440 }
fcf45b4c
GFT		 441
442out:
443 return rc;
d7699f87
GFT		 444}
445
3bf61c55
GFT		 446static int
447jme_setup_tx_resources(struct jme_adapter *jme)
d7699f87 448{
d7699f87
GFT		 449 struct jme_ring *txring = &(jme->txring[0]);
450
451 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 452 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
453 &(txring->dmaalloc),
454 GFP_ATOMIC);
fcf45b4c 455
4330c2f2
GFT		 456 if(!txring->alloc) {
457 txring->desc = NULL;
458 txring->dmaalloc = 0;
459 txring->dma = 0;
d7699f87 460 return -ENOMEM;
4330c2f2 461 }
d7699f87
GFT		 462
463 /*
464 * 16 Bytes align
465 */
3bf61c55
GFT		 466 txring->desc = (void*)ALIGN((unsigned long)(txring->alloc),
467 RING_DESC_ALIGN);
4330c2f2 468 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
d7699f87
GFT		 469 txring->next_to_use = 0;
470 txring->next_to_clean = 0;
b3821cc5 471 atomic_set(&txring->nr_free, jme->tx_ring_size);
d7699f87
GFT		 472
473 /*
b3821cc5 474 * Initialize Transmit Descriptors
d7699f87 475 */
b3821cc5 476 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
3bf61c55 477 memset(txring->bufinf, 0,
b3821cc5 478 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
d7699f87
GFT		 479
480 return 0;
481}
482
3bf61c55
GFT		 483static void
484jme_free_tx_resources(struct jme_adapter *jme)
d7699f87
GFT		 485{
486 int i;
487 struct jme_ring *txring = &(jme->txring[0]);
4330c2f2 488 struct jme_buffer_info *txbi = txring->bufinf;
d7699f87
GFT		 489
490 if(txring->alloc) {
b3821cc5 491 for(i = 0 ; i < jme->tx_ring_size ; ++i) {
4330c2f2
GFT		 492 txbi = txring->bufinf + i;
493 if(txbi->skb) {
494 dev_kfree_skb(txbi->skb);
495 txbi->skb = NULL;
d7699f87 496 }
3bf61c55
GFT		 497 txbi->mapping = 0;
498 txbi->len = 0;
499 txbi->nr_desc = 0;
d7699f87
GFT		 500 }
501
502 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 503 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
d7699f87
GFT		 504 txring->alloc,
505 txring->dmaalloc);
3bf61c55
GFT		 506
507 txring->alloc = NULL;
508 txring->desc = NULL;
509 txring->dmaalloc = 0;
510 txring->dma = 0;
d7699f87 511 }
3bf61c55
GFT		 512 txring->next_to_use = 0;
513 txring->next_to_clean = 0;
79ce639c 514 atomic_set(&txring->nr_free, 0);
d7699f87
GFT		 515
516}
517
3bf61c55
GFT		 518__always_inline static void
519jme_enable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 520{
521 /*
522 * Select Queue 0
523 */
524 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
525
526 /*
527 * Setup TX Queue 0 DMA Bass Address
528 */
fcf45b4c 529 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
3bf61c55 530 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
fcf45b4c 531 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 532
533 /*
534 * Setup TX Descptor Count
535 */
b3821cc5 536 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
d7699f87
GFT		 537
538 /*
539 * Enable TX Engine
540 */
541 wmb();
4330c2f2
GFT		 542 jwrite32(jme, JME_TXCS, jme->reg_txcs |
543 TXCS_SELECT_QUEUE0 |
544 TXCS_ENABLE);
d7699f87
GFT		 545
546}
547
29bdd921
GFT		 548__always_inline static void
549jme_restart_tx_engine(struct jme_adapter *jme)
550{
551 /*
552 * Restart TX Engine
553 */
554 jwrite32(jme, JME_TXCS, jme->reg_txcs |
555 TXCS_SELECT_QUEUE0 |
556 TXCS_ENABLE);
557}
558
3bf61c55
GFT		 559__always_inline static void
560jme_disable_tx_engine(struct jme_adapter *jme)
d7699f87
GFT		 561{
562 int i;
563 __u32 val;
564
565 /*
566 * Disable TX Engine
567 */
fcf45b4c 568 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
d7699f87
GFT		 569
570 val = jread32(jme, JME_TXCS);
571 for(i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i)
572 {
fcf45b4c 573 mdelay(1);
d7699f87
GFT		 574 val = jread32(jme, JME_TXCS);
575 }
576
8c198884 577 if(!i) {
4330c2f2 578 jeprintk(jme->dev->name, "Disable TX engine timeout.\n");
8c198884
GFT		 579 jme_reset_mac_processor(jme);
580 }
d7699f87
GFT		 581
582
583}
584
3bf61c55
GFT		 585static void
586jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
d7699f87
GFT		 587{
588 struct jme_ring *rxring = jme->rxring;
3bf61c55 589 register volatile struct rxdesc* rxdesc = rxring->desc;
4330c2f2
GFT		 590 struct jme_buffer_info *rxbi = rxring->bufinf;
591 rxdesc += i;
592 rxbi += i;
593
594 rxdesc->dw[0] = 0;
595 rxdesc->dw[1] = 0;
3bf61c55 596 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
fcf45b4c
GFT		 597 rxdesc->desc1.bufaddrl = cpu_to_le32(
598 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
3bf61c55
GFT		 599 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
600 if(jme->dev->features & NETIF_F_HIGHDMA)
601 rxdesc->desc1.flags = RXFLAG_64BIT;
d7699f87 602 wmb();
3bf61c55 603 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
d7699f87
GFT		 604}
605
3bf61c55
GFT		 606static int
607jme_make_new_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 608{
609 struct jme_ring *rxring = &(jme->rxring[0]);
b3821cc5 610 struct jme_buffer_info *rxbi = rxring->bufinf + i;
4330c2f2
GFT		 611 unsigned long offset;
612 struct sk_buff* skb;
613
79ce639c
GFT		 614 skb = netdev_alloc_skb(jme->dev,
615 jme->dev->mtu + RX_EXTRA_LEN);
4330c2f2
GFT		 616 if(unlikely(!skb))
617 return -ENOMEM;
3bf61c55 618
3bf61c55
GFT		 619 if(unlikely(offset =
620 (unsigned long)(skb->data)
79ce639c 621 & ((unsigned long)RX_BUF_DMA_ALIGN - 1)))
4330c2f2 622 skb_reserve(skb, RX_BUF_DMA_ALIGN - offset);
4330c2f2 623
4330c2f2 624 rxbi->skb = skb;
3bf61c55 625 rxbi->len = skb_tailroom(skb);
b3821cc5
GFT		 626 rxbi->mapping = pci_map_page(jme->pdev,
627 virt_to_page(skb->data),
628 offset_in_page(skb->data),
629 rxbi->len,
630 PCI_DMA_FROMDEVICE);
4330c2f2
GFT		 631
632 return 0;
633}
634
3bf61c55
GFT		 635static void
636jme_free_rx_buf(struct jme_adapter *jme, int i)
4330c2f2
GFT		 637{
638 struct jme_ring *rxring = &(jme->rxring[0]);
639 struct jme_buffer_info *rxbi = rxring->bufinf;
640 rxbi += i;
641
642 if(rxbi->skb) {
b3821cc5 643 pci_unmap_page(jme->pdev,
4330c2f2 644 rxbi->mapping,
3bf61c55 645 rxbi->len,
4330c2f2
GFT		 646 PCI_DMA_FROMDEVICE);
647 dev_kfree_skb(rxbi->skb);
648 rxbi->skb = NULL;
649 rxbi->mapping = 0;
3bf61c55 650 rxbi->len = 0;
4330c2f2
GFT		 651 }
652}
653
3bf61c55
GFT		 654static void
655jme_free_rx_resources(struct jme_adapter *jme)
656{
657 int i;
658 struct jme_ring *rxring = &(jme->rxring[0]);
659
660 if(rxring->alloc) {
b3821cc5 661 for(i = 0 ; i < jme->rx_ring_size ; ++i)
3bf61c55
GFT		 662 jme_free_rx_buf(jme, i);
663
664 dma_free_coherent(&(jme->pdev->dev),
b3821cc5 665 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
3bf61c55
GFT		 666 rxring->alloc,
667 rxring->dmaalloc);
668 rxring->alloc = NULL;
669 rxring->desc = NULL;
670 rxring->dmaalloc = 0;
671 rxring->dma = 0;
672 }
673 rxring->next_to_use = 0;
674 rxring->next_to_clean = 0;
675}
676
677static int
678jme_setup_rx_resources(struct jme_adapter *jme)
d7699f87
GFT		 679{
680 int i;
681 struct jme_ring *rxring = &(jme->rxring[0]);
682
683 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
b3821cc5
GFT		 684 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
685 &(rxring->dmaalloc),
686 GFP_ATOMIC);
4330c2f2
GFT		 687 if(!rxring->alloc) {
688 rxring->desc = NULL;
689 rxring->dmaalloc = 0;
690 rxring->dma = 0;
d7699f87 691 return -ENOMEM;
4330c2f2 692 }
d7699f87
GFT		 693
694 /*
695 * 16 Bytes align
696 */
3bf61c55
GFT		 697 rxring->desc = (void*)ALIGN((unsigned long)(rxring->alloc),
698 RING_DESC_ALIGN);
4330c2f2 699 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
d7699f87
GFT		 700 rxring->next_to_use = 0;
701 rxring->next_to_clean = 0;
702
d7699f87
GFT		 703 /*
704 * Initiallize Receive Descriptors
705 */
b3821cc5 706 for(i = 0 ; i < jme->rx_ring_size ; ++i) {
3bf61c55
GFT		 707 if(unlikely(jme_make_new_rx_buf(jme, i))) {
708 jme_free_rx_resources(jme);
709 return -ENOMEM;
710 }
d7699f87
GFT		 711
712 jme_set_clean_rxdesc(jme, i);
713 }
714
d7699f87
GFT		 715 return 0;
716}
717
3bf61c55
GFT		 718__always_inline static void
719jme_enable_rx_engine(struct jme_adapter *jme)
d7699f87 720{
d7699f87
GFT		 721 /*
722 * Setup RX DMA Bass Address
723 */
fcf45b4c 724 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
3bf61c55 725 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
fcf45b4c 726 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
d7699f87
GFT		 727
728 /*
b3821cc5 729 * Setup RX Descriptor Count
d7699f87 730 */
b3821cc5 731 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
d7699f87 732
3bf61c55 733 /*
d7699f87
GFT		 734 * Setup Unicast Filter
735 */
736 jme_set_multi(jme->dev);
737
738 /*
739 * Enable RX Engine
740 */
741 wmb();
79ce639c 742 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 743 RXCS_QUEUESEL_Q0 |
744 RXCS_ENABLE |
745 RXCS_QST);
d7699f87
GFT		 746}
747
3bf61c55
GFT		 748__always_inline static void
749jme_restart_rx_engine(struct jme_adapter *jme)
4330c2f2
GFT		 750{
751 /*
3bf61c55 752 * Start RX Engine
4330c2f2 753 */
79ce639c 754 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
4330c2f2
GFT		 755 RXCS_QUEUESEL_Q0 |
756 RXCS_ENABLE |
757 RXCS_QST);
758}
759
760
3bf61c55
GFT		 761__always_inline static void
762jme_disable_rx_engine(struct jme_adapter *jme)
d7699f87
GFT		 763{
764 int i;
765 __u32 val;
766
767 /*
768 * Disable RX Engine
769 */
29bdd921 770 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
d7699f87
GFT		 771
772 val = jread32(jme, JME_RXCS);
773 for(i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i)
774 {
29bdd921 775 mdelay(1);
d7699f87
GFT		 776 val = jread32(jme, JME_RXCS);
777 }
778
779 if(!i)
4330c2f2 780 jeprintk(jme->dev->name, "Disable RX engine timeout.\n");
d7699f87
GFT		 781
782}
783
192570e0
GFT		 784static int
785jme_rxsum_ok(struct jme_adapter *jme, __u16 flags)
786{
787 if(!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
788 return false;
789
790 if(unlikely((flags & RXWBFLAG_TCPON) &&
791 !(flags & RXWBFLAG_TCPCS))) {
792 csum_dbg(jme->dev->name, "TCP Checksum error.\n");
793 return false;
794 }
795
796 if(unlikely((flags & RXWBFLAG_UDPON) &&
797 !(flags & RXWBFLAG_UDPCS))) {
798 csum_dbg(jme->dev->name, "UDP Checksum error.\n");
799 return false;
800 }
801
802 if(unlikely((flags & RXWBFLAG_IPV4) &&
803 !(flags & RXWBFLAG_IPCS))) {
804 csum_dbg(jme->dev->name, "IPv4 Checksum error.\n");
805 return false;
806 }
807
808 return true;
809}
810
3bf61c55 811static void
42b1055e 812jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
d7699f87 813{
d7699f87 814 struct jme_ring *rxring = &(jme->rxring[0]);
3bf61c55
GFT		 815 volatile struct rxdesc *rxdesc = rxring->desc;
816 struct jme_buffer_info *rxbi = rxring->bufinf;
d7699f87 817 struct sk_buff *skb;
3bf61c55 818 int framesize;
d7699f87 819
3bf61c55
GFT		 820 rxdesc += idx;
821 rxbi += idx;
d7699f87 822
3bf61c55
GFT		 823 skb = rxbi->skb;
824 pci_dma_sync_single_for_cpu(jme->pdev,
825 rxbi->mapping,
826 rxbi->len,
827 PCI_DMA_FROMDEVICE);
828
829 if(unlikely(jme_make_new_rx_buf(jme, idx))) {
830 pci_dma_sync_single_for_device(jme->pdev,
831 rxbi->mapping,
832 rxbi->len,
833 PCI_DMA_FROMDEVICE);
834
835 ++(NET_STAT(jme).rx_dropped);
836 }
837 else {
838 framesize = le16_to_cpu(rxdesc->descwb.framesize)
839 - RX_PREPAD_SIZE;
840
841 skb_reserve(skb, RX_PREPAD_SIZE);
842 skb_put(skb, framesize);
843 skb->protocol = eth_type_trans(skb, jme->dev);
844
192570e0 845 if(jme_rxsum_ok(jme, rxdesc->descwb.flags))
8c198884 846 skb->ip_summed = CHECKSUM_UNNECESSARY;
29bdd921
GFT		 847 else
848 skb->ip_summed = CHECKSUM_NONE;
8c198884 849
b3821cc5
GFT		 850
851 if(rxdesc->descwb.flags & RXWBFLAG_TAGON) {
852 vlan_dbg(jme->dev->name, "VLAN: %04x\n",
853 rxdesc->descwb.vlan);
854 if(jme->vlgrp) {
855 vlan_dbg(jme->dev->name,
856 "VLAN Passed to kernel.\n");
857 vlan_hwaccel_rx(skb, jme->vlgrp,
42b1055e 858 le32_to_cpu(rxdesc->descwb.vlan));
b3821cc5
GFT		 859 NET_STAT(jme).rx_bytes += 4;
860 }
861 }
862 else {
42b1055e 863 netif_rx(skb);
b3821cc5 864 }
3bf61c55 865
b3821cc5
GFT		 866 if((le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST) ==
867 RXWBFLAG_DEST_MUL)
3bf61c55
GFT		 868 ++(NET_STAT(jme).multicast);
869
870 jme->dev->last_rx = jiffies;
871 NET_STAT(jme).rx_bytes += framesize;
872 ++(NET_STAT(jme).rx_packets);
873 }
874
875 jme_set_clean_rxdesc(jme, idx);
876
877}
878
192570e0 879
8c198884 880
3bf61c55
GFT		 881static int
882jme_process_receive(struct jme_adapter *jme, int limit)
883{
884 struct jme_ring *rxring = &(jme->rxring[0]);
885 volatile struct rxdesc *rxdesc = rxring->desc;
b3821cc5 886 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
3bf61c55 887
192570e0
GFT		 888 if(unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
889 goto out_inc;
890
891 if(unlikely(atomic_read(&jme->link_changing) != 1))
892 goto out_inc;
893
894 if(unlikely(!netif_carrier_ok(jme->dev)))
895 goto out_inc;
896
3bf61c55
GFT		 897 i = rxring->next_to_clean;
898 while( limit-- > 0 )
d7699f87 899 {
3bf61c55
GFT		 900 rxdesc = rxring->desc;
901 rxdesc += i;
902
4330c2f2 903 if((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
3bf61c55
GFT		 904 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
905 goto out;
d7699f87 906
4330c2f2
GFT		 907 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
908
3bf61c55 909 rx_dbg(jme->dev->name, "RX: Cleaning %d\n", i);
4330c2f2 910
8c198884 911 if(unlikely(desccnt > 1 ||
192570e0 912 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
d7699f87 913
3bf61c55
GFT		 914 if(rxdesc->descwb.errstat & RXWBERR_CRCERR)
915 ++(NET_STAT(jme).rx_crc_errors);
916 else if(rxdesc->descwb.errstat & RXWBERR_OVERUN)
917 ++(NET_STAT(jme).rx_fifo_errors);
918 else
919 ++(NET_STAT(jme).rx_errors);
4330c2f2 920
79ce639c
GFT		 921 if(desccnt > 1) {
922 rx_dbg(jme->dev->name,
923 "RX: More than one(%d) descriptor, "
924 "framelen=%d\n",
925 desccnt, le16_to_cpu(rxdesc->descwb.framesize));
3bf61c55 926 limit -= desccnt - 1;
79ce639c 927 }
4330c2f2 928
3bf61c55 929 for(j = i, ccnt = desccnt ; ccnt-- ; ) {
4330c2f2 930 jme_set_clean_rxdesc(jme, j);
b3821cc5 931 j = (j + 1) & (mask);
4330c2f2 932 }
3bf61c55 933
d7699f87
GFT		 934 }
935 else {
42b1055e 936 jme_alloc_and_feed_skb(jme, i);
3bf61c55 937 }
4330c2f2 938
b3821cc5 939 i = (i + desccnt) & (mask);
3bf61c55 940 }
4330c2f2 941
192570e0 942
3bf61c55
GFT		 943out:
944 rx_dbg(jme->dev->name, "RX: Stop at %d\n", i);
945 rx_dbg(jme->dev->name, "RX: RXNDA offset %d\n",
946 (jread32(jme, JME_RXNDA) - jread32(jme, JME_RXDBA_LO))
947 >> 4);
4330c2f2 948
3bf61c55 949 rxring->next_to_clean = i;
4330c2f2 950
192570e0
GFT		 951out_inc:
952 atomic_inc(&jme->rx_cleaning);
953
3bf61c55 954 return limit > 0 ? limit : 0;
4330c2f2 955
3bf61c55 956}
d7699f87 957
79ce639c
GFT		 958static void
959jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
960{
192570e0
GFT		 961 if(likely(atmp == dpi->cur)) {
962 dpi->cnt = 0;
79ce639c 963 return;
192570e0 964 }
79ce639c
GFT		 965
966 if(dpi->attempt == atmp) {
967 ++(dpi->cnt);
968 }
969 else {
970 dpi->attempt = atmp;
971 dpi->cnt = 0;
972 }
973
974}
975
976static void
977jme_dynamic_pcc(struct jme_adapter *jme)
978{
979 register struct dynpcc_info *dpi = &(jme->dpi);
980
981 if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
982 jme_attempt_pcc(dpi, PCC_P3);
192570e0 983 else if((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
79ce639c
GFT		 984 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
985 jme_attempt_pcc(dpi, PCC_P2);
986 else
987 jme_attempt_pcc(dpi, PCC_P1);
988
192570e0 989 if(unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
79ce639c
GFT		 990 jme_set_rx_pcc(jme, dpi->attempt);
991 dpi->cur = dpi->attempt;
992 dpi->cnt = 0;
993 }
994}
995
996static void
997jme_start_pcc_timer(struct jme_adapter *jme)
998{
999 struct dynpcc_info *dpi = &(jme->dpi);
1000 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1001 dpi->last_pkts = NET_STAT(jme).rx_packets;
1002 dpi->intr_cnt = 0;
1003 jwrite32(jme, JME_TMCSR,
1004 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1005}
1006
192570e0 1007__always_inline static void
29bdd921
GFT		 1008jme_stop_pcc_timer(struct jme_adapter *jme)
1009{
1010 jwrite32(jme, JME_TMCSR, 0);
1011}
1012
79ce639c
GFT		 1013static void
1014jme_pcc_tasklet(unsigned long arg)
1015{
1016 struct jme_adapter *jme = (struct jme_adapter*)arg;
1017 struct net_device *netdev = jme->dev;
1018
29bdd921 1019
b3821cc5 1020 if(unlikely(!netif_carrier_ok(netdev) ||
29bdd921
GFT		 1021 (atomic_read(&jme->link_changing) != 1)
1022 )) {
1023 jme_stop_pcc_timer(jme);
79ce639c
GFT		 1024 return;
1025 }
29bdd921 1026
192570e0
GFT		 1027 if(!(jme->flags & JME_FLAG_POLL))
1028 jme_dynamic_pcc(jme);
1029
79ce639c
GFT		 1030 jme_start_pcc_timer(jme);
1031}
1032
192570e0
GFT		 1033__always_inline static void
1034jme_polling_mode(struct jme_adapter *jme)
1035{
1036 jme_set_rx_pcc(jme, PCC_OFF);
1037}
1038
1039__always_inline static void
1040jme_interrupt_mode(struct jme_adapter *jme)
1041{
1042 jme_set_rx_pcc(jme, PCC_P1);
1043}
1044
3bf61c55
GFT		 1045static void
1046jme_link_change_tasklet(unsigned long arg)
1047{
1048 struct jme_adapter *jme = (struct jme_adapter*)arg;
fcf45b4c
GFT		 1049 struct net_device *netdev = jme->dev;
1050 int timeout = WAIT_TASKLET_TIMEOUT;
1051 int rc;
1052
1053 if(!atomic_dec_and_test(&jme->link_changing))
1054 goto out;
1055
29bdd921 1056 if(jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
fcf45b4c
GFT		 1057 goto out;
1058
29bdd921 1059 jme->old_mtu = netdev->mtu;
fcf45b4c
GFT		 1060 netif_stop_queue(netdev);
1061
1062 while(--timeout > 0 &&
1063 (
1064 atomic_read(&jme->rx_cleaning) != 1 ||
1065 atomic_read(&jme->tx_cleaning) != 1
1066 )) {
1067
1068 mdelay(1);
1069 }
1070
1071 if(netif_carrier_ok(netdev)) {
29bdd921 1072 jme_stop_pcc_timer(jme);
fcf45b4c
GFT		 1073 jme_reset_mac_processor(jme);
1074 jme_free_rx_resources(jme);
1075 jme_free_tx_resources(jme);
192570e0
GFT		 1076
1077 if(jme->flags & JME_FLAG_POLL) {
1078 jme_polling_mode(jme);
1079 napi_disable(&jme->napi);
1080 }
fcf45b4c
GFT		 1081 }
1082
1083 jme_check_link(netdev, 0);
1084 if(netif_carrier_ok(netdev)) {
1085 rc = jme_setup_rx_resources(jme);
1086 if(rc) {
1087 jeprintk(netdev->name,
1088 "Allocating resources for RX error"
1089 ", Device STOPPED!\n");
1090 goto out;
1091 }
1092
1093
1094 rc = jme_setup_tx_resources(jme);
1095 if(rc) {
1096 jeprintk(netdev->name,
1097 "Allocating resources for TX error"
1098 ", Device STOPPED!\n");
1099 goto err_out_free_rx_resources;
1100 }
1101
1102 jme_enable_rx_engine(jme);
1103 jme_enable_tx_engine(jme);
1104
1105 netif_start_queue(netdev);
192570e0
GFT		 1106
1107 if(jme->flags & JME_FLAG_POLL) {
1108 napi_enable(&jme->napi);
1109 jme_interrupt_mode(jme);
1110 }
1111
79ce639c 1112 jme_start_pcc_timer(jme);
fcf45b4c
GFT		 1113 }
1114
1115 goto out;
1116
1117err_out_free_rx_resources:
1118 jme_free_rx_resources(jme);
1119out:
1120 atomic_inc(&jme->link_changing);
3bf61c55 1121}
d7699f87 1122
3bf61c55
GFT		 1123static void
1124jme_rx_clean_tasklet(unsigned long arg)
1125{
1126 struct jme_adapter *jme = (struct jme_adapter*)arg;
79ce639c 1127 struct dynpcc_info *dpi = &(jme->dpi);
d7699f87 1128
192570e0
GFT		 1129 jme_process_receive(jme, jme->rx_ring_size);
1130 ++(dpi->intr_cnt);
42b1055e 1131
192570e0 1132}
fcf45b4c 1133
192570e0
GFT		 1134static int
1135jme_poll(struct napi_struct *napi, int budget)
1136{
1137 struct jme_adapter *jme = container_of(napi, struct jme_adapter, napi);
1138 struct net_device *netdev = jme->dev;
1139 int rest;
fcf45b4c 1140
192570e0 1141 rest = jme_process_receive(jme, budget);
fcf45b4c 1142
192570e0
GFT		 1143 while(!atomic_dec_and_test(&jme->rx_empty)) {
1144 ++(NET_STAT(jme).rx_dropped);
1145 jme_restart_rx_engine(jme);
1146 }
1147 atomic_inc(&jme->rx_empty);
1148
1149 if(rest) {
1150 netif_rx_complete(netdev, napi);
1151 jme_interrupt_mode(jme);
1152 }
1153
1154 return budget - rest;
fcf45b4c
GFT		 1155}
1156
1157static void
1158jme_rx_empty_tasklet(unsigned long arg)
1159{
1160 struct jme_adapter *jme = (struct jme_adapter*)arg;
1161
79ce639c 1162 if(unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1163 return;
1164
b3821cc5 1165 if(unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1166 return;
1167
b3821cc5 1168 queue_dbg(jme->dev->name, "RX Queue Full!\n");
29bdd921 1169
fcf45b4c
GFT		 1170 jme_rx_clean_tasklet(arg);
1171 jme_restart_rx_engine(jme);
4330c2f2
GFT		 1172}
1173
b3821cc5
GFT		 1174static void
1175jme_wake_queue_if_stopped(struct jme_adapter *jme)
1176{
1177 struct jme_ring *txring = jme->txring;
1178
1179 smp_wmb();
1180 if(unlikely(netif_queue_stopped(jme->dev) &&
1181 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1182
1183 queue_dbg(jme->dev->name, "TX Queue Waked.\n");
1184 netif_wake_queue(jme->dev);
1185
1186 }
1187
1188}
1189
3bf61c55
GFT		 1190static void
1191jme_tx_clean_tasklet(unsigned long arg)
4330c2f2
GFT		 1192{
1193 struct jme_adapter *jme = (struct jme_adapter*)arg;
3bf61c55
GFT		 1194 struct jme_ring *txring = &(jme->txring[0]);
1195 volatile struct txdesc *txdesc = txring->desc;
1196 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
b3821cc5 1197 int i, j, cnt = 0, max, err, mask;
3bf61c55 1198
79ce639c 1199 if(unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
fcf45b4c
GFT		 1200 goto out;
1201
79ce639c 1202 if(unlikely(atomic_read(&jme->link_changing) != 1))
fcf45b4c
GFT		 1203 goto out;
1204
b3821cc5 1205 if(unlikely(!netif_carrier_ok(jme->dev)))
fcf45b4c
GFT		 1206 goto out;
1207
b3821cc5
GFT		 1208 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1209 mask = jme->tx_ring_mask;
3bf61c55
GFT		 1210
1211 tx_dbg(jme->dev->name, "Tx Tasklet: In\n");
1212
1213 for(i = txring->next_to_clean ; cnt < max ; ) {
1214
1215 ctxbi = txbi + i;
1216
b3821cc5
GFT		 1217 if(likely(ctxbi->skb &&
1218 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
8c198884
GFT		 1219
1220 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
3bf61c55
GFT		 1221
1222 tx_dbg(jme->dev->name,
1223 "Tx Tasklet: Clean %d+%d\n",
1224 i, ctxbi->nr_desc);
1225
1226 for(j = 1 ; j < ctxbi->nr_desc ; ++j) {
b3821cc5
GFT		 1227 ttxbi = txbi + ((i + j) & (mask));
1228 txdesc[(i + j) & (mask)].dw[0] = 0;
3bf61c55 1229
b3821cc5 1230 pci_unmap_page(jme->pdev,
3bf61c55
GFT		 1231 ttxbi->mapping,
1232 ttxbi->len,
1233 PCI_DMA_TODEVICE);
1234
3bf61c55
GFT		 1235 ttxbi->mapping = 0;
1236 ttxbi->len = 0;
1237 }
1238
1239 dev_kfree_skb(ctxbi->skb);
3bf61c55
GFT		 1240
1241 cnt += ctxbi->nr_desc;
1242
8c198884
GFT		 1243 if(unlikely(err))
1244 ++(NET_STAT(jme).tx_carrier_errors);
b3821cc5 1245 else {
8c198884 1246 ++(NET_STAT(jme).tx_packets);
b3821cc5
GFT		 1247 NET_STAT(jme).tx_bytes += ctxbi->len;
1248 }
1249
1250 ctxbi->skb = NULL;
1251 ctxbi->len = 0;
3bf61c55
GFT		 1252 }
1253 else {
1254 if(!ctxbi->skb)
1255 tx_dbg(jme->dev->name,
1256 "Tx Tasklet:"
b3821cc5 1257 " Stopped due to no skb.\n");
3bf61c55
GFT		 1258 else
1259 tx_dbg(jme->dev->name,
1260 "Tx Tasklet:"
b3821cc5 1261 "Stopped due to not done.\n");
3bf61c55
GFT		 1262 break;
1263 }
1264
b3821cc5 1265 i = (i + ctxbi->nr_desc) & mask;
3bf61c55
GFT		 1266
1267 ctxbi->nr_desc = 0;
d7699f87
GFT		 1268 }
1269
3bf61c55
GFT		 1270 tx_dbg(jme->dev->name,
1271 "Tx Tasklet: Stop %d Jiffies %lu\n",
1272 i, jiffies);
1273 txring->next_to_clean = i;
1274
79ce639c 1275 atomic_add(cnt, &txring->nr_free);
3bf61c55 1276
b3821cc5
GFT		 1277 jme_wake_queue_if_stopped(jme);
1278
fcf45b4c
GFT		 1279out:
1280 atomic_inc(&jme->tx_cleaning);
d7699f87
GFT		 1281}
1282
79ce639c
GFT		 1283static void
1284jme_intr_msi(struct jme_adapter *jme, __u32 intrstat)
d7699f87 1285{
3bf61c55
GFT		 1286 /*
1287 * Disable interrupt
1288 */
1289 jwrite32f(jme, JME_IENC, INTR_ENABLE);
d7699f87 1290
29bdd921
GFT		 1291 /*
1292 * Write 1 clear interrupt status
1293 */
1294 jwrite32f(jme, JME_IEVE, intrstat);
1295
79ce639c 1296 if(intrstat & (INTR_LINKCH | INTR_SWINTR)) {
3bf61c55 1297 tasklet_schedule(&jme->linkch_task);
29bdd921 1298 goto out_reenable;
fcf45b4c 1299 }
d7699f87 1300
79ce639c
GFT		 1301 if(intrstat & INTR_TMINTR)
1302 tasklet_schedule(&jme->pcc_task);
1303
3bf61c55 1304 if(intrstat & (INTR_PCCTXTO | INTR_PCCTX))
4330c2f2 1305 tasklet_schedule(&jme->txclean_task);
d7699f87 1306
192570e0
GFT		 1307 if(jme->flags & JME_FLAG_POLL) {
1308 if(intrstat & INTR_RX0EMP)
1309 atomic_inc(&jme->rx_empty);
1310
1311 if((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1312 if(likely(
1313 netif_rx_schedule_prep(jme->dev, &jme->napi))) {
1314 jme_polling_mode(jme);
1315 __netif_rx_schedule(jme->dev, &jme->napi);
1316 }
1317 }
1318 }
1319 else {
1320 if(intrstat & INTR_RX0EMP)
1321 tasklet_schedule(&jme->rxempty_task);
1322
1323 if(intrstat & (INTR_PCCRX0TO | INTR_PCCRX0))
1324 tasklet_schedule(&jme->rxclean_task);
4330c2f2 1325 }
d7699f87 1326
29bdd921 1327out_reenable:
3bf61c55 1328 /*
fcf45b4c 1329 * Re-enable interrupt
3bf61c55 1330 */
fcf45b4c 1331 jwrite32f(jme, JME_IENS, INTR_ENABLE);
3bf61c55 1332
79ce639c
GFT		 1333
1334}
1335
1336static irqreturn_t
1337jme_intr(int irq, void *dev_id)
1338{
1339 struct net_device *netdev = dev_id;
1340 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c
GFT		 1341 __u32 intrstat;
1342
1343 intrstat = jread32(jme, JME_IEVE);
1344
1345 /*
1346 * Check if it's really an interrupt for us
1347 */
29bdd921
GFT		 1348 if(unlikely(intrstat == 0))
1349 return IRQ_NONE;
79ce639c
GFT		 1350
1351 /*
1352 * Check if the device still exist
1353 */
29bdd921
GFT		 1354 if(unlikely(intrstat == ~((typeof(intrstat))0)))
1355 return IRQ_NONE;
79ce639c
GFT		 1356
1357 jme_intr_msi(jme, intrstat);
1358
29bdd921 1359 return IRQ_HANDLED;
d7699f87
GFT		 1360}
1361
79ce639c
GFT		 1362static irqreturn_t
1363jme_msi(int irq, void *dev_id)
1364{
1365 struct net_device *netdev = dev_id;
1366 struct jme_adapter *jme = netdev_priv(netdev);
1367 __u32 intrstat;
1368
1369 pci_dma_sync_single_for_cpu(jme->pdev,
1370 jme->shadow_dma,
1371 sizeof(__u32) * SHADOW_REG_NR,
1372 PCI_DMA_FROMDEVICE);
1373 intrstat = jme->shadow_regs[SHADOW_IEVE];
1374 jme->shadow_regs[SHADOW_IEVE] = 0;
1375
1376 jme_intr_msi(jme, intrstat);
1377
1378 return IRQ_HANDLED;
1379}
1380
1381
1382static void
1383jme_reset_link(struct jme_adapter *jme)
1384{
1385 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1386}
1387
fcf45b4c
GFT		 1388static void
1389jme_restart_an(struct jme_adapter *jme)
1390{
1391 __u32 bmcr;
79ce639c 1392 unsigned long flags;
fcf45b4c 1393
79ce639c 1394 spin_lock_irqsave(&jme->phy_lock, flags);
fcf45b4c
GFT		 1395 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1396 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1397 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
79ce639c
GFT		 1398 spin_unlock_irqrestore(&jme->phy_lock, flags);
1399}
1400
1401static int
1402jme_request_irq(struct jme_adapter *jme)
1403{
1404 int rc;
1405 struct net_device *netdev = jme->dev;
1406 irq_handler_t handler = jme_intr;
1407 int irq_flags = IRQF_SHARED;
1408
1409 if (!pci_enable_msi(jme->pdev)) {
1410 jme->flags |= JME_FLAG_MSI;
1411 handler = jme_msi;
1412 irq_flags = 0;
1413 }
1414
1415 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1416 netdev);
1417 if(rc) {
1418 jeprintk(netdev->name,
b3821cc5 1419 "Unable to request %s interrupt (return: %d)\n",
29bdd921 1420 jme->flags & JME_FLAG_MSI ? "MSI":"INTx", rc);
79ce639c
GFT		 1421
1422 if(jme->flags & JME_FLAG_MSI) {
1423 pci_disable_msi(jme->pdev);
1424 jme->flags &= ~JME_FLAG_MSI;
1425 }
1426 }
1427 else {
1428 netdev->irq = jme->pdev->irq;
1429 }
1430
1431 return rc;
1432}
1433
1434static void
1435jme_free_irq(struct jme_adapter *jme)
1436{
1437 free_irq(jme->pdev->irq, jme->dev);
1438 if (jme->flags & JME_FLAG_MSI) {
1439 pci_disable_msi(jme->pdev);
1440 jme->flags &= ~JME_FLAG_MSI;
1441 jme->dev->irq = jme->pdev->irq;
1442 }
fcf45b4c
GFT		 1443}
1444
3bf61c55
GFT		 1445static int
1446jme_open(struct net_device *netdev)
d7699f87
GFT		 1447{
1448 struct jme_adapter *jme = netdev_priv(netdev);
fcf45b4c
GFT		 1449 int rc, timeout = 100;
1450
1451 while(
1452 --timeout > 0 &&
1453 (
1454 atomic_read(&jme->link_changing) != 1 ||
1455 atomic_read(&jme->rx_cleaning) != 1 ||
1456 atomic_read(&jme->tx_cleaning) != 1
1457 )
1458 )
1459 msleep(10);
1460
79ce639c
GFT		 1461 if(!timeout) {
1462 rc = -EBUSY;
1463 goto err_out;
1464 }
1465
42b1055e 1466 jme_clear_pm(jme);
fcf45b4c 1467 jme_reset_mac_processor(jme);
d7699f87 1468
79ce639c
GFT		 1469 rc = jme_request_irq(jme);
1470 if(rc)
4330c2f2 1471 goto err_out;
79ce639c 1472
4330c2f2 1473 jme_enable_shadow(jme);
d7699f87 1474 jme_start_irq(jme);
42b1055e
GFT		 1475
1476 if(jme->flags & JME_FLAG_SSET)
1477 jme_set_settings(netdev, &jme->old_ecmd);
1478 else
1479 jme_reset_phy_processor(jme);
1480
29bdd921 1481 jme_reset_link(jme);
d7699f87
GFT		 1482
1483 return 0;
1484
d7699f87
GFT		 1485err_out:
1486 netif_stop_queue(netdev);
1487 netif_carrier_off(netdev);
4330c2f2 1488 return rc;
d7699f87
GFT		 1489}
1490
42b1055e
GFT		 1491static void
1492jme_set_100m_half(struct jme_adapter *jme)
1493{
1494 __u32 bmcr, tmp;
1495
1496 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1497 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1498 BMCR_SPEED1000 | BMCR_FULLDPLX);
1499 tmp |= BMCR_SPEED100;
1500
1501 if (bmcr != tmp)
1502 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1503
1504 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1505}
1506
1507static void
1508jme_phy_off(struct jme_adapter *jme)
1509{
1510 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1511}
1512
1513
3bf61c55
GFT		 1514static int
1515jme_close(struct net_device *netdev)
d7699f87
GFT		 1516{
1517 struct jme_adapter *jme = netdev_priv(netdev);
1518
1519 netif_stop_queue(netdev);
1520 netif_carrier_off(netdev);
1521
1522 jme_stop_irq(jme);
4330c2f2 1523 jme_disable_shadow(jme);
79ce639c 1524 jme_free_irq(jme);
d7699f87 1525
192570e0
GFT		 1526 if(jme->flags & JME_FLAG_POLL)
1527 napi_disable(&jme->napi);
1528
4330c2f2
GFT		 1529 tasklet_kill(&jme->linkch_task);
1530 tasklet_kill(&jme->txclean_task);
1531 tasklet_kill(&jme->rxclean_task);
fcf45b4c 1532 tasklet_kill(&jme->rxempty_task);
8c198884
GFT		 1533
1534 jme_reset_mac_processor(jme);
d7699f87
GFT		 1535 jme_free_rx_resources(jme);
1536 jme_free_tx_resources(jme);
42b1055e 1537 jme->phylink = 0;
b3821cc5
GFT		 1538 jme_phy_off(jme);
1539
1540 return 0;
1541}
1542
1543static int
1544jme_alloc_txdesc(struct jme_adapter *jme,
1545 struct sk_buff *skb)
1546{
1547 struct jme_ring *txring = jme->txring;
1548 int idx, nr_alloc, mask = jme->tx_ring_mask;
1549
1550 idx = txring->next_to_use;
1551 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1552
1553 if(unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1554 return -1;
1555
1556 atomic_sub(nr_alloc, &txring->nr_free);
42b1055e 1557
b3821cc5
GFT		 1558 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1559
1560 return idx;
1561}
1562
1563static void
1564jme_fill_tx_map(struct pci_dev *pdev,
1565 volatile struct txdesc *txdesc,
1566 struct jme_buffer_info *txbi,
1567 struct page *page,
1568 __u32 page_offset,
1569 __u32 len,
1570 __u8 hidma)
1571{
1572 dma_addr_t dmaaddr;
1573
1574 dmaaddr = pci_map_page(pdev,
1575 page,
1576 page_offset,
1577 len,
1578 PCI_DMA_TODEVICE);
1579
1580 pci_dma_sync_single_for_device(pdev,
1581 dmaaddr,
1582 len,
1583 PCI_DMA_TODEVICE);
1584
1585 txdesc->dw[0] = 0;
1586 txdesc->dw[1] = 0;
1587 txdesc->desc2.flags = TXFLAG_OWN;
1588 txdesc->desc2.flags |= (hidma)?TXFLAG_64BIT:0;
1589 txdesc->desc2.datalen = cpu_to_le16(len);
1590 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1591 txdesc->desc2.bufaddrl = cpu_to_le32(
1592 (__u64)dmaaddr & 0xFFFFFFFFUL);
1593
1594 txbi->mapping = dmaaddr;
1595 txbi->len = len;
1596}
1597
1598static void
1599jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1600{
1601 struct jme_ring *txring = jme->txring;
1602 volatile struct txdesc *txdesc = txring->desc, *ctxdesc;
1603 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1604 __u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1605 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1606 int mask = jme->tx_ring_mask;
1607 struct skb_frag_struct *frag;
1608 __u32 len;
1609
1610 for(i = 0 ; i < nr_frags ; ++i) {
1611 frag = &skb_shinfo(skb)->frags[i];
1612 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1613 ctxbi = txbi + ((idx + i + 2) & (mask));
1614
1615 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1616 frag->page_offset, frag->size, hidma);
42b1055e 1617 }
b3821cc5
GFT		 1618
1619 len = skb_is_nonlinear(skb)?skb_headlen(skb):skb->len;
1620 ctxdesc = txdesc + ((idx + 1) & (mask));
1621 ctxbi = txbi + ((idx + 1) & (mask));
1622 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1623 offset_in_page(skb->data), len, hidma);
1624
1625}
1626
1627static int
1628jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1629{
1630 if(unlikely(skb_shinfo(skb)->gso_size &&
1631 skb_header_cloned(skb) &&
1632 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1633 dev_kfree_skb(skb);
1634 return -1;
1635 }
1636
1637 return 0;
1638}
1639
1640static int
1641jme_tx_tso(struct sk_buff *skb,
1642 volatile __u16 *mss, __u8 *flags)
1643{
1644 if((*mss = (skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT))) {
1645 *flags |= TXFLAG_LSEN;
1646
1647 if(skb->protocol == __constant_htons(ETH_P_IP)) {
1648 struct iphdr *iph = ip_hdr(skb);
1649
1650 iph->check = 0;
1651 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1652 iph->daddr, 0,
1653 IPPROTO_TCP,
1654 0);
1655 }
1656 else {
1657 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1658
1659 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1660 &ip6h->daddr, 0,
1661 IPPROTO_TCP,
1662 0);
1663 }
1664
1665 return 0;
1666 }
1667
1668 return 1;
1669}
1670
1671static void
1672jme_tx_csum(struct sk_buff *skb, __u8 *flags)
1673{
1674 if(skb->ip_summed == CHECKSUM_PARTIAL) {
1675 __u8 ip_proto;
1676
1677 switch (skb->protocol) {
1678 case __constant_htons(ETH_P_IP):
1679 ip_proto = ip_hdr(skb)->protocol;
1680 break;
1681 case __constant_htons(ETH_P_IPV6):
1682 ip_proto = ipv6_hdr(skb)->nexthdr;
1683 break;
1684 default:
1685 ip_proto = 0;
1686 break;
1687 }
1688
1689 switch(ip_proto) {
1690 case IPPROTO_TCP:
1691 *flags |= TXFLAG_TCPCS;
1692 break;
1693 case IPPROTO_UDP:
1694 *flags |= TXFLAG_UDPCS;
1695 break;
1696 default:
1697 jeprintk("jme", "Error upper layer protocol.\n");
1698 break;
1699 }
1700 }
1701}
1702
1703__always_inline static void
1704jme_tx_vlan(struct sk_buff *skb, volatile __u16 *vlan, __u8 *flags)
1705{
1706 if(vlan_tx_tag_present(skb)) {
1707 vlan_dbg("jme", "Tag found!(%04x)\n", vlan_tx_tag_get(skb));
1708 *flags |= TXFLAG_TAGON;
1709 *vlan = vlan_tx_tag_get(skb);
42b1055e 1710 }
b3821cc5
GFT		 1711}
1712
1713static int
1714jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1715{
1716 struct jme_ring *txring = jme->txring;
1717 volatile struct txdesc *txdesc;
1718 struct jme_buffer_info *txbi;
1719 __u8 flags;
1720
1721 txdesc = (volatile struct txdesc*)txring->desc + idx;
1722 txbi = txring->bufinf + idx;
1723
1724 txdesc->dw[0] = 0;
1725 txdesc->dw[1] = 0;
1726 txdesc->dw[2] = 0;
1727 txdesc->dw[3] = 0;
1728 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1729 /*
1730 * Set OWN bit at final.
1731 * When kernel transmit faster than NIC.
1732 * And NIC trying to send this descriptor before we tell
1733 * it to start sending this TX queue.
1734 * Other fields are already filled correctly.
1735 */
1736 wmb();
1737 flags = TXFLAG_OWN | TXFLAG_INT;
1738 //Set checksum flags while not tso
1739 if(jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1740 jme_tx_csum(skb, &flags);
1741 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1742 txdesc->desc1.flags = flags;
1743 /*
1744 * Set tx buffer info after telling NIC to send
1745 * For better tx_clean timing
1746 */
1747 wmb();
1748 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1749 txbi->skb = skb;
1750 txbi->len = skb->len;
d7699f87
GFT		 1751
1752 return 0;
1753}
1754
b3821cc5
GFT		 1755static void
1756jme_stop_queue_if_full(struct jme_adapter *jme)
1757{
1758 struct jme_ring *txring = jme->txring;
1759
1760 smp_wmb();
1761 if(unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1762 netif_stop_queue(jme->dev);
1763 queue_dbg(jme->dev->name, "TX Queue Paused.\n");
1764 smp_wmb();
1765 if (atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold)) {
1766 netif_wake_queue(jme->dev);
1767 queue_dbg(jme->dev->name, "TX Queue Fast Waked.\n");
1768 }
1769 }
1770
1771}
1772
3bf61c55
GFT		 1773/*
1774 * This function is already protected by netif_tx_lock()
1775 */
1776static int
1777jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
d7699f87
GFT		 1778{
1779 struct jme_adapter *jme = netdev_priv(netdev);
b3821cc5 1780 int idx;
d7699f87 1781
b3821cc5
GFT		 1782 if(skb_shinfo(skb)->nr_frags) {
1783 tx_dbg(netdev->name, "Frags: %d Headlen: %d Len: %d MSS: %d Sum:%d\n",
1784 skb_shinfo(skb)->nr_frags,
1785 skb_headlen(skb),
1786 skb->len,
1787 skb_shinfo(skb)->gso_size,
1788 skb->ip_summed);
1789 }
1790
1791 if(unlikely(jme_expand_header(jme, skb))) {
1792 ++(NET_STAT(jme).tx_dropped);
1793 return NETDEV_TX_OK;
1794 }
1795
1796 idx = jme_alloc_txdesc(jme, skb);
79ce639c 1797
b3821cc5
GFT		 1798 if(unlikely(idx<0)) {
1799 netif_stop_queue(netdev);
1800 jeprintk(netdev->name,
1801 "BUG! Tx ring full when queue awake!\n");
d7699f87 1802
b3821cc5
GFT		 1803 return NETDEV_TX_BUSY;
1804 }
1805
1806 jme_map_tx_skb(jme, skb, idx);
1807 jme_fill_first_tx_desc(jme, skb, idx);
1808
1809 tx_dbg(jme->dev->name, "Xmit: %d+%d\n", idx, skb_shinfo(skb)->nr_frags + 2);
d7699f87 1810
4330c2f2
GFT		 1811 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1812 TXCS_SELECT_QUEUE0 |
1813 TXCS_QUEUE0S |
1814 TXCS_ENABLE);
d7699f87
GFT		 1815 netdev->trans_start = jiffies;
1816
b3821cc5
GFT		 1817 jme_stop_queue_if_full(jme);
1818
4330c2f2 1819 return NETDEV_TX_OK;
d7699f87
GFT		 1820}
1821
3bf61c55
GFT		 1822static int
1823jme_set_macaddr(struct net_device *netdev, void *p)
d7699f87
GFT		 1824{
1825 struct jme_adapter *jme = netdev_priv(netdev);
1826 struct sockaddr *addr = p;
1827 __u32 val;
1828
1829 if(netif_running(netdev))
1830 return -EBUSY;
1831
fcf45b4c 1832 spin_lock(&jme->macaddr_lock);
d7699f87
GFT		 1833 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1834
1835 val = addr->sa_data[3] << 24 |
1836 addr->sa_data[2] << 16 |
1837 addr->sa_data[1] << 8 |
1838 addr->sa_data[0];
4330c2f2 1839 jwrite32(jme, JME_RXUMA_LO, val);
d7699f87
GFT		 1840 val = addr->sa_data[5] << 8 |
1841 addr->sa_data[4];
4330c2f2 1842 jwrite32(jme, JME_RXUMA_HI, val);
fcf45b4c 1843 spin_unlock(&jme->macaddr_lock);
d7699f87
GFT		 1844
1845 return 0;
1846}
1847
3bf61c55
GFT		 1848static void
1849jme_set_multi(struct net_device *netdev)
d7699f87 1850{
3bf61c55 1851 struct jme_adapter *jme = netdev_priv(netdev);
d7699f87 1852 u32 mc_hash[2] = {};
d7699f87 1853 int i;
8c198884 1854 unsigned long flags;
d7699f87 1855
8c198884
GFT		 1856 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1857
1858 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
d7699f87 1859
3bf61c55 1860 if (netdev->flags & IFF_PROMISC) {
8c198884 1861 jme->reg_rxmcs |= RXMCS_ALLFRAME;
3bf61c55
GFT		 1862 }
1863 else if (netdev->flags & IFF_ALLMULTI) {
8c198884 1864 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
3bf61c55 1865 }
d7699f87 1866 else if(netdev->flags & IFF_MULTICAST) {
3bf61c55
GFT		 1867 struct dev_mc_list *mclist;
1868 int bit_nr;
d7699f87 1869
8c198884 1870 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
3bf61c55
GFT		 1871 for (i = 0, mclist = netdev->mc_list;
1872 mclist && i < netdev->mc_count;
1873 ++i, mclist = mclist->next) {
1874
d7699f87
GFT		 1875 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1876 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
d7699f87
GFT		 1877 }
1878
4330c2f2
GFT		 1879 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1880 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
d7699f87
GFT		 1881 }
1882
d7699f87 1883 wmb();
8c198884
GFT		 1884 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1885
1886 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
d7699f87
GFT		 1887}
1888
3bf61c55 1889static int
8c198884 1890jme_change_mtu(struct net_device *netdev, int new_mtu)
d7699f87 1891{
79ce639c
GFT		 1892 struct jme_adapter *jme = netdev_priv(netdev);
1893
29bdd921
GFT		 1894 if(new_mtu == jme->old_mtu)
1895 return 0;
1896
79ce639c 1897 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
42b1055e 1898 ((new_mtu) < IPV6_MIN_MTU))
79ce639c
GFT		 1899 return -EINVAL;
1900
1901 if(new_mtu > 4000) {
1902 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1903 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1904 jme_restart_rx_engine(jme);
1905 }
1906 else {
1907 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1908 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1909 jme_restart_rx_engine(jme);
1910 }
1911
1912 if(new_mtu > 1900) {
b3821cc5
GFT		 1913 netdev->features &= ~(NETIF_F_HW_CSUM |
1914 NETIF_F_TSO |
1915 NETIF_F_TSO6);
79ce639c
GFT		 1916 }
1917 else {
b3821cc5
GFT		 1918 if(jme->flags & JME_FLAG_TXCSUM)
1919 netdev->features |= NETIF_F_HW_CSUM;
1920 if(jme->flags & JME_FLAG_TSO)
1921 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
79ce639c
GFT		 1922 }
1923
1924 netdev->mtu = new_mtu;
1925 jme_reset_link(jme);
1926
1927 return 0;
d7699f87
GFT		 1928}
1929
8c198884
GFT		 1930static void
1931jme_tx_timeout(struct net_device *netdev)
1932{
1933 struct jme_adapter *jme = netdev_priv(netdev);
1934
1935 /*
1936 * Reset the link
b3821cc5 1937 * And the link change will reinitialize all RX/TX resources
8c198884 1938 */
42b1055e 1939 jme->phylink = 0;
29bdd921 1940 jme_reset_link(jme);
8c198884
GFT		 1941}
1942
42b1055e
GFT		 1943static void
1944jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
1945{
1946 struct jme_adapter *jme = netdev_priv(netdev);
1947
1948 jme->vlgrp = grp;
1949}
1950
3bf61c55
GFT		 1951static void
1952jme_get_drvinfo(struct net_device *netdev,
1953 struct ethtool_drvinfo *info)
d7699f87
GFT		 1954{
1955 struct jme_adapter *jme = netdev_priv(netdev);
1956
1957 strcpy(info->driver, DRV_NAME);
1958 strcpy(info->version, DRV_VERSION);
1959 strcpy(info->bus_info, pci_name(jme->pdev));
1960}
1961
8c198884
GFT		 1962static int
1963jme_get_regs_len(struct net_device *netdev)
1964{
1965 return 0x400;
1966}
1967
1968static void
1969mmapio_memcpy(struct jme_adapter *jme, __u32 *p, __u32 reg, int len)
1970{
1971 int i;
1972
1973 for(i = 0 ; i < len ; i += 4)
79ce639c 1974 p[i >> 2] = jread32(jme, reg + i);
8c198884
GFT		 1975
1976}
1977
1978static void
1979jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
1980{
1981 struct jme_adapter *jme = netdev_priv(netdev);
1982 __u32 *p32 = (__u32*)p;
1983
1984 memset(p, 0, 0x400);
1985
1986 regs->version = 1;
1987 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
1988
1989 p32 += 0x100 >> 2;
1990 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
1991
1992 p32 += 0x100 >> 2;
1993 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
1994
1995 p32 += 0x100 >> 2;
1996 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
1997
1998}
1999
2000static int
2001jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2002{
2003 struct jme_adapter *jme = netdev_priv(netdev);
2004
192570e0
GFT		 2005 if(jme->flags & JME_FLAG_POLL)
2006 ecmd->use_adaptive_rx_coalesce = false;
2007 else
2008 ecmd->use_adaptive_rx_coalesce = true;
2009
8c198884
GFT		 2010 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2011 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2012
2013 switch(jme->dpi.cur) {
2014 case PCC_P1:
2015 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2016 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2017 break;
2018 case PCC_P2:
2019 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2020 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2021 break;
2022 case PCC_P3:
2023 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2024 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2025 break;
2026 default:
2027 break;
2028 }
2029
2030 return 0;
2031}
2032
192570e0
GFT		 2033static int
2034jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2035{
2036 struct jme_adapter *jme = netdev_priv(netdev);
2037 struct dynpcc_info *dpi = &(jme->dpi);
2038
2039 if(ecmd->use_adaptive_rx_coalesce
2040 && (jme->flags & JME_FLAG_POLL)) {
2041 jme->flags &= ~JME_FLAG_POLL;
2042 napi_disable(&jme->napi);
2043 dpi->cur = PCC_P1;
2044 dpi->attempt = PCC_P1;
2045 dpi->cnt = 0;
2046 jme_set_rx_pcc(jme, PCC_P1);
2047 jme_interrupt_mode(jme);
2048 }
2049 else if(!(ecmd->use_adaptive_rx_coalesce)
2050 && !(jme->flags & JME_FLAG_POLL)) {
2051 jme->flags |= JME_FLAG_POLL;
2052 napi_enable(&jme->napi);
2053 jme_interrupt_mode(jme);
2054 }
2055
2056 return 0;
2057}
2058
8c198884
GFT		 2059static void
2060jme_get_pauseparam(struct net_device *netdev,
2061 struct ethtool_pauseparam *ecmd)
2062{
2063 struct jme_adapter *jme = netdev_priv(netdev);
2064 unsigned long flags;
2065 __u32 val;
2066
2067 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2068 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2069
2070 spin_lock_irqsave(&jme->phy_lock, flags);
2071 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2072 spin_unlock_irqrestore(&jme->phy_lock, flags);
b3821cc5
GFT		 2073
2074 ecmd->autoneg =
2075 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
8c198884
GFT		 2076}
2077
2078static int
2079jme_set_pauseparam(struct net_device *netdev,
2080 struct ethtool_pauseparam *ecmd)
2081{
2082 struct jme_adapter *jme = netdev_priv(netdev);
2083 unsigned long flags;
2084 __u32 val;
2085
2086 if( ((jme->reg_txpfc & TXPFC_PF_EN) != 0) !=
2087 (ecmd->tx_pause != 0)) {
2088
2089 if(ecmd->tx_pause)
2090 jme->reg_txpfc |= TXPFC_PF_EN;
2091 else
2092 jme->reg_txpfc &= ~TXPFC_PF_EN;
2093
2094 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2095 }
2096
2097 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2098 if( ((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) !=
2099 (ecmd->rx_pause != 0)) {
2100
2101 if(ecmd->rx_pause)
2102 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2103 else
2104 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2105
2106 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2107 }
2108 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2109
2110 spin_lock_irqsave(&jme->phy_lock, flags);
2111 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
b3821cc5 2112 if( ((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) !=
8c198884
GFT		 2113 (ecmd->autoneg != 0)) {
2114
2115 if(ecmd->autoneg)
2116 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2117 else
2118 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2119
b3821cc5
GFT		 2120 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2121 MII_ADVERTISE, val);
8c198884
GFT		 2122 }
2123 spin_unlock_irqrestore(&jme->phy_lock, flags);
2124
2125 return 0;
2126}
2127
29bdd921
GFT		 2128static void
2129jme_get_wol(struct net_device *netdev,
2130 struct ethtool_wolinfo *wol)
2131{
2132 struct jme_adapter *jme = netdev_priv(netdev);
2133
2134 wol->supported = WAKE_MAGIC | WAKE_PHY;
2135
2136 wol->wolopts = 0;
2137
2138 if(jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2139 wol->wolopts |= WAKE_PHY;
2140
2141 if(jme->reg_pmcs & PMCS_MFEN)
2142 wol->wolopts |= WAKE_MAGIC;
2143
2144}
2145
2146static int
2147jme_set_wol(struct net_device *netdev,
2148 struct ethtool_wolinfo *wol)
2149{
2150 struct jme_adapter *jme = netdev_priv(netdev);
2151
2152 if(wol->wolopts & (WAKE_MAGICSECURE |
2153 WAKE_UCAST |
2154 WAKE_MCAST |
2155 WAKE_BCAST |
2156 WAKE_ARP))
2157 return -EOPNOTSUPP;
2158
2159 jme->reg_pmcs = 0;
2160
2161 if(wol->wolopts & WAKE_PHY)
2162 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2163
2164 if(wol->wolopts & WAKE_MAGIC)
2165 jme->reg_pmcs |= PMCS_MFEN;
2166
42b1055e 2167
29bdd921
GFT		 2168 return 0;
2169}
b3821cc5 2170
3bf61c55
GFT		 2171static int
2172jme_get_settings(struct net_device *netdev,
2173 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2174{
2175 struct jme_adapter *jme = netdev_priv(netdev);
2176 int rc;
79ce639c 2177 unsigned long flags;
8c198884 2178
79ce639c 2179 spin_lock_irqsave(&jme->phy_lock, flags);
d7699f87 2180 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
79ce639c 2181 spin_unlock_irqrestore(&jme->phy_lock, flags);
d7699f87
GFT		 2182 return rc;
2183}
2184
3bf61c55
GFT		 2185static int
2186jme_set_settings(struct net_device *netdev,
2187 struct ethtool_cmd *ecmd)
d7699f87
GFT		 2188{
2189 struct jme_adapter *jme = netdev_priv(netdev);
79ce639c 2190 int rc, fdc=0;
fcf45b4c
GFT		 2191 unsigned long flags;
2192
8c198884
GFT		 2193 if(ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2194 return -EINVAL;
2195
79ce639c
GFT		 2196 if(jme->mii_if.force_media &&
2197 ecmd->autoneg != AUTONEG_ENABLE &&
2198 (jme->mii_if.full_duplex != ecmd->duplex))
2199 fdc = 1;
2200
fcf45b4c 2201 spin_lock_irqsave(&jme->phy_lock, flags);
d7699f87 2202 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
fcf45b4c
GFT		 2203 spin_unlock_irqrestore(&jme->phy_lock, flags);
2204
79ce639c
GFT		 2205 if(!rc && fdc)
2206 jme_reset_link(jme);
2207
29bdd921
GFT		 2208 if(!rc) {
2209 jme->flags |= JME_FLAG_SSET;
2210 jme->old_ecmd = *ecmd;
2211 }
2212
d7699f87
GFT		 2213 return rc;
2214}
2215
3bf61c55
GFT		 2216static __u32
2217jme_get_link(struct net_device *netdev)
2218{
d7699f87
GFT		 2219 struct jme_adapter *jme = netdev_priv(netdev);
2220 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2221}
2222
8c198884
GFT		 2223static u32
2224jme_get_rx_csum(struct net_device *netdev)
2225{
2226 struct jme_adapter *jme = netdev_priv(netdev);
2227
2228 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2229}
2230
2231static int
2232jme_set_rx_csum(struct net_device *netdev, u32 on)
2233{
2234 struct jme_adapter *jme = netdev_priv(netdev);
2235 unsigned long flags;
b3821cc5 2236
8c198884
GFT		 2237 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2238 if(on)
2239 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2240 else
2241 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2242 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2243 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2244
2245 return 0;
2246}
2247
2248static int
2249jme_set_tx_csum(struct net_device *netdev, u32 on)
2250{
b3821cc5
GFT		 2251 struct jme_adapter *jme = netdev_priv(netdev);
2252
2253 if(on) {
2254 jme->flags |= JME_FLAG_TXCSUM;
2255 if(netdev->mtu <= 1900)
2256 netdev->features |= NETIF_F_HW_CSUM;
2257 }
2258 else {
2259 jme->flags &= ~JME_FLAG_TXCSUM;
8c198884 2260 netdev->features &= ~NETIF_F_HW_CSUM;
b3821cc5 2261 }
8c198884
GFT		 2262
2263 return 0;
2264}
2265
b3821cc5
GFT		 2266static int
2267jme_set_tso(struct net_device *netdev, u32 on)
2268{
2269 struct jme_adapter *jme = netdev_priv(netdev);
2270
2271 if (on) {
2272 jme->flags |= JME_FLAG_TSO;
2273 if(netdev->mtu <= 1900)
2274 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2275 }
2276 else {
2277 jme->flags &= ~JME_FLAG_TSO;
2278 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2279 }
2280
2281 return 0;
2282}
2283
8c198884
GFT		 2284static int
2285jme_nway_reset(struct net_device *netdev)
2286{
2287 struct jme_adapter *jme = netdev_priv(netdev);
2288 jme_restart_an(jme);
2289 return 0;
2290}
2291
d7699f87
GFT		 2292static const struct ethtool_ops jme_ethtool_ops = {
2293 .get_drvinfo = jme_get_drvinfo,
8c198884
GFT		 2294 .get_regs_len = jme_get_regs_len,
2295 .get_regs = jme_get_regs,
2296 .get_coalesce = jme_get_coalesce,
192570e0 2297 .set_coalesce = jme_set_coalesce,
8c198884
GFT		 2298 .get_pauseparam = jme_get_pauseparam,
2299 .set_pauseparam = jme_set_pauseparam,
29bdd921
GFT		 2300 .get_wol = jme_get_wol,
2301 .set_wol = jme_set_wol,
d7699f87
GFT		 2302 .get_settings = jme_get_settings,
2303 .set_settings = jme_set_settings,
2304 .get_link = jme_get_link,
8c198884
GFT		 2305 .get_rx_csum = jme_get_rx_csum,
2306 .set_rx_csum = jme_set_rx_csum,
2307 .set_tx_csum = jme_set_tx_csum,
b3821cc5
GFT		 2308 .set_tso = jme_set_tso,
2309 .set_sg = ethtool_op_set_sg,
8c198884 2310 .nway_reset = jme_nway_reset,
d7699f87
GFT		 2311};
2312
3bf61c55
GFT		 2313static int
2314jme_pci_dma64(struct pci_dev *pdev)
d7699f87 2315{
3bf61c55 2316 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
42b1055e
GFT		 2317 if(!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
2318 dprintk("jme", "64Bit DMA Selected.\n");
3bf61c55 2319 return 1;
42b1055e 2320 }
3bf61c55 2321
8c198884 2322 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
42b1055e
GFT		 2323 if(!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK)) {
2324 dprintk("jme", "40Bit DMA Selected.\n");
8c198884 2325 return 1;
42b1055e 2326 }
8c198884 2327
3bf61c55 2328 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
42b1055e
GFT		 2329 if(!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
2330 dprintk("jme", "32Bit DMA Selected.\n");
3bf61c55 2331 return 0;
42b1055e 2332 }
3bf61c55
GFT		 2333
2334 return -1;
2335}
2336
42b1055e
GFT		 2337__always_inline static void
2338jme_set_phy_ps(struct jme_adapter *jme)
2339{
2340 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, 0x00001000);
2341}
2342
3bf61c55
GFT		 2343static int __devinit
2344jme_init_one(struct pci_dev *pdev,
2345 const struct pci_device_id *ent)
2346{
2347 int rc = 0, using_dac;
d7699f87
GFT		 2348 struct net_device *netdev;
2349 struct jme_adapter *jme;
d7699f87
GFT		 2350
2351 /*
2352 * set up PCI device basics
2353 */
4330c2f2
GFT		 2354 rc = pci_enable_device(pdev);
2355 if(rc) {
2356 printk(KERN_ERR PFX "Cannot enable PCI device.\n");
2357 goto err_out;
2358 }
d7699f87 2359
3bf61c55
GFT		 2360 using_dac = jme_pci_dma64(pdev);
2361 if(using_dac < 0) {
2362 printk(KERN_ERR PFX "Cannot set PCI DMA Mask.\n");
2363 rc = -EIO;
2364 goto err_out_disable_pdev;
2365 }
2366
4330c2f2
GFT		 2367 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2368 printk(KERN_ERR PFX "No PCI resource region found.\n");
2369 rc = -ENOMEM;
2370 goto err_out_disable_pdev;
2371 }
d7699f87 2372
4330c2f2
GFT		 2373 rc = pci_request_regions(pdev, DRV_NAME);
2374 if(rc) {
2375 printk(KERN_ERR PFX "Cannot obtain PCI resource region.\n");
2376 goto err_out_disable_pdev;
2377 }
d7699f87
GFT		 2378
2379 pci_set_master(pdev);
2380
2381 /*
2382 * alloc and init net device
2383 */
3bf61c55 2384 netdev = alloc_etherdev(sizeof(*jme));
d7699f87 2385 if(!netdev) {
42b1055e 2386 printk(KERN_ERR PFX "Cannot allocate netdev structure.\n");
4330c2f2
GFT		 2387 rc = -ENOMEM;
2388 goto err_out_release_regions;
d7699f87
GFT		 2389 }
2390 netdev->open = jme_open;
2391 netdev->stop = jme_close;
2392 netdev->hard_start_xmit = jme_start_xmit;
d7699f87
GFT		 2393 netdev->set_mac_address = jme_set_macaddr;
2394 netdev->set_multicast_list = jme_set_multi;
2395 netdev->change_mtu = jme_change_mtu;
2396 netdev->ethtool_ops = &jme_ethtool_ops;
8c198884
GFT		 2397 netdev->tx_timeout = jme_tx_timeout;
2398 netdev->watchdog_timeo = TX_TIMEOUT;
42b1055e 2399 netdev->vlan_rx_register = jme_vlan_rx_register;
3bf61c55 2400 NETDEV_GET_STATS(netdev, &jme_get_stats);
42b1055e 2401 netdev->features = NETIF_F_HW_CSUM |
b3821cc5
GFT		 2402 NETIF_F_SG |
2403 NETIF_F_TSO |
2404 NETIF_F_TSO6 |
42b1055e
GFT		 2405 NETIF_F_HW_VLAN_TX |
2406 NETIF_F_HW_VLAN_RX;
3bf61c55 2407 if(using_dac)
8c198884 2408 netdev->features |= NETIF_F_HIGHDMA;
d7699f87
GFT		 2409
2410 SET_NETDEV_DEV(netdev, &pdev->dev);
2411 pci_set_drvdata(pdev, netdev);
2412
2413 /*
2414 * init adapter info
2415 */
2416 jme = netdev_priv(netdev);
2417 jme->pdev = pdev;
2418 jme->dev = netdev;
29bdd921 2419 jme->old_mtu = netdev->mtu = 1500;
fcf45b4c 2420 jme->phylink = 0;
b3821cc5
GFT		 2421 jme->tx_ring_size = 1 << 10;
2422 jme->tx_ring_mask = jme->tx_ring_size - 1;
2423 jme->tx_wake_threshold = 1 << 9;
2424 jme->rx_ring_size = 1 << 9;
2425 jme->rx_ring_mask = jme->rx_ring_size - 1;
d7699f87
GFT		 2426 jme->regs = ioremap(pci_resource_start(pdev, 0),
2427 pci_resource_len(pdev, 0));
4330c2f2 2428 if (!(jme->regs)) {
42b1055e 2429 printk(KERN_ERR PFX "Mapping PCI resource region error.\n");
d7699f87
GFT		 2430 rc = -ENOMEM;
2431 goto err_out_free_netdev;
2432 }
4330c2f2
GFT		 2433 jme->shadow_regs = pci_alloc_consistent(pdev,
2434 sizeof(__u32) * SHADOW_REG_NR,
2435 &(jme->shadow_dma));
2436 if (!(jme->shadow_regs)) {
42b1055e 2437 printk(KERN_ERR PFX "Allocating shadow register mapping error.\n");
4330c2f2
GFT		 2438 rc = -ENOMEM;
2439 goto err_out_unmap;
2440 }
2441
192570e0
GFT		 2442 netif_napi_add(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2);
2443
d7699f87 2444 spin_lock_init(&jme->phy_lock);
fcf45b4c 2445 spin_lock_init(&jme->macaddr_lock);
8c198884 2446 spin_lock_init(&jme->rxmcs_lock);
fcf45b4c 2447
fcf45b4c
GFT		 2448 atomic_set(&jme->link_changing, 1);
2449 atomic_set(&jme->rx_cleaning, 1);
2450 atomic_set(&jme->tx_cleaning, 1);
192570e0 2451 atomic_set(&jme->rx_empty, 1);
fcf45b4c 2452
79ce639c
GFT		 2453 tasklet_init(&jme->pcc_task,
2454 &jme_pcc_tasklet,
2455 (unsigned long) jme);
4330c2f2
GFT		 2456 tasklet_init(&jme->linkch_task,
2457 &jme_link_change_tasklet,
2458 (unsigned long) jme);
2459 tasklet_init(&jme->txclean_task,
2460 &jme_tx_clean_tasklet,
2461 (unsigned long) jme);
2462 tasklet_init(&jme->rxclean_task,
2463 &jme_rx_clean_tasklet,
2464 (unsigned long) jme);
fcf45b4c
GFT		 2465 tasklet_init(&jme->rxempty_task,
2466 &jme_rx_empty_tasklet,
2467 (unsigned long) jme);
d7699f87
GFT		 2468 jme->mii_if.dev = netdev;
2469 jme->mii_if.phy_id = 1;
2470 jme->mii_if.supports_gmii = 1;
2471 jme->mii_if.mdio_read = jme_mdio_read;
2472 jme->mii_if.mdio_write = jme_mdio_write;
2473
8c198884
GFT		 2474 jme->dpi.cur = PCC_P1;
2475
2476 jme->reg_ghc = GHC_DPX | GHC_SPEED_1000M;
79ce639c 2477 jme->reg_rxcs = RXCS_DEFAULT;
8c198884
GFT		 2478 jme->reg_rxmcs = RXMCS_DEFAULT;
2479 jme->reg_txpfc = 0;
b3821cc5 2480 jme->reg_pmcs = PMCS_LFEN | PMCS_LREN | PMCS_MFEN;
192570e0
GFT		 2481 jme->flags = JME_FLAG_TXCSUM | JME_FLAG_TSO | JME_FLAG_POLL;
2482
fcf45b4c
GFT		 2483 /*
2484 * Get Max Read Req Size from PCI Config Space
2485 */
2486 pci_read_config_byte(pdev, PCI_CONF_DCSR_MRRS, &jme->mrrs);
2487 switch(jme->mrrs) {
2488 case MRRS_128B:
2489 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2490 break;
2491 case MRRS_256B:
2492 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2493 break;
2494 default:
2495 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2496 break;
2497 };
2498
2499
d7699f87
GFT		 2500 /*
2501 * Reset MAC processor and reload EEPROM for MAC Address
2502 */
2503 jme_clear_pm(jme);
42b1055e
GFT		 2504 jme_set_phy_ps(jme);
2505 jme_phy_off(jme);
d7699f87 2506 jme_reset_mac_processor(jme);
4330c2f2
GFT		 2507 rc = jme_reload_eeprom(jme);
2508 if(rc) {
3bf61c55 2509 printk(KERN_ERR PFX
b3821cc5 2510 "Reload eeprom for reading MAC Address error.\n");
4330c2f2
GFT		 2511 goto err_out_free_shadow;
2512 }
d7699f87
GFT		 2513 jme_load_macaddr(netdev);
2514
2515
2516 /*
2517 * Tell stack that we are not ready to work until open()
2518 */
2519 netif_carrier_off(netdev);
2520 netif_stop_queue(netdev);
2521
2522 /*
2523 * Register netdev
2524 */
4330c2f2
GFT		 2525 rc = register_netdev(netdev);
2526 if(rc) {
2527 printk(KERN_ERR PFX "Cannot register net device.\n");
2528 goto err_out_free_shadow;
2529 }
d7699f87 2530
4330c2f2 2531 jprintk(netdev->name,
8c198884 2532 "JMC250 gigabit eth %02x:%02x:%02x:%02x:%02x:%02x\n",
4330c2f2
GFT		 2533 netdev->dev_addr[0],
2534 netdev->dev_addr[1],
2535 netdev->dev_addr[2],
2536 netdev->dev_addr[3],
2537 netdev->dev_addr[4],
8c198884 2538 netdev->dev_addr[5]);
d7699f87
GFT		 2539
2540 return 0;
2541
4330c2f2
GFT		 2542err_out_free_shadow:
2543 pci_free_consistent(pdev,
2544 sizeof(__u32) * SHADOW_REG_NR,
2545 jme->shadow_regs,
2546 jme->shadow_dma);
d7699f87
GFT		 2547err_out_unmap:
2548 iounmap(jme->regs);
2549err_out_free_netdev:
2550 pci_set_drvdata(pdev, NULL);
2551 free_netdev(netdev);
4330c2f2
GFT		 2552err_out_release_regions:
2553 pci_release_regions(pdev);
d7699f87
GFT		 2554err_out_disable_pdev:
2555 pci_disable_device(pdev);
d7699f87 2556err_out:
4330c2f2 2557 return rc;
d7699f87
GFT		 2558}
2559
3bf61c55
GFT		 2560static void __devexit
2561jme_remove_one(struct pci_dev *pdev)
2562{
d7699f87
GFT		 2563 struct net_device *netdev = pci_get_drvdata(pdev);
2564 struct jme_adapter *jme = netdev_priv(netdev);
2565
2566 unregister_netdev(netdev);
4330c2f2
GFT		 2567 pci_free_consistent(pdev,
2568 sizeof(__u32) * SHADOW_REG_NR,
2569 jme->shadow_regs,
2570 jme->shadow_dma);
d7699f87
GFT		 2571 iounmap(jme->regs);
2572 pci_set_drvdata(pdev, NULL);
2573 free_netdev(netdev);
2574 pci_release_regions(pdev);
2575 pci_disable_device(pdev);
2576
2577}
2578
29bdd921
GFT		 2579static int
2580jme_suspend(struct pci_dev *pdev, pm_message_t state)
2581{
2582 struct net_device *netdev = pci_get_drvdata(pdev);
2583 struct jme_adapter *jme = netdev_priv(netdev);
2584 int timeout = 100;
2585
2586 atomic_dec(&jme->link_changing);
2587
2588 netif_device_detach(netdev);
2589 netif_stop_queue(netdev);
2590 jme_stop_irq(jme);
2591 jme_free_irq(jme);
2592
2593 while(--timeout > 0 &&
2594 (
2595 atomic_read(&jme->rx_cleaning) != 1 ||
2596 atomic_read(&jme->tx_cleaning) != 1
2597 )) {
2598 mdelay(1);
2599 }
2600 if(!timeout) {
2601 jeprintk(netdev->name, "Waiting tasklets timeout.\n");
2602 return -EBUSY;
2603 }
2604 jme_disable_shadow(jme);
2605
2606 if(netif_carrier_ok(netdev)) {
2607 jme_stop_pcc_timer(jme);
2608 jme_reset_mac_processor(jme);
2609 jme_free_rx_resources(jme);
2610 jme_free_tx_resources(jme);
2611 netif_carrier_off(netdev);
2612 jme->phylink = 0;
192570e0
GFT		 2613
2614 if(jme->flags & JME_FLAG_POLL) {
2615 jme_polling_mode(jme);
2616 napi_disable(&jme->napi);
2617 }
29bdd921
GFT		 2618 }
2619
29bdd921
GFT		 2620
2621 pci_save_state(pdev);
2622 if(jme->reg_pmcs) {
42b1055e 2623 jme_set_100m_half(jme);
29bdd921 2624 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
42b1055e
GFT		 2625 pci_enable_wake(pdev, PCI_D3hot, true);
2626 pci_enable_wake(pdev, PCI_D3cold, true);
29bdd921
GFT		 2627 }
2628 else {
42b1055e
GFT		 2629 jme_phy_off(jme);
2630 pci_enable_wake(pdev, PCI_D3hot, false);
2631 pci_enable_wake(pdev, PCI_D3cold, false);
29bdd921
GFT		 2632 }
2633 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2634
2635 return 0;
2636}
2637
2638static int
2639jme_resume(struct pci_dev *pdev)
2640{
2641 struct net_device *netdev = pci_get_drvdata(pdev);
2642 struct jme_adapter *jme = netdev_priv(netdev);
2643
2644 jme_clear_pm(jme);
2645 pci_restore_state(pdev);
2646
2647 if(jme->flags & JME_FLAG_SSET)
2648 jme_set_settings(netdev, &jme->old_ecmd);
2649 else
2650 jme_reset_phy_processor(jme);
2651
2652 jme_reset_mac_processor(jme);
2653 jme_enable_shadow(jme);
2654 jme_request_irq(jme);
2655 jme_start_irq(jme);
2656 netif_device_attach(netdev);
2657
2658 atomic_inc(&jme->link_changing);
2659
2660 jme_reset_link(jme);
2661
2662 return 0;
2663}
2664
d7699f87
GFT		 2665static struct pci_device_id jme_pci_tbl[] = {
2666 { PCI_VDEVICE(JMICRON, 0x250) },
2667 { }
2668};
2669
2670static struct pci_driver jme_driver = {
2671 .name = DRV_NAME,
2672 .id_table = jme_pci_tbl,
2673 .probe = jme_init_one,
2674 .remove = __devexit_p(jme_remove_one),
d7699f87
GFT		 2675#ifdef CONFIG_PM
2676 .suspend = jme_suspend,
2677 .resume = jme_resume,
2678#endif /* CONFIG_PM */
d7699f87
GFT		 2679};
2680
3bf61c55
GFT		 2681static int __init
2682jme_init_module(void)
d7699f87 2683{
4330c2f2
GFT		 2684 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
2685 "driver version %s\n", DRV_VERSION);
d7699f87
GFT		 2686 return pci_register_driver(&jme_driver);
2687}
2688
3bf61c55
GFT		 2689static void __exit
2690jme_cleanup_module(void)
d7699f87
GFT		 2691{
2692 pci_unregister_driver(&jme_driver);
2693}
2694
2695module_init(jme_init_module);
2696module_exit(jme_cleanup_module);
2697
3bf61c55 2698MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
d7699f87
GFT		 2699MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
2700MODULE_LICENSE("GPL");
2701MODULE_VERSION(DRV_VERSION);
2702MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
2703
JMicron Ethernet Linux driver