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[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
04193058 50#define DRV_VERSION "2.0.16-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
e8e26350 56 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 57};
58
59/* ixgbe_pci_tbl - PCI Device ID Table
60 *
61 * Wildcard entries (PCI_ANY_ID) should come last
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 68 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 board_82598 },
9a799d71 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 73 board_82598 },
0befdb3e
JB		 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 77 board_82598 },
8d792cd9
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 board_82598 },
c4900be0
DS		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 board_82598 },
b95f5fcb
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 board_82598 },
2f21bdd3
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89 board_82598 },
e8e26350
PW		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91 board_82599 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93 board_82599 },
9a799d71
AK		 94
95 /* required last entry */
96 {0, }
97};
98MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
5dd2d332 100#ifdef CONFIG_IXGBE_DCA
bd0362dd 101static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 102 void *p);
bd0362dd
JC		 103static struct notifier_block dca_notifier = {
104 .notifier_call = ixgbe_notify_dca,
105 .next = NULL,
106 .priority = 0
107};
108#endif
109
9a799d71
AK		 110MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112MODULE_LICENSE("GPL");
113MODULE_VERSION(DRV_VERSION);
114
115#define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
5eba3699
AV		 117static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118{
119 u32 ctrl_ext;
120
121 /* Let firmware take over control of h/w */
122 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 124 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 125}
126
127static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128{
129 u32 ctrl_ext;
130
131 /* Let firmware know the driver has taken over */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 134 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 135}
9a799d71 136
e8e26350
PW		 137/*
138 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139 * @adapter: pointer to adapter struct
140 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141 * @queue: queue to map the corresponding interrupt to
142 * @msix_vector: the vector to map to the corresponding queue
143 *
144 */
145static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146 u8 queue, u8 msix_vector)
9a799d71
AK		 147{
148 u32 ivar, index;
e8e26350
PW		 149 struct ixgbe_hw *hw = &adapter->hw;
150 switch (hw->mac.type) {
151 case ixgbe_mac_82598EB:
152 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153 if (direction == -1)
154 direction = 0;
155 index = (((direction * 64) + queue) >> 2) & 0x1F;
156 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158 ivar |= (msix_vector << (8 * (queue & 0x3)));
159 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160 break;
161 case ixgbe_mac_82599EB:
162 if (direction == -1) {
163 /* other causes */
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 index = ((queue & 1) * 8);
166 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167 ivar &= ~(0xFF << index);
168 ivar |= (msix_vector << index);
169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170 break;
171 } else {
172 /* tx or rx causes */
173 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174 index = ((16 * (queue & 1)) + (8 * direction));
175 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176 ivar &= ~(0xFF << index);
177 ivar |= (msix_vector << index);
178 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179 break;
180 }
181 default:
182 break;
183 }
9a799d71
AK		 184}
185
186static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 187 struct ixgbe_tx_buffer
188 *tx_buffer_info)
9a799d71 189{
44df32c5 190 tx_buffer_info->dma = 0;
9a799d71 191 if (tx_buffer_info->skb) {
44df32c5
AD		 192 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
193 DMA_TO_DEVICE);
9a799d71
AK		 194 dev_kfree_skb_any(tx_buffer_info->skb);
195 tx_buffer_info->skb = NULL;
196 }
44df32c5 197 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 198 /* tx_buffer_info must be completely set up in the transmit path */
199}
200
201static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 202 struct ixgbe_ring *tx_ring,
203 unsigned int eop)
9a799d71 204{
e01c31a5 205 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 206
9a799d71 207 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 208 * check with the clearing of time_stamp and movement of eop */
9a799d71 209 adapter->detect_tx_hung = false;
44df32c5 210 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 211 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
212 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
213 /* detected Tx unit hang */
e01c31a5
JB		 214 union ixgbe_adv_tx_desc *tx_desc;
215 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 216 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 217 " Tx Queue <%d>\n"
218 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 219 " next_to_use <%x>\n"
220 " next_to_clean <%x>\n"
221 "tx_buffer_info[next_to_clean]\n"
222 " time_stamp <%lx>\n"
e01c31a5
JB		 223 " jiffies <%lx>\n",
224 tx_ring->queue_index,
44df32c5
AD		 225 IXGBE_READ_REG(hw, tx_ring->head),
226 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 227 tx_ring->next_to_use, eop,
228 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 229 return true;
230 }
231
232 return false;
233}
234
b4617240
PW		 235#define IXGBE_MAX_TXD_PWR 14
236#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 237
238/* Tx Descriptors needed, worst case */
239#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
240 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
241#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 242 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 243
e01c31a5
JB		 244static void ixgbe_tx_timeout(struct net_device *netdev);
245
9a799d71
AK		 246/**
247 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
248 * @adapter: board private structure
e01c31a5 249 * @tx_ring: tx ring to clean
9a1a69ad
JB		 250 *
251 * returns true if transmit work is done
9a799d71
AK		 252 **/
253static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 254 struct ixgbe_ring *tx_ring)
9a799d71 255{
e01c31a5 256 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 257 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
258 struct ixgbe_tx_buffer *tx_buffer_info;
259 unsigned int i, eop, count = 0;
e01c31a5 260 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 261
262 i = tx_ring->next_to_clean;
12207e49
PWJ		 263 eop = tx_ring->tx_buffer_info[i].next_to_watch;
264 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
265
266 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 267 (count < tx_ring->work_limit)) {
12207e49
PWJ		 268 bool cleaned = false;
269 for ( ; !cleaned; count++) {
270 struct sk_buff *skb;
9a799d71
AK		 271 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
272 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 273 cleaned = (i == eop);
e01c31a5 274 skb = tx_buffer_info->skb;
9a799d71 275
12207e49 276 if (cleaned && skb) {
e092be60 277 unsigned int segs, bytecount;
e01c31a5
JB		 278
279 /* gso_segs is currently only valid for tcp */
e092be60
AV		 280 segs = skb_shinfo(skb)->gso_segs ?: 1;
281 /* multiply data chunks by size of headers */
282 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 283 skb->len;
284 total_packets += segs;
285 total_bytes += bytecount;
e092be60 286 }
e01c31a5 287
9a799d71 288 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 289 tx_buffer_info);
9a799d71 290
12207e49
PWJ		 291 tx_desc->wb.status = 0;
292
9a799d71
AK		 293 i++;
294 if (i == tx_ring->count)
295 i = 0;
e01c31a5 296 }
12207e49
PWJ		 297
298 eop = tx_ring->tx_buffer_info[i].next_to_watch;
299 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
300 }
301
9a799d71
AK		 302 tx_ring->next_to_clean = i;
303
e092be60 304#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 305 if (unlikely(count && netif_carrier_ok(netdev) &&
306 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 307 /* Make sure that anybody stopping the queue after this
308 * sees the new next_to_clean.
309 */
310 smp_mb();
30eba97a
AV		 311 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
312 !test_bit(__IXGBE_DOWN, &adapter->state)) {
313 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 314 ++adapter->restart_queue;
30eba97a 315 }
e092be60 316 }
9a799d71 317
e01c31a5
JB		 318 if (adapter->detect_tx_hung) {
319 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
320 /* schedule immediate reset if we believe we hung */
321 DPRINTK(PROBE, INFO,
322 "tx hang %d detected, resetting adapter\n",
323 adapter->tx_timeout_count + 1);
324 ixgbe_tx_timeout(adapter->netdev);
325 }
326 }
9a799d71 327
e01c31a5 328 /* re-arm the interrupt */
9a1a69ad 329 if (count >= tx_ring->work_limit)
e01c31a5 330 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 331
e01c31a5
JB		 332 tx_ring->total_bytes += total_bytes;
333 tx_ring->total_packets += total_packets;
e01c31a5 334 tx_ring->stats.packets += total_packets;
12207e49 335 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 336 adapter->net_stats.tx_bytes += total_bytes;
337 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 338 return (count < tx_ring->work_limit);
9a799d71
AK		 339}
340
5dd2d332 341#ifdef CONFIG_IXGBE_DCA
bd0362dd 342static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 343 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 344{
345 u32 rxctrl;
346 int cpu = get_cpu();
3a581073 347 int q = rx_ring - adapter->rx_ring;
bd0362dd 348
3a581073 349 if (rx_ring->cpu != cpu) {
bd0362dd 350 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 351 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
352 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
353 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
354 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
355 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
356 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
357 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
358 }
bd0362dd
JC		 359 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
360 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 361 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
362 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 363 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 365 rx_ring->cpu = cpu;
bd0362dd
JC		 366 }
367 put_cpu();
368}
369
370static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 371 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 372{
373 u32 txctrl;
374 int cpu = get_cpu();
3a581073 375 int q = tx_ring - adapter->tx_ring;
bd0362dd 376
3a581073 377 if (tx_ring->cpu != cpu) {
bd0362dd 378 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 379 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
380 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
381 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
382 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
383 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
384 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
385 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
386 }
bd0362dd
JC		 387 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
388 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 389 tx_ring->cpu = cpu;
bd0362dd
JC		 390 }
391 put_cpu();
392}
393
394static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
395{
396 int i;
397
398 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
399 return;
400
401 for (i = 0; i < adapter->num_tx_queues; i++) {
402 adapter->tx_ring[i].cpu = -1;
403 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
404 }
405 for (i = 0; i < adapter->num_rx_queues; i++) {
406 adapter->rx_ring[i].cpu = -1;
407 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
408 }
409}
410
411static int __ixgbe_notify_dca(struct device *dev, void *data)
412{
413 struct net_device *netdev = dev_get_drvdata(dev);
414 struct ixgbe_adapter *adapter = netdev_priv(netdev);
415 unsigned long event = *(unsigned long *)data;
416
417 switch (event) {
418 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 419 /* if we're already enabled, don't do it again */
420 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
421 break;
bd0362dd
JC		 422 /* Always use CB2 mode, difference is masked
423 * in the CB driver. */
424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 425 if (dca_add_requester(dev) == 0) {
96b0e0f6 426 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 427 ixgbe_setup_dca(adapter);
428 break;
429 }
430 /* Fall Through since DCA is disabled. */
431 case DCA_PROVIDER_REMOVE:
432 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
433 dca_remove_requester(dev);
434 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
436 }
437 break;
438 }
439
652f093f 440 return 0;
bd0362dd
JC		 441}
442
5dd2d332 443#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 444/**
445 * ixgbe_receive_skb - Send a completed packet up the stack
446 * @adapter: board private structure
447 * @skb: packet to send up
177db6ff
MC		 448 * @status: hardware indication of status of receive
449 * @rx_ring: rx descriptor ring (for a specific queue) to setup
450 * @rx_desc: rx descriptor
9a799d71 451 **/
78b6f4ce 452static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 453 struct sk_buff *skb, u8 status,
177db6ff 454 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 455{
78b6f4ce
HX		 456 struct ixgbe_adapter *adapter = q_vector->adapter;
457 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 458 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
459 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 460
0c8dfc83 461 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
78b6f4ce 462 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
2f90b865 463 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 464 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 465 else
78b6f4ce 466 napi_gro_receive(napi, skb);
177db6ff
MC		 467 } else {
468 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 469 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 470 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
471 else
472 netif_receive_skb(skb);
473 } else {
2f90b865 474 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 475 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
476 else
477 netif_rx(skb);
478 }
9a799d71
AK		 479 }
480}
481
e59bd25d
AV		 482/**
483 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
484 * @adapter: address of board private structure
485 * @status_err: hardware indication of status of receive
486 * @skb: skb currently being received and modified
487 **/
9a799d71 488static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 489 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 490{
491 skb->ip_summed = CHECKSUM_NONE;
492
712744be
JB		 493 /* Rx csum disabled */
494 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 495 return;
e59bd25d
AV		 496
497 /* if IP and error */
498 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
499 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 500 adapter->hw_csum_rx_error++;
501 return;
502 }
e59bd25d
AV		 503
504 if (!(status_err & IXGBE_RXD_STAT_L4CS))
505 return;
506
507 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
508 adapter->hw_csum_rx_error++;
509 return;
510 }
511
9a799d71 512 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 513 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 514 adapter->hw_csum_rx_good++;
515}
516
e8e26350
PW		 517static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
518 struct ixgbe_ring *rx_ring, u32 val)
519{
520 /*
521 * Force memory writes to complete before letting h/w
522 * know there are new descriptors to fetch. (Only
523 * applicable for weak-ordered memory model archs,
524 * such as IA-64).
525 */
526 wmb();
527 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
528}
529
9a799d71
AK		 530/**
531 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
532 * @adapter: address of board private structure
533 **/
534static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 535 struct ixgbe_ring *rx_ring,
536 int cleaned_count)
9a799d71 537{
9a799d71
AK		 538 struct pci_dev *pdev = adapter->pdev;
539 union ixgbe_adv_rx_desc *rx_desc;
3a581073 540 struct ixgbe_rx_buffer *bi;
9a799d71 541 unsigned int i;
e8e26350 542 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 543
544 i = rx_ring->next_to_use;
3a581073 545 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 546
547 while (cleaned_count--) {
548 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
549
762f4c57 550 if (!bi->page_dma &&
3a581073 551 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 552 if (!bi->page) {
762f4c57
JB		 553 bi->page = alloc_page(GFP_ATOMIC);
554 if (!bi->page) {
555 adapter->alloc_rx_page_failed++;
556 goto no_buffers;
557 }
558 bi->page_offset = 0;
559 } else {
560 /* use a half page if we're re-using */
561 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 562 }
762f4c57
JB		 563
564 bi->page_dma = pci_map_page(pdev, bi->page,
565 bi->page_offset,
566 (PAGE_SIZE / 2),
567 PCI_DMA_FROMDEVICE);
9a799d71
AK		 568 }
569
3a581073 570 if (!bi->skb) {
5ecc3614 571 struct sk_buff *skb;
e8e26350 572 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 573
574 if (!skb) {
575 adapter->alloc_rx_buff_failed++;
576 goto no_buffers;
577 }
578
579 /*
580 * Make buffer alignment 2 beyond a 16 byte boundary
581 * this will result in a 16 byte aligned IP header after
582 * the 14 byte MAC header is removed
583 */
584 skb_reserve(skb, NET_IP_ALIGN);
585
3a581073 586 bi->skb = skb;
e8e26350 587 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 588 PCI_DMA_FROMDEVICE);
9a799d71
AK		 589 }
590 /* Refresh the desc even if buffer_addrs didn't change because
591 * each write-back erases this info. */
592 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 593 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
594 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 595 } else {
3a581073 596 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 597 }
598
599 i++;
600 if (i == rx_ring->count)
601 i = 0;
3a581073 602 bi = &rx_ring->rx_buffer_info[i];
9a799d71 603 }
7c6e0a43 604
9a799d71
AK		 605no_buffers:
606 if (rx_ring->next_to_use != i) {
607 rx_ring->next_to_use = i;
608 if (i-- == 0)
609 i = (rx_ring->count - 1);
610
e8e26350 611 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 612 }
613}
614
7c6e0a43
JB		 615static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
616{
617 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
618}
619
620static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
621{
622 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
623}
624
78b6f4ce 625static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 626 struct ixgbe_ring *rx_ring,
627 int *work_done, int work_to_do)
9a799d71 628{
78b6f4ce 629 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 630 struct pci_dev *pdev = adapter->pdev;
631 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
632 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
633 struct sk_buff *skb;
634 unsigned int i;
7c6e0a43 635 u32 len, staterr;
177db6ff
MC		 636 u16 hdr_info;
637 bool cleaned = false;
9a799d71 638 int cleaned_count = 0;
d2f4fbe2 639 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 640
641 i = rx_ring->next_to_clean;
9a799d71
AK		 642 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
643 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
644 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 645
646 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 647 u32 upper_len = 0;
9a799d71
AK		 648 if (*work_done >= work_to_do)
649 break;
650 (*work_done)++;
651
652 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 653 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
654 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 655 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 656 if (hdr_info & IXGBE_RXDADV_SPH)
657 adapter->rx_hdr_split++;
658 if (len > IXGBE_RX_HDR_SIZE)
659 len = IXGBE_RX_HDR_SIZE;
660 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 661 } else {
9a799d71 662 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 663 }
9a799d71
AK		 664
665 cleaned = true;
666 skb = rx_buffer_info->skb;
667 prefetch(skb->data - NET_IP_ALIGN);
668 rx_buffer_info->skb = NULL;
669
670 if (len && !skb_shinfo(skb)->nr_frags) {
671 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 672 rx_ring->rx_buf_len,
b4617240 673 PCI_DMA_FROMDEVICE);
9a799d71
AK		 674 skb_put(skb, len);
675 }
676
677 if (upper_len) {
678 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 679 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 680 rx_buffer_info->page_dma = 0;
681 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 682 rx_buffer_info->page,
683 rx_buffer_info->page_offset,
684 upper_len);
685
686 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
687 (page_count(rx_buffer_info->page) != 1))
688 rx_buffer_info->page = NULL;
689 else
690 get_page(rx_buffer_info->page);
9a799d71
AK		 691
692 skb->len += upper_len;
693 skb->data_len += upper_len;
694 skb->truesize += upper_len;
695 }
696
697 i++;
698 if (i == rx_ring->count)
699 i = 0;
700 next_buffer = &rx_ring->rx_buffer_info[i];
701
702 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
703 prefetch(next_rxd);
704
705 cleaned_count++;
706 if (staterr & IXGBE_RXD_STAT_EOP) {
707 rx_ring->stats.packets++;
708 rx_ring->stats.bytes += skb->len;
709 } else {
710 rx_buffer_info->skb = next_buffer->skb;
711 rx_buffer_info->dma = next_buffer->dma;
712 next_buffer->skb = skb;
762f4c57 713 next_buffer->dma = 0;
9a799d71
AK		 714 adapter->non_eop_descs++;
715 goto next_desc;
716 }
717
718 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
719 dev_kfree_skb_irq(skb);
720 goto next_desc;
721 }
722
723 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 724
725 /* probably a little skewed due to removing CRC */
726 total_rx_bytes += skb->len;
727 total_rx_packets++;
728
74ce8dd2 729 skb->protocol = eth_type_trans(skb, adapter->netdev);
78b6f4ce 730 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
9a799d71
AK		 731
732next_desc:
733 rx_desc->wb.upper.status_error = 0;
734
735 /* return some buffers to hardware, one at a time is too slow */
736 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
737 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
738 cleaned_count = 0;
739 }
740
741 /* use prefetched values */
742 rx_desc = next_rxd;
743 rx_buffer_info = next_buffer;
744
745 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 746 }
747
9a799d71
AK		 748 rx_ring->next_to_clean = i;
749 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
750
751 if (cleaned_count)
752 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
753
f494e8fa
AV		 754 rx_ring->total_packets += total_rx_packets;
755 rx_ring->total_bytes += total_rx_bytes;
756 adapter->net_stats.rx_bytes += total_rx_bytes;
757 adapter->net_stats.rx_packets += total_rx_packets;
758
9a799d71
AK		 759 return cleaned;
760}
761
021230d4 762static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 763/**
764 * ixgbe_configure_msix - Configure MSI-X hardware
765 * @adapter: board private structure
766 *
767 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
768 * interrupts.
769 **/
770static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
771{
021230d4
AV		 772 struct ixgbe_q_vector *q_vector;
773 int i, j, q_vectors, v_idx, r_idx;
774 u32 mask;
9a799d71 775
021230d4 776 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 777
4df10466
JB		 778 /*
779 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 780 * corresponding register.
781 */
782 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
783 q_vector = &adapter->q_vector[v_idx];
784 /* XXX for_each_bit(...) */
785 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 786 adapter->num_rx_queues);
021230d4
AV		 787
788 for (i = 0; i < q_vector->rxr_count; i++) {
789 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 790 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 791 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 792 adapter->num_rx_queues,
793 r_idx + 1);
021230d4
AV		 794 }
795 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 796 adapter->num_tx_queues);
021230d4
AV		 797
798 for (i = 0; i < q_vector->txr_count; i++) {
799 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 800 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 801 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 802 adapter->num_tx_queues,
803 r_idx + 1);
021230d4
AV		 804 }
805
30efa5a3 806 /* if this is a tx only vector halve the interrupt rate */
021230d4 807 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 808 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 809 else if (q_vector->rxr_count)
30efa5a3
JB		 810 /* rx only */
811 q_vector->eitr = adapter->eitr_param;
021230d4 812
509ee935 813 /*
4df10466 814 * since this is initial set up don't need to call
509ee935
JB		 815 * ixgbe_write_eitr helper
816 */
021230d4 817 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 818 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 819 }
820
e8e26350
PW		 821 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
822 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
823 v_idx);
824 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
825 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
827
41fb9248 828 /* set up to autoclear timer, and the vectors */
021230d4 829 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 830 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 831 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 832}
833
f494e8fa
AV		 834enum latency_range {
835 lowest_latency = 0,
836 low_latency = 1,
837 bulk_latency = 2,
838 latency_invalid = 255
839};
840
841/**
842 * ixgbe_update_itr - update the dynamic ITR value based on statistics
843 * @adapter: pointer to adapter
844 * @eitr: eitr setting (ints per sec) to give last timeslice
845 * @itr_setting: current throttle rate in ints/second
846 * @packets: the number of packets during this measurement interval
847 * @bytes: the number of bytes during this measurement interval
848 *
849 * Stores a new ITR value based on packets and byte
850 * counts during the last interrupt. The advantage of per interrupt
851 * computation is faster updates and more accurate ITR for the current
852 * traffic pattern. Constants in this function were computed
853 * based on theoretical maximum wire speed and thresholds were set based
854 * on testing data as well as attempting to minimize response time
855 * while increasing bulk throughput.
856 * this functionality is controlled by the InterruptThrottleRate module
857 * parameter (see ixgbe_param.c)
858 **/
859static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 860 u32 eitr, u8 itr_setting,
861 int packets, int bytes)
f494e8fa
AV		 862{
863 unsigned int retval = itr_setting;
864 u32 timepassed_us;
865 u64 bytes_perint;
866
867 if (packets == 0)
868 goto update_itr_done;
869
870
871 /* simple throttlerate management
872 * 0-20MB/s lowest (100000 ints/s)
873 * 20-100MB/s low (20000 ints/s)
874 * 100-1249MB/s bulk (8000 ints/s)
875 */
876 /* what was last interrupt timeslice? */
877 timepassed_us = 1000000/eitr;
878 bytes_perint = bytes / timepassed_us; /* bytes/usec */
879
880 switch (itr_setting) {
881 case lowest_latency:
882 if (bytes_perint > adapter->eitr_low)
883 retval = low_latency;
884 break;
885 case low_latency:
886 if (bytes_perint > adapter->eitr_high)
887 retval = bulk_latency;
888 else if (bytes_perint <= adapter->eitr_low)
889 retval = lowest_latency;
890 break;
891 case bulk_latency:
892 if (bytes_perint <= adapter->eitr_high)
893 retval = low_latency;
894 break;
895 }
896
897update_itr_done:
898 return retval;
899}
900
509ee935
JB		 901/**
902 * ixgbe_write_eitr - write EITR register in hardware specific way
903 * @adapter: pointer to adapter struct
904 * @v_idx: vector index into q_vector array
905 * @itr_reg: new value to be written in *register* format, not ints/s
906 *
907 * This function is made to be called by ethtool and by the driver
908 * when it needs to update EITR registers at runtime. Hardware
909 * specific quirks/differences are taken care of here.
910 */
911void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
912{
913 struct ixgbe_hw *hw = &adapter->hw;
914 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
915 /* must write high and low 16 bits to reset counter */
916 itr_reg |= (itr_reg << 16);
917 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
918 /*
919 * set the WDIS bit to not clear the timer bits and cause an
920 * immediate assertion of the interrupt
921 */
922 itr_reg |= IXGBE_EITR_CNT_WDIS;
923 }
924 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
925}
926
f494e8fa
AV		 927static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
928{
929 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 930 u32 new_itr;
931 u8 current_itr, ret_itr;
932 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 933 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 934 struct ixgbe_ring *rx_ring, *tx_ring;
935
936 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
937 for (i = 0; i < q_vector->txr_count; i++) {
938 tx_ring = &(adapter->tx_ring[r_idx]);
939 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 940 q_vector->tx_itr,
941 tx_ring->total_packets,
942 tx_ring->total_bytes);
f494e8fa
AV		 943 /* if the result for this queue would decrease interrupt
944 * rate for this vector then use that result */
30efa5a3 945 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 946 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 947 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 948 r_idx + 1);
f494e8fa
AV		 949 }
950
951 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
952 for (i = 0; i < q_vector->rxr_count; i++) {
953 rx_ring = &(adapter->rx_ring[r_idx]);
954 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 955 q_vector->rx_itr,
956 rx_ring->total_packets,
957 rx_ring->total_bytes);
f494e8fa
AV		 958 /* if the result for this queue would decrease interrupt
959 * rate for this vector then use that result */
30efa5a3 960 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 961 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 962 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 963 r_idx + 1);
f494e8fa
AV		 964 }
965
30efa5a3 966 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 967
968 switch (current_itr) {
969 /* counts and packets in update_itr are dependent on these numbers */
970 case lowest_latency:
971 new_itr = 100000;
972 break;
973 case low_latency:
974 new_itr = 20000; /* aka hwitr = ~200 */
975 break;
976 case bulk_latency:
977 default:
978 new_itr = 8000;
979 break;
980 }
981
982 if (new_itr != q_vector->eitr) {
983 u32 itr_reg;
509ee935
JB		 984
985 /* save the algorithm value here, not the smoothed one */
986 q_vector->eitr = new_itr;
f494e8fa
AV		 987 /* do an exponential smoothing */
988 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 989 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 990 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 991 }
992
993 return;
994}
995
0befdb3e
JB		 996static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
997{
998 struct ixgbe_hw *hw = &adapter->hw;
999
1000 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1001 (eicr & IXGBE_EICR_GPI_SDP1)) {
1002 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1003 /* write to clear the interrupt */
1004 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1005 }
1006}
cf8280ee 1007
e8e26350
PW		 1008static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1009{
1010 struct ixgbe_hw *hw = &adapter->hw;
1011
1012 if (eicr & IXGBE_EICR_GPI_SDP1) {
1013 /* Clear the interrupt */
1014 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1015 schedule_work(&adapter->multispeed_fiber_task);
1016 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1017 /* Clear the interrupt */
1018 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1019 schedule_work(&adapter->sfp_config_module_task);
1020 } else {
1021 /* Interrupt isn't for us... */
1022 return;
1023 }
1024}
1025
cf8280ee
JB		 1026static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1027{
1028 struct ixgbe_hw *hw = &adapter->hw;
1029
1030 adapter->lsc_int++;
1031 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1032 adapter->link_check_timeout = jiffies;
1033 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1034 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1035 schedule_work(&adapter->watchdog_task);
1036 }
1037}
1038
9a799d71
AK		 1039static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1040{
1041 struct net_device *netdev = data;
1042 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1043 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1044 u32 eicr;
1045
1046 /*
1047 * Workaround for Silicon errata. Use clear-by-write instead
1048 * of clear-by-read. Reading with EICS will return the
1049 * interrupt causes without clearing, which later be done
1050 * with the write to EICR.
1051 */
1052 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1053 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1054
cf8280ee
JB		 1055 if (eicr & IXGBE_EICR_LSC)
1056 ixgbe_check_lsc(adapter);
d4f80882 1057
e8e26350
PW		 1058 if (hw->mac.type == ixgbe_mac_82598EB)
1059 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1060
e8e26350
PW		 1061 if (hw->mac.type == ixgbe_mac_82599EB)
1062 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1063 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1064 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1065
1066 return IRQ_HANDLED;
1067}
1068
1069static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1070{
021230d4
AV		 1071 struct ixgbe_q_vector *q_vector = data;
1072 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1073 struct ixgbe_ring *tx_ring;
021230d4
AV		 1074 int i, r_idx;
1075
1076 if (!q_vector->txr_count)
1077 return IRQ_HANDLED;
1078
1079 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1080 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1081 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1082#ifdef CONFIG_IXGBE_DCA
bd0362dd 1083 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1084 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1085#endif
3a581073
JB		 1086 tx_ring->total_bytes = 0;
1087 tx_ring->total_packets = 0;
1088 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1089 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1090 r_idx + 1);
021230d4 1091 }
9a799d71 1092
9a799d71
AK		 1093 return IRQ_HANDLED;
1094}
1095
021230d4
AV		 1096/**
1097 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1098 * @irq: unused
1099 * @data: pointer to our q_vector struct for this interrupt vector
1100 **/
9a799d71
AK		 1101static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1102{
021230d4
AV		 1103 struct ixgbe_q_vector *q_vector = data;
1104 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1105 struct ixgbe_ring *rx_ring;
021230d4 1106 int r_idx;
30efa5a3 1107 int i;
021230d4
AV		 1108
1109 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1110 for (i = 0; i < q_vector->rxr_count; i++) {
1111 rx_ring = &(adapter->rx_ring[r_idx]);
1112 rx_ring->total_bytes = 0;
1113 rx_ring->total_packets = 0;
1114 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1115 r_idx + 1);
1116 }
1117
021230d4
AV		 1118 if (!q_vector->rxr_count)
1119 return IRQ_HANDLED;
1120
30efa5a3 1121 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1122 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1123 /* disable interrupts on this vector only */
3a581073 1124 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
288379f0 1125 napi_schedule(&q_vector->napi);
021230d4
AV		 1126
1127 return IRQ_HANDLED;
1128}
1129
1130static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1131{
1132 ixgbe_msix_clean_rx(irq, data);
1133 ixgbe_msix_clean_tx(irq, data);
9a799d71 1134
9a799d71
AK		 1135 return IRQ_HANDLED;
1136}
1137
021230d4
AV		 1138/**
1139 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1140 * @napi: napi struct with our devices info in it
1141 * @budget: amount of work driver is allowed to do this pass, in packets
1142 *
f0848276
JB		 1143 * This function is optimized for cleaning one queue only on a single
1144 * q_vector!!!
021230d4 1145 **/
9a799d71
AK		 1146static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1147{
021230d4 1148 struct ixgbe_q_vector *q_vector =
b4617240 1149 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1150 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1151 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1152 int work_done = 0;
021230d4 1153 long r_idx;
9a799d71 1154
021230d4 1155 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1156 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1157#ifdef CONFIG_IXGBE_DCA
bd0362dd 1158 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1159 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1160#endif
9a799d71 1161
78b6f4ce 1162 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1163
021230d4
AV		 1164 /* If all Rx work done, exit the polling mode */
1165 if (work_done < budget) {
288379f0 1166 napi_complete(napi);
509ee935 1167 if (adapter->itr_setting & 1)
f494e8fa 1168 ixgbe_set_itr_msix(q_vector);
9a799d71 1169 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1170 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1171 }
1172
1173 return work_done;
1174}
1175
f0848276
JB		 1176/**
1177 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1178 * @napi: napi struct with our devices info in it
1179 * @budget: amount of work driver is allowed to do this pass, in packets
1180 *
1181 * This function will clean more than one rx queue associated with a
1182 * q_vector.
1183 **/
1184static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1185{
1186 struct ixgbe_q_vector *q_vector =
1187 container_of(napi, struct ixgbe_q_vector, napi);
1188 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1189 struct ixgbe_ring *rx_ring = NULL;
1190 int work_done = 0, i;
1191 long r_idx;
1192 u16 enable_mask = 0;
1193
1194 /* attempt to distribute budget to each queue fairly, but don't allow
1195 * the budget to go below 1 because we'll exit polling */
1196 budget /= (q_vector->rxr_count ?: 1);
1197 budget = max(budget, 1);
1198 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1199 for (i = 0; i < q_vector->rxr_count; i++) {
1200 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1201#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1202 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1203 ixgbe_update_rx_dca(adapter, rx_ring);
1204#endif
78b6f4ce 1205 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1206 enable_mask |= rx_ring->v_idx;
1207 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1208 r_idx + 1);
1209 }
1210
1211 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1212 rx_ring = &(adapter->rx_ring[r_idx]);
1213 /* If all Rx work done, exit the polling mode */
7f821875 1214 if (work_done < budget) {
288379f0 1215 napi_complete(napi);
509ee935 1216 if (adapter->itr_setting & 1)
f0848276
JB		 1217 ixgbe_set_itr_msix(q_vector);
1218 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1219 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1220 return 0;
1221 }
1222
1223 return work_done;
1224}
021230d4 1225static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1226 int r_idx)
021230d4
AV		 1227{
1228 a->q_vector[v_idx].adapter = a;
1229 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1230 a->q_vector[v_idx].rxr_count++;
1231 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1232}
1233
1234static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1235 int r_idx)
021230d4
AV		 1236{
1237 a->q_vector[v_idx].adapter = a;
1238 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1239 a->q_vector[v_idx].txr_count++;
1240 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1241}
1242
9a799d71 1243/**
021230d4
AV		 1244 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1245 * @adapter: board private structure to initialize
1246 * @vectors: allotted vector count for descriptor rings
9a799d71 1247 *
021230d4
AV		 1248 * This function maps descriptor rings to the queue-specific vectors
1249 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1250 * one vector per ring/queue, but on a constrained vector budget, we
1251 * group the rings as "efficiently" as possible. You would add new
1252 * mapping configurations in here.
9a799d71 1253 **/
021230d4 1254static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1255 int vectors)
021230d4
AV		 1256{
1257 int v_start = 0;
1258 int rxr_idx = 0, txr_idx = 0;
1259 int rxr_remaining = adapter->num_rx_queues;
1260 int txr_remaining = adapter->num_tx_queues;
1261 int i, j;
1262 int rqpv, tqpv;
1263 int err = 0;
1264
1265 /* No mapping required if MSI-X is disabled. */
1266 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1267 goto out;
9a799d71 1268
021230d4
AV		 1269 /*
1270 * The ideal configuration...
1271 * We have enough vectors to map one per queue.
1272 */
1273 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1274 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1275 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1276
021230d4
AV		 1277 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1278 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1279
9a799d71 1280 goto out;
021230d4 1281 }
9a799d71 1282
021230d4
AV		 1283 /*
1284 * If we don't have enough vectors for a 1-to-1
1285 * mapping, we'll have to group them so there are
1286 * multiple queues per vector.
1287 */
1288 /* Re-adjusting *qpv takes care of the remainder. */
1289 for (i = v_start; i < vectors; i++) {
1290 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1291 for (j = 0; j < rqpv; j++) {
1292 map_vector_to_rxq(adapter, i, rxr_idx);
1293 rxr_idx++;
1294 rxr_remaining--;
1295 }
1296 }
1297 for (i = v_start; i < vectors; i++) {
1298 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1299 for (j = 0; j < tqpv; j++) {
1300 map_vector_to_txq(adapter, i, txr_idx);
1301 txr_idx++;
1302 txr_remaining--;
9a799d71 1303 }
9a799d71
AK		 1304 }
1305
021230d4
AV		 1306out:
1307 return err;
1308}
1309
1310/**
1311 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1312 * @adapter: board private structure
1313 *
1314 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1315 * interrupts from the kernel.
1316 **/
1317static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1318{
1319 struct net_device *netdev = adapter->netdev;
1320 irqreturn_t (*handler)(int, void *);
1321 int i, vector, q_vectors, err;
cb13fc20 1322 int ri=0, ti=0;
021230d4
AV		 1323
1324 /* Decrement for Other and TCP Timer vectors */
1325 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1326
1327 /* Map the Tx/Rx rings to the vectors we were allotted. */
1328 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1329 if (err)
1330 goto out;
1331
1332#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1333 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1334 &ixgbe_msix_clean_many)
021230d4
AV		 1335 for (vector = 0; vector < q_vectors; vector++) {
1336 handler = SET_HANDLER(&adapter->q_vector[vector]);
cb13fc20
RO		 1337
1338 if(handler == &ixgbe_msix_clean_rx) {
1339 sprintf(adapter->name[vector], "%s-%s-%d",
1340 netdev->name, "rx", ri++);
1341 }
1342 else if(handler == &ixgbe_msix_clean_tx) {
1343 sprintf(adapter->name[vector], "%s-%s-%d",
1344 netdev->name, "tx", ti++);
1345 }
1346 else
1347 sprintf(adapter->name[vector], "%s-%s-%d",
1348 netdev->name, "TxRx", vector);
1349
021230d4 1350 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1351 handler, 0, adapter->name[vector],
1352 &(adapter->q_vector[vector]));
9a799d71
AK		 1353 if (err) {
1354 DPRINTK(PROBE, ERR,
b4617240
PW		 1355 "request_irq failed for MSIX interrupt "
1356 "Error: %d\n", err);
021230d4 1357 goto free_queue_irqs;
9a799d71 1358 }
9a799d71
AK		 1359 }
1360
021230d4
AV		 1361 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1362 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1363 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1364 if (err) {
1365 DPRINTK(PROBE, ERR,
1366 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1367 goto free_queue_irqs;
9a799d71
AK		 1368 }
1369
9a799d71
AK		 1370 return 0;
1371
021230d4
AV		 1372free_queue_irqs:
1373 for (i = vector - 1; i >= 0; i--)
1374 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1375 &(adapter->q_vector[i]));
021230d4
AV		 1376 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1377 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1378 kfree(adapter->msix_entries);
1379 adapter->msix_entries = NULL;
021230d4 1380out:
9a799d71
AK		 1381 return err;
1382}
1383
f494e8fa
AV		 1384static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1385{
f494e8fa
AV		 1386 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1387 u8 current_itr;
1388 u32 new_itr = q_vector->eitr;
1389 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1390 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1391
30efa5a3 1392 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1393 q_vector->tx_itr,
1394 tx_ring->total_packets,
1395 tx_ring->total_bytes);
30efa5a3 1396 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1397 q_vector->rx_itr,
1398 rx_ring->total_packets,
1399 rx_ring->total_bytes);
f494e8fa 1400
30efa5a3 1401 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1402
1403 switch (current_itr) {
1404 /* counts and packets in update_itr are dependent on these numbers */
1405 case lowest_latency:
1406 new_itr = 100000;
1407 break;
1408 case low_latency:
1409 new_itr = 20000; /* aka hwitr = ~200 */
1410 break;
1411 case bulk_latency:
1412 new_itr = 8000;
1413 break;
1414 default:
1415 break;
1416 }
1417
1418 if (new_itr != q_vector->eitr) {
1419 u32 itr_reg;
509ee935
JB		 1420
1421 /* save the algorithm value here, not the smoothed one */
1422 q_vector->eitr = new_itr;
f494e8fa
AV		 1423 /* do an exponential smoothing */
1424 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1425 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1426 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1427 }
1428
1429 return;
1430}
1431
79aefa45
AD		 1432/**
1433 * ixgbe_irq_enable - Enable default interrupt generation settings
1434 * @adapter: board private structure
1435 **/
1436static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1437{
1438 u32 mask;
1439 mask = IXGBE_EIMS_ENABLE_MASK;
6ab33d51
DM		 1440 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1441 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1442 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1443 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1444 mask |= IXGBE_EIMS_GPI_SDP1;
1445 mask |= IXGBE_EIMS_GPI_SDP2;
1446 }
1447
79aefa45 1448 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
e8e26350
PW		 1449 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1450 /* enable the rest of the queue vectors */
1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1),
1452 (IXGBE_EIMS_RTX_QUEUE << 16));
1453 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1454 ((IXGBE_EIMS_RTX_QUEUE << 16) |
1455 IXGBE_EIMS_RTX_QUEUE));
1456 }
79aefa45
AD		 1457 IXGBE_WRITE_FLUSH(&adapter->hw);
1458}
021230d4 1459
9a799d71 1460/**
021230d4 1461 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1462 * @irq: interrupt number
1463 * @data: pointer to a network interface device structure
9a799d71
AK		 1464 **/
1465static irqreturn_t ixgbe_intr(int irq, void *data)
1466{
1467 struct net_device *netdev = data;
1468 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1469 struct ixgbe_hw *hw = &adapter->hw;
1470 u32 eicr;
1471
54037505
DS		 1472 /*
1473 * Workaround for silicon errata. Mask the interrupts
1474 * before the read of EICR.
1475 */
1476 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1477
021230d4
AV		 1478 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1479 * therefore no explict interrupt disable is necessary */
1480 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1481 if (!eicr) {
1482 /* shared interrupt alert!
1483 * make sure interrupts are enabled because the read will
1484 * have disabled interrupts due to EIAM */
1485 ixgbe_irq_enable(adapter);
9a799d71 1486 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1487 }
9a799d71 1488
cf8280ee
JB		 1489 if (eicr & IXGBE_EICR_LSC)
1490 ixgbe_check_lsc(adapter);
021230d4 1491
e8e26350
PW		 1492 if (hw->mac.type == ixgbe_mac_82599EB)
1493 ixgbe_check_sfp_event(adapter, eicr);
1494
0befdb3e
JB		 1495 ixgbe_check_fan_failure(adapter, eicr);
1496
288379f0 1497 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
f494e8fa
AV		 1498 adapter->tx_ring[0].total_packets = 0;
1499 adapter->tx_ring[0].total_bytes = 0;
1500 adapter->rx_ring[0].total_packets = 0;
1501 adapter->rx_ring[0].total_bytes = 0;
021230d4 1502 /* would disable interrupts here but EIAM disabled it */
288379f0 1503 __napi_schedule(&adapter->q_vector[0].napi);
9a799d71
AK		 1504 }
1505
1506 return IRQ_HANDLED;
1507}
1508
021230d4
AV		 1509static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1510{
1511 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1512
1513 for (i = 0; i < q_vectors; i++) {
1514 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1515 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1516 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1517 q_vector->rxr_count = 0;
1518 q_vector->txr_count = 0;
1519 }
1520}
1521
9a799d71
AK		 1522/**
1523 * ixgbe_request_irq - initialize interrupts
1524 * @adapter: board private structure
1525 *
1526 * Attempts to configure interrupts using the best available
1527 * capabilities of the hardware and kernel.
1528 **/
021230d4 1529static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1530{
1531 struct net_device *netdev = adapter->netdev;
021230d4 1532 int err;
9a799d71 1533
021230d4
AV		 1534 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1535 err = ixgbe_request_msix_irqs(adapter);
1536 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1537 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1538 netdev->name, netdev);
021230d4
AV		 1539 } else {
1540 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1541 netdev->name, netdev);
9a799d71
AK		 1542 }
1543
9a799d71
AK		 1544 if (err)
1545 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1546
9a799d71
AK		 1547 return err;
1548}
1549
1550static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1551{
1552 struct net_device *netdev = adapter->netdev;
1553
1554 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1555 int i, q_vectors;
9a799d71 1556
021230d4
AV		 1557 q_vectors = adapter->num_msix_vectors;
1558
1559 i = q_vectors - 1;
9a799d71 1560 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1561
021230d4
AV		 1562 i--;
1563 for (; i >= 0; i--) {
1564 free_irq(adapter->msix_entries[i].vector,
b4617240 1565 &(adapter->q_vector[i]));
021230d4
AV		 1566 }
1567
1568 ixgbe_reset_q_vectors(adapter);
1569 } else {
1570 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1571 }
1572}
1573
22d5a71b
JB		 1574/**
1575 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1576 * @adapter: board private structure
1577 **/
1578static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1579{
1580 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1581 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(2), ~0);
1584 }
1585 IXGBE_WRITE_FLUSH(&adapter->hw);
1586 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1587 int i;
1588 for (i = 0; i < adapter->num_msix_vectors; i++)
1589 synchronize_irq(adapter->msix_entries[i].vector);
1590 } else {
1591 synchronize_irq(adapter->pdev->irq);
1592 }
1593}
1594
1595static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter)
1596{
1597 u32 mask = IXGBE_EIMS_RTX_QUEUE;
1598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1599 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask << 16);
1601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1602 (mask << 16 | mask));
1603 }
1604 /* skip the flush */
1605}
1606
9a799d71
AK		 1607/**
1608 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1609 *
1610 **/
1611static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1612{
9a799d71
AK		 1613 struct ixgbe_hw *hw = &adapter->hw;
1614
021230d4 1615 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1616 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1617
e8e26350
PW		 1618 ixgbe_set_ivar(adapter, 0, 0, 0);
1619 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1620
1621 map_vector_to_rxq(adapter, 0, 0);
1622 map_vector_to_txq(adapter, 0, 0);
1623
1624 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1625}
1626
1627/**
3a581073 1628 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1629 * @adapter: board private structure
1630 *
1631 * Configure the Tx unit of the MAC after a reset.
1632 **/
1633static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1634{
12207e49 1635 u64 tdba;
9a799d71 1636 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1637 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1638
1639 /* Setup the HW Tx Head and Tail descriptor pointers */
1640 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1641 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1642 j = ring->reg_idx;
1643 tdba = ring->dma;
1644 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1645 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1646 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1647 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1648 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1649 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1650 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1651 adapter->tx_ring[i].head = IXGBE_TDH(j);
1652 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1653 /* Disable Tx Head Writeback RO bit, since this hoses
1654 * bookkeeping if things aren't delivered in order.
1655 */
e01c31a5 1656 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1657 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1658 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1659 }
e8e26350
PW		 1660 if (hw->mac.type == ixgbe_mac_82599EB) {
1661 /* We enable 8 traffic classes, DCB only */
1662 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1663 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1664 IXGBE_MTQC_8TC_8TQ));
1665 }
9a799d71
AK		 1666}
1667
e8e26350 1668#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1669
1670static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1671{
1672 struct ixgbe_ring *rx_ring;
1673 u32 srrctl;
e8e26350 1674 int queue0 = 0;
3be1adfb
AD		 1675 unsigned long mask;
1676
e8e26350
PW		 1677 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1678 queue0 = index;
cc41ac7c 1679 } else {
3be1adfb
AD		 1680 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1681 queue0 = index & mask;
1682 index = index & mask;
cc41ac7c 1683 }
3be1adfb 1684
cc41ac7c
JB		 1685 rx_ring = &adapter->rx_ring[queue0];
1686
1687 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1688
1689 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1690 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1691
1692 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
32344a39
JB		 1693 u16 bufsz = IXGBE_RXBUFFER_2048;
1694 /* grow the amount we can receive on large page machines */
1695 if (bufsz < (PAGE_SIZE / 2))
1696 bufsz = (PAGE_SIZE / 2);
1697 /* cap the bufsz at our largest descriptor size */
1698 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1699
1700 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c
JB		 1701 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1702 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1703 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1704 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1705 } else {
1706 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1707
1708 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1709 srrctl |= IXGBE_RXBUFFER_2048 >>
1710 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1711 else
1712 srrctl |= rx_ring->rx_buf_len >>
1713 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1714 }
e8e26350 1715
cc41ac7c
JB		 1716 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1717}
9a799d71 1718
9a799d71 1719/**
3a581073 1720 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1721 * @adapter: board private structure
1722 *
1723 * Configure the Rx unit of the MAC after a reset.
1724 **/
1725static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1726{
1727 u64 rdba;
1728 struct ixgbe_hw *hw = &adapter->hw;
1729 struct net_device *netdev = adapter->netdev;
1730 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1731 int i, j;
9a799d71 1732 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1733 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1734 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1735 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1736 u32 fctrl, hlreg0;
509ee935 1737 u32 reta = 0, mrqc = 0;
cc41ac7c 1738 u32 rdrxctl;
7c6e0a43 1739 int rx_buf_len;
9a799d71
AK		 1740
1741 /* Decide whether to use packet split mode or not */
762f4c57 1742 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1743
1744 /* Set the RX buffer length according to the mode */
1745 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1746 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1747 if (hw->mac.type == ixgbe_mac_82599EB) {
1748 /* PSRTYPE must be initialized in 82599 */
1749 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1750 IXGBE_PSRTYPE_UDPHDR |
1751 IXGBE_PSRTYPE_IPV4HDR |
1752 IXGBE_PSRTYPE_IPV6HDR;
1753 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1754 }
9a799d71
AK		 1755 } else {
1756 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1757 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1758 else
7c6e0a43 1759 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1760 }
1761
1762 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1763 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1764 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1765 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1766 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1767
1768 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1769 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1770 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1771 else
1772 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1773 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1774
9a799d71
AK		 1775 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1776 /* disable receives while setting up the descriptors */
1777 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1778 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1779
1780 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1781 * the Base and Length of the Rx Descriptor Ring */
1782 for (i = 0; i < adapter->num_rx_queues; i++) {
1783 rdba = adapter->rx_ring[i].dma;
7c6e0a43 1784 j = adapter->rx_ring[i].reg_idx;
284901a9 1785 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 1786 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1787 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1788 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1789 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1790 adapter->rx_ring[i].head = IXGBE_RDH(j);
1791 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1792 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c
JB		 1793
1794 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1795 }
1796
e8e26350
PW		 1797 if (hw->mac.type == ixgbe_mac_82598EB) {
1798 /*
1799 * For VMDq support of different descriptor types or
1800 * buffer sizes through the use of multiple SRRCTL
1801 * registers, RDRXCTL.MVMEN must be set to 1
1802 *
1803 * also, the manual doesn't mention it clearly but DCA hints
1804 * will only use queue 0's tags unless this bit is set. Side
1805 * effects of setting this bit are only that SRRCTL must be
1806 * fully programmed [0..15]
1807 */
2a41ff81
JB		 1808 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1809 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1810 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 1811 }
177db6ff 1812
e8e26350
PW		 1813 /* Program MRQC for the distribution of queues */
1814 if (hw->mac.type == ixgbe_mac_82599EB) {
1815 int mask = adapter->flags & (
1816 IXGBE_FLAG_RSS_ENABLED
1817 | IXGBE_FLAG_DCB_ENABLED
1818 );
1819
1820 switch (mask) {
1821 case (IXGBE_FLAG_RSS_ENABLED):
1822 mrqc = IXGBE_MRQC_RSSEN;
1823 break;
1824 case (IXGBE_FLAG_DCB_ENABLED):
1825 mrqc = IXGBE_MRQC_RT8TCEN;
1826 break;
1827 default:
1828 break;
1829 }
1830 }
021230d4 1831 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1832 /* Fill out redirection table */
021230d4
AV		 1833 for (i = 0, j = 0; i < 128; i++, j++) {
1834 if (j == adapter->ring_feature[RING_F_RSS].indices)
1835 j = 0;
1836 /* reta = 4-byte sliding window of
1837 * 0x00..(indices-1)(indices-1)00..etc. */
1838 reta = (reta << 8) | (j * 0x11);
1839 if ((i & 3) == 3)
1840 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1841 }
1842
1843 /* Fill out hash function seeds */
1844 for (i = 0; i < 10; i++)
7c6e0a43 1845 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 1846
2a41ff81
JB		 1847 if (hw->mac.type == ixgbe_mac_82598EB)
1848 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 1849 /* Perform hash on these packet types */
2a41ff81
JB		 1850 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1851 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1852 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1853 | IXGBE_MRQC_RSS_FIELD_IPV6
1854 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1855 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 1856 }
2a41ff81 1857 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 1858
021230d4
AV		 1859 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1860
1861 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1862 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1863 /* Disable indicating checksum in descriptor, enables
1864 * RSS hash */
9a799d71 1865 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1866 }
021230d4
AV		 1867 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1868 /* Enable IPv4 payload checksum for UDP fragments
1869 * if PCSD is not set */
1870 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1871 }
1872
1873 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 1874
1875 if (hw->mac.type == ixgbe_mac_82599EB) {
1876 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1877 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1878 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1879 }
9a799d71
AK		 1880}
1881
068c89b0
DS		 1882static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1883{
1884 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1885 struct ixgbe_hw *hw = &adapter->hw;
1886
1887 /* add VID to filter table */
1888 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1889}
1890
1891static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1892{
1893 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1894 struct ixgbe_hw *hw = &adapter->hw;
1895
1896 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1897 ixgbe_irq_disable(adapter);
1898
1899 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1900
1901 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1902 ixgbe_irq_enable(adapter);
1903
1904 /* remove VID from filter table */
1905 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1906}
1907
9a799d71 1908static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1909 struct vlan_group *grp)
9a799d71
AK		 1910{
1911 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1912 u32 ctrl;
e8e26350 1913 int i, j;
9a799d71 1914
d4f80882
AV		 1915 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1916 ixgbe_irq_disable(adapter);
9a799d71
AK		 1917 adapter->vlgrp = grp;
1918
2f90b865
AD		 1919 /*
1920 * For a DCB driver, always enable VLAN tag stripping so we can
1921 * still receive traffic from a DCB-enabled host even if we're
1922 * not in DCB mode.
1923 */
1924 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 1925 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1926 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1927 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1928 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1929 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1930 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 1931 /* enable VLAN tag insert/strip */
1932 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 1933 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1934 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 1935 for (i = 0; i < adapter->num_rx_queues; i++) {
1936 j = adapter->rx_ring[i].reg_idx;
1937 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
1938 ctrl |= IXGBE_RXDCTL_VME;
1939 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
1940 }
9a799d71 1941 }
e8e26350 1942 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 1943
d4f80882
AV		 1944 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1945 ixgbe_irq_enable(adapter);
9a799d71
AK		 1946}
1947
9a799d71
AK		 1948static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1949{
1950 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1951
1952 if (adapter->vlgrp) {
1953 u16 vid;
1954 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1955 if (!vlan_group_get_device(adapter->vlgrp, vid))
1956 continue;
1957 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1958 }
1959 }
1960}
1961
2c5645cf
CL		 1962static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1963{
1964 struct dev_mc_list *mc_ptr;
1965 u8 *addr = *mc_addr_ptr;
1966 *vmdq = 0;
1967
1968 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1969 if (mc_ptr->next)
1970 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1971 else
1972 *mc_addr_ptr = NULL;
1973
1974 return addr;
1975}
1976
9a799d71 1977/**
2c5645cf 1978 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1979 * @netdev: network interface device structure
1980 *
2c5645cf
CL		 1981 * The set_rx_method entry point is called whenever the unicast/multicast
1982 * address list or the network interface flags are updated. This routine is
1983 * responsible for configuring the hardware for proper unicast, multicast and
1984 * promiscuous mode.
9a799d71 1985 **/
2c5645cf 1986static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1987{
1988 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1989 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1990 u32 fctrl, vlnctrl;
2c5645cf
CL		 1991 u8 *addr_list = NULL;
1992 int addr_count = 0;
9a799d71
AK		 1993
1994 /* Check for Promiscuous and All Multicast modes */
1995
1996 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1997 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1998
1999 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2000 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2001 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2002 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2003 } else {
746b9f02
PM		 2004 if (netdev->flags & IFF_ALLMULTI) {
2005 fctrl |= IXGBE_FCTRL_MPE;
2006 fctrl &= ~IXGBE_FCTRL_UPE;
2007 } else {
2008 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2009 }
3d01625a 2010 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2011 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2012 }
2013
2014 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2015 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2016
2c5645cf
CL		 2017 /* reprogram secondary unicast list */
2018 addr_count = netdev->uc_count;
2019 if (addr_count)
2020 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2021 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2022 ixgbe_addr_list_itr);
9a799d71 2023
2c5645cf
CL		 2024 /* reprogram multicast list */
2025 addr_count = netdev->mc_count;
2026 if (addr_count)
2027 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2028 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2029 ixgbe_addr_list_itr);
9a799d71
AK		 2030}
2031
021230d4
AV		 2032static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2033{
2034 int q_idx;
2035 struct ixgbe_q_vector *q_vector;
2036 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2037
2038 /* legacy and MSI only use one vector */
2039 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2040 q_vectors = 1;
2041
2042 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2043 struct napi_struct *napi;
021230d4
AV		 2044 q_vector = &adapter->q_vector[q_idx];
2045 if (!q_vector->rxr_count)
2046 continue;
f0848276
JB		 2047 napi = &q_vector->napi;
2048 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2049 (q_vector->rxr_count > 1))
2050 napi->poll = &ixgbe_clean_rxonly_many;
2051
2052 napi_enable(napi);
021230d4
AV		 2053 }
2054}
2055
2056static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2057{
2058 int q_idx;
2059 struct ixgbe_q_vector *q_vector;
2060 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2061
2062 /* legacy and MSI only use one vector */
2063 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2064 q_vectors = 1;
2065
2066 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2067 q_vector = &adapter->q_vector[q_idx];
2068 if (!q_vector->rxr_count)
2069 continue;
2070 napi_disable(&q_vector->napi);
2071 }
2072}
2073
7a6b6f51 2074#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2075/*
2076 * ixgbe_configure_dcb - Configure DCB hardware
2077 * @adapter: ixgbe adapter struct
2078 *
2079 * This is called by the driver on open to configure the DCB hardware.
2080 * This is also called by the gennetlink interface when reconfiguring
2081 * the DCB state.
2082 */
2083static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2084{
2085 struct ixgbe_hw *hw = &adapter->hw;
2086 u32 txdctl, vlnctrl;
2087 int i, j;
2088
2089 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2090 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2091 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2092
2093 /* reconfigure the hardware */
2094 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2095
2096 for (i = 0; i < adapter->num_tx_queues; i++) {
2097 j = adapter->tx_ring[i].reg_idx;
2098 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2099 /* PThresh workaround for Tx hang with DFP enabled. */
2100 txdctl |= 32;
2101 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2102 }
2103 /* Enable VLAN tag insert/strip */
2104 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2105 if (hw->mac.type == ixgbe_mac_82598EB) {
2106 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2107 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2108 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2109 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2110 vlnctrl |= IXGBE_VLNCTRL_VFE;
2111 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2112 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2113 for (i = 0; i < adapter->num_rx_queues; i++) {
2114 j = adapter->rx_ring[i].reg_idx;
2115 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2116 vlnctrl |= IXGBE_RXDCTL_VME;
2117 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2118 }
2119 }
2f90b865
AD		 2120 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2121}
2122
2123#endif
9a799d71
AK		 2124static void ixgbe_configure(struct ixgbe_adapter *adapter)
2125{
2126 struct net_device *netdev = adapter->netdev;
2127 int i;
2128
2c5645cf 2129 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2130
2131 ixgbe_restore_vlan(adapter);
7a6b6f51 2132#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2133 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2134 netif_set_gso_max_size(netdev, 32768);
2135 ixgbe_configure_dcb(adapter);
2136 } else {
2137 netif_set_gso_max_size(netdev, 65536);
2138 }
2139#else
2140 netif_set_gso_max_size(netdev, 65536);
2141#endif
9a799d71
AK		 2142
2143 ixgbe_configure_tx(adapter);
2144 ixgbe_configure_rx(adapter);
2145 for (i = 0; i < adapter->num_rx_queues; i++)
2146 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2147 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2148}
2149
e8e26350
PW		 2150static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2151{
2152 switch (hw->phy.type) {
2153 case ixgbe_phy_sfp_avago:
2154 case ixgbe_phy_sfp_ftl:
2155 case ixgbe_phy_sfp_intel:
2156 case ixgbe_phy_sfp_unknown:
2157 case ixgbe_phy_tw_tyco:
2158 case ixgbe_phy_tw_unknown:
2159 return true;
2160 default:
2161 return false;
2162 }
2163}
2164
0ecc061d 2165/**
e8e26350
PW		 2166 * ixgbe_sfp_link_config - set up SFP+ link
2167 * @adapter: pointer to private adapter struct
2168 **/
2169static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2170{
2171 struct ixgbe_hw *hw = &adapter->hw;
2172
2173 if (hw->phy.multispeed_fiber) {
2174 /*
2175 * In multispeed fiber setups, the device may not have
2176 * had a physical connection when the driver loaded.
2177 * If that's the case, the initial link configuration
2178 * couldn't get the MAC into 10G or 1G mode, so we'll
2179 * never have a link status change interrupt fire.
2180 * We need to try and force an autonegotiation
2181 * session, then bring up link.
2182 */
2183 hw->mac.ops.setup_sfp(hw);
2184 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2185 schedule_work(&adapter->multispeed_fiber_task);
2186 } else {
2187 /*
2188 * Direct Attach Cu and non-multispeed fiber modules
2189 * still need to be configured properly prior to
2190 * attempting link.
2191 */
2192 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2193 schedule_work(&adapter->sfp_config_module_task);
2194 }
2195}
2196
2197/**
2198 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2199 * @hw: pointer to private hardware struct
2200 *
2201 * Returns 0 on success, negative on failure
2202 **/
e8e26350 2203static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2204{
2205 u32 autoneg;
2206 bool link_up = false;
2207 u32 ret = IXGBE_ERR_LINK_SETUP;
2208
2209 if (hw->mac.ops.check_link)
2210 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2211
2212 if (ret)
2213 goto link_cfg_out;
2214
2215 if (hw->mac.ops.get_link_capabilities)
2216 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2217 &hw->mac.autoneg);
2218 if (ret)
2219 goto link_cfg_out;
2220
2221 if (hw->mac.ops.setup_link_speed)
2222 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2223link_cfg_out:
2224 return ret;
2225}
2226
e8e26350
PW		 2227#define IXGBE_MAX_RX_DESC_POLL 10
2228static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2229 int rxr)
2230{
2231 int j = adapter->rx_ring[rxr].reg_idx;
2232 int k;
2233
2234 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2235 if (IXGBE_READ_REG(&adapter->hw,
2236 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2237 break;
2238 else
2239 msleep(1);
2240 }
2241 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2242 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2243 "not set within the polling period\n", rxr);
2244 }
2245 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2246 (adapter->rx_ring[rxr].count - 1));
2247}
2248
9a799d71
AK		 2249static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2250{
2251 struct net_device *netdev = adapter->netdev;
9a799d71 2252 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2253 int i, j = 0;
e8e26350 2254 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2255 int err;
9a799d71 2256 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2257 u32 txdctl, rxdctl, mhadd;
e8e26350 2258 u32 dmatxctl;
021230d4 2259 u32 gpie;
9a799d71 2260
5eba3699
AV		 2261 ixgbe_get_hw_control(adapter);
2262
021230d4
AV		 2263 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2264 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2265 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2266 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2267 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2268 } else {
2269 /* MSI only */
021230d4 2270 gpie = 0;
9a799d71 2271 }
021230d4
AV		 2272 /* XXX: to interrupt immediately for EICS writes, enable this */
2273 /* gpie |= IXGBE_GPIE_EIMEN; */
2274 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2275 }
2276
021230d4
AV		 2277 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2278 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2279 * specifically only auto mask tx and rx interrupts */
2280 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2281 }
9a799d71 2282
0befdb3e
JB		 2283 /* Enable fan failure interrupt if media type is copper */
2284 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2285 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2286 gpie |= IXGBE_SDP1_GPIEN;
2287 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2288 }
2289
e8e26350
PW		 2290 if (hw->mac.type == ixgbe_mac_82599EB) {
2291 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2292 gpie |= IXGBE_SDP1_GPIEN;
2293 gpie |= IXGBE_SDP2_GPIEN;
2294 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2295 }
2296
021230d4 2297 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2298 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2299 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2300 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2301
2302 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2303 }
2304
2305 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2306 j = adapter->tx_ring[i].reg_idx;
2307 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2308 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2309 txdctl |= (8 << 16);
e8e26350
PW		 2310 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2311 }
2312
2313 if (hw->mac.type == ixgbe_mac_82599EB) {
2314 /* DMATXCTL.EN must be set after all Tx queue config is done */
2315 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2316 dmatxctl |= IXGBE_DMATXCTL_TE;
2317 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2318 }
2319 for (i = 0; i < adapter->num_tx_queues; i++) {
2320 j = adapter->tx_ring[i].reg_idx;
2321 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2322 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2323 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2324 }
2325
e8e26350 2326 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2327 j = adapter->rx_ring[i].reg_idx;
2328 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2329 /* enable PTHRESH=32 descriptors (half the internal cache)
2330 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2331 * this also removes a pesky rx_no_buffer_count increment */
2332 rxdctl |= 0x0020;
9a799d71 2333 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2334 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2335 if (hw->mac.type == ixgbe_mac_82599EB)
2336 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2337 }
2338 /* enable all receives */
2339 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2340 if (hw->mac.type == ixgbe_mac_82598EB)
2341 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2342 else
2343 rxdctl |= IXGBE_RXCTRL_RXEN;
2344 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2345
2346 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2347 ixgbe_configure_msix(adapter);
2348 else
2349 ixgbe_configure_msi_and_legacy(adapter);
2350
2351 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2352 ixgbe_napi_enable_all(adapter);
2353
2354 /* clear any pending interrupts, may auto mask */
2355 IXGBE_READ_REG(hw, IXGBE_EICR);
2356
9a799d71
AK		 2357 ixgbe_irq_enable(adapter);
2358
e8e26350
PW		 2359 /*
2360 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2361 * arrived before interrupts were enabled. We need to kick off
2362 * the SFP+ module setup first, then try to bring up link.
2363 * If we're not hot-pluggable SFP+, we just need to configure link
2364 * and bring it up.
2365 */
2366 err = hw->phy.ops.identify(hw);
2367 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2368 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2369 ixgbe_down(adapter);
2370 return err;
2371 }
2372
2373 if (ixgbe_is_sfp(hw)) {
2374 ixgbe_sfp_link_config(adapter);
2375 } else {
2376 err = ixgbe_non_sfp_link_config(hw);
2377 if (err)
2378 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2379 }
0ecc061d 2380
1da100bb
PWJ		 2381 /* enable transmits */
2382 netif_tx_start_all_queues(netdev);
2383
9a799d71
AK		 2384 /* bring the link up in the watchdog, this could race with our first
2385 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2386 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2387 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2388 mod_timer(&adapter->watchdog_timer, jiffies);
2389 return 0;
2390}
2391
d4f80882
AV		 2392void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2393{
2394 WARN_ON(in_interrupt());
2395 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2396 msleep(1);
2397 ixgbe_down(adapter);
2398 ixgbe_up(adapter);
2399 clear_bit(__IXGBE_RESETTING, &adapter->state);
2400}
2401
9a799d71
AK		 2402int ixgbe_up(struct ixgbe_adapter *adapter)
2403{
2404 /* hardware has been reset, we need to reload some things */
2405 ixgbe_configure(adapter);
2406
4dd64df8
JB		 2407 ixgbe_napi_add_all(adapter);
2408
9a799d71
AK		 2409 return ixgbe_up_complete(adapter);
2410}
2411
2412void ixgbe_reset(struct ixgbe_adapter *adapter)
2413{
c44ade9e
JB		 2414 struct ixgbe_hw *hw = &adapter->hw;
2415 if (hw->mac.ops.init_hw(hw))
2416 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2417
2418 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2419 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2420
2421}
2422
9a799d71
AK		 2423/**
2424 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2425 * @adapter: board private structure
2426 * @rx_ring: ring to free buffers from
2427 **/
2428static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2429 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2430{
2431 struct pci_dev *pdev = adapter->pdev;
2432 unsigned long size;
2433 unsigned int i;
2434
2435 /* Free all the Rx ring sk_buffs */
2436
2437 for (i = 0; i < rx_ring->count; i++) {
2438 struct ixgbe_rx_buffer *rx_buffer_info;
2439
2440 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2441 if (rx_buffer_info->dma) {
2442 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2443 rx_ring->rx_buf_len,
2444 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2445 rx_buffer_info->dma = 0;
2446 }
2447 if (rx_buffer_info->skb) {
2448 dev_kfree_skb(rx_buffer_info->skb);
2449 rx_buffer_info->skb = NULL;
2450 }
2451 if (!rx_buffer_info->page)
2452 continue;
762f4c57
JB		 2453 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2454 PCI_DMA_FROMDEVICE);
9a799d71 2455 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2456 put_page(rx_buffer_info->page);
2457 rx_buffer_info->page = NULL;
762f4c57 2458 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2459 }
2460
2461 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2462 memset(rx_ring->rx_buffer_info, 0, size);
2463
2464 /* Zero out the descriptor ring */
2465 memset(rx_ring->desc, 0, rx_ring->size);
2466
2467 rx_ring->next_to_clean = 0;
2468 rx_ring->next_to_use = 0;
2469
9891ca7c
JB		 2470 if (rx_ring->head)
2471 writel(0, adapter->hw.hw_addr + rx_ring->head);
2472 if (rx_ring->tail)
2473 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2474}
2475
2476/**
2477 * ixgbe_clean_tx_ring - Free Tx Buffers
2478 * @adapter: board private structure
2479 * @tx_ring: ring to be cleaned
2480 **/
2481static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2482 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2483{
2484 struct ixgbe_tx_buffer *tx_buffer_info;
2485 unsigned long size;
2486 unsigned int i;
2487
2488 /* Free all the Tx ring sk_buffs */
2489
2490 for (i = 0; i < tx_ring->count; i++) {
2491 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2492 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2493 }
2494
2495 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2496 memset(tx_ring->tx_buffer_info, 0, size);
2497
2498 /* Zero out the descriptor ring */
2499 memset(tx_ring->desc, 0, tx_ring->size);
2500
2501 tx_ring->next_to_use = 0;
2502 tx_ring->next_to_clean = 0;
2503
9891ca7c
JB		 2504 if (tx_ring->head)
2505 writel(0, adapter->hw.hw_addr + tx_ring->head);
2506 if (tx_ring->tail)
2507 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2508}
2509
2510/**
021230d4 2511 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2512 * @adapter: board private structure
2513 **/
021230d4 2514static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2515{
2516 int i;
2517
021230d4
AV		 2518 for (i = 0; i < adapter->num_rx_queues; i++)
2519 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2520}
2521
2522/**
021230d4 2523 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2524 * @adapter: board private structure
2525 **/
021230d4 2526static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2527{
2528 int i;
2529
021230d4
AV		 2530 for (i = 0; i < adapter->num_tx_queues; i++)
2531 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2532}
2533
2534void ixgbe_down(struct ixgbe_adapter *adapter)
2535{
2536 struct net_device *netdev = adapter->netdev;
7f821875 2537 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2538 u32 rxctrl;
7f821875
JB		 2539 u32 txdctl;
2540 int i, j;
9a799d71
AK		 2541
2542 /* signal that we are down to the interrupt handler */
2543 set_bit(__IXGBE_DOWN, &adapter->state);
2544
2545 /* disable receives */
7f821875
JB		 2546 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2547 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2548
2549 netif_tx_disable(netdev);
2550
7f821875 2551 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2552 msleep(10);
2553
7f821875
JB		 2554 netif_tx_stop_all_queues(netdev);
2555
9a799d71
AK		 2556 ixgbe_irq_disable(adapter);
2557
021230d4 2558 ixgbe_napi_disable_all(adapter);
7f821875 2559
9a799d71 2560 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2561 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2562
7f821875
JB		 2563 /* disable transmits in the hardware now that interrupts are off */
2564 for (i = 0; i < adapter->num_tx_queues; i++) {
2565 j = adapter->tx_ring[i].reg_idx;
2566 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2567 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2568 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2569 }
88512539
PW		 2570 /* Disable the Tx DMA engine on 82599 */
2571 if (hw->mac.type == ixgbe_mac_82599EB)
2572 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2573 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2574 ~IXGBE_DMATXCTL_TE));
7f821875 2575
9a799d71 2576 netif_carrier_off(netdev);
9a799d71 2577
5dd2d332 2578#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2579 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2580 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2581 dca_remove_requester(&adapter->pdev->dev);
2582 }
2583
2584#endif
6f4a0e45
PL		 2585 if (!pci_channel_offline(adapter->pdev))
2586 ixgbe_reset(adapter);
9a799d71
AK		 2587 ixgbe_clean_all_tx_rings(adapter);
2588 ixgbe_clean_all_rx_rings(adapter);
2589
5dd2d332 2590#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2591 /* since we reset the hardware DCA settings were cleared */
2592 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2593 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2594 /* always use CB2 mode, difference is masked
2595 * in the CB driver */
b4617240 2596 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2597 ixgbe_setup_dca(adapter);
2598 }
2599#endif
9a799d71
AK		 2600}
2601
9a799d71 2602/**
021230d4
AV		 2603 * ixgbe_poll - NAPI Rx polling callback
2604 * @napi: structure for representing this polling device
2605 * @budget: how many packets driver is allowed to clean
2606 *
2607 * This function is used for legacy and MSI, NAPI mode
9a799d71 2608 **/
021230d4 2609static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2610{
9a1a69ad
JB		 2611 struct ixgbe_q_vector *q_vector =
2612 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2613 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2614 int tx_clean_complete, work_done = 0;
9a799d71 2615
5dd2d332 2616#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2617 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2618 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2619 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2620 }
2621#endif
2622
9a1a69ad 2623 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2624 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2625
9a1a69ad 2626 if (!tx_clean_complete)
d2c7ddd6
DM		 2627 work_done = budget;
2628
53e52c72
DM		 2629 /* If budget not fully consumed, exit the polling mode */
2630 if (work_done < budget) {
288379f0 2631 napi_complete(napi);
509ee935 2632 if (adapter->itr_setting & 1)
f494e8fa 2633 ixgbe_set_itr(adapter);
d4f80882 2634 if (!test_bit(__IXGBE_DOWN, &adapter->state))
22d5a71b 2635 ixgbe_irq_enable_queues(adapter);
9a799d71 2636 }
9a799d71
AK		 2637 return work_done;
2638}
2639
2640/**
2641 * ixgbe_tx_timeout - Respond to a Tx Hang
2642 * @netdev: network interface device structure
2643 **/
2644static void ixgbe_tx_timeout(struct net_device *netdev)
2645{
2646 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2647
2648 /* Do the reset outside of interrupt context */
2649 schedule_work(&adapter->reset_task);
2650}
2651
2652static void ixgbe_reset_task(struct work_struct *work)
2653{
2654 struct ixgbe_adapter *adapter;
2655 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2656
2f90b865
AD		 2657 /* If we're already down or resetting, just bail */
2658 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2659 test_bit(__IXGBE_RESETTING, &adapter->state))
2660 return;
2661
9a799d71
AK		 2662 adapter->tx_timeout_count++;
2663
d4f80882 2664 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2665}
2666
bc97114d
PWJ		 2667#ifdef CONFIG_IXGBE_DCB
2668static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2669{
bc97114d 2670 bool ret = false;
b9804972 2671
bc97114d
PWJ		 2672 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2673 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2674 adapter->num_rx_queues =
2675 adapter->ring_feature[RING_F_DCB].indices;
2676 adapter->num_tx_queues =
2677 adapter->ring_feature[RING_F_DCB].indices;
2678 ret = true;
2679 } else {
bc97114d
PWJ		 2680 ret = false;
2681 }
2f90b865 2682
bc97114d
PWJ		 2683 return ret;
2684}
2685#endif
2686
4df10466
JB		 2687/**
2688 * ixgbe_set_rss_queues: Allocate queues for RSS
2689 * @adapter: board private structure to initialize
2690 *
2691 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2692 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2693 *
2694 **/
bc97114d
PWJ		 2695static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2696{
2697 bool ret = false;
2698
2699 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2700 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2701 adapter->num_rx_queues =
2702 adapter->ring_feature[RING_F_RSS].indices;
2703 adapter->num_tx_queues =
2704 adapter->ring_feature[RING_F_RSS].indices;
2705 ret = true;
2706 } else {
bc97114d 2707 ret = false;
b9804972
JB		 2708 }
2709
bc97114d
PWJ		 2710 return ret;
2711}
2712
4df10466
JB		 2713/*
2714 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2715 * @adapter: board private structure to initialize
2716 *
2717 * This is the top level queue allocation routine. The order here is very
2718 * important, starting with the "most" number of features turned on at once,
2719 * and ending with the smallest set of features. This way large combinations
2720 * can be allocated if they're turned on, and smaller combinations are the
2721 * fallthrough conditions.
2722 *
2723 **/
bc97114d
PWJ		 2724static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2725{
bc97114d
PWJ		 2726#ifdef CONFIG_IXGBE_DCB
2727 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 2728 goto done;
bc97114d
PWJ		 2729
2730#endif
2731 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 2732 goto done;
2733
2734 /* fallback to base case */
2735 adapter->num_rx_queues = 1;
2736 adapter->num_tx_queues = 1;
2737
2738done:
2739 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2740 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 2741}
2742
021230d4 2743static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2744 int vectors)
021230d4
AV		 2745{
2746 int err, vector_threshold;
2747
2748 /* We'll want at least 3 (vector_threshold):
2749 * 1) TxQ[0] Cleanup
2750 * 2) RxQ[0] Cleanup
2751 * 3) Other (Link Status Change, etc.)
2752 * 4) TCP Timer (optional)
2753 */
2754 vector_threshold = MIN_MSIX_COUNT;
2755
2756 /* The more we get, the more we will assign to Tx/Rx Cleanup
2757 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2758 * Right now, we simply care about how many we'll get; we'll
2759 * set them up later while requesting irq's.
2760 */
2761 while (vectors >= vector_threshold) {
2762 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2763 vectors);
021230d4
AV		 2764 if (!err) /* Success in acquiring all requested vectors. */
2765 break;
2766 else if (err < 0)
2767 vectors = 0; /* Nasty failure, quit now */
2768 else /* err == number of vectors we should try again with */
2769 vectors = err;
2770 }
2771
2772 if (vectors < vector_threshold) {
2773 /* Can't allocate enough MSI-X interrupts? Oh well.
2774 * This just means we'll go with either a single MSI
2775 * vector or fall back to legacy interrupts.
2776 */
2777 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2778 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2779 kfree(adapter->msix_entries);
2780 adapter->msix_entries = NULL;
2f90b865 2781 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4 2782 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2783 ixgbe_set_num_queues(adapter);
021230d4
AV		 2784 } else {
2785 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 2786 /*
2787 * Adjust for only the vectors we'll use, which is minimum
2788 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2789 * vectors we were allocated.
2790 */
2791 adapter->num_msix_vectors = min(vectors,
2792 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 2793 }
2794}
2795
021230d4 2796/**
bc97114d 2797 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 2798 * @adapter: board private structure to initialize
2799 *
bc97114d
PWJ		 2800 * Cache the descriptor ring offsets for RSS to the assigned rings.
2801 *
021230d4 2802 **/
bc97114d 2803static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 2804{
bc97114d
PWJ		 2805 int i;
2806 bool ret = false;
2807
2808 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2809 for (i = 0; i < adapter->num_rx_queues; i++)
2810 adapter->rx_ring[i].reg_idx = i;
2811 for (i = 0; i < adapter->num_tx_queues; i++)
2812 adapter->tx_ring[i].reg_idx = i;
2813 ret = true;
2814 } else {
2815 ret = false;
2816 }
2817
2818 return ret;
2819}
2820
2821#ifdef CONFIG_IXGBE_DCB
2822/**
2823 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2824 * @adapter: board private structure to initialize
2825 *
2826 * Cache the descriptor ring offsets for DCB to the assigned rings.
2827 *
2828 **/
2829static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2830{
2831 int i;
2832 bool ret = false;
2833 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2834
2835 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2836 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 2837 /* the number of queues is assumed to be symmetric */
2838 for (i = 0; i < dcb_i; i++) {
2839 adapter->rx_ring[i].reg_idx = i << 3;
2840 adapter->tx_ring[i].reg_idx = i << 2;
2841 }
bc97114d 2842 ret = true;
e8e26350 2843 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 2844 if (dcb_i == 8) {
2845 /*
2846 * Tx TC0 starts at: descriptor queue 0
2847 * Tx TC1 starts at: descriptor queue 32
2848 * Tx TC2 starts at: descriptor queue 64
2849 * Tx TC3 starts at: descriptor queue 80
2850 * Tx TC4 starts at: descriptor queue 96
2851 * Tx TC5 starts at: descriptor queue 104
2852 * Tx TC6 starts at: descriptor queue 112
2853 * Tx TC7 starts at: descriptor queue 120
2854 *
2855 * Rx TC0-TC7 are offset by 16 queues each
2856 */
2857 for (i = 0; i < 3; i++) {
2858 adapter->tx_ring[i].reg_idx = i << 5;
2859 adapter->rx_ring[i].reg_idx = i << 4;
2860 }
2861 for ( ; i < 5; i++) {
2862 adapter->tx_ring[i].reg_idx =
2863 ((i + 2) << 4);
2864 adapter->rx_ring[i].reg_idx = i << 4;
2865 }
2866 for ( ; i < dcb_i; i++) {
2867 adapter->tx_ring[i].reg_idx =
2868 ((i + 8) << 3);
2869 adapter->rx_ring[i].reg_idx = i << 4;
2870 }
2871
2872 ret = true;
2873 } else if (dcb_i == 4) {
2874 /*
2875 * Tx TC0 starts at: descriptor queue 0
2876 * Tx TC1 starts at: descriptor queue 64
2877 * Tx TC2 starts at: descriptor queue 96
2878 * Tx TC3 starts at: descriptor queue 112
2879 *
2880 * Rx TC0-TC3 are offset by 32 queues each
2881 */
2882 adapter->tx_ring[0].reg_idx = 0;
2883 adapter->tx_ring[1].reg_idx = 64;
2884 adapter->tx_ring[2].reg_idx = 96;
2885 adapter->tx_ring[3].reg_idx = 112;
2886 for (i = 0 ; i < dcb_i; i++)
2887 adapter->rx_ring[i].reg_idx = i << 5;
2888
2889 ret = true;
2890 } else {
2891 ret = false;
e8e26350 2892 }
bc97114d
PWJ		 2893 } else {
2894 ret = false;
021230d4 2895 }
bc97114d
PWJ		 2896 } else {
2897 ret = false;
021230d4 2898 }
bc97114d
PWJ		 2899
2900 return ret;
2901}
2902#endif
2903
2904/**
2905 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2906 * @adapter: board private structure to initialize
2907 *
2908 * Once we know the feature-set enabled for the device, we'll cache
2909 * the register offset the descriptor ring is assigned to.
2910 *
2911 * Note, the order the various feature calls is important. It must start with
2912 * the "most" features enabled at the same time, then trickle down to the
2913 * least amount of features turned on at once.
2914 **/
2915static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2916{
2917 /* start with default case */
2918 adapter->rx_ring[0].reg_idx = 0;
2919 adapter->tx_ring[0].reg_idx = 0;
2920
2921#ifdef CONFIG_IXGBE_DCB
2922 if (ixgbe_cache_ring_dcb(adapter))
2923 return;
2924
2925#endif
2926 if (ixgbe_cache_ring_rss(adapter))
2927 return;
021230d4
AV		 2928}
2929
9a799d71
AK		 2930/**
2931 * ixgbe_alloc_queues - Allocate memory for all rings
2932 * @adapter: board private structure to initialize
2933 *
2934 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 2935 * number of queues at compile-time. The polling_netdev array is
2936 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 2937 **/
2f90b865 2938static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 2939{
2940 int i;
2941
2942 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 2943 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 2944 if (!adapter->tx_ring)
021230d4 2945 goto err_tx_ring_allocation;
9a799d71
AK		 2946
2947 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 2948 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2949 if (!adapter->rx_ring)
2950 goto err_rx_ring_allocation;
9a799d71 2951
021230d4 2952 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 2953 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 2954 adapter->tx_ring[i].queue_index = i;
2955 }
b9804972 2956
9a799d71 2957 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 2958 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 2959 adapter->rx_ring[i].queue_index = i;
2960 }
2961
2962 ixgbe_cache_ring_register(adapter);
2963
2964 return 0;
2965
2966err_rx_ring_allocation:
2967 kfree(adapter->tx_ring);
2968err_tx_ring_allocation:
2969 return -ENOMEM;
2970}
2971
2972/**
2973 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2974 * @adapter: board private structure to initialize
2975 *
2976 * Attempt to configure the interrupts using the best available
2977 * capabilities of the hardware and the kernel.
2978 **/
feea6a57 2979static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 2980{
8be0e467 2981 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 2982 int err = 0;
2983 int vector, v_budget;
2984
2985 /*
2986 * It's easy to be greedy for MSI-X vectors, but it really
2987 * doesn't do us much good if we have a lot more vectors
2988 * than CPU's. So let's be conservative and only ask for
2989 * (roughly) twice the number of vectors as there are CPU's.
2990 */
2991 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 2992 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 2993
2994 /*
2995 * At the same time, hardware can only support a maximum of
8be0e467
PW		 2996 * hw.mac->max_msix_vectors vectors. With features
2997 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
2998 * descriptor queues supported by our device. Thus, we cap it off in
2999 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3000 */
8be0e467 3001 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3002
3003 /* A failure in MSI-X entry allocation isn't fatal, but it does
3004 * mean we disable MSI-X capabilities of the adapter. */
3005 adapter->msix_entries = kcalloc(v_budget,
b4617240 3006 sizeof(struct msix_entry), GFP_KERNEL);
021230d4 3007 if (!adapter->msix_entries) {
2f90b865 3008 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 3009 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3010 ixgbe_set_num_queues(adapter);
3011 kfree(adapter->tx_ring);
3012 kfree(adapter->rx_ring);
3013 err = ixgbe_alloc_queues(adapter);
3014 if (err) {
3015 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 3016 "for queues\n");
021230d4
AV		 3017 goto out;
3018 }
3019
3020 goto try_msi;
3021 }
3022
3023 for (vector = 0; vector < v_budget; vector++)
3024 adapter->msix_entries[vector].entry = vector;
3025
3026 ixgbe_acquire_msix_vectors(adapter, v_budget);
3027
3028 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3029 goto out;
3030
3031try_msi:
3032 err = pci_enable_msi(adapter->pdev);
3033 if (!err) {
3034 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3035 } else {
3036 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3037 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3038 /* reset err */
3039 err = 0;
3040 }
3041
3042out:
021230d4
AV		 3043 return err;
3044}
3045
2f90b865 3046void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3047{
3048 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3049 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3050 pci_disable_msix(adapter->pdev);
3051 kfree(adapter->msix_entries);
3052 adapter->msix_entries = NULL;
3053 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3054 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3055 pci_disable_msi(adapter->pdev);
3056 }
3057 return;
3058}
3059
3060/**
3061 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3062 * @adapter: board private structure to initialize
3063 *
3064 * We determine which interrupt scheme to use based on...
3065 * - Kernel support (MSI, MSI-X)
3066 * - which can be user-defined (via MODULE_PARAM)
3067 * - Hardware queue count (num_*_queues)
3068 * - defined by miscellaneous hardware support/features (RSS, etc.)
3069 **/
2f90b865 3070int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3071{
3072 int err;
3073
3074 /* Number of supported queues */
3075 ixgbe_set_num_queues(adapter);
3076
3077 err = ixgbe_alloc_queues(adapter);
3078 if (err) {
3079 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3080 goto err_alloc_queues;
3081 }
3082
3083 err = ixgbe_set_interrupt_capability(adapter);
3084 if (err) {
3085 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3086 goto err_set_interrupt;
9a799d71
AK		 3087 }
3088
021230d4 3089 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3090 "Tx Queue count = %u\n",
3091 (adapter->num_rx_queues > 1) ? "Enabled" :
3092 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3093
3094 set_bit(__IXGBE_DOWN, &adapter->state);
3095
9a799d71 3096 return 0;
021230d4
AV		 3097
3098err_set_interrupt:
3099 kfree(adapter->tx_ring);
3100 kfree(adapter->rx_ring);
3101err_alloc_queues:
3102 return err;
9a799d71
AK		 3103}
3104
c4900be0
DS		 3105/**
3106 * ixgbe_sfp_timer - worker thread to find a missing module
3107 * @data: pointer to our adapter struct
3108 **/
3109static void ixgbe_sfp_timer(unsigned long data)
3110{
3111 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3112
4df10466
JB		 3113 /*
3114 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3115 * delays that sfp+ detection requires
3116 */
3117 schedule_work(&adapter->sfp_task);
3118}
3119
3120/**
3121 * ixgbe_sfp_task - worker thread to find a missing module
3122 * @work: pointer to work_struct containing our data
3123 **/
3124static void ixgbe_sfp_task(struct work_struct *work)
3125{
3126 struct ixgbe_adapter *adapter = container_of(work,
3127 struct ixgbe_adapter,
3128 sfp_task);
3129 struct ixgbe_hw *hw = &adapter->hw;
3130
3131 if ((hw->phy.type == ixgbe_phy_nl) &&
3132 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3133 s32 ret = hw->phy.ops.identify_sfp(hw);
3134 if (ret)
3135 goto reschedule;
3136 ret = hw->phy.ops.reset(hw);
3137 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3138 DPRINTK(PROBE, ERR, "failed to initialize because an "
3139 "unsupported SFP+ module type was detected.\n"
3140 "Reload the driver after installing a "
3141 "supported module.\n");
3142 unregister_netdev(adapter->netdev);
3143 } else {
3144 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3145 hw->phy.sfp_type);
3146 }
3147 /* don't need this routine any more */
3148 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3149 }
3150 return;
3151reschedule:
3152 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3153 mod_timer(&adapter->sfp_timer,
3154 round_jiffies(jiffies + (2 * HZ)));
3155}
3156
9a799d71
AK		 3157/**
3158 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3159 * @adapter: board private structure to initialize
3160 *
3161 * ixgbe_sw_init initializes the Adapter private data structure.
3162 * Fields are initialized based on PCI device information and
3163 * OS network device settings (MTU size).
3164 **/
3165static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3166{
3167 struct ixgbe_hw *hw = &adapter->hw;
3168 struct pci_dev *pdev = adapter->pdev;
021230d4 3169 unsigned int rss;
7a6b6f51 3170#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3171 int j;
3172 struct tc_configuration *tc;
3173#endif
021230d4 3174
c44ade9e
JB		 3175 /* PCI config space info */
3176
3177 hw->vendor_id = pdev->vendor;
3178 hw->device_id = pdev->device;
3179 hw->revision_id = pdev->revision;
3180 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3181 hw->subsystem_device_id = pdev->subsystem_device;
3182
021230d4
AV		 3183 /* Set capability flags */
3184 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3185 adapter->ring_feature[RING_F_RSS].indices = rss;
3186 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3187 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
e8e26350
PW		 3188 if (hw->mac.type == ixgbe_mac_82598EB)
3189 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3190 else if (hw->mac.type == ixgbe_mac_82599EB)
3191 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
2f90b865 3192
7a6b6f51 3193#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3194 /* Configure DCB traffic classes */
3195 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3196 tc = &adapter->dcb_cfg.tc_config[j];
3197 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3198 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3199 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3200 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3201 tc->dcb_pfc = pfc_disabled;
3202 }
3203 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3204 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3205 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3206 adapter->dcb_cfg.round_robin_enable = false;
3207 adapter->dcb_set_bitmap = 0x00;
3208 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3209 adapter->ring_feature[RING_F_DCB].indices);
3210
3211#endif
9a799d71
AK		 3212
3213 /* default flow control settings */
cd7664f6 3214 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3215 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
2b9ade93
JB		 3216 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3217 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3218 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3219 hw->fc.send_xon = true;
71fd570b 3220 hw->fc.disable_fc_autoneg = false;
9a799d71 3221
30efa5a3
JB		 3222 /* enable itr by default in dynamic mode */
3223 adapter->itr_setting = 1;
3224 adapter->eitr_param = 20000;
3225
3226 /* set defaults for eitr in MegaBytes */
3227 adapter->eitr_low = 10;
3228 adapter->eitr_high = 20;
3229
3230 /* set default ring sizes */
3231 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3232 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3233
9a799d71 3234 /* initialize eeprom parameters */
c44ade9e 3235 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3236 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3237 return -EIO;
3238 }
3239
021230d4 3240 /* enable rx csum by default */
9a799d71
AK		 3241 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3242
9a799d71
AK		 3243 set_bit(__IXGBE_DOWN, &adapter->state);
3244
3245 return 0;
3246}
3247
3248/**
3249 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3250 * @adapter: board private structure
3a581073 3251 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3252 *
3253 * Return 0 on success, negative on failure
3254 **/
3255int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3256 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3257{
3258 struct pci_dev *pdev = adapter->pdev;
3259 int size;
3260
3a581073
JB		 3261 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3262 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3263 if (!tx_ring->tx_buffer_info)
3264 goto err;
3a581073 3265 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3266
3267 /* round up to nearest 4K */
12207e49 3268 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3269 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3270
3a581073
JB		 3271 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3272 &tx_ring->dma);
e01c31a5
JB		 3273 if (!tx_ring->desc)
3274 goto err;
9a799d71 3275
3a581073
JB		 3276 tx_ring->next_to_use = 0;
3277 tx_ring->next_to_clean = 0;
3278 tx_ring->work_limit = tx_ring->count;
9a799d71 3279 return 0;
e01c31a5
JB		 3280
3281err:
3282 vfree(tx_ring->tx_buffer_info);
3283 tx_ring->tx_buffer_info = NULL;
3284 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3285 "descriptor ring\n");
3286 return -ENOMEM;
9a799d71
AK		 3287}
3288
69888674
AD		 3289/**
3290 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3291 * @adapter: board private structure
3292 *
3293 * If this function returns with an error, then it's possible one or
3294 * more of the rings is populated (while the rest are not). It is the
3295 * callers duty to clean those orphaned rings.
3296 *
3297 * Return 0 on success, negative on failure
3298 **/
3299static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3300{
3301 int i, err = 0;
3302
3303 for (i = 0; i < adapter->num_tx_queues; i++) {
3304 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3305 if (!err)
3306 continue;
3307 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3308 break;
3309 }
3310
3311 return err;
3312}
3313
9a799d71
AK		 3314/**
3315 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3316 * @adapter: board private structure
3a581073 3317 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3318 *
3319 * Returns 0 on success, negative on failure
3320 **/
3321int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3322 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3323{
3324 struct pci_dev *pdev = adapter->pdev;
021230d4 3325 int size;
9a799d71 3326
3a581073
JB		 3327 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3328 rx_ring->rx_buffer_info = vmalloc(size);
3329 if (!rx_ring->rx_buffer_info) {
9a799d71 3330 DPRINTK(PROBE, ERR,
b4617240 3331 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3332 goto alloc_failed;
9a799d71 3333 }
3a581073 3334 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3335
9a799d71 3336 /* Round up to nearest 4K */
3a581073
JB		 3337 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3338 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3339
3a581073 3340 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3341
3a581073 3342 if (!rx_ring->desc) {
9a799d71 3343 DPRINTK(PROBE, ERR,
b4617240 3344 "Memory allocation failed for the rx desc ring\n");
3a581073 3345 vfree(rx_ring->rx_buffer_info);
177db6ff 3346 goto alloc_failed;
9a799d71
AK		 3347 }
3348
3a581073
JB		 3349 rx_ring->next_to_clean = 0;
3350 rx_ring->next_to_use = 0;
9a799d71
AK		 3351
3352 return 0;
177db6ff
MC		 3353
3354alloc_failed:
177db6ff 3355 return -ENOMEM;
9a799d71
AK		 3356}
3357
69888674
AD		 3358/**
3359 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3360 * @adapter: board private structure
3361 *
3362 * If this function returns with an error, then it's possible one or
3363 * more of the rings is populated (while the rest are not). It is the
3364 * callers duty to clean those orphaned rings.
3365 *
3366 * Return 0 on success, negative on failure
3367 **/
3368
3369static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3370{
3371 int i, err = 0;
3372
3373 for (i = 0; i < adapter->num_rx_queues; i++) {
3374 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3375 if (!err)
3376 continue;
3377 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3378 break;
3379 }
3380
3381 return err;
3382}
3383
9a799d71
AK		 3384/**
3385 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3386 * @adapter: board private structure
3387 * @tx_ring: Tx descriptor ring for a specific queue
3388 *
3389 * Free all transmit software resources
3390 **/
c431f97e
JB		 3391void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3392 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3393{
3394 struct pci_dev *pdev = adapter->pdev;
3395
3396 ixgbe_clean_tx_ring(adapter, tx_ring);
3397
3398 vfree(tx_ring->tx_buffer_info);
3399 tx_ring->tx_buffer_info = NULL;
3400
3401 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3402
3403 tx_ring->desc = NULL;
3404}
3405
3406/**
3407 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3408 * @adapter: board private structure
3409 *
3410 * Free all transmit software resources
3411 **/
3412static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3413{
3414 int i;
3415
3416 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 3417 if (adapter->tx_ring[i].desc)
3418 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3419}
3420
3421/**
b4617240 3422 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3423 * @adapter: board private structure
3424 * @rx_ring: ring to clean the resources from
3425 *
3426 * Free all receive software resources
3427 **/
c431f97e
JB		 3428void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3429 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3430{
3431 struct pci_dev *pdev = adapter->pdev;
3432
3433 ixgbe_clean_rx_ring(adapter, rx_ring);
3434
3435 vfree(rx_ring->rx_buffer_info);
3436 rx_ring->rx_buffer_info = NULL;
3437
3438 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3439
3440 rx_ring->desc = NULL;
3441}
3442
3443/**
3444 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3445 * @adapter: board private structure
3446 *
3447 * Free all receive software resources
3448 **/
3449static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3450{
3451 int i;
3452
3453 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 3454 if (adapter->rx_ring[i].desc)
3455 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3456}
3457
9a799d71
AK		 3458/**
3459 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3460 * @netdev: network interface device structure
3461 * @new_mtu: new value for maximum frame size
3462 *
3463 * Returns 0 on success, negative on failure
3464 **/
3465static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3466{
3467 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3468 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3469
42c783c5
JB		 3470 /* MTU < 68 is an error and causes problems on some kernels */
3471 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3472 return -EINVAL;
3473
021230d4 3474 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3475 netdev->mtu, new_mtu);
021230d4 3476 /* must set new MTU before calling down or up */
9a799d71
AK		 3477 netdev->mtu = new_mtu;
3478
d4f80882
AV		 3479 if (netif_running(netdev))
3480 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3481
3482 return 0;
3483}
3484
3485/**
3486 * ixgbe_open - Called when a network interface is made active
3487 * @netdev: network interface device structure
3488 *
3489 * Returns 0 on success, negative value on failure
3490 *
3491 * The open entry point is called when a network interface is made
3492 * active by the system (IFF_UP). At this point all resources needed
3493 * for transmit and receive operations are allocated, the interrupt
3494 * handler is registered with the OS, the watchdog timer is started,
3495 * and the stack is notified that the interface is ready.
3496 **/
3497static int ixgbe_open(struct net_device *netdev)
3498{
3499 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3500 int err;
4bebfaa5
AK		 3501
3502 /* disallow open during test */
3503 if (test_bit(__IXGBE_TESTING, &adapter->state))
3504 return -EBUSY;
9a799d71 3505
54386467
JB		 3506 netif_carrier_off(netdev);
3507
9a799d71
AK		 3508 /* allocate transmit descriptors */
3509 err = ixgbe_setup_all_tx_resources(adapter);
3510 if (err)
3511 goto err_setup_tx;
3512
9a799d71
AK		 3513 /* allocate receive descriptors */
3514 err = ixgbe_setup_all_rx_resources(adapter);
3515 if (err)
3516 goto err_setup_rx;
3517
3518 ixgbe_configure(adapter);
3519
4dd64df8
JB		 3520 ixgbe_napi_add_all(adapter);
3521
021230d4 3522 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3523 if (err)
3524 goto err_req_irq;
3525
9a799d71
AK		 3526 err = ixgbe_up_complete(adapter);
3527 if (err)
3528 goto err_up;
3529
d55b53ff
JK		 3530 netif_tx_start_all_queues(netdev);
3531
9a799d71
AK		 3532 return 0;
3533
3534err_up:
5eba3699 3535 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3536 ixgbe_free_irq(adapter);
3537err_req_irq:
9a799d71 3538err_setup_rx:
a20a1199 3539 ixgbe_free_all_rx_resources(adapter);
9a799d71 3540err_setup_tx:
a20a1199 3541 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 3542 ixgbe_reset(adapter);
3543
3544 return err;
3545}
3546
3547/**
3548 * ixgbe_close - Disables a network interface
3549 * @netdev: network interface device structure
3550 *
3551 * Returns 0, this is not allowed to fail
3552 *
3553 * The close entry point is called when an interface is de-activated
3554 * by the OS. The hardware is still under the drivers control, but
3555 * needs to be disabled. A global MAC reset is issued to stop the
3556 * hardware, and all transmit and receive resources are freed.
3557 **/
3558static int ixgbe_close(struct net_device *netdev)
3559{
3560 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3561
3562 ixgbe_down(adapter);
3563 ixgbe_free_irq(adapter);
3564
3565 ixgbe_free_all_tx_resources(adapter);
3566 ixgbe_free_all_rx_resources(adapter);
3567
5eba3699 3568 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3569
3570 return 0;
3571}
3572
b3c8b4ba
AD		 3573/**
3574 * ixgbe_napi_add_all - prep napi structs for use
3575 * @adapter: private struct
4dd64df8 3576 *
b3c8b4ba
AD		 3577 * helper function to napi_add each possible q_vector->napi
3578 */
2f90b865 3579void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3580{
3581 int q_idx, q_vectors;
7adf1525 3582 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 3583 int (*poll)(struct napi_struct *, int);
3584
7adf1525
PWJ		 3585 /* check if we already have our netdev->napi_list populated */
3586 if (&netdev->napi_list != netdev->napi_list.next)
3587 return;
3588
b3c8b4ba
AD		 3589 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3590 poll = &ixgbe_clean_rxonly;
3591 /* Only enable as many vectors as we have rx queues. */
3592 q_vectors = adapter->num_rx_queues;
3593 } else {
3594 poll = &ixgbe_poll;
3595 /* only one q_vector for legacy modes */
3596 q_vectors = 1;
3597 }
3598
3599 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3600 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3601 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3602 }
3603}
3604
2f90b865 3605void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3606{
3607 int q_idx;
3608 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3609
3610 /* legacy and MSI only use one vector */
3611 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3612 q_vectors = 1;
3613
3614 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3615 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3616 if (!q_vector->rxr_count)
3617 continue;
3618 netif_napi_del(&q_vector->napi);
3619 }
3620}
3621
3622#ifdef CONFIG_PM
3623static int ixgbe_resume(struct pci_dev *pdev)
3624{
3625 struct net_device *netdev = pci_get_drvdata(pdev);
3626 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3627 u32 err;
3628
3629 pci_set_power_state(pdev, PCI_D0);
3630 pci_restore_state(pdev);
3631 err = pci_enable_device(pdev);
3632 if (err) {
69888674 3633 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3634 "suspend\n");
3635 return err;
3636 }
3637 pci_set_master(pdev);
3638
3639 pci_enable_wake(pdev, PCI_D3hot, 0);
3640 pci_enable_wake(pdev, PCI_D3cold, 0);
3641
3642 err = ixgbe_init_interrupt_scheme(adapter);
3643 if (err) {
3644 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3645 "device\n");
3646 return err;
3647 }
3648
b3c8b4ba
AD		 3649 ixgbe_reset(adapter);
3650
3651 if (netif_running(netdev)) {
3652 err = ixgbe_open(adapter->netdev);
3653 if (err)
3654 return err;
3655 }
3656
3657 netif_device_attach(netdev);
3658
3659 return 0;
3660}
b3c8b4ba 3661#endif /* CONFIG_PM */
9d8d05ae
RW		 3662
3663static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 3664{
3665 struct net_device *netdev = pci_get_drvdata(pdev);
3666 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3667 struct ixgbe_hw *hw = &adapter->hw;
3668 u32 ctrl, fctrl;
3669 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3670#ifdef CONFIG_PM
3671 int retval = 0;
3672#endif
3673
3674 netif_device_detach(netdev);
3675
3676 if (netif_running(netdev)) {
3677 ixgbe_down(adapter);
3678 ixgbe_free_irq(adapter);
3679 ixgbe_free_all_tx_resources(adapter);
3680 ixgbe_free_all_rx_resources(adapter);
3681 }
3682 ixgbe_reset_interrupt_capability(adapter);
3683 ixgbe_napi_del_all(adapter);
7adf1525 3684 INIT_LIST_HEAD(&netdev->napi_list);
b3c8b4ba
AD		 3685 kfree(adapter->tx_ring);
3686 kfree(adapter->rx_ring);
3687
3688#ifdef CONFIG_PM
3689 retval = pci_save_state(pdev);
3690 if (retval)
3691 return retval;
4df10466 3692
b3c8b4ba 3693#endif
e8e26350
PW		 3694 if (wufc) {
3695 ixgbe_set_rx_mode(netdev);
b3c8b4ba 3696
e8e26350
PW		 3697 /* turn on all-multi mode if wake on multicast is enabled */
3698 if (wufc & IXGBE_WUFC_MC) {
3699 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3700 fctrl |= IXGBE_FCTRL_MPE;
3701 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3702 }
3703
3704 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3705 ctrl |= IXGBE_CTRL_GIO_DIS;
3706 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3707
3708 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3709 } else {
3710 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3711 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3712 }
3713
3714 if (wufc && hw->mac.type == ixgbe_mac_82599EB) {
3715 pci_enable_wake(pdev, PCI_D3hot, 1);
3716 pci_enable_wake(pdev, PCI_D3cold, 1);
3717 } else {
3718 pci_enable_wake(pdev, PCI_D3hot, 0);
3719 pci_enable_wake(pdev, PCI_D3cold, 0);
3720 }
b3c8b4ba 3721
9d8d05ae
RW		 3722 *enable_wake = !!wufc;
3723
b3c8b4ba
AD		 3724 ixgbe_release_hw_control(adapter);
3725
3726 pci_disable_device(pdev);
3727
9d8d05ae
RW		 3728 return 0;
3729}
3730
3731#ifdef CONFIG_PM
3732static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3733{
3734 int retval;
3735 bool wake;
3736
3737 retval = __ixgbe_shutdown(pdev, &wake);
3738 if (retval)
3739 return retval;
3740
3741 if (wake) {
3742 pci_prepare_to_sleep(pdev);
3743 } else {
3744 pci_wake_from_d3(pdev, false);
3745 pci_set_power_state(pdev, PCI_D3hot);
3746 }
b3c8b4ba
AD		 3747
3748 return 0;
3749}
9d8d05ae 3750#endif /* CONFIG_PM */
b3c8b4ba
AD		 3751
3752static void ixgbe_shutdown(struct pci_dev *pdev)
3753{
9d8d05ae
RW		 3754 bool wake;
3755
3756 __ixgbe_shutdown(pdev, &wake);
3757
3758 if (system_state == SYSTEM_POWER_OFF) {
3759 pci_wake_from_d3(pdev, wake);
3760 pci_set_power_state(pdev, PCI_D3hot);
3761 }
b3c8b4ba
AD		 3762}
3763
9a799d71
AK		 3764/**
3765 * ixgbe_update_stats - Update the board statistics counters.
3766 * @adapter: board private structure
3767 **/
3768void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3769{
3770 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3771 u64 total_mpc = 0;
3772 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 3773
d51019a4
PW		 3774 if (hw->mac.type == ixgbe_mac_82599EB) {
3775 for (i = 0; i < 16; i++)
3776 adapter->hw_rx_no_dma_resources +=
3777 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3778 }
3779
9a799d71 3780 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3781 for (i = 0; i < 8; i++) {
3782 /* for packet buffers not used, the register should read 0 */
3783 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3784 missed_rx += mpc;
3785 adapter->stats.mpc[i] += mpc;
3786 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 3787 if (hw->mac.type == ixgbe_mac_82598EB)
3788 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3789 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3790 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3791 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3792 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 3793 if (hw->mac.type == ixgbe_mac_82599EB) {
3794 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3795 IXGBE_PXONRXCNT(i));
3796 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3797 IXGBE_PXOFFRXCNT(i));
3798 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 3799 } else {
3800 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3801 IXGBE_PXONRXC(i));
3802 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3803 IXGBE_PXOFFRXC(i));
3804 }
2f90b865
AD		 3805 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3806 IXGBE_PXONTXC(i));
2f90b865 3807 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 3808 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3809 }
3810 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3811 /* work around hardware counting issue */
3812 adapter->stats.gprc -= missed_rx;
3813
3814 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 3815 if (hw->mac.type == ixgbe_mac_82599EB) {
3816 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3817 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3818 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3819 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3820 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3821 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3822 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3823 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3824 } else {
3825 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3826 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3827 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3828 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3829 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3830 }
9a799d71
AK		 3831 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3832 adapter->stats.bprc += bprc;
3833 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 3834 if (hw->mac.type == ixgbe_mac_82598EB)
3835 adapter->stats.mprc -= bprc;
9a799d71
AK		 3836 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3837 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3838 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3839 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3840 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3841 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3842 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 3843 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 3844 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3845 adapter->stats.lxontxc += lxon;
3846 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3847 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3848 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3849 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3850 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3851 /*
3852 * 82598 errata - tx of flow control packets is included in tx counters
3853 */
3854 xon_off_tot = lxon + lxoff;
3855 adapter->stats.gptc -= xon_off_tot;
3856 adapter->stats.mptc -= xon_off_tot;
3857 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3858 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3859 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3860 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3861 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3862 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3863 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3864 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3865 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3866 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3867 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3868 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3869 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3870
3871 /* Fill out the OS statistics structure */
9a799d71
AK		 3872 adapter->net_stats.multicast = adapter->stats.mprc;
3873
3874 /* Rx Errors */
3875 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3876 adapter->stats.rlec;
9a799d71
AK		 3877 adapter->net_stats.rx_dropped = 0;
3878 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3879 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3880 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3881}
3882
3883/**
3884 * ixgbe_watchdog - Timer Call-back
3885 * @data: pointer to adapter cast into an unsigned long
3886 **/
3887static void ixgbe_watchdog(unsigned long data)
3888{
3889 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3890 struct ixgbe_hw *hw = &adapter->hw;
3891
3892 /* Do the watchdog outside of interrupt context due to the lovely
3893 * delays that some of the newer hardware requires */
3894 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
22d5a71b
JB		 3895 u64 eics = 0;
3896 int i;
3897
3898 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
3899 eics |= (1 << i);
3900
cf8280ee 3901 /* Cause software interrupt to ensure rx rings are cleaned */
22d5a71b
JB		 3902 switch (hw->mac.type) {
3903 case ixgbe_mac_82598EB:
3904 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3905 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
3906 } else {
3907 /*
3908 * for legacy and MSI interrupts don't set any
3909 * bits that are enabled for EIAM, because this
3910 * operation would set *both* EIMS and EICS for
3911 * any bit in EIAM
3912 */
3913 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3914 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3915 }
3916 break;
3917 case ixgbe_mac_82599EB:
3918 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3919 /*
3920 * EICS(0..15) first 0-15 q vectors
3921 * EICS[1] (16..31) q vectors 16-31
3922 * EICS[2] (0..31) q vectors 32-63
3923 */
3924 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3925 (u32)(eics & 0xFFFF));
3926 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
3927 (u32)(eics & 0xFFFF0000));
3928 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(2),
3929 (u32)(eics >> 32));
3930 } else {
3931 /*
3932 * for legacy and MSI interrupts don't set any
3933 * bits that are enabled for EIAM, because this
3934 * operation would set *both* EIMS and EICS for
3935 * any bit in EIAM
3936 */
3937 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3938 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3939 }
3940 break;
3941 default:
3942 break;
cf8280ee
JB		 3943 }
3944 /* Reset the timer */
3945 mod_timer(&adapter->watchdog_timer,
3946 round_jiffies(jiffies + 2 * HZ));
3947 }
9a799d71 3948
cf8280ee
JB		 3949 schedule_work(&adapter->watchdog_task);
3950}
3951
e8e26350
PW		 3952/**
3953 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
3954 * @work: pointer to work_struct containing our data
3955 **/
3956static void ixgbe_multispeed_fiber_task(struct work_struct *work)
3957{
3958 struct ixgbe_adapter *adapter = container_of(work,
3959 struct ixgbe_adapter,
3960 multispeed_fiber_task);
3961 struct ixgbe_hw *hw = &adapter->hw;
3962 u32 autoneg;
3963
3964 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
3965 if (hw->mac.ops.get_link_capabilities)
3966 hw->mac.ops.get_link_capabilities(hw, &autoneg,
3967 &hw->mac.autoneg);
3968 if (hw->mac.ops.setup_link_speed)
3969 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3970 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3971 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
3972}
3973
3974/**
3975 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
3976 * @work: pointer to work_struct containing our data
3977 **/
3978static void ixgbe_sfp_config_module_task(struct work_struct *work)
3979{
3980 struct ixgbe_adapter *adapter = container_of(work,
3981 struct ixgbe_adapter,
3982 sfp_config_module_task);
3983 struct ixgbe_hw *hw = &adapter->hw;
3984 u32 err;
3985
3986 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
3987 err = hw->phy.ops.identify_sfp(hw);
3988 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3989 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
3990 ixgbe_down(adapter);
3991 return;
3992 }
3993 hw->mac.ops.setup_sfp(hw);
3994
8d1c3c07 3995 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 3996 /* This will also work for DA Twinax connections */
3997 schedule_work(&adapter->multispeed_fiber_task);
3998 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
3999}
4000
cf8280ee 4001/**
69888674
AD		 4002 * ixgbe_watchdog_task - worker thread to bring link up
4003 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4004 **/
4005static void ixgbe_watchdog_task(struct work_struct *work)
4006{
4007 struct ixgbe_adapter *adapter = container_of(work,
4008 struct ixgbe_adapter,
4009 watchdog_task);
4010 struct net_device *netdev = adapter->netdev;
4011 struct ixgbe_hw *hw = &adapter->hw;
4012 u32 link_speed = adapter->link_speed;
4013 bool link_up = adapter->link_up;
4014
4015 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4016
4017 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4018 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4019 if (link_up ||
4020 time_after(jiffies, (adapter->link_check_timeout +
4021 IXGBE_TRY_LINK_TIMEOUT))) {
4022 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4023 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4024 }
4025 adapter->link_up = link_up;
4026 adapter->link_speed = link_speed;
4027 }
9a799d71
AK		 4028
4029 if (link_up) {
4030 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4031 bool flow_rx, flow_tx;
4032
4033 if (hw->mac.type == ixgbe_mac_82599EB) {
4034 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4035 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4036 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4037 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4038 } else {
4039 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4040 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4041 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4042 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4043 }
4044
a46e534b
JK		 4045 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4046 "Flow Control: %s\n",
4047 netdev->name,
4048 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4049 "10 Gbps" :
4050 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4051 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4052 ((flow_rx && flow_tx) ? "RX/TX" :
4053 (flow_rx ? "RX" :
4054 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4055
4056 netif_carrier_on(netdev);
9a799d71
AK		 4057 } else {
4058 /* Force detection of hung controller */
4059 adapter->detect_tx_hung = true;
4060 }
4061 } else {
cf8280ee
JB		 4062 adapter->link_up = false;
4063 adapter->link_speed = 0;
9a799d71 4064 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4065 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4066 netdev->name);
9a799d71 4067 netif_carrier_off(netdev);
9a799d71
AK		 4068 }
4069 }
4070
4071 ixgbe_update_stats(adapter);
cf8280ee 4072 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4073}
4074
9a799d71 4075static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4076 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4077 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4078{
4079 struct ixgbe_adv_tx_context_desc *context_desc;
4080 unsigned int i;
4081 int err;
4082 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4083 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4084 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4085
4086 if (skb_is_gso(skb)) {
4087 if (skb_header_cloned(skb)) {
4088 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4089 if (err)
4090 return err;
4091 }
4092 l4len = tcp_hdrlen(skb);
4093 *hdr_len += l4len;
4094
8327d000 4095 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4096 struct iphdr *iph = ip_hdr(skb);
4097 iph->tot_len = 0;
4098 iph->check = 0;
4099 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4100 iph->daddr, 0,
4101 IPPROTO_TCP,
4102 0);
9a799d71
AK		 4103 adapter->hw_tso_ctxt++;
4104 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4105 ipv6_hdr(skb)->payload_len = 0;
4106 tcp_hdr(skb)->check =
4107 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4108 &ipv6_hdr(skb)->daddr,
4109 0, IPPROTO_TCP, 0);
9a799d71
AK		 4110 adapter->hw_tso6_ctxt++;
4111 }
4112
4113 i = tx_ring->next_to_use;
4114
4115 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4116 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4117
4118 /* VLAN MACLEN IPLEN */
4119 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4120 vlan_macip_lens |=
4121 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4122 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4123 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4124 *hdr_len += skb_network_offset(skb);
4125 vlan_macip_lens |=
4126 (skb_transport_header(skb) - skb_network_header(skb));
4127 *hdr_len +=
4128 (skb_transport_header(skb) - skb_network_header(skb));
4129 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4130 context_desc->seqnum_seed = 0;
4131
4132 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4133 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4134 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4135
8327d000 4136 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4137 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4138 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4139 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4140
4141 /* MSS L4LEN IDX */
9f8cdf4f 4142 mss_l4len_idx =
9a799d71
AK		 4143 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4144 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4145 /* use index 1 for TSO */
4146 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4147 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4148
4149 tx_buffer_info->time_stamp = jiffies;
4150 tx_buffer_info->next_to_watch = i;
4151
4152 i++;
4153 if (i == tx_ring->count)
4154 i = 0;
4155 tx_ring->next_to_use = i;
4156
4157 return true;
4158 }
4159 return false;
4160}
4161
4162static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4163 struct ixgbe_ring *tx_ring,
4164 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4165{
4166 struct ixgbe_adv_tx_context_desc *context_desc;
4167 unsigned int i;
4168 struct ixgbe_tx_buffer *tx_buffer_info;
4169 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4170
4171 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4172 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4173 i = tx_ring->next_to_use;
4174 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4175 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4176
4177 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4178 vlan_macip_lens |=
4179 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4180 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4181 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4182 if (skb->ip_summed == CHECKSUM_PARTIAL)
4183 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4184 skb_network_header(skb));
9a799d71
AK		 4185
4186 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4187 context_desc->seqnum_seed = 0;
4188
4189 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4190 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4191
4192 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4193 switch (skb->protocol) {
09640e63 4194 case cpu_to_be16(ETH_P_IP):
9a799d71 4195 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4196 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4197 type_tucmd_mlhl |=
b4617240 4198 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 4199 break;
09640e63 4200 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4201 /* XXX what about other V6 headers?? */
4202 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4203 type_tucmd_mlhl |=
b4617240 4204 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 4205 break;
41825d71
AK		 4206 default:
4207 if (unlikely(net_ratelimit())) {
4208 DPRINTK(PROBE, WARNING,
4209 "partial checksum but proto=%x!\n",
4210 skb->protocol);
4211 }
4212 break;
4213 }
9a799d71
AK		 4214 }
4215
4216 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4217 /* use index zero for tx checksum offload */
9a799d71
AK		 4218 context_desc->mss_l4len_idx = 0;
4219
4220 tx_buffer_info->time_stamp = jiffies;
4221 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4222
9a799d71
AK		 4223 adapter->hw_csum_tx_good++;
4224 i++;
4225 if (i == tx_ring->count)
4226 i = 0;
4227 tx_ring->next_to_use = i;
4228
4229 return true;
4230 }
9f8cdf4f 4231
9a799d71
AK		 4232 return false;
4233}
4234
4235static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 4236 struct ixgbe_ring *tx_ring,
4237 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 4238{
4239 struct ixgbe_tx_buffer *tx_buffer_info;
44df32c5 4240 unsigned int len = skb_headlen(skb);
9a799d71
AK		 4241 unsigned int offset = 0, size, count = 0, i;
4242 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4243 unsigned int f;
44df32c5 4244 dma_addr_t *map;
9a799d71
AK		 4245
4246 i = tx_ring->next_to_use;
4247
44df32c5
AD		 4248 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4249 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4250 return 0;
4251 }
4252
4253 map = skb_shinfo(skb)->dma_maps;
4254
9a799d71
AK		 4255 while (len) {
4256 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4257 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4258
4259 tx_buffer_info->length = size;
44df32c5 4260 tx_buffer_info->dma = map[0] + offset;
9a799d71
AK		 4261 tx_buffer_info->time_stamp = jiffies;
4262 tx_buffer_info->next_to_watch = i;
4263
4264 len -= size;
4265 offset += size;
4266 count++;
44df32c5
AD		 4267
4268 if (len) {
4269 i++;
4270 if (i == tx_ring->count)
4271 i = 0;
4272 }
9a799d71
AK		 4273 }
4274
4275 for (f = 0; f < nr_frags; f++) {
4276 struct skb_frag_struct *frag;
4277
4278 frag = &skb_shinfo(skb)->frags[f];
4279 len = frag->size;
44df32c5 4280 offset = 0;
9a799d71
AK		 4281
4282 while (len) {
44df32c5
AD		 4283 i++;
4284 if (i == tx_ring->count)
4285 i = 0;
4286
9a799d71
AK		 4287 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4288 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4289
4290 tx_buffer_info->length = size;
44df32c5 4291 tx_buffer_info->dma = map[f + 1] + offset;
9a799d71
AK		 4292 tx_buffer_info->time_stamp = jiffies;
4293 tx_buffer_info->next_to_watch = i;
4294
4295 len -= size;
4296 offset += size;
4297 count++;
9a799d71
AK		 4298 }
4299 }
44df32c5 4300
9a799d71
AK		 4301 tx_ring->tx_buffer_info[i].skb = skb;
4302 tx_ring->tx_buffer_info[first].next_to_watch = i;
4303
4304 return count;
4305}
4306
4307static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4308 struct ixgbe_ring *tx_ring,
4309 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4310{
4311 union ixgbe_adv_tx_desc *tx_desc = NULL;
4312 struct ixgbe_tx_buffer *tx_buffer_info;
4313 u32 olinfo_status = 0, cmd_type_len = 0;
4314 unsigned int i;
4315 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4316
4317 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4318
4319 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4320
4321 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4322 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4323
4324 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4325 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4326
4327 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4328 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4329
4eeae6fd
PW		 4330 /* use index 1 context for tso */
4331 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4332 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4333 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4334 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4335
4336 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4337 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4338 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4339
4340 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4341
4342 i = tx_ring->next_to_use;
4343 while (count--) {
4344 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4345 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4346 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4347 tx_desc->read.cmd_type_len =
b4617240 4348 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4349 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4350 i++;
4351 if (i == tx_ring->count)
4352 i = 0;
4353 }
4354
4355 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4356
4357 /*
4358 * Force memory writes to complete before letting h/w
4359 * know there are new descriptors to fetch. (Only
4360 * applicable for weak-ordered memory model archs,
4361 * such as IA-64).
4362 */
4363 wmb();
4364
4365 tx_ring->next_to_use = i;
4366 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4367}
4368
e092be60 4369static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4370 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4371{
4372 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4373
30eba97a 4374 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4375 /* Herbert's original patch had:
4376 * smp_mb__after_netif_stop_queue();
4377 * but since that doesn't exist yet, just open code it. */
4378 smp_mb();
4379
4380 /* We need to check again in a case another CPU has just
4381 * made room available. */
4382 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4383 return -EBUSY;
4384
4385 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4386 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4387 ++adapter->restart_queue;
4388 return 0;
4389}
4390
4391static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4392 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4393{
4394 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4395 return 0;
4396 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4397}
4398
09a3b1f8
SH		 4399static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4400{
4401 struct ixgbe_adapter *adapter = netdev_priv(dev);
4402
4403 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4404 return 0; /* All traffic should default to class 0 */
4405
4406 return skb_tx_hash(dev, skb);
4407}
4408
9a799d71
AK		 4409static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4410{
4411 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4412 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4413 unsigned int first;
4414 unsigned int tx_flags = 0;
30eba97a
AV		 4415 u8 hdr_len = 0;
4416 int r_idx = 0, tso;
9a799d71
AK		 4417 int count = 0;
4418 unsigned int f;
9f8cdf4f 4419
95615d90 4420 r_idx = skb->queue_mapping;
30eba97a 4421 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4422
9f8cdf4f
JB		 4423 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4424 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4425 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4426 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4427 tx_flags |= (skb->queue_mapping << 13);
4428 }
4429 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4430 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4431 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4432 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4433 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4434 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4435 }
9f8cdf4f
JB		 4436 /* three things can cause us to need a context descriptor */
4437 if (skb_is_gso(skb) ||
4438 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4439 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 4440 count++;
4441
9f8cdf4f
JB		 4442 count += TXD_USE_COUNT(skb_headlen(skb));
4443 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4444 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4445
e092be60 4446 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4447 adapter->tx_busy++;
9a799d71
AK		 4448 return NETDEV_TX_BUSY;
4449 }
9a799d71 4450
8327d000 4451 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4452 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4453 first = tx_ring->next_to_use;
4454 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4455 if (tso < 0) {
4456 dev_kfree_skb_any(skb);
4457 return NETDEV_TX_OK;
4458 }
4459
4460 if (tso)
4461 tx_flags |= IXGBE_TX_FLAGS_TSO;
4462 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 4463 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 4464 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4465
44df32c5 4466 count = ixgbe_tx_map(adapter, tx_ring, skb, first);
9a799d71 4467
44df32c5
AD		 4468 if (count) {
4469 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4470 hdr_len);
4471 netdev->trans_start = jiffies;
4472 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 4473
44df32c5
AD		 4474 } else {
4475 dev_kfree_skb_any(skb);
4476 tx_ring->tx_buffer_info[first].time_stamp = 0;
4477 tx_ring->next_to_use = first;
4478 }
9a799d71
AK		 4479
4480 return NETDEV_TX_OK;
4481}
4482
4483/**
4484 * ixgbe_get_stats - Get System Network Statistics
4485 * @netdev: network interface device structure
4486 *
4487 * Returns the address of the device statistics structure.
4488 * The statistics are actually updated from the timer callback.
4489 **/
4490static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4491{
4492 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4493
4494 /* only return the current stats */
4495 return &adapter->net_stats;
4496}
4497
4498/**
4499 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4500 * @netdev: network interface device structure
4501 * @p: pointer to an address structure
4502 *
4503 * Returns 0 on success, negative on failure
4504 **/
4505static int ixgbe_set_mac(struct net_device *netdev, void *p)
4506{
4507 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4508 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4509 struct sockaddr *addr = p;
4510
4511 if (!is_valid_ether_addr(addr->sa_data))
4512 return -EADDRNOTAVAIL;
4513
4514 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4515 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4516
b4617240 4517 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4518
4519 return 0;
4520}
4521
4522#ifdef CONFIG_NET_POLL_CONTROLLER
4523/*
4524 * Polling 'interrupt' - used by things like netconsole to send skbs
4525 * without having to re-enable interrupts. It's not called while
4526 * the interrupt routine is executing.
4527 */
4528static void ixgbe_netpoll(struct net_device *netdev)
4529{
4530 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4531
4532 disable_irq(adapter->pdev->irq);
4533 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4534 ixgbe_intr(adapter->pdev->irq, netdev);
4535 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4536 enable_irq(adapter->pdev->irq);
4537}
4538#endif
4539
0edc3527
SH		 4540static const struct net_device_ops ixgbe_netdev_ops = {
4541 .ndo_open = ixgbe_open,
4542 .ndo_stop = ixgbe_close,
00829823 4543 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 4544 .ndo_select_queue = ixgbe_select_queue,
0edc3527 4545 .ndo_get_stats = ixgbe_get_stats,
e90d400c 4546 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 4547 .ndo_set_multicast_list = ixgbe_set_rx_mode,
4548 .ndo_validate_addr = eth_validate_addr,
4549 .ndo_set_mac_address = ixgbe_set_mac,
4550 .ndo_change_mtu = ixgbe_change_mtu,
4551 .ndo_tx_timeout = ixgbe_tx_timeout,
4552 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
4553 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
4554 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
4555#ifdef CONFIG_NET_POLL_CONTROLLER
4556 .ndo_poll_controller = ixgbe_netpoll,
4557#endif
4558};
4559
9a799d71
AK		 4560/**
4561 * ixgbe_probe - Device Initialization Routine
4562 * @pdev: PCI device information struct
4563 * @ent: entry in ixgbe_pci_tbl
4564 *
4565 * Returns 0 on success, negative on failure
4566 *
4567 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4568 * The OS initialization, configuring of the adapter private structure,
4569 * and a hardware reset occur.
4570 **/
4571static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 4572 const struct pci_device_id *ent)
9a799d71
AK		 4573{
4574 struct net_device *netdev;
4575 struct ixgbe_adapter *adapter = NULL;
4576 struct ixgbe_hw *hw;
4577 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 4578 static int cards_found;
4579 int i, err, pci_using_dac;
e8e26350 4580 u16 pm_value = 0;
c44ade9e 4581 u32 part_num, eec;
9a799d71
AK		 4582
4583 err = pci_enable_device(pdev);
4584 if (err)
4585 return err;
4586
6a35528a
YH		 4587 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
4588 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 4589 pci_using_dac = 1;
4590 } else {
284901a9 4591 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 4592 if (err) {
284901a9 4593 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 4594 if (err) {
b4617240
PW		 4595 dev_err(&pdev->dev, "No usable DMA "
4596 "configuration, aborting\n");
9a799d71
AK		 4597 goto err_dma;
4598 }
4599 }
4600 pci_using_dac = 0;
4601 }
4602
4603 err = pci_request_regions(pdev, ixgbe_driver_name);
4604 if (err) {
4605 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4606 goto err_pci_reg;
4607 }
4608
6fabd715
PWJ		 4609 err = pci_enable_pcie_error_reporting(pdev);
4610 if (err) {
4611 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4612 "0x%x\n", err);
4613 /* non-fatal, continue */
4614 }
4615
9a799d71 4616 pci_set_master(pdev);
fb3b27bc 4617 pci_save_state(pdev);
9a799d71 4618
30eba97a 4619 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 4620 if (!netdev) {
4621 err = -ENOMEM;
4622 goto err_alloc_etherdev;
4623 }
4624
9a799d71
AK		 4625 SET_NETDEV_DEV(netdev, &pdev->dev);
4626
4627 pci_set_drvdata(pdev, netdev);
4628 adapter = netdev_priv(netdev);
4629
4630 adapter->netdev = netdev;
4631 adapter->pdev = pdev;
4632 hw = &adapter->hw;
4633 hw->back = adapter;
4634 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4635
05857980
JK		 4636 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4637 pci_resource_len(pdev, 0));
9a799d71
AK		 4638 if (!hw->hw_addr) {
4639 err = -EIO;
4640 goto err_ioremap;
4641 }
4642
4643 for (i = 1; i <= 5; i++) {
4644 if (pci_resource_len(pdev, i) == 0)
4645 continue;
4646 }
4647
0edc3527 4648 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 4649 ixgbe_set_ethtool_ops(netdev);
9a799d71 4650 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 4651 strcpy(netdev->name, pci_name(pdev));
4652
9a799d71
AK		 4653 adapter->bd_number = cards_found;
4654
9a799d71
AK		 4655 /* Setup hw api */
4656 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 4657 hw->mac.type = ii->mac;
9a799d71 4658
c44ade9e
JB		 4659 /* EEPROM */
4660 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4661 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4662 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4663 if (!(eec & (1 << 8)))
4664 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4665
4666 /* PHY */
4667 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0
DS		 4668 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4669
4670 /* set up this timer and work struct before calling get_invariants
4671 * which might start the timer
4672 */
4673 init_timer(&adapter->sfp_timer);
4674 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4675 adapter->sfp_timer.data = (unsigned long) adapter;
4676
4677 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 4678
e8e26350
PW		 4679 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4680 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4681
4682 /* a new SFP+ module arrival, called from GPI SDP2 context */
4683 INIT_WORK(&adapter->sfp_config_module_task,
4684 ixgbe_sfp_config_module_task);
4685
9a799d71 4686 err = ii->get_invariants(hw);
c4900be0
DS		 4687 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4688 /* start a kernel thread to watch for a module to arrive */
4689 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4690 mod_timer(&adapter->sfp_timer,
4691 round_jiffies(jiffies + (2 * HZ)));
4692 err = 0;
4693 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4694 DPRINTK(PROBE, ERR, "failed to load because an "
4695 "unsupported SFP+ module type was detected.\n");
9a799d71 4696 goto err_hw_init;
c4900be0
DS		 4697 } else if (err) {
4698 goto err_hw_init;
4699 }
9a799d71
AK		 4700
4701 /* setup the private structure */
4702 err = ixgbe_sw_init(adapter);
4703 if (err)
4704 goto err_sw_init;
4705
c44ade9e
JB		 4706 /* reset_hw fills in the perm_addr as well */
4707 err = hw->mac.ops.reset_hw(hw);
04f165ef
PW		 4708 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4709 dev_err(&adapter->pdev->dev, "failed to load because an "
4710 "unsupported SFP+ module type was detected.\n");
4711 goto err_sw_init;
4712 } else if (err) {
c44ade9e
JB		 4713 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4714 goto err_sw_init;
4715 }
4716
9a799d71 4717 netdev->features = NETIF_F_SG |
b4617240
PW		 4718 NETIF_F_IP_CSUM |
4719 NETIF_F_HW_VLAN_TX |
4720 NETIF_F_HW_VLAN_RX |
4721 NETIF_F_HW_VLAN_FILTER;
9a799d71 4722
e9990a9c 4723 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4724 netdev->features |= NETIF_F_TSO;
9a799d71 4725 netdev->features |= NETIF_F_TSO6;
78b6f4ce 4726 netdev->features |= NETIF_F_GRO;
ad31c402
JK		 4727
4728 netdev->vlan_features |= NETIF_F_TSO;
4729 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4730 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4731 netdev->vlan_features |= NETIF_F_SG;
4732
2f90b865
AD		 4733 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4734 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4735
7a6b6f51 4736#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4737 netdev->dcbnl_ops = &dcbnl_ops;
4738#endif
4739
9a799d71
AK		 4740 if (pci_using_dac)
4741 netdev->features |= NETIF_F_HIGHDMA;
4742
9a799d71 4743 /* make sure the EEPROM is good */
c44ade9e 4744 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4745 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4746 err = -EIO;
4747 goto err_eeprom;
4748 }
4749
4750 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4751 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4752
c44ade9e
JB		 4753 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4754 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4755 err = -EIO;
4756 goto err_eeprom;
4757 }
4758
4759 init_timer(&adapter->watchdog_timer);
4760 adapter->watchdog_timer.function = &ixgbe_watchdog;
4761 adapter->watchdog_timer.data = (unsigned long)adapter;
4762
4763 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 4764 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 4765
021230d4
AV		 4766 err = ixgbe_init_interrupt_scheme(adapter);
4767 if (err)
4768 goto err_sw_init;
9a799d71 4769
e8e26350
PW		 4770 switch (pdev->device) {
4771 case IXGBE_DEV_ID_82599_KX4:
4772#define IXGBE_PCIE_PMCSR 0x44
4773 adapter->wol = IXGBE_WUFC_MAG;
4774 pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value);
4775 pci_write_config_word(pdev, IXGBE_PCIE_PMCSR,
4776 (pm_value | (1 << 8)));
4777 break;
4778 default:
4779 adapter->wol = 0;
4780 break;
4781 }
4782 device_init_wakeup(&adapter->pdev->dev, true);
4783 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4784
04f165ef
PW		 4785 /* pick up the PCI bus settings for reporting later */
4786 hw->mac.ops.get_bus_info(hw);
4787
9a799d71 4788 /* print bus type/speed/width info */
7c510e4b 4789 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 4790 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4791 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4792 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4793 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4794 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 4795 "Unknown"),
7c510e4b 4796 netdev->dev_addr);
c44ade9e 4797 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 4798 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4799 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4800 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4801 (part_num >> 8), (part_num & 0xff));
4802 else
4803 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4804 hw->mac.type, hw->phy.type,
4805 (part_num >> 8), (part_num & 0xff));
9a799d71 4806
e8e26350 4807 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 4808 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 4809 "this card is not sufficient for optimal "
4810 "performance.\n");
0c254d86 4811 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 4812 "PCI-Express slot is required.\n");
0c254d86
AK		 4813 }
4814
34b0368c
PWJ		 4815 /* save off EEPROM version number */
4816 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4817
9a799d71 4818 /* reset the hardware with the new settings */
c44ade9e
JB		 4819 hw->mac.ops.start_hw(hw);
4820
9a799d71
AK		 4821 strcpy(netdev->name, "eth%d");
4822 err = register_netdev(netdev);
4823 if (err)
4824 goto err_register;
4825
54386467
JB		 4826 /* carrier off reporting is important to ethtool even BEFORE open */
4827 netif_carrier_off(netdev);
4828
5dd2d332 4829#ifdef CONFIG_IXGBE_DCA
652f093f 4830 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 4831 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4832 /* always use CB2 mode, difference is masked
4833 * in the CB driver */
4834 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4835 ixgbe_setup_dca(adapter);
4836 }
4837#endif
9a799d71
AK		 4838
4839 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4840 cards_found++;
4841 return 0;
4842
4843err_register:
5eba3699 4844 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4845err_hw_init:
4846err_sw_init:
021230d4 4847 ixgbe_reset_interrupt_capability(adapter);
9a799d71 4848err_eeprom:
c4900be0
DS		 4849 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4850 del_timer_sync(&adapter->sfp_timer);
4851 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4852 cancel_work_sync(&adapter->multispeed_fiber_task);
4853 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4854 iounmap(hw->hw_addr);
4855err_ioremap:
4856 free_netdev(netdev);
4857err_alloc_etherdev:
4858 pci_release_regions(pdev);
4859err_pci_reg:
4860err_dma:
4861 pci_disable_device(pdev);
4862 return err;
4863}
4864
4865/**
4866 * ixgbe_remove - Device Removal Routine
4867 * @pdev: PCI device information struct
4868 *
4869 * ixgbe_remove is called by the PCI subsystem to alert the driver
4870 * that it should release a PCI device. The could be caused by a
4871 * Hot-Plug event, or because the driver is going to be removed from
4872 * memory.
4873 **/
4874static void __devexit ixgbe_remove(struct pci_dev *pdev)
4875{
4876 struct net_device *netdev = pci_get_drvdata(pdev);
4877 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 4878 int err;
9a799d71
AK		 4879
4880 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 4881 /* clear the module not found bit to make sure the worker won't
4882 * reschedule
4883 */
4884 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 4885 del_timer_sync(&adapter->watchdog_timer);
4886
c4900be0
DS		 4887 del_timer_sync(&adapter->sfp_timer);
4888 cancel_work_sync(&adapter->watchdog_task);
4889 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4890 cancel_work_sync(&adapter->multispeed_fiber_task);
4891 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4892 flush_scheduled_work();
4893
5dd2d332 4894#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4895 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4896 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4897 dca_remove_requester(&pdev->dev);
4898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4899 }
4900
4901#endif
c4900be0
DS		 4902 if (netdev->reg_state == NETREG_REGISTERED)
4903 unregister_netdev(netdev);
9a799d71 4904
021230d4 4905 ixgbe_reset_interrupt_capability(adapter);
5eba3699 4906
021230d4 4907 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4908
4909 iounmap(adapter->hw.hw_addr);
4910 pci_release_regions(pdev);
4911
021230d4
AV		 4912 DPRINTK(PROBE, INFO, "complete\n");
4913 kfree(adapter->tx_ring);
4914 kfree(adapter->rx_ring);
4915
9a799d71
AK		 4916 free_netdev(netdev);
4917
6fabd715
PWJ		 4918 err = pci_disable_pcie_error_reporting(pdev);
4919 if (err)
4920 dev_err(&pdev->dev,
4921 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4922
9a799d71
AK		 4923 pci_disable_device(pdev);
4924}
4925
4926/**
4927 * ixgbe_io_error_detected - called when PCI error is detected
4928 * @pdev: Pointer to PCI device
4929 * @state: The current pci connection state
4930 *
4931 * This function is called after a PCI bus error affecting
4932 * this device has been detected.
4933 */
4934static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 4935 pci_channel_state_t state)
9a799d71
AK		 4936{
4937 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4938 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4939
4940 netif_device_detach(netdev);
4941
4942 if (netif_running(netdev))
4943 ixgbe_down(adapter);
4944 pci_disable_device(pdev);
4945
b4617240 4946 /* Request a slot reset. */
9a799d71
AK		 4947 return PCI_ERS_RESULT_NEED_RESET;
4948}
4949
4950/**
4951 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4952 * @pdev: Pointer to PCI device
4953 *
4954 * Restart the card from scratch, as if from a cold-boot.
4955 */
4956static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4957{
4958 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4959 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 4960 pci_ers_result_t result;
4961 int err;
9a799d71
AK		 4962
4963 if (pci_enable_device(pdev)) {
4964 DPRINTK(PROBE, ERR,
b4617240 4965 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 4966 result = PCI_ERS_RESULT_DISCONNECT;
4967 } else {
4968 pci_set_master(pdev);
4969 pci_restore_state(pdev);
9a799d71 4970
6fabd715
PWJ		 4971 pci_enable_wake(pdev, PCI_D3hot, 0);
4972 pci_enable_wake(pdev, PCI_D3cold, 0);
9a799d71 4973
6fabd715 4974 ixgbe_reset(adapter);
88512539 4975 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 4976 result = PCI_ERS_RESULT_RECOVERED;
4977 }
4978
4979 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4980 if (err) {
4981 dev_err(&pdev->dev,
4982 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4983 /* non-fatal, continue */
4984 }
9a799d71 4985
6fabd715 4986 return result;
9a799d71
AK		 4987}
4988
4989/**
4990 * ixgbe_io_resume - called when traffic can start flowing again.
4991 * @pdev: Pointer to PCI device
4992 *
4993 * This callback is called when the error recovery driver tells us that
4994 * its OK to resume normal operation.
4995 */
4996static void ixgbe_io_resume(struct pci_dev *pdev)
4997{
4998 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4999 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5000
5001 if (netif_running(netdev)) {
5002 if (ixgbe_up(adapter)) {
5003 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5004 return;
5005 }
5006 }
5007
5008 netif_device_attach(netdev);
9a799d71
AK		 5009}
5010
5011static struct pci_error_handlers ixgbe_err_handler = {
5012 .error_detected = ixgbe_io_error_detected,
5013 .slot_reset = ixgbe_io_slot_reset,
5014 .resume = ixgbe_io_resume,
5015};
5016
5017static struct pci_driver ixgbe_driver = {
5018 .name = ixgbe_driver_name,
5019 .id_table = ixgbe_pci_tbl,
5020 .probe = ixgbe_probe,
5021 .remove = __devexit_p(ixgbe_remove),
5022#ifdef CONFIG_PM
5023 .suspend = ixgbe_suspend,
5024 .resume = ixgbe_resume,
5025#endif
5026 .shutdown = ixgbe_shutdown,
5027 .err_handler = &ixgbe_err_handler
5028};
5029
5030/**
5031 * ixgbe_init_module - Driver Registration Routine
5032 *
5033 * ixgbe_init_module is the first routine called when the driver is
5034 * loaded. All it does is register with the PCI subsystem.
5035 **/
5036static int __init ixgbe_init_module(void)
5037{
5038 int ret;
5039 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5040 ixgbe_driver_string, ixgbe_driver_version);
5041
5042 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5043
5dd2d332 5044#ifdef CONFIG_IXGBE_DCA
bd0362dd 5045 dca_register_notify(&dca_notifier);
bd0362dd 5046#endif
5dd2d332 5047
9a799d71
AK		 5048 ret = pci_register_driver(&ixgbe_driver);
5049 return ret;
5050}
b4617240 5051
9a799d71
AK		 5052module_init(ixgbe_init_module);
5053
5054/**
5055 * ixgbe_exit_module - Driver Exit Cleanup Routine
5056 *
5057 * ixgbe_exit_module is called just before the driver is removed
5058 * from memory.
5059 **/
5060static void __exit ixgbe_exit_module(void)
5061{
5dd2d332 5062#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5063 dca_unregister_notify(&dca_notifier);
5064#endif
9a799d71
AK		 5065 pci_unregister_driver(&ixgbe_driver);
5066}
bd0362dd 5067
5dd2d332 5068#ifdef CONFIG_IXGBE_DCA
bd0362dd 5069static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5070 void *p)
bd0362dd
JC		 5071{
5072 int ret_val;
5073
5074 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5075 __ixgbe_notify_dca);
bd0362dd
JC		 5076
5077 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5078}
b453368d 5079
5dd2d332 5080#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5081#ifdef DEBUG
5082/**
5083 * ixgbe_get_hw_dev_name - return device name string
5084 * used by hardware layer to print debugging information
5085 **/
5086char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5087{
5088 struct ixgbe_adapter *adapter = hw->back;
5089 return adapter->netdev->name;
5090}
bd0362dd 5091
b453368d 5092#endif
9a799d71
AK		 5093module_exit(ixgbe_exit_module);
5094
5095/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree