drm/radeon/kms: add some missing regs to evergreen gpu init

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 37c7a434ed3485c3401b120c5b231258355b3986..1caf625e472b607b92b2841f0dcf7fae44785cde 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1260,6 +1260,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
        WREG32(VGT_GS_VERTEX_REUSE, 16);
        WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 
+       WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
+       WREG32(VGT_OUT_DEALLOC_CNTL, 16);
+
        WREG32(CB_PERF_CTR0_SEL_0, 0);
        WREG32(CB_PERF_CTR0_SEL_1, 0);
        WREG32(CB_PERF_CTR1_SEL_0, 0);
@@ -1269,6 +1272,26 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
        WREG32(CB_PERF_CTR3_SEL_0, 0);
        WREG32(CB_PERF_CTR3_SEL_1, 0);
 
+       /* clear render buffer base addresses */
+       WREG32(CB_COLOR0_BASE, 0);
+       WREG32(CB_COLOR1_BASE, 0);
+       WREG32(CB_COLOR2_BASE, 0);
+       WREG32(CB_COLOR3_BASE, 0);
+       WREG32(CB_COLOR4_BASE, 0);
+       WREG32(CB_COLOR5_BASE, 0);
+       WREG32(CB_COLOR6_BASE, 0);
+       WREG32(CB_COLOR7_BASE, 0);
+       WREG32(CB_COLOR8_BASE, 0);
+       WREG32(CB_COLOR9_BASE, 0);
+       WREG32(CB_COLOR10_BASE, 0);
+       WREG32(CB_COLOR11_BASE, 0);
+
+       /* set the shader const cache sizes to 0 */
+       for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
+               WREG32(i, 0);
+       for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
+               WREG32(i, 0);
+
        hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
        WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 

diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 79683f6b4452907854d2a6fa9639bf04132a785c..a1cd621780e21bc5fdd7251c397dfc362d3c5ec3 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -713,6 +713,9 @@
 #define SQ_GSVS_RING_OFFSET_2                          0x28930
 #define SQ_GSVS_RING_OFFSET_3                          0x28934
 
+#define SQ_ALU_CONST_BUFFER_SIZE_PS_0                  0x28140
+#define SQ_ALU_CONST_BUFFER_SIZE_HS_0                  0x28f80
+
 #define SQ_ALU_CONST_CACHE_PS_0                                0x28940
 #define SQ_ALU_CONST_CACHE_PS_1                                0x28944
 #define SQ_ALU_CONST_CACHE_PS_2                                0x28948