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gianfar: fix signedness issue
[net-next-2.6.git] / drivers / net / gianfar.c
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0bbaf069 1/*
1da177e4
LT		 2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
a12f801d 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 12 *
a12f801d
SG		 13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
0bbaf069 28 *
b31a1d8b
AF		 29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
0bbaf069 39 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
bb40dcbb 43 * of frames or amount of time have passed). In NAPI, the
1da177e4 44 * interrupt handler will signal there is work to be done, and
0aa1538f 45 * exit. This method will start at the last known empty
0bbaf069 46 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
1da177e4 65#include <linux/kernel.h>
1da177e4
LT		 66#include <linux/string.h>
67#include <linux/errno.h>
bb40dcbb 68#include <linux/unistd.h>
1da177e4
LT		 69#include <linux/slab.h>
70#include <linux/interrupt.h>
71#include <linux/init.h>
72#include <linux/delay.h>
73#include <linux/netdevice.h>
74#include <linux/etherdevice.h>
75#include <linux/skbuff.h>
0bbaf069 76#include <linux/if_vlan.h>
1da177e4
LT		 77#include <linux/spinlock.h>
78#include <linux/mm.h>
fe192a49 79#include <linux/of_mdio.h>
b31a1d8b 80#include <linux/of_platform.h>
0bbaf069
KG		 81#include <linux/ip.h>
82#include <linux/tcp.h>
83#include <linux/udp.h>
9c07b884 84#include <linux/in.h>
cc772ab7 85#include <linux/net_tstamp.h>
1da177e4
LT		 86
87#include <asm/io.h>
7d350977 88#include <asm/reg.h>
1da177e4
LT		 89#include <asm/irq.h>
90#include <asm/uaccess.h>
91#include <linux/module.h>
1da177e4
LT		 92#include <linux/dma-mapping.h>
93#include <linux/crc32.h>
bb40dcbb
AF		 94#include <linux/mii.h>
95#include <linux/phy.h>
b31a1d8b
AF		 96#include <linux/phy_fixed.h>
97#include <linux/of.h>
1da177e4
LT		 98
99#include "gianfar.h"
1577ecef 100#include "fsl_pq_mdio.h"
1da177e4
LT		 101
102#define TX_TIMEOUT (1*HZ)
1da177e4
LT		 103#undef BRIEF_GFAR_ERRORS
104#undef VERBOSE_GFAR_ERRORS
105
1da177e4 106const char gfar_driver_name[] = "Gianfar Ethernet";
7f7f5316 107const char gfar_driver_version[] = "1.3";
1da177e4 108
1da177e4
LT		 109static int gfar_enet_open(struct net_device *dev);
110static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 111static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 112static void gfar_timeout(struct net_device *dev);
113static int gfar_close(struct net_device *dev);
815b97c6 114struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 115static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6 116 struct sk_buff *skb);
1da177e4
LT		 117static int gfar_set_mac_address(struct net_device *dev);
118static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 119static irqreturn_t gfar_error(int irq, void *dev_id);
120static irqreturn_t gfar_transmit(int irq, void *dev_id);
121static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 122static void adjust_link(struct net_device *dev);
123static void init_registers(struct net_device *dev);
124static int init_phy(struct net_device *dev);
2dc11581 125static int gfar_probe(struct platform_device *ofdev,
b31a1d8b 126 const struct of_device_id *match);
2dc11581 127static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 128static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 129static void gfar_set_multi(struct net_device *dev);
130static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 131static void gfar_configure_serdes(struct net_device *dev);
bea3348e 132static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 133#ifdef CONFIG_NET_POLL_CONTROLLER
134static void gfar_netpoll(struct net_device *dev);
135#endif
a12f801d
SG		 136int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
137static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a
DH		 138static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
139 int amount_pull);
0bbaf069
KG		 140static void gfar_vlan_rx_register(struct net_device *netdev,
141 struct vlan_group *grp);
7f7f5316 142void gfar_halt(struct net_device *dev);
d87eb127 143static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 144void gfar_start(struct net_device *dev);
145static void gfar_clear_exact_match(struct net_device *dev);
146static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
26ccfc37 147static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 148
1da177e4
LT		 149MODULE_AUTHOR("Freescale Semiconductor, Inc");
150MODULE_DESCRIPTION("Gianfar Ethernet Driver");
151MODULE_LICENSE("GPL");
152
a12f801d 153static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 154 dma_addr_t buf)
155{
8a102fe0
AV		 156 u32 lstatus;
157
158 bdp->bufPtr = buf;
159
160 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 161 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 162 lstatus |= BD_LFLAG(RXBD_WRAP);
163
164 eieio();
165
166 bdp->lstatus = lstatus;
167}
168
8728327e 169static int gfar_init_bds(struct net_device *ndev)
826aa4a0 170{
8728327e 171 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 172 struct gfar_priv_tx_q *tx_queue = NULL;
173 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 174 struct txbd8 *txbdp;
175 struct rxbd8 *rxbdp;
fba4ed03 176 int i, j;
a12f801d 177
fba4ed03
SG		 178 for (i = 0; i < priv->num_tx_queues; i++) {
179 tx_queue = priv->tx_queue[i];
180 /* Initialize some variables in our dev structure */
181 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
182 tx_queue->dirty_tx = tx_queue->tx_bd_base;
183 tx_queue->cur_tx = tx_queue->tx_bd_base;
184 tx_queue->skb_curtx = 0;
185 tx_queue->skb_dirtytx = 0;
186
187 /* Initialize Transmit Descriptor Ring */
188 txbdp = tx_queue->tx_bd_base;
189 for (j = 0; j < tx_queue->tx_ring_size; j++) {
190 txbdp->lstatus = 0;
191 txbdp->bufPtr = 0;
192 txbdp++;
193 }
8728327e 194
fba4ed03
SG		 195 /* Set the last descriptor in the ring to indicate wrap */
196 txbdp--;
197 txbdp->status |= TXBD_WRAP;
8728327e
AV		 198 }
199
fba4ed03
SG		 200 for (i = 0; i < priv->num_rx_queues; i++) {
201 rx_queue = priv->rx_queue[i];
202 rx_queue->cur_rx = rx_queue->rx_bd_base;
203 rx_queue->skb_currx = 0;
204 rxbdp = rx_queue->rx_bd_base;
8728327e 205
fba4ed03
SG		 206 for (j = 0; j < rx_queue->rx_ring_size; j++) {
207 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 208
fba4ed03
SG		 209 if (skb) {
210 gfar_init_rxbdp(rx_queue, rxbdp,
211 rxbdp->bufPtr);
212 } else {
213 skb = gfar_new_skb(ndev);
214 if (!skb) {
215 pr_err("%s: Can't allocate RX buffers\n",
216 ndev->name);
217 goto err_rxalloc_fail;
218 }
219 rx_queue->rx_skbuff[j] = skb;
220
221 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 222 }
8728327e 223
fba4ed03 224 rxbdp++;
8728327e
AV		 225 }
226
8728327e
AV		 227 }
228
229 return 0;
fba4ed03
SG		 230
231err_rxalloc_fail:
232 free_skb_resources(priv);
233 return -ENOMEM;
8728327e
AV		 234}
235
236static int gfar_alloc_skb_resources(struct net_device *ndev)
237{
826aa4a0 238 void *vaddr;
fba4ed03
SG		 239 dma_addr_t addr;
240 int i, j, k;
826aa4a0
AV		 241 struct gfar_private *priv = netdev_priv(ndev);
242 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 243 struct gfar_priv_tx_q *tx_queue = NULL;
244 struct gfar_priv_rx_q *rx_queue = NULL;
245
fba4ed03
SG		 246 priv->total_tx_ring_size = 0;
247 for (i = 0; i < priv->num_tx_queues; i++)
248 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
249
250 priv->total_rx_ring_size = 0;
251 for (i = 0; i < priv->num_rx_queues; i++)
252 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 253
254 /* Allocate memory for the buffer descriptors */
8728327e 255 vaddr = dma_alloc_coherent(dev,
fba4ed03
SG		 256 sizeof(struct txbd8) * priv->total_tx_ring_size +
257 sizeof(struct rxbd8) * priv->total_rx_ring_size,
258 &addr, GFP_KERNEL);
826aa4a0
AV		 259 if (!vaddr) {
260 if (netif_msg_ifup(priv))
261 pr_err("%s: Could not allocate buffer descriptors!\n",
262 ndev->name);
263 return -ENOMEM;
264 }
265
fba4ed03
SG		 266 for (i = 0; i < priv->num_tx_queues; i++) {
267 tx_queue = priv->tx_queue[i];
268 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
269 tx_queue->tx_bd_dma_base = addr;
270 tx_queue->dev = ndev;
271 /* enet DMA only understands physical addresses */
272 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
273 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
274 }
826aa4a0 275
826aa4a0 276 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 277 for (i = 0; i < priv->num_rx_queues; i++) {
278 rx_queue = priv->rx_queue[i];
279 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
280 rx_queue->rx_bd_dma_base = addr;
281 rx_queue->dev = ndev;
282 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
283 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
284 }
826aa4a0
AV		 285
286 /* Setup the skbuff rings */
fba4ed03
SG		 287 for (i = 0; i < priv->num_tx_queues; i++) {
288 tx_queue = priv->tx_queue[i];
289 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
a12f801d 290 tx_queue->tx_ring_size, GFP_KERNEL);
fba4ed03
SG		 291 if (!tx_queue->tx_skbuff) {
292 if (netif_msg_ifup(priv))
293 pr_err("%s: Could not allocate tx_skbuff\n",
294 ndev->name);
295 goto cleanup;
296 }
826aa4a0 297
fba4ed03
SG		 298 for (k = 0; k < tx_queue->tx_ring_size; k++)
299 tx_queue->tx_skbuff[k] = NULL;
300 }
826aa4a0 301
fba4ed03
SG		 302 for (i = 0; i < priv->num_rx_queues; i++) {
303 rx_queue = priv->rx_queue[i];
304 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
a12f801d 305 rx_queue->rx_ring_size, GFP_KERNEL);
826aa4a0 306
fba4ed03
SG		 307 if (!rx_queue->rx_skbuff) {
308 if (netif_msg_ifup(priv))
309 pr_err("%s: Could not allocate rx_skbuff\n",
310 ndev->name);
311 goto cleanup;
312 }
313
314 for (j = 0; j < rx_queue->rx_ring_size; j++)
315 rx_queue->rx_skbuff[j] = NULL;
316 }
826aa4a0 317
8728327e
AV		 318 if (gfar_init_bds(ndev))
319 goto cleanup;
826aa4a0
AV		 320
321 return 0;
322
323cleanup:
324 free_skb_resources(priv);
325 return -ENOMEM;
326}
327
fba4ed03
SG		 328static void gfar_init_tx_rx_base(struct gfar_private *priv)
329{
46ceb60c 330 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 331 u32 __iomem *baddr;
fba4ed03
SG		 332 int i;
333
334 baddr = &regs->tbase0;
335 for(i = 0; i < priv->num_tx_queues; i++) {
336 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
337 baddr += 2;
338 }
339
340 baddr = &regs->rbase0;
341 for(i = 0; i < priv->num_rx_queues; i++) {
342 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
343 baddr += 2;
344 }
345}
346
826aa4a0
AV		 347static void gfar_init_mac(struct net_device *ndev)
348{
349 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 350 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 351 u32 rctrl = 0;
352 u32 tctrl = 0;
353 u32 attrs = 0;
354
fba4ed03
SG		 355 /* write the tx/rx base registers */
356 gfar_init_tx_rx_base(priv);
32c513bc 357
826aa4a0 358 /* Configure the coalescing support */
46ceb60c 359 gfar_configure_coalescing(priv, 0xFF, 0xFF);
fba4ed03 360
1ccb8389 361 if (priv->rx_filer_enable) {
fba4ed03 362 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 363 /* Program the RIR0 reg with the required distribution */
364 gfar_write(&regs->rir0, DEFAULT_RIR0);
365 }
826aa4a0
AV		 366
367 if (priv->rx_csum_enable)
368 rctrl |= RCTRL_CHECKSUMMING;
369
370 if (priv->extended_hash) {
371 rctrl |= RCTRL_EXTHASH;
372
373 gfar_clear_exact_match(ndev);
374 rctrl |= RCTRL_EMEN;
375 }
376
377 if (priv->padding) {
378 rctrl &= ~RCTRL_PAL_MASK;
379 rctrl |= RCTRL_PADDING(priv->padding);
380 }
381
cc772ab7
MR		 382 /* Insert receive time stamps into padding alignment bytes */
383 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
384 rctrl &= ~RCTRL_PAL_MASK;
97553f7f 385 rctrl |= RCTRL_PADDING(8);
cc772ab7
MR		 386 priv->padding = 8;
387 }
388
97553f7f
MR		 389 /* Enable HW time stamping if requested from user space */
390 if (priv->hwts_rx_en)
391 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
392
826aa4a0
AV		 393 /* keep vlan related bits if it's enabled */
394 if (priv->vlgrp) {
395 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
396 tctrl |= TCTRL_VLINS;
397 }
398
399 /* Init rctrl based on our settings */
400 gfar_write(&regs->rctrl, rctrl);
401
402 if (ndev->features & NETIF_F_IP_CSUM)
403 tctrl |= TCTRL_INIT_CSUM;
404
fba4ed03
SG		 405 tctrl |= TCTRL_TXSCHED_PRIO;
406
826aa4a0
AV		 407 gfar_write(&regs->tctrl, tctrl);
408
409 /* Set the extraction length and index */
410 attrs = ATTRELI_EL(priv->rx_stash_size) |
411 ATTRELI_EI(priv->rx_stash_index);
412
413 gfar_write(&regs->attreli, attrs);
414
415 /* Start with defaults, and add stashing or locking
416 * depending on the approprate variables */
417 attrs = ATTR_INIT_SETTINGS;
418
419 if (priv->bd_stash_en)
420 attrs |= ATTR_BDSTASH;
421
422 if (priv->rx_stash_size != 0)
423 attrs |= ATTR_BUFSTASH;
424
425 gfar_write(&regs->attr, attrs);
426
427 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
428 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
429 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
430}
431
a7f38041
SG		 432static struct net_device_stats *gfar_get_stats(struct net_device *dev)
433{
434 struct gfar_private *priv = netdev_priv(dev);
435 struct netdev_queue *txq;
436 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
437 unsigned long tx_packets = 0, tx_bytes = 0;
438 int i = 0;
439
440 for (i = 0; i < priv->num_rx_queues; i++) {
441 rx_packets += priv->rx_queue[i]->stats.rx_packets;
442 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
443 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
444 }
445
446 dev->stats.rx_packets = rx_packets;
447 dev->stats.rx_bytes = rx_bytes;
448 dev->stats.rx_dropped = rx_dropped;
449
450 for (i = 0; i < priv->num_tx_queues; i++) {
451 txq = netdev_get_tx_queue(dev, i);
452 tx_bytes += txq->tx_bytes;
453 tx_packets += txq->tx_packets;
454 }
455
456 dev->stats.tx_bytes = tx_bytes;
457 dev->stats.tx_packets = tx_packets;
458
459 return &dev->stats;
460}
461
26ccfc37
AF		 462static const struct net_device_ops gfar_netdev_ops = {
463 .ndo_open = gfar_enet_open,
464 .ndo_start_xmit = gfar_start_xmit,
465 .ndo_stop = gfar_close,
466 .ndo_change_mtu = gfar_change_mtu,
467 .ndo_set_multicast_list = gfar_set_multi,
468 .ndo_tx_timeout = gfar_timeout,
469 .ndo_do_ioctl = gfar_ioctl,
a7f38041 470 .ndo_get_stats = gfar_get_stats,
26ccfc37 471 .ndo_vlan_rx_register = gfar_vlan_rx_register,
240c102d
BH		 472 .ndo_set_mac_address = eth_mac_addr,
473 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 474#ifdef CONFIG_NET_POLL_CONTROLLER
475 .ndo_poll_controller = gfar_netpoll,
476#endif
477};
478
7a8b3372
SG		 479unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
480unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
481
fba4ed03
SG		 482void lock_rx_qs(struct gfar_private *priv)
483{
484 int i = 0x0;
485
486 for (i = 0; i < priv->num_rx_queues; i++)
487 spin_lock(&priv->rx_queue[i]->rxlock);
488}
489
490void lock_tx_qs(struct gfar_private *priv)
491{
492 int i = 0x0;
493
494 for (i = 0; i < priv->num_tx_queues; i++)
495 spin_lock(&priv->tx_queue[i]->txlock);
496}
497
498void unlock_rx_qs(struct gfar_private *priv)
499{
500 int i = 0x0;
501
502 for (i = 0; i < priv->num_rx_queues; i++)
503 spin_unlock(&priv->rx_queue[i]->rxlock);
504}
505
506void unlock_tx_qs(struct gfar_private *priv)
507{
508 int i = 0x0;
509
510 for (i = 0; i < priv->num_tx_queues; i++)
511 spin_unlock(&priv->tx_queue[i]->txlock);
512}
513
7f7f5316
AF		 514/* Returns 1 if incoming frames use an FCB */
515static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 516{
cc772ab7
MR		 517 return priv->vlgrp || priv->rx_csum_enable ||
518 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
0bbaf069 519}
bb40dcbb 520
fba4ed03
SG		 521static void free_tx_pointers(struct gfar_private *priv)
522{
523 int i = 0;
524
525 for (i = 0; i < priv->num_tx_queues; i++)
526 kfree(priv->tx_queue[i]);
527}
528
529static void free_rx_pointers(struct gfar_private *priv)
530{
531 int i = 0;
532
533 for (i = 0; i < priv->num_rx_queues; i++)
534 kfree(priv->rx_queue[i]);
535}
536
46ceb60c
SG		 537static void unmap_group_regs(struct gfar_private *priv)
538{
539 int i = 0;
540
541 for (i = 0; i < MAXGROUPS; i++)
542 if (priv->gfargrp[i].regs)
543 iounmap(priv->gfargrp[i].regs);
544}
545
546static void disable_napi(struct gfar_private *priv)
547{
548 int i = 0;
549
550 for (i = 0; i < priv->num_grps; i++)
551 napi_disable(&priv->gfargrp[i].napi);
552}
553
554static void enable_napi(struct gfar_private *priv)
555{
556 int i = 0;
557
558 for (i = 0; i < priv->num_grps; i++)
559 napi_enable(&priv->gfargrp[i].napi);
560}
561
562static int gfar_parse_group(struct device_node *np,
563 struct gfar_private *priv, const char *model)
564{
565 u32 *queue_mask;
46ceb60c 566
7ce97d4f 567 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
46ceb60c
SG		 568 if (!priv->gfargrp[priv->num_grps].regs)
569 return -ENOMEM;
570
571 priv->gfargrp[priv->num_grps].interruptTransmit =
572 irq_of_parse_and_map(np, 0);
573
574 /* If we aren't the FEC we have multiple interrupts */
575 if (model && strcasecmp(model, "FEC")) {
576 priv->gfargrp[priv->num_grps].interruptReceive =
577 irq_of_parse_and_map(np, 1);
578 priv->gfargrp[priv->num_grps].interruptError =
579 irq_of_parse_and_map(np,2);
28cb6ccd
NK		 580 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
581 priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ ||
582 priv->gfargrp[priv->num_grps].interruptError == NO_IRQ)
46ceb60c 583 return -EINVAL;
46ceb60c
SG		 584 }
585
586 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
587 priv->gfargrp[priv->num_grps].priv = priv;
588 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
589 if(priv->mode == MQ_MG_MODE) {
590 queue_mask = (u32 *)of_get_property(np,
591 "fsl,rx-bit-map", NULL);
592 priv->gfargrp[priv->num_grps].rx_bit_map =
593 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
594 queue_mask = (u32 *)of_get_property(np,
595 "fsl,tx-bit-map", NULL);
596 priv->gfargrp[priv->num_grps].tx_bit_map =
597 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
598 } else {
599 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
600 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
601 }
602 priv->num_grps++;
603
604 return 0;
605}
606
2dc11581 607static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 608{
b31a1d8b
AF		 609 const char *model;
610 const char *ctype;
611 const void *mac_addr;
fba4ed03
SG		 612 int err = 0, i;
613 struct net_device *dev = NULL;
614 struct gfar_private *priv = NULL;
61c7a080 615 struct device_node *np = ofdev->dev.of_node;
46ceb60c 616 struct device_node *child = NULL;
4d7902f2
AF		 617 const u32 *stash;
618 const u32 *stash_len;
619 const u32 *stash_idx;
fba4ed03
SG		 620 unsigned int num_tx_qs, num_rx_qs;
621 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 622
623 if (!np || !of_device_is_available(np))
624 return -ENODEV;
625
fba4ed03
SG		 626 /* parse the num of tx and rx queues */
627 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
628 num_tx_qs = tx_queues ? *tx_queues : 1;
629
630 if (num_tx_qs > MAX_TX_QS) {
631 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
632 num_tx_qs, MAX_TX_QS);
633 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
634 return -EINVAL;
635 }
636
637 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
638 num_rx_qs = rx_queues ? *rx_queues : 1;
639
640 if (num_rx_qs > MAX_RX_QS) {
641 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
642 num_tx_qs, MAX_TX_QS);
643 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
644 return -EINVAL;
645 }
646
647 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
648 dev = *pdev;
649 if (NULL == dev)
650 return -ENOMEM;
651
652 priv = netdev_priv(dev);
61c7a080 653 priv->node = ofdev->dev.of_node;
fba4ed03
SG		 654 priv->ndev = dev;
655
fba4ed03 656 priv->num_tx_queues = num_tx_qs;
fe069123 657 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 658 priv->num_rx_queues = num_rx_qs;
46ceb60c 659 priv->num_grps = 0x0;
b31a1d8b
AF		 660
661 model = of_get_property(np, "model", NULL);
662
46ceb60c
SG		 663 for (i = 0; i < MAXGROUPS; i++)
664 priv->gfargrp[i].regs = NULL;
b31a1d8b 665
46ceb60c
SG		 666 /* Parse and initialize group specific information */
667 if (of_device_is_compatible(np, "fsl,etsec2")) {
668 priv->mode = MQ_MG_MODE;
669 for_each_child_of_node(np, child) {
670 err = gfar_parse_group(child, priv, model);
671 if (err)
672 goto err_grp_init;
b31a1d8b 673 }
46ceb60c
SG		 674 } else {
675 priv->mode = SQ_SG_MODE;
676 err = gfar_parse_group(np, priv, model);
677 if(err)
678 goto err_grp_init;
b31a1d8b
AF		 679 }
680
fba4ed03
SG		 681 for (i = 0; i < priv->num_tx_queues; i++)
682 priv->tx_queue[i] = NULL;
683 for (i = 0; i < priv->num_rx_queues; i++)
684 priv->rx_queue[i] = NULL;
685
686 for (i = 0; i < priv->num_tx_queues; i++) {
de47f072
JP		 687 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
688 GFP_KERNEL);
fba4ed03
SG		 689 if (!priv->tx_queue[i]) {
690 err = -ENOMEM;
691 goto tx_alloc_failed;
692 }
693 priv->tx_queue[i]->tx_skbuff = NULL;
694 priv->tx_queue[i]->qindex = i;
695 priv->tx_queue[i]->dev = dev;
696 spin_lock_init(&(priv->tx_queue[i]->txlock));
697 }
698
699 for (i = 0; i < priv->num_rx_queues; i++) {
de47f072
JP		 700 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
701 GFP_KERNEL);
fba4ed03
SG		 702 if (!priv->rx_queue[i]) {
703 err = -ENOMEM;
704 goto rx_alloc_failed;
705 }
706 priv->rx_queue[i]->rx_skbuff = NULL;
707 priv->rx_queue[i]->qindex = i;
708 priv->rx_queue[i]->dev = dev;
709 spin_lock_init(&(priv->rx_queue[i]->rxlock));
710 }
711
712
4d7902f2
AF		 713 stash = of_get_property(np, "bd-stash", NULL);
714
a12f801d 715 if (stash) {
4d7902f2
AF		 716 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
717 priv->bd_stash_en = 1;
718 }
719
720 stash_len = of_get_property(np, "rx-stash-len", NULL);
721
722 if (stash_len)
723 priv->rx_stash_size = *stash_len;
724
725 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
726
727 if (stash_idx)
728 priv->rx_stash_index = *stash_idx;
729
730 if (stash_len || stash_idx)
731 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
732
b31a1d8b
AF		 733 mac_addr = of_get_mac_address(np);
734 if (mac_addr)
735 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
736
737 if (model && !strcasecmp(model, "TSEC"))
738 priv->device_flags =
739 FSL_GIANFAR_DEV_HAS_GIGABIT |
740 FSL_GIANFAR_DEV_HAS_COALESCE |
741 FSL_GIANFAR_DEV_HAS_RMON |
742 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
743 if (model && !strcasecmp(model, "eTSEC"))
744 priv->device_flags =
745 FSL_GIANFAR_DEV_HAS_GIGABIT |
746 FSL_GIANFAR_DEV_HAS_COALESCE |
747 FSL_GIANFAR_DEV_HAS_RMON |
748 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
2c2db48a 749 FSL_GIANFAR_DEV_HAS_PADDING |
b31a1d8b
AF		 750 FSL_GIANFAR_DEV_HAS_CSUM |
751 FSL_GIANFAR_DEV_HAS_VLAN |
752 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
97553f7f
MR		 753 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
754 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 755
756 ctype = of_get_property(np, "phy-connection-type", NULL);
757
758 /* We only care about rgmii-id. The rest are autodetected */
759 if (ctype && !strcmp(ctype, "rgmii-id"))
760 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
761 else
762 priv->interface = PHY_INTERFACE_MODE_MII;
763
764 if (of_get_property(np, "fsl,magic-packet", NULL))
765 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
766
fe192a49 767 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 768
769 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 770 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 771
772 return 0;
773
fba4ed03
SG		 774rx_alloc_failed:
775 free_rx_pointers(priv);
776tx_alloc_failed:
777 free_tx_pointers(priv);
46ceb60c
SG		 778err_grp_init:
779 unmap_group_regs(priv);
fba4ed03 780 free_netdev(dev);
b31a1d8b
AF		 781 return err;
782}
783
cc772ab7
MR		 784static int gfar_hwtstamp_ioctl(struct net_device *netdev,
785 struct ifreq *ifr, int cmd)
786{
787 struct hwtstamp_config config;
788 struct gfar_private *priv = netdev_priv(netdev);
789
790 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
791 return -EFAULT;
792
793 /* reserved for future extensions */
794 if (config.flags)
795 return -EINVAL;
796
f0ee7acf
MR		 797 switch (config.tx_type) {
798 case HWTSTAMP_TX_OFF:
799 priv->hwts_tx_en = 0;
800 break;
801 case HWTSTAMP_TX_ON:
802 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
803 return -ERANGE;
804 priv->hwts_tx_en = 1;
805 break;
806 default:
cc772ab7 807 return -ERANGE;
f0ee7acf 808 }
cc772ab7
MR		 809
810 switch (config.rx_filter) {
811 case HWTSTAMP_FILTER_NONE:
97553f7f
MR		 812 if (priv->hwts_rx_en) {
813 stop_gfar(netdev);
814 priv->hwts_rx_en = 0;
815 startup_gfar(netdev);
816 }
cc772ab7
MR		 817 break;
818 default:
819 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
820 return -ERANGE;
97553f7f
MR		 821 if (!priv->hwts_rx_en) {
822 stop_gfar(netdev);
823 priv->hwts_rx_en = 1;
824 startup_gfar(netdev);
825 }
cc772ab7
MR		 826 config.rx_filter = HWTSTAMP_FILTER_ALL;
827 break;
828 }
829
830 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
831 -EFAULT : 0;
832}
833
0faac9f7
CW		 834/* Ioctl MII Interface */
835static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
836{
837 struct gfar_private *priv = netdev_priv(dev);
838
839 if (!netif_running(dev))
840 return -EINVAL;
841
cc772ab7
MR		 842 if (cmd == SIOCSHWTSTAMP)
843 return gfar_hwtstamp_ioctl(dev, rq, cmd);
844
0faac9f7
CW		 845 if (!priv->phydev)
846 return -ENODEV;
847
28b04113 848 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 849}
850
fba4ed03
SG		 851static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
852{
853 unsigned int new_bit_map = 0x0;
854 int mask = 0x1 << (max_qs - 1), i;
855 for (i = 0; i < max_qs; i++) {
856 if (bit_map & mask)
857 new_bit_map = new_bit_map + (1 << i);
858 mask = mask >> 0x1;
859 }
860 return new_bit_map;
861}
7a8b3372 862
18294ad1
AV		 863static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
864 u32 class)
7a8b3372
SG		 865{
866 u32 rqfpr = FPR_FILER_MASK;
867 u32 rqfcr = 0x0;
868
869 rqfar--;
870 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
871 ftp_rqfpr[rqfar] = rqfpr;
872 ftp_rqfcr[rqfar] = rqfcr;
873 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
874
875 rqfar--;
876 rqfcr = RQFCR_CMP_NOMATCH;
877 ftp_rqfpr[rqfar] = rqfpr;
878 ftp_rqfcr[rqfar] = rqfcr;
879 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
880
881 rqfar--;
882 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
883 rqfpr = class;
884 ftp_rqfcr[rqfar] = rqfcr;
885 ftp_rqfpr[rqfar] = rqfpr;
886 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
887
888 rqfar--;
889 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
890 rqfpr = class;
891 ftp_rqfcr[rqfar] = rqfcr;
892 ftp_rqfpr[rqfar] = rqfpr;
893 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
894
895 return rqfar;
896}
897
898static void gfar_init_filer_table(struct gfar_private *priv)
899{
900 int i = 0x0;
901 u32 rqfar = MAX_FILER_IDX;
902 u32 rqfcr = 0x0;
903 u32 rqfpr = FPR_FILER_MASK;
904
905 /* Default rule */
906 rqfcr = RQFCR_CMP_MATCH;
907 ftp_rqfcr[rqfar] = rqfcr;
908 ftp_rqfpr[rqfar] = rqfpr;
909 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
910
911 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
912 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
913 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
914 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
915 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
916 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
917
85dd08eb 918 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 919 priv->cur_filer_idx = rqfar;
920
921 /* Rest are masked rules */
922 rqfcr = RQFCR_CMP_NOMATCH;
923 for (i = 0; i < rqfar; i++) {
924 ftp_rqfcr[i] = rqfcr;
925 ftp_rqfpr[i] = rqfpr;
926 gfar_write_filer(priv, i, rqfcr, rqfpr);
927 }
928}
929
7d350977
AV		 930static void gfar_detect_errata(struct gfar_private *priv)
931{
932 struct device *dev = &priv->ofdev->dev;
933 unsigned int pvr = mfspr(SPRN_PVR);
934 unsigned int svr = mfspr(SPRN_SVR);
935 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
936 unsigned int rev = svr & 0xffff;
937
938 /* MPC8313 Rev 2.0 and higher; All MPC837x */
939 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
940 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
941 priv->errata |= GFAR_ERRATA_74;
942
deb90eac
AV		 943 /* MPC8313 and MPC837x all rev */
944 if ((pvr == 0x80850010 && mod == 0x80b0) ||
945 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
946 priv->errata |= GFAR_ERRATA_76;
947
511d934f
AV		 948 /* MPC8313 and MPC837x all rev */
949 if ((pvr == 0x80850010 && mod == 0x80b0) ||
950 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
951 priv->errata |= GFAR_ERRATA_A002;
952
7d350977
AV		 953 if (priv->errata)
954 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
955 priv->errata);
956}
957
bb40dcbb
AF		 958/* Set up the ethernet device structure, private data,
959 * and anything else we need before we start */
2dc11581 960static int gfar_probe(struct platform_device *ofdev,
b31a1d8b 961 const struct of_device_id *match)
1da177e4
LT		 962{
963 u32 tempval;
964 struct net_device *dev = NULL;
965 struct gfar_private *priv = NULL;
f4983704 966 struct gfar __iomem *regs = NULL;
46ceb60c 967 int err = 0, i, grp_idx = 0;
c50a5d9a 968 int len_devname;
fba4ed03 969 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 970 u32 isrg = 0;
18294ad1 971 u32 __iomem *baddr;
1da177e4 972
fba4ed03 973 err = gfar_of_init(ofdev, &dev);
1da177e4 974
fba4ed03
SG		 975 if (err)
976 return err;
1da177e4
LT		 977
978 priv = netdev_priv(dev);
4826857f
KG		 979 priv->ndev = dev;
980 priv->ofdev = ofdev;
61c7a080 981 priv->node = ofdev->dev.of_node;
4826857f 982 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 983
d87eb127 984 spin_lock_init(&priv->bflock);
ab939905 985 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 986
b31a1d8b 987 dev_set_drvdata(&ofdev->dev, priv);
46ceb60c 988 regs = priv->gfargrp[0].regs;
1da177e4 989
7d350977
AV		 990 gfar_detect_errata(priv);
991
1da177e4
LT		 992 /* Stop the DMA engine now, in case it was running before */
993 /* (The firmware could have used it, and left it running). */
257d938a 994 gfar_halt(dev);
1da177e4
LT		 995
996 /* Reset MAC layer */
f4983704 997 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 998
b98ac702
AF		 999 /* We need to delay at least 3 TX clocks */
1000 udelay(2);
1001
1da177e4 1002 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 1003 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 1004
1005 /* Initialize MACCFG2. */
7d350977
AV		 1006 tempval = MACCFG2_INIT_SETTINGS;
1007 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1008 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1009 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 1010
1011 /* Initialize ECNTRL */
f4983704 1012 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 1013
1da177e4 1014 /* Set the dev->base_addr to the gfar reg region */
f4983704 1015 dev->base_addr = (unsigned long) regs;
1da177e4 1016
b31a1d8b 1017 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 1018
1019 /* Fill in the dev structure */
1da177e4 1020 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1021 dev->mtu = 1500;
26ccfc37 1022 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1023 dev->ethtool_ops = &gfar_ethtool_ops;
1024
fba4ed03 1025 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c
SG		 1026 for (i = 0; i < priv->num_grps; i++)
1027 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
a12f801d 1028
b31a1d8b 1029 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
0bbaf069 1030 priv->rx_csum_enable = 1;
4669bc90 1031 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
0bbaf069
KG		 1032 } else
1033 priv->rx_csum_enable = 0;
1034
1035 priv->vlgrp = NULL;
1da177e4 1036
26ccfc37 1037 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
0bbaf069 1038 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
0bbaf069 1039
b31a1d8b 1040 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 1041 priv->extended_hash = 1;
1042 priv->hash_width = 9;
1043
f4983704
SG		 1044 priv->hash_regs[0] = &regs->igaddr0;
1045 priv->hash_regs[1] = &regs->igaddr1;
1046 priv->hash_regs[2] = &regs->igaddr2;
1047 priv->hash_regs[3] = &regs->igaddr3;
1048 priv->hash_regs[4] = &regs->igaddr4;
1049 priv->hash_regs[5] = &regs->igaddr5;
1050 priv->hash_regs[6] = &regs->igaddr6;
1051 priv->hash_regs[7] = &regs->igaddr7;
1052 priv->hash_regs[8] = &regs->gaddr0;
1053 priv->hash_regs[9] = &regs->gaddr1;
1054 priv->hash_regs[10] = &regs->gaddr2;
1055 priv->hash_regs[11] = &regs->gaddr3;
1056 priv->hash_regs[12] = &regs->gaddr4;
1057 priv->hash_regs[13] = &regs->gaddr5;
1058 priv->hash_regs[14] = &regs->gaddr6;
1059 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 1060
1061 } else {
1062 priv->extended_hash = 0;
1063 priv->hash_width = 8;
1064
f4983704
SG		 1065 priv->hash_regs[0] = &regs->gaddr0;
1066 priv->hash_regs[1] = &regs->gaddr1;
1067 priv->hash_regs[2] = &regs->gaddr2;
1068 priv->hash_regs[3] = &regs->gaddr3;
1069 priv->hash_regs[4] = &regs->gaddr4;
1070 priv->hash_regs[5] = &regs->gaddr5;
1071 priv->hash_regs[6] = &regs->gaddr6;
1072 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 1073 }
1074
b31a1d8b 1075 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 1076 priv->padding = DEFAULT_PADDING;
1077 else
1078 priv->padding = 0;
1079
cc772ab7
MR		 1080 if (dev->features & NETIF_F_IP_CSUM ||
1081 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
0bbaf069 1082 dev->hard_header_len += GMAC_FCB_LEN;
1da177e4 1083
46ceb60c
SG		 1084 /* Program the isrg regs only if number of grps > 1 */
1085 if (priv->num_grps > 1) {
1086 baddr = &regs->isrg0;
1087 for (i = 0; i < priv->num_grps; i++) {
1088 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1089 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1090 gfar_write(baddr, isrg);
1091 baddr++;
1092 isrg = 0x0;
1093 }
1094 }
1095
fba4ed03 1096 /* Need to reverse the bit maps as bit_map's MSB is q0
984b3f57 1097 * but, for_each_set_bit parses from right to left, which
fba4ed03 1098 * basically reverses the queue numbers */
46ceb60c
SG		 1099 for (i = 0; i< priv->num_grps; i++) {
1100 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1101 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1102 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1103 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1104 }
1105
1106 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1107 * also assign queues to groups */
1108 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1109 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
984b3f57 1110 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
46ceb60c
SG		 1111 priv->num_rx_queues) {
1112 priv->gfargrp[grp_idx].num_rx_queues++;
1113 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1114 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1115 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1116 }
1117 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
984b3f57 1118 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
46ceb60c
SG		 1119 priv->num_tx_queues) {
1120 priv->gfargrp[grp_idx].num_tx_queues++;
1121 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1122 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1123 tqueue = tqueue | (TQUEUE_EN0 >> i);
1124 }
1125 priv->gfargrp[grp_idx].rstat = rstat;
1126 priv->gfargrp[grp_idx].tstat = tstat;
1127 rstat = tstat =0;
fba4ed03 1128 }
fba4ed03
SG		 1129
1130 gfar_write(&regs->rqueue, rqueue);
1131 gfar_write(&regs->tqueue, tqueue);
1132
1da177e4 1133 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1134
a12f801d 1135 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1136 for (i = 0; i < priv->num_tx_queues; i++) {
1137 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1138 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1139 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1140 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1141 }
a12f801d 1142
fba4ed03
SG		 1143 for (i = 0; i < priv->num_rx_queues; i++) {
1144 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1145 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1146 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1147 }
1da177e4 1148
1ccb8389
SG		 1149 /* enable filer if using multiple RX queues*/
1150 if(priv->num_rx_queues > 1)
1151 priv->rx_filer_enable = 1;
0bbaf069
KG		 1152 /* Enable most messages by default */
1153 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1154
d3eab82b
TP		 1155 /* Carrier starts down, phylib will bring it up */
1156 netif_carrier_off(dev);
1157
1da177e4
LT		 1158 err = register_netdev(dev);
1159
1160 if (err) {
1161 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1162 dev->name);
1163 goto register_fail;
1164 }
1165
2884e5cc
AV		 1166 device_init_wakeup(&dev->dev,
1167 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1168
c50a5d9a
DH		 1169 /* fill out IRQ number and name fields */
1170 len_devname = strlen(dev->name);
46ceb60c
SG		 1171 for (i = 0; i < priv->num_grps; i++) {
1172 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1173 len_devname);
1174 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1175 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1176 "_g", sizeof("_g"));
1177 priv->gfargrp[i].int_name_tx[
1178 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1179 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1180 priv->gfargrp[i].int_name_tx)],
1181 "_tx", sizeof("_tx") + 1);
1182
1183 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1184 len_devname);
1185 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1186 "_g", sizeof("_g"));
1187 priv->gfargrp[i].int_name_rx[
1188 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1189 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1190 priv->gfargrp[i].int_name_rx)],
1191 "_rx", sizeof("_rx") + 1);
1192
1193 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1194 len_devname);
1195 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1196 "_g", sizeof("_g"));
1197 priv->gfargrp[i].int_name_er[strlen(
1198 priv->gfargrp[i].int_name_er)] = i+48;
1199 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1200 priv->gfargrp[i].int_name_er)],
1201 "_er", sizeof("_er") + 1);
1202 } else
1203 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1204 }
c50a5d9a 1205
7a8b3372
SG		 1206 /* Initialize the filer table */
1207 gfar_init_filer_table(priv);
1208
7f7f5316
AF		 1209 /* Create all the sysfs files */
1210 gfar_init_sysfs(dev);
1211
1da177e4 1212 /* Print out the device info */
e174961c 1213 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1da177e4
LT		 1214
1215 /* Even more device info helps when determining which kernel */
7f7f5316 1216 /* provided which set of benchmarks. */
1da177e4 1217 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
fba4ed03 1218 for (i = 0; i < priv->num_rx_queues; i++)
ddc01b3b 1219 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
fba4ed03
SG		 1220 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1221 for(i = 0; i < priv->num_tx_queues; i++)
ddc01b3b 1222 printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
fba4ed03 1223 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1224
1225 return 0;
1226
1227register_fail:
46ceb60c 1228 unmap_group_regs(priv);
fba4ed03
SG		 1229 free_tx_pointers(priv);
1230 free_rx_pointers(priv);
fe192a49
GL		 1231 if (priv->phy_node)
1232 of_node_put(priv->phy_node);
1233 if (priv->tbi_node)
1234 of_node_put(priv->tbi_node);
1da177e4 1235 free_netdev(dev);
bb40dcbb 1236 return err;
1da177e4
LT		 1237}
1238
2dc11581 1239static int gfar_remove(struct platform_device *ofdev)
1da177e4 1240{
b31a1d8b 1241 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 1242
fe192a49
GL		 1243 if (priv->phy_node)
1244 of_node_put(priv->phy_node);
1245 if (priv->tbi_node)
1246 of_node_put(priv->tbi_node);
1247
b31a1d8b 1248 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 1249
d9d8e041 1250 unregister_netdev(priv->ndev);
46ceb60c 1251 unmap_group_regs(priv);
4826857f 1252 free_netdev(priv->ndev);
1da177e4
LT		 1253
1254 return 0;
1255}
1256
d87eb127 1257#ifdef CONFIG_PM
be926fc4
AV		 1258
1259static int gfar_suspend(struct device *dev)
d87eb127 1260{
be926fc4
AV		 1261 struct gfar_private *priv = dev_get_drvdata(dev);
1262 struct net_device *ndev = priv->ndev;
46ceb60c 1263 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1264 unsigned long flags;
1265 u32 tempval;
1266
1267 int magic_packet = priv->wol_en &&
b31a1d8b 1268 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1269
be926fc4 1270 netif_device_detach(ndev);
d87eb127 1271
be926fc4 1272 if (netif_running(ndev)) {
fba4ed03
SG		 1273
1274 local_irq_save(flags);
1275 lock_tx_qs(priv);
1276 lock_rx_qs(priv);
d87eb127 1277
be926fc4 1278 gfar_halt_nodisable(ndev);
d87eb127
SW		 1279
1280 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1281 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1282
1283 tempval &= ~MACCFG1_TX_EN;
1284
1285 if (!magic_packet)
1286 tempval &= ~MACCFG1_RX_EN;
1287
f4983704 1288 gfar_write(&regs->maccfg1, tempval);
d87eb127 1289
fba4ed03
SG		 1290 unlock_rx_qs(priv);
1291 unlock_tx_qs(priv);
1292 local_irq_restore(flags);
d87eb127 1293
46ceb60c 1294 disable_napi(priv);
d87eb127
SW		 1295
1296 if (magic_packet) {
1297 /* Enable interrupt on Magic Packet */
f4983704 1298 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1299
1300 /* Enable Magic Packet mode */
f4983704 1301 tempval = gfar_read(&regs->maccfg2);
d87eb127 1302 tempval |= MACCFG2_MPEN;
f4983704 1303 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1304 } else {
1305 phy_stop(priv->phydev);
1306 }
1307 }
1308
1309 return 0;
1310}
1311
be926fc4 1312static int gfar_resume(struct device *dev)
d87eb127 1313{
be926fc4
AV		 1314 struct gfar_private *priv = dev_get_drvdata(dev);
1315 struct net_device *ndev = priv->ndev;
46ceb60c 1316 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1317 unsigned long flags;
1318 u32 tempval;
1319 int magic_packet = priv->wol_en &&
b31a1d8b 1320 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1321
be926fc4
AV		 1322 if (!netif_running(ndev)) {
1323 netif_device_attach(ndev);
d87eb127
SW		 1324 return 0;
1325 }
1326
1327 if (!magic_packet && priv->phydev)
1328 phy_start(priv->phydev);
1329
1330 /* Disable Magic Packet mode, in case something
1331 * else woke us up.
1332 */
fba4ed03
SG		 1333 local_irq_save(flags);
1334 lock_tx_qs(priv);
1335 lock_rx_qs(priv);
d87eb127 1336
f4983704 1337 tempval = gfar_read(&regs->maccfg2);
d87eb127 1338 tempval &= ~MACCFG2_MPEN;
f4983704 1339 gfar_write(&regs->maccfg2, tempval);
d87eb127 1340
be926fc4 1341 gfar_start(ndev);
d87eb127 1342
fba4ed03
SG		 1343 unlock_rx_qs(priv);
1344 unlock_tx_qs(priv);
1345 local_irq_restore(flags);
d87eb127 1346
be926fc4
AV		 1347 netif_device_attach(ndev);
1348
46ceb60c 1349 enable_napi(priv);
be926fc4
AV		 1350
1351 return 0;
1352}
1353
1354static int gfar_restore(struct device *dev)
1355{
1356 struct gfar_private *priv = dev_get_drvdata(dev);
1357 struct net_device *ndev = priv->ndev;
1358
1359 if (!netif_running(ndev))
1360 return 0;
1361
1362 gfar_init_bds(ndev);
1363 init_registers(ndev);
1364 gfar_set_mac_address(ndev);
1365 gfar_init_mac(ndev);
1366 gfar_start(ndev);
1367
1368 priv->oldlink = 0;
1369 priv->oldspeed = 0;
1370 priv->oldduplex = -1;
1371
1372 if (priv->phydev)
1373 phy_start(priv->phydev);
d87eb127 1374
be926fc4 1375 netif_device_attach(ndev);
5ea681d4 1376 enable_napi(priv);
d87eb127
SW		 1377
1378 return 0;
1379}
be926fc4
AV		 1380
1381static struct dev_pm_ops gfar_pm_ops = {
1382 .suspend = gfar_suspend,
1383 .resume = gfar_resume,
1384 .freeze = gfar_suspend,
1385 .thaw = gfar_resume,
1386 .restore = gfar_restore,
1387};
1388
1389#define GFAR_PM_OPS (&gfar_pm_ops)
1390
d87eb127 1391#else
be926fc4
AV		 1392
1393#define GFAR_PM_OPS NULL
be926fc4 1394
d87eb127 1395#endif
1da177e4 1396
e8a2b6a4
AF		 1397/* Reads the controller's registers to determine what interface
1398 * connects it to the PHY.
1399 */
1400static phy_interface_t gfar_get_interface(struct net_device *dev)
1401{
1402 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1403 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1404 u32 ecntrl;
1405
f4983704 1406 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1407
1408 if (ecntrl & ECNTRL_SGMII_MODE)
1409 return PHY_INTERFACE_MODE_SGMII;
1410
1411 if (ecntrl & ECNTRL_TBI_MODE) {
1412 if (ecntrl & ECNTRL_REDUCED_MODE)
1413 return PHY_INTERFACE_MODE_RTBI;
1414 else
1415 return PHY_INTERFACE_MODE_TBI;
1416 }
1417
1418 if (ecntrl & ECNTRL_REDUCED_MODE) {
1419 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1420 return PHY_INTERFACE_MODE_RMII;
7132ab7f 1421 else {
b31a1d8b 1422 phy_interface_t interface = priv->interface;
7132ab7f
AF		 1423
1424 /*
1425 * This isn't autodetected right now, so it must
1426 * be set by the device tree or platform code.
1427 */
1428 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1429 return PHY_INTERFACE_MODE_RGMII_ID;
1430
e8a2b6a4 1431 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1432 }
e8a2b6a4
AF		 1433 }
1434
b31a1d8b 1435 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1436 return PHY_INTERFACE_MODE_GMII;
1437
1438 return PHY_INTERFACE_MODE_MII;
1439}
1440
1441
bb40dcbb
AF		 1442/* Initializes driver's PHY state, and attaches to the PHY.
1443 * Returns 0 on success.
1da177e4
LT		 1444 */
1445static int init_phy(struct net_device *dev)
1446{
1447 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1448 uint gigabit_support =
b31a1d8b 1449 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1450 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1451 phy_interface_t interface;
1da177e4
LT		 1452
1453 priv->oldlink = 0;
1454 priv->oldspeed = 0;
1455 priv->oldduplex = -1;
1456
e8a2b6a4
AF		 1457 interface = gfar_get_interface(dev);
1458
1db780f8
AV		 1459 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1460 interface);
1461 if (!priv->phydev)
1462 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1463 interface);
1464 if (!priv->phydev) {
1465 dev_err(&dev->dev, "could not attach to PHY\n");
1466 return -ENODEV;
fe192a49 1467 }
1da177e4 1468
d3c12873
KJ		 1469 if (interface == PHY_INTERFACE_MODE_SGMII)
1470 gfar_configure_serdes(dev);
1471
bb40dcbb 1472 /* Remove any features not supported by the controller */
fe192a49
GL		 1473 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1474 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1475
1476 return 0;
1da177e4
LT		 1477}
1478
d0313587
PG		 1479/*
1480 * Initialize TBI PHY interface for communicating with the
1481 * SERDES lynx PHY on the chip. We communicate with this PHY
1482 * through the MDIO bus on each controller, treating it as a
1483 * "normal" PHY at the address found in the TBIPA register. We assume
1484 * that the TBIPA register is valid. Either the MDIO bus code will set
1485 * it to a value that doesn't conflict with other PHYs on the bus, or the
1486 * value doesn't matter, as there are no other PHYs on the bus.
1487 */
d3c12873
KJ		 1488static void gfar_configure_serdes(struct net_device *dev)
1489{
1490 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1491 struct phy_device *tbiphy;
1492
1493 if (!priv->tbi_node) {
1494 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1495 "device tree specify a tbi-handle\n");
1496 return;
1497 }
c132419e 1498
fe192a49
GL		 1499 tbiphy = of_phy_find_device(priv->tbi_node);
1500 if (!tbiphy) {
1501 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1502 return;
1503 }
d3c12873 1504
b31a1d8b
AF		 1505 /*
1506 * If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1507 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1508 * everything for us? Resetting it takes the link down and requires
1509 * several seconds for it to come back.
1510 */
fe192a49 1511 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1512 return;
d3c12873 1513
d0313587 1514 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1515 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1516
fe192a49 1517 phy_write(tbiphy, MII_ADVERTISE,
d3c12873
KJ		 1518 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1519 ADVERTISE_1000XPSE_ASYM);
1520
fe192a49 1521 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
d3c12873
KJ		 1522 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1523}
1524
1da177e4
LT		 1525static void init_registers(struct net_device *dev)
1526{
1527 struct gfar_private *priv = netdev_priv(dev);
f4983704 1528 struct gfar __iomem *regs = NULL;
46ceb60c 1529 int i = 0;
1da177e4 1530
46ceb60c
SG		 1531 for (i = 0; i < priv->num_grps; i++) {
1532 regs = priv->gfargrp[i].regs;
1533 /* Clear IEVENT */
1534 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1535
46ceb60c
SG		 1536 /* Initialize IMASK */
1537 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1538 }
1da177e4 1539
46ceb60c 1540 regs = priv->gfargrp[0].regs;
1da177e4 1541 /* Init hash registers to zero */
f4983704
SG		 1542 gfar_write(&regs->igaddr0, 0);
1543 gfar_write(&regs->igaddr1, 0);
1544 gfar_write(&regs->igaddr2, 0);
1545 gfar_write(&regs->igaddr3, 0);
1546 gfar_write(&regs->igaddr4, 0);
1547 gfar_write(&regs->igaddr5, 0);
1548 gfar_write(&regs->igaddr6, 0);
1549 gfar_write(&regs->igaddr7, 0);
1550
1551 gfar_write(&regs->gaddr0, 0);
1552 gfar_write(&regs->gaddr1, 0);
1553 gfar_write(&regs->gaddr2, 0);
1554 gfar_write(&regs->gaddr3, 0);
1555 gfar_write(&regs->gaddr4, 0);
1556 gfar_write(&regs->gaddr5, 0);
1557 gfar_write(&regs->gaddr6, 0);
1558 gfar_write(&regs->gaddr7, 0);
1da177e4 1559
1da177e4 1560 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1561 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1562 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1563
1564 /* Mask off the CAM interrupts */
f4983704
SG		 1565 gfar_write(&regs->rmon.cam1, 0xffffffff);
1566 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1567 }
1568
1569 /* Initialize the max receive buffer length */
f4983704 1570 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1571
1da177e4 1572 /* Initialize the Minimum Frame Length Register */
f4983704 1573 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1574}
1575
511d934f
AV		 1576static int __gfar_is_rx_idle(struct gfar_private *priv)
1577{
1578 u32 res;
1579
1580 /*
1581 * Normaly TSEC should not hang on GRS commands, so we should
1582 * actually wait for IEVENT_GRSC flag.
1583 */
1584 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1585 return 0;
1586
1587 /*
1588 * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1589 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1590 * and the Rx can be safely reset.
1591 */
1592 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1593 res &= 0x7f807f80;
1594 if ((res & 0xffff) == (res >> 16))
1595 return 1;
1596
1597 return 0;
1598}
0bbaf069
KG		 1599
1600/* Halt the receive and transmit queues */
d87eb127 1601static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1602{
1603 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1604 struct gfar __iomem *regs = NULL;
1da177e4 1605 u32 tempval;
46ceb60c 1606 int i = 0;
1da177e4 1607
46ceb60c
SG		 1608 for (i = 0; i < priv->num_grps; i++) {
1609 regs = priv->gfargrp[i].regs;
1610 /* Mask all interrupts */
1611 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1612
46ceb60c
SG		 1613 /* Clear all interrupts */
1614 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1615 }
1da177e4 1616
46ceb60c 1617 regs = priv->gfargrp[0].regs;
1da177e4 1618 /* Stop the DMA, and wait for it to stop */
f4983704 1619 tempval = gfar_read(&regs->dmactrl);
1da177e4
LT		 1620 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1621 != (DMACTRL_GRS | DMACTRL_GTS)) {
511d934f
AV		 1622 int ret;
1623
1da177e4 1624 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1625 gfar_write(&regs->dmactrl, tempval);
1da177e4 1626
511d934f
AV		 1627 do {
1628 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1629 (IEVENT_GRSC | IEVENT_GTSC)) ==
1630 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1631 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1632 ret = __gfar_is_rx_idle(priv);
1633 } while (!ret);
1da177e4 1634 }
d87eb127 1635}
d87eb127
SW		 1636
1637/* Halt the receive and transmit queues */
1638void gfar_halt(struct net_device *dev)
1639{
1640 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1641 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1642 u32 tempval;
1da177e4 1643
2a54adc3
SW		 1644 gfar_halt_nodisable(dev);
1645
1da177e4
LT		 1646 /* Disable Rx and Tx */
1647 tempval = gfar_read(&regs->maccfg1);
1648 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1649 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1650}
1651
46ceb60c
SG		 1652static void free_grp_irqs(struct gfar_priv_grp *grp)
1653{
1654 free_irq(grp->interruptError, grp);
1655 free_irq(grp->interruptTransmit, grp);
1656 free_irq(grp->interruptReceive, grp);
1657}
1658
0bbaf069
KG		 1659void stop_gfar(struct net_device *dev)
1660{
1661 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1662 unsigned long flags;
46ceb60c 1663 int i;
0bbaf069 1664
bb40dcbb
AF		 1665 phy_stop(priv->phydev);
1666
a12f801d 1667
0bbaf069 1668 /* Lock it down */
fba4ed03
SG		 1669 local_irq_save(flags);
1670 lock_tx_qs(priv);
1671 lock_rx_qs(priv);
0bbaf069 1672
0bbaf069 1673 gfar_halt(dev);
1da177e4 1674
fba4ed03
SG		 1675 unlock_rx_qs(priv);
1676 unlock_tx_qs(priv);
1677 local_irq_restore(flags);
1da177e4
LT		 1678
1679 /* Free the IRQs */
b31a1d8b 1680 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1681 for (i = 0; i < priv->num_grps; i++)
1682 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1683 } else {
46ceb60c
SG		 1684 for (i = 0; i < priv->num_grps; i++)
1685 free_irq(priv->gfargrp[i].interruptTransmit,
1686 &priv->gfargrp[i]);
1da177e4
LT		 1687 }
1688
1689 free_skb_resources(priv);
1da177e4
LT		 1690}
1691
fba4ed03 1692static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1693{
1da177e4 1694 struct txbd8 *txbdp;
fba4ed03 1695 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1696 int i, j;
1da177e4 1697
a12f801d 1698 txbdp = tx_queue->tx_bd_base;
1da177e4 1699
a12f801d
SG		 1700 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1701 if (!tx_queue->tx_skbuff[i])
4669bc90 1702 continue;
1da177e4 1703
4826857f 1704 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90
DH		 1705 txbdp->length, DMA_TO_DEVICE);
1706 txbdp->lstatus = 0;
fba4ed03
SG		 1707 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1708 j++) {
4669bc90 1709 txbdp++;
4826857f 1710 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90 1711 txbdp->length, DMA_TO_DEVICE);
1da177e4 1712 }
ad5da7ab 1713 txbdp++;
a12f801d
SG		 1714 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1715 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1716 }
a12f801d 1717 kfree(tx_queue->tx_skbuff);
fba4ed03 1718}
1da177e4 1719
fba4ed03
SG		 1720static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1721{
1722 struct rxbd8 *rxbdp;
1723 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1724 int i;
1da177e4 1725
fba4ed03 1726 rxbdp = rx_queue->rx_bd_base;
1da177e4 1727
a12f801d
SG		 1728 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1729 if (rx_queue->rx_skbuff[i]) {
fba4ed03
SG		 1730 dma_unmap_single(&priv->ofdev->dev,
1731 rxbdp->bufPtr, priv->rx_buffer_size,
e69edd21 1732 DMA_FROM_DEVICE);
a12f801d
SG		 1733 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1734 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1735 }
e69edd21
AV		 1736 rxbdp->lstatus = 0;
1737 rxbdp->bufPtr = 0;
1738 rxbdp++;
1da177e4 1739 }
a12f801d 1740 kfree(rx_queue->rx_skbuff);
fba4ed03 1741}
e69edd21 1742
fba4ed03
SG		 1743/* If there are any tx skbs or rx skbs still around, free them.
1744 * Then free tx_skbuff and rx_skbuff */
1745static void free_skb_resources(struct gfar_private *priv)
1746{
1747 struct gfar_priv_tx_q *tx_queue = NULL;
1748 struct gfar_priv_rx_q *rx_queue = NULL;
1749 int i;
1750
1751 /* Go through all the buffer descriptors and free their data buffers */
1752 for (i = 0; i < priv->num_tx_queues; i++) {
1753 tx_queue = priv->tx_queue[i];
7c0d10d3 1754 if(tx_queue->tx_skbuff)
fba4ed03
SG		 1755 free_skb_tx_queue(tx_queue);
1756 }
1757
1758 for (i = 0; i < priv->num_rx_queues; i++) {
1759 rx_queue = priv->rx_queue[i];
7c0d10d3 1760 if(rx_queue->rx_skbuff)
fba4ed03
SG		 1761 free_skb_rx_queue(rx_queue);
1762 }
1763
1764 dma_free_coherent(&priv->ofdev->dev,
1765 sizeof(struct txbd8) * priv->total_tx_ring_size +
1766 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1767 priv->tx_queue[0]->tx_bd_base,
1768 priv->tx_queue[0]->tx_bd_dma_base);
7df9c43f 1769 skb_queue_purge(&priv->rx_recycle);
1da177e4
LT		 1770}
1771
0bbaf069
KG		 1772void gfar_start(struct net_device *dev)
1773{
1774 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1775 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1776 u32 tempval;
46ceb60c 1777 int i = 0;
0bbaf069
KG		 1778
1779 /* Enable Rx and Tx in MACCFG1 */
1780 tempval = gfar_read(&regs->maccfg1);
1781 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1782 gfar_write(&regs->maccfg1, tempval);
1783
1784 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1785 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1786 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1787 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1788
0bbaf069 1789 /* Make sure we aren't stopped */
f4983704 1790 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1791 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1792 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1793
46ceb60c
SG		 1794 for (i = 0; i < priv->num_grps; i++) {
1795 regs = priv->gfargrp[i].regs;
1796 /* Clear THLT/RHLT, so that the DMA starts polling now */
1797 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1798 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1799 /* Unmask the interrupts we look for */
1800 gfar_write(&regs->imask, IMASK_DEFAULT);
1801 }
12dea57b 1802
1ae5dc34 1803 dev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1804}
1805
46ceb60c 1806void gfar_configure_coalescing(struct gfar_private *priv,
18294ad1 1807 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1808{
46ceb60c 1809 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1810 u32 __iomem *baddr;
46ceb60c 1811 int i = 0;
1da177e4 1812
46ceb60c
SG		 1813 /* Backward compatible case ---- even if we enable
1814 * multiple queues, there's only single reg to program
1815 */
1816 gfar_write(&regs->txic, 0);
1817 if(likely(priv->tx_queue[0]->txcoalescing))
1818 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1da177e4 1819
46ceb60c
SG		 1820 gfar_write(&regs->rxic, 0);
1821 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1822 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
815b97c6 1823
46ceb60c
SG		 1824 if (priv->mode == MQ_MG_MODE) {
1825 baddr = &regs->txic0;
984b3f57 1826 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
46ceb60c
SG		 1827 if (likely(priv->tx_queue[i]->txcoalescing)) {
1828 gfar_write(baddr + i, 0);
1829 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1830 }
1831 }
1832
1833 baddr = &regs->rxic0;
984b3f57 1834 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
46ceb60c
SG		 1835 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1836 gfar_write(baddr + i, 0);
1837 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1838 }
1839 }
1840 }
1841}
1842
1843static int register_grp_irqs(struct gfar_priv_grp *grp)
1844{
1845 struct gfar_private *priv = grp->priv;
1846 struct net_device *dev = priv->ndev;
1847 int err;
1da177e4 1848
1da177e4
LT		 1849 /* If the device has multiple interrupts, register for
1850 * them. Otherwise, only register for the one */
b31a1d8b 1851 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1852 /* Install our interrupt handlers for Error,
1da177e4 1853 * Transmit, and Receive */
46ceb60c
SG		 1854 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1855 grp->int_name_er,grp)) < 0) {
0bbaf069 1856 if (netif_msg_intr(priv))
46ceb60c
SG		 1857 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1858 dev->name, grp->interruptError);
1859
2145f1af 1860 goto err_irq_fail;
1da177e4
LT		 1861 }
1862
46ceb60c
SG		 1863 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1864 0, grp->int_name_tx, grp)) < 0) {
0bbaf069 1865 if (netif_msg_intr(priv))
46ceb60c
SG		 1866 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1867 dev->name, grp->interruptTransmit);
1da177e4
LT		 1868 goto tx_irq_fail;
1869 }
1870
46ceb60c
SG		 1871 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1872 grp->int_name_rx, grp)) < 0) {
0bbaf069 1873 if (netif_msg_intr(priv))
46ceb60c
SG		 1874 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1875 dev->name, grp->interruptReceive);
1da177e4
LT		 1876 goto rx_irq_fail;
1877 }
1878 } else {
46ceb60c
SG		 1879 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1880 grp->int_name_tx, grp)) < 0) {
0bbaf069 1881 if (netif_msg_intr(priv))
46ceb60c
SG		 1882 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1883 dev->name, grp->interruptTransmit);
1da177e4
LT		 1884 goto err_irq_fail;
1885 }
1886 }
1887
46ceb60c
SG		 1888 return 0;
1889
1890rx_irq_fail:
1891 free_irq(grp->interruptTransmit, grp);
1892tx_irq_fail:
1893 free_irq(grp->interruptError, grp);
1894err_irq_fail:
1895 return err;
1896
1897}
1898
1899/* Bring the controller up and running */
1900int startup_gfar(struct net_device *ndev)
1901{
1902 struct gfar_private *priv = netdev_priv(ndev);
1903 struct gfar __iomem *regs = NULL;
1904 int err, i, j;
1905
1906 for (i = 0; i < priv->num_grps; i++) {
1907 regs= priv->gfargrp[i].regs;
1908 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1909 }
1910
1911 regs= priv->gfargrp[0].regs;
1912 err = gfar_alloc_skb_resources(ndev);
1913 if (err)
1914 return err;
1915
1916 gfar_init_mac(ndev);
1917
1918 for (i = 0; i < priv->num_grps; i++) {
1919 err = register_grp_irqs(&priv->gfargrp[i]);
1920 if (err) {
1921 for (j = 0; j < i; j++)
1922 free_grp_irqs(&priv->gfargrp[j]);
1923 goto irq_fail;
1924 }
1925 }
1926
7f7f5316 1927 /* Start the controller */
ccc05c6e 1928 gfar_start(ndev);
1da177e4 1929
826aa4a0
AV		 1930 phy_start(priv->phydev);
1931
46ceb60c
SG		 1932 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1933
1da177e4
LT		 1934 return 0;
1935
46ceb60c 1936irq_fail:
e69edd21 1937 free_skb_resources(priv);
1da177e4
LT		 1938 return err;
1939}
1940
1941/* Called when something needs to use the ethernet device */
1942/* Returns 0 for success. */
1943static int gfar_enet_open(struct net_device *dev)
1944{
94e8cc35 1945 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1946 int err;
1947
46ceb60c 1948 enable_napi(priv);
bea3348e 1949
0fd56bb5
AF		 1950 skb_queue_head_init(&priv->rx_recycle);
1951
1da177e4
LT		 1952 /* Initialize a bunch of registers */
1953 init_registers(dev);
1954
1955 gfar_set_mac_address(dev);
1956
1957 err = init_phy(dev);
1958
a12f801d 1959 if (err) {
46ceb60c 1960 disable_napi(priv);
1da177e4 1961 return err;
bea3348e 1962 }
1da177e4
LT		 1963
1964 err = startup_gfar(dev);
db0e8e3f 1965 if (err) {
46ceb60c 1966 disable_napi(priv);
db0e8e3f
AV		 1967 return err;
1968 }
1da177e4 1969
fba4ed03 1970 netif_tx_start_all_queues(dev);
1da177e4 1971
2884e5cc
AV		 1972 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1973
1da177e4
LT		 1974 return err;
1975}
1976
54dc79fe 1977static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1978{
54dc79fe 1979 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1980
1981 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1982
0bbaf069
KG		 1983 return fcb;
1984}
1985
1986static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1987{
7f7f5316 1988 u8 flags = 0;
0bbaf069
KG		 1989
1990 /* If we're here, it's a IP packet with a TCP or UDP
1991 * payload. We set it to checksum, using a pseudo-header
1992 * we provide
1993 */
7f7f5316 1994 flags = TXFCB_DEFAULT;
0bbaf069 1995
7f7f5316
AF		 1996 /* Tell the controller what the protocol is */
1997 /* And provide the already calculated phcs */
eddc9ec5 1998 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 1999 flags |= TXFCB_UDP;
4bedb452 2000 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 2001 } else
8da32de5 2002 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 2003
2004 /* l3os is the distance between the start of the
2005 * frame (skb->data) and the start of the IP hdr.
2006 * l4os is the distance between the start of the
2007 * l3 hdr and the l4 hdr */
bbe735e4 2008 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
cfe1fc77 2009 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2010
7f7f5316 2011 fcb->flags = flags;
0bbaf069
KG		 2012}
2013
7f7f5316 2014void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2015{
7f7f5316 2016 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 2017 fcb->vlctl = vlan_tx_tag_get(skb);
2018}
2019
4669bc90
DH		 2020static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2021 struct txbd8 *base, int ring_size)
2022{
2023 struct txbd8 *new_bd = bdp + stride;
2024
2025 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2026}
2027
2028static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2029 int ring_size)
2030{
2031 return skip_txbd(bdp, 1, base, ring_size);
2032}
2033
1da177e4
LT		 2034/* This is called by the kernel when a frame is ready for transmission. */
2035/* It is pointed to by the dev->hard_start_xmit function pointer */
2036static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2037{
2038 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2039 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2040 struct netdev_queue *txq;
f4983704 2041 struct gfar __iomem *regs = NULL;
0bbaf069 2042 struct txfcb *fcb = NULL;
f0ee7acf 2043 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2044 u32 lstatus;
f0ee7acf 2045 int i, rq = 0, do_tstamp = 0;
4669bc90 2046 u32 bufaddr;
fef6108d 2047 unsigned long flags;
f0ee7acf 2048 unsigned int nr_frags, nr_txbds, length;
fba4ed03 2049
deb90eac
AV		 2050 /*
2051 * TOE=1 frames larger than 2500 bytes may see excess delays
2052 * before start of transmission.
2053 */
2054 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2055 skb->ip_summed == CHECKSUM_PARTIAL &&
2056 skb->len > 2500)) {
2057 int ret;
2058
2059 ret = skb_checksum_help(skb);
2060 if (ret)
2061 return ret;
2062 }
2063
fba4ed03
SG		 2064 rq = skb->queue_mapping;
2065 tx_queue = priv->tx_queue[rq];
2066 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2067 base = tx_queue->tx_bd_base;
46ceb60c 2068 regs = tx_queue->grp->regs;
f0ee7acf
MR		 2069
2070 /* check if time stamp should be generated */
2244d07b
OH		 2071 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2072 priv->hwts_tx_en))
f0ee7acf 2073 do_tstamp = 1;
4669bc90 2074
5b28beaf
LY		 2075 /* make space for additional header when fcb is needed */
2076 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
eab6d18d 2077 vlan_tx_tag_present(skb) ||
f0ee7acf 2078 unlikely(do_tstamp)) &&
5b28beaf 2079 (skb_headroom(skb) < GMAC_FCB_LEN)) {
54dc79fe
SH		 2080 struct sk_buff *skb_new;
2081
2082 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2083 if (!skb_new) {
2084 dev->stats.tx_errors++;
bd14ba84 2085 kfree_skb(skb);
54dc79fe
SH		 2086 return NETDEV_TX_OK;
2087 }
2088 kfree_skb(skb);
2089 skb = skb_new;
2090 }
2091
4669bc90
DH		 2092 /* total number of fragments in the SKB */
2093 nr_frags = skb_shinfo(skb)->nr_frags;
2094
f0ee7acf
MR		 2095 /* calculate the required number of TxBDs for this skb */
2096 if (unlikely(do_tstamp))
2097 nr_txbds = nr_frags + 2;
2098 else
2099 nr_txbds = nr_frags + 1;
2100
4669bc90 2101 /* check if there is space to queue this packet */
f0ee7acf 2102 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2103 /* no space, stop the queue */
fba4ed03 2104 netif_tx_stop_queue(txq);
4669bc90 2105 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2106 return NETDEV_TX_BUSY;
2107 }
1da177e4
LT		 2108
2109 /* Update transmit stats */
a7f38041
SG		 2110 txq->tx_bytes += skb->len;
2111 txq->tx_packets ++;
1da177e4 2112
a12f801d 2113 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2114 lstatus = txbdp->lstatus;
2115
2116 /* Time stamp insertion requires one additional TxBD */
2117 if (unlikely(do_tstamp))
2118 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2119 tx_queue->tx_ring_size);
1da177e4 2120
4669bc90 2121 if (nr_frags == 0) {
f0ee7acf
MR		 2122 if (unlikely(do_tstamp))
2123 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2124 TXBD_INTERRUPT);
2125 else
2126 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2127 } else {
2128 /* Place the fragment addresses and lengths into the TxBDs */
2129 for (i = 0; i < nr_frags; i++) {
2130 /* Point at the next BD, wrapping as needed */
a12f801d 2131 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2132
2133 length = skb_shinfo(skb)->frags[i].size;
2134
2135 lstatus = txbdp->lstatus | length |
2136 BD_LFLAG(TXBD_READY);
2137
2138 /* Handle the last BD specially */
2139 if (i == nr_frags - 1)
2140 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2141
4826857f 2142 bufaddr = dma_map_page(&priv->ofdev->dev,
4669bc90
DH		 2143 skb_shinfo(skb)->frags[i].page,
2144 skb_shinfo(skb)->frags[i].page_offset,
2145 length,
2146 DMA_TO_DEVICE);
2147
2148 /* set the TxBD length and buffer pointer */
2149 txbdp->bufPtr = bufaddr;
2150 txbdp->lstatus = lstatus;
2151 }
2152
2153 lstatus = txbdp_start->lstatus;
2154 }
1da177e4 2155
0bbaf069 2156 /* Set up checksumming */
12dea57b 2157 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe
SH		 2158 fcb = gfar_add_fcb(skb);
2159 lstatus |= BD_LFLAG(TXBD_TOE);
2160 gfar_tx_checksum(skb, fcb);
0bbaf069
KG		 2161 }
2162
eab6d18d 2163 if (vlan_tx_tag_present(skb)) {
54dc79fe
SH		 2164 if (unlikely(NULL == fcb)) {
2165 fcb = gfar_add_fcb(skb);
5a5efed4 2166 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 2167 }
54dc79fe
SH		 2168
2169 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 2170 }
2171
f0ee7acf
MR		 2172 /* Setup tx hardware time stamping if requested */
2173 if (unlikely(do_tstamp)) {
2244d07b 2174 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf
MR		 2175 if (fcb == NULL)
2176 fcb = gfar_add_fcb(skb);
2177 fcb->ptp = 1;
2178 lstatus |= BD_LFLAG(TXBD_TOE);
2179 }
2180
4826857f 2181 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
4669bc90 2182 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2183
f0ee7acf
MR		 2184 /*
2185 * If time stamping is requested one additional TxBD must be set up. The
2186 * first TxBD points to the FCB and must have a data length of
2187 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2188 * the full frame length.
2189 */
2190 if (unlikely(do_tstamp)) {
2191 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2192 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2193 (skb_headlen(skb) - GMAC_FCB_LEN);
2194 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2195 } else {
2196 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2197 }
1da177e4 2198
a3bc1f11
AV		 2199 /*
2200 * We can work in parallel with gfar_clean_tx_ring(), except
2201 * when modifying num_txbdfree. Note that we didn't grab the lock
2202 * when we were reading the num_txbdfree and checking for available
2203 * space, that's because outside of this function it can only grow,
2204 * and once we've got needed space, it cannot suddenly disappear.
2205 *
2206 * The lock also protects us from gfar_error(), which can modify
2207 * regs->tstat and thus retrigger the transfers, which is why we
2208 * also must grab the lock before setting ready bit for the first
2209 * to be transmitted BD.
2210 */
2211 spin_lock_irqsave(&tx_queue->txlock, flags);
2212
4669bc90
DH		 2213 /*
2214 * The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2215 * semantics (it requires synchronization between cacheable and
2216 * uncacheable mappings, which eieio doesn't provide and which we
2217 * don't need), thus requiring a more expensive sync instruction. At
2218 * some point, the set of architecture-independent barrier functions
2219 * should be expanded to include weaker barriers.
2220 */
3b6330ce 2221 eieio();
7f7f5316 2222
4669bc90
DH		 2223 txbdp_start->lstatus = lstatus;
2224
0eddba52
AV		 2225 eieio(); /* force lstatus write before tx_skbuff */
2226
2227 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2228
4669bc90
DH		 2229 /* Update the current skb pointer to the next entry we will use
2230 * (wrapping if necessary) */
a12f801d
SG		 2231 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2232 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2233
a12f801d 2234 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2235
2236 /* reduce TxBD free count */
f0ee7acf 2237 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2238
2239 /* If the next BD still needs to be cleaned up, then the bds
2240 are full. We need to tell the kernel to stop sending us stuff. */
a12f801d 2241 if (!tx_queue->num_txbdfree) {
fba4ed03 2242 netif_tx_stop_queue(txq);
1da177e4 2243
09f75cd7 2244 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2245 }
2246
1da177e4 2247 /* Tell the DMA to go go go */
fba4ed03 2248 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2249
2250 /* Unlock priv */
a12f801d 2251 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2252
54dc79fe 2253 return NETDEV_TX_OK;
1da177e4
LT		 2254}
2255
2256/* Stops the kernel queue, and halts the controller */
2257static int gfar_close(struct net_device *dev)
2258{
2259 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2260
46ceb60c 2261 disable_napi(priv);
bea3348e 2262
ab939905 2263 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2264 stop_gfar(dev);
2265
bb40dcbb
AF		 2266 /* Disconnect from the PHY */
2267 phy_disconnect(priv->phydev);
2268 priv->phydev = NULL;
1da177e4 2269
fba4ed03 2270 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2271
2272 return 0;
2273}
2274
1da177e4 2275/* Changes the mac address if the controller is not running. */
f162b9d5 2276static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2277{
7f7f5316 2278 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2279
2280 return 0;
2281}
2282
2283
0bbaf069
KG		 2284/* Enables and disables VLAN insertion/extraction */
2285static void gfar_vlan_rx_register(struct net_device *dev,
2286 struct vlan_group *grp)
2287{
2288 struct gfar_private *priv = netdev_priv(dev);
f4983704 2289 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2290 unsigned long flags;
2291 u32 tempval;
2292
46ceb60c 2293 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2294 local_irq_save(flags);
2295 lock_rx_qs(priv);
0bbaf069 2296
cd1f55a5 2297 priv->vlgrp = grp;
0bbaf069
KG		 2298
2299 if (grp) {
2300 /* Enable VLAN tag insertion */
f4983704 2301 tempval = gfar_read(&regs->tctrl);
0bbaf069
KG		 2302 tempval |= TCTRL_VLINS;
2303
f4983704 2304 gfar_write(&regs->tctrl, tempval);
6aa20a22 2305
0bbaf069 2306 /* Enable VLAN tag extraction */
f4983704 2307 tempval = gfar_read(&regs->rctrl);
77ecaf2d 2308 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
f4983704 2309 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2310 } else {
2311 /* Disable VLAN tag insertion */
f4983704 2312 tempval = gfar_read(&regs->tctrl);
0bbaf069 2313 tempval &= ~TCTRL_VLINS;
f4983704 2314 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2315
2316 /* Disable VLAN tag extraction */
f4983704 2317 tempval = gfar_read(&regs->rctrl);
0bbaf069 2318 tempval &= ~RCTRL_VLEX;
77ecaf2d
DH		 2319 /* If parse is no longer required, then disable parser */
2320 if (tempval & RCTRL_REQ_PARSER)
2321 tempval |= RCTRL_PRSDEP_INIT;
2322 else
2323 tempval &= ~RCTRL_PRSDEP_INIT;
f4983704 2324 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2325 }
2326
77ecaf2d
DH		 2327 gfar_change_mtu(dev, dev->mtu);
2328
fba4ed03
SG		 2329 unlock_rx_qs(priv);
2330 local_irq_restore(flags);
0bbaf069
KG		 2331}
2332
1da177e4
LT		 2333static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2334{
2335 int tempsize, tempval;
2336 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2337 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2338 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2339 int frame_size = new_mtu + ETH_HLEN;
2340
77ecaf2d 2341 if (priv->vlgrp)
faa89577 2342 frame_size += VLAN_HLEN;
0bbaf069 2343
1da177e4 2344 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
0bbaf069
KG		 2345 if (netif_msg_drv(priv))
2346 printk(KERN_ERR "%s: Invalid MTU setting\n",
2347 dev->name);
1da177e4
LT		 2348 return -EINVAL;
2349 }
2350
77ecaf2d
DH		 2351 if (gfar_uses_fcb(priv))
2352 frame_size += GMAC_FCB_LEN;
2353
2354 frame_size += priv->padding;
2355
1da177e4
LT		 2356 tempsize =
2357 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2358 INCREMENTAL_BUFFER_SIZE;
2359
2360 /* Only stop and start the controller if it isn't already
7f7f5316 2361 * stopped, and we changed something */
1da177e4
LT		 2362 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2363 stop_gfar(dev);
2364
2365 priv->rx_buffer_size = tempsize;
2366
2367 dev->mtu = new_mtu;
2368
f4983704
SG		 2369 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2370 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2371
2372 /* If the mtu is larger than the max size for standard
2373 * ethernet frames (ie, a jumbo frame), then set maccfg2
2374 * to allow huge frames, and to check the length */
f4983704 2375 tempval = gfar_read(&regs->maccfg2);
1da177e4 2376
7d350977
AV		 2377 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2378 gfar_has_errata(priv, GFAR_ERRATA_74))
1da177e4
LT		 2379 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2380 else
2381 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2382
f4983704 2383 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2384
2385 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2386 startup_gfar(dev);
2387
2388 return 0;
2389}
2390
ab939905 2391/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2392 * transmitted after a set amount of time.
2393 * For now, assume that clearing out all the structures, and
ab939905
SS		 2394 * starting over will fix the problem.
2395 */
2396static void gfar_reset_task(struct work_struct *work)
1da177e4 2397{
ab939905
SS		 2398 struct gfar_private *priv = container_of(work, struct gfar_private,
2399 reset_task);
4826857f 2400 struct net_device *dev = priv->ndev;
1da177e4
LT		 2401
2402 if (dev->flags & IFF_UP) {
fba4ed03 2403 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2404 stop_gfar(dev);
2405 startup_gfar(dev);
fba4ed03 2406 netif_tx_start_all_queues(dev);
1da177e4
LT		 2407 }
2408
263ba320 2409 netif_tx_schedule_all(dev);
1da177e4
LT		 2410}
2411
ab939905
SS		 2412static void gfar_timeout(struct net_device *dev)
2413{
2414 struct gfar_private *priv = netdev_priv(dev);
2415
2416 dev->stats.tx_errors++;
2417 schedule_work(&priv->reset_task);
2418}
2419
acbc0f03
EL		 2420static void gfar_align_skb(struct sk_buff *skb)
2421{
2422 /* We need the data buffer to be aligned properly. We will reserve
2423 * as many bytes as needed to align the data properly
2424 */
2425 skb_reserve(skb, RXBUF_ALIGNMENT -
2426 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2427}
2428
1da177e4 2429/* Interrupt Handler for Transmit complete */
a12f801d 2430static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2431{
a12f801d 2432 struct net_device *dev = tx_queue->dev;
d080cd63 2433 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2434 struct gfar_priv_rx_q *rx_queue = NULL;
f0ee7acf 2435 struct txbd8 *bdp, *next = NULL;
4669bc90 2436 struct txbd8 *lbdp = NULL;
a12f801d 2437 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2438 struct sk_buff *skb;
2439 int skb_dirtytx;
a12f801d 2440 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2441 int frags = 0, nr_txbds = 0;
4669bc90 2442 int i;
d080cd63 2443 int howmany = 0;
4669bc90 2444 u32 lstatus;
f0ee7acf 2445 size_t buflen;
1da177e4 2446
fba4ed03 2447 rx_queue = priv->rx_queue[tx_queue->qindex];
a12f801d
SG		 2448 bdp = tx_queue->dirty_tx;
2449 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2450
a12f801d 2451 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2452 unsigned long flags;
2453
4669bc90 2454 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf
MR		 2455
2456 /*
2457 * When time stamping, one additional TxBD must be freed.
2458 * Also, we need to dma_unmap_single() the TxPAL.
2459 */
2244d07b 2460 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2461 nr_txbds = frags + 2;
2462 else
2463 nr_txbds = frags + 1;
2464
2465 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2466
4669bc90 2467 lstatus = lbdp->lstatus;
1da177e4 2468
4669bc90
DH		 2469 /* Only clean completed frames */
2470 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2471 (lstatus & BD_LENGTH_MASK))
2472 break;
2473
2244d07b 2474 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2475 next = next_txbd(bdp, base, tx_ring_size);
2476 buflen = next->length + GMAC_FCB_LEN;
2477 } else
2478 buflen = bdp->length;
2479
2480 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2481 buflen, DMA_TO_DEVICE);
2482
2244d07b 2483 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2484 struct skb_shared_hwtstamps shhwtstamps;
2485 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2486 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2487 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2488 skb_tstamp_tx(skb, &shhwtstamps);
2489 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2490 bdp = next;
2491 }
81183059 2492
4669bc90
DH		 2493 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2494 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2495
4669bc90 2496 for (i = 0; i < frags; i++) {
4826857f 2497 dma_unmap_page(&priv->ofdev->dev,
4669bc90
DH		 2498 bdp->bufPtr,
2499 bdp->length,
2500 DMA_TO_DEVICE);
2501 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2502 bdp = next_txbd(bdp, base, tx_ring_size);
2503 }
1da177e4 2504
0fd56bb5
AF		 2505 /*
2506 * If there's room in the queue (limit it to rx_buffer_size)
2507 * we add this skb back into the pool, if it's the right size
2508 */
a12f801d 2509 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
0fd56bb5 2510 skb_recycle_check(skb, priv->rx_buffer_size +
acbc0f03
EL		 2511 RXBUF_ALIGNMENT)) {
2512 gfar_align_skb(skb);
cd0ea241 2513 skb_queue_head(&priv->rx_recycle, skb);
acbc0f03 2514 } else
0fd56bb5
AF		 2515 dev_kfree_skb_any(skb);
2516
a12f801d 2517 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2518
4669bc90
DH		 2519 skb_dirtytx = (skb_dirtytx + 1) &
2520 TX_RING_MOD_MASK(tx_ring_size);
2521
2522 howmany++;
a3bc1f11 2523 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2524 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2525 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2526 }
1da177e4 2527
4669bc90 2528 /* If we freed a buffer, we can restart transmission, if necessary */
fba4ed03
SG		 2529 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2530 netif_wake_subqueue(dev, tx_queue->qindex);
1da177e4 2531
4669bc90 2532 /* Update dirty indicators */
a12f801d
SG		 2533 tx_queue->skb_dirtytx = skb_dirtytx;
2534 tx_queue->dirty_tx = bdp;
1da177e4 2535
d080cd63
DH		 2536 return howmany;
2537}
2538
f4983704 2539static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2540{
a6d0b91a
AV		 2541 unsigned long flags;
2542
fba4ed03
SG		 2543 spin_lock_irqsave(&gfargrp->grplock, flags);
2544 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2545 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2546 __napi_schedule(&gfargrp->napi);
8707bdd4
JP		 2547 } else {
2548 /*
2549 * Clear IEVENT, so interrupts aren't called again
2550 * because of the packets that have already arrived.
2551 */
f4983704 2552 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2553 }
fba4ed03 2554 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2555
8c7396ae 2556}
1da177e4 2557
8c7396ae 2558/* Interrupt Handler for Transmit complete */
f4983704 2559static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2560{
f4983704 2561 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2562 return IRQ_HANDLED;
2563}
2564
a12f801d 2565static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6
AF		 2566 struct sk_buff *skb)
2567{
a12f801d 2568 struct net_device *dev = rx_queue->dev;
815b97c6 2569 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2570 dma_addr_t buf;
815b97c6 2571
8a102fe0
AV		 2572 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2573 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2574 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2575}
2576
acbc0f03 2577static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2578{
2579 struct gfar_private *priv = netdev_priv(dev);
2580 struct sk_buff *skb = NULL;
1da177e4 2581
acbc0f03 2582 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2583 if (!skb)
1da177e4
LT		 2584 return NULL;
2585
acbc0f03 2586 gfar_align_skb(skb);
7f7f5316 2587
acbc0f03
EL		 2588 return skb;
2589}
2590
2591struct sk_buff * gfar_new_skb(struct net_device *dev)
2592{
2593 struct gfar_private *priv = netdev_priv(dev);
2594 struct sk_buff *skb = NULL;
2595
cd0ea241 2596 skb = skb_dequeue(&priv->rx_recycle);
acbc0f03
EL		 2597 if (!skb)
2598 skb = gfar_alloc_skb(dev);
1da177e4 2599
1da177e4
LT		 2600 return skb;
2601}
2602
298e1a9e 2603static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2604{
298e1a9e 2605 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2606 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2607 struct gfar_extra_stats *estats = &priv->extra_stats;
2608
2609 /* If the packet was truncated, none of the other errors
2610 * matter */
2611 if (status & RXBD_TRUNCATED) {
2612 stats->rx_length_errors++;
2613
2614 estats->rx_trunc++;
2615
2616 return;
2617 }
2618 /* Count the errors, if there were any */
2619 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2620 stats->rx_length_errors++;
2621
2622 if (status & RXBD_LARGE)
2623 estats->rx_large++;
2624 else
2625 estats->rx_short++;
2626 }
2627 if (status & RXBD_NONOCTET) {
2628 stats->rx_frame_errors++;
2629 estats->rx_nonoctet++;
2630 }
2631 if (status & RXBD_CRCERR) {
2632 estats->rx_crcerr++;
2633 stats->rx_crc_errors++;
2634 }
2635 if (status & RXBD_OVERRUN) {
2636 estats->rx_overrun++;
2637 stats->rx_crc_errors++;
2638 }
2639}
2640
f4983704 2641irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2642{
f4983704 2643 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2644 return IRQ_HANDLED;
2645}
2646
0bbaf069
KG		 2647static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2648{
2649 /* If valid headers were found, and valid sums
2650 * were verified, then we tell the kernel that no
2651 * checksumming is necessary. Otherwise, it is */
7f7f5316 2652 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2653 skb->ip_summed = CHECKSUM_UNNECESSARY;
2654 else
bc8acf2c 2655 skb_checksum_none_assert(skb);
0bbaf069
KG		 2656}
2657
2658
1da177e4
LT		 2659/* gfar_process_frame() -- handle one incoming packet if skb
2660 * isn't NULL. */
2661static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2c2db48a 2662 int amount_pull)
1da177e4
LT		 2663{
2664 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2665 struct rxfcb *fcb = NULL;
1da177e4 2666
2c2db48a 2667 int ret;
1da177e4 2668
2c2db48a
DH		 2669 /* fcb is at the beginning if exists */
2670 fcb = (struct rxfcb *)skb->data;
0bbaf069 2671
2c2db48a
DH		 2672 /* Remove the FCB from the skb */
2673 /* Remove the padded bytes, if there are any */
f74dac08
SG		 2674 if (amount_pull) {
2675 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2676 skb_pull(skb, amount_pull);
f74dac08 2677 }
0bbaf069 2678
cc772ab7
MR		 2679 /* Get receive timestamp from the skb */
2680 if (priv->hwts_rx_en) {
2681 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2682 u64 *ns = (u64 *) skb->data;
2683 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2684 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2685 }
2686
2687 if (priv->padding)
2688 skb_pull(skb, priv->padding);
2689
2c2db48a
DH		 2690 if (priv->rx_csum_enable)
2691 gfar_rx_checksum(skb, fcb);
0bbaf069 2692
2c2db48a
DH		 2693 /* Tell the skb what kind of packet this is */
2694 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2695
2c2db48a
DH		 2696 /* Send the packet up the stack */
2697 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2698 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2699 else
2700 ret = netif_receive_skb(skb);
0bbaf069 2701
2c2db48a
DH		 2702 if (NET_RX_DROP == ret)
2703 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 2704
2705 return 0;
2706}
2707
2708/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 2709 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 2710 * of frames handled
2711 */
a12f801d 2712int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2713{
a12f801d 2714 struct net_device *dev = rx_queue->dev;
31de198b 2715 struct rxbd8 *bdp, *base;
1da177e4 2716 struct sk_buff *skb;
2c2db48a
DH		 2717 int pkt_len;
2718 int amount_pull;
1da177e4
LT		 2719 int howmany = 0;
2720 struct gfar_private *priv = netdev_priv(dev);
2721
2722 /* Get the first full descriptor */
a12f801d
SG		 2723 bdp = rx_queue->cur_rx;
2724 base = rx_queue->rx_bd_base;
1da177e4 2725
cc772ab7 2726 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2c2db48a 2727
1da177e4 2728 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2729 struct sk_buff *newskb;
3b6330ce 2730 rmb();
815b97c6
AF		 2731
2732 /* Add another skb for the future */
2733 newskb = gfar_new_skb(dev);
2734
a12f801d 2735 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2736
4826857f 2737 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
81183059
AF		 2738 priv->rx_buffer_size, DMA_FROM_DEVICE);
2739
63b88b90
AV		 2740 if (unlikely(!(bdp->status & RXBD_ERR) &&
2741 bdp->length > priv->rx_buffer_size))
2742 bdp->status = RXBD_LARGE;
2743
815b97c6
AF		 2744 /* We drop the frame if we failed to allocate a new buffer */
2745 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2746 bdp->status & RXBD_ERR)) {
2747 count_errors(bdp->status, dev);
2748
2749 if (unlikely(!newskb))
2750 newskb = skb;
acbc0f03 2751 else if (skb)
cd0ea241 2752 skb_queue_head(&priv->rx_recycle, skb);
815b97c6 2753 } else {
1da177e4 2754 /* Increment the number of packets */
a7f38041 2755 rx_queue->stats.rx_packets++;
1da177e4
LT		 2756 howmany++;
2757
2c2db48a
DH		 2758 if (likely(skb)) {
2759 pkt_len = bdp->length - ETH_FCS_LEN;
2760 /* Remove the FCS from the packet length */
2761 skb_put(skb, pkt_len);
a7f38041 2762 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2763 skb_record_rx_queue(skb, rx_queue->qindex);
2c2db48a
DH		 2764 gfar_process_frame(dev, skb, amount_pull);
2765
2766 } else {
2767 if (netif_msg_rx_err(priv))
2768 printk(KERN_WARNING
2769 "%s: Missing skb!\n", dev->name);
a7f38041 2770 rx_queue->stats.rx_dropped++;
2c2db48a
DH		 2771 priv->extra_stats.rx_skbmissing++;
2772 }
1da177e4 2773
1da177e4
LT		 2774 }
2775
a12f801d 2776 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2777
815b97c6 2778 /* Setup the new bdp */
a12f801d 2779 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2780
2781 /* Update to the next pointer */
a12f801d 2782 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2783
2784 /* update to point at the next skb */
a12f801d
SG		 2785 rx_queue->skb_currx =
2786 (rx_queue->skb_currx + 1) &
2787 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2788 }
2789
2790 /* Update the current rxbd pointer to be the next one */
a12f801d 2791 rx_queue->cur_rx = bdp;
1da177e4 2792
1da177e4
LT		 2793 return howmany;
2794}
2795
bea3348e 2796static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2797{
fba4ed03
SG		 2798 struct gfar_priv_grp *gfargrp = container_of(napi,
2799 struct gfar_priv_grp, napi);
2800 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2801 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2802 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03
SG		 2803 struct gfar_priv_rx_q *rx_queue = NULL;
2804 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
18294ad1
AV		 2805 int tx_cleaned = 0, i, left_over_budget = budget;
2806 unsigned long serviced_queues = 0;
fba4ed03 2807 int num_queues = 0;
d080cd63 2808
fba4ed03
SG		 2809 num_queues = gfargrp->num_rx_queues;
2810 budget_per_queue = budget/num_queues;
2811
8c7396ae
DH		 2812 /* Clear IEVENT, so interrupts aren't called again
2813 * because of the packets that have already arrived */
f4983704 2814 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2815
fba4ed03 2816 while (num_queues && left_over_budget) {
1da177e4 2817
fba4ed03
SG		 2818 budget_per_queue = left_over_budget/num_queues;
2819 left_over_budget = 0;
2820
984b3f57 2821 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
fba4ed03
SG		 2822 if (test_bit(i, &serviced_queues))
2823 continue;
2824 rx_queue = priv->rx_queue[i];
2825 tx_queue = priv->tx_queue[rx_queue->qindex];
2826
a3bc1f11 2827 tx_cleaned += gfar_clean_tx_ring(tx_queue);
fba4ed03
SG		 2828 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2829 budget_per_queue);
2830 rx_cleaned += rx_cleaned_per_queue;
2831 if(rx_cleaned_per_queue < budget_per_queue) {
2832 left_over_budget = left_over_budget +
2833 (budget_per_queue - rx_cleaned_per_queue);
2834 set_bit(i, &serviced_queues);
2835 num_queues--;
2836 }
2837 }
2838 }
1da177e4 2839
42199884
AF		 2840 if (tx_cleaned)
2841 return budget;
2842
2843 if (rx_cleaned < budget) {
288379f0 2844 napi_complete(napi);
1da177e4
LT		 2845
2846 /* Clear the halt bit in RSTAT */
fba4ed03 2847 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2848
f4983704 2849 gfar_write(&regs->imask, IMASK_DEFAULT);
1da177e4
LT		 2850
2851 /* If we are coalescing interrupts, update the timer */
2852 /* Otherwise, clear it */
46ceb60c
SG		 2853 gfar_configure_coalescing(priv,
2854 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
1da177e4
LT		 2855 }
2856
42199884 2857 return rx_cleaned;
1da177e4 2858}
1da177e4 2859
f2d71c2d
VW		 2860#ifdef CONFIG_NET_POLL_CONTROLLER
2861/*
2862 * Polling 'interrupt' - used by things like netconsole to send skbs
2863 * without having to re-enable interrupts. It's not called while
2864 * the interrupt routine is executing.
2865 */
2866static void gfar_netpoll(struct net_device *dev)
2867{
2868 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2869 int i = 0;
f2d71c2d
VW		 2870
2871 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2872 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 2873 for (i = 0; i < priv->num_grps; i++) {
2874 disable_irq(priv->gfargrp[i].interruptTransmit);
2875 disable_irq(priv->gfargrp[i].interruptReceive);
2876 disable_irq(priv->gfargrp[i].interruptError);
2877 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2878 &priv->gfargrp[i]);
2879 enable_irq(priv->gfargrp[i].interruptError);
2880 enable_irq(priv->gfargrp[i].interruptReceive);
2881 enable_irq(priv->gfargrp[i].interruptTransmit);
2882 }
f2d71c2d 2883 } else {
46ceb60c
SG		 2884 for (i = 0; i < priv->num_grps; i++) {
2885 disable_irq(priv->gfargrp[i].interruptTransmit);
2886 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2887 &priv->gfargrp[i]);
2888 enable_irq(priv->gfargrp[i].interruptTransmit);
43de004b 2889 }
f2d71c2d
VW		 2890 }
2891}
2892#endif
2893
1da177e4 2894/* The interrupt handler for devices with one interrupt */
f4983704 2895static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2896{
f4983704 2897 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2898
2899 /* Save ievent for future reference */
f4983704 2900 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2901
1da177e4 2902 /* Check for reception */
538cc7ee 2903 if (events & IEVENT_RX_MASK)
f4983704 2904 gfar_receive(irq, grp_id);
1da177e4
LT		 2905
2906 /* Check for transmit completion */
538cc7ee 2907 if (events & IEVENT_TX_MASK)
f4983704 2908 gfar_transmit(irq, grp_id);
1da177e4 2909
538cc7ee
SS		 2910 /* Check for errors */
2911 if (events & IEVENT_ERR_MASK)
f4983704 2912 gfar_error(irq, grp_id);
1da177e4
LT		 2913
2914 return IRQ_HANDLED;
2915}
2916
1da177e4
LT		 2917/* Called every time the controller might need to be made
2918 * aware of new link state. The PHY code conveys this
bb40dcbb 2919 * information through variables in the phydev structure, and this
1da177e4
LT		 2920 * function converts those variables into the appropriate
2921 * register values, and can bring down the device if needed.
2922 */
2923static void adjust_link(struct net_device *dev)
2924{
2925 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2926 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2927 unsigned long flags;
2928 struct phy_device *phydev = priv->phydev;
2929 int new_state = 0;
2930
fba4ed03
SG		 2931 local_irq_save(flags);
2932 lock_tx_qs(priv);
2933
bb40dcbb
AF		 2934 if (phydev->link) {
2935 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2936 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2937
1da177e4
LT		 2938 /* Now we make sure that we can be in full duplex mode.
2939 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 2940 if (phydev->duplex != priv->oldduplex) {
2941 new_state = 1;
2942 if (!(phydev->duplex))
1da177e4 2943 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2944 else
1da177e4 2945 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2946
bb40dcbb 2947 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2948 }
2949
bb40dcbb
AF		 2950 if (phydev->speed != priv->oldspeed) {
2951 new_state = 1;
2952 switch (phydev->speed) {
1da177e4 2953 case 1000:
1da177e4
LT		 2954 tempval =
2955 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 2956
2957 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2958 break;
2959 case 100:
2960 case 10:
1da177e4
LT		 2961 tempval =
2962 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 2963
2964 /* Reduced mode distinguishes
2965 * between 10 and 100 */
2966 if (phydev->speed == SPEED_100)
2967 ecntrl |= ECNTRL_R100;
2968 else
2969 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2970 break;
2971 default:
0bbaf069
KG		 2972 if (netif_msg_link(priv))
2973 printk(KERN_WARNING
bb40dcbb
AF		 2974 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2975 dev->name, phydev->speed);
1da177e4
LT		 2976 break;
2977 }
2978
bb40dcbb 2979 priv->oldspeed = phydev->speed;
1da177e4
LT		 2980 }
2981
bb40dcbb 2982 gfar_write(&regs->maccfg2, tempval);
7f7f5316 2983 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 2984
1da177e4 2985 if (!priv->oldlink) {
bb40dcbb 2986 new_state = 1;
1da177e4 2987 priv->oldlink = 1;
1da177e4 2988 }
bb40dcbb
AF		 2989 } else if (priv->oldlink) {
2990 new_state = 1;
2991 priv->oldlink = 0;
2992 priv->oldspeed = 0;
2993 priv->oldduplex = -1;
1da177e4 2994 }
1da177e4 2995
bb40dcbb
AF		 2996 if (new_state && netif_msg_link(priv))
2997 phy_print_status(phydev);
fba4ed03
SG		 2998 unlock_tx_qs(priv);
2999 local_irq_restore(flags);
bb40dcbb 3000}
1da177e4
LT		 3001
3002/* Update the hash table based on the current list of multicast
3003 * addresses we subscribe to. Also, change the promiscuity of
3004 * the device based on the flags (this function is called
3005 * whenever dev->flags is changed */
3006static void gfar_set_multi(struct net_device *dev)
3007{
22bedad3 3008 struct netdev_hw_addr *ha;
1da177e4 3009 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3010 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3011 u32 tempval;
3012
a12f801d 3013 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3014 /* Set RCTRL to PROM */
3015 tempval = gfar_read(&regs->rctrl);
3016 tempval |= RCTRL_PROM;
3017 gfar_write(&regs->rctrl, tempval);
3018 } else {
3019 /* Set RCTRL to not PROM */
3020 tempval = gfar_read(&regs->rctrl);
3021 tempval &= ~(RCTRL_PROM);
3022 gfar_write(&regs->rctrl, tempval);
3023 }
6aa20a22 3024
a12f801d 3025 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3026 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3027 gfar_write(&regs->igaddr0, 0xffffffff);
3028 gfar_write(&regs->igaddr1, 0xffffffff);
3029 gfar_write(&regs->igaddr2, 0xffffffff);
3030 gfar_write(&regs->igaddr3, 0xffffffff);
3031 gfar_write(&regs->igaddr4, 0xffffffff);
3032 gfar_write(&regs->igaddr5, 0xffffffff);
3033 gfar_write(&regs->igaddr6, 0xffffffff);
3034 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3035 gfar_write(&regs->gaddr0, 0xffffffff);
3036 gfar_write(&regs->gaddr1, 0xffffffff);
3037 gfar_write(&regs->gaddr2, 0xffffffff);
3038 gfar_write(&regs->gaddr3, 0xffffffff);
3039 gfar_write(&regs->gaddr4, 0xffffffff);
3040 gfar_write(&regs->gaddr5, 0xffffffff);
3041 gfar_write(&regs->gaddr6, 0xffffffff);
3042 gfar_write(&regs->gaddr7, 0xffffffff);
3043 } else {
7f7f5316
AF		 3044 int em_num;
3045 int idx;
3046
1da177e4 3047 /* zero out the hash */
0bbaf069
KG		 3048 gfar_write(&regs->igaddr0, 0x0);
3049 gfar_write(&regs->igaddr1, 0x0);
3050 gfar_write(&regs->igaddr2, 0x0);
3051 gfar_write(&regs->igaddr3, 0x0);
3052 gfar_write(&regs->igaddr4, 0x0);
3053 gfar_write(&regs->igaddr5, 0x0);
3054 gfar_write(&regs->igaddr6, 0x0);
3055 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3056 gfar_write(&regs->gaddr0, 0x0);
3057 gfar_write(&regs->gaddr1, 0x0);
3058 gfar_write(&regs->gaddr2, 0x0);
3059 gfar_write(&regs->gaddr3, 0x0);
3060 gfar_write(&regs->gaddr4, 0x0);
3061 gfar_write(&regs->gaddr5, 0x0);
3062 gfar_write(&regs->gaddr6, 0x0);
3063 gfar_write(&regs->gaddr7, 0x0);
3064
7f7f5316
AF		 3065 /* If we have extended hash tables, we need to
3066 * clear the exact match registers to prepare for
3067 * setting them */
3068 if (priv->extended_hash) {
3069 em_num = GFAR_EM_NUM + 1;
3070 gfar_clear_exact_match(dev);
3071 idx = 1;
3072 } else {
3073 idx = 0;
3074 em_num = 0;
3075 }
3076
4cd24eaf 3077 if (netdev_mc_empty(dev))
1da177e4
LT		 3078 return;
3079
3080 /* Parse the list, and set the appropriate bits */
22bedad3 3081 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3082 if (idx < em_num) {
22bedad3 3083 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3084 idx++;
3085 } else
22bedad3 3086 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3087 }
3088 }
1da177e4
LT		 3089}
3090
7f7f5316
AF		 3091
3092/* Clears each of the exact match registers to zero, so they
3093 * don't interfere with normal reception */
3094static void gfar_clear_exact_match(struct net_device *dev)
3095{
3096 int idx;
3097 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
3098
3099 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3100 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
3101}
3102
1da177e4
LT		 3103/* Set the appropriate hash bit for the given addr */
3104/* The algorithm works like so:
3105 * 1) Take the Destination Address (ie the multicast address), and
3106 * do a CRC on it (little endian), and reverse the bits of the
3107 * result.
3108 * 2) Use the 8 most significant bits as a hash into a 256-entry
3109 * table. The table is controlled through 8 32-bit registers:
3110 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3111 * gaddr7. This means that the 3 most significant bits in the
3112 * hash index which gaddr register to use, and the 5 other bits
3113 * indicate which bit (assuming an IBM numbering scheme, which
3114 * for PowerPC (tm) is usually the case) in the register holds
3115 * the entry. */
3116static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3117{
3118 u32 tempval;
3119 struct gfar_private *priv = netdev_priv(dev);
1da177e4 3120 u32 result = ether_crc(MAC_ADDR_LEN, addr);
0bbaf069
KG		 3121 int width = priv->hash_width;
3122 u8 whichbit = (result >> (32 - width)) & 0x1f;
3123 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3124 u32 value = (1 << (31-whichbit));
3125
0bbaf069 3126 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3127 tempval |= value;
0bbaf069 3128 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3129}
3130
7f7f5316
AF		 3131
3132/* There are multiple MAC Address register pairs on some controllers
3133 * This function sets the numth pair to a given address
3134 */
3135static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
3136{
3137 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3138 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316
AF		 3139 int idx;
3140 char tmpbuf[MAC_ADDR_LEN];
3141 u32 tempval;
f4983704 3142 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3143
3144 macptr += num*2;
3145
3146 /* Now copy it into the mac registers backwards, cuz */
3147 /* little endian is silly */
3148 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3149 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3150
3151 gfar_write(macptr, *((u32 *) (tmpbuf)));
3152
3153 tempval = *((u32 *) (tmpbuf + 4));
3154
3155 gfar_write(macptr+1, tempval);
3156}
3157
1da177e4 3158/* GFAR error interrupt handler */
f4983704 3159static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3160{
f4983704
SG		 3161 struct gfar_priv_grp *gfargrp = grp_id;
3162 struct gfar __iomem *regs = gfargrp->regs;
3163 struct gfar_private *priv= gfargrp->priv;
3164 struct net_device *dev = priv->ndev;
1da177e4
LT		 3165
3166 /* Save ievent for future reference */
f4983704 3167 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3168
3169 /* Clear IEVENT */
f4983704 3170 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3171
3172 /* Magic Packet is not an error. */
b31a1d8b 3173 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3174 (events & IEVENT_MAG))
3175 events &= ~IEVENT_MAG;
1da177e4
LT		 3176
3177 /* Hmm... */
0bbaf069
KG		 3178 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3179 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
f4983704 3180 dev->name, events, gfar_read(&regs->imask));
1da177e4
LT		 3181
3182 /* Update the error counters */
3183 if (events & IEVENT_TXE) {
09f75cd7 3184 dev->stats.tx_errors++;
1da177e4
LT		 3185
3186 if (events & IEVENT_LC)
09f75cd7 3187 dev->stats.tx_window_errors++;
1da177e4 3188 if (events & IEVENT_CRL)
09f75cd7 3189 dev->stats.tx_aborted_errors++;
1da177e4 3190 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3191 unsigned long flags;
3192
0bbaf069 3193 if (netif_msg_tx_err(priv))
538cc7ee
SS		 3194 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3195 "packet dropped.\n", dev->name);
09f75cd7 3196 dev->stats.tx_dropped++;
1da177e4
LT		 3197 priv->extra_stats.tx_underrun++;
3198
836cf7fa
AV		 3199 local_irq_save(flags);
3200 lock_tx_qs(priv);
3201
1da177e4 3202 /* Reactivate the Tx Queues */
fba4ed03 3203 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3204
3205 unlock_tx_qs(priv);
3206 local_irq_restore(flags);
1da177e4 3207 }
0bbaf069
KG		 3208 if (netif_msg_tx_err(priv))
3209 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1da177e4
LT		 3210 }
3211 if (events & IEVENT_BSY) {
09f75cd7 3212 dev->stats.rx_errors++;
1da177e4
LT		 3213 priv->extra_stats.rx_bsy++;
3214
f4983704 3215 gfar_receive(irq, grp_id);
1da177e4 3216
0bbaf069 3217 if (netif_msg_rx_err(priv))
538cc7ee 3218 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
f4983704 3219 dev->name, gfar_read(&regs->rstat));
1da177e4
LT		 3220 }
3221 if (events & IEVENT_BABR) {
09f75cd7 3222 dev->stats.rx_errors++;
1da177e4
LT		 3223 priv->extra_stats.rx_babr++;
3224
0bbaf069 3225 if (netif_msg_rx_err(priv))
538cc7ee 3226 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1da177e4
LT		 3227 }
3228 if (events & IEVENT_EBERR) {
3229 priv->extra_stats.eberr++;
0bbaf069 3230 if (netif_msg_rx_err(priv))
538cc7ee 3231 printk(KERN_DEBUG "%s: bus error\n", dev->name);
1da177e4 3232 }
0bbaf069 3233 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
538cc7ee 3234 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1da177e4
LT		 3235
3236 if (events & IEVENT_BABT) {
3237 priv->extra_stats.tx_babt++;
0bbaf069 3238 if (netif_msg_tx_err(priv))
538cc7ee 3239 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1da177e4
LT		 3240 }
3241 return IRQ_HANDLED;
3242}
3243
b31a1d8b
AF		 3244static struct of_device_id gfar_match[] =
3245{
3246 {
3247 .type = "network",
3248 .compatible = "gianfar",
3249 },
46ceb60c
SG		 3250 {
3251 .compatible = "fsl,etsec2",
3252 },
b31a1d8b
AF		 3253 {},
3254};
e72701ac 3255MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3256
1da177e4 3257/* Structure for a device driver */
b31a1d8b 3258static struct of_platform_driver gfar_driver = {
4018294b
GL		 3259 .driver = {
3260 .name = "fsl-gianfar",
3261 .owner = THIS_MODULE,
3262 .pm = GFAR_PM_OPS,
3263 .of_match_table = gfar_match,
3264 },
1da177e4
LT		 3265 .probe = gfar_probe,
3266 .remove = gfar_remove,
3267};
3268
3269static int __init gfar_init(void)
3270{
1577ecef 3271 return of_register_platform_driver(&gfar_driver);
1da177e4
LT		 3272}
3273
3274static void __exit gfar_exit(void)
3275{
b31a1d8b 3276 of_unregister_platform_driver(&gfar_driver);
1da177e4
LT		 3277}
3278
3279module_init(gfar_init);
3280module_exit(gfar_exit);
3281
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