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Commit | Line | Data |
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0bbaf069 | 1 | /* |
1da177e4 LT |
2 | * drivers/net/gianfar.c |
3 | * | |
4 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
5 | * This driver is designed for the non-CPM ethernet controllers |
6 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
7 | * Based on 8260_io/fcc_enet.c |
8 | * | |
9 | * Author: Andy Fleming | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala |
1da177e4 | 11 | * |
e8a2b6a4 | 12 | * Copyright (c) 2002-2006 Freescale Semiconductor, Inc. |
538cc7ee | 13 | * Copyright (c) 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
1da177e4 | 64 | #include <linux/kernel.h> |
1da177e4 LT |
65 | #include <linux/string.h> |
66 | #include <linux/errno.h> | |
bb40dcbb | 67 | #include <linux/unistd.h> |
1da177e4 LT |
68 | #include <linux/slab.h> |
69 | #include <linux/interrupt.h> | |
70 | #include <linux/init.h> | |
71 | #include <linux/delay.h> | |
72 | #include <linux/netdevice.h> | |
73 | #include <linux/etherdevice.h> | |
74 | #include <linux/skbuff.h> | |
0bbaf069 | 75 | #include <linux/if_vlan.h> |
1da177e4 LT |
76 | #include <linux/spinlock.h> |
77 | #include <linux/mm.h> | |
b31a1d8b | 78 | #include <linux/of_platform.h> |
0bbaf069 KG |
79 | #include <linux/ip.h> |
80 | #include <linux/tcp.h> | |
81 | #include <linux/udp.h> | |
9c07b884 | 82 | #include <linux/in.h> |
1da177e4 LT |
83 | |
84 | #include <asm/io.h> | |
85 | #include <asm/irq.h> | |
86 | #include <asm/uaccess.h> | |
87 | #include <linux/module.h> | |
1da177e4 LT |
88 | #include <linux/dma-mapping.h> |
89 | #include <linux/crc32.h> | |
bb40dcbb AF |
90 | #include <linux/mii.h> |
91 | #include <linux/phy.h> | |
b31a1d8b AF |
92 | #include <linux/phy_fixed.h> |
93 | #include <linux/of.h> | |
1da177e4 LT |
94 | |
95 | #include "gianfar.h" | |
1577ecef | 96 | #include "fsl_pq_mdio.h" |
1da177e4 LT |
97 | |
98 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 LT |
99 | #undef BRIEF_GFAR_ERRORS |
100 | #undef VERBOSE_GFAR_ERRORS | |
101 | ||
1da177e4 | 102 | const char gfar_driver_name[] = "Gianfar Ethernet"; |
7f7f5316 | 103 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 104 | |
1da177e4 LT |
105 | static int gfar_enet_open(struct net_device *dev); |
106 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 107 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
108 | static void gfar_timeout(struct net_device *dev); |
109 | static int gfar_close(struct net_device *dev); | |
815b97c6 AF |
110 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
111 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, | |
112 | struct sk_buff *skb); | |
1da177e4 LT |
113 | static int gfar_set_mac_address(struct net_device *dev); |
114 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
115 | static irqreturn_t gfar_error(int irq, void *dev_id); |
116 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
117 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
118 | static void adjust_link(struct net_device *dev); |
119 | static void init_registers(struct net_device *dev); | |
120 | static int init_phy(struct net_device *dev); | |
b31a1d8b AF |
121 | static int gfar_probe(struct of_device *ofdev, |
122 | const struct of_device_id *match); | |
123 | static int gfar_remove(struct of_device *ofdev); | |
bb40dcbb | 124 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
125 | static void gfar_set_multi(struct net_device *dev); |
126 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 127 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 128 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
129 | #ifdef CONFIG_NET_POLL_CONTROLLER |
130 | static void gfar_netpoll(struct net_device *dev); | |
131 | #endif | |
0bbaf069 | 132 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit); |
f162b9d5 | 133 | static int gfar_clean_tx_ring(struct net_device *dev); |
2c2db48a DH |
134 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
135 | int amount_pull); | |
0bbaf069 KG |
136 | static void gfar_vlan_rx_register(struct net_device *netdev, |
137 | struct vlan_group *grp); | |
7f7f5316 | 138 | void gfar_halt(struct net_device *dev); |
d87eb127 | 139 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
140 | void gfar_start(struct net_device *dev); |
141 | static void gfar_clear_exact_match(struct net_device *dev); | |
142 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr); | |
1da177e4 | 143 | |
1da177e4 LT |
144 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
145 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
146 | MODULE_LICENSE("GPL"); | |
147 | ||
7f7f5316 AF |
148 | /* Returns 1 if incoming frames use an FCB */ |
149 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 150 | { |
77ecaf2d | 151 | return priv->vlgrp || priv->rx_csum_enable; |
0bbaf069 | 152 | } |
bb40dcbb | 153 | |
b31a1d8b AF |
154 | static int gfar_of_init(struct net_device *dev) |
155 | { | |
156 | struct device_node *phy, *mdio; | |
157 | const unsigned int *id; | |
158 | const char *model; | |
159 | const char *ctype; | |
160 | const void *mac_addr; | |
161 | const phandle *ph; | |
162 | u64 addr, size; | |
163 | int err = 0; | |
164 | struct gfar_private *priv = netdev_priv(dev); | |
165 | struct device_node *np = priv->node; | |
166 | char bus_name[MII_BUS_ID_SIZE]; | |
167 | ||
168 | if (!np || !of_device_is_available(np)) | |
169 | return -ENODEV; | |
170 | ||
171 | /* get a pointer to the register memory */ | |
172 | addr = of_translate_address(np, of_get_address(np, 0, &size, NULL)); | |
173 | priv->regs = ioremap(addr, size); | |
174 | ||
175 | if (priv->regs == NULL) | |
176 | return -ENOMEM; | |
177 | ||
178 | priv->interruptTransmit = irq_of_parse_and_map(np, 0); | |
179 | ||
180 | model = of_get_property(np, "model", NULL); | |
181 | ||
182 | /* If we aren't the FEC we have multiple interrupts */ | |
183 | if (model && strcasecmp(model, "FEC")) { | |
184 | priv->interruptReceive = irq_of_parse_and_map(np, 1); | |
185 | ||
186 | priv->interruptError = irq_of_parse_and_map(np, 2); | |
187 | ||
188 | if (priv->interruptTransmit < 0 || | |
189 | priv->interruptReceive < 0 || | |
190 | priv->interruptError < 0) { | |
191 | err = -EINVAL; | |
192 | goto err_out; | |
193 | } | |
194 | } | |
195 | ||
196 | mac_addr = of_get_mac_address(np); | |
197 | if (mac_addr) | |
198 | memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN); | |
199 | ||
200 | if (model && !strcasecmp(model, "TSEC")) | |
201 | priv->device_flags = | |
202 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
203 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
204 | FSL_GIANFAR_DEV_HAS_RMON | | |
205 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
206 | if (model && !strcasecmp(model, "eTSEC")) | |
207 | priv->device_flags = | |
208 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
209 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
210 | FSL_GIANFAR_DEV_HAS_RMON | | |
211 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
2c2db48a | 212 | FSL_GIANFAR_DEV_HAS_PADDING | |
b31a1d8b AF |
213 | FSL_GIANFAR_DEV_HAS_CSUM | |
214 | FSL_GIANFAR_DEV_HAS_VLAN | | |
215 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
216 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH; | |
217 | ||
218 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
219 | ||
220 | /* We only care about rgmii-id. The rest are autodetected */ | |
221 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
222 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
223 | else | |
224 | priv->interface = PHY_INTERFACE_MODE_MII; | |
225 | ||
226 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
227 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
228 | ||
229 | ph = of_get_property(np, "phy-handle", NULL); | |
230 | if (ph == NULL) { | |
231 | u32 *fixed_link; | |
232 | ||
233 | fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL); | |
234 | if (!fixed_link) { | |
235 | err = -ENODEV; | |
236 | goto err_out; | |
237 | } | |
238 | ||
a1d8f601 KG |
239 | snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), |
240 | PHY_ID_FMT, "0", fixed_link[0]); | |
b31a1d8b AF |
241 | } else { |
242 | phy = of_find_node_by_phandle(*ph); | |
243 | ||
244 | if (phy == NULL) { | |
245 | err = -ENODEV; | |
246 | goto err_out; | |
247 | } | |
248 | ||
249 | mdio = of_get_parent(phy); | |
250 | ||
251 | id = of_get_property(phy, "reg", NULL); | |
252 | ||
253 | of_node_put(phy); | |
254 | of_node_put(mdio); | |
255 | ||
1577ecef | 256 | fsl_pq_mdio_bus_name(bus_name, mdio); |
a1d8f601 | 257 | snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x", |
b31a1d8b AF |
258 | bus_name, *id); |
259 | } | |
260 | ||
261 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
262 | ph = of_get_property(np, "tbi-handle", NULL); | |
263 | if (ph) { | |
264 | struct device_node *tbi = of_find_node_by_phandle(*ph); | |
265 | struct of_device *ofdev; | |
266 | struct mii_bus *bus; | |
267 | ||
268 | if (!tbi) | |
269 | return 0; | |
270 | ||
271 | mdio = of_get_parent(tbi); | |
272 | if (!mdio) | |
273 | return 0; | |
274 | ||
275 | ofdev = of_find_device_by_node(mdio); | |
276 | ||
277 | of_node_put(mdio); | |
278 | ||
279 | id = of_get_property(tbi, "reg", NULL); | |
280 | if (!id) | |
281 | return 0; | |
282 | ||
283 | of_node_put(tbi); | |
284 | ||
285 | bus = dev_get_drvdata(&ofdev->dev); | |
286 | ||
287 | priv->tbiphy = bus->phy_map[*id]; | |
288 | } | |
289 | ||
290 | return 0; | |
291 | ||
292 | err_out: | |
293 | iounmap(priv->regs); | |
294 | return err; | |
295 | } | |
296 | ||
0faac9f7 CW |
297 | /* Ioctl MII Interface */ |
298 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
299 | { | |
300 | struct gfar_private *priv = netdev_priv(dev); | |
301 | ||
302 | if (!netif_running(dev)) | |
303 | return -EINVAL; | |
304 | ||
305 | if (!priv->phydev) | |
306 | return -ENODEV; | |
307 | ||
308 | return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); | |
309 | } | |
310 | ||
bb40dcbb AF |
311 | /* Set up the ethernet device structure, private data, |
312 | * and anything else we need before we start */ | |
b31a1d8b AF |
313 | static int gfar_probe(struct of_device *ofdev, |
314 | const struct of_device_id *match) | |
1da177e4 LT |
315 | { |
316 | u32 tempval; | |
317 | struct net_device *dev = NULL; | |
318 | struct gfar_private *priv = NULL; | |
b31a1d8b | 319 | DECLARE_MAC_BUF(mac); |
c50a5d9a DH |
320 | int err = 0; |
321 | int len_devname; | |
1da177e4 LT |
322 | |
323 | /* Create an ethernet device instance */ | |
324 | dev = alloc_etherdev(sizeof (*priv)); | |
325 | ||
bb40dcbb | 326 | if (NULL == dev) |
1da177e4 LT |
327 | return -ENOMEM; |
328 | ||
329 | priv = netdev_priv(dev); | |
bea3348e | 330 | priv->dev = dev; |
b31a1d8b | 331 | priv->node = ofdev->node; |
1da177e4 | 332 | |
b31a1d8b | 333 | err = gfar_of_init(dev); |
1da177e4 | 334 | |
b31a1d8b | 335 | if (err) |
1da177e4 | 336 | goto regs_fail; |
1da177e4 | 337 | |
fef6108d AF |
338 | spin_lock_init(&priv->txlock); |
339 | spin_lock_init(&priv->rxlock); | |
d87eb127 | 340 | spin_lock_init(&priv->bflock); |
ab939905 | 341 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 342 | |
b31a1d8b | 343 | dev_set_drvdata(&ofdev->dev, priv); |
1da177e4 LT |
344 | |
345 | /* Stop the DMA engine now, in case it was running before */ | |
346 | /* (The firmware could have used it, and left it running). */ | |
257d938a | 347 | gfar_halt(dev); |
1da177e4 LT |
348 | |
349 | /* Reset MAC layer */ | |
350 | gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); | |
351 | ||
352 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); | |
353 | gfar_write(&priv->regs->maccfg1, tempval); | |
354 | ||
355 | /* Initialize MACCFG2. */ | |
356 | gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS); | |
357 | ||
358 | /* Initialize ECNTRL */ | |
359 | gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS); | |
360 | ||
1da177e4 LT |
361 | /* Set the dev->base_addr to the gfar reg region */ |
362 | dev->base_addr = (unsigned long) (priv->regs); | |
363 | ||
b31a1d8b | 364 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
365 | |
366 | /* Fill in the dev structure */ | |
367 | dev->open = gfar_enet_open; | |
368 | dev->hard_start_xmit = gfar_start_xmit; | |
369 | dev->tx_timeout = gfar_timeout; | |
370 | dev->watchdog_timeo = TX_TIMEOUT; | |
bea3348e | 371 | netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT); |
f2d71c2d VW |
372 | #ifdef CONFIG_NET_POLL_CONTROLLER |
373 | dev->poll_controller = gfar_netpoll; | |
1da177e4 LT |
374 | #endif |
375 | dev->stop = gfar_close; | |
1da177e4 LT |
376 | dev->change_mtu = gfar_change_mtu; |
377 | dev->mtu = 1500; | |
378 | dev->set_multicast_list = gfar_set_multi; | |
379 | ||
0bbaf069 | 380 | dev->ethtool_ops = &gfar_ethtool_ops; |
0faac9f7 | 381 | dev->do_ioctl = gfar_ioctl; |
0bbaf069 | 382 | |
b31a1d8b | 383 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
0bbaf069 | 384 | priv->rx_csum_enable = 1; |
4669bc90 | 385 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA; |
0bbaf069 KG |
386 | } else |
387 | priv->rx_csum_enable = 0; | |
388 | ||
389 | priv->vlgrp = NULL; | |
1da177e4 | 390 | |
b31a1d8b | 391 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
0bbaf069 | 392 | dev->vlan_rx_register = gfar_vlan_rx_register; |
1da177e4 | 393 | |
0bbaf069 | 394 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
0bbaf069 KG |
395 | } |
396 | ||
b31a1d8b | 397 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
398 | priv->extended_hash = 1; |
399 | priv->hash_width = 9; | |
400 | ||
401 | priv->hash_regs[0] = &priv->regs->igaddr0; | |
402 | priv->hash_regs[1] = &priv->regs->igaddr1; | |
403 | priv->hash_regs[2] = &priv->regs->igaddr2; | |
404 | priv->hash_regs[3] = &priv->regs->igaddr3; | |
405 | priv->hash_regs[4] = &priv->regs->igaddr4; | |
406 | priv->hash_regs[5] = &priv->regs->igaddr5; | |
407 | priv->hash_regs[6] = &priv->regs->igaddr6; | |
408 | priv->hash_regs[7] = &priv->regs->igaddr7; | |
409 | priv->hash_regs[8] = &priv->regs->gaddr0; | |
410 | priv->hash_regs[9] = &priv->regs->gaddr1; | |
411 | priv->hash_regs[10] = &priv->regs->gaddr2; | |
412 | priv->hash_regs[11] = &priv->regs->gaddr3; | |
413 | priv->hash_regs[12] = &priv->regs->gaddr4; | |
414 | priv->hash_regs[13] = &priv->regs->gaddr5; | |
415 | priv->hash_regs[14] = &priv->regs->gaddr6; | |
416 | priv->hash_regs[15] = &priv->regs->gaddr7; | |
417 | ||
418 | } else { | |
419 | priv->extended_hash = 0; | |
420 | priv->hash_width = 8; | |
421 | ||
422 | priv->hash_regs[0] = &priv->regs->gaddr0; | |
1577ecef | 423 | priv->hash_regs[1] = &priv->regs->gaddr1; |
0bbaf069 KG |
424 | priv->hash_regs[2] = &priv->regs->gaddr2; |
425 | priv->hash_regs[3] = &priv->regs->gaddr3; | |
426 | priv->hash_regs[4] = &priv->regs->gaddr4; | |
427 | priv->hash_regs[5] = &priv->regs->gaddr5; | |
428 | priv->hash_regs[6] = &priv->regs->gaddr6; | |
429 | priv->hash_regs[7] = &priv->regs->gaddr7; | |
430 | } | |
431 | ||
b31a1d8b | 432 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
433 | priv->padding = DEFAULT_PADDING; |
434 | else | |
435 | priv->padding = 0; | |
436 | ||
0bbaf069 KG |
437 | if (dev->features & NETIF_F_IP_CSUM) |
438 | dev->hard_header_len += GMAC_FCB_LEN; | |
1da177e4 LT |
439 | |
440 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; | |
1da177e4 LT |
441 | priv->tx_ring_size = DEFAULT_TX_RING_SIZE; |
442 | priv->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
4669bc90 | 443 | priv->num_txbdfree = DEFAULT_TX_RING_SIZE; |
1da177e4 LT |
444 | |
445 | priv->txcoalescing = DEFAULT_TX_COALESCE; | |
b46a8454 | 446 | priv->txic = DEFAULT_TXIC; |
1da177e4 | 447 | priv->rxcoalescing = DEFAULT_RX_COALESCE; |
b46a8454 | 448 | priv->rxic = DEFAULT_RXIC; |
1da177e4 | 449 | |
0bbaf069 KG |
450 | /* Enable most messages by default */ |
451 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
452 | ||
d3eab82b TP |
453 | /* Carrier starts down, phylib will bring it up */ |
454 | netif_carrier_off(dev); | |
455 | ||
1da177e4 LT |
456 | err = register_netdev(dev); |
457 | ||
458 | if (err) { | |
459 | printk(KERN_ERR "%s: Cannot register net device, aborting.\n", | |
460 | dev->name); | |
461 | goto register_fail; | |
462 | } | |
463 | ||
2884e5cc AV |
464 | device_init_wakeup(&dev->dev, |
465 | priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
466 | ||
c50a5d9a DH |
467 | /* fill out IRQ number and name fields */ |
468 | len_devname = strlen(dev->name); | |
469 | strncpy(&priv->int_name_tx[0], dev->name, len_devname); | |
470 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { | |
471 | strncpy(&priv->int_name_tx[len_devname], | |
472 | "_tx", sizeof("_tx") + 1); | |
473 | ||
474 | strncpy(&priv->int_name_rx[0], dev->name, len_devname); | |
475 | strncpy(&priv->int_name_rx[len_devname], | |
476 | "_rx", sizeof("_rx") + 1); | |
477 | ||
478 | strncpy(&priv->int_name_er[0], dev->name, len_devname); | |
479 | strncpy(&priv->int_name_er[len_devname], | |
480 | "_er", sizeof("_er") + 1); | |
481 | } else | |
482 | priv->int_name_tx[len_devname] = '\0'; | |
483 | ||
7f7f5316 AF |
484 | /* Create all the sysfs files */ |
485 | gfar_init_sysfs(dev); | |
486 | ||
1da177e4 | 487 | /* Print out the device info */ |
e174961c | 488 | printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr); |
1da177e4 LT |
489 | |
490 | /* Even more device info helps when determining which kernel */ | |
7f7f5316 | 491 | /* provided which set of benchmarks. */ |
1da177e4 | 492 | printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name); |
1da177e4 LT |
493 | printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n", |
494 | dev->name, priv->rx_ring_size, priv->tx_ring_size); | |
495 | ||
496 | return 0; | |
497 | ||
498 | register_fail: | |
cc8c6e37 | 499 | iounmap(priv->regs); |
1da177e4 LT |
500 | regs_fail: |
501 | free_netdev(dev); | |
bb40dcbb | 502 | return err; |
1da177e4 LT |
503 | } |
504 | ||
b31a1d8b | 505 | static int gfar_remove(struct of_device *ofdev) |
1da177e4 | 506 | { |
b31a1d8b | 507 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 508 | |
b31a1d8b | 509 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 510 | |
cc8c6e37 | 511 | iounmap(priv->regs); |
b31a1d8b | 512 | free_netdev(priv->dev); |
1da177e4 LT |
513 | |
514 | return 0; | |
515 | } | |
516 | ||
d87eb127 | 517 | #ifdef CONFIG_PM |
b31a1d8b | 518 | static int gfar_suspend(struct of_device *ofdev, pm_message_t state) |
d87eb127 | 519 | { |
b31a1d8b AF |
520 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
521 | struct net_device *dev = priv->dev; | |
d87eb127 SW |
522 | unsigned long flags; |
523 | u32 tempval; | |
524 | ||
525 | int magic_packet = priv->wol_en && | |
b31a1d8b | 526 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
527 | |
528 | netif_device_detach(dev); | |
529 | ||
530 | if (netif_running(dev)) { | |
531 | spin_lock_irqsave(&priv->txlock, flags); | |
532 | spin_lock(&priv->rxlock); | |
533 | ||
534 | gfar_halt_nodisable(dev); | |
535 | ||
536 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
537 | tempval = gfar_read(&priv->regs->maccfg1); | |
538 | ||
539 | tempval &= ~MACCFG1_TX_EN; | |
540 | ||
541 | if (!magic_packet) | |
542 | tempval &= ~MACCFG1_RX_EN; | |
543 | ||
544 | gfar_write(&priv->regs->maccfg1, tempval); | |
545 | ||
546 | spin_unlock(&priv->rxlock); | |
547 | spin_unlock_irqrestore(&priv->txlock, flags); | |
548 | ||
d87eb127 | 549 | napi_disable(&priv->napi); |
d87eb127 SW |
550 | |
551 | if (magic_packet) { | |
552 | /* Enable interrupt on Magic Packet */ | |
553 | gfar_write(&priv->regs->imask, IMASK_MAG); | |
554 | ||
555 | /* Enable Magic Packet mode */ | |
556 | tempval = gfar_read(&priv->regs->maccfg2); | |
557 | tempval |= MACCFG2_MPEN; | |
558 | gfar_write(&priv->regs->maccfg2, tempval); | |
559 | } else { | |
560 | phy_stop(priv->phydev); | |
561 | } | |
562 | } | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
b31a1d8b | 567 | static int gfar_resume(struct of_device *ofdev) |
d87eb127 | 568 | { |
b31a1d8b AF |
569 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
570 | struct net_device *dev = priv->dev; | |
d87eb127 SW |
571 | unsigned long flags; |
572 | u32 tempval; | |
573 | int magic_packet = priv->wol_en && | |
b31a1d8b | 574 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
575 | |
576 | if (!netif_running(dev)) { | |
577 | netif_device_attach(dev); | |
578 | return 0; | |
579 | } | |
580 | ||
581 | if (!magic_packet && priv->phydev) | |
582 | phy_start(priv->phydev); | |
583 | ||
584 | /* Disable Magic Packet mode, in case something | |
585 | * else woke us up. | |
586 | */ | |
587 | ||
588 | spin_lock_irqsave(&priv->txlock, flags); | |
589 | spin_lock(&priv->rxlock); | |
590 | ||
591 | tempval = gfar_read(&priv->regs->maccfg2); | |
592 | tempval &= ~MACCFG2_MPEN; | |
593 | gfar_write(&priv->regs->maccfg2, tempval); | |
594 | ||
595 | gfar_start(dev); | |
596 | ||
597 | spin_unlock(&priv->rxlock); | |
598 | spin_unlock_irqrestore(&priv->txlock, flags); | |
599 | ||
600 | netif_device_attach(dev); | |
601 | ||
d87eb127 | 602 | napi_enable(&priv->napi); |
d87eb127 SW |
603 | |
604 | return 0; | |
605 | } | |
606 | #else | |
607 | #define gfar_suspend NULL | |
608 | #define gfar_resume NULL | |
609 | #endif | |
1da177e4 | 610 | |
e8a2b6a4 AF |
611 | /* Reads the controller's registers to determine what interface |
612 | * connects it to the PHY. | |
613 | */ | |
614 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
615 | { | |
616 | struct gfar_private *priv = netdev_priv(dev); | |
617 | u32 ecntrl = gfar_read(&priv->regs->ecntrl); | |
618 | ||
619 | if (ecntrl & ECNTRL_SGMII_MODE) | |
620 | return PHY_INTERFACE_MODE_SGMII; | |
621 | ||
622 | if (ecntrl & ECNTRL_TBI_MODE) { | |
623 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
624 | return PHY_INTERFACE_MODE_RTBI; | |
625 | else | |
626 | return PHY_INTERFACE_MODE_TBI; | |
627 | } | |
628 | ||
629 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
630 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) | |
631 | return PHY_INTERFACE_MODE_RMII; | |
7132ab7f | 632 | else { |
b31a1d8b | 633 | phy_interface_t interface = priv->interface; |
7132ab7f AF |
634 | |
635 | /* | |
636 | * This isn't autodetected right now, so it must | |
637 | * be set by the device tree or platform code. | |
638 | */ | |
639 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
640 | return PHY_INTERFACE_MODE_RGMII_ID; | |
641 | ||
e8a2b6a4 | 642 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 643 | } |
e8a2b6a4 AF |
644 | } |
645 | ||
b31a1d8b | 646 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
647 | return PHY_INTERFACE_MODE_GMII; |
648 | ||
649 | return PHY_INTERFACE_MODE_MII; | |
650 | } | |
651 | ||
652 | ||
bb40dcbb AF |
653 | /* Initializes driver's PHY state, and attaches to the PHY. |
654 | * Returns 0 on success. | |
1da177e4 LT |
655 | */ |
656 | static int init_phy(struct net_device *dev) | |
657 | { | |
658 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 659 | uint gigabit_support = |
b31a1d8b | 660 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb AF |
661 | SUPPORTED_1000baseT_Full : 0; |
662 | struct phy_device *phydev; | |
e8a2b6a4 | 663 | phy_interface_t interface; |
1da177e4 LT |
664 | |
665 | priv->oldlink = 0; | |
666 | priv->oldspeed = 0; | |
667 | priv->oldduplex = -1; | |
668 | ||
e8a2b6a4 AF |
669 | interface = gfar_get_interface(dev); |
670 | ||
b31a1d8b | 671 | phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface); |
1da177e4 | 672 | |
d3c12873 KJ |
673 | if (interface == PHY_INTERFACE_MODE_SGMII) |
674 | gfar_configure_serdes(dev); | |
675 | ||
bb40dcbb AF |
676 | if (IS_ERR(phydev)) { |
677 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
678 | return PTR_ERR(phydev); | |
1da177e4 LT |
679 | } |
680 | ||
bb40dcbb AF |
681 | /* Remove any features not supported by the controller */ |
682 | phydev->supported &= (GFAR_SUPPORTED | gigabit_support); | |
683 | phydev->advertising = phydev->supported; | |
1da177e4 | 684 | |
bb40dcbb | 685 | priv->phydev = phydev; |
1da177e4 LT |
686 | |
687 | return 0; | |
1da177e4 LT |
688 | } |
689 | ||
d0313587 PG |
690 | /* |
691 | * Initialize TBI PHY interface for communicating with the | |
692 | * SERDES lynx PHY on the chip. We communicate with this PHY | |
693 | * through the MDIO bus on each controller, treating it as a | |
694 | * "normal" PHY at the address found in the TBIPA register. We assume | |
695 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
696 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
697 | * value doesn't matter, as there are no other PHYs on the bus. | |
698 | */ | |
d3c12873 KJ |
699 | static void gfar_configure_serdes(struct net_device *dev) |
700 | { | |
701 | struct gfar_private *priv = netdev_priv(dev); | |
c132419e | 702 | |
b31a1d8b AF |
703 | if (!priv->tbiphy) { |
704 | printk(KERN_WARNING "SGMII mode requires that the device " | |
705 | "tree specify a tbi-handle\n"); | |
706 | return; | |
707 | } | |
d3c12873 | 708 | |
b31a1d8b AF |
709 | /* |
710 | * If the link is already up, we must already be ok, and don't need to | |
bdb59f94 TP |
711 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
712 | * everything for us? Resetting it takes the link down and requires | |
713 | * several seconds for it to come back. | |
714 | */ | |
b31a1d8b AF |
715 | if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS) |
716 | return; | |
d3c12873 | 717 | |
d0313587 | 718 | /* Single clk mode, mii mode off(for serdes communication) */ |
b31a1d8b | 719 | phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 720 | |
b31a1d8b | 721 | phy_write(priv->tbiphy, MII_ADVERTISE, |
d3c12873 KJ |
722 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
723 | ADVERTISE_1000XPSE_ASYM); | |
724 | ||
b31a1d8b | 725 | phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE | |
d3c12873 KJ |
726 | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); |
727 | } | |
728 | ||
1da177e4 LT |
729 | static void init_registers(struct net_device *dev) |
730 | { | |
731 | struct gfar_private *priv = netdev_priv(dev); | |
732 | ||
733 | /* Clear IEVENT */ | |
734 | gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR); | |
735 | ||
736 | /* Initialize IMASK */ | |
737 | gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR); | |
738 | ||
739 | /* Init hash registers to zero */ | |
0bbaf069 KG |
740 | gfar_write(&priv->regs->igaddr0, 0); |
741 | gfar_write(&priv->regs->igaddr1, 0); | |
742 | gfar_write(&priv->regs->igaddr2, 0); | |
743 | gfar_write(&priv->regs->igaddr3, 0); | |
744 | gfar_write(&priv->regs->igaddr4, 0); | |
745 | gfar_write(&priv->regs->igaddr5, 0); | |
746 | gfar_write(&priv->regs->igaddr6, 0); | |
747 | gfar_write(&priv->regs->igaddr7, 0); | |
1da177e4 LT |
748 | |
749 | gfar_write(&priv->regs->gaddr0, 0); | |
750 | gfar_write(&priv->regs->gaddr1, 0); | |
751 | gfar_write(&priv->regs->gaddr2, 0); | |
752 | gfar_write(&priv->regs->gaddr3, 0); | |
753 | gfar_write(&priv->regs->gaddr4, 0); | |
754 | gfar_write(&priv->regs->gaddr5, 0); | |
755 | gfar_write(&priv->regs->gaddr6, 0); | |
756 | gfar_write(&priv->regs->gaddr7, 0); | |
757 | ||
1da177e4 | 758 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 759 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
cc8c6e37 | 760 | memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
761 | |
762 | /* Mask off the CAM interrupts */ | |
763 | gfar_write(&priv->regs->rmon.cam1, 0xffffffff); | |
764 | gfar_write(&priv->regs->rmon.cam2, 0xffffffff); | |
765 | } | |
766 | ||
767 | /* Initialize the max receive buffer length */ | |
768 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
769 | ||
1da177e4 LT |
770 | /* Initialize the Minimum Frame Length Register */ |
771 | gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS); | |
1da177e4 LT |
772 | } |
773 | ||
0bbaf069 KG |
774 | |
775 | /* Halt the receive and transmit queues */ | |
d87eb127 | 776 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
777 | { |
778 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 779 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
780 | u32 tempval; |
781 | ||
1da177e4 LT |
782 | /* Mask all interrupts */ |
783 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
784 | ||
785 | /* Clear all interrupts */ | |
786 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
787 | ||
788 | /* Stop the DMA, and wait for it to stop */ | |
789 | tempval = gfar_read(&priv->regs->dmactrl); | |
790 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) | |
791 | != (DMACTRL_GRS | DMACTRL_GTS)) { | |
792 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); | |
793 | gfar_write(&priv->regs->dmactrl, tempval); | |
794 | ||
795 | while (!(gfar_read(&priv->regs->ievent) & | |
796 | (IEVENT_GRSC | IEVENT_GTSC))) | |
797 | cpu_relax(); | |
798 | } | |
d87eb127 | 799 | } |
d87eb127 SW |
800 | |
801 | /* Halt the receive and transmit queues */ | |
802 | void gfar_halt(struct net_device *dev) | |
803 | { | |
804 | struct gfar_private *priv = netdev_priv(dev); | |
805 | struct gfar __iomem *regs = priv->regs; | |
806 | u32 tempval; | |
1da177e4 | 807 | |
2a54adc3 SW |
808 | gfar_halt_nodisable(dev); |
809 | ||
1da177e4 LT |
810 | /* Disable Rx and Tx */ |
811 | tempval = gfar_read(®s->maccfg1); | |
812 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
813 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
814 | } |
815 | ||
816 | void stop_gfar(struct net_device *dev) | |
817 | { | |
818 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 819 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
820 | unsigned long flags; |
821 | ||
bb40dcbb AF |
822 | phy_stop(priv->phydev); |
823 | ||
0bbaf069 | 824 | /* Lock it down */ |
fef6108d AF |
825 | spin_lock_irqsave(&priv->txlock, flags); |
826 | spin_lock(&priv->rxlock); | |
0bbaf069 | 827 | |
0bbaf069 | 828 | gfar_halt(dev); |
1da177e4 | 829 | |
fef6108d AF |
830 | spin_unlock(&priv->rxlock); |
831 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1da177e4 LT |
832 | |
833 | /* Free the IRQs */ | |
b31a1d8b | 834 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
1da177e4 LT |
835 | free_irq(priv->interruptError, dev); |
836 | free_irq(priv->interruptTransmit, dev); | |
837 | free_irq(priv->interruptReceive, dev); | |
838 | } else { | |
1577ecef | 839 | free_irq(priv->interruptTransmit, dev); |
1da177e4 LT |
840 | } |
841 | ||
842 | free_skb_resources(priv); | |
843 | ||
cf782298 | 844 | dma_free_coherent(&dev->dev, |
1da177e4 LT |
845 | sizeof(struct txbd8)*priv->tx_ring_size |
846 | + sizeof(struct rxbd8)*priv->rx_ring_size, | |
847 | priv->tx_bd_base, | |
0bbaf069 | 848 | gfar_read(®s->tbase0)); |
1da177e4 LT |
849 | } |
850 | ||
851 | /* If there are any tx skbs or rx skbs still around, free them. | |
852 | * Then free tx_skbuff and rx_skbuff */ | |
bb40dcbb | 853 | static void free_skb_resources(struct gfar_private *priv) |
1da177e4 LT |
854 | { |
855 | struct rxbd8 *rxbdp; | |
856 | struct txbd8 *txbdp; | |
4669bc90 | 857 | int i, j; |
1da177e4 LT |
858 | |
859 | /* Go through all the buffer descriptors and free their data buffers */ | |
860 | txbdp = priv->tx_bd_base; | |
861 | ||
862 | for (i = 0; i < priv->tx_ring_size; i++) { | |
4669bc90 DH |
863 | if (!priv->tx_skbuff[i]) |
864 | continue; | |
1da177e4 | 865 | |
4669bc90 DH |
866 | dma_unmap_single(&priv->dev->dev, txbdp->bufPtr, |
867 | txbdp->length, DMA_TO_DEVICE); | |
868 | txbdp->lstatus = 0; | |
869 | for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) { | |
870 | txbdp++; | |
871 | dma_unmap_page(&priv->dev->dev, txbdp->bufPtr, | |
872 | txbdp->length, DMA_TO_DEVICE); | |
1da177e4 | 873 | } |
ad5da7ab | 874 | txbdp++; |
4669bc90 DH |
875 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
876 | priv->tx_skbuff[i] = NULL; | |
1da177e4 LT |
877 | } |
878 | ||
879 | kfree(priv->tx_skbuff); | |
880 | ||
881 | rxbdp = priv->rx_bd_base; | |
882 | ||
883 | /* rx_skbuff is not guaranteed to be allocated, so only | |
884 | * free it and its contents if it is allocated */ | |
885 | if(priv->rx_skbuff != NULL) { | |
886 | for (i = 0; i < priv->rx_ring_size; i++) { | |
887 | if (priv->rx_skbuff[i]) { | |
cf782298 | 888 | dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr, |
7f7f5316 | 889 | priv->rx_buffer_size, |
1da177e4 LT |
890 | DMA_FROM_DEVICE); |
891 | ||
892 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
893 | priv->rx_skbuff[i] = NULL; | |
894 | } | |
895 | ||
5a5efed4 | 896 | rxbdp->lstatus = 0; |
1da177e4 LT |
897 | rxbdp->bufPtr = 0; |
898 | ||
899 | rxbdp++; | |
900 | } | |
901 | ||
902 | kfree(priv->rx_skbuff); | |
903 | } | |
904 | } | |
905 | ||
0bbaf069 KG |
906 | void gfar_start(struct net_device *dev) |
907 | { | |
908 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 909 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
910 | u32 tempval; |
911 | ||
912 | /* Enable Rx and Tx in MACCFG1 */ | |
913 | tempval = gfar_read(®s->maccfg1); | |
914 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
915 | gfar_write(®s->maccfg1, tempval); | |
916 | ||
917 | /* Initialize DMACTRL to have WWR and WOP */ | |
918 | tempval = gfar_read(&priv->regs->dmactrl); | |
919 | tempval |= DMACTRL_INIT_SETTINGS; | |
920 | gfar_write(&priv->regs->dmactrl, tempval); | |
921 | ||
0bbaf069 KG |
922 | /* Make sure we aren't stopped */ |
923 | tempval = gfar_read(&priv->regs->dmactrl); | |
924 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); | |
925 | gfar_write(&priv->regs->dmactrl, tempval); | |
926 | ||
fef6108d AF |
927 | /* Clear THLT/RHLT, so that the DMA starts polling now */ |
928 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT); | |
929 | gfar_write(®s->rstat, RSTAT_CLEAR_RHALT); | |
930 | ||
0bbaf069 KG |
931 | /* Unmask the interrupts we look for */ |
932 | gfar_write(®s->imask, IMASK_DEFAULT); | |
12dea57b DH |
933 | |
934 | dev->trans_start = jiffies; | |
0bbaf069 KG |
935 | } |
936 | ||
1da177e4 LT |
937 | /* Bring the controller up and running */ |
938 | int startup_gfar(struct net_device *dev) | |
939 | { | |
940 | struct txbd8 *txbdp; | |
941 | struct rxbd8 *rxbdp; | |
f9663aea | 942 | dma_addr_t addr = 0; |
1da177e4 LT |
943 | unsigned long vaddr; |
944 | int i; | |
945 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 946 | struct gfar __iomem *regs = priv->regs; |
1da177e4 | 947 | int err = 0; |
0bbaf069 | 948 | u32 rctrl = 0; |
7f7f5316 | 949 | u32 attrs = 0; |
1da177e4 LT |
950 | |
951 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
952 | ||
953 | /* Allocate memory for the buffer descriptors */ | |
cf782298 | 954 | vaddr = (unsigned long) dma_alloc_coherent(&dev->dev, |
1da177e4 LT |
955 | sizeof (struct txbd8) * priv->tx_ring_size + |
956 | sizeof (struct rxbd8) * priv->rx_ring_size, | |
957 | &addr, GFP_KERNEL); | |
958 | ||
959 | if (vaddr == 0) { | |
0bbaf069 KG |
960 | if (netif_msg_ifup(priv)) |
961 | printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n", | |
962 | dev->name); | |
1da177e4 LT |
963 | return -ENOMEM; |
964 | } | |
965 | ||
966 | priv->tx_bd_base = (struct txbd8 *) vaddr; | |
967 | ||
968 | /* enet DMA only understands physical addresses */ | |
0bbaf069 | 969 | gfar_write(®s->tbase0, addr); |
1da177e4 LT |
970 | |
971 | /* Start the rx descriptor ring where the tx ring leaves off */ | |
972 | addr = addr + sizeof (struct txbd8) * priv->tx_ring_size; | |
973 | vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size; | |
974 | priv->rx_bd_base = (struct rxbd8 *) vaddr; | |
0bbaf069 | 975 | gfar_write(®s->rbase0, addr); |
1da177e4 LT |
976 | |
977 | /* Setup the skbuff rings */ | |
978 | priv->tx_skbuff = | |
979 | (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) * | |
980 | priv->tx_ring_size, GFP_KERNEL); | |
981 | ||
bb40dcbb | 982 | if (NULL == priv->tx_skbuff) { |
0bbaf069 KG |
983 | if (netif_msg_ifup(priv)) |
984 | printk(KERN_ERR "%s: Could not allocate tx_skbuff\n", | |
985 | dev->name); | |
1da177e4 LT |
986 | err = -ENOMEM; |
987 | goto tx_skb_fail; | |
988 | } | |
989 | ||
990 | for (i = 0; i < priv->tx_ring_size; i++) | |
991 | priv->tx_skbuff[i] = NULL; | |
992 | ||
993 | priv->rx_skbuff = | |
994 | (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) * | |
995 | priv->rx_ring_size, GFP_KERNEL); | |
996 | ||
bb40dcbb | 997 | if (NULL == priv->rx_skbuff) { |
0bbaf069 KG |
998 | if (netif_msg_ifup(priv)) |
999 | printk(KERN_ERR "%s: Could not allocate rx_skbuff\n", | |
1000 | dev->name); | |
1da177e4 LT |
1001 | err = -ENOMEM; |
1002 | goto rx_skb_fail; | |
1003 | } | |
1004 | ||
1005 | for (i = 0; i < priv->rx_ring_size; i++) | |
1006 | priv->rx_skbuff[i] = NULL; | |
1007 | ||
1008 | /* Initialize some variables in our dev structure */ | |
4669bc90 | 1009 | priv->num_txbdfree = priv->tx_ring_size; |
1da177e4 LT |
1010 | priv->dirty_tx = priv->cur_tx = priv->tx_bd_base; |
1011 | priv->cur_rx = priv->rx_bd_base; | |
1012 | priv->skb_curtx = priv->skb_dirtytx = 0; | |
1013 | priv->skb_currx = 0; | |
1014 | ||
1015 | /* Initialize Transmit Descriptor Ring */ | |
1016 | txbdp = priv->tx_bd_base; | |
1017 | for (i = 0; i < priv->tx_ring_size; i++) { | |
5a5efed4 | 1018 | txbdp->lstatus = 0; |
1da177e4 LT |
1019 | txbdp->bufPtr = 0; |
1020 | txbdp++; | |
1021 | } | |
1022 | ||
1023 | /* Set the last descriptor in the ring to indicate wrap */ | |
1024 | txbdp--; | |
1025 | txbdp->status |= TXBD_WRAP; | |
1026 | ||
1027 | rxbdp = priv->rx_bd_base; | |
1028 | for (i = 0; i < priv->rx_ring_size; i++) { | |
815b97c6 | 1029 | struct sk_buff *skb; |
1da177e4 | 1030 | |
815b97c6 | 1031 | skb = gfar_new_skb(dev); |
1da177e4 | 1032 | |
815b97c6 AF |
1033 | if (!skb) { |
1034 | printk(KERN_ERR "%s: Can't allocate RX buffers\n", | |
1035 | dev->name); | |
1036 | ||
1037 | goto err_rxalloc_fail; | |
1038 | } | |
1da177e4 LT |
1039 | |
1040 | priv->rx_skbuff[i] = skb; | |
1041 | ||
815b97c6 AF |
1042 | gfar_new_rxbdp(dev, rxbdp, skb); |
1043 | ||
1da177e4 LT |
1044 | rxbdp++; |
1045 | } | |
1046 | ||
1047 | /* Set the last descriptor in the ring to wrap */ | |
1048 | rxbdp--; | |
1049 | rxbdp->status |= RXBD_WRAP; | |
1050 | ||
1051 | /* If the device has multiple interrupts, register for | |
1052 | * them. Otherwise, only register for the one */ | |
b31a1d8b | 1053 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1054 | /* Install our interrupt handlers for Error, |
1da177e4 LT |
1055 | * Transmit, and Receive */ |
1056 | if (request_irq(priv->interruptError, gfar_error, | |
c50a5d9a | 1057 | 0, priv->int_name_er, dev) < 0) { |
0bbaf069 KG |
1058 | if (netif_msg_intr(priv)) |
1059 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
1060 | dev->name, priv->interruptError); | |
1da177e4 LT |
1061 | |
1062 | err = -1; | |
1063 | goto err_irq_fail; | |
1064 | } | |
1065 | ||
1066 | if (request_irq(priv->interruptTransmit, gfar_transmit, | |
c50a5d9a | 1067 | 0, priv->int_name_tx, dev) < 0) { |
0bbaf069 KG |
1068 | if (netif_msg_intr(priv)) |
1069 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
1070 | dev->name, priv->interruptTransmit); | |
1da177e4 LT |
1071 | |
1072 | err = -1; | |
1073 | ||
1074 | goto tx_irq_fail; | |
1075 | } | |
1076 | ||
1077 | if (request_irq(priv->interruptReceive, gfar_receive, | |
c50a5d9a | 1078 | 0, priv->int_name_rx, dev) < 0) { |
0bbaf069 KG |
1079 | if (netif_msg_intr(priv)) |
1080 | printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n", | |
1081 | dev->name, priv->interruptReceive); | |
1da177e4 LT |
1082 | |
1083 | err = -1; | |
1084 | goto rx_irq_fail; | |
1085 | } | |
1086 | } else { | |
1087 | if (request_irq(priv->interruptTransmit, gfar_interrupt, | |
c50a5d9a | 1088 | 0, priv->int_name_tx, dev) < 0) { |
0bbaf069 KG |
1089 | if (netif_msg_intr(priv)) |
1090 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
c50a5d9a | 1091 | dev->name, priv->interruptTransmit); |
1da177e4 LT |
1092 | |
1093 | err = -1; | |
1094 | goto err_irq_fail; | |
1095 | } | |
1096 | } | |
1097 | ||
bb40dcbb | 1098 | phy_start(priv->phydev); |
1da177e4 LT |
1099 | |
1100 | /* Configure the coalescing support */ | |
b46a8454 | 1101 | gfar_write(®s->txic, 0); |
1da177e4 | 1102 | if (priv->txcoalescing) |
b46a8454 | 1103 | gfar_write(®s->txic, priv->txic); |
1da177e4 | 1104 | |
b46a8454 | 1105 | gfar_write(®s->rxic, 0); |
1da177e4 | 1106 | if (priv->rxcoalescing) |
b46a8454 | 1107 | gfar_write(®s->rxic, priv->rxic); |
1da177e4 | 1108 | |
0bbaf069 KG |
1109 | if (priv->rx_csum_enable) |
1110 | rctrl |= RCTRL_CHECKSUMMING; | |
1da177e4 | 1111 | |
7f7f5316 | 1112 | if (priv->extended_hash) { |
0bbaf069 | 1113 | rctrl |= RCTRL_EXTHASH; |
1da177e4 | 1114 | |
7f7f5316 AF |
1115 | gfar_clear_exact_match(dev); |
1116 | rctrl |= RCTRL_EMEN; | |
1117 | } | |
1118 | ||
7f7f5316 AF |
1119 | if (priv->padding) { |
1120 | rctrl &= ~RCTRL_PAL_MASK; | |
1121 | rctrl |= RCTRL_PADDING(priv->padding); | |
1122 | } | |
1123 | ||
0bbaf069 KG |
1124 | /* Init rctrl based on our settings */ |
1125 | gfar_write(&priv->regs->rctrl, rctrl); | |
1da177e4 | 1126 | |
0bbaf069 KG |
1127 | if (dev->features & NETIF_F_IP_CSUM) |
1128 | gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM); | |
1da177e4 | 1129 | |
7f7f5316 AF |
1130 | /* Set the extraction length and index */ |
1131 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
1132 | ATTRELI_EI(priv->rx_stash_index); | |
1133 | ||
1134 | gfar_write(&priv->regs->attreli, attrs); | |
1135 | ||
1136 | /* Start with defaults, and add stashing or locking | |
1137 | * depending on the approprate variables */ | |
1138 | attrs = ATTR_INIT_SETTINGS; | |
1139 | ||
1140 | if (priv->bd_stash_en) | |
1141 | attrs |= ATTR_BDSTASH; | |
1142 | ||
1143 | if (priv->rx_stash_size != 0) | |
1144 | attrs |= ATTR_BUFSTASH; | |
1145 | ||
1146 | gfar_write(&priv->regs->attr, attrs); | |
1147 | ||
1148 | gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold); | |
1149 | gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve); | |
1150 | gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
1151 | ||
1152 | /* Start the controller */ | |
0bbaf069 | 1153 | gfar_start(dev); |
1da177e4 LT |
1154 | |
1155 | return 0; | |
1156 | ||
1157 | rx_irq_fail: | |
1158 | free_irq(priv->interruptTransmit, dev); | |
1159 | tx_irq_fail: | |
1160 | free_irq(priv->interruptError, dev); | |
1161 | err_irq_fail: | |
7d2e3cb7 | 1162 | err_rxalloc_fail: |
1da177e4 LT |
1163 | rx_skb_fail: |
1164 | free_skb_resources(priv); | |
1165 | tx_skb_fail: | |
cf782298 | 1166 | dma_free_coherent(&dev->dev, |
1da177e4 LT |
1167 | sizeof(struct txbd8)*priv->tx_ring_size |
1168 | + sizeof(struct rxbd8)*priv->rx_ring_size, | |
1169 | priv->tx_bd_base, | |
0bbaf069 | 1170 | gfar_read(®s->tbase0)); |
1da177e4 | 1171 | |
1da177e4 LT |
1172 | return err; |
1173 | } | |
1174 | ||
1175 | /* Called when something needs to use the ethernet device */ | |
1176 | /* Returns 0 for success. */ | |
1177 | static int gfar_enet_open(struct net_device *dev) | |
1178 | { | |
94e8cc35 | 1179 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1180 | int err; |
1181 | ||
bea3348e SH |
1182 | napi_enable(&priv->napi); |
1183 | ||
1da177e4 LT |
1184 | /* Initialize a bunch of registers */ |
1185 | init_registers(dev); | |
1186 | ||
1187 | gfar_set_mac_address(dev); | |
1188 | ||
1189 | err = init_phy(dev); | |
1190 | ||
bea3348e SH |
1191 | if(err) { |
1192 | napi_disable(&priv->napi); | |
1da177e4 | 1193 | return err; |
bea3348e | 1194 | } |
1da177e4 LT |
1195 | |
1196 | err = startup_gfar(dev); | |
db0e8e3f | 1197 | if (err) { |
bea3348e | 1198 | napi_disable(&priv->napi); |
db0e8e3f AV |
1199 | return err; |
1200 | } | |
1da177e4 LT |
1201 | |
1202 | netif_start_queue(dev); | |
1203 | ||
2884e5cc AV |
1204 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1205 | ||
1da177e4 LT |
1206 | return err; |
1207 | } | |
1208 | ||
a22823e7 | 1209 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 KG |
1210 | { |
1211 | struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN); | |
1212 | ||
a22823e7 | 1213 | cacheable_memzero(fcb, GMAC_FCB_LEN); |
0bbaf069 | 1214 | |
0bbaf069 KG |
1215 | return fcb; |
1216 | } | |
1217 | ||
1218 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb) | |
1219 | { | |
7f7f5316 | 1220 | u8 flags = 0; |
0bbaf069 KG |
1221 | |
1222 | /* If we're here, it's a IP packet with a TCP or UDP | |
1223 | * payload. We set it to checksum, using a pseudo-header | |
1224 | * we provide | |
1225 | */ | |
7f7f5316 | 1226 | flags = TXFCB_DEFAULT; |
0bbaf069 | 1227 | |
7f7f5316 AF |
1228 | /* Tell the controller what the protocol is */ |
1229 | /* And provide the already calculated phcs */ | |
eddc9ec5 | 1230 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 1231 | flags |= TXFCB_UDP; |
4bedb452 | 1232 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 1233 | } else |
8da32de5 | 1234 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
1235 | |
1236 | /* l3os is the distance between the start of the | |
1237 | * frame (skb->data) and the start of the IP hdr. | |
1238 | * l4os is the distance between the start of the | |
1239 | * l3 hdr and the l4 hdr */ | |
bbe735e4 | 1240 | fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN); |
cfe1fc77 | 1241 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 1242 | |
7f7f5316 | 1243 | fcb->flags = flags; |
0bbaf069 KG |
1244 | } |
1245 | ||
7f7f5316 | 1246 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 1247 | { |
7f7f5316 | 1248 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
1249 | fcb->vlctl = vlan_tx_tag_get(skb); |
1250 | } | |
1251 | ||
4669bc90 DH |
1252 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
1253 | struct txbd8 *base, int ring_size) | |
1254 | { | |
1255 | struct txbd8 *new_bd = bdp + stride; | |
1256 | ||
1257 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
1258 | } | |
1259 | ||
1260 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
1261 | int ring_size) | |
1262 | { | |
1263 | return skip_txbd(bdp, 1, base, ring_size); | |
1264 | } | |
1265 | ||
1da177e4 LT |
1266 | /* This is called by the kernel when a frame is ready for transmission. */ |
1267 | /* It is pointed to by the dev->hard_start_xmit function pointer */ | |
1268 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1269 | { | |
1270 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1271 | struct txfcb *fcb = NULL; |
4669bc90 | 1272 | struct txbd8 *txbdp, *txbdp_start, *base; |
5a5efed4 | 1273 | u32 lstatus; |
4669bc90 DH |
1274 | int i; |
1275 | u32 bufaddr; | |
fef6108d | 1276 | unsigned long flags; |
4669bc90 DH |
1277 | unsigned int nr_frags, length; |
1278 | ||
1279 | base = priv->tx_bd_base; | |
1280 | ||
1281 | /* total number of fragments in the SKB */ | |
1282 | nr_frags = skb_shinfo(skb)->nr_frags; | |
1283 | ||
1284 | spin_lock_irqsave(&priv->txlock, flags); | |
1285 | ||
1286 | /* check if there is space to queue this packet */ | |
1287 | if (nr_frags > priv->num_txbdfree) { | |
1288 | /* no space, stop the queue */ | |
1289 | netif_stop_queue(dev); | |
1290 | dev->stats.tx_fifo_errors++; | |
1291 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1292 | return NETDEV_TX_BUSY; | |
1293 | } | |
1da177e4 LT |
1294 | |
1295 | /* Update transmit stats */ | |
09f75cd7 | 1296 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 1297 | |
4669bc90 | 1298 | txbdp = txbdp_start = priv->cur_tx; |
1da177e4 | 1299 | |
4669bc90 DH |
1300 | if (nr_frags == 0) { |
1301 | lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1302 | } else { | |
1303 | /* Place the fragment addresses and lengths into the TxBDs */ | |
1304 | for (i = 0; i < nr_frags; i++) { | |
1305 | /* Point at the next BD, wrapping as needed */ | |
1306 | txbdp = next_txbd(txbdp, base, priv->tx_ring_size); | |
1307 | ||
1308 | length = skb_shinfo(skb)->frags[i].size; | |
1309 | ||
1310 | lstatus = txbdp->lstatus | length | | |
1311 | BD_LFLAG(TXBD_READY); | |
1312 | ||
1313 | /* Handle the last BD specially */ | |
1314 | if (i == nr_frags - 1) | |
1315 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 1316 | |
4669bc90 DH |
1317 | bufaddr = dma_map_page(&dev->dev, |
1318 | skb_shinfo(skb)->frags[i].page, | |
1319 | skb_shinfo(skb)->frags[i].page_offset, | |
1320 | length, | |
1321 | DMA_TO_DEVICE); | |
1322 | ||
1323 | /* set the TxBD length and buffer pointer */ | |
1324 | txbdp->bufPtr = bufaddr; | |
1325 | txbdp->lstatus = lstatus; | |
1326 | } | |
1327 | ||
1328 | lstatus = txbdp_start->lstatus; | |
1329 | } | |
1da177e4 | 1330 | |
0bbaf069 | 1331 | /* Set up checksumming */ |
12dea57b | 1332 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
a22823e7 | 1333 | fcb = gfar_add_fcb(skb); |
5a5efed4 | 1334 | lstatus |= BD_LFLAG(TXBD_TOE); |
0bbaf069 KG |
1335 | gfar_tx_checksum(skb, fcb); |
1336 | } | |
1337 | ||
77ecaf2d | 1338 | if (priv->vlgrp && vlan_tx_tag_present(skb)) { |
7f7f5316 | 1339 | if (unlikely(NULL == fcb)) { |
a22823e7 | 1340 | fcb = gfar_add_fcb(skb); |
5a5efed4 | 1341 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 1342 | } |
0bbaf069 KG |
1343 | |
1344 | gfar_tx_vlan(skb, fcb); | |
1345 | } | |
1346 | ||
4669bc90 | 1347 | /* setup the TxBD length and buffer pointer for the first BD */ |
1da177e4 | 1348 | priv->tx_skbuff[priv->skb_curtx] = skb; |
4669bc90 DH |
1349 | txbdp_start->bufPtr = dma_map_single(&dev->dev, skb->data, |
1350 | skb_headlen(skb), DMA_TO_DEVICE); | |
1da177e4 | 1351 | |
4669bc90 | 1352 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); |
1da177e4 | 1353 | |
4669bc90 DH |
1354 | /* |
1355 | * The powerpc-specific eieio() is used, as wmb() has too strong | |
3b6330ce SW |
1356 | * semantics (it requires synchronization between cacheable and |
1357 | * uncacheable mappings, which eieio doesn't provide and which we | |
1358 | * don't need), thus requiring a more expensive sync instruction. At | |
1359 | * some point, the set of architecture-independent barrier functions | |
1360 | * should be expanded to include weaker barriers. | |
1361 | */ | |
3b6330ce | 1362 | eieio(); |
7f7f5316 | 1363 | |
4669bc90 DH |
1364 | txbdp_start->lstatus = lstatus; |
1365 | ||
1366 | /* Update the current skb pointer to the next entry we will use | |
1367 | * (wrapping if necessary) */ | |
1368 | priv->skb_curtx = (priv->skb_curtx + 1) & | |
1369 | TX_RING_MOD_MASK(priv->tx_ring_size); | |
1370 | ||
1371 | priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size); | |
1372 | ||
1373 | /* reduce TxBD free count */ | |
1374 | priv->num_txbdfree -= (nr_frags + 1); | |
1375 | ||
1376 | dev->trans_start = jiffies; | |
1da177e4 LT |
1377 | |
1378 | /* If the next BD still needs to be cleaned up, then the bds | |
1379 | are full. We need to tell the kernel to stop sending us stuff. */ | |
4669bc90 | 1380 | if (!priv->num_txbdfree) { |
1da177e4 LT |
1381 | netif_stop_queue(dev); |
1382 | ||
09f75cd7 | 1383 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
1384 | } |
1385 | ||
1da177e4 LT |
1386 | /* Tell the DMA to go go go */ |
1387 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
1388 | ||
1389 | /* Unlock priv */ | |
fef6108d | 1390 | spin_unlock_irqrestore(&priv->txlock, flags); |
1da177e4 LT |
1391 | |
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | /* Stops the kernel queue, and halts the controller */ | |
1396 | static int gfar_close(struct net_device *dev) | |
1397 | { | |
1398 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e SH |
1399 | |
1400 | napi_disable(&priv->napi); | |
1401 | ||
ab939905 | 1402 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
1403 | stop_gfar(dev); |
1404 | ||
bb40dcbb AF |
1405 | /* Disconnect from the PHY */ |
1406 | phy_disconnect(priv->phydev); | |
1407 | priv->phydev = NULL; | |
1da177e4 LT |
1408 | |
1409 | netif_stop_queue(dev); | |
1410 | ||
1411 | return 0; | |
1412 | } | |
1413 | ||
1da177e4 | 1414 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 1415 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 1416 | { |
7f7f5316 | 1417 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
1418 | |
1419 | return 0; | |
1420 | } | |
1421 | ||
1422 | ||
0bbaf069 KG |
1423 | /* Enables and disables VLAN insertion/extraction */ |
1424 | static void gfar_vlan_rx_register(struct net_device *dev, | |
1425 | struct vlan_group *grp) | |
1426 | { | |
1427 | struct gfar_private *priv = netdev_priv(dev); | |
1428 | unsigned long flags; | |
1429 | u32 tempval; | |
1430 | ||
fef6108d | 1431 | spin_lock_irqsave(&priv->rxlock, flags); |
0bbaf069 | 1432 | |
cd1f55a5 | 1433 | priv->vlgrp = grp; |
0bbaf069 KG |
1434 | |
1435 | if (grp) { | |
1436 | /* Enable VLAN tag insertion */ | |
1437 | tempval = gfar_read(&priv->regs->tctrl); | |
1438 | tempval |= TCTRL_VLINS; | |
1439 | ||
1440 | gfar_write(&priv->regs->tctrl, tempval); | |
6aa20a22 | 1441 | |
0bbaf069 KG |
1442 | /* Enable VLAN tag extraction */ |
1443 | tempval = gfar_read(&priv->regs->rctrl); | |
1444 | tempval |= RCTRL_VLEX; | |
77ecaf2d | 1445 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); |
0bbaf069 KG |
1446 | gfar_write(&priv->regs->rctrl, tempval); |
1447 | } else { | |
1448 | /* Disable VLAN tag insertion */ | |
1449 | tempval = gfar_read(&priv->regs->tctrl); | |
1450 | tempval &= ~TCTRL_VLINS; | |
1451 | gfar_write(&priv->regs->tctrl, tempval); | |
1452 | ||
1453 | /* Disable VLAN tag extraction */ | |
1454 | tempval = gfar_read(&priv->regs->rctrl); | |
1455 | tempval &= ~RCTRL_VLEX; | |
77ecaf2d DH |
1456 | /* If parse is no longer required, then disable parser */ |
1457 | if (tempval & RCTRL_REQ_PARSER) | |
1458 | tempval |= RCTRL_PRSDEP_INIT; | |
1459 | else | |
1460 | tempval &= ~RCTRL_PRSDEP_INIT; | |
0bbaf069 KG |
1461 | gfar_write(&priv->regs->rctrl, tempval); |
1462 | } | |
1463 | ||
77ecaf2d DH |
1464 | gfar_change_mtu(dev, dev->mtu); |
1465 | ||
fef6108d | 1466 | spin_unlock_irqrestore(&priv->rxlock, flags); |
0bbaf069 KG |
1467 | } |
1468 | ||
1da177e4 LT |
1469 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
1470 | { | |
1471 | int tempsize, tempval; | |
1472 | struct gfar_private *priv = netdev_priv(dev); | |
1473 | int oldsize = priv->rx_buffer_size; | |
0bbaf069 KG |
1474 | int frame_size = new_mtu + ETH_HLEN; |
1475 | ||
77ecaf2d | 1476 | if (priv->vlgrp) |
faa89577 | 1477 | frame_size += VLAN_HLEN; |
0bbaf069 | 1478 | |
1da177e4 | 1479 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
0bbaf069 KG |
1480 | if (netif_msg_drv(priv)) |
1481 | printk(KERN_ERR "%s: Invalid MTU setting\n", | |
1482 | dev->name); | |
1da177e4 LT |
1483 | return -EINVAL; |
1484 | } | |
1485 | ||
77ecaf2d DH |
1486 | if (gfar_uses_fcb(priv)) |
1487 | frame_size += GMAC_FCB_LEN; | |
1488 | ||
1489 | frame_size += priv->padding; | |
1490 | ||
1da177e4 LT |
1491 | tempsize = |
1492 | (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + | |
1493 | INCREMENTAL_BUFFER_SIZE; | |
1494 | ||
1495 | /* Only stop and start the controller if it isn't already | |
7f7f5316 | 1496 | * stopped, and we changed something */ |
1da177e4 LT |
1497 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
1498 | stop_gfar(dev); | |
1499 | ||
1500 | priv->rx_buffer_size = tempsize; | |
1501 | ||
1502 | dev->mtu = new_mtu; | |
1503 | ||
1504 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
1505 | gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size); | |
1506 | ||
1507 | /* If the mtu is larger than the max size for standard | |
1508 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
1509 | * to allow huge frames, and to check the length */ | |
1510 | tempval = gfar_read(&priv->regs->maccfg2); | |
1511 | ||
1512 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE) | |
1513 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1514 | else | |
1515 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1516 | ||
1517 | gfar_write(&priv->regs->maccfg2, tempval); | |
1518 | ||
1519 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
1520 | startup_gfar(dev); | |
1521 | ||
1522 | return 0; | |
1523 | } | |
1524 | ||
ab939905 | 1525 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
1526 | * transmitted after a set amount of time. |
1527 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
1528 | * starting over will fix the problem. |
1529 | */ | |
1530 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 1531 | { |
ab939905 SS |
1532 | struct gfar_private *priv = container_of(work, struct gfar_private, |
1533 | reset_task); | |
1534 | struct net_device *dev = priv->dev; | |
1da177e4 LT |
1535 | |
1536 | if (dev->flags & IFF_UP) { | |
1537 | stop_gfar(dev); | |
1538 | startup_gfar(dev); | |
1539 | } | |
1540 | ||
263ba320 | 1541 | netif_tx_schedule_all(dev); |
1da177e4 LT |
1542 | } |
1543 | ||
ab939905 SS |
1544 | static void gfar_timeout(struct net_device *dev) |
1545 | { | |
1546 | struct gfar_private *priv = netdev_priv(dev); | |
1547 | ||
1548 | dev->stats.tx_errors++; | |
1549 | schedule_work(&priv->reset_task); | |
1550 | } | |
1551 | ||
1da177e4 | 1552 | /* Interrupt Handler for Transmit complete */ |
f162b9d5 | 1553 | static int gfar_clean_tx_ring(struct net_device *dev) |
1da177e4 | 1554 | { |
d080cd63 | 1555 | struct gfar_private *priv = netdev_priv(dev); |
4669bc90 DH |
1556 | struct txbd8 *bdp; |
1557 | struct txbd8 *lbdp = NULL; | |
1558 | struct txbd8 *base = priv->tx_bd_base; | |
1559 | struct sk_buff *skb; | |
1560 | int skb_dirtytx; | |
1561 | int tx_ring_size = priv->tx_ring_size; | |
1562 | int frags = 0; | |
1563 | int i; | |
d080cd63 | 1564 | int howmany = 0; |
4669bc90 | 1565 | u32 lstatus; |
1da177e4 | 1566 | |
1da177e4 | 1567 | bdp = priv->dirty_tx; |
4669bc90 | 1568 | skb_dirtytx = priv->skb_dirtytx; |
1da177e4 | 1569 | |
4669bc90 DH |
1570 | while ((skb = priv->tx_skbuff[skb_dirtytx])) { |
1571 | frags = skb_shinfo(skb)->nr_frags; | |
1572 | lbdp = skip_txbd(bdp, frags, base, tx_ring_size); | |
1da177e4 | 1573 | |
4669bc90 | 1574 | lstatus = lbdp->lstatus; |
1da177e4 | 1575 | |
4669bc90 DH |
1576 | /* Only clean completed frames */ |
1577 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
1578 | (lstatus & BD_LENGTH_MASK)) | |
1579 | break; | |
1580 | ||
1581 | dma_unmap_single(&dev->dev, | |
1582 | bdp->bufPtr, | |
1583 | bdp->length, | |
1584 | DMA_TO_DEVICE); | |
81183059 | 1585 | |
4669bc90 DH |
1586 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
1587 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 1588 | |
4669bc90 DH |
1589 | for (i = 0; i < frags; i++) { |
1590 | dma_unmap_page(&dev->dev, | |
1591 | bdp->bufPtr, | |
1592 | bdp->length, | |
1593 | DMA_TO_DEVICE); | |
1594 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
1595 | bdp = next_txbd(bdp, base, tx_ring_size); | |
1596 | } | |
1da177e4 | 1597 | |
4669bc90 DH |
1598 | dev_kfree_skb_any(skb); |
1599 | priv->tx_skbuff[skb_dirtytx] = NULL; | |
d080cd63 | 1600 | |
4669bc90 DH |
1601 | skb_dirtytx = (skb_dirtytx + 1) & |
1602 | TX_RING_MOD_MASK(tx_ring_size); | |
1603 | ||
1604 | howmany++; | |
1605 | priv->num_txbdfree += frags + 1; | |
1606 | } | |
1da177e4 | 1607 | |
4669bc90 DH |
1608 | /* If we freed a buffer, we can restart transmission, if necessary */ |
1609 | if (netif_queue_stopped(dev) && priv->num_txbdfree) | |
1610 | netif_wake_queue(dev); | |
1da177e4 | 1611 | |
4669bc90 DH |
1612 | /* Update dirty indicators */ |
1613 | priv->skb_dirtytx = skb_dirtytx; | |
1614 | priv->dirty_tx = bdp; | |
1da177e4 | 1615 | |
d080cd63 DH |
1616 | dev->stats.tx_packets += howmany; |
1617 | ||
1618 | return howmany; | |
1619 | } | |
1620 | ||
8c7396ae | 1621 | static void gfar_schedule_cleanup(struct net_device *dev) |
d080cd63 | 1622 | { |
d080cd63 | 1623 | struct gfar_private *priv = netdev_priv(dev); |
a6d0b91a AV |
1624 | unsigned long flags; |
1625 | ||
1626 | spin_lock_irqsave(&priv->txlock, flags); | |
1627 | spin_lock(&priv->rxlock); | |
1628 | ||
288379f0 | 1629 | if (napi_schedule_prep(&priv->napi)) { |
8c7396ae | 1630 | gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED); |
288379f0 | 1631 | __napi_schedule(&priv->napi); |
2f448911 | 1632 | } |
a6d0b91a AV |
1633 | |
1634 | spin_unlock(&priv->rxlock); | |
1635 | spin_unlock_irqrestore(&priv->txlock, flags); | |
8c7396ae | 1636 | } |
1da177e4 | 1637 | |
8c7396ae DH |
1638 | /* Interrupt Handler for Transmit complete */ |
1639 | static irqreturn_t gfar_transmit(int irq, void *dev_id) | |
1640 | { | |
1641 | gfar_schedule_cleanup((struct net_device *)dev_id); | |
1da177e4 LT |
1642 | return IRQ_HANDLED; |
1643 | } | |
1644 | ||
815b97c6 AF |
1645 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, |
1646 | struct sk_buff *skb) | |
1647 | { | |
1648 | struct gfar_private *priv = netdev_priv(dev); | |
5a5efed4 | 1649 | u32 lstatus; |
815b97c6 AF |
1650 | |
1651 | bdp->bufPtr = dma_map_single(&dev->dev, skb->data, | |
1652 | priv->rx_buffer_size, DMA_FROM_DEVICE); | |
1653 | ||
5a5efed4 | 1654 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); |
815b97c6 AF |
1655 | |
1656 | if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1) | |
5a5efed4 | 1657 | lstatus |= BD_LFLAG(RXBD_WRAP); |
815b97c6 AF |
1658 | |
1659 | eieio(); | |
1660 | ||
5a5efed4 | 1661 | bdp->lstatus = lstatus; |
815b97c6 AF |
1662 | } |
1663 | ||
1664 | ||
1665 | struct sk_buff * gfar_new_skb(struct net_device *dev) | |
1da177e4 | 1666 | { |
7f7f5316 | 1667 | unsigned int alignamount; |
1da177e4 LT |
1668 | struct gfar_private *priv = netdev_priv(dev); |
1669 | struct sk_buff *skb = NULL; | |
1da177e4 LT |
1670 | |
1671 | /* We have to allocate the skb, so keep trying till we succeed */ | |
815b97c6 | 1672 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
1da177e4 | 1673 | |
815b97c6 | 1674 | if (!skb) |
1da177e4 LT |
1675 | return NULL; |
1676 | ||
7f7f5316 | 1677 | alignamount = RXBUF_ALIGNMENT - |
bea3348e | 1678 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)); |
7f7f5316 | 1679 | |
1da177e4 LT |
1680 | /* We need the data buffer to be aligned properly. We will reserve |
1681 | * as many bytes as needed to align the data properly | |
1682 | */ | |
7f7f5316 | 1683 | skb_reserve(skb, alignamount); |
1da177e4 | 1684 | |
1da177e4 LT |
1685 | return skb; |
1686 | } | |
1687 | ||
298e1a9e | 1688 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 1689 | { |
298e1a9e | 1690 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 1691 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
1692 | struct gfar_extra_stats *estats = &priv->extra_stats; |
1693 | ||
1694 | /* If the packet was truncated, none of the other errors | |
1695 | * matter */ | |
1696 | if (status & RXBD_TRUNCATED) { | |
1697 | stats->rx_length_errors++; | |
1698 | ||
1699 | estats->rx_trunc++; | |
1700 | ||
1701 | return; | |
1702 | } | |
1703 | /* Count the errors, if there were any */ | |
1704 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
1705 | stats->rx_length_errors++; | |
1706 | ||
1707 | if (status & RXBD_LARGE) | |
1708 | estats->rx_large++; | |
1709 | else | |
1710 | estats->rx_short++; | |
1711 | } | |
1712 | if (status & RXBD_NONOCTET) { | |
1713 | stats->rx_frame_errors++; | |
1714 | estats->rx_nonoctet++; | |
1715 | } | |
1716 | if (status & RXBD_CRCERR) { | |
1717 | estats->rx_crcerr++; | |
1718 | stats->rx_crc_errors++; | |
1719 | } | |
1720 | if (status & RXBD_OVERRUN) { | |
1721 | estats->rx_overrun++; | |
1722 | stats->rx_crc_errors++; | |
1723 | } | |
1724 | } | |
1725 | ||
7d12e780 | 1726 | irqreturn_t gfar_receive(int irq, void *dev_id) |
1da177e4 | 1727 | { |
8c7396ae | 1728 | gfar_schedule_cleanup((struct net_device *)dev_id); |
1da177e4 LT |
1729 | return IRQ_HANDLED; |
1730 | } | |
1731 | ||
0bbaf069 KG |
1732 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
1733 | { | |
1734 | /* If valid headers were found, and valid sums | |
1735 | * were verified, then we tell the kernel that no | |
1736 | * checksumming is necessary. Otherwise, it is */ | |
7f7f5316 | 1737 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
1738 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1739 | else | |
1740 | skb->ip_summed = CHECKSUM_NONE; | |
1741 | } | |
1742 | ||
1743 | ||
1da177e4 LT |
1744 | /* gfar_process_frame() -- handle one incoming packet if skb |
1745 | * isn't NULL. */ | |
1746 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, | |
2c2db48a | 1747 | int amount_pull) |
1da177e4 LT |
1748 | { |
1749 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1750 | struct rxfcb *fcb = NULL; |
1da177e4 | 1751 | |
2c2db48a | 1752 | int ret; |
1da177e4 | 1753 | |
2c2db48a DH |
1754 | /* fcb is at the beginning if exists */ |
1755 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 1756 | |
2c2db48a DH |
1757 | /* Remove the FCB from the skb */ |
1758 | /* Remove the padded bytes, if there are any */ | |
1759 | if (amount_pull) | |
1760 | skb_pull(skb, amount_pull); | |
0bbaf069 | 1761 | |
2c2db48a DH |
1762 | if (priv->rx_csum_enable) |
1763 | gfar_rx_checksum(skb, fcb); | |
0bbaf069 | 1764 | |
2c2db48a DH |
1765 | /* Tell the skb what kind of packet this is */ |
1766 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 1767 | |
2c2db48a DH |
1768 | /* Send the packet up the stack */ |
1769 | if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) | |
1770 | ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl); | |
1771 | else | |
1772 | ret = netif_receive_skb(skb); | |
0bbaf069 | 1773 | |
2c2db48a DH |
1774 | if (NET_RX_DROP == ret) |
1775 | priv->extra_stats.kernel_dropped++; | |
1da177e4 LT |
1776 | |
1777 | return 0; | |
1778 | } | |
1779 | ||
1780 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
0bbaf069 | 1781 | * until the budget/quota has been reached. Returns the number |
1da177e4 LT |
1782 | * of frames handled |
1783 | */ | |
0bbaf069 | 1784 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit) |
1da177e4 | 1785 | { |
31de198b | 1786 | struct rxbd8 *bdp, *base; |
1da177e4 | 1787 | struct sk_buff *skb; |
2c2db48a DH |
1788 | int pkt_len; |
1789 | int amount_pull; | |
1da177e4 LT |
1790 | int howmany = 0; |
1791 | struct gfar_private *priv = netdev_priv(dev); | |
1792 | ||
1793 | /* Get the first full descriptor */ | |
1794 | bdp = priv->cur_rx; | |
31de198b | 1795 | base = priv->rx_bd_base; |
1da177e4 | 1796 | |
2c2db48a DH |
1797 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) + |
1798 | priv->padding; | |
1799 | ||
1da177e4 | 1800 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 1801 | struct sk_buff *newskb; |
3b6330ce | 1802 | rmb(); |
815b97c6 AF |
1803 | |
1804 | /* Add another skb for the future */ | |
1805 | newskb = gfar_new_skb(dev); | |
1806 | ||
1da177e4 LT |
1807 | skb = priv->rx_skbuff[priv->skb_currx]; |
1808 | ||
81183059 AF |
1809 | dma_unmap_single(&priv->dev->dev, bdp->bufPtr, |
1810 | priv->rx_buffer_size, DMA_FROM_DEVICE); | |
1811 | ||
815b97c6 AF |
1812 | /* We drop the frame if we failed to allocate a new buffer */ |
1813 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
1814 | bdp->status & RXBD_ERR)) { | |
1815 | count_errors(bdp->status, dev); | |
1816 | ||
1817 | if (unlikely(!newskb)) | |
1818 | newskb = skb; | |
8882d9a6 | 1819 | else if (skb) |
815b97c6 | 1820 | dev_kfree_skb_any(skb); |
815b97c6 | 1821 | } else { |
1da177e4 | 1822 | /* Increment the number of packets */ |
09f75cd7 | 1823 | dev->stats.rx_packets++; |
1da177e4 LT |
1824 | howmany++; |
1825 | ||
2c2db48a DH |
1826 | if (likely(skb)) { |
1827 | pkt_len = bdp->length - ETH_FCS_LEN; | |
1828 | /* Remove the FCS from the packet length */ | |
1829 | skb_put(skb, pkt_len); | |
1830 | dev->stats.rx_bytes += pkt_len; | |
1da177e4 | 1831 | |
1577ecef AF |
1832 | if (in_irq() || irqs_disabled()) |
1833 | printk("Interrupt problem!\n"); | |
2c2db48a DH |
1834 | gfar_process_frame(dev, skb, amount_pull); |
1835 | ||
1836 | } else { | |
1837 | if (netif_msg_rx_err(priv)) | |
1838 | printk(KERN_WARNING | |
1839 | "%s: Missing skb!\n", dev->name); | |
1840 | dev->stats.rx_dropped++; | |
1841 | priv->extra_stats.rx_skbmissing++; | |
1842 | } | |
1da177e4 | 1843 | |
1da177e4 LT |
1844 | } |
1845 | ||
815b97c6 | 1846 | priv->rx_skbuff[priv->skb_currx] = newskb; |
1da177e4 | 1847 | |
815b97c6 AF |
1848 | /* Setup the new bdp */ |
1849 | gfar_new_rxbdp(dev, bdp, newskb); | |
1da177e4 LT |
1850 | |
1851 | /* Update to the next pointer */ | |
31de198b | 1852 | bdp = next_bd(bdp, base, priv->rx_ring_size); |
1da177e4 LT |
1853 | |
1854 | /* update to point at the next skb */ | |
1855 | priv->skb_currx = | |
815b97c6 AF |
1856 | (priv->skb_currx + 1) & |
1857 | RX_RING_MOD_MASK(priv->rx_ring_size); | |
1da177e4 LT |
1858 | } |
1859 | ||
1860 | /* Update the current rxbd pointer to be the next one */ | |
1861 | priv->cur_rx = bdp; | |
1862 | ||
1da177e4 LT |
1863 | return howmany; |
1864 | } | |
1865 | ||
bea3348e | 1866 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1867 | { |
bea3348e SH |
1868 | struct gfar_private *priv = container_of(napi, struct gfar_private, napi); |
1869 | struct net_device *dev = priv->dev; | |
42199884 AF |
1870 | int tx_cleaned = 0; |
1871 | int rx_cleaned = 0; | |
d080cd63 DH |
1872 | unsigned long flags; |
1873 | ||
8c7396ae DH |
1874 | /* Clear IEVENT, so interrupts aren't called again |
1875 | * because of the packets that have already arrived */ | |
1876 | gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); | |
1877 | ||
d080cd63 DH |
1878 | /* If we fail to get the lock, don't bother with the TX BDs */ |
1879 | if (spin_trylock_irqsave(&priv->txlock, flags)) { | |
42199884 | 1880 | tx_cleaned = gfar_clean_tx_ring(dev); |
d080cd63 DH |
1881 | spin_unlock_irqrestore(&priv->txlock, flags); |
1882 | } | |
1da177e4 | 1883 | |
42199884 | 1884 | rx_cleaned = gfar_clean_rx_ring(dev, budget); |
1da177e4 | 1885 | |
42199884 AF |
1886 | if (tx_cleaned) |
1887 | return budget; | |
1888 | ||
1889 | if (rx_cleaned < budget) { | |
288379f0 | 1890 | napi_complete(napi); |
1da177e4 LT |
1891 | |
1892 | /* Clear the halt bit in RSTAT */ | |
1893 | gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT); | |
1894 | ||
1895 | gfar_write(&priv->regs->imask, IMASK_DEFAULT); | |
1896 | ||
1897 | /* If we are coalescing interrupts, update the timer */ | |
1898 | /* Otherwise, clear it */ | |
2f448911 AF |
1899 | if (likely(priv->rxcoalescing)) { |
1900 | gfar_write(&priv->regs->rxic, 0); | |
b46a8454 | 1901 | gfar_write(&priv->regs->rxic, priv->rxic); |
2f448911 | 1902 | } |
8c7396ae DH |
1903 | if (likely(priv->txcoalescing)) { |
1904 | gfar_write(&priv->regs->txic, 0); | |
1905 | gfar_write(&priv->regs->txic, priv->txic); | |
1906 | } | |
1da177e4 LT |
1907 | } |
1908 | ||
42199884 | 1909 | return rx_cleaned; |
1da177e4 | 1910 | } |
1da177e4 | 1911 | |
f2d71c2d VW |
1912 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1913 | /* | |
1914 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1915 | * without having to re-enable interrupts. It's not called while | |
1916 | * the interrupt routine is executing. | |
1917 | */ | |
1918 | static void gfar_netpoll(struct net_device *dev) | |
1919 | { | |
1920 | struct gfar_private *priv = netdev_priv(dev); | |
1921 | ||
1922 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 1923 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
f2d71c2d VW |
1924 | disable_irq(priv->interruptTransmit); |
1925 | disable_irq(priv->interruptReceive); | |
1926 | disable_irq(priv->interruptError); | |
1927 | gfar_interrupt(priv->interruptTransmit, dev); | |
1928 | enable_irq(priv->interruptError); | |
1929 | enable_irq(priv->interruptReceive); | |
1930 | enable_irq(priv->interruptTransmit); | |
1931 | } else { | |
1932 | disable_irq(priv->interruptTransmit); | |
1933 | gfar_interrupt(priv->interruptTransmit, dev); | |
1934 | enable_irq(priv->interruptTransmit); | |
1935 | } | |
1936 | } | |
1937 | #endif | |
1938 | ||
1da177e4 | 1939 | /* The interrupt handler for devices with one interrupt */ |
7d12e780 | 1940 | static irqreturn_t gfar_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1941 | { |
1942 | struct net_device *dev = dev_id; | |
1943 | struct gfar_private *priv = netdev_priv(dev); | |
1944 | ||
1945 | /* Save ievent for future reference */ | |
1946 | u32 events = gfar_read(&priv->regs->ievent); | |
1947 | ||
1da177e4 | 1948 | /* Check for reception */ |
538cc7ee | 1949 | if (events & IEVENT_RX_MASK) |
7d12e780 | 1950 | gfar_receive(irq, dev_id); |
1da177e4 LT |
1951 | |
1952 | /* Check for transmit completion */ | |
538cc7ee | 1953 | if (events & IEVENT_TX_MASK) |
7d12e780 | 1954 | gfar_transmit(irq, dev_id); |
1da177e4 | 1955 | |
538cc7ee SS |
1956 | /* Check for errors */ |
1957 | if (events & IEVENT_ERR_MASK) | |
1958 | gfar_error(irq, dev_id); | |
1da177e4 LT |
1959 | |
1960 | return IRQ_HANDLED; | |
1961 | } | |
1962 | ||
1da177e4 LT |
1963 | /* Called every time the controller might need to be made |
1964 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 1965 | * information through variables in the phydev structure, and this |
1da177e4 LT |
1966 | * function converts those variables into the appropriate |
1967 | * register values, and can bring down the device if needed. | |
1968 | */ | |
1969 | static void adjust_link(struct net_device *dev) | |
1970 | { | |
1971 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 1972 | struct gfar __iomem *regs = priv->regs; |
bb40dcbb AF |
1973 | unsigned long flags; |
1974 | struct phy_device *phydev = priv->phydev; | |
1975 | int new_state = 0; | |
1976 | ||
fef6108d | 1977 | spin_lock_irqsave(&priv->txlock, flags); |
bb40dcbb AF |
1978 | if (phydev->link) { |
1979 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 1980 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 1981 | |
1da177e4 LT |
1982 | /* Now we make sure that we can be in full duplex mode. |
1983 | * If not, we operate in half-duplex mode. */ | |
bb40dcbb AF |
1984 | if (phydev->duplex != priv->oldduplex) { |
1985 | new_state = 1; | |
1986 | if (!(phydev->duplex)) | |
1da177e4 | 1987 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 1988 | else |
1da177e4 | 1989 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 1990 | |
bb40dcbb | 1991 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
1992 | } |
1993 | ||
bb40dcbb AF |
1994 | if (phydev->speed != priv->oldspeed) { |
1995 | new_state = 1; | |
1996 | switch (phydev->speed) { | |
1da177e4 | 1997 | case 1000: |
1da177e4 LT |
1998 | tempval = |
1999 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2000 | |
2001 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2002 | break; |
2003 | case 100: | |
2004 | case 10: | |
1da177e4 LT |
2005 | tempval = |
2006 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2007 | |
2008 | /* Reduced mode distinguishes | |
2009 | * between 10 and 100 */ | |
2010 | if (phydev->speed == SPEED_100) | |
2011 | ecntrl |= ECNTRL_R100; | |
2012 | else | |
2013 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2014 | break; |
2015 | default: | |
0bbaf069 KG |
2016 | if (netif_msg_link(priv)) |
2017 | printk(KERN_WARNING | |
bb40dcbb AF |
2018 | "%s: Ack! Speed (%d) is not 10/100/1000!\n", |
2019 | dev->name, phydev->speed); | |
1da177e4 LT |
2020 | break; |
2021 | } | |
2022 | ||
bb40dcbb | 2023 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
2024 | } |
2025 | ||
bb40dcbb | 2026 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 2027 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 2028 | |
1da177e4 | 2029 | if (!priv->oldlink) { |
bb40dcbb | 2030 | new_state = 1; |
1da177e4 | 2031 | priv->oldlink = 1; |
1da177e4 | 2032 | } |
bb40dcbb AF |
2033 | } else if (priv->oldlink) { |
2034 | new_state = 1; | |
2035 | priv->oldlink = 0; | |
2036 | priv->oldspeed = 0; | |
2037 | priv->oldduplex = -1; | |
1da177e4 | 2038 | } |
1da177e4 | 2039 | |
bb40dcbb AF |
2040 | if (new_state && netif_msg_link(priv)) |
2041 | phy_print_status(phydev); | |
2042 | ||
fef6108d | 2043 | spin_unlock_irqrestore(&priv->txlock, flags); |
bb40dcbb | 2044 | } |
1da177e4 LT |
2045 | |
2046 | /* Update the hash table based on the current list of multicast | |
2047 | * addresses we subscribe to. Also, change the promiscuity of | |
2048 | * the device based on the flags (this function is called | |
2049 | * whenever dev->flags is changed */ | |
2050 | static void gfar_set_multi(struct net_device *dev) | |
2051 | { | |
2052 | struct dev_mc_list *mc_ptr; | |
2053 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 2054 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
2055 | u32 tempval; |
2056 | ||
2057 | if(dev->flags & IFF_PROMISC) { | |
1da177e4 LT |
2058 | /* Set RCTRL to PROM */ |
2059 | tempval = gfar_read(®s->rctrl); | |
2060 | tempval |= RCTRL_PROM; | |
2061 | gfar_write(®s->rctrl, tempval); | |
2062 | } else { | |
2063 | /* Set RCTRL to not PROM */ | |
2064 | tempval = gfar_read(®s->rctrl); | |
2065 | tempval &= ~(RCTRL_PROM); | |
2066 | gfar_write(®s->rctrl, tempval); | |
2067 | } | |
6aa20a22 | 2068 | |
1da177e4 LT |
2069 | if(dev->flags & IFF_ALLMULTI) { |
2070 | /* Set the hash to rx all multicast frames */ | |
0bbaf069 KG |
2071 | gfar_write(®s->igaddr0, 0xffffffff); |
2072 | gfar_write(®s->igaddr1, 0xffffffff); | |
2073 | gfar_write(®s->igaddr2, 0xffffffff); | |
2074 | gfar_write(®s->igaddr3, 0xffffffff); | |
2075 | gfar_write(®s->igaddr4, 0xffffffff); | |
2076 | gfar_write(®s->igaddr5, 0xffffffff); | |
2077 | gfar_write(®s->igaddr6, 0xffffffff); | |
2078 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
2079 | gfar_write(®s->gaddr0, 0xffffffff); |
2080 | gfar_write(®s->gaddr1, 0xffffffff); | |
2081 | gfar_write(®s->gaddr2, 0xffffffff); | |
2082 | gfar_write(®s->gaddr3, 0xffffffff); | |
2083 | gfar_write(®s->gaddr4, 0xffffffff); | |
2084 | gfar_write(®s->gaddr5, 0xffffffff); | |
2085 | gfar_write(®s->gaddr6, 0xffffffff); | |
2086 | gfar_write(®s->gaddr7, 0xffffffff); | |
2087 | } else { | |
7f7f5316 AF |
2088 | int em_num; |
2089 | int idx; | |
2090 | ||
1da177e4 | 2091 | /* zero out the hash */ |
0bbaf069 KG |
2092 | gfar_write(®s->igaddr0, 0x0); |
2093 | gfar_write(®s->igaddr1, 0x0); | |
2094 | gfar_write(®s->igaddr2, 0x0); | |
2095 | gfar_write(®s->igaddr3, 0x0); | |
2096 | gfar_write(®s->igaddr4, 0x0); | |
2097 | gfar_write(®s->igaddr5, 0x0); | |
2098 | gfar_write(®s->igaddr6, 0x0); | |
2099 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
2100 | gfar_write(®s->gaddr0, 0x0); |
2101 | gfar_write(®s->gaddr1, 0x0); | |
2102 | gfar_write(®s->gaddr2, 0x0); | |
2103 | gfar_write(®s->gaddr3, 0x0); | |
2104 | gfar_write(®s->gaddr4, 0x0); | |
2105 | gfar_write(®s->gaddr5, 0x0); | |
2106 | gfar_write(®s->gaddr6, 0x0); | |
2107 | gfar_write(®s->gaddr7, 0x0); | |
2108 | ||
7f7f5316 AF |
2109 | /* If we have extended hash tables, we need to |
2110 | * clear the exact match registers to prepare for | |
2111 | * setting them */ | |
2112 | if (priv->extended_hash) { | |
2113 | em_num = GFAR_EM_NUM + 1; | |
2114 | gfar_clear_exact_match(dev); | |
2115 | idx = 1; | |
2116 | } else { | |
2117 | idx = 0; | |
2118 | em_num = 0; | |
2119 | } | |
2120 | ||
1da177e4 LT |
2121 | if(dev->mc_count == 0) |
2122 | return; | |
2123 | ||
2124 | /* Parse the list, and set the appropriate bits */ | |
2125 | for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | |
7f7f5316 AF |
2126 | if (idx < em_num) { |
2127 | gfar_set_mac_for_addr(dev, idx, | |
2128 | mc_ptr->dmi_addr); | |
2129 | idx++; | |
2130 | } else | |
2131 | gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr); | |
1da177e4 LT |
2132 | } |
2133 | } | |
2134 | ||
2135 | return; | |
2136 | } | |
2137 | ||
7f7f5316 AF |
2138 | |
2139 | /* Clears each of the exact match registers to zero, so they | |
2140 | * don't interfere with normal reception */ | |
2141 | static void gfar_clear_exact_match(struct net_device *dev) | |
2142 | { | |
2143 | int idx; | |
2144 | u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0}; | |
2145 | ||
2146 | for(idx = 1;idx < GFAR_EM_NUM + 1;idx++) | |
2147 | gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr); | |
2148 | } | |
2149 | ||
1da177e4 LT |
2150 | /* Set the appropriate hash bit for the given addr */ |
2151 | /* The algorithm works like so: | |
2152 | * 1) Take the Destination Address (ie the multicast address), and | |
2153 | * do a CRC on it (little endian), and reverse the bits of the | |
2154 | * result. | |
2155 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
2156 | * table. The table is controlled through 8 32-bit registers: | |
2157 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
2158 | * gaddr7. This means that the 3 most significant bits in the | |
2159 | * hash index which gaddr register to use, and the 5 other bits | |
2160 | * indicate which bit (assuming an IBM numbering scheme, which | |
2161 | * for PowerPC (tm) is usually the case) in the register holds | |
2162 | * the entry. */ | |
2163 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) | |
2164 | { | |
2165 | u32 tempval; | |
2166 | struct gfar_private *priv = netdev_priv(dev); | |
1da177e4 | 2167 | u32 result = ether_crc(MAC_ADDR_LEN, addr); |
0bbaf069 KG |
2168 | int width = priv->hash_width; |
2169 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
2170 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
2171 | u32 value = (1 << (31-whichbit)); |
2172 | ||
0bbaf069 | 2173 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 2174 | tempval |= value; |
0bbaf069 | 2175 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
2176 | |
2177 | return; | |
2178 | } | |
2179 | ||
7f7f5316 AF |
2180 | |
2181 | /* There are multiple MAC Address register pairs on some controllers | |
2182 | * This function sets the numth pair to a given address | |
2183 | */ | |
2184 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr) | |
2185 | { | |
2186 | struct gfar_private *priv = netdev_priv(dev); | |
2187 | int idx; | |
2188 | char tmpbuf[MAC_ADDR_LEN]; | |
2189 | u32 tempval; | |
cc8c6e37 | 2190 | u32 __iomem *macptr = &priv->regs->macstnaddr1; |
7f7f5316 AF |
2191 | |
2192 | macptr += num*2; | |
2193 | ||
2194 | /* Now copy it into the mac registers backwards, cuz */ | |
2195 | /* little endian is silly */ | |
2196 | for (idx = 0; idx < MAC_ADDR_LEN; idx++) | |
2197 | tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx]; | |
2198 | ||
2199 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
2200 | ||
2201 | tempval = *((u32 *) (tmpbuf + 4)); | |
2202 | ||
2203 | gfar_write(macptr+1, tempval); | |
2204 | } | |
2205 | ||
1da177e4 | 2206 | /* GFAR error interrupt handler */ |
7d12e780 | 2207 | static irqreturn_t gfar_error(int irq, void *dev_id) |
1da177e4 LT |
2208 | { |
2209 | struct net_device *dev = dev_id; | |
2210 | struct gfar_private *priv = netdev_priv(dev); | |
2211 | ||
2212 | /* Save ievent for future reference */ | |
2213 | u32 events = gfar_read(&priv->regs->ievent); | |
2214 | ||
2215 | /* Clear IEVENT */ | |
d87eb127 SW |
2216 | gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK); |
2217 | ||
2218 | /* Magic Packet is not an error. */ | |
b31a1d8b | 2219 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
2220 | (events & IEVENT_MAG)) |
2221 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
2222 | |
2223 | /* Hmm... */ | |
0bbaf069 KG |
2224 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
2225 | printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
538cc7ee | 2226 | dev->name, events, gfar_read(&priv->regs->imask)); |
1da177e4 LT |
2227 | |
2228 | /* Update the error counters */ | |
2229 | if (events & IEVENT_TXE) { | |
09f75cd7 | 2230 | dev->stats.tx_errors++; |
1da177e4 LT |
2231 | |
2232 | if (events & IEVENT_LC) | |
09f75cd7 | 2233 | dev->stats.tx_window_errors++; |
1da177e4 | 2234 | if (events & IEVENT_CRL) |
09f75cd7 | 2235 | dev->stats.tx_aborted_errors++; |
1da177e4 | 2236 | if (events & IEVENT_XFUN) { |
0bbaf069 | 2237 | if (netif_msg_tx_err(priv)) |
538cc7ee SS |
2238 | printk(KERN_DEBUG "%s: TX FIFO underrun, " |
2239 | "packet dropped.\n", dev->name); | |
09f75cd7 | 2240 | dev->stats.tx_dropped++; |
1da177e4 LT |
2241 | priv->extra_stats.tx_underrun++; |
2242 | ||
2243 | /* Reactivate the Tx Queues */ | |
2244 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
2245 | } | |
0bbaf069 KG |
2246 | if (netif_msg_tx_err(priv)) |
2247 | printk(KERN_DEBUG "%s: Transmit Error\n", dev->name); | |
1da177e4 LT |
2248 | } |
2249 | if (events & IEVENT_BSY) { | |
09f75cd7 | 2250 | dev->stats.rx_errors++; |
1da177e4 LT |
2251 | priv->extra_stats.rx_bsy++; |
2252 | ||
7d12e780 | 2253 | gfar_receive(irq, dev_id); |
1da177e4 | 2254 | |
0bbaf069 | 2255 | if (netif_msg_rx_err(priv)) |
538cc7ee SS |
2256 | printk(KERN_DEBUG "%s: busy error (rstat: %x)\n", |
2257 | dev->name, gfar_read(&priv->regs->rstat)); | |
1da177e4 LT |
2258 | } |
2259 | if (events & IEVENT_BABR) { | |
09f75cd7 | 2260 | dev->stats.rx_errors++; |
1da177e4 LT |
2261 | priv->extra_stats.rx_babr++; |
2262 | ||
0bbaf069 | 2263 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2264 | printk(KERN_DEBUG "%s: babbling RX error\n", dev->name); |
1da177e4 LT |
2265 | } |
2266 | if (events & IEVENT_EBERR) { | |
2267 | priv->extra_stats.eberr++; | |
0bbaf069 | 2268 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2269 | printk(KERN_DEBUG "%s: bus error\n", dev->name); |
1da177e4 | 2270 | } |
0bbaf069 | 2271 | if ((events & IEVENT_RXC) && netif_msg_rx_status(priv)) |
538cc7ee | 2272 | printk(KERN_DEBUG "%s: control frame\n", dev->name); |
1da177e4 LT |
2273 | |
2274 | if (events & IEVENT_BABT) { | |
2275 | priv->extra_stats.tx_babt++; | |
0bbaf069 | 2276 | if (netif_msg_tx_err(priv)) |
538cc7ee | 2277 | printk(KERN_DEBUG "%s: babbling TX error\n", dev->name); |
1da177e4 LT |
2278 | } |
2279 | return IRQ_HANDLED; | |
2280 | } | |
2281 | ||
72abb461 KS |
2282 | /* work with hotplug and coldplug */ |
2283 | MODULE_ALIAS("platform:fsl-gianfar"); | |
2284 | ||
b31a1d8b AF |
2285 | static struct of_device_id gfar_match[] = |
2286 | { | |
2287 | { | |
2288 | .type = "network", | |
2289 | .compatible = "gianfar", | |
2290 | }, | |
2291 | {}, | |
2292 | }; | |
2293 | ||
1da177e4 | 2294 | /* Structure for a device driver */ |
b31a1d8b AF |
2295 | static struct of_platform_driver gfar_driver = { |
2296 | .name = "fsl-gianfar", | |
2297 | .match_table = gfar_match, | |
2298 | ||
1da177e4 LT |
2299 | .probe = gfar_probe, |
2300 | .remove = gfar_remove, | |
d87eb127 SW |
2301 | .suspend = gfar_suspend, |
2302 | .resume = gfar_resume, | |
1da177e4 LT |
2303 | }; |
2304 | ||
2305 | static int __init gfar_init(void) | |
2306 | { | |
1577ecef | 2307 | return of_register_platform_driver(&gfar_driver); |
1da177e4 LT |
2308 | } |
2309 | ||
2310 | static void __exit gfar_exit(void) | |
2311 | { | |
b31a1d8b | 2312 | of_unregister_platform_driver(&gfar_driver); |
1da177e4 LT |
2313 | } |
2314 | ||
2315 | module_init(gfar_init); | |
2316 | module_exit(gfar_exit); | |
2317 |