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FEC: Fix kernel panic in fec_set_mac_address.
[net-next-2.6.git] / drivers / net / gianfar.c
CommitLineData
0bbaf069 1/*
1da177e4
LT		 2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
a12f801d 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 12 *
a12f801d
SG		 13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
0bbaf069 28 *
b31a1d8b
AF		 29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
0bbaf069 39 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
bb40dcbb 43 * of frames or amount of time have passed). In NAPI, the
1da177e4 44 * interrupt handler will signal there is work to be done, and
0aa1538f 45 * exit. This method will start at the last known empty
0bbaf069 46 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
1da177e4 65#include <linux/kernel.h>
1da177e4
LT		 66#include <linux/string.h>
67#include <linux/errno.h>
bb40dcbb 68#include <linux/unistd.h>
1da177e4
LT		 69#include <linux/slab.h>
70#include <linux/interrupt.h>
71#include <linux/init.h>
72#include <linux/delay.h>
73#include <linux/netdevice.h>
74#include <linux/etherdevice.h>
75#include <linux/skbuff.h>
0bbaf069 76#include <linux/if_vlan.h>
1da177e4
LT		 77#include <linux/spinlock.h>
78#include <linux/mm.h>
fe192a49 79#include <linux/of_mdio.h>
b31a1d8b 80#include <linux/of_platform.h>
0bbaf069
KG		 81#include <linux/ip.h>
82#include <linux/tcp.h>
83#include <linux/udp.h>
9c07b884 84#include <linux/in.h>
1da177e4
LT		 85
86#include <asm/io.h>
87#include <asm/irq.h>
88#include <asm/uaccess.h>
89#include <linux/module.h>
1da177e4
LT		 90#include <linux/dma-mapping.h>
91#include <linux/crc32.h>
bb40dcbb
AF		 92#include <linux/mii.h>
93#include <linux/phy.h>
b31a1d8b
AF		 94#include <linux/phy_fixed.h>
95#include <linux/of.h>
1da177e4
LT		 96
97#include "gianfar.h"
1577ecef 98#include "fsl_pq_mdio.h"
1da177e4
LT		 99
100#define TX_TIMEOUT (1*HZ)
1da177e4
LT		 101#undef BRIEF_GFAR_ERRORS
102#undef VERBOSE_GFAR_ERRORS
103
1da177e4 104const char gfar_driver_name[] = "Gianfar Ethernet";
7f7f5316 105const char gfar_driver_version[] = "1.3";
1da177e4 106
1da177e4
LT		 107static int gfar_enet_open(struct net_device *dev);
108static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 109static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 110static void gfar_timeout(struct net_device *dev);
111static int gfar_close(struct net_device *dev);
815b97c6 112struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 113static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6 114 struct sk_buff *skb);
1da177e4
LT		 115static int gfar_set_mac_address(struct net_device *dev);
116static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 117static irqreturn_t gfar_error(int irq, void *dev_id);
118static irqreturn_t gfar_transmit(int irq, void *dev_id);
119static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 120static void adjust_link(struct net_device *dev);
121static void init_registers(struct net_device *dev);
122static int init_phy(struct net_device *dev);
b31a1d8b
AF		 123static int gfar_probe(struct of_device *ofdev,
124 const struct of_device_id *match);
125static int gfar_remove(struct of_device *ofdev);
bb40dcbb 126static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 127static void gfar_set_multi(struct net_device *dev);
128static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 129static void gfar_configure_serdes(struct net_device *dev);
bea3348e 130static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 131#ifdef CONFIG_NET_POLL_CONTROLLER
132static void gfar_netpoll(struct net_device *dev);
133#endif
a12f801d
SG		 134int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a
DH		 136static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 int amount_pull);
0bbaf069
KG		 138static void gfar_vlan_rx_register(struct net_device *netdev,
139 struct vlan_group *grp);
7f7f5316 140void gfar_halt(struct net_device *dev);
d87eb127 141static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 142void gfar_start(struct net_device *dev);
143static void gfar_clear_exact_match(struct net_device *dev);
144static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
26ccfc37 145static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 146
1da177e4
LT		 147MODULE_AUTHOR("Freescale Semiconductor, Inc");
148MODULE_DESCRIPTION("Gianfar Ethernet Driver");
149MODULE_LICENSE("GPL");
150
a12f801d 151static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 152 dma_addr_t buf)
153{
8a102fe0
AV		 154 u32 lstatus;
155
156 bdp->bufPtr = buf;
157
158 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 159 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 160 lstatus |= BD_LFLAG(RXBD_WRAP);
161
162 eieio();
163
164 bdp->lstatus = lstatus;
165}
166
8728327e 167static int gfar_init_bds(struct net_device *ndev)
826aa4a0 168{
8728327e 169 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 170 struct gfar_priv_tx_q *tx_queue = NULL;
171 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 172 struct txbd8 *txbdp;
173 struct rxbd8 *rxbdp;
fba4ed03 174 int i, j;
a12f801d 175
fba4ed03
SG		 176 for (i = 0; i < priv->num_tx_queues; i++) {
177 tx_queue = priv->tx_queue[i];
178 /* Initialize some variables in our dev structure */
179 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
180 tx_queue->dirty_tx = tx_queue->tx_bd_base;
181 tx_queue->cur_tx = tx_queue->tx_bd_base;
182 tx_queue->skb_curtx = 0;
183 tx_queue->skb_dirtytx = 0;
184
185 /* Initialize Transmit Descriptor Ring */
186 txbdp = tx_queue->tx_bd_base;
187 for (j = 0; j < tx_queue->tx_ring_size; j++) {
188 txbdp->lstatus = 0;
189 txbdp->bufPtr = 0;
190 txbdp++;
191 }
8728327e 192
fba4ed03
SG		 193 /* Set the last descriptor in the ring to indicate wrap */
194 txbdp--;
195 txbdp->status |= TXBD_WRAP;
8728327e
AV		 196 }
197
fba4ed03
SG		 198 for (i = 0; i < priv->num_rx_queues; i++) {
199 rx_queue = priv->rx_queue[i];
200 rx_queue->cur_rx = rx_queue->rx_bd_base;
201 rx_queue->skb_currx = 0;
202 rxbdp = rx_queue->rx_bd_base;
8728327e 203
fba4ed03
SG		 204 for (j = 0; j < rx_queue->rx_ring_size; j++) {
205 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 206
fba4ed03
SG		 207 if (skb) {
208 gfar_init_rxbdp(rx_queue, rxbdp,
209 rxbdp->bufPtr);
210 } else {
211 skb = gfar_new_skb(ndev);
212 if (!skb) {
213 pr_err("%s: Can't allocate RX buffers\n",
214 ndev->name);
215 goto err_rxalloc_fail;
216 }
217 rx_queue->rx_skbuff[j] = skb;
218
219 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 220 }
8728327e 221
fba4ed03 222 rxbdp++;
8728327e
AV		 223 }
224
8728327e
AV		 225 }
226
227 return 0;
fba4ed03
SG		 228
229err_rxalloc_fail:
230 free_skb_resources(priv);
231 return -ENOMEM;
8728327e
AV		 232}
233
234static int gfar_alloc_skb_resources(struct net_device *ndev)
235{
826aa4a0 236 void *vaddr;
fba4ed03
SG		 237 dma_addr_t addr;
238 int i, j, k;
826aa4a0
AV		 239 struct gfar_private *priv = netdev_priv(ndev);
240 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 241 struct gfar_priv_tx_q *tx_queue = NULL;
242 struct gfar_priv_rx_q *rx_queue = NULL;
243
fba4ed03
SG		 244 priv->total_tx_ring_size = 0;
245 for (i = 0; i < priv->num_tx_queues; i++)
246 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
247
248 priv->total_rx_ring_size = 0;
249 for (i = 0; i < priv->num_rx_queues; i++)
250 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 251
252 /* Allocate memory for the buffer descriptors */
8728327e 253 vaddr = dma_alloc_coherent(dev,
fba4ed03
SG		 254 sizeof(struct txbd8) * priv->total_tx_ring_size +
255 sizeof(struct rxbd8) * priv->total_rx_ring_size,
256 &addr, GFP_KERNEL);
826aa4a0
AV		 257 if (!vaddr) {
258 if (netif_msg_ifup(priv))
259 pr_err("%s: Could not allocate buffer descriptors!\n",
260 ndev->name);
261 return -ENOMEM;
262 }
263
fba4ed03
SG		 264 for (i = 0; i < priv->num_tx_queues; i++) {
265 tx_queue = priv->tx_queue[i];
266 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
267 tx_queue->tx_bd_dma_base = addr;
268 tx_queue->dev = ndev;
269 /* enet DMA only understands physical addresses */
270 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
271 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
272 }
826aa4a0 273
826aa4a0 274 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 275 for (i = 0; i < priv->num_rx_queues; i++) {
276 rx_queue = priv->rx_queue[i];
277 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
278 rx_queue->rx_bd_dma_base = addr;
279 rx_queue->dev = ndev;
280 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
281 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
282 }
826aa4a0
AV		 283
284 /* Setup the skbuff rings */
fba4ed03
SG		 285 for (i = 0; i < priv->num_tx_queues; i++) {
286 tx_queue = priv->tx_queue[i];
287 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
a12f801d 288 tx_queue->tx_ring_size, GFP_KERNEL);
fba4ed03
SG		 289 if (!tx_queue->tx_skbuff) {
290 if (netif_msg_ifup(priv))
291 pr_err("%s: Could not allocate tx_skbuff\n",
292 ndev->name);
293 goto cleanup;
294 }
826aa4a0 295
fba4ed03
SG		 296 for (k = 0; k < tx_queue->tx_ring_size; k++)
297 tx_queue->tx_skbuff[k] = NULL;
298 }
826aa4a0 299
fba4ed03
SG		 300 for (i = 0; i < priv->num_rx_queues; i++) {
301 rx_queue = priv->rx_queue[i];
302 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
a12f801d 303 rx_queue->rx_ring_size, GFP_KERNEL);
826aa4a0 304
fba4ed03
SG		 305 if (!rx_queue->rx_skbuff) {
306 if (netif_msg_ifup(priv))
307 pr_err("%s: Could not allocate rx_skbuff\n",
308 ndev->name);
309 goto cleanup;
310 }
311
312 for (j = 0; j < rx_queue->rx_ring_size; j++)
313 rx_queue->rx_skbuff[j] = NULL;
314 }
826aa4a0 315
8728327e
AV		 316 if (gfar_init_bds(ndev))
317 goto cleanup;
826aa4a0
AV		 318
319 return 0;
320
321cleanup:
322 free_skb_resources(priv);
323 return -ENOMEM;
324}
325
fba4ed03
SG		 326static void gfar_init_tx_rx_base(struct gfar_private *priv)
327{
46ceb60c 328 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 329 u32 __iomem *baddr;
fba4ed03
SG		 330 int i;
331
332 baddr = &regs->tbase0;
333 for(i = 0; i < priv->num_tx_queues; i++) {
334 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
335 baddr += 2;
336 }
337
338 baddr = &regs->rbase0;
339 for(i = 0; i < priv->num_rx_queues; i++) {
340 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
341 baddr += 2;
342 }
343}
344
826aa4a0
AV		 345static void gfar_init_mac(struct net_device *ndev)
346{
347 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 348 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 349 u32 rctrl = 0;
350 u32 tctrl = 0;
351 u32 attrs = 0;
352
fba4ed03
SG		 353 /* write the tx/rx base registers */
354 gfar_init_tx_rx_base(priv);
32c513bc 355
826aa4a0 356 /* Configure the coalescing support */
46ceb60c 357 gfar_configure_coalescing(priv, 0xFF, 0xFF);
fba4ed03 358
1ccb8389 359 if (priv->rx_filer_enable) {
fba4ed03 360 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 361 /* Program the RIR0 reg with the required distribution */
362 gfar_write(&regs->rir0, DEFAULT_RIR0);
363 }
826aa4a0
AV		 364
365 if (priv->rx_csum_enable)
366 rctrl |= RCTRL_CHECKSUMMING;
367
368 if (priv->extended_hash) {
369 rctrl |= RCTRL_EXTHASH;
370
371 gfar_clear_exact_match(ndev);
372 rctrl |= RCTRL_EMEN;
373 }
374
375 if (priv->padding) {
376 rctrl &= ~RCTRL_PAL_MASK;
377 rctrl |= RCTRL_PADDING(priv->padding);
378 }
379
380 /* keep vlan related bits if it's enabled */
381 if (priv->vlgrp) {
382 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
383 tctrl |= TCTRL_VLINS;
384 }
385
386 /* Init rctrl based on our settings */
387 gfar_write(&regs->rctrl, rctrl);
388
389 if (ndev->features & NETIF_F_IP_CSUM)
390 tctrl |= TCTRL_INIT_CSUM;
391
fba4ed03
SG		 392 tctrl |= TCTRL_TXSCHED_PRIO;
393
826aa4a0
AV		 394 gfar_write(&regs->tctrl, tctrl);
395
396 /* Set the extraction length and index */
397 attrs = ATTRELI_EL(priv->rx_stash_size) |
398 ATTRELI_EI(priv->rx_stash_index);
399
400 gfar_write(&regs->attreli, attrs);
401
402 /* Start with defaults, and add stashing or locking
403 * depending on the approprate variables */
404 attrs = ATTR_INIT_SETTINGS;
405
406 if (priv->bd_stash_en)
407 attrs |= ATTR_BDSTASH;
408
409 if (priv->rx_stash_size != 0)
410 attrs |= ATTR_BUFSTASH;
411
412 gfar_write(&regs->attr, attrs);
413
414 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
415 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
416 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
417}
418
a7f38041
SG		 419static struct net_device_stats *gfar_get_stats(struct net_device *dev)
420{
421 struct gfar_private *priv = netdev_priv(dev);
422 struct netdev_queue *txq;
423 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
424 unsigned long tx_packets = 0, tx_bytes = 0;
425 int i = 0;
426
427 for (i = 0; i < priv->num_rx_queues; i++) {
428 rx_packets += priv->rx_queue[i]->stats.rx_packets;
429 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
430 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
431 }
432
433 dev->stats.rx_packets = rx_packets;
434 dev->stats.rx_bytes = rx_bytes;
435 dev->stats.rx_dropped = rx_dropped;
436
437 for (i = 0; i < priv->num_tx_queues; i++) {
438 txq = netdev_get_tx_queue(dev, i);
439 tx_bytes += txq->tx_bytes;
440 tx_packets += txq->tx_packets;
441 }
442
443 dev->stats.tx_bytes = tx_bytes;
444 dev->stats.tx_packets = tx_packets;
445
446 return &dev->stats;
447}
448
26ccfc37
AF		 449static const struct net_device_ops gfar_netdev_ops = {
450 .ndo_open = gfar_enet_open,
451 .ndo_start_xmit = gfar_start_xmit,
452 .ndo_stop = gfar_close,
453 .ndo_change_mtu = gfar_change_mtu,
454 .ndo_set_multicast_list = gfar_set_multi,
455 .ndo_tx_timeout = gfar_timeout,
456 .ndo_do_ioctl = gfar_ioctl,
a7f38041 457 .ndo_get_stats = gfar_get_stats,
26ccfc37 458 .ndo_vlan_rx_register = gfar_vlan_rx_register,
240c102d
BH		 459 .ndo_set_mac_address = eth_mac_addr,
460 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 461#ifdef CONFIG_NET_POLL_CONTROLLER
462 .ndo_poll_controller = gfar_netpoll,
463#endif
464};
465
7a8b3372
SG		 466unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
467unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
468
fba4ed03
SG		 469void lock_rx_qs(struct gfar_private *priv)
470{
471 int i = 0x0;
472
473 for (i = 0; i < priv->num_rx_queues; i++)
474 spin_lock(&priv->rx_queue[i]->rxlock);
475}
476
477void lock_tx_qs(struct gfar_private *priv)
478{
479 int i = 0x0;
480
481 for (i = 0; i < priv->num_tx_queues; i++)
482 spin_lock(&priv->tx_queue[i]->txlock);
483}
484
485void unlock_rx_qs(struct gfar_private *priv)
486{
487 int i = 0x0;
488
489 for (i = 0; i < priv->num_rx_queues; i++)
490 spin_unlock(&priv->rx_queue[i]->rxlock);
491}
492
493void unlock_tx_qs(struct gfar_private *priv)
494{
495 int i = 0x0;
496
497 for (i = 0; i < priv->num_tx_queues; i++)
498 spin_unlock(&priv->tx_queue[i]->txlock);
499}
500
7f7f5316
AF		 501/* Returns 1 if incoming frames use an FCB */
502static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 503{
77ecaf2d 504 return priv->vlgrp || priv->rx_csum_enable;
0bbaf069 505}
bb40dcbb 506
fba4ed03
SG		 507static void free_tx_pointers(struct gfar_private *priv)
508{
509 int i = 0;
510
511 for (i = 0; i < priv->num_tx_queues; i++)
512 kfree(priv->tx_queue[i]);
513}
514
515static void free_rx_pointers(struct gfar_private *priv)
516{
517 int i = 0;
518
519 for (i = 0; i < priv->num_rx_queues; i++)
520 kfree(priv->rx_queue[i]);
521}
522
46ceb60c
SG		 523static void unmap_group_regs(struct gfar_private *priv)
524{
525 int i = 0;
526
527 for (i = 0; i < MAXGROUPS; i++)
528 if (priv->gfargrp[i].regs)
529 iounmap(priv->gfargrp[i].regs);
530}
531
532static void disable_napi(struct gfar_private *priv)
533{
534 int i = 0;
535
536 for (i = 0; i < priv->num_grps; i++)
537 napi_disable(&priv->gfargrp[i].napi);
538}
539
540static void enable_napi(struct gfar_private *priv)
541{
542 int i = 0;
543
544 for (i = 0; i < priv->num_grps; i++)
545 napi_enable(&priv->gfargrp[i].napi);
546}
547
548static int gfar_parse_group(struct device_node *np,
549 struct gfar_private *priv, const char *model)
550{
551 u32 *queue_mask;
46ceb60c 552
7ce97d4f 553 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
46ceb60c
SG		 554 if (!priv->gfargrp[priv->num_grps].regs)
555 return -ENOMEM;
556
557 priv->gfargrp[priv->num_grps].interruptTransmit =
558 irq_of_parse_and_map(np, 0);
559
560 /* If we aren't the FEC we have multiple interrupts */
561 if (model && strcasecmp(model, "FEC")) {
562 priv->gfargrp[priv->num_grps].interruptReceive =
563 irq_of_parse_and_map(np, 1);
564 priv->gfargrp[priv->num_grps].interruptError =
565 irq_of_parse_and_map(np,2);
566 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
567 priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
568 priv->gfargrp[priv->num_grps].interruptError < 0) {
569 return -EINVAL;
570 }
571 }
572
573 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
574 priv->gfargrp[priv->num_grps].priv = priv;
575 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
576 if(priv->mode == MQ_MG_MODE) {
577 queue_mask = (u32 *)of_get_property(np,
578 "fsl,rx-bit-map", NULL);
579 priv->gfargrp[priv->num_grps].rx_bit_map =
580 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
581 queue_mask = (u32 *)of_get_property(np,
582 "fsl,tx-bit-map", NULL);
583 priv->gfargrp[priv->num_grps].tx_bit_map =
584 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
585 } else {
586 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
587 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
588 }
589 priv->num_grps++;
590
591 return 0;
592}
593
fba4ed03 594static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
b31a1d8b 595{
b31a1d8b
AF		 596 const char *model;
597 const char *ctype;
598 const void *mac_addr;
fba4ed03
SG		 599 int err = 0, i;
600 struct net_device *dev = NULL;
601 struct gfar_private *priv = NULL;
602 struct device_node *np = ofdev->node;
46ceb60c 603 struct device_node *child = NULL;
4d7902f2
AF		 604 const u32 *stash;
605 const u32 *stash_len;
606 const u32 *stash_idx;
fba4ed03
SG		 607 unsigned int num_tx_qs, num_rx_qs;
608 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 609
610 if (!np || !of_device_is_available(np))
611 return -ENODEV;
612
fba4ed03
SG		 613 /* parse the num of tx and rx queues */
614 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
615 num_tx_qs = tx_queues ? *tx_queues : 1;
616
617 if (num_tx_qs > MAX_TX_QS) {
618 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
619 num_tx_qs, MAX_TX_QS);
620 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
621 return -EINVAL;
622 }
623
624 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
625 num_rx_qs = rx_queues ? *rx_queues : 1;
626
627 if (num_rx_qs > MAX_RX_QS) {
628 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
629 num_tx_qs, MAX_TX_QS);
630 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
631 return -EINVAL;
632 }
633
634 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
635 dev = *pdev;
636 if (NULL == dev)
637 return -ENOMEM;
638
639 priv = netdev_priv(dev);
640 priv->node = ofdev->node;
641 priv->ndev = dev;
642
643 dev->num_tx_queues = num_tx_qs;
644 dev->real_num_tx_queues = num_tx_qs;
645 priv->num_tx_queues = num_tx_qs;
646 priv->num_rx_queues = num_rx_qs;
46ceb60c 647 priv->num_grps = 0x0;
b31a1d8b
AF		 648
649 model = of_get_property(np, "model", NULL);
650
46ceb60c
SG		 651 for (i = 0; i < MAXGROUPS; i++)
652 priv->gfargrp[i].regs = NULL;
b31a1d8b 653
46ceb60c
SG		 654 /* Parse and initialize group specific information */
655 if (of_device_is_compatible(np, "fsl,etsec2")) {
656 priv->mode = MQ_MG_MODE;
657 for_each_child_of_node(np, child) {
658 err = gfar_parse_group(child, priv, model);
659 if (err)
660 goto err_grp_init;
b31a1d8b 661 }
46ceb60c
SG		 662 } else {
663 priv->mode = SQ_SG_MODE;
664 err = gfar_parse_group(np, priv, model);
665 if(err)
666 goto err_grp_init;
b31a1d8b
AF		 667 }
668
fba4ed03
SG		 669 for (i = 0; i < priv->num_tx_queues; i++)
670 priv->tx_queue[i] = NULL;
671 for (i = 0; i < priv->num_rx_queues; i++)
672 priv->rx_queue[i] = NULL;
673
674 for (i = 0; i < priv->num_tx_queues; i++) {
ed130589 675 priv->tx_queue[i] = (struct gfar_priv_tx_q *)kzalloc(
fba4ed03
SG		 676 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
677 if (!priv->tx_queue[i]) {
678 err = -ENOMEM;
679 goto tx_alloc_failed;
680 }
681 priv->tx_queue[i]->tx_skbuff = NULL;
682 priv->tx_queue[i]->qindex = i;
683 priv->tx_queue[i]->dev = dev;
684 spin_lock_init(&(priv->tx_queue[i]->txlock));
685 }
686
687 for (i = 0; i < priv->num_rx_queues; i++) {
ed130589 688 priv->rx_queue[i] = (struct gfar_priv_rx_q *)kzalloc(
fba4ed03
SG		 689 sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
690 if (!priv->rx_queue[i]) {
691 err = -ENOMEM;
692 goto rx_alloc_failed;
693 }
694 priv->rx_queue[i]->rx_skbuff = NULL;
695 priv->rx_queue[i]->qindex = i;
696 priv->rx_queue[i]->dev = dev;
697 spin_lock_init(&(priv->rx_queue[i]->rxlock));
698 }
699
700
4d7902f2
AF		 701 stash = of_get_property(np, "bd-stash", NULL);
702
a12f801d 703 if (stash) {
4d7902f2
AF		 704 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
705 priv->bd_stash_en = 1;
706 }
707
708 stash_len = of_get_property(np, "rx-stash-len", NULL);
709
710 if (stash_len)
711 priv->rx_stash_size = *stash_len;
712
713 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
714
715 if (stash_idx)
716 priv->rx_stash_index = *stash_idx;
717
718 if (stash_len || stash_idx)
719 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
720
b31a1d8b
AF		 721 mac_addr = of_get_mac_address(np);
722 if (mac_addr)
723 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
724
725 if (model && !strcasecmp(model, "TSEC"))
726 priv->device_flags =
727 FSL_GIANFAR_DEV_HAS_GIGABIT |
728 FSL_GIANFAR_DEV_HAS_COALESCE |
729 FSL_GIANFAR_DEV_HAS_RMON |
730 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
731 if (model && !strcasecmp(model, "eTSEC"))
732 priv->device_flags =
733 FSL_GIANFAR_DEV_HAS_GIGABIT |
734 FSL_GIANFAR_DEV_HAS_COALESCE |
735 FSL_GIANFAR_DEV_HAS_RMON |
736 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
2c2db48a 737 FSL_GIANFAR_DEV_HAS_PADDING |
b31a1d8b
AF		 738 FSL_GIANFAR_DEV_HAS_CSUM |
739 FSL_GIANFAR_DEV_HAS_VLAN |
740 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
741 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
742
743 ctype = of_get_property(np, "phy-connection-type", NULL);
744
745 /* We only care about rgmii-id. The rest are autodetected */
746 if (ctype && !strcmp(ctype, "rgmii-id"))
747 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
748 else
749 priv->interface = PHY_INTERFACE_MODE_MII;
750
751 if (of_get_property(np, "fsl,magic-packet", NULL))
752 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
753
fe192a49 754 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 755
756 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 757 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 758
759 return 0;
760
fba4ed03
SG		 761rx_alloc_failed:
762 free_rx_pointers(priv);
763tx_alloc_failed:
764 free_tx_pointers(priv);
46ceb60c
SG		 765err_grp_init:
766 unmap_group_regs(priv);
fba4ed03 767 free_netdev(dev);
b31a1d8b
AF		 768 return err;
769}
770
0faac9f7
CW		 771/* Ioctl MII Interface */
772static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
773{
774 struct gfar_private *priv = netdev_priv(dev);
775
776 if (!netif_running(dev))
777 return -EINVAL;
778
779 if (!priv->phydev)
780 return -ENODEV;
781
782 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
783}
784
fba4ed03
SG		 785static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
786{
787 unsigned int new_bit_map = 0x0;
788 int mask = 0x1 << (max_qs - 1), i;
789 for (i = 0; i < max_qs; i++) {
790 if (bit_map & mask)
791 new_bit_map = new_bit_map + (1 << i);
792 mask = mask >> 0x1;
793 }
794 return new_bit_map;
795}
7a8b3372 796
18294ad1
AV		 797static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
798 u32 class)
7a8b3372
SG		 799{
800 u32 rqfpr = FPR_FILER_MASK;
801 u32 rqfcr = 0x0;
802
803 rqfar--;
804 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
805 ftp_rqfpr[rqfar] = rqfpr;
806 ftp_rqfcr[rqfar] = rqfcr;
807 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
808
809 rqfar--;
810 rqfcr = RQFCR_CMP_NOMATCH;
811 ftp_rqfpr[rqfar] = rqfpr;
812 ftp_rqfcr[rqfar] = rqfcr;
813 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
814
815 rqfar--;
816 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
817 rqfpr = class;
818 ftp_rqfcr[rqfar] = rqfcr;
819 ftp_rqfpr[rqfar] = rqfpr;
820 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
821
822 rqfar--;
823 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
824 rqfpr = class;
825 ftp_rqfcr[rqfar] = rqfcr;
826 ftp_rqfpr[rqfar] = rqfpr;
827 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
828
829 return rqfar;
830}
831
832static void gfar_init_filer_table(struct gfar_private *priv)
833{
834 int i = 0x0;
835 u32 rqfar = MAX_FILER_IDX;
836 u32 rqfcr = 0x0;
837 u32 rqfpr = FPR_FILER_MASK;
838
839 /* Default rule */
840 rqfcr = RQFCR_CMP_MATCH;
841 ftp_rqfcr[rqfar] = rqfcr;
842 ftp_rqfpr[rqfar] = rqfpr;
843 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
844
845 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
846 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
847 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
848 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
849 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
850 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
851
852 /* cur_filer_idx indicated the fisrt non-masked rule */
853 priv->cur_filer_idx = rqfar;
854
855 /* Rest are masked rules */
856 rqfcr = RQFCR_CMP_NOMATCH;
857 for (i = 0; i < rqfar; i++) {
858 ftp_rqfcr[i] = rqfcr;
859 ftp_rqfpr[i] = rqfpr;
860 gfar_write_filer(priv, i, rqfcr, rqfpr);
861 }
862}
863
bb40dcbb
AF		 864/* Set up the ethernet device structure, private data,
865 * and anything else we need before we start */
b31a1d8b
AF		 866static int gfar_probe(struct of_device *ofdev,
867 const struct of_device_id *match)
1da177e4
LT		 868{
869 u32 tempval;
870 struct net_device *dev = NULL;
871 struct gfar_private *priv = NULL;
f4983704 872 struct gfar __iomem *regs = NULL;
46ceb60c 873 int err = 0, i, grp_idx = 0;
c50a5d9a 874 int len_devname;
fba4ed03 875 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 876 u32 isrg = 0;
18294ad1 877 u32 __iomem *baddr;
1da177e4 878
fba4ed03 879 err = gfar_of_init(ofdev, &dev);
1da177e4 880
fba4ed03
SG		 881 if (err)
882 return err;
1da177e4
LT		 883
884 priv = netdev_priv(dev);
4826857f
KG		 885 priv->ndev = dev;
886 priv->ofdev = ofdev;
b31a1d8b 887 priv->node = ofdev->node;
4826857f 888 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 889
d87eb127 890 spin_lock_init(&priv->bflock);
ab939905 891 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 892
b31a1d8b 893 dev_set_drvdata(&ofdev->dev, priv);
46ceb60c 894 regs = priv->gfargrp[0].regs;
1da177e4
LT		 895
896 /* Stop the DMA engine now, in case it was running before */
897 /* (The firmware could have used it, and left it running). */
257d938a 898 gfar_halt(dev);
1da177e4
LT		 899
900 /* Reset MAC layer */
f4983704 901 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 902
b98ac702
AF		 903 /* We need to delay at least 3 TX clocks */
904 udelay(2);
905
1da177e4 906 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 907 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 908
909 /* Initialize MACCFG2. */
f4983704 910 gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
1da177e4
LT		 911
912 /* Initialize ECNTRL */
f4983704 913 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 914
1da177e4 915 /* Set the dev->base_addr to the gfar reg region */
f4983704 916 dev->base_addr = (unsigned long) regs;
1da177e4 917
b31a1d8b 918 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 919
920 /* Fill in the dev structure */
1da177e4 921 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 922 dev->mtu = 1500;
26ccfc37 923 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 924 dev->ethtool_ops = &gfar_ethtool_ops;
925
fba4ed03 926 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c
SG		 927 for (i = 0; i < priv->num_grps; i++)
928 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
a12f801d 929
b31a1d8b 930 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
0bbaf069 931 priv->rx_csum_enable = 1;
4669bc90 932 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
0bbaf069
KG		 933 } else
934 priv->rx_csum_enable = 0;
935
936 priv->vlgrp = NULL;
1da177e4 937
26ccfc37 938 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
0bbaf069 939 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
0bbaf069 940
b31a1d8b 941 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 942 priv->extended_hash = 1;
943 priv->hash_width = 9;
944
f4983704
SG		 945 priv->hash_regs[0] = &regs->igaddr0;
946 priv->hash_regs[1] = &regs->igaddr1;
947 priv->hash_regs[2] = &regs->igaddr2;
948 priv->hash_regs[3] = &regs->igaddr3;
949 priv->hash_regs[4] = &regs->igaddr4;
950 priv->hash_regs[5] = &regs->igaddr5;
951 priv->hash_regs[6] = &regs->igaddr6;
952 priv->hash_regs[7] = &regs->igaddr7;
953 priv->hash_regs[8] = &regs->gaddr0;
954 priv->hash_regs[9] = &regs->gaddr1;
955 priv->hash_regs[10] = &regs->gaddr2;
956 priv->hash_regs[11] = &regs->gaddr3;
957 priv->hash_regs[12] = &regs->gaddr4;
958 priv->hash_regs[13] = &regs->gaddr5;
959 priv->hash_regs[14] = &regs->gaddr6;
960 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 961
962 } else {
963 priv->extended_hash = 0;
964 priv->hash_width = 8;
965
f4983704
SG		 966 priv->hash_regs[0] = &regs->gaddr0;
967 priv->hash_regs[1] = &regs->gaddr1;
968 priv->hash_regs[2] = &regs->gaddr2;
969 priv->hash_regs[3] = &regs->gaddr3;
970 priv->hash_regs[4] = &regs->gaddr4;
971 priv->hash_regs[5] = &regs->gaddr5;
972 priv->hash_regs[6] = &regs->gaddr6;
973 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 974 }
975
b31a1d8b 976 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 977 priv->padding = DEFAULT_PADDING;
978 else
979 priv->padding = 0;
980
0bbaf069
KG		 981 if (dev->features & NETIF_F_IP_CSUM)
982 dev->hard_header_len += GMAC_FCB_LEN;
1da177e4 983
46ceb60c
SG		 984 /* Program the isrg regs only if number of grps > 1 */
985 if (priv->num_grps > 1) {
986 baddr = &regs->isrg0;
987 for (i = 0; i < priv->num_grps; i++) {
988 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
989 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
990 gfar_write(baddr, isrg);
991 baddr++;
992 isrg = 0x0;
993 }
994 }
995
fba4ed03 996 /* Need to reverse the bit maps as bit_map's MSB is q0
984b3f57 997 * but, for_each_set_bit parses from right to left, which
fba4ed03 998 * basically reverses the queue numbers */
46ceb60c
SG		 999 for (i = 0; i< priv->num_grps; i++) {
1000 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1001 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1002 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1003 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1004 }
1005
1006 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1007 * also assign queues to groups */
1008 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1009 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
984b3f57 1010 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
46ceb60c
SG		 1011 priv->num_rx_queues) {
1012 priv->gfargrp[grp_idx].num_rx_queues++;
1013 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1014 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1015 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1016 }
1017 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
984b3f57 1018 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
46ceb60c
SG		 1019 priv->num_tx_queues) {
1020 priv->gfargrp[grp_idx].num_tx_queues++;
1021 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1022 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1023 tqueue = tqueue | (TQUEUE_EN0 >> i);
1024 }
1025 priv->gfargrp[grp_idx].rstat = rstat;
1026 priv->gfargrp[grp_idx].tstat = tstat;
1027 rstat = tstat =0;
fba4ed03 1028 }
fba4ed03
SG		 1029
1030 gfar_write(&regs->rqueue, rqueue);
1031 gfar_write(&regs->tqueue, tqueue);
1032
1da177e4 1033 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1034
a12f801d 1035 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1036 for (i = 0; i < priv->num_tx_queues; i++) {
1037 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1038 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1039 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1040 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1041 }
a12f801d 1042
fba4ed03
SG		 1043 for (i = 0; i < priv->num_rx_queues; i++) {
1044 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1045 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1046 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1047 }
1da177e4 1048
1ccb8389
SG		 1049 /* enable filer if using multiple RX queues*/
1050 if(priv->num_rx_queues > 1)
1051 priv->rx_filer_enable = 1;
0bbaf069
KG		 1052 /* Enable most messages by default */
1053 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1054
d3eab82b
TP		 1055 /* Carrier starts down, phylib will bring it up */
1056 netif_carrier_off(dev);
1057
1da177e4
LT		 1058 err = register_netdev(dev);
1059
1060 if (err) {
1061 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1062 dev->name);
1063 goto register_fail;
1064 }
1065
2884e5cc
AV		 1066 device_init_wakeup(&dev->dev,
1067 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1068
c50a5d9a
DH		 1069 /* fill out IRQ number and name fields */
1070 len_devname = strlen(dev->name);
46ceb60c
SG		 1071 for (i = 0; i < priv->num_grps; i++) {
1072 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1073 len_devname);
1074 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1075 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1076 "_g", sizeof("_g"));
1077 priv->gfargrp[i].int_name_tx[
1078 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1079 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1080 priv->gfargrp[i].int_name_tx)],
1081 "_tx", sizeof("_tx") + 1);
1082
1083 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1084 len_devname);
1085 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1086 "_g", sizeof("_g"));
1087 priv->gfargrp[i].int_name_rx[
1088 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1089 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1090 priv->gfargrp[i].int_name_rx)],
1091 "_rx", sizeof("_rx") + 1);
1092
1093 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1094 len_devname);
1095 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1096 "_g", sizeof("_g"));
1097 priv->gfargrp[i].int_name_er[strlen(
1098 priv->gfargrp[i].int_name_er)] = i+48;
1099 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1100 priv->gfargrp[i].int_name_er)],
1101 "_er", sizeof("_er") + 1);
1102 } else
1103 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1104 }
c50a5d9a 1105
7a8b3372
SG		 1106 /* Initialize the filer table */
1107 gfar_init_filer_table(priv);
1108
7f7f5316
AF		 1109 /* Create all the sysfs files */
1110 gfar_init_sysfs(dev);
1111
1da177e4 1112 /* Print out the device info */
e174961c 1113 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1da177e4
LT		 1114
1115 /* Even more device info helps when determining which kernel */
7f7f5316 1116 /* provided which set of benchmarks. */
1da177e4 1117 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
fba4ed03 1118 for (i = 0; i < priv->num_rx_queues; i++)
ddc01b3b 1119 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
fba4ed03
SG		 1120 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1121 for(i = 0; i < priv->num_tx_queues; i++)
ddc01b3b 1122 printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
fba4ed03 1123 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1124
1125 return 0;
1126
1127register_fail:
46ceb60c 1128 unmap_group_regs(priv);
fba4ed03
SG		 1129 free_tx_pointers(priv);
1130 free_rx_pointers(priv);
fe192a49
GL		 1131 if (priv->phy_node)
1132 of_node_put(priv->phy_node);
1133 if (priv->tbi_node)
1134 of_node_put(priv->tbi_node);
1da177e4 1135 free_netdev(dev);
bb40dcbb 1136 return err;
1da177e4
LT		 1137}
1138
b31a1d8b 1139static int gfar_remove(struct of_device *ofdev)
1da177e4 1140{
b31a1d8b 1141 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 1142
fe192a49
GL		 1143 if (priv->phy_node)
1144 of_node_put(priv->phy_node);
1145 if (priv->tbi_node)
1146 of_node_put(priv->tbi_node);
1147
b31a1d8b 1148 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 1149
d9d8e041 1150 unregister_netdev(priv->ndev);
46ceb60c 1151 unmap_group_regs(priv);
4826857f 1152 free_netdev(priv->ndev);
1da177e4
LT		 1153
1154 return 0;
1155}
1156
d87eb127 1157#ifdef CONFIG_PM
be926fc4
AV		 1158
1159static int gfar_suspend(struct device *dev)
d87eb127 1160{
be926fc4
AV		 1161 struct gfar_private *priv = dev_get_drvdata(dev);
1162 struct net_device *ndev = priv->ndev;
46ceb60c 1163 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1164 unsigned long flags;
1165 u32 tempval;
1166
1167 int magic_packet = priv->wol_en &&
b31a1d8b 1168 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1169
be926fc4 1170 netif_device_detach(ndev);
d87eb127 1171
be926fc4 1172 if (netif_running(ndev)) {
fba4ed03
SG		 1173
1174 local_irq_save(flags);
1175 lock_tx_qs(priv);
1176 lock_rx_qs(priv);
d87eb127 1177
be926fc4 1178 gfar_halt_nodisable(ndev);
d87eb127
SW		 1179
1180 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1181 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1182
1183 tempval &= ~MACCFG1_TX_EN;
1184
1185 if (!magic_packet)
1186 tempval &= ~MACCFG1_RX_EN;
1187
f4983704 1188 gfar_write(&regs->maccfg1, tempval);
d87eb127 1189
fba4ed03
SG		 1190 unlock_rx_qs(priv);
1191 unlock_tx_qs(priv);
1192 local_irq_restore(flags);
d87eb127 1193
46ceb60c 1194 disable_napi(priv);
d87eb127
SW		 1195
1196 if (magic_packet) {
1197 /* Enable interrupt on Magic Packet */
f4983704 1198 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1199
1200 /* Enable Magic Packet mode */
f4983704 1201 tempval = gfar_read(&regs->maccfg2);
d87eb127 1202 tempval |= MACCFG2_MPEN;
f4983704 1203 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1204 } else {
1205 phy_stop(priv->phydev);
1206 }
1207 }
1208
1209 return 0;
1210}
1211
be926fc4 1212static int gfar_resume(struct device *dev)
d87eb127 1213{
be926fc4
AV		 1214 struct gfar_private *priv = dev_get_drvdata(dev);
1215 struct net_device *ndev = priv->ndev;
46ceb60c 1216 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1217 unsigned long flags;
1218 u32 tempval;
1219 int magic_packet = priv->wol_en &&
b31a1d8b 1220 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1221
be926fc4
AV		 1222 if (!netif_running(ndev)) {
1223 netif_device_attach(ndev);
d87eb127
SW		 1224 return 0;
1225 }
1226
1227 if (!magic_packet && priv->phydev)
1228 phy_start(priv->phydev);
1229
1230 /* Disable Magic Packet mode, in case something
1231 * else woke us up.
1232 */
fba4ed03
SG		 1233 local_irq_save(flags);
1234 lock_tx_qs(priv);
1235 lock_rx_qs(priv);
d87eb127 1236
f4983704 1237 tempval = gfar_read(&regs->maccfg2);
d87eb127 1238 tempval &= ~MACCFG2_MPEN;
f4983704 1239 gfar_write(&regs->maccfg2, tempval);
d87eb127 1240
be926fc4 1241 gfar_start(ndev);
d87eb127 1242
fba4ed03
SG		 1243 unlock_rx_qs(priv);
1244 unlock_tx_qs(priv);
1245 local_irq_restore(flags);
d87eb127 1246
be926fc4
AV		 1247 netif_device_attach(ndev);
1248
46ceb60c 1249 enable_napi(priv);
be926fc4
AV		 1250
1251 return 0;
1252}
1253
1254static int gfar_restore(struct device *dev)
1255{
1256 struct gfar_private *priv = dev_get_drvdata(dev);
1257 struct net_device *ndev = priv->ndev;
1258
1259 if (!netif_running(ndev))
1260 return 0;
1261
1262 gfar_init_bds(ndev);
1263 init_registers(ndev);
1264 gfar_set_mac_address(ndev);
1265 gfar_init_mac(ndev);
1266 gfar_start(ndev);
1267
1268 priv->oldlink = 0;
1269 priv->oldspeed = 0;
1270 priv->oldduplex = -1;
1271
1272 if (priv->phydev)
1273 phy_start(priv->phydev);
d87eb127 1274
be926fc4 1275 netif_device_attach(ndev);
5ea681d4 1276 enable_napi(priv);
d87eb127
SW		 1277
1278 return 0;
1279}
be926fc4
AV		 1280
1281static struct dev_pm_ops gfar_pm_ops = {
1282 .suspend = gfar_suspend,
1283 .resume = gfar_resume,
1284 .freeze = gfar_suspend,
1285 .thaw = gfar_resume,
1286 .restore = gfar_restore,
1287};
1288
1289#define GFAR_PM_OPS (&gfar_pm_ops)
1290
1291static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
1292{
1293 return gfar_suspend(&ofdev->dev);
1294}
1295
1296static int gfar_legacy_resume(struct of_device *ofdev)
1297{
1298 return gfar_resume(&ofdev->dev);
1299}
1300
d87eb127 1301#else
be926fc4
AV		 1302
1303#define GFAR_PM_OPS NULL
1304#define gfar_legacy_suspend NULL
1305#define gfar_legacy_resume NULL
1306
d87eb127 1307#endif
1da177e4 1308
e8a2b6a4
AF		 1309/* Reads the controller's registers to determine what interface
1310 * connects it to the PHY.
1311 */
1312static phy_interface_t gfar_get_interface(struct net_device *dev)
1313{
1314 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1315 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1316 u32 ecntrl;
1317
f4983704 1318 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1319
1320 if (ecntrl & ECNTRL_SGMII_MODE)
1321 return PHY_INTERFACE_MODE_SGMII;
1322
1323 if (ecntrl & ECNTRL_TBI_MODE) {
1324 if (ecntrl & ECNTRL_REDUCED_MODE)
1325 return PHY_INTERFACE_MODE_RTBI;
1326 else
1327 return PHY_INTERFACE_MODE_TBI;
1328 }
1329
1330 if (ecntrl & ECNTRL_REDUCED_MODE) {
1331 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1332 return PHY_INTERFACE_MODE_RMII;
7132ab7f 1333 else {
b31a1d8b 1334 phy_interface_t interface = priv->interface;
7132ab7f
AF		 1335
1336 /*
1337 * This isn't autodetected right now, so it must
1338 * be set by the device tree or platform code.
1339 */
1340 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1341 return PHY_INTERFACE_MODE_RGMII_ID;
1342
e8a2b6a4 1343 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1344 }
e8a2b6a4
AF		 1345 }
1346
b31a1d8b 1347 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1348 return PHY_INTERFACE_MODE_GMII;
1349
1350 return PHY_INTERFACE_MODE_MII;
1351}
1352
1353
bb40dcbb
AF		 1354/* Initializes driver's PHY state, and attaches to the PHY.
1355 * Returns 0 on success.
1da177e4
LT		 1356 */
1357static int init_phy(struct net_device *dev)
1358{
1359 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1360 uint gigabit_support =
b31a1d8b 1361 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1362 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1363 phy_interface_t interface;
1da177e4
LT		 1364
1365 priv->oldlink = 0;
1366 priv->oldspeed = 0;
1367 priv->oldduplex = -1;
1368
e8a2b6a4
AF		 1369 interface = gfar_get_interface(dev);
1370
1db780f8
AV		 1371 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1372 interface);
1373 if (!priv->phydev)
1374 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1375 interface);
1376 if (!priv->phydev) {
1377 dev_err(&dev->dev, "could not attach to PHY\n");
1378 return -ENODEV;
fe192a49 1379 }
1da177e4 1380
d3c12873
KJ		 1381 if (interface == PHY_INTERFACE_MODE_SGMII)
1382 gfar_configure_serdes(dev);
1383
bb40dcbb 1384 /* Remove any features not supported by the controller */
fe192a49
GL		 1385 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1386 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1387
1388 return 0;
1da177e4
LT		 1389}
1390
d0313587
PG		 1391/*
1392 * Initialize TBI PHY interface for communicating with the
1393 * SERDES lynx PHY on the chip. We communicate with this PHY
1394 * through the MDIO bus on each controller, treating it as a
1395 * "normal" PHY at the address found in the TBIPA register. We assume
1396 * that the TBIPA register is valid. Either the MDIO bus code will set
1397 * it to a value that doesn't conflict with other PHYs on the bus, or the
1398 * value doesn't matter, as there are no other PHYs on the bus.
1399 */
d3c12873
KJ		 1400static void gfar_configure_serdes(struct net_device *dev)
1401{
1402 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1403 struct phy_device *tbiphy;
1404
1405 if (!priv->tbi_node) {
1406 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1407 "device tree specify a tbi-handle\n");
1408 return;
1409 }
c132419e 1410
fe192a49
GL		 1411 tbiphy = of_phy_find_device(priv->tbi_node);
1412 if (!tbiphy) {
1413 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1414 return;
1415 }
d3c12873 1416
b31a1d8b
AF		 1417 /*
1418 * If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1419 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1420 * everything for us? Resetting it takes the link down and requires
1421 * several seconds for it to come back.
1422 */
fe192a49 1423 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1424 return;
d3c12873 1425
d0313587 1426 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1427 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1428
fe192a49 1429 phy_write(tbiphy, MII_ADVERTISE,
d3c12873
KJ		 1430 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1431 ADVERTISE_1000XPSE_ASYM);
1432
fe192a49 1433 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
d3c12873
KJ		 1434 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1435}
1436
1da177e4
LT		 1437static void init_registers(struct net_device *dev)
1438{
1439 struct gfar_private *priv = netdev_priv(dev);
f4983704 1440 struct gfar __iomem *regs = NULL;
46ceb60c 1441 int i = 0;
1da177e4 1442
46ceb60c
SG		 1443 for (i = 0; i < priv->num_grps; i++) {
1444 regs = priv->gfargrp[i].regs;
1445 /* Clear IEVENT */
1446 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1447
46ceb60c
SG		 1448 /* Initialize IMASK */
1449 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1450 }
1da177e4 1451
46ceb60c 1452 regs = priv->gfargrp[0].regs;
1da177e4 1453 /* Init hash registers to zero */
f4983704
SG		 1454 gfar_write(&regs->igaddr0, 0);
1455 gfar_write(&regs->igaddr1, 0);
1456 gfar_write(&regs->igaddr2, 0);
1457 gfar_write(&regs->igaddr3, 0);
1458 gfar_write(&regs->igaddr4, 0);
1459 gfar_write(&regs->igaddr5, 0);
1460 gfar_write(&regs->igaddr6, 0);
1461 gfar_write(&regs->igaddr7, 0);
1462
1463 gfar_write(&regs->gaddr0, 0);
1464 gfar_write(&regs->gaddr1, 0);
1465 gfar_write(&regs->gaddr2, 0);
1466 gfar_write(&regs->gaddr3, 0);
1467 gfar_write(&regs->gaddr4, 0);
1468 gfar_write(&regs->gaddr5, 0);
1469 gfar_write(&regs->gaddr6, 0);
1470 gfar_write(&regs->gaddr7, 0);
1da177e4 1471
1da177e4 1472 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1473 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1474 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1475
1476 /* Mask off the CAM interrupts */
f4983704
SG		 1477 gfar_write(&regs->rmon.cam1, 0xffffffff);
1478 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1479 }
1480
1481 /* Initialize the max receive buffer length */
f4983704 1482 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1483
1da177e4 1484 /* Initialize the Minimum Frame Length Register */
f4983704 1485 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1486}
1487
0bbaf069
KG		 1488
1489/* Halt the receive and transmit queues */
d87eb127 1490static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1491{
1492 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1493 struct gfar __iomem *regs = NULL;
1da177e4 1494 u32 tempval;
46ceb60c 1495 int i = 0;
1da177e4 1496
46ceb60c
SG		 1497 for (i = 0; i < priv->num_grps; i++) {
1498 regs = priv->gfargrp[i].regs;
1499 /* Mask all interrupts */
1500 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1501
46ceb60c
SG		 1502 /* Clear all interrupts */
1503 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1504 }
1da177e4 1505
46ceb60c 1506 regs = priv->gfargrp[0].regs;
1da177e4 1507 /* Stop the DMA, and wait for it to stop */
f4983704 1508 tempval = gfar_read(&regs->dmactrl);
1da177e4
LT		 1509 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1510 != (DMACTRL_GRS | DMACTRL_GTS)) {
1511 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1512 gfar_write(&regs->dmactrl, tempval);
1da177e4 1513
761ed01b
AF		 1514 spin_event_timeout(((gfar_read(&regs->ievent) &
1515 (IEVENT_GRSC | IEVENT_GTSC)) ==
1516 (IEVENT_GRSC | IEVENT_GTSC)), -1, 0);
1da177e4 1517 }
d87eb127 1518}
d87eb127
SW		 1519
1520/* Halt the receive and transmit queues */
1521void gfar_halt(struct net_device *dev)
1522{
1523 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1524 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1525 u32 tempval;
1da177e4 1526
2a54adc3
SW		 1527 gfar_halt_nodisable(dev);
1528
1da177e4
LT		 1529 /* Disable Rx and Tx */
1530 tempval = gfar_read(&regs->maccfg1);
1531 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1532 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1533}
1534
46ceb60c
SG		 1535static void free_grp_irqs(struct gfar_priv_grp *grp)
1536{
1537 free_irq(grp->interruptError, grp);
1538 free_irq(grp->interruptTransmit, grp);
1539 free_irq(grp->interruptReceive, grp);
1540}
1541
0bbaf069
KG		 1542void stop_gfar(struct net_device *dev)
1543{
1544 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1545 unsigned long flags;
46ceb60c 1546 int i;
0bbaf069 1547
bb40dcbb
AF		 1548 phy_stop(priv->phydev);
1549
a12f801d 1550
0bbaf069 1551 /* Lock it down */
fba4ed03
SG		 1552 local_irq_save(flags);
1553 lock_tx_qs(priv);
1554 lock_rx_qs(priv);
0bbaf069 1555
0bbaf069 1556 gfar_halt(dev);
1da177e4 1557
fba4ed03
SG		 1558 unlock_rx_qs(priv);
1559 unlock_tx_qs(priv);
1560 local_irq_restore(flags);
1da177e4
LT		 1561
1562 /* Free the IRQs */
b31a1d8b 1563 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1564 for (i = 0; i < priv->num_grps; i++)
1565 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1566 } else {
46ceb60c
SG		 1567 for (i = 0; i < priv->num_grps; i++)
1568 free_irq(priv->gfargrp[i].interruptTransmit,
1569 &priv->gfargrp[i]);
1da177e4
LT		 1570 }
1571
1572 free_skb_resources(priv);
1da177e4
LT		 1573}
1574
fba4ed03 1575static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1576{
1da177e4 1577 struct txbd8 *txbdp;
fba4ed03 1578 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1579 int i, j;
1da177e4 1580
a12f801d 1581 txbdp = tx_queue->tx_bd_base;
1da177e4 1582
a12f801d
SG		 1583 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1584 if (!tx_queue->tx_skbuff[i])
4669bc90 1585 continue;
1da177e4 1586
4826857f 1587 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90
DH		 1588 txbdp->length, DMA_TO_DEVICE);
1589 txbdp->lstatus = 0;
fba4ed03
SG		 1590 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1591 j++) {
4669bc90 1592 txbdp++;
4826857f 1593 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90 1594 txbdp->length, DMA_TO_DEVICE);
1da177e4 1595 }
ad5da7ab 1596 txbdp++;
a12f801d
SG		 1597 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1598 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1599 }
a12f801d 1600 kfree(tx_queue->tx_skbuff);
fba4ed03 1601}
1da177e4 1602
fba4ed03
SG		 1603static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1604{
1605 struct rxbd8 *rxbdp;
1606 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1607 int i;
1da177e4 1608
fba4ed03 1609 rxbdp = rx_queue->rx_bd_base;
1da177e4 1610
a12f801d
SG		 1611 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1612 if (rx_queue->rx_skbuff[i]) {
fba4ed03
SG		 1613 dma_unmap_single(&priv->ofdev->dev,
1614 rxbdp->bufPtr, priv->rx_buffer_size,
e69edd21 1615 DMA_FROM_DEVICE);
a12f801d
SG		 1616 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1617 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1618 }
e69edd21
AV		 1619 rxbdp->lstatus = 0;
1620 rxbdp->bufPtr = 0;
1621 rxbdp++;
1da177e4 1622 }
a12f801d 1623 kfree(rx_queue->rx_skbuff);
fba4ed03 1624}
e69edd21 1625
fba4ed03
SG		 1626/* If there are any tx skbs or rx skbs still around, free them.
1627 * Then free tx_skbuff and rx_skbuff */
1628static void free_skb_resources(struct gfar_private *priv)
1629{
1630 struct gfar_priv_tx_q *tx_queue = NULL;
1631 struct gfar_priv_rx_q *rx_queue = NULL;
1632 int i;
1633
1634 /* Go through all the buffer descriptors and free their data buffers */
1635 for (i = 0; i < priv->num_tx_queues; i++) {
1636 tx_queue = priv->tx_queue[i];
7c0d10d3 1637 if(tx_queue->tx_skbuff)
fba4ed03
SG		 1638 free_skb_tx_queue(tx_queue);
1639 }
1640
1641 for (i = 0; i < priv->num_rx_queues; i++) {
1642 rx_queue = priv->rx_queue[i];
7c0d10d3 1643 if(rx_queue->rx_skbuff)
fba4ed03
SG		 1644 free_skb_rx_queue(rx_queue);
1645 }
1646
1647 dma_free_coherent(&priv->ofdev->dev,
1648 sizeof(struct txbd8) * priv->total_tx_ring_size +
1649 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1650 priv->tx_queue[0]->tx_bd_base,
1651 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 1652}
1653
0bbaf069
KG		 1654void gfar_start(struct net_device *dev)
1655{
1656 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1657 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1658 u32 tempval;
46ceb60c 1659 int i = 0;
0bbaf069
KG		 1660
1661 /* Enable Rx and Tx in MACCFG1 */
1662 tempval = gfar_read(&regs->maccfg1);
1663 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1664 gfar_write(&regs->maccfg1, tempval);
1665
1666 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1667 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1668 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1669 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1670
0bbaf069 1671 /* Make sure we aren't stopped */
f4983704 1672 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1673 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1674 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1675
46ceb60c
SG		 1676 for (i = 0; i < priv->num_grps; i++) {
1677 regs = priv->gfargrp[i].regs;
1678 /* Clear THLT/RHLT, so that the DMA starts polling now */
1679 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1680 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1681 /* Unmask the interrupts we look for */
1682 gfar_write(&regs->imask, IMASK_DEFAULT);
1683 }
12dea57b
DH		 1684
1685 dev->trans_start = jiffies;
0bbaf069
KG		 1686}
1687
46ceb60c 1688void gfar_configure_coalescing(struct gfar_private *priv,
18294ad1 1689 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1690{
46ceb60c 1691 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1692 u32 __iomem *baddr;
46ceb60c 1693 int i = 0;
1da177e4 1694
46ceb60c
SG		 1695 /* Backward compatible case ---- even if we enable
1696 * multiple queues, there's only single reg to program
1697 */
1698 gfar_write(&regs->txic, 0);
1699 if(likely(priv->tx_queue[0]->txcoalescing))
1700 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1da177e4 1701
46ceb60c
SG		 1702 gfar_write(&regs->rxic, 0);
1703 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1704 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
815b97c6 1705
46ceb60c
SG		 1706 if (priv->mode == MQ_MG_MODE) {
1707 baddr = &regs->txic0;
984b3f57 1708 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
46ceb60c
SG		 1709 if (likely(priv->tx_queue[i]->txcoalescing)) {
1710 gfar_write(baddr + i, 0);
1711 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1712 }
1713 }
1714
1715 baddr = &regs->rxic0;
984b3f57 1716 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
46ceb60c
SG		 1717 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1718 gfar_write(baddr + i, 0);
1719 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1720 }
1721 }
1722 }
1723}
1724
1725static int register_grp_irqs(struct gfar_priv_grp *grp)
1726{
1727 struct gfar_private *priv = grp->priv;
1728 struct net_device *dev = priv->ndev;
1729 int err;
1da177e4 1730
1da177e4
LT		 1731 /* If the device has multiple interrupts, register for
1732 * them. Otherwise, only register for the one */
b31a1d8b 1733 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1734 /* Install our interrupt handlers for Error,
1da177e4 1735 * Transmit, and Receive */
46ceb60c
SG		 1736 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1737 grp->int_name_er,grp)) < 0) {
0bbaf069 1738 if (netif_msg_intr(priv))
46ceb60c
SG		 1739 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1740 dev->name, grp->interruptError);
1741
1742 goto err_irq_fail;
1da177e4
LT		 1743 }
1744
46ceb60c
SG		 1745 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1746 0, grp->int_name_tx, grp)) < 0) {
0bbaf069 1747 if (netif_msg_intr(priv))
46ceb60c
SG		 1748 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1749 dev->name, grp->interruptTransmit);
1da177e4
LT		 1750 goto tx_irq_fail;
1751 }
1752
46ceb60c
SG		 1753 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1754 grp->int_name_rx, grp)) < 0) {
0bbaf069 1755 if (netif_msg_intr(priv))
46ceb60c
SG		 1756 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1757 dev->name, grp->interruptReceive);
1da177e4
LT		 1758 goto rx_irq_fail;
1759 }
1760 } else {
46ceb60c
SG		 1761 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1762 grp->int_name_tx, grp)) < 0) {
0bbaf069 1763 if (netif_msg_intr(priv))
46ceb60c
SG		 1764 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1765 dev->name, grp->interruptTransmit);
1da177e4
LT		 1766 goto err_irq_fail;
1767 }
1768 }
1769
46ceb60c
SG		 1770 return 0;
1771
1772rx_irq_fail:
1773 free_irq(grp->interruptTransmit, grp);
1774tx_irq_fail:
1775 free_irq(grp->interruptError, grp);
1776err_irq_fail:
1777 return err;
1778
1779}
1780
1781/* Bring the controller up and running */
1782int startup_gfar(struct net_device *ndev)
1783{
1784 struct gfar_private *priv = netdev_priv(ndev);
1785 struct gfar __iomem *regs = NULL;
1786 int err, i, j;
1787
1788 for (i = 0; i < priv->num_grps; i++) {
1789 regs= priv->gfargrp[i].regs;
1790 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1791 }
1792
1793 regs= priv->gfargrp[0].regs;
1794 err = gfar_alloc_skb_resources(ndev);
1795 if (err)
1796 return err;
1797
1798 gfar_init_mac(ndev);
1799
1800 for (i = 0; i < priv->num_grps; i++) {
1801 err = register_grp_irqs(&priv->gfargrp[i]);
1802 if (err) {
1803 for (j = 0; j < i; j++)
1804 free_grp_irqs(&priv->gfargrp[j]);
1805 goto irq_fail;
1806 }
1807 }
1808
7f7f5316 1809 /* Start the controller */
ccc05c6e 1810 gfar_start(ndev);
1da177e4 1811
826aa4a0
AV		 1812 phy_start(priv->phydev);
1813
46ceb60c
SG		 1814 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1815
1da177e4
LT		 1816 return 0;
1817
46ceb60c 1818irq_fail:
e69edd21 1819 free_skb_resources(priv);
1da177e4
LT		 1820 return err;
1821}
1822
1823/* Called when something needs to use the ethernet device */
1824/* Returns 0 for success. */
1825static int gfar_enet_open(struct net_device *dev)
1826{
94e8cc35 1827 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1828 int err;
1829
46ceb60c 1830 enable_napi(priv);
bea3348e 1831
0fd56bb5
AF		 1832 skb_queue_head_init(&priv->rx_recycle);
1833
1da177e4
LT		 1834 /* Initialize a bunch of registers */
1835 init_registers(dev);
1836
1837 gfar_set_mac_address(dev);
1838
1839 err = init_phy(dev);
1840
a12f801d 1841 if (err) {
46ceb60c 1842 disable_napi(priv);
1da177e4 1843 return err;
bea3348e 1844 }
1da177e4
LT		 1845
1846 err = startup_gfar(dev);
db0e8e3f 1847 if (err) {
46ceb60c 1848 disable_napi(priv);
db0e8e3f
AV		 1849 return err;
1850 }
1da177e4 1851
fba4ed03 1852 netif_tx_start_all_queues(dev);
1da177e4 1853
2884e5cc
AV		 1854 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1855
1da177e4
LT		 1856 return err;
1857}
1858
54dc79fe 1859static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1860{
54dc79fe 1861 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1862
1863 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1864
0bbaf069
KG		 1865 return fcb;
1866}
1867
1868static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1869{
7f7f5316 1870 u8 flags = 0;
0bbaf069
KG		 1871
1872 /* If we're here, it's a IP packet with a TCP or UDP
1873 * payload. We set it to checksum, using a pseudo-header
1874 * we provide
1875 */
7f7f5316 1876 flags = TXFCB_DEFAULT;
0bbaf069 1877
7f7f5316
AF		 1878 /* Tell the controller what the protocol is */
1879 /* And provide the already calculated phcs */
eddc9ec5 1880 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 1881 flags |= TXFCB_UDP;
4bedb452 1882 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 1883 } else
8da32de5 1884 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 1885
1886 /* l3os is the distance between the start of the
1887 * frame (skb->data) and the start of the IP hdr.
1888 * l4os is the distance between the start of the
1889 * l3 hdr and the l4 hdr */
bbe735e4 1890 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
cfe1fc77 1891 fcb->l4os = skb_network_header_len(skb);
0bbaf069 1892
7f7f5316 1893 fcb->flags = flags;
0bbaf069
KG		 1894}
1895
7f7f5316 1896void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 1897{
7f7f5316 1898 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 1899 fcb->vlctl = vlan_tx_tag_get(skb);
1900}
1901
4669bc90
DH		 1902static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1903 struct txbd8 *base, int ring_size)
1904{
1905 struct txbd8 *new_bd = bdp + stride;
1906
1907 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1908}
1909
1910static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1911 int ring_size)
1912{
1913 return skip_txbd(bdp, 1, base, ring_size);
1914}
1915
1da177e4
LT		 1916/* This is called by the kernel when a frame is ready for transmission. */
1917/* It is pointed to by the dev->hard_start_xmit function pointer */
1918static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1919{
1920 struct gfar_private *priv = netdev_priv(dev);
a12f801d 1921 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 1922 struct netdev_queue *txq;
f4983704 1923 struct gfar __iomem *regs = NULL;
0bbaf069 1924 struct txfcb *fcb = NULL;
4669bc90 1925 struct txbd8 *txbdp, *txbdp_start, *base;
5a5efed4 1926 u32 lstatus;
fba4ed03 1927 int i, rq = 0;
4669bc90 1928 u32 bufaddr;
fef6108d 1929 unsigned long flags;
4669bc90
DH		 1930 unsigned int nr_frags, length;
1931
fba4ed03
SG		 1932
1933 rq = skb->queue_mapping;
1934 tx_queue = priv->tx_queue[rq];
1935 txq = netdev_get_tx_queue(dev, rq);
a12f801d 1936 base = tx_queue->tx_bd_base;
46ceb60c 1937 regs = tx_queue->grp->regs;
4669bc90 1938
5b28beaf
LY		 1939 /* make space for additional header when fcb is needed */
1940 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1941 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1942 (skb_headroom(skb) < GMAC_FCB_LEN)) {
54dc79fe
SH		 1943 struct sk_buff *skb_new;
1944
1945 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1946 if (!skb_new) {
1947 dev->stats.tx_errors++;
bd14ba84 1948 kfree_skb(skb);
54dc79fe
SH		 1949 return NETDEV_TX_OK;
1950 }
1951 kfree_skb(skb);
1952 skb = skb_new;
1953 }
1954
4669bc90
DH		 1955 /* total number of fragments in the SKB */
1956 nr_frags = skb_shinfo(skb)->nr_frags;
1957
4669bc90 1958 /* check if there is space to queue this packet */
a12f801d 1959 if ((nr_frags+1) > tx_queue->num_txbdfree) {
4669bc90 1960 /* no space, stop the queue */
fba4ed03 1961 netif_tx_stop_queue(txq);
4669bc90 1962 dev->stats.tx_fifo_errors++;
4669bc90
DH		 1963 return NETDEV_TX_BUSY;
1964 }
1da177e4
LT		 1965
1966 /* Update transmit stats */
a7f38041
SG		 1967 txq->tx_bytes += skb->len;
1968 txq->tx_packets ++;
1da177e4 1969
a12f801d 1970 txbdp = txbdp_start = tx_queue->cur_tx;
1da177e4 1971
4669bc90
DH		 1972 if (nr_frags == 0) {
1973 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1974 } else {
1975 /* Place the fragment addresses and lengths into the TxBDs */
1976 for (i = 0; i < nr_frags; i++) {
1977 /* Point at the next BD, wrapping as needed */
a12f801d 1978 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 1979
1980 length = skb_shinfo(skb)->frags[i].size;
1981
1982 lstatus = txbdp->lstatus | length |
1983 BD_LFLAG(TXBD_READY);
1984
1985 /* Handle the last BD specially */
1986 if (i == nr_frags - 1)
1987 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 1988
4826857f 1989 bufaddr = dma_map_page(&priv->ofdev->dev,
4669bc90
DH		 1990 skb_shinfo(skb)->frags[i].page,
1991 skb_shinfo(skb)->frags[i].page_offset,
1992 length,
1993 DMA_TO_DEVICE);
1994
1995 /* set the TxBD length and buffer pointer */
1996 txbdp->bufPtr = bufaddr;
1997 txbdp->lstatus = lstatus;
1998 }
1999
2000 lstatus = txbdp_start->lstatus;
2001 }
1da177e4 2002
0bbaf069 2003 /* Set up checksumming */
12dea57b 2004 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe
SH		 2005 fcb = gfar_add_fcb(skb);
2006 lstatus |= BD_LFLAG(TXBD_TOE);
2007 gfar_tx_checksum(skb, fcb);
0bbaf069
KG		 2008 }
2009
77ecaf2d 2010 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
54dc79fe
SH		 2011 if (unlikely(NULL == fcb)) {
2012 fcb = gfar_add_fcb(skb);
5a5efed4 2013 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 2014 }
54dc79fe
SH		 2015
2016 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 2017 }
2018
4669bc90 2019 /* setup the TxBD length and buffer pointer for the first BD */
4826857f 2020 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
4669bc90 2021 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2022
4669bc90 2023 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1da177e4 2024
a3bc1f11
AV		 2025 /*
2026 * We can work in parallel with gfar_clean_tx_ring(), except
2027 * when modifying num_txbdfree. Note that we didn't grab the lock
2028 * when we were reading the num_txbdfree and checking for available
2029 * space, that's because outside of this function it can only grow,
2030 * and once we've got needed space, it cannot suddenly disappear.
2031 *
2032 * The lock also protects us from gfar_error(), which can modify
2033 * regs->tstat and thus retrigger the transfers, which is why we
2034 * also must grab the lock before setting ready bit for the first
2035 * to be transmitted BD.
2036 */
2037 spin_lock_irqsave(&tx_queue->txlock, flags);
2038
4669bc90
DH		 2039 /*
2040 * The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2041 * semantics (it requires synchronization between cacheable and
2042 * uncacheable mappings, which eieio doesn't provide and which we
2043 * don't need), thus requiring a more expensive sync instruction. At
2044 * some point, the set of architecture-independent barrier functions
2045 * should be expanded to include weaker barriers.
2046 */
3b6330ce 2047 eieio();
7f7f5316 2048
4669bc90
DH		 2049 txbdp_start->lstatus = lstatus;
2050
0eddba52
AV		 2051 eieio(); /* force lstatus write before tx_skbuff */
2052
2053 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2054
4669bc90
DH		 2055 /* Update the current skb pointer to the next entry we will use
2056 * (wrapping if necessary) */
a12f801d
SG		 2057 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2058 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2059
a12f801d 2060 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2061
2062 /* reduce TxBD free count */
a12f801d 2063 tx_queue->num_txbdfree -= (nr_frags + 1);
4669bc90
DH		 2064
2065 dev->trans_start = jiffies;
1da177e4
LT		 2066
2067 /* If the next BD still needs to be cleaned up, then the bds
2068 are full. We need to tell the kernel to stop sending us stuff. */
a12f801d 2069 if (!tx_queue->num_txbdfree) {
fba4ed03 2070 netif_tx_stop_queue(txq);
1da177e4 2071
09f75cd7 2072 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2073 }
2074
1da177e4 2075 /* Tell the DMA to go go go */
fba4ed03 2076 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2077
2078 /* Unlock priv */
a12f801d 2079 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2080
54dc79fe 2081 return NETDEV_TX_OK;
1da177e4
LT		 2082}
2083
2084/* Stops the kernel queue, and halts the controller */
2085static int gfar_close(struct net_device *dev)
2086{
2087 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2088
46ceb60c 2089 disable_napi(priv);
bea3348e 2090
0fd56bb5 2091 skb_queue_purge(&priv->rx_recycle);
ab939905 2092 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2093 stop_gfar(dev);
2094
bb40dcbb
AF		 2095 /* Disconnect from the PHY */
2096 phy_disconnect(priv->phydev);
2097 priv->phydev = NULL;
1da177e4 2098
fba4ed03 2099 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2100
2101 return 0;
2102}
2103
1da177e4 2104/* Changes the mac address if the controller is not running. */
f162b9d5 2105static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2106{
7f7f5316 2107 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2108
2109 return 0;
2110}
2111
2112
0bbaf069
KG		 2113/* Enables and disables VLAN insertion/extraction */
2114static void gfar_vlan_rx_register(struct net_device *dev,
2115 struct vlan_group *grp)
2116{
2117 struct gfar_private *priv = netdev_priv(dev);
f4983704 2118 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2119 unsigned long flags;
2120 u32 tempval;
2121
46ceb60c 2122 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2123 local_irq_save(flags);
2124 lock_rx_qs(priv);
0bbaf069 2125
cd1f55a5 2126 priv->vlgrp = grp;
0bbaf069
KG		 2127
2128 if (grp) {
2129 /* Enable VLAN tag insertion */
f4983704 2130 tempval = gfar_read(&regs->tctrl);
0bbaf069
KG		 2131 tempval |= TCTRL_VLINS;
2132
f4983704 2133 gfar_write(&regs->tctrl, tempval);
6aa20a22 2134
0bbaf069 2135 /* Enable VLAN tag extraction */
f4983704 2136 tempval = gfar_read(&regs->rctrl);
77ecaf2d 2137 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
f4983704 2138 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2139 } else {
2140 /* Disable VLAN tag insertion */
f4983704 2141 tempval = gfar_read(&regs->tctrl);
0bbaf069 2142 tempval &= ~TCTRL_VLINS;
f4983704 2143 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2144
2145 /* Disable VLAN tag extraction */
f4983704 2146 tempval = gfar_read(&regs->rctrl);
0bbaf069 2147 tempval &= ~RCTRL_VLEX;
77ecaf2d
DH		 2148 /* If parse is no longer required, then disable parser */
2149 if (tempval & RCTRL_REQ_PARSER)
2150 tempval |= RCTRL_PRSDEP_INIT;
2151 else
2152 tempval &= ~RCTRL_PRSDEP_INIT;
f4983704 2153 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2154 }
2155
77ecaf2d
DH		 2156 gfar_change_mtu(dev, dev->mtu);
2157
fba4ed03
SG		 2158 unlock_rx_qs(priv);
2159 local_irq_restore(flags);
0bbaf069
KG		 2160}
2161
1da177e4
LT		 2162static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2163{
2164 int tempsize, tempval;
2165 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2166 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2167 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2168 int frame_size = new_mtu + ETH_HLEN;
2169
77ecaf2d 2170 if (priv->vlgrp)
faa89577 2171 frame_size += VLAN_HLEN;
0bbaf069 2172
1da177e4 2173 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
0bbaf069
KG		 2174 if (netif_msg_drv(priv))
2175 printk(KERN_ERR "%s: Invalid MTU setting\n",
2176 dev->name);
1da177e4
LT		 2177 return -EINVAL;
2178 }
2179
77ecaf2d
DH		 2180 if (gfar_uses_fcb(priv))
2181 frame_size += GMAC_FCB_LEN;
2182
2183 frame_size += priv->padding;
2184
1da177e4
LT		 2185 tempsize =
2186 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2187 INCREMENTAL_BUFFER_SIZE;
2188
2189 /* Only stop and start the controller if it isn't already
7f7f5316 2190 * stopped, and we changed something */
1da177e4
LT		 2191 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2192 stop_gfar(dev);
2193
2194 priv->rx_buffer_size = tempsize;
2195
2196 dev->mtu = new_mtu;
2197
f4983704
SG		 2198 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2199 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2200
2201 /* If the mtu is larger than the max size for standard
2202 * ethernet frames (ie, a jumbo frame), then set maccfg2
2203 * to allow huge frames, and to check the length */
f4983704 2204 tempval = gfar_read(&regs->maccfg2);
1da177e4
LT		 2205
2206 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
2207 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2208 else
2209 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2210
f4983704 2211 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2212
2213 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2214 startup_gfar(dev);
2215
2216 return 0;
2217}
2218
ab939905 2219/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2220 * transmitted after a set amount of time.
2221 * For now, assume that clearing out all the structures, and
ab939905
SS		 2222 * starting over will fix the problem.
2223 */
2224static void gfar_reset_task(struct work_struct *work)
1da177e4 2225{
ab939905
SS		 2226 struct gfar_private *priv = container_of(work, struct gfar_private,
2227 reset_task);
4826857f 2228 struct net_device *dev = priv->ndev;
1da177e4
LT		 2229
2230 if (dev->flags & IFF_UP) {
fba4ed03 2231 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2232 stop_gfar(dev);
2233 startup_gfar(dev);
fba4ed03 2234 netif_tx_start_all_queues(dev);
1da177e4
LT		 2235 }
2236
263ba320 2237 netif_tx_schedule_all(dev);
1da177e4
LT		 2238}
2239
ab939905
SS		 2240static void gfar_timeout(struct net_device *dev)
2241{
2242 struct gfar_private *priv = netdev_priv(dev);
2243
2244 dev->stats.tx_errors++;
2245 schedule_work(&priv->reset_task);
2246}
2247
1da177e4 2248/* Interrupt Handler for Transmit complete */
a12f801d 2249static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2250{
a12f801d 2251 struct net_device *dev = tx_queue->dev;
d080cd63 2252 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2253 struct gfar_priv_rx_q *rx_queue = NULL;
4669bc90
DH		 2254 struct txbd8 *bdp;
2255 struct txbd8 *lbdp = NULL;
a12f801d 2256 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2257 struct sk_buff *skb;
2258 int skb_dirtytx;
a12f801d 2259 int tx_ring_size = tx_queue->tx_ring_size;
4669bc90
DH		 2260 int frags = 0;
2261 int i;
d080cd63 2262 int howmany = 0;
4669bc90 2263 u32 lstatus;
1da177e4 2264
fba4ed03 2265 rx_queue = priv->rx_queue[tx_queue->qindex];
a12f801d
SG		 2266 bdp = tx_queue->dirty_tx;
2267 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2268
a12f801d 2269 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2270 unsigned long flags;
2271
4669bc90
DH		 2272 frags = skb_shinfo(skb)->nr_frags;
2273 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1da177e4 2274
4669bc90 2275 lstatus = lbdp->lstatus;
1da177e4 2276
4669bc90
DH		 2277 /* Only clean completed frames */
2278 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2279 (lstatus & BD_LENGTH_MASK))
2280 break;
2281
4826857f 2282 dma_unmap_single(&priv->ofdev->dev,
4669bc90
DH		 2283 bdp->bufPtr,
2284 bdp->length,
2285 DMA_TO_DEVICE);
81183059 2286
4669bc90
DH		 2287 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2288 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2289
4669bc90 2290 for (i = 0; i < frags; i++) {
4826857f 2291 dma_unmap_page(&priv->ofdev->dev,
4669bc90
DH		 2292 bdp->bufPtr,
2293 bdp->length,
2294 DMA_TO_DEVICE);
2295 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2296 bdp = next_txbd(bdp, base, tx_ring_size);
2297 }
1da177e4 2298
0fd56bb5
AF		 2299 /*
2300 * If there's room in the queue (limit it to rx_buffer_size)
2301 * we add this skb back into the pool, if it's the right size
2302 */
a12f801d 2303 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
0fd56bb5
AF		 2304 skb_recycle_check(skb, priv->rx_buffer_size +
2305 RXBUF_ALIGNMENT))
2306 __skb_queue_head(&priv->rx_recycle, skb);
2307 else
2308 dev_kfree_skb_any(skb);
2309
a12f801d 2310 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2311
4669bc90
DH		 2312 skb_dirtytx = (skb_dirtytx + 1) &
2313 TX_RING_MOD_MASK(tx_ring_size);
2314
2315 howmany++;
a3bc1f11 2316 spin_lock_irqsave(&tx_queue->txlock, flags);
a12f801d 2317 tx_queue->num_txbdfree += frags + 1;
a3bc1f11 2318 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2319 }
1da177e4 2320
4669bc90 2321 /* If we freed a buffer, we can restart transmission, if necessary */
fba4ed03
SG		 2322 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2323 netif_wake_subqueue(dev, tx_queue->qindex);
1da177e4 2324
4669bc90 2325 /* Update dirty indicators */
a12f801d
SG		 2326 tx_queue->skb_dirtytx = skb_dirtytx;
2327 tx_queue->dirty_tx = bdp;
1da177e4 2328
d080cd63
DH		 2329 return howmany;
2330}
2331
f4983704 2332static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2333{
a6d0b91a
AV		 2334 unsigned long flags;
2335
fba4ed03
SG		 2336 spin_lock_irqsave(&gfargrp->grplock, flags);
2337 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2338 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2339 __napi_schedule(&gfargrp->napi);
8707bdd4
JP		 2340 } else {
2341 /*
2342 * Clear IEVENT, so interrupts aren't called again
2343 * because of the packets that have already arrived.
2344 */
f4983704 2345 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2346 }
fba4ed03 2347 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2348
8c7396ae 2349}
1da177e4 2350
8c7396ae 2351/* Interrupt Handler for Transmit complete */
f4983704 2352static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2353{
f4983704 2354 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2355 return IRQ_HANDLED;
2356}
2357
a12f801d 2358static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6
AF		 2359 struct sk_buff *skb)
2360{
a12f801d 2361 struct net_device *dev = rx_queue->dev;
815b97c6 2362 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2363 dma_addr_t buf;
815b97c6 2364
8a102fe0
AV		 2365 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2366 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2367 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2368}
2369
2370
2371struct sk_buff * gfar_new_skb(struct net_device *dev)
1da177e4 2372{
7f7f5316 2373 unsigned int alignamount;
1da177e4
LT		 2374 struct gfar_private *priv = netdev_priv(dev);
2375 struct sk_buff *skb = NULL;
1da177e4 2376
0fd56bb5
AF		 2377 skb = __skb_dequeue(&priv->rx_recycle);
2378 if (!skb)
2379 skb = netdev_alloc_skb(dev,
2380 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1da177e4 2381
815b97c6 2382 if (!skb)
1da177e4
LT		 2383 return NULL;
2384
7f7f5316 2385 alignamount = RXBUF_ALIGNMENT -
bea3348e 2386 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
7f7f5316 2387
1da177e4
LT		 2388 /* We need the data buffer to be aligned properly. We will reserve
2389 * as many bytes as needed to align the data properly
2390 */
7f7f5316 2391 skb_reserve(skb, alignamount);
a6d36d56 2392 GFAR_CB(skb)->alignamount = alignamount;
1da177e4 2393
1da177e4
LT		 2394 return skb;
2395}
2396
298e1a9e 2397static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2398{
298e1a9e 2399 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2400 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2401 struct gfar_extra_stats *estats = &priv->extra_stats;
2402
2403 /* If the packet was truncated, none of the other errors
2404 * matter */
2405 if (status & RXBD_TRUNCATED) {
2406 stats->rx_length_errors++;
2407
2408 estats->rx_trunc++;
2409
2410 return;
2411 }
2412 /* Count the errors, if there were any */
2413 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2414 stats->rx_length_errors++;
2415
2416 if (status & RXBD_LARGE)
2417 estats->rx_large++;
2418 else
2419 estats->rx_short++;
2420 }
2421 if (status & RXBD_NONOCTET) {
2422 stats->rx_frame_errors++;
2423 estats->rx_nonoctet++;
2424 }
2425 if (status & RXBD_CRCERR) {
2426 estats->rx_crcerr++;
2427 stats->rx_crc_errors++;
2428 }
2429 if (status & RXBD_OVERRUN) {
2430 estats->rx_overrun++;
2431 stats->rx_crc_errors++;
2432 }
2433}
2434
f4983704 2435irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2436{
f4983704 2437 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2438 return IRQ_HANDLED;
2439}
2440
0bbaf069
KG		 2441static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2442{
2443 /* If valid headers were found, and valid sums
2444 * were verified, then we tell the kernel that no
2445 * checksumming is necessary. Otherwise, it is */
7f7f5316 2446 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2447 skb->ip_summed = CHECKSUM_UNNECESSARY;
2448 else
2449 skb->ip_summed = CHECKSUM_NONE;
2450}
2451
2452
1da177e4
LT		 2453/* gfar_process_frame() -- handle one incoming packet if skb
2454 * isn't NULL. */
2455static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2c2db48a 2456 int amount_pull)
1da177e4
LT		 2457{
2458 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2459 struct rxfcb *fcb = NULL;
1da177e4 2460
2c2db48a 2461 int ret;
1da177e4 2462
2c2db48a
DH		 2463 /* fcb is at the beginning if exists */
2464 fcb = (struct rxfcb *)skb->data;
0bbaf069 2465
2c2db48a
DH		 2466 /* Remove the FCB from the skb */
2467 /* Remove the padded bytes, if there are any */
f74dac08
SG		 2468 if (amount_pull) {
2469 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2470 skb_pull(skb, amount_pull);
f74dac08 2471 }
0bbaf069 2472
2c2db48a
DH		 2473 if (priv->rx_csum_enable)
2474 gfar_rx_checksum(skb, fcb);
0bbaf069 2475
2c2db48a
DH		 2476 /* Tell the skb what kind of packet this is */
2477 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2478
2c2db48a
DH		 2479 /* Send the packet up the stack */
2480 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2481 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2482 else
2483 ret = netif_receive_skb(skb);
0bbaf069 2484
2c2db48a
DH		 2485 if (NET_RX_DROP == ret)
2486 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 2487
2488 return 0;
2489}
2490
2491/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 2492 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 2493 * of frames handled
2494 */
a12f801d 2495int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2496{
a12f801d 2497 struct net_device *dev = rx_queue->dev;
31de198b 2498 struct rxbd8 *bdp, *base;
1da177e4 2499 struct sk_buff *skb;
2c2db48a
DH		 2500 int pkt_len;
2501 int amount_pull;
1da177e4
LT		 2502 int howmany = 0;
2503 struct gfar_private *priv = netdev_priv(dev);
2504
2505 /* Get the first full descriptor */
a12f801d
SG		 2506 bdp = rx_queue->cur_rx;
2507 base = rx_queue->rx_bd_base;
1da177e4 2508
2c2db48a
DH		 2509 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
2510 priv->padding;
2511
1da177e4 2512 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2513 struct sk_buff *newskb;
3b6330ce 2514 rmb();
815b97c6
AF		 2515
2516 /* Add another skb for the future */
2517 newskb = gfar_new_skb(dev);
2518
a12f801d 2519 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2520
4826857f 2521 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
81183059
AF		 2522 priv->rx_buffer_size, DMA_FROM_DEVICE);
2523
815b97c6
AF		 2524 /* We drop the frame if we failed to allocate a new buffer */
2525 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2526 bdp->status & RXBD_ERR)) {
2527 count_errors(bdp->status, dev);
2528
2529 if (unlikely(!newskb))
2530 newskb = skb;
4e2fd555
LB		 2531 else if (skb) {
2532 /*
a6d36d56 2533 * We need to un-reserve() the skb to what it
4e2fd555
LB		 2534 * was before gfar_new_skb() re-aligned
2535 * it to an RXBUF_ALIGNMENT boundary
2536 * before we put the skb back on the
2537 * recycle list.
2538 */
a6d36d56 2539 skb_reserve(skb, -GFAR_CB(skb)->alignamount);
0fd56bb5 2540 __skb_queue_head(&priv->rx_recycle, skb);
4e2fd555 2541 }
815b97c6 2542 } else {
1da177e4 2543 /* Increment the number of packets */
a7f38041 2544 rx_queue->stats.rx_packets++;
1da177e4
LT		 2545 howmany++;
2546
2c2db48a
DH		 2547 if (likely(skb)) {
2548 pkt_len = bdp->length - ETH_FCS_LEN;
2549 /* Remove the FCS from the packet length */
2550 skb_put(skb, pkt_len);
a7f38041 2551 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2552 skb_record_rx_queue(skb, rx_queue->qindex);
2c2db48a
DH		 2553 gfar_process_frame(dev, skb, amount_pull);
2554
2555 } else {
2556 if (netif_msg_rx_err(priv))
2557 printk(KERN_WARNING
2558 "%s: Missing skb!\n", dev->name);
a7f38041 2559 rx_queue->stats.rx_dropped++;
2c2db48a
DH		 2560 priv->extra_stats.rx_skbmissing++;
2561 }
1da177e4 2562
1da177e4
LT		 2563 }
2564
a12f801d 2565 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2566
815b97c6 2567 /* Setup the new bdp */
a12f801d 2568 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2569
2570 /* Update to the next pointer */
a12f801d 2571 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2572
2573 /* update to point at the next skb */
a12f801d
SG		 2574 rx_queue->skb_currx =
2575 (rx_queue->skb_currx + 1) &
2576 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2577 }
2578
2579 /* Update the current rxbd pointer to be the next one */
a12f801d 2580 rx_queue->cur_rx = bdp;
1da177e4 2581
1da177e4
LT		 2582 return howmany;
2583}
2584
bea3348e 2585static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2586{
fba4ed03
SG		 2587 struct gfar_priv_grp *gfargrp = container_of(napi,
2588 struct gfar_priv_grp, napi);
2589 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2590 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2591 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03
SG		 2592 struct gfar_priv_rx_q *rx_queue = NULL;
2593 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
18294ad1
AV		 2594 int tx_cleaned = 0, i, left_over_budget = budget;
2595 unsigned long serviced_queues = 0;
fba4ed03 2596 int num_queues = 0;
d080cd63 2597
fba4ed03
SG		 2598 num_queues = gfargrp->num_rx_queues;
2599 budget_per_queue = budget/num_queues;
2600
8c7396ae
DH		 2601 /* Clear IEVENT, so interrupts aren't called again
2602 * because of the packets that have already arrived */
f4983704 2603 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2604
fba4ed03 2605 while (num_queues && left_over_budget) {
1da177e4 2606
fba4ed03
SG		 2607 budget_per_queue = left_over_budget/num_queues;
2608 left_over_budget = 0;
2609
984b3f57 2610 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
fba4ed03
SG		 2611 if (test_bit(i, &serviced_queues))
2612 continue;
2613 rx_queue = priv->rx_queue[i];
2614 tx_queue = priv->tx_queue[rx_queue->qindex];
2615
a3bc1f11 2616 tx_cleaned += gfar_clean_tx_ring(tx_queue);
fba4ed03
SG		 2617 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2618 budget_per_queue);
2619 rx_cleaned += rx_cleaned_per_queue;
2620 if(rx_cleaned_per_queue < budget_per_queue) {
2621 left_over_budget = left_over_budget +
2622 (budget_per_queue - rx_cleaned_per_queue);
2623 set_bit(i, &serviced_queues);
2624 num_queues--;
2625 }
2626 }
2627 }
1da177e4 2628
42199884
AF		 2629 if (tx_cleaned)
2630 return budget;
2631
2632 if (rx_cleaned < budget) {
288379f0 2633 napi_complete(napi);
1da177e4
LT		 2634
2635 /* Clear the halt bit in RSTAT */
fba4ed03 2636 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2637
f4983704 2638 gfar_write(&regs->imask, IMASK_DEFAULT);
1da177e4
LT		 2639
2640 /* If we are coalescing interrupts, update the timer */
2641 /* Otherwise, clear it */
46ceb60c
SG		 2642 gfar_configure_coalescing(priv,
2643 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
1da177e4
LT		 2644 }
2645
42199884 2646 return rx_cleaned;
1da177e4 2647}
1da177e4 2648
f2d71c2d
VW		 2649#ifdef CONFIG_NET_POLL_CONTROLLER
2650/*
2651 * Polling 'interrupt' - used by things like netconsole to send skbs
2652 * without having to re-enable interrupts. It's not called while
2653 * the interrupt routine is executing.
2654 */
2655static void gfar_netpoll(struct net_device *dev)
2656{
2657 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2658 int i = 0;
f2d71c2d
VW		 2659
2660 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2661 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 2662 for (i = 0; i < priv->num_grps; i++) {
2663 disable_irq(priv->gfargrp[i].interruptTransmit);
2664 disable_irq(priv->gfargrp[i].interruptReceive);
2665 disable_irq(priv->gfargrp[i].interruptError);
2666 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2667 &priv->gfargrp[i]);
2668 enable_irq(priv->gfargrp[i].interruptError);
2669 enable_irq(priv->gfargrp[i].interruptReceive);
2670 enable_irq(priv->gfargrp[i].interruptTransmit);
2671 }
f2d71c2d 2672 } else {
46ceb60c
SG		 2673 for (i = 0; i < priv->num_grps; i++) {
2674 disable_irq(priv->gfargrp[i].interruptTransmit);
2675 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2676 &priv->gfargrp[i]);
2677 enable_irq(priv->gfargrp[i].interruptTransmit);
43de004b 2678 }
f2d71c2d
VW		 2679 }
2680}
2681#endif
2682
1da177e4 2683/* The interrupt handler for devices with one interrupt */
f4983704 2684static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2685{
f4983704 2686 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2687
2688 /* Save ievent for future reference */
f4983704 2689 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2690
1da177e4 2691 /* Check for reception */
538cc7ee 2692 if (events & IEVENT_RX_MASK)
f4983704 2693 gfar_receive(irq, grp_id);
1da177e4
LT		 2694
2695 /* Check for transmit completion */
538cc7ee 2696 if (events & IEVENT_TX_MASK)
f4983704 2697 gfar_transmit(irq, grp_id);
1da177e4 2698
538cc7ee
SS		 2699 /* Check for errors */
2700 if (events & IEVENT_ERR_MASK)
f4983704 2701 gfar_error(irq, grp_id);
1da177e4
LT		 2702
2703 return IRQ_HANDLED;
2704}
2705
1da177e4
LT		 2706/* Called every time the controller might need to be made
2707 * aware of new link state. The PHY code conveys this
bb40dcbb 2708 * information through variables in the phydev structure, and this
1da177e4
LT		 2709 * function converts those variables into the appropriate
2710 * register values, and can bring down the device if needed.
2711 */
2712static void adjust_link(struct net_device *dev)
2713{
2714 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2715 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2716 unsigned long flags;
2717 struct phy_device *phydev = priv->phydev;
2718 int new_state = 0;
2719
fba4ed03
SG		 2720 local_irq_save(flags);
2721 lock_tx_qs(priv);
2722
bb40dcbb
AF		 2723 if (phydev->link) {
2724 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2725 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2726
1da177e4
LT		 2727 /* Now we make sure that we can be in full duplex mode.
2728 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 2729 if (phydev->duplex != priv->oldduplex) {
2730 new_state = 1;
2731 if (!(phydev->duplex))
1da177e4 2732 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2733 else
1da177e4 2734 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2735
bb40dcbb 2736 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2737 }
2738
bb40dcbb
AF		 2739 if (phydev->speed != priv->oldspeed) {
2740 new_state = 1;
2741 switch (phydev->speed) {
1da177e4 2742 case 1000:
1da177e4
LT		 2743 tempval =
2744 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 2745
2746 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2747 break;
2748 case 100:
2749 case 10:
1da177e4
LT		 2750 tempval =
2751 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 2752
2753 /* Reduced mode distinguishes
2754 * between 10 and 100 */
2755 if (phydev->speed == SPEED_100)
2756 ecntrl |= ECNTRL_R100;
2757 else
2758 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2759 break;
2760 default:
0bbaf069
KG		 2761 if (netif_msg_link(priv))
2762 printk(KERN_WARNING
bb40dcbb
AF		 2763 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2764 dev->name, phydev->speed);
1da177e4
LT		 2765 break;
2766 }
2767
bb40dcbb 2768 priv->oldspeed = phydev->speed;
1da177e4
LT		 2769 }
2770
bb40dcbb 2771 gfar_write(&regs->maccfg2, tempval);
7f7f5316 2772 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 2773
1da177e4 2774 if (!priv->oldlink) {
bb40dcbb 2775 new_state = 1;
1da177e4 2776 priv->oldlink = 1;
1da177e4 2777 }
bb40dcbb
AF		 2778 } else if (priv->oldlink) {
2779 new_state = 1;
2780 priv->oldlink = 0;
2781 priv->oldspeed = 0;
2782 priv->oldduplex = -1;
1da177e4 2783 }
1da177e4 2784
bb40dcbb
AF		 2785 if (new_state && netif_msg_link(priv))
2786 phy_print_status(phydev);
fba4ed03
SG		 2787 unlock_tx_qs(priv);
2788 local_irq_restore(flags);
bb40dcbb 2789}
1da177e4
LT		 2790
2791/* Update the hash table based on the current list of multicast
2792 * addresses we subscribe to. Also, change the promiscuity of
2793 * the device based on the flags (this function is called
2794 * whenever dev->flags is changed */
2795static void gfar_set_multi(struct net_device *dev)
2796{
2797 struct dev_mc_list *mc_ptr;
2798 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2799 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 2800 u32 tempval;
2801
a12f801d 2802 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 2803 /* Set RCTRL to PROM */
2804 tempval = gfar_read(&regs->rctrl);
2805 tempval |= RCTRL_PROM;
2806 gfar_write(&regs->rctrl, tempval);
2807 } else {
2808 /* Set RCTRL to not PROM */
2809 tempval = gfar_read(&regs->rctrl);
2810 tempval &= ~(RCTRL_PROM);
2811 gfar_write(&regs->rctrl, tempval);
2812 }
6aa20a22 2813
a12f801d 2814 if (dev->flags & IFF_ALLMULTI) {
1da177e4 2815 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 2816 gfar_write(&regs->igaddr0, 0xffffffff);
2817 gfar_write(&regs->igaddr1, 0xffffffff);
2818 gfar_write(&regs->igaddr2, 0xffffffff);
2819 gfar_write(&regs->igaddr3, 0xffffffff);
2820 gfar_write(&regs->igaddr4, 0xffffffff);
2821 gfar_write(&regs->igaddr5, 0xffffffff);
2822 gfar_write(&regs->igaddr6, 0xffffffff);
2823 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 2824 gfar_write(&regs->gaddr0, 0xffffffff);
2825 gfar_write(&regs->gaddr1, 0xffffffff);
2826 gfar_write(&regs->gaddr2, 0xffffffff);
2827 gfar_write(&regs->gaddr3, 0xffffffff);
2828 gfar_write(&regs->gaddr4, 0xffffffff);
2829 gfar_write(&regs->gaddr5, 0xffffffff);
2830 gfar_write(&regs->gaddr6, 0xffffffff);
2831 gfar_write(&regs->gaddr7, 0xffffffff);
2832 } else {
7f7f5316
AF		 2833 int em_num;
2834 int idx;
2835
1da177e4 2836 /* zero out the hash */
0bbaf069
KG		 2837 gfar_write(&regs->igaddr0, 0x0);
2838 gfar_write(&regs->igaddr1, 0x0);
2839 gfar_write(&regs->igaddr2, 0x0);
2840 gfar_write(&regs->igaddr3, 0x0);
2841 gfar_write(&regs->igaddr4, 0x0);
2842 gfar_write(&regs->igaddr5, 0x0);
2843 gfar_write(&regs->igaddr6, 0x0);
2844 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 2845 gfar_write(&regs->gaddr0, 0x0);
2846 gfar_write(&regs->gaddr1, 0x0);
2847 gfar_write(&regs->gaddr2, 0x0);
2848 gfar_write(&regs->gaddr3, 0x0);
2849 gfar_write(&regs->gaddr4, 0x0);
2850 gfar_write(&regs->gaddr5, 0x0);
2851 gfar_write(&regs->gaddr6, 0x0);
2852 gfar_write(&regs->gaddr7, 0x0);
2853
7f7f5316
AF		 2854 /* If we have extended hash tables, we need to
2855 * clear the exact match registers to prepare for
2856 * setting them */
2857 if (priv->extended_hash) {
2858 em_num = GFAR_EM_NUM + 1;
2859 gfar_clear_exact_match(dev);
2860 idx = 1;
2861 } else {
2862 idx = 0;
2863 em_num = 0;
2864 }
2865
4cd24eaf 2866 if (netdev_mc_empty(dev))
1da177e4
LT		 2867 return;
2868
2869 /* Parse the list, and set the appropriate bits */
48e2f183 2870 netdev_for_each_mc_addr(mc_ptr, dev) {
7f7f5316
AF		 2871 if (idx < em_num) {
2872 gfar_set_mac_for_addr(dev, idx,
2873 mc_ptr->dmi_addr);
2874 idx++;
2875 } else
2876 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1da177e4
LT		 2877 }
2878 }
2879
2880 return;
2881}
2882
7f7f5316
AF		 2883
2884/* Clears each of the exact match registers to zero, so they
2885 * don't interfere with normal reception */
2886static void gfar_clear_exact_match(struct net_device *dev)
2887{
2888 int idx;
2889 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2890
2891 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2892 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2893}
2894
1da177e4
LT		 2895/* Set the appropriate hash bit for the given addr */
2896/* The algorithm works like so:
2897 * 1) Take the Destination Address (ie the multicast address), and
2898 * do a CRC on it (little endian), and reverse the bits of the
2899 * result.
2900 * 2) Use the 8 most significant bits as a hash into a 256-entry
2901 * table. The table is controlled through 8 32-bit registers:
2902 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2903 * gaddr7. This means that the 3 most significant bits in the
2904 * hash index which gaddr register to use, and the 5 other bits
2905 * indicate which bit (assuming an IBM numbering scheme, which
2906 * for PowerPC (tm) is usually the case) in the register holds
2907 * the entry. */
2908static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2909{
2910 u32 tempval;
2911 struct gfar_private *priv = netdev_priv(dev);
1da177e4 2912 u32 result = ether_crc(MAC_ADDR_LEN, addr);
0bbaf069
KG		 2913 int width = priv->hash_width;
2914 u8 whichbit = (result >> (32 - width)) & 0x1f;
2915 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 2916 u32 value = (1 << (31-whichbit));
2917
0bbaf069 2918 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 2919 tempval |= value;
0bbaf069 2920 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 2921
2922 return;
2923}
2924
7f7f5316
AF		 2925
2926/* There are multiple MAC Address register pairs on some controllers
2927 * This function sets the numth pair to a given address
2928 */
2929static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2930{
2931 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2932 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316
AF		 2933 int idx;
2934 char tmpbuf[MAC_ADDR_LEN];
2935 u32 tempval;
f4983704 2936 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 2937
2938 macptr += num*2;
2939
2940 /* Now copy it into the mac registers backwards, cuz */
2941 /* little endian is silly */
2942 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2943 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2944
2945 gfar_write(macptr, *((u32 *) (tmpbuf)));
2946
2947 tempval = *((u32 *) (tmpbuf + 4));
2948
2949 gfar_write(macptr+1, tempval);
2950}
2951
1da177e4 2952/* GFAR error interrupt handler */
f4983704 2953static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 2954{
f4983704
SG		 2955 struct gfar_priv_grp *gfargrp = grp_id;
2956 struct gfar __iomem *regs = gfargrp->regs;
2957 struct gfar_private *priv= gfargrp->priv;
2958 struct net_device *dev = priv->ndev;
1da177e4
LT		 2959
2960 /* Save ievent for future reference */
f4983704 2961 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 2962
2963 /* Clear IEVENT */
f4983704 2964 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 2965
2966 /* Magic Packet is not an error. */
b31a1d8b 2967 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 2968 (events & IEVENT_MAG))
2969 events &= ~IEVENT_MAG;
1da177e4
LT		 2970
2971 /* Hmm... */
0bbaf069
KG		 2972 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2973 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
f4983704 2974 dev->name, events, gfar_read(&regs->imask));
1da177e4
LT		 2975
2976 /* Update the error counters */
2977 if (events & IEVENT_TXE) {
09f75cd7 2978 dev->stats.tx_errors++;
1da177e4
LT		 2979
2980 if (events & IEVENT_LC)
09f75cd7 2981 dev->stats.tx_window_errors++;
1da177e4 2982 if (events & IEVENT_CRL)
09f75cd7 2983 dev->stats.tx_aborted_errors++;
1da177e4 2984 if (events & IEVENT_XFUN) {
836cf7fa
AV		 2985 unsigned long flags;
2986
0bbaf069 2987 if (netif_msg_tx_err(priv))
538cc7ee
SS		 2988 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2989 "packet dropped.\n", dev->name);
09f75cd7 2990 dev->stats.tx_dropped++;
1da177e4
LT		 2991 priv->extra_stats.tx_underrun++;
2992
836cf7fa
AV		 2993 local_irq_save(flags);
2994 lock_tx_qs(priv);
2995
1da177e4 2996 /* Reactivate the Tx Queues */
fba4ed03 2997 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 2998
2999 unlock_tx_qs(priv);
3000 local_irq_restore(flags);
1da177e4 3001 }
0bbaf069
KG		 3002 if (netif_msg_tx_err(priv))
3003 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1da177e4
LT		 3004 }
3005 if (events & IEVENT_BSY) {
09f75cd7 3006 dev->stats.rx_errors++;
1da177e4
LT		 3007 priv->extra_stats.rx_bsy++;
3008
f4983704 3009 gfar_receive(irq, grp_id);
1da177e4 3010
0bbaf069 3011 if (netif_msg_rx_err(priv))
538cc7ee 3012 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
f4983704 3013 dev->name, gfar_read(&regs->rstat));
1da177e4
LT		 3014 }
3015 if (events & IEVENT_BABR) {
09f75cd7 3016 dev->stats.rx_errors++;
1da177e4
LT		 3017 priv->extra_stats.rx_babr++;
3018
0bbaf069 3019 if (netif_msg_rx_err(priv))
538cc7ee 3020 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1da177e4
LT		 3021 }
3022 if (events & IEVENT_EBERR) {
3023 priv->extra_stats.eberr++;
0bbaf069 3024 if (netif_msg_rx_err(priv))
538cc7ee 3025 printk(KERN_DEBUG "%s: bus error\n", dev->name);
1da177e4 3026 }
0bbaf069 3027 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
538cc7ee 3028 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1da177e4
LT		 3029
3030 if (events & IEVENT_BABT) {
3031 priv->extra_stats.tx_babt++;
0bbaf069 3032 if (netif_msg_tx_err(priv))
538cc7ee 3033 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1da177e4
LT		 3034 }
3035 return IRQ_HANDLED;
3036}
3037
b31a1d8b
AF		 3038static struct of_device_id gfar_match[] =
3039{
3040 {
3041 .type = "network",
3042 .compatible = "gianfar",
3043 },
46ceb60c
SG		 3044 {
3045 .compatible = "fsl,etsec2",
3046 },
b31a1d8b
AF		 3047 {},
3048};
e72701ac 3049MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3050
1da177e4 3051/* Structure for a device driver */
b31a1d8b
AF		 3052static struct of_platform_driver gfar_driver = {
3053 .name = "fsl-gianfar",
3054 .match_table = gfar_match,
3055
1da177e4
LT		 3056 .probe = gfar_probe,
3057 .remove = gfar_remove,
be926fc4
AV		 3058 .suspend = gfar_legacy_suspend,
3059 .resume = gfar_legacy_resume,
3060 .driver.pm = GFAR_PM_OPS,
1da177e4
LT		 3061};
3062
3063static int __init gfar_init(void)
3064{
1577ecef 3065 return of_register_platform_driver(&gfar_driver);
1da177e4
LT		 3066}
3067
3068static void __exit gfar_exit(void)
3069{
b31a1d8b 3070 of_unregister_platform_driver(&gfar_driver);
1da177e4
LT		 3071}
3072
3073module_init(gfar_init);
3074module_exit(gfar_exit);
3075
Clone of davem's net-next-2.6 tree