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1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
926bd900 3 * Copyright(c) 2002-2010 Exar Corp.
d44570e4 4 *
1da177e4
LT		 5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4 27 * The module loadable parameters that are supported by the driver and a brief
a2a20aef 28 * explanation of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
958de193 41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
6cef2b8e
JP		 57#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
1da177e4
LT		 59#include <linux/module.h>
60#include <linux/types.h>
61#include <linux/errno.h>
62#include <linux/ioport.h>
63#include <linux/pci.h>
1e7f0bd8 64#include <linux/dma-mapping.h>
1da177e4
LT		 65#include <linux/kernel.h>
66#include <linux/netdevice.h>
67#include <linux/etherdevice.h>
40239396 68#include <linux/mdio.h>
1da177e4
LT		 69#include <linux/skbuff.h>
70#include <linux/init.h>
71#include <linux/delay.h>
72#include <linux/stddef.h>
73#include <linux/ioctl.h>
74#include <linux/timex.h>
1da177e4 75#include <linux/ethtool.h>
1da177e4 76#include <linux/workqueue.h>
be3a6b02 77#include <linux/if_vlan.h>
7d3d0439
RA		 78#include <linux/ip.h>
79#include <linux/tcp.h>
d44570e4
JP		 80#include <linux/uaccess.h>
81#include <linux/io.h>
5a0e3ad6 82#include <linux/slab.h>
7d3d0439 83#include <net/tcp.h>
1da177e4 84
1da177e4 85#include <asm/system.h>
fe931395 86#include <asm/div64.h>
330ce0de 87#include <asm/irq.h>
1da177e4
LT		 88
89/* local include */
90#include "s2io.h"
91#include "s2io-regs.h"
92
958de193 93#define DRV_VERSION "2.0.26.26"
6c1792f4 94
1da177e4 95/* S2io Driver name & version. */
20346722 96static char s2io_driver_name[] = "Neterion";
6c1792f4 97static char s2io_driver_version[] = DRV_VERSION;
1da177e4 98
d44570e4
JP		 99static int rxd_size[2] = {32, 48};
100static int rxd_count[2] = {127, 85};
da6971d8 101
1ee6dd77 102static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 103{
104 int ret;
105
106 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
d44570e4 107 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
5e25b9dd
K		 108
109 return ret;
110}
111
20346722 112/*
1da177e4
LT		 113 * Cards with following subsystem_id have a link state indication
114 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
115 * macro below identifies these cards given the subsystem_id.
116 */
d44570e4
JP		 117#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
118 (dev_type == XFRAME_I_DEVICE) ? \
119 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
120 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 121
122#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
123 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 124
d44570e4 125static inline int is_s2io_card_up(const struct s2io_nic *sp)
92b84437
SS		 126{
127 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
128}
129
1da177e4 130/* Ethtool related variables and Macros. */
6fce365d 131static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 132 "Register test\t(offline)",
133 "Eeprom test\t(offline)",
134 "Link test\t(online)",
135 "RLDRAM test\t(offline)",
136 "BIST Test\t(offline)"
137};
138
6fce365d 139static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 140 {"tmac_frms"},
141 {"tmac_data_octets"},
142 {"tmac_drop_frms"},
143 {"tmac_mcst_frms"},
144 {"tmac_bcst_frms"},
145 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 146 {"tmac_ttl_octets"},
147 {"tmac_ucst_frms"},
148 {"tmac_nucst_frms"},
1da177e4 149 {"tmac_any_err_frms"},
bd1034f0 150 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 151 {"tmac_vld_ip_octets"},
152 {"tmac_vld_ip"},
153 {"tmac_drop_ip"},
154 {"tmac_icmp"},
155 {"tmac_rst_tcp"},
156 {"tmac_tcp"},
157 {"tmac_udp"},
158 {"rmac_vld_frms"},
159 {"rmac_data_octets"},
160 {"rmac_fcs_err_frms"},
161 {"rmac_drop_frms"},
162 {"rmac_vld_mcst_frms"},
163 {"rmac_vld_bcst_frms"},
164 {"rmac_in_rng_len_err_frms"},
bd1034f0 165 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 166 {"rmac_long_frms"},
167 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 168 {"rmac_unsup_ctrl_frms"},
169 {"rmac_ttl_octets"},
170 {"rmac_accepted_ucst_frms"},
171 {"rmac_accepted_nucst_frms"},
1da177e4 172 {"rmac_discarded_frms"},
bd1034f0
AR		 173 {"rmac_drop_events"},
174 {"rmac_ttl_less_fb_octets"},
175 {"rmac_ttl_frms"},
1da177e4
LT		 176 {"rmac_usized_frms"},
177 {"rmac_osized_frms"},
178 {"rmac_frag_frms"},
179 {"rmac_jabber_frms"},
bd1034f0
AR		 180 {"rmac_ttl_64_frms"},
181 {"rmac_ttl_65_127_frms"},
182 {"rmac_ttl_128_255_frms"},
183 {"rmac_ttl_256_511_frms"},
184 {"rmac_ttl_512_1023_frms"},
185 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 186 {"rmac_ip"},
187 {"rmac_ip_octets"},
188 {"rmac_hdr_err_ip"},
189 {"rmac_drop_ip"},
190 {"rmac_icmp"},
191 {"rmac_tcp"},
192 {"rmac_udp"},
193 {"rmac_err_drp_udp"},
bd1034f0
AR		 194 {"rmac_xgmii_err_sym"},
195 {"rmac_frms_q0"},
196 {"rmac_frms_q1"},
197 {"rmac_frms_q2"},
198 {"rmac_frms_q3"},
199 {"rmac_frms_q4"},
200 {"rmac_frms_q5"},
201 {"rmac_frms_q6"},
202 {"rmac_frms_q7"},
203 {"rmac_full_q0"},
204 {"rmac_full_q1"},
205 {"rmac_full_q2"},
206 {"rmac_full_q3"},
207 {"rmac_full_q4"},
208 {"rmac_full_q5"},
209 {"rmac_full_q6"},
210 {"rmac_full_q7"},
1da177e4 211 {"rmac_pause_cnt"},
bd1034f0
AR		 212 {"rmac_xgmii_data_err_cnt"},
213 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 214 {"rmac_accepted_ip"},
215 {"rmac_err_tcp"},
bd1034f0
AR		 216 {"rd_req_cnt"},
217 {"new_rd_req_cnt"},
218 {"new_rd_req_rtry_cnt"},
219 {"rd_rtry_cnt"},
220 {"wr_rtry_rd_ack_cnt"},
221 {"wr_req_cnt"},
222 {"new_wr_req_cnt"},
223 {"new_wr_req_rtry_cnt"},
224 {"wr_rtry_cnt"},
225 {"wr_disc_cnt"},
226 {"rd_rtry_wr_ack_cnt"},
227 {"txp_wr_cnt"},
228 {"txd_rd_cnt"},
229 {"txd_wr_cnt"},
230 {"rxd_rd_cnt"},
231 {"rxd_wr_cnt"},
232 {"txf_rd_cnt"},
fa1f0cb3
SS		 233 {"rxf_wr_cnt"}
234};
235
6fce365d 236static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 237 {"rmac_ttl_1519_4095_frms"},
238 {"rmac_ttl_4096_8191_frms"},
239 {"rmac_ttl_8192_max_frms"},
240 {"rmac_ttl_gt_max_frms"},
241 {"rmac_osized_alt_frms"},
242 {"rmac_jabber_alt_frms"},
243 {"rmac_gt_max_alt_frms"},
244 {"rmac_vlan_frms"},
245 {"rmac_len_discard"},
246 {"rmac_fcs_discard"},
247 {"rmac_pf_discard"},
248 {"rmac_da_discard"},
249 {"rmac_red_discard"},
250 {"rmac_rts_discard"},
251 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 252 {"link_fault_cnt"}
253};
254
6fce365d 255static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 256 {"\n DRIVER STATISTICS"},
257 {"single_bit_ecc_errs"},
258 {"double_bit_ecc_errs"},
bd1034f0
AR		 259 {"parity_err_cnt"},
260 {"serious_err_cnt"},
261 {"soft_reset_cnt"},
262 {"fifo_full_cnt"},
8116f3cf
SS		 263 {"ring_0_full_cnt"},
264 {"ring_1_full_cnt"},
265 {"ring_2_full_cnt"},
266 {"ring_3_full_cnt"},
267 {"ring_4_full_cnt"},
268 {"ring_5_full_cnt"},
269 {"ring_6_full_cnt"},
270 {"ring_7_full_cnt"},
43b7c451
SH		 271 {"alarm_transceiver_temp_high"},
272 {"alarm_transceiver_temp_low"},
273 {"alarm_laser_bias_current_high"},
274 {"alarm_laser_bias_current_low"},
275 {"alarm_laser_output_power_high"},
276 {"alarm_laser_output_power_low"},
277 {"warn_transceiver_temp_high"},
278 {"warn_transceiver_temp_low"},
279 {"warn_laser_bias_current_high"},
280 {"warn_laser_bias_current_low"},
281 {"warn_laser_output_power_high"},
282 {"warn_laser_output_power_low"},
283 {"lro_aggregated_pkts"},
284 {"lro_flush_both_count"},
285 {"lro_out_of_sequence_pkts"},
286 {"lro_flush_due_to_max_pkts"},
287 {"lro_avg_aggr_pkts"},
288 {"mem_alloc_fail_cnt"},
289 {"pci_map_fail_cnt"},
290 {"watchdog_timer_cnt"},
291 {"mem_allocated"},
292 {"mem_freed"},
293 {"link_up_cnt"},
294 {"link_down_cnt"},
295 {"link_up_time"},
296 {"link_down_time"},
297 {"tx_tcode_buf_abort_cnt"},
298 {"tx_tcode_desc_abort_cnt"},
299 {"tx_tcode_parity_err_cnt"},
300 {"tx_tcode_link_loss_cnt"},
301 {"tx_tcode_list_proc_err_cnt"},
302 {"rx_tcode_parity_err_cnt"},
303 {"rx_tcode_abort_cnt"},
304 {"rx_tcode_parity_abort_cnt"},
305 {"rx_tcode_rda_fail_cnt"},
306 {"rx_tcode_unkn_prot_cnt"},
307 {"rx_tcode_fcs_err_cnt"},
308 {"rx_tcode_buf_size_err_cnt"},
309 {"rx_tcode_rxd_corrupt_cnt"},
310 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 311 {"tda_err_cnt"},
312 {"pfc_err_cnt"},
313 {"pcc_err_cnt"},
314 {"tti_err_cnt"},
315 {"tpa_err_cnt"},
316 {"sm_err_cnt"},
317 {"lso_err_cnt"},
318 {"mac_tmac_err_cnt"},
319 {"mac_rmac_err_cnt"},
320 {"xgxs_txgxs_err_cnt"},
321 {"xgxs_rxgxs_err_cnt"},
322 {"rc_err_cnt"},
323 {"prc_pcix_err_cnt"},
324 {"rpa_err_cnt"},
325 {"rda_err_cnt"},
326 {"rti_err_cnt"},
327 {"mc_err_cnt"}
1da177e4
LT		 328};
329
4c3616cd
AMR		 330#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
331#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
332#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3 333
d44570e4
JP		 334#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
335#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
fa1f0cb3 336
d44570e4
JP		 337#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
338#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
1da177e4 339
4c3616cd 340#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
d44570e4 341#define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
1da177e4 342
d44570e4
JP		 343#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
344 init_timer(&timer); \
345 timer.function = handle; \
346 timer.data = (unsigned long)arg; \
347 mod_timer(&timer, (jiffies + exp)) \
25fff88e 348
2fd37688
SS		 349/* copy mac addr to def_mac_addr array */
350static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
351{
352 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
353 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
354 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
355 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
356 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
357 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
358}
04025095 359
be3a6b02
K		 360/* Add the vlan */
361static void s2io_vlan_rx_register(struct net_device *dev,
04025095 362 struct vlan_group *grp)
be3a6b02 363{
2fda096d 364 int i;
4cf1653a 365 struct s2io_nic *nic = netdev_priv(dev);
2fda096d 366 unsigned long flags[MAX_TX_FIFOS];
2fda096d 367 struct config_param *config = &nic->config;
ffb5df6c 368 struct mac_info *mac_control = &nic->mac_control;
2fda096d 369
13d866a9
JP		 370 for (i = 0; i < config->tx_fifo_num; i++) {
371 struct fifo_info *fifo = &mac_control->fifos[i];
372
373 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
374 }
be3a6b02 375
be3a6b02 376 nic->vlgrp = grp;
13d866a9
JP		 377
378 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
379 struct fifo_info *fifo = &mac_control->fifos[i];
380
381 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
382 }
be3a6b02
K		 383}
384
cdb5bf02 385/* Unregister the vlan */
04025095 386static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 387{
388 int i;
4cf1653a 389 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02 390 unsigned long flags[MAX_TX_FIFOS];
cdb5bf02 391 struct config_param *config = &nic->config;
ffb5df6c 392 struct mac_info *mac_control = &nic->mac_control;
cdb5bf02 393
13d866a9
JP		 394 for (i = 0; i < config->tx_fifo_num; i++) {
395 struct fifo_info *fifo = &mac_control->fifos[i];
396
397 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
398 }
cdb5bf02
SH		 399
400 if (nic->vlgrp)
401 vlan_group_set_device(nic->vlgrp, vid, NULL);
402
13d866a9
JP		 403 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
404 struct fifo_info *fifo = &mac_control->fifos[i];
405
406 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
407 }
cdb5bf02
SH		 408}
409
20346722 410/*
1da177e4
LT		 411 * Constants to be programmed into the Xena's registers, to configure
412 * the XAUI.
413 */
414
1da177e4 415#define END_SIGN 0x0
f71e1309 416static const u64 herc_act_dtx_cfg[] = {
541ae68f 417 /* Set address */
e960fc5c 418 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 419 /* Write data */
e960fc5c 420 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 421 /* Set address */
422 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
423 /* Write data */
424 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
425 /* Set address */
e960fc5c 426 0x801205150D440000ULL, 0x801205150D4400E0ULL,
427 /* Write data */
428 0x801205150D440004ULL, 0x801205150D4400E4ULL,
429 /* Set address */
541ae68f
K		 430 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
431 /* Write data */
432 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
433 /* Done */
434 END_SIGN
435};
436
f71e1309 437static const u64 xena_dtx_cfg[] = {
c92ca04b 438 /* Set address */
1da177e4 439 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 440 /* Write data */
441 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
442 /* Set address */
443 0x8001051500000000ULL, 0x80010515000000E0ULL,
444 /* Write data */
445 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
446 /* Set address */
1da177e4 447 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 448 /* Write data */
449 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 450 END_SIGN
451};
452
20346722 453/*
1da177e4
LT		 454 * Constants for Fixing the MacAddress problem seen mostly on
455 * Alpha machines.
456 */
f71e1309 457static const u64 fix_mac[] = {
1da177e4
LT		 458 0x0060000000000000ULL, 0x0060600000000000ULL,
459 0x0040600000000000ULL, 0x0000600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0060600000000000ULL,
470 0x0020600000000000ULL, 0x0000600000000000ULL,
471 0x0040600000000000ULL, 0x0060600000000000ULL,
472 END_SIGN
473};
474
b41477f3
AR		 475MODULE_LICENSE("GPL");
476MODULE_VERSION(DRV_VERSION);
477
478
1da177e4 479/* Module Loadable parameters. */
6cfc482b 480S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 481S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 482S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 483S2IO_PARM_INT(rx_ring_mode, 1);
484S2IO_PARM_INT(use_continuous_tx_intrs, 1);
485S2IO_PARM_INT(rmac_pause_time, 0x100);
486S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
487S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
488S2IO_PARM_INT(shared_splits, 0);
489S2IO_PARM_INT(tmac_util_period, 5);
490S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 491S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 492/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
493S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 494/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 495S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 496/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 497S2IO_PARM_INT(intr_type, 2);
7d3d0439 498/* Large receive offload feature */
958de193 499static unsigned int lro_enable = 1;
43b7c451
SH		 500module_param_named(lro, lro_enable, uint, 0);
501
7d3d0439
RA		 502/* Max pkts to be aggregated by LRO at one time. If not specified,
503 * aggregation happens until we hit max IP pkt size(64K)
504 */
b41477f3 505S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 506S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 507
508S2IO_PARM_INT(napi, 1);
509S2IO_PARM_INT(ufo, 0);
926930b2 510S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 511
512static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
d44570e4 513{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
b41477f3 514static unsigned int rx_ring_sz[MAX_RX_RINGS] =
d44570e4 515{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
b41477f3 516static unsigned int rts_frm_len[MAX_RX_RINGS] =
d44570e4 517{[0 ...(MAX_RX_RINGS - 1)] = 0 };
b41477f3
AR		 518
519module_param_array(tx_fifo_len, uint, NULL, 0);
520module_param_array(rx_ring_sz, uint, NULL, 0);
521module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 522
20346722 523/*
1da177e4 524 * S2IO device table.
20346722 525 * This table lists all the devices that this driver supports.
1da177e4 526 */
a3aa1884 527static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
1da177e4
LT		 528 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
529 PCI_ANY_ID, PCI_ANY_ID},
530 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
531 PCI_ANY_ID, PCI_ANY_ID},
532 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
d44570e4
JP		 533 PCI_ANY_ID, PCI_ANY_ID},
534 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
535 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 536 {0,}
537};
538
539MODULE_DEVICE_TABLE(pci, s2io_tbl);
540
d796fdb7
LV		 541static struct pci_error_handlers s2io_err_handler = {
542 .error_detected = s2io_io_error_detected,
543 .slot_reset = s2io_io_slot_reset,
544 .resume = s2io_io_resume,
545};
546
1da177e4 547static struct pci_driver s2io_driver = {
d44570e4
JP		 548 .name = "S2IO",
549 .id_table = s2io_tbl,
550 .probe = s2io_init_nic,
551 .remove = __devexit_p(s2io_rem_nic),
552 .err_handler = &s2io_err_handler,
1da177e4
LT		 553};
554
555/* A simplifier macro used both by init and free shared_mem Fns(). */
556#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
557
3a3d5756
SH		 558/* netqueue manipulation helper functions */
559static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
560{
fd2ea0a7
DM		 561 if (!sp->config.multiq) {
562 int i;
563
3a3d5756
SH		 564 for (i = 0; i < sp->config.tx_fifo_num; i++)
565 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 566 }
fd2ea0a7 567 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 568}
569
570static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
571{
fd2ea0a7 572 if (!sp->config.multiq)
3a3d5756
SH		 573 sp->mac_control.fifos[fifo_no].queue_state =
574 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 575
576 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 577}
578
579static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
580{
fd2ea0a7
DM		 581 if (!sp->config.multiq) {
582 int i;
583
3a3d5756
SH		 584 for (i = 0; i < sp->config.tx_fifo_num; i++)
585 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 586 }
fd2ea0a7 587 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 588}
589
590static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
591{
fd2ea0a7 592 if (!sp->config.multiq)
3a3d5756
SH		 593 sp->mac_control.fifos[fifo_no].queue_state =
594 FIFO_QUEUE_START;
fd2ea0a7
DM		 595
596 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 597}
598
599static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
600{
fd2ea0a7
DM		 601 if (!sp->config.multiq) {
602 int i;
603
3a3d5756
SH		 604 for (i = 0; i < sp->config.tx_fifo_num; i++)
605 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 606 }
fd2ea0a7 607 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 608}
609
610static inline void s2io_wake_tx_queue(
611 struct fifo_info *fifo, int cnt, u8 multiq)
612{
613
3a3d5756
SH		 614 if (multiq) {
615 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
616 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 617 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 618 if (netif_queue_stopped(fifo->dev)) {
619 fifo->queue_state = FIFO_QUEUE_START;
620 netif_wake_queue(fifo->dev);
621 }
622 }
623}
624
1da177e4
LT		 625/**
626 * init_shared_mem - Allocation and Initialization of Memory
627 * @nic: Device private variable.
20346722
K		 628 * Description: The function allocates all the memory areas shared
629 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 630 * Rx descriptors and the statistics block.
631 */
632
633static int init_shared_mem(struct s2io_nic *nic)
634{
635 u32 size;
636 void *tmp_v_addr, *tmp_v_addr_next;
637 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 638 struct RxD_block *pre_rxd_blk = NULL;
372cc597 639 int i, j, blk_cnt;
1da177e4
LT		 640 int lst_size, lst_per_page;
641 struct net_device *dev = nic->dev;
8ae418cf 642 unsigned long tmp;
1ee6dd77 643 struct buffAdd *ba;
ffb5df6c
JP		 644 struct config_param *config = &nic->config;
645 struct mac_info *mac_control = &nic->mac_control;
491976b2 646 unsigned long long mem_allocated = 0;
1da177e4 647
13d866a9 648 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 649 size = 0;
650 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 651 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
652
653 size += tx_cfg->fifo_len;
1da177e4
LT		 654 }
655 if (size > MAX_AVAILABLE_TXDS) {
9e39f7c5
JP		 656 DBG_PRINT(ERR_DBG,
657 "Too many TxDs requested: %d, max supported: %d\n",
658 size, MAX_AVAILABLE_TXDS);
b41477f3 659 return -EINVAL;
1da177e4
LT		 660 }
661
2fda096d
SR		 662 size = 0;
663 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 664 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
665
666 size = tx_cfg->fifo_len;
2fda096d
SR		 667 /*
668 * Legal values are from 2 to 8192
669 */
670 if (size < 2) {
9e39f7c5
JP		 671 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
672 "Valid lengths are 2 through 8192\n",
673 i, size);
2fda096d
SR		 674 return -EINVAL;
675 }
676 }
677
1ee6dd77 678 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 679 lst_per_page = PAGE_SIZE / lst_size;
680
681 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 682 struct fifo_info *fifo = &mac_control->fifos[i];
683 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 685 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 686
687 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
688 if (!fifo->list_info) {
d44570e4 689 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
1da177e4
LT		 690 return -ENOMEM;
691 }
491976b2 692 mem_allocated += list_holder_size;
1da177e4
LT		 693 }
694 for (i = 0; i < config->tx_fifo_num; i++) {
695 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
696 lst_per_page);
13d866a9
JP		 697 struct fifo_info *fifo = &mac_control->fifos[i];
698 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
699
700 fifo->tx_curr_put_info.offset = 0;
701 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
702 fifo->tx_curr_get_info.offset = 0;
703 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
704 fifo->fifo_no = i;
705 fifo->nic = nic;
706 fifo->max_txds = MAX_SKB_FRAGS + 2;
707 fifo->dev = dev;
20346722 708
1da177e4
LT		 709 for (j = 0; j < page_num; j++) {
710 int k = 0;
711 dma_addr_t tmp_p;
712 void *tmp_v;
713 tmp_v = pci_alloc_consistent(nic->pdev,
714 PAGE_SIZE, &tmp_p);
715 if (!tmp_v) {
9e39f7c5
JP		 716 DBG_PRINT(INFO_DBG,
717 "pci_alloc_consistent failed for TxDL\n");
1da177e4
LT		 718 return -ENOMEM;
719 }
776bd20f 720 /* If we got a zero DMA address(can happen on
721 * certain platforms like PPC), reallocate.
722 * Store virtual address of page we don't want,
723 * to be freed later.
724 */
725 if (!tmp_p) {
726 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 727 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 728 "%s: Zero DMA address for TxDL. "
729 "Virtual address %p\n",
730 dev->name, tmp_v);
776bd20f 731 tmp_v = pci_alloc_consistent(nic->pdev,
d44570e4 732 PAGE_SIZE, &tmp_p);
776bd20f 733 if (!tmp_v) {
0c61ed5f 734 DBG_PRINT(INFO_DBG,
9e39f7c5 735 "pci_alloc_consistent failed for TxDL\n");
776bd20f 736 return -ENOMEM;
737 }
491976b2 738 mem_allocated += PAGE_SIZE;
776bd20f 739 }
1da177e4
LT		 740 while (k < lst_per_page) {
741 int l = (j * lst_per_page) + k;
13d866a9 742 if (l == tx_cfg->fifo_len)
20346722 743 break;
13d866a9 744 fifo->list_info[l].list_virt_addr =
d44570e4 745 tmp_v + (k * lst_size);
13d866a9 746 fifo->list_info[l].list_phy_addr =
d44570e4 747 tmp_p + (k * lst_size);
1da177e4
LT		 748 k++;
749 }
750 }
751 }
1da177e4 752
2fda096d 753 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 754 struct fifo_info *fifo = &mac_control->fifos[i];
755 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
756
757 size = tx_cfg->fifo_len;
758 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
759 if (!fifo->ufo_in_band_v)
2fda096d
SR		 760 return -ENOMEM;
761 mem_allocated += (size * sizeof(u64));
762 }
fed5eccd 763
1da177e4
LT		 764 /* Allocation and initialization of RXDs in Rings */
765 size = 0;
766 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 767 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
768 struct ring_info *ring = &mac_control->rings[i];
769
770 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
9e39f7c5
JP		 771 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
772 "multiple of RxDs per Block\n",
773 dev->name, i);
1da177e4
LT		 774 return FAILURE;
775 }
13d866a9
JP		 776 size += rx_cfg->num_rxd;
777 ring->block_count = rx_cfg->num_rxd /
d44570e4 778 (rxd_count[nic->rxd_mode] + 1);
13d866a9 779 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 780 }
da6971d8 781 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 782 size = (size * (sizeof(struct RxD1)));
da6971d8 783 else
1ee6dd77 784 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 785
786 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 787 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
788 struct ring_info *ring = &mac_control->rings[i];
789
790 ring->rx_curr_get_info.block_index = 0;
791 ring->rx_curr_get_info.offset = 0;
792 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
793 ring->rx_curr_put_info.block_index = 0;
794 ring->rx_curr_put_info.offset = 0;
795 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
796 ring->nic = nic;
797 ring->ring_no = i;
13d866a9
JP		 798
799 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 800 /* Allocating all the Rx blocks */
801 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 802 struct rx_block_info *rx_blocks;
da6971d8
AR		 803 int l;
804
13d866a9 805 rx_blocks = &ring->rx_blocks[j];
d44570e4 806 size = SIZE_OF_BLOCK; /* size is always page size */
1da177e4
LT		 807 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
808 &tmp_p_addr);
809 if (tmp_v_addr == NULL) {
810 /*
20346722
K		 811 * In case of failure, free_shared_mem()
812 * is called, which should free any
813 * memory that was alloced till the
1da177e4
LT		 814 * failure happened.
815 */
da6971d8 816 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 817 return -ENOMEM;
818 }
491976b2 819 mem_allocated += size;
1da177e4 820 memset(tmp_v_addr, 0, size);
4f870320
JP		 821
822 size = sizeof(struct rxd_info) *
823 rxd_count[nic->rxd_mode];
da6971d8
AR		 824 rx_blocks->block_virt_addr = tmp_v_addr;
825 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 826 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 827 if (!rx_blocks->rxds)
828 return -ENOMEM;
4f870320 829 mem_allocated += size;
d44570e4 830 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
da6971d8
AR		 831 rx_blocks->rxds[l].virt_addr =
832 rx_blocks->block_virt_addr +
833 (rxd_size[nic->rxd_mode] * l);
834 rx_blocks->rxds[l].dma_addr =
835 rx_blocks->block_dma_addr +
836 (rxd_size[nic->rxd_mode] * l);
837 }
1da177e4
LT		 838 }
839 /* Interlinking all Rx Blocks */
840 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 841 int next = (j + 1) % blk_cnt;
842 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
843 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
844 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
845 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 846
d44570e4 847 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
1da177e4 848 pre_rxd_blk->reserved_2_pNext_RxD_block =
d44570e4 849 (unsigned long)tmp_v_addr_next;
1da177e4 850 pre_rxd_blk->pNext_RxD_Blk_physical =
d44570e4 851 (u64)tmp_p_addr_next;
1da177e4
LT		 852 }
853 }
6d517a27 854 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 855 /*
856 * Allocation of Storages for buffer addresses in 2BUFF mode
857 * and the buffers as well.
858 */
859 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 860 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
861 struct ring_info *ring = &mac_control->rings[i];
862
863 blk_cnt = rx_cfg->num_rxd /
d44570e4 864 (rxd_count[nic->rxd_mode] + 1);
4f870320
JP		 865 size = sizeof(struct buffAdd *) * blk_cnt;
866 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 867 if (!ring->ba)
1da177e4 868 return -ENOMEM;
4f870320 869 mem_allocated += size;
da6971d8
AR		 870 for (j = 0; j < blk_cnt; j++) {
871 int k = 0;
4f870320
JP		 872
873 size = sizeof(struct buffAdd) *
874 (rxd_count[nic->rxd_mode] + 1);
875 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 876 if (!ring->ba[j])
1da177e4 877 return -ENOMEM;
4f870320 878 mem_allocated += size;
da6971d8 879 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 880 ba = &ring->ba[j][k];
4f870320
JP		 881 size = BUF0_LEN + ALIGN_SIZE;
882 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 883 if (!ba->ba_0_org)
884 return -ENOMEM;
4f870320 885 mem_allocated += size;
da6971d8
AR		 886 tmp = (unsigned long)ba->ba_0_org;
887 tmp += ALIGN_SIZE;
d44570e4
JP		 888 tmp &= ~((unsigned long)ALIGN_SIZE);
889 ba->ba_0 = (void *)tmp;
da6971d8 890
4f870320
JP		 891 size = BUF1_LEN + ALIGN_SIZE;
892 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 893 if (!ba->ba_1_org)
894 return -ENOMEM;
4f870320 895 mem_allocated += size;
d44570e4 896 tmp = (unsigned long)ba->ba_1_org;
da6971d8 897 tmp += ALIGN_SIZE;
d44570e4
JP		 898 tmp &= ~((unsigned long)ALIGN_SIZE);
899 ba->ba_1 = (void *)tmp;
da6971d8
AR		 900 k++;
901 }
1da177e4
LT		 902 }
903 }
904 }
1da177e4
LT		 905
906 /* Allocation and initialization of Statistics block */
1ee6dd77 907 size = sizeof(struct stat_block);
d44570e4
JP		 908 mac_control->stats_mem =
909 pci_alloc_consistent(nic->pdev, size,
910 &mac_control->stats_mem_phy);
1da177e4
LT		 911
912 if (!mac_control->stats_mem) {
20346722
K		 913 /*
914 * In case of failure, free_shared_mem() is called, which
915 * should free any memory that was alloced till the
1da177e4
LT		 916 * failure happened.
917 */
918 return -ENOMEM;
919 }
491976b2 920 mem_allocated += size;
1da177e4
LT		 921 mac_control->stats_mem_sz = size;
922
923 tmp_v_addr = mac_control->stats_mem;
d44570e4 924 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
1da177e4 925 memset(tmp_v_addr, 0, size);
3a22813a
BL		 926 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
927 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
491976b2 928 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 929 return SUCCESS;
930}
931
20346722
K		 932/**
933 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 934 * @nic: Device private variable.
935 * Description: This function is to free all memory locations allocated by
936 * the init_shared_mem() function and return it to the kernel.
937 */
938
939static void free_shared_mem(struct s2io_nic *nic)
940{
941 int i, j, blk_cnt, size;
942 void *tmp_v_addr;
943 dma_addr_t tmp_p_addr;
1da177e4 944 int lst_size, lst_per_page;
8910b49f 945 struct net_device *dev;
491976b2 946 int page_num = 0;
ffb5df6c
JP		 947 struct config_param *config;
948 struct mac_info *mac_control;
949 struct stat_block *stats;
950 struct swStat *swstats;
1da177e4
LT		 951
952 if (!nic)
953 return;
954
8910b49f
MG		 955 dev = nic->dev;
956
1da177e4 957 config = &nic->config;
ffb5df6c
JP		 958 mac_control = &nic->mac_control;
959 stats = mac_control->stats_info;
960 swstats = &stats->sw_stat;
1da177e4 961
d44570e4 962 lst_size = sizeof(struct TxD) * config->max_txds;
1da177e4
LT		 963 lst_per_page = PAGE_SIZE / lst_size;
964
965 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 966 struct fifo_info *fifo = &mac_control->fifos[i];
967 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
968
969 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 970 for (j = 0; j < page_num; j++) {
971 int mem_blks = (j * lst_per_page);
13d866a9
JP		 972 struct list_info_hold *fli;
973
974 if (!fifo->list_info)
6aa20a22 975 return;
13d866a9
JP		 976
977 fli = &fifo->list_info[mem_blks];
978 if (!fli->list_virt_addr)
1da177e4
LT		 979 break;
980 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 981 fli->list_virt_addr,
982 fli->list_phy_addr);
ffb5df6c 983 swstats->mem_freed += PAGE_SIZE;
1da177e4 984 }
776bd20f 985 /* If we got a zero DMA address during allocation,
986 * free the page now
987 */
988 if (mac_control->zerodma_virt_addr) {
989 pci_free_consistent(nic->pdev, PAGE_SIZE,
990 mac_control->zerodma_virt_addr,
991 (dma_addr_t)0);
6aa20a22 992 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 993 "%s: Freeing TxDL with zero DMA address. "
994 "Virtual address %p\n",
995 dev->name, mac_control->zerodma_virt_addr);
ffb5df6c 996 swstats->mem_freed += PAGE_SIZE;
776bd20f 997 }
13d866a9 998 kfree(fifo->list_info);
82c2d023 999 swstats->mem_freed += tx_cfg->fifo_len *
d44570e4 1000 sizeof(struct list_info_hold);
1da177e4
LT		 1001 }
1002
1da177e4 1003 size = SIZE_OF_BLOCK;
1da177e4 1004 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1005 struct ring_info *ring = &mac_control->rings[i];
1006
1007 blk_cnt = ring->block_count;
1da177e4 1008 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1009 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1010 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1011 if (tmp_v_addr == NULL)
1012 break;
1013 pci_free_consistent(nic->pdev, size,
1014 tmp_v_addr, tmp_p_addr);
ffb5df6c 1015 swstats->mem_freed += size;
13d866a9 1016 kfree(ring->rx_blocks[j].rxds);
ffb5df6c
JP		 1017 swstats->mem_freed += sizeof(struct rxd_info) *
1018 rxd_count[nic->rxd_mode];
1da177e4
LT		 1019 }
1020 }
1021
6d517a27 1022 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1023 /* Freeing buffer storage addresses in 2BUFF mode. */
1024 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1025 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1026 struct ring_info *ring = &mac_control->rings[i];
1027
1028 blk_cnt = rx_cfg->num_rxd /
1029 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1030 for (j = 0; j < blk_cnt; j++) {
1031 int k = 0;
13d866a9 1032 if (!ring->ba[j])
da6971d8
AR		 1033 continue;
1034 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1035 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1036 kfree(ba->ba_0_org);
ffb5df6c
JP		 1037 swstats->mem_freed +=
1038 BUF0_LEN + ALIGN_SIZE;
da6971d8 1039 kfree(ba->ba_1_org);
ffb5df6c
JP		 1040 swstats->mem_freed +=
1041 BUF1_LEN + ALIGN_SIZE;
da6971d8
AR		 1042 k++;
1043 }
13d866a9 1044 kfree(ring->ba[j]);
ffb5df6c
JP		 1045 swstats->mem_freed += sizeof(struct buffAdd) *
1046 (rxd_count[nic->rxd_mode] + 1);
1da177e4 1047 }
13d866a9 1048 kfree(ring->ba);
ffb5df6c
JP		 1049 swstats->mem_freed += sizeof(struct buffAdd *) *
1050 blk_cnt;
1da177e4 1051 }
1da177e4 1052 }
1da177e4 1053
2fda096d 1054 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1055 struct fifo_info *fifo = &mac_control->fifos[i];
1056 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1057
1058 if (fifo->ufo_in_band_v) {
ffb5df6c
JP		 1059 swstats->mem_freed += tx_cfg->fifo_len *
1060 sizeof(u64);
13d866a9 1061 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1062 }
1063 }
1064
1da177e4 1065 if (mac_control->stats_mem) {
ffb5df6c 1066 swstats->mem_freed += mac_control->stats_mem_sz;
1da177e4
LT		 1067 pci_free_consistent(nic->pdev,
1068 mac_control->stats_mem_sz,
1069 mac_control->stats_mem,
1070 mac_control->stats_mem_phy);
491976b2 1071 }
1da177e4
LT		 1072}
1073
541ae68f
K		 1074/**
1075 * s2io_verify_pci_mode -
1076 */
1077
1ee6dd77 1078static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1079{
1ee6dd77 1080 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1081 register u64 val64 = 0;
1082 int mode;
1083
1084 val64 = readq(&bar0->pci_mode);
1085 mode = (u8)GET_PCI_MODE(val64);
1086
d44570e4 1087 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1088 return -1; /* Unknown PCI mode */
1089 return mode;
1090}
1091
c92ca04b
AR		 1092#define NEC_VENID 0x1033
1093#define NEC_DEVID 0x0125
1094static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1095{
1096 struct pci_dev *tdev = NULL;
26d36b64
AC		 1097 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1098 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1099 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1100 pci_dev_put(tdev);
c92ca04b 1101 return 1;
7ad62dbc 1102 }
c92ca04b
AR		 1103 }
1104 }
1105 return 0;
1106}
541ae68f 1107
7b32a312 1108static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 1109/**
1110 * s2io_print_pci_mode -
1111 */
1ee6dd77 1112static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1113{
1ee6dd77 1114 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1115 register u64 val64 = 0;
1116 int mode;
1117 struct config_param *config = &nic->config;
9e39f7c5 1118 const char *pcimode;
541ae68f
K		 1119
1120 val64 = readq(&bar0->pci_mode);
1121 mode = (u8)GET_PCI_MODE(val64);
1122
d44570e4 1123 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1124 return -1; /* Unknown PCI mode */
1125
c92ca04b
AR		 1126 config->bus_speed = bus_speed[mode];
1127
1128 if (s2io_on_nec_bridge(nic->pdev)) {
1129 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
d44570e4 1130 nic->dev->name);
c92ca04b
AR		 1131 return mode;
1132 }
1133
d44570e4
JP		 1134 switch (mode) {
1135 case PCI_MODE_PCI_33:
9e39f7c5 1136 pcimode = "33MHz PCI bus";
d44570e4
JP		 1137 break;
1138 case PCI_MODE_PCI_66:
9e39f7c5 1139 pcimode = "66MHz PCI bus";
d44570e4
JP		 1140 break;
1141 case PCI_MODE_PCIX_M1_66:
9e39f7c5 1142 pcimode = "66MHz PCIX(M1) bus";
d44570e4
JP		 1143 break;
1144 case PCI_MODE_PCIX_M1_100:
9e39f7c5 1145 pcimode = "100MHz PCIX(M1) bus";
d44570e4
JP		 1146 break;
1147 case PCI_MODE_PCIX_M1_133:
9e39f7c5 1148 pcimode = "133MHz PCIX(M1) bus";
d44570e4
JP		 1149 break;
1150 case PCI_MODE_PCIX_M2_66:
9e39f7c5 1151 pcimode = "133MHz PCIX(M2) bus";
d44570e4
JP		 1152 break;
1153 case PCI_MODE_PCIX_M2_100:
9e39f7c5 1154 pcimode = "200MHz PCIX(M2) bus";
d44570e4
JP		 1155 break;
1156 case PCI_MODE_PCIX_M2_133:
9e39f7c5 1157 pcimode = "266MHz PCIX(M2) bus";
d44570e4
JP		 1158 break;
1159 default:
9e39f7c5
JP		 1160 pcimode = "unsupported bus!";
1161 mode = -1;
541ae68f
K		 1162 }
1163
9e39f7c5
JP		 1164 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1165 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1166
541ae68f
K		 1167 return mode;
1168}
1169
b7c5678f
RV		 1170/**
1171 * init_tti - Initialization transmit traffic interrupt scheme
1172 * @nic: device private variable
1173 * @link: link status (UP/DOWN) used to enable/disable continuous
1174 * transmit interrupts
1175 * Description: The function configures transmit traffic interrupts
1176 * Return Value: SUCCESS on success and
1177 * '-1' on failure
1178 */
1179
0d66afe7 1180static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1181{
1182 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1183 register u64 val64 = 0;
1184 int i;
ffb5df6c 1185 struct config_param *config = &nic->config;
b7c5678f
RV		 1186
1187 for (i = 0; i < config->tx_fifo_num; i++) {
1188 /*
1189 * TTI Initialization. Default Tx timer gets us about
1190 * 250 interrupts per sec. Continuous interrupts are enabled
1191 * by default.
1192 */
1193 if (nic->device_type == XFRAME_II_DEVICE) {
1194 int count = (nic->config.bus_speed * 125)/2;
1195 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1196 } else
1197 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1198
1199 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
d44570e4
JP		 1200 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1201 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1202 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1203 if (i == 0)
1204 if (use_continuous_tx_intrs && (link == LINK_UP))
1205 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1206 writeq(val64, &bar0->tti_data1_mem);
1207
ac731ab6
SH		 1208 if (nic->config.intr_type == MSI_X) {
1209 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1210 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1211 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1212 TTI_DATA2_MEM_TX_UFC_D(0x300);
1213 } else {
1214 if ((nic->config.tx_steering_type ==
d44570e4
JP		 1215 TX_DEFAULT_STEERING) &&
1216 (config->tx_fifo_num > 1) &&
1217 (i >= nic->udp_fifo_idx) &&
1218 (i < (nic->udp_fifo_idx +
1219 nic->total_udp_fifos)))
ac731ab6
SH		 1220 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1221 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1222 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1223 TTI_DATA2_MEM_TX_UFC_D(0x120);
1224 else
1225 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1226 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1227 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1228 TTI_DATA2_MEM_TX_UFC_D(0x80);
1229 }
b7c5678f
RV		 1230
1231 writeq(val64, &bar0->tti_data2_mem);
1232
d44570e4
JP		 1233 val64 = TTI_CMD_MEM_WE |
1234 TTI_CMD_MEM_STROBE_NEW_CMD |
1235 TTI_CMD_MEM_OFFSET(i);
b7c5678f
RV		 1236 writeq(val64, &bar0->tti_command_mem);
1237
1238 if (wait_for_cmd_complete(&bar0->tti_command_mem,
d44570e4
JP		 1239 TTI_CMD_MEM_STROBE_NEW_CMD,
1240 S2IO_BIT_RESET) != SUCCESS)
b7c5678f
RV		 1241 return FAILURE;
1242 }
1243
1244 return SUCCESS;
1245}
1246
20346722
K		 1247/**
1248 * init_nic - Initialization of hardware
b7c5678f 1249 * @nic: device private variable
20346722
K		 1250 * Description: The function sequentially configures every block
1251 * of the H/W from their reset values.
1252 * Return Value: SUCCESS on success and
1da177e4
LT		 1253 * '-1' on failure (endian settings incorrect).
1254 */
1255
1256static int init_nic(struct s2io_nic *nic)
1257{
1ee6dd77 1258 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1259 struct net_device *dev = nic->dev;
1260 register u64 val64 = 0;
1261 void __iomem *add;
1262 u32 time;
1263 int i, j;
c92ca04b 1264 int dtx_cnt = 0;
1da177e4 1265 unsigned long long mem_share;
20346722 1266 int mem_size;
ffb5df6c
JP		 1267 struct config_param *config = &nic->config;
1268 struct mac_info *mac_control = &nic->mac_control;
1da177e4 1269
5e25b9dd 1270 /* to set the swapper controle on the card */
d44570e4
JP		 1271 if (s2io_set_swapper(nic)) {
1272 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
9f74ffde 1273 return -EIO;
1da177e4
LT		 1274 }
1275
541ae68f
K		 1276 /*
1277 * Herc requires EOI to be removed from reset before XGXS, so..
1278 */
1279 if (nic->device_type & XFRAME_II_DEVICE) {
1280 val64 = 0xA500000000ULL;
1281 writeq(val64, &bar0->sw_reset);
1282 msleep(500);
1283 val64 = readq(&bar0->sw_reset);
1284 }
1285
1da177e4
LT		 1286 /* Remove XGXS from reset state */
1287 val64 = 0;
1288 writeq(val64, &bar0->sw_reset);
1da177e4 1289 msleep(500);
20346722 1290 val64 = readq(&bar0->sw_reset);
1da177e4 1291
7962024e
SH		 1292 /* Ensure that it's safe to access registers by checking
1293 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1294 */
1295 if (nic->device_type == XFRAME_II_DEVICE) {
1296 for (i = 0; i < 50; i++) {
1297 val64 = readq(&bar0->adapter_status);
1298 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1299 break;
1300 msleep(10);
1301 }
1302 if (i == 50)
1303 return -ENODEV;
1304 }
1305
1da177e4
LT		 1306 /* Enable Receiving broadcasts */
1307 add = &bar0->mac_cfg;
1308 val64 = readq(&bar0->mac_cfg);
1309 val64 |= MAC_RMAC_BCAST_ENABLE;
1310 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 1311 writel((u32)val64, add);
1da177e4
LT		 1312 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1313 writel((u32) (val64 >> 32), (add + 4));
1314
1315 /* Read registers in all blocks */
1316 val64 = readq(&bar0->mac_int_mask);
1317 val64 = readq(&bar0->mc_int_mask);
1318 val64 = readq(&bar0->xgxs_int_mask);
1319
1320 /* Set MTU */
1321 val64 = dev->mtu;
1322 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1323
541ae68f
K		 1324 if (nic->device_type & XFRAME_II_DEVICE) {
1325 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1326 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1327 &bar0->dtx_control, UF);
541ae68f
K		 1328 if (dtx_cnt & 0x1)
1329 msleep(1); /* Necessary!! */
1da177e4
LT		 1330 dtx_cnt++;
1331 }
541ae68f 1332 } else {
c92ca04b
AR		 1333 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1334 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1335 &bar0->dtx_control, UF);
1336 val64 = readq(&bar0->dtx_control);
1337 dtx_cnt++;
1da177e4
LT		 1338 }
1339 }
1340
1341 /* Tx DMA Initialization */
1342 val64 = 0;
1343 writeq(val64, &bar0->tx_fifo_partition_0);
1344 writeq(val64, &bar0->tx_fifo_partition_1);
1345 writeq(val64, &bar0->tx_fifo_partition_2);
1346 writeq(val64, &bar0->tx_fifo_partition_3);
1347
1da177e4 1348 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1349 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1350
1351 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1352 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1353
1354 if (i == (config->tx_fifo_num - 1)) {
1355 if (i % 2 == 0)
1356 i++;
1357 }
1358
1359 switch (i) {
1360 case 1:
1361 writeq(val64, &bar0->tx_fifo_partition_0);
1362 val64 = 0;
b7c5678f 1363 j = 0;
1da177e4
LT		 1364 break;
1365 case 3:
1366 writeq(val64, &bar0->tx_fifo_partition_1);
1367 val64 = 0;
b7c5678f 1368 j = 0;
1da177e4
LT		 1369 break;
1370 case 5:
1371 writeq(val64, &bar0->tx_fifo_partition_2);
1372 val64 = 0;
b7c5678f 1373 j = 0;
1da177e4
LT		 1374 break;
1375 case 7:
1376 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1377 val64 = 0;
1378 j = 0;
1379 break;
1380 default:
1381 j++;
1da177e4
LT		 1382 break;
1383 }
1384 }
1385
5e25b9dd
K		 1386 /*
1387 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1388 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1389 */
d44570e4 1390 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
5e25b9dd
K		 1391 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1392
1da177e4
LT		 1393 val64 = readq(&bar0->tx_fifo_partition_0);
1394 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
d44570e4 1395 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1da177e4 1396
20346722
K		 1397 /*
1398 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1399 * integrity checking.
1400 */
1401 val64 = readq(&bar0->tx_pa_cfg);
d44570e4
JP		 1402 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1403 TX_PA_CFG_IGNORE_SNAP_OUI |
1404 TX_PA_CFG_IGNORE_LLC_CTRL |
1405 TX_PA_CFG_IGNORE_L2_ERR;
1da177e4
LT		 1406 writeq(val64, &bar0->tx_pa_cfg);
1407
1408 /* Rx DMA intialization. */
1409 val64 = 0;
1410 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1411 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1412
1413 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1414 }
1415 writeq(val64, &bar0->rx_queue_priority);
1416
20346722
K		 1417 /*
1418 * Allocating equal share of memory to all the
1da177e4
LT		 1419 * configured Rings.
1420 */
1421 val64 = 0;
541ae68f
K		 1422 if (nic->device_type & XFRAME_II_DEVICE)
1423 mem_size = 32;
1424 else
1425 mem_size = 64;
1426
1da177e4
LT		 1427 for (i = 0; i < config->rx_ring_num; i++) {
1428 switch (i) {
1429 case 0:
20346722
K		 1430 mem_share = (mem_size / config->rx_ring_num +
1431 mem_size % config->rx_ring_num);
1da177e4
LT		 1432 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1433 continue;
1434 case 1:
20346722 1435 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1436 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1437 continue;
1438 case 2:
20346722 1439 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1440 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1441 continue;
1442 case 3:
20346722 1443 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1444 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1445 continue;
1446 case 4:
20346722 1447 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1448 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1449 continue;
1450 case 5:
20346722 1451 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1452 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1453 continue;
1454 case 6:
20346722 1455 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1456 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1457 continue;
1458 case 7:
20346722 1459 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1460 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1461 continue;
1462 }
1463 }
1464 writeq(val64, &bar0->rx_queue_cfg);
1465
20346722 1466 /*
5e25b9dd 1467 * Filling Tx round robin registers
b7c5678f 1468 * as per the number of FIFOs for equal scheduling priority
1da177e4 1469 */
5e25b9dd
K		 1470 switch (config->tx_fifo_num) {
1471 case 1:
b7c5678f 1472 val64 = 0x0;
5e25b9dd
K		 1473 writeq(val64, &bar0->tx_w_round_robin_0);
1474 writeq(val64, &bar0->tx_w_round_robin_1);
1475 writeq(val64, &bar0->tx_w_round_robin_2);
1476 writeq(val64, &bar0->tx_w_round_robin_3);
1477 writeq(val64, &bar0->tx_w_round_robin_4);
1478 break;
1479 case 2:
b7c5678f 1480 val64 = 0x0001000100010001ULL;
5e25b9dd 1481 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1482 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1483 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1484 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1485 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1486 writeq(val64, &bar0->tx_w_round_robin_4);
1487 break;
1488 case 3:
b7c5678f 1489 val64 = 0x0001020001020001ULL;
5e25b9dd 1490 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1491 val64 = 0x0200010200010200ULL;
5e25b9dd 1492 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1493 val64 = 0x0102000102000102ULL;
5e25b9dd 1494 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1495 val64 = 0x0001020001020001ULL;
5e25b9dd 1496 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1497 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1498 writeq(val64, &bar0->tx_w_round_robin_4);
1499 break;
1500 case 4:
b7c5678f 1501 val64 = 0x0001020300010203ULL;
5e25b9dd 1502 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1503 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1504 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1506 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1507 writeq(val64, &bar0->tx_w_round_robin_4);
1508 break;
1509 case 5:
b7c5678f 1510 val64 = 0x0001020304000102ULL;
5e25b9dd 1511 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1512 val64 = 0x0304000102030400ULL;
5e25b9dd 1513 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1514 val64 = 0x0102030400010203ULL;
5e25b9dd 1515 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1516 val64 = 0x0400010203040001ULL;
5e25b9dd 1517 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1518 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1519 writeq(val64, &bar0->tx_w_round_robin_4);
1520 break;
1521 case 6:
b7c5678f 1522 val64 = 0x0001020304050001ULL;
5e25b9dd 1523 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1524 val64 = 0x0203040500010203ULL;
5e25b9dd 1525 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1526 val64 = 0x0405000102030405ULL;
5e25b9dd 1527 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1528 val64 = 0x0001020304050001ULL;
5e25b9dd 1529 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1530 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1531 writeq(val64, &bar0->tx_w_round_robin_4);
1532 break;
1533 case 7:
b7c5678f 1534 val64 = 0x0001020304050600ULL;
5e25b9dd 1535 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1536 val64 = 0x0102030405060001ULL;
5e25b9dd 1537 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1538 val64 = 0x0203040506000102ULL;
5e25b9dd 1539 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1540 val64 = 0x0304050600010203ULL;
5e25b9dd 1541 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1542 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1543 writeq(val64, &bar0->tx_w_round_robin_4);
1544 break;
1545 case 8:
b7c5678f 1546 val64 = 0x0001020304050607ULL;
5e25b9dd 1547 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1548 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1549 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1551 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1552 writeq(val64, &bar0->tx_w_round_robin_4);
1553 break;
1554 }
1555
b41477f3 1556 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1557 val64 = readq(&bar0->tx_fifo_partition_0);
1558 val64 |= (TX_FIFO_PARTITION_EN);
1559 writeq(val64, &bar0->tx_fifo_partition_0);
1560
5e25b9dd 1561 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1562 * number of Rings and steering based on QoS with
1563 * equal priority.
1564 */
5e25b9dd
K		 1565 switch (config->rx_ring_num) {
1566 case 1:
0425b46a
SH		 1567 val64 = 0x0;
1568 writeq(val64, &bar0->rx_w_round_robin_0);
1569 writeq(val64, &bar0->rx_w_round_robin_1);
1570 writeq(val64, &bar0->rx_w_round_robin_2);
1571 writeq(val64, &bar0->rx_w_round_robin_3);
1572 writeq(val64, &bar0->rx_w_round_robin_4);
1573
5e25b9dd
K		 1574 val64 = 0x8080808080808080ULL;
1575 writeq(val64, &bar0->rts_qos_steering);
1576 break;
1577 case 2:
0425b46a 1578 val64 = 0x0001000100010001ULL;
5e25b9dd 1579 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1580 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1581 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1582 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1583 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1584 writeq(val64, &bar0->rx_w_round_robin_4);
1585
1586 val64 = 0x8080808040404040ULL;
1587 writeq(val64, &bar0->rts_qos_steering);
1588 break;
1589 case 3:
0425b46a 1590 val64 = 0x0001020001020001ULL;
5e25b9dd 1591 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1592 val64 = 0x0200010200010200ULL;
5e25b9dd 1593 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1594 val64 = 0x0102000102000102ULL;
5e25b9dd 1595 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1596 val64 = 0x0001020001020001ULL;
5e25b9dd 1597 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1598 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1599 writeq(val64, &bar0->rx_w_round_robin_4);
1600
1601 val64 = 0x8080804040402020ULL;
1602 writeq(val64, &bar0->rts_qos_steering);
1603 break;
1604 case 4:
0425b46a 1605 val64 = 0x0001020300010203ULL;
5e25b9dd 1606 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1607 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1608 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1609 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1610 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1611 writeq(val64, &bar0->rx_w_round_robin_4);
1612
1613 val64 = 0x8080404020201010ULL;
1614 writeq(val64, &bar0->rts_qos_steering);
1615 break;
1616 case 5:
0425b46a 1617 val64 = 0x0001020304000102ULL;
5e25b9dd 1618 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1619 val64 = 0x0304000102030400ULL;
5e25b9dd 1620 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1621 val64 = 0x0102030400010203ULL;
5e25b9dd 1622 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1623 val64 = 0x0400010203040001ULL;
5e25b9dd 1624 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1625 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1626 writeq(val64, &bar0->rx_w_round_robin_4);
1627
1628 val64 = 0x8080404020201008ULL;
1629 writeq(val64, &bar0->rts_qos_steering);
1630 break;
1631 case 6:
0425b46a 1632 val64 = 0x0001020304050001ULL;
5e25b9dd 1633 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1634 val64 = 0x0203040500010203ULL;
5e25b9dd 1635 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1636 val64 = 0x0405000102030405ULL;
5e25b9dd 1637 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1638 val64 = 0x0001020304050001ULL;
5e25b9dd 1639 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1640 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1641 writeq(val64, &bar0->rx_w_round_robin_4);
1642
1643 val64 = 0x8080404020100804ULL;
1644 writeq(val64, &bar0->rts_qos_steering);
1645 break;
1646 case 7:
0425b46a 1647 val64 = 0x0001020304050600ULL;
5e25b9dd 1648 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1649 val64 = 0x0102030405060001ULL;
5e25b9dd 1650 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1651 val64 = 0x0203040506000102ULL;
5e25b9dd 1652 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1653 val64 = 0x0304050600010203ULL;
5e25b9dd 1654 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1655 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1656 writeq(val64, &bar0->rx_w_round_robin_4);
1657
1658 val64 = 0x8080402010080402ULL;
1659 writeq(val64, &bar0->rts_qos_steering);
1660 break;
1661 case 8:
0425b46a 1662 val64 = 0x0001020304050607ULL;
5e25b9dd 1663 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1664 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1665 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1666 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1667 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1668 writeq(val64, &bar0->rx_w_round_robin_4);
1669
1670 val64 = 0x8040201008040201ULL;
1671 writeq(val64, &bar0->rts_qos_steering);
1672 break;
1673 }
1da177e4
LT		 1674
1675 /* UDP Fix */
1676 val64 = 0;
20346722 1677 for (i = 0; i < 8; i++)
1da177e4
LT		 1678 writeq(val64, &bar0->rts_frm_len_n[i]);
1679
5e25b9dd
K		 1680 /* Set the default rts frame length for the rings configured */
1681 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1682 for (i = 0 ; i < config->rx_ring_num ; i++)
1683 writeq(val64, &bar0->rts_frm_len_n[i]);
1684
1685 /* Set the frame length for the configured rings
1686 * desired by the user
1687 */
1688 for (i = 0; i < config->rx_ring_num; i++) {
1689 /* If rts_frm_len[i] == 0 then it is assumed that user not
1690 * specified frame length steering.
1691 * If the user provides the frame length then program
1692 * the rts_frm_len register for those values or else
1693 * leave it as it is.
1694 */
1695 if (rts_frm_len[i] != 0) {
1696 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
d44570e4 1697 &bar0->rts_frm_len_n[i]);
5e25b9dd
K		 1698 }
1699 }
8a4bdbaa 1700
9fc93a41
SS		 1701 /* Disable differentiated services steering logic */
1702 for (i = 0; i < 64; i++) {
1703 if (rts_ds_steer(nic, i, 0) == FAILURE) {
9e39f7c5
JP		 1704 DBG_PRINT(ERR_DBG,
1705 "%s: rts_ds_steer failed on codepoint %d\n",
1706 dev->name, i);
9f74ffde 1707 return -ENODEV;
9fc93a41
SS		 1708 }
1709 }
1710
20346722 1711 /* Program statistics memory */
1da177e4 1712 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1713
541ae68f
K		 1714 if (nic->device_type == XFRAME_II_DEVICE) {
1715 val64 = STAT_BC(0x320);
1716 writeq(val64, &bar0->stat_byte_cnt);
1717 }
1718
20346722 1719 /*
1da177e4
LT		 1720 * Initializing the sampling rate for the device to calculate the
1721 * bandwidth utilization.
1722 */
1723 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
d44570e4 1724 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1da177e4
LT		 1725 writeq(val64, &bar0->mac_link_util);
1726
20346722
K		 1727 /*
1728 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1729 * Scheme.
1730 */
1da177e4 1731
b7c5678f
RV		 1732 /* Initialize TTI */
1733 if (SUCCESS != init_tti(nic, nic->last_link_state))
1734 return -ENODEV;
1da177e4 1735
8a4bdbaa
SS		 1736 /* RTI Initialization */
1737 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1738 /*
8a4bdbaa
SS		 1739 * Programmed to generate Apprx 500 Intrs per
1740 * second
1741 */
1742 int count = (nic->config.bus_speed * 125)/4;
1743 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1744 } else
1745 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1746 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
d44570e4
JP		 1747 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1748 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1749 RTI_DATA1_MEM_RX_TIMER_AC_EN;
8a4bdbaa
SS		 1750
1751 writeq(val64, &bar0->rti_data1_mem);
1752
1753 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1754 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1755 if (nic->config.intr_type == MSI_X)
d44570e4
JP		 1756 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1757 RTI_DATA2_MEM_RX_UFC_D(0x40));
8a4bdbaa 1758 else
d44570e4
JP		 1759 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1760 RTI_DATA2_MEM_RX_UFC_D(0x80));
8a4bdbaa 1761 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1762
8a4bdbaa 1763 for (i = 0; i < config->rx_ring_num; i++) {
d44570e4
JP		 1764 val64 = RTI_CMD_MEM_WE |
1765 RTI_CMD_MEM_STROBE_NEW_CMD |
1766 RTI_CMD_MEM_OFFSET(i);
8a4bdbaa 1767 writeq(val64, &bar0->rti_command_mem);
1da177e4 1768
8a4bdbaa
SS		 1769 /*
1770 * Once the operation completes, the Strobe bit of the
1771 * command register will be reset. We poll for this
1772 * particular condition. We wait for a maximum of 500ms
1773 * for the operation to complete, if it's not complete
1774 * by then we return error.
1775 */
1776 time = 0;
f957bcf0 1777 while (true) {
8a4bdbaa
SS		 1778 val64 = readq(&bar0->rti_command_mem);
1779 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1780 break;
b6e3f982 1781
8a4bdbaa 1782 if (time > 10) {
9e39f7c5 1783 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
8a4bdbaa 1784 dev->name);
9f74ffde 1785 return -ENODEV;
b6e3f982 1786 }
8a4bdbaa
SS		 1787 time++;
1788 msleep(50);
1da177e4 1789 }
1da177e4
LT		 1790 }
1791
20346722
K		 1792 /*
1793 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1794 * the 8 Queues on Rx side.
1795 */
1796 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1798
1799 /* Disable RMAC PAD STRIPPING */
509a2671 1800 add = &bar0->mac_cfg;
1da177e4
LT		 1801 val64 = readq(&bar0->mac_cfg);
1802 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1803 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1804 writel((u32) (val64), add);
1805 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806 writel((u32) (val64 >> 32), (add + 4));
1807 val64 = readq(&bar0->mac_cfg);
1808
7d3d0439
RA		 1809 /* Enable FCS stripping by adapter */
1810 add = &bar0->mac_cfg;
1811 val64 = readq(&bar0->mac_cfg);
1812 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1813 if (nic->device_type == XFRAME_II_DEVICE)
1814 writeq(val64, &bar0->mac_cfg);
1815 else {
1816 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817 writel((u32) (val64), add);
1818 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1819 writel((u32) (val64 >> 32), (add + 4));
1820 }
1821
20346722
K		 1822 /*
1823 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1824 * generated by xena.
1825 */
1826 val64 = readq(&bar0->rmac_pause_cfg);
1827 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1828 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1829 writeq(val64, &bar0->rmac_pause_cfg);
1830
20346722 1831 /*
1da177e4
LT		 1832 * Set the Threshold Limit for Generating the pause frame
1833 * If the amount of data in any Queue exceeds ratio of
1834 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1835 * pause frame is generated
1836 */
1837 val64 = 0;
1838 for (i = 0; i < 4; i++) {
d44570e4
JP		 1839 val64 |= (((u64)0xFF00 |
1840 nic->mac_control.mc_pause_threshold_q0q3)
1841 << (i * 2 * 8));
1da177e4
LT		 1842 }
1843 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1844
1845 val64 = 0;
1846 for (i = 0; i < 4; i++) {
d44570e4
JP		 1847 val64 |= (((u64)0xFF00 |
1848 nic->mac_control.mc_pause_threshold_q4q7)
1849 << (i * 2 * 8));
1da177e4
LT		 1850 }
1851 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1852
20346722
K		 1853 /*
1854 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1855 * exceeded the limit pointed by shared_splits
1856 */
1857 val64 = readq(&bar0->pic_control);
1858 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1859 writeq(val64, &bar0->pic_control);
1860
863c11a9
AR		 1861 if (nic->config.bus_speed == 266) {
1862 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1863 writeq(0x0, &bar0->read_retry_delay);
1864 writeq(0x0, &bar0->write_retry_delay);
1865 }
1866
541ae68f
K		 1867 /*
1868 * Programming the Herc to split every write transaction
1869 * that does not start on an ADB to reduce disconnects.
1870 */
1871 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1872 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1873 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1874 writeq(val64, &bar0->misc_control);
1875 val64 = readq(&bar0->pic_control2);
b7b5a128 1876 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1877 writeq(val64, &bar0->pic_control2);
541ae68f 1878 }
c92ca04b
AR		 1879 if (strstr(nic->product_name, "CX4")) {
1880 val64 = TMAC_AVG_IPG(0x17);
1881 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1882 }
1883
1da177e4
LT		 1884 return SUCCESS;
1885}
a371a07d
K		 1886#define LINK_UP_DOWN_INTERRUPT 1
1887#define MAC_RMAC_ERR_TIMER 2
1888
1ee6dd77 1889static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d
K		 1890{
1891 if (nic->device_type == XFRAME_II_DEVICE)
1892 return LINK_UP_DOWN_INTERRUPT;
1893 else
1894 return MAC_RMAC_ERR_TIMER;
1895}
8116f3cf 1896
9caab458
SS		 1897/**
1898 * do_s2io_write_bits - update alarm bits in alarm register
1899 * @value: alarm bits
1900 * @flag: interrupt status
1901 * @addr: address value
1902 * Description: update alarm bits in alarm register
1903 * Return Value:
1904 * NONE.
1905 */
1906static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1907{
1908 u64 temp64;
1909
1910 temp64 = readq(addr);
1911
d44570e4
JP		 1912 if (flag == ENABLE_INTRS)
1913 temp64 &= ~((u64)value);
9caab458 1914 else
d44570e4 1915 temp64 |= ((u64)value);
9caab458
SS		 1916 writeq(temp64, addr);
1917}
1da177e4 1918
43b7c451 1919static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1920{
1921 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1922 register u64 gen_int_mask = 0;
01e16faa 1923 u64 interruptible;
9caab458 1924
01e16faa 1925 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458 1926 if (mask & TX_DMA_INTR) {
9caab458
SS		 1927 gen_int_mask |= TXDMA_INT_M;
1928
1929 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
d44570e4
JP		 1930 TXDMA_PCC_INT | TXDMA_TTI_INT |
1931 TXDMA_LSO_INT | TXDMA_TPA_INT |
1932 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
9caab458
SS		 1933
1934 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
d44570e4
JP		 1935 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1936 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1937 &bar0->pfc_err_mask);
9caab458
SS		 1938
1939 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
d44570e4
JP		 1940 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1941 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
9caab458
SS		 1942
1943 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
d44570e4
JP		 1944 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1945 PCC_N_SERR | PCC_6_COF_OV_ERR |
1946 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1947 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1948 PCC_TXB_ECC_SG_ERR,
1949 flag, &bar0->pcc_err_mask);
9caab458
SS		 1950
1951 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
d44570e4 1952 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
9caab458
SS		 1953
1954 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
d44570e4
JP		 1955 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1956 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1957 flag, &bar0->lso_err_mask);
9caab458
SS		 1958
1959 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
d44570e4 1960 flag, &bar0->tpa_err_mask);
9caab458
SS		 1961
1962 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
9caab458
SS		 1963 }
1964
1965 if (mask & TX_MAC_INTR) {
1966 gen_int_mask |= TXMAC_INT_M;
1967 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
d44570e4 1968 &bar0->mac_int_mask);
9caab458 1969 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
d44570e4
JP		 1970 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1971 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1972 flag, &bar0->mac_tmac_err_mask);
9caab458
SS		 1973 }
1974
1975 if (mask & TX_XGXS_INTR) {
1976 gen_int_mask |= TXXGXS_INT_M;
1977 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
d44570e4 1978 &bar0->xgxs_int_mask);
9caab458 1979 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
d44570e4
JP		 1980 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1981 flag, &bar0->xgxs_txgxs_err_mask);
9caab458
SS		 1982 }
1983
1984 if (mask & RX_DMA_INTR) {
1985 gen_int_mask |= RXDMA_INT_M;
1986 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
d44570e4
JP		 1987 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1988 flag, &bar0->rxdma_int_mask);
9caab458 1989 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
d44570e4
JP		 1990 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1991 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1992 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
9caab458 1993 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
d44570e4
JP		 1994 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1995 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1996 &bar0->prc_pcix_err_mask);
9caab458 1997 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
d44570e4
JP		 1998 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1999 &bar0->rpa_err_mask);
9caab458 2000 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
d44570e4
JP		 2001 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2002 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2003 RDA_FRM_ECC_SG_ERR |
2004 RDA_MISC_ERR|RDA_PCIX_ERR,
2005 flag, &bar0->rda_err_mask);
9caab458 2006 do_s2io_write_bits(RTI_SM_ERR_ALARM |
d44570e4
JP		 2007 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2008 flag, &bar0->rti_err_mask);
9caab458
SS		 2009 }
2010
2011 if (mask & RX_MAC_INTR) {
2012 gen_int_mask |= RXMAC_INT_M;
2013 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
d44570e4
JP		 2014 &bar0->mac_int_mask);
2015 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2016 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2017 RMAC_DOUBLE_ECC_ERR);
01e16faa
SH		 2018 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2019 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2020 do_s2io_write_bits(interruptible,
d44570e4 2021 flag, &bar0->mac_rmac_err_mask);
9caab458
SS		 2022 }
2023
d44570e4 2024 if (mask & RX_XGXS_INTR) {
9caab458
SS		 2025 gen_int_mask |= RXXGXS_INT_M;
2026 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
d44570e4 2027 &bar0->xgxs_int_mask);
9caab458 2028 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
d44570e4 2029 &bar0->xgxs_rxgxs_err_mask);
9caab458
SS		 2030 }
2031
2032 if (mask & MC_INTR) {
2033 gen_int_mask |= MC_INT_M;
d44570e4
JP		 2034 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2035 flag, &bar0->mc_int_mask);
9caab458 2036 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
d44570e4
JP		 2037 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2038 &bar0->mc_err_mask);
9caab458
SS		 2039 }
2040 nic->general_int_mask = gen_int_mask;
2041
2042 /* Remove this line when alarm interrupts are enabled */
2043 nic->general_int_mask = 0;
2044}
d44570e4 2045
20346722
K		 2046/**
2047 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2048 * @nic: device private variable,
2049 * @mask: A mask indicating which Intr block must be modified and,
2050 * @flag: A flag indicating whether to enable or disable the Intrs.
2051 * Description: This function will either disable or enable the interrupts
20346722
K		 2052 * depending on the flag argument. The mask argument can be used to
2053 * enable/disable any Intr block.
1da177e4
LT		 2054 * Return Value: NONE.
2055 */
2056
2057static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2058{
1ee6dd77 2059 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2060 register u64 temp64 = 0, intr_mask = 0;
2061
2062 intr_mask = nic->general_int_mask;
1da177e4
LT		 2063
2064 /* Top level interrupt classification */
2065 /* PIC Interrupts */
9caab458 2066 if (mask & TX_PIC_INTR) {
1da177e4 2067 /* Enable PIC Intrs in the general intr mask register */
9caab458 2068 intr_mask |= TXPIC_INT_M;
1da177e4 2069 if (flag == ENABLE_INTRS) {
20346722 2070 /*
a371a07d 2071 * If Hercules adapter enable GPIO otherwise
b41477f3 2072 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 2073 * interrupts for now.
2074 * TODO
1da177e4 2075 */
a371a07d 2076 if (s2io_link_fault_indication(nic) ==
d44570e4 2077 LINK_UP_DOWN_INTERRUPT) {
9caab458 2078 do_s2io_write_bits(PIC_INT_GPIO, flag,
d44570e4 2079 &bar0->pic_int_mask);
9caab458 2080 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
d44570e4 2081 &bar0->gpio_int_mask);
9caab458 2082 } else
a371a07d 2083 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2084 } else if (flag == DISABLE_INTRS) {
20346722
K		 2085 /*
2086 * Disable PIC Intrs in the general
2087 * intr mask register
1da177e4
LT		 2088 */
2089 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2090 }
2091 }
2092
1da177e4
LT		 2093 /* Tx traffic interrupts */
2094 if (mask & TX_TRAFFIC_INTR) {
9caab458 2095 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2096 if (flag == ENABLE_INTRS) {
20346722 2097 /*
1da177e4 2098 * Enable all the Tx side interrupts
20346722 2099 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2100 */
2101 writeq(0x0, &bar0->tx_traffic_mask);
2102 } else if (flag == DISABLE_INTRS) {
20346722
K		 2103 /*
2104 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2105 * register.
2106 */
2107 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2108 }
2109 }
2110
2111 /* Rx traffic interrupts */
2112 if (mask & RX_TRAFFIC_INTR) {
9caab458 2113 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2114 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2115 /* writing 0 Enables all 8 RX interrupt levels */
2116 writeq(0x0, &bar0->rx_traffic_mask);
2117 } else if (flag == DISABLE_INTRS) {
20346722
K		 2118 /*
2119 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2120 * register.
2121 */
2122 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2123 }
2124 }
9caab458
SS		 2125
2126 temp64 = readq(&bar0->general_int_mask);
2127 if (flag == ENABLE_INTRS)
d44570e4 2128 temp64 &= ~((u64)intr_mask);
9caab458
SS		 2129 else
2130 temp64 = DISABLE_ALL_INTRS;
2131 writeq(temp64, &bar0->general_int_mask);
2132
2133 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2134}
2135
19a60522
SS		 2136/**
2137 * verify_pcc_quiescent- Checks for PCC quiescent state
2138 * Return: 1 If PCC is quiescence
2139 * 0 If PCC is not quiescence
2140 */
1ee6dd77 2141static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2142{
19a60522 2143 int ret = 0, herc;
1ee6dd77 2144 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2145 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2146
19a60522 2147 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2148
f957bcf0 2149 if (flag == false) {
44c10138 2150 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2151 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2152 ret = 1;
19a60522
SS		 2153 } else {
2154 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2155 ret = 1;
20346722
K		 2156 }
2157 } else {
44c10138 2158 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2159 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2160 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2161 ret = 1;
5e25b9dd
K		 2162 } else {
2163 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2164 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2165 ret = 1;
20346722
K		 2166 }
2167 }
2168
2169 return ret;
2170}
2171/**
2172 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2173 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2174 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2175 * differs and the calling function passes the input argument flag to
2176 * indicate this.
20346722 2177 * Return: 1 If xena is quiescence
1da177e4
LT		 2178 * 0 If Xena is not quiescence
2179 */
2180
1ee6dd77 2181static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2182{
19a60522 2183 int mode;
1ee6dd77 2184 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2185 u64 val64 = readq(&bar0->adapter_status);
2186 mode = s2io_verify_pci_mode(sp);
1da177e4 2187
19a60522 2188 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
9e39f7c5 2189 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
19a60522
SS		 2190 return 0;
2191 }
2192 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
9e39f7c5 2193 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
19a60522
SS		 2194 return 0;
2195 }
2196 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
9e39f7c5 2197 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
19a60522
SS		 2198 return 0;
2199 }
2200 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
9e39f7c5 2201 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
19a60522
SS		 2202 return 0;
2203 }
2204 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
9e39f7c5 2205 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
19a60522
SS		 2206 return 0;
2207 }
2208 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
9e39f7c5 2209 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
19a60522
SS		 2210 return 0;
2211 }
2212 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
9e39f7c5 2213 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
19a60522
SS		 2214 return 0;
2215 }
2216 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
9e39f7c5 2217 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
19a60522 2218 return 0;
1da177e4
LT		 2219 }
2220
19a60522
SS		 2221 /*
2222 * In PCI 33 mode, the P_PLL is not used, and therefore,
2223 * the the P_PLL_LOCK bit in the adapter_status register will
2224 * not be asserted.
2225 */
2226 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
d44570e4
JP		 2227 sp->device_type == XFRAME_II_DEVICE &&
2228 mode != PCI_MODE_PCI_33) {
9e39f7c5 2229 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
19a60522
SS		 2230 return 0;
2231 }
2232 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
d44570e4 2233 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
9e39f7c5 2234 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
19a60522
SS		 2235 return 0;
2236 }
2237 return 1;
1da177e4
LT		 2238}
2239
2240/**
2241 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2242 * @sp: Pointer to device specifc structure
20346722 2243 * Description :
1da177e4
LT		 2244 * New procedure to clear mac address reading problems on Alpha platforms
2245 *
2246 */
2247
d44570e4 2248static void fix_mac_address(struct s2io_nic *sp)
1da177e4 2249{
1ee6dd77 2250 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2251 u64 val64;
2252 int i = 0;
2253
2254 while (fix_mac[i] != END_SIGN) {
2255 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2256 udelay(10);
1da177e4
LT		 2257 val64 = readq(&bar0->gpio_control);
2258 }
2259}
2260
2261/**
20346722 2262 * start_nic - Turns the device on
1da177e4 2263 * @nic : device private variable.
20346722
K		 2264 * Description:
2265 * This function actually turns the device on. Before this function is
2266 * called,all Registers are configured from their reset states
2267 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2268 * calling this function, the device interrupts are cleared and the NIC is
2269 * literally switched on by writing into the adapter control register.
20346722 2270 * Return Value:
1da177e4
LT		 2271 * SUCCESS on success and -1 on failure.
2272 */
2273
2274static int start_nic(struct s2io_nic *nic)
2275{
1ee6dd77 2276 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2277 struct net_device *dev = nic->dev;
2278 register u64 val64 = 0;
20346722 2279 u16 subid, i;
ffb5df6c
JP		 2280 struct config_param *config = &nic->config;
2281 struct mac_info *mac_control = &nic->mac_control;
1da177e4
LT		 2282
2283 /* PRC Initialization and configuration */
2284 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2285 struct ring_info *ring = &mac_control->rings[i];
2286
d44570e4 2287 writeq((u64)ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2288 &bar0->prc_rxd0_n[i]);
2289
2290 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2291 if (nic->rxd_mode == RXD_MODE_1)
2292 val64 |= PRC_CTRL_RC_ENABLED;
2293 else
2294 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2295 if (nic->device_type == XFRAME_II_DEVICE)
2296 val64 |= PRC_CTRL_GROUP_READS;
2297 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2298 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2299 writeq(val64, &bar0->prc_ctrl_n[i]);
2300 }
2301
da6971d8
AR		 2302 if (nic->rxd_mode == RXD_MODE_3B) {
2303 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2304 val64 = readq(&bar0->rx_pa_cfg);
2305 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2306 writeq(val64, &bar0->rx_pa_cfg);
2307 }
1da177e4 2308
926930b2
SS		 2309 if (vlan_tag_strip == 0) {
2310 val64 = readq(&bar0->rx_pa_cfg);
2311 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2312 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2313 nic->vlan_strip_flag = 0;
926930b2
SS		 2314 }
2315
20346722 2316 /*
1da177e4
LT		 2317 * Enabling MC-RLDRAM. After enabling the device, we timeout
2318 * for around 100ms, which is approximately the time required
2319 * for the device to be ready for operation.
2320 */
2321 val64 = readq(&bar0->mc_rldram_mrs);
2322 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2323 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2324 val64 = readq(&bar0->mc_rldram_mrs);
2325
20346722 2326 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2327
2328 /* Enabling ECC Protection. */
2329 val64 = readq(&bar0->adapter_control);
2330 val64 &= ~ADAPTER_ECC_EN;
2331 writeq(val64, &bar0->adapter_control);
2332
20346722
K		 2333 /*
2334 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2335 * it.
2336 */
2337 val64 = readq(&bar0->adapter_status);
19a60522 2338 if (!verify_xena_quiescence(nic)) {
9e39f7c5
JP		 2339 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2340 "Adapter status reads: 0x%llx\n",
2341 dev->name, (unsigned long long)val64);
1da177e4
LT		 2342 return FAILURE;
2343 }
2344
20346722 2345 /*
1da177e4 2346 * With some switches, link might be already up at this point.
20346722
K		 2347 * Because of this weird behavior, when we enable laser,
2348 * we may not get link. We need to handle this. We cannot
2349 * figure out which switch is misbehaving. So we are forced to
2350 * make a global change.
1da177e4
LT		 2351 */
2352
2353 /* Enabling Laser. */
2354 val64 = readq(&bar0->adapter_control);
2355 val64 |= ADAPTER_EOI_TX_ON;
2356 writeq(val64, &bar0->adapter_control);
2357
c92ca04b
AR		 2358 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2359 /*
2360 * Dont see link state interrupts initally on some switches,
2361 * so directly scheduling the link state task here.
2362 */
2363 schedule_work(&nic->set_link_task);
2364 }
1da177e4
LT		 2365 /* SXE-002: Initialize link and activity LED */
2366 subid = nic->pdev->subsystem_device;
541ae68f
K		 2367 if (((subid & 0xFF) >= 0x07) &&
2368 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2369 val64 = readq(&bar0->gpio_control);
2370 val64 |= 0x0000800000000000ULL;
2371 writeq(val64, &bar0->gpio_control);
2372 val64 = 0x0411040400000000ULL;
509a2671 2373 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2374 }
2375
1da177e4
LT		 2376 return SUCCESS;
2377}
fed5eccd
AR		 2378/**
2379 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2380 */
d44570e4
JP		 2381static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2382 struct TxD *txdlp, int get_off)
fed5eccd 2383{
1ee6dd77 2384 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2385 struct sk_buff *skb;
1ee6dd77 2386 struct TxD *txds;
fed5eccd
AR		 2387 u16 j, frg_cnt;
2388
2389 txds = txdlp;
2fda096d 2390 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
d44570e4
JP		 2391 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2392 sizeof(u64), PCI_DMA_TODEVICE);
fed5eccd
AR		 2393 txds++;
2394 }
2395
d44570e4 2396 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
fed5eccd 2397 if (!skb) {
1ee6dd77 2398 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2399 return NULL;
2400 }
d44570e4 2401 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
e743d313 2402 skb_headlen(skb), PCI_DMA_TODEVICE);
fed5eccd
AR		 2403 frg_cnt = skb_shinfo(skb)->nr_frags;
2404 if (frg_cnt) {
2405 txds++;
2406 for (j = 0; j < frg_cnt; j++, txds++) {
2407 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2408 if (!txds->Buffer_Pointer)
2409 break;
d44570e4
JP		 2410 pci_unmap_page(nic->pdev,
2411 (dma_addr_t)txds->Buffer_Pointer,
fed5eccd
AR		 2412 frag->size, PCI_DMA_TODEVICE);
2413 }
2414 }
d44570e4
JP		 2415 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2416 return skb;
fed5eccd 2417}
1da177e4 2418
20346722
K		 2419/**
2420 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2421 * @nic : device private variable.
20346722 2422 * Description:
1da177e4 2423 * Free all queued Tx buffers.
20346722 2424 * Return Value: void
d44570e4 2425 */
1da177e4
LT		 2426
2427static void free_tx_buffers(struct s2io_nic *nic)
2428{
2429 struct net_device *dev = nic->dev;
2430 struct sk_buff *skb;
1ee6dd77 2431 struct TxD *txdp;
1da177e4 2432 int i, j;
fed5eccd 2433 int cnt = 0;
ffb5df6c
JP		 2434 struct config_param *config = &nic->config;
2435 struct mac_info *mac_control = &nic->mac_control;
2436 struct stat_block *stats = mac_control->stats_info;
2437 struct swStat *swstats = &stats->sw_stat;
1da177e4
LT		 2438
2439 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2440 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2441 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2442 unsigned long flags;
13d866a9
JP		 2443
2444 spin_lock_irqsave(&fifo->tx_lock, flags);
2445 for (j = 0; j < tx_cfg->fifo_len; j++) {
2446 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2447 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2448 if (skb) {
ffb5df6c 2449 swstats->mem_freed += skb->truesize;
fed5eccd
AR		 2450 dev_kfree_skb(skb);
2451 cnt++;
1da177e4 2452 }
1da177e4
LT		 2453 }
2454 DBG_PRINT(INTR_DBG,
9e39f7c5 2455 "%s: forcibly freeing %d skbs on FIFO%d\n",
1da177e4 2456 dev->name, cnt, i);
13d866a9
JP		 2457 fifo->tx_curr_get_info.offset = 0;
2458 fifo->tx_curr_put_info.offset = 0;
2459 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2460 }
2461}
2462
20346722
K		 2463/**
2464 * stop_nic - To stop the nic
1da177e4 2465 * @nic ; device private variable.
20346722
K		 2466 * Description:
2467 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2468 * function does. This function is called to stop the device.
2469 * Return Value:
2470 * void.
2471 */
2472
2473static void stop_nic(struct s2io_nic *nic)
2474{
1ee6dd77 2475 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2476 register u64 val64 = 0;
5d3213cc 2477 u16 interruptible;
1da177e4
LT		 2478
2479 /* Disable all interrupts */
9caab458 2480 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2481 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2482 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2483 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2484
5d3213cc
AR		 2485 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2486 val64 = readq(&bar0->adapter_control);
2487 val64 &= ~(ADAPTER_CNTL_EN);
2488 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2489}
2490
20346722
K		 2491/**
2492 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2493 * @ring_info: per ring structure
3f78d885
SH		 2494 * @from_card_up: If this is true, we will map the buffer to get
2495 * the dma address for buf0 and buf1 to give it to the card.
2496 * Else we will sync the already mapped buffer to give it to the card.
20346722 2497 * Description:
1da177e4
LT		 2498 * The function allocates Rx side skbs and puts the physical
2499 * address of these buffers into the RxD buffer pointers, so that the NIC
2500 * can DMA the received frame into these locations.
2501 * The NIC supports 3 receive modes, viz
2502 * 1. single buffer,
2503 * 2. three buffer and
2504 * 3. Five buffer modes.
20346722
K		 2505 * Each mode defines how many fragments the received frame will be split
2506 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2507 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2508 * is split into 3 fragments. As of now only single buffer mode is
2509 * supported.
2510 * Return Value:
2511 * SUCCESS on success or an appropriate -ve value on failure.
2512 */
8d8bb39b 2513static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
d44570e4 2514 int from_card_up)
1da177e4 2515{
1da177e4 2516 struct sk_buff *skb;
1ee6dd77 2517 struct RxD_t *rxdp;
0425b46a 2518 int off, size, block_no, block_no1;
1da177e4 2519 u32 alloc_tab = 0;
20346722 2520 u32 alloc_cnt;
20346722 2521 u64 tmp;
1ee6dd77 2522 struct buffAdd *ba;
1ee6dd77 2523 struct RxD_t *first_rxdp = NULL;
363dc367 2524 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2525 int rxd_index = 0;
6d517a27
VP		 2526 struct RxD1 *rxdp1;
2527 struct RxD3 *rxdp3;
ffb5df6c 2528 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2529
0425b46a 2530 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2531
0425b46a 2532 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2533 while (alloc_tab < alloc_cnt) {
0425b46a 2534 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2535
0425b46a
SH		 2536 off = ring->rx_curr_put_info.offset;
2537
2538 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2539
2540 rxd_index = off + 1;
2541 if (block_no)
2542 rxd_index += (block_no * ring->rxd_count);
da6971d8 2543
7d2e3cb7 2544 if ((block_no == block_no1) &&
d44570e4
JP		 2545 (off == ring->rx_curr_get_info.offset) &&
2546 (rxdp->Host_Control)) {
9e39f7c5
JP		 2547 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2548 ring->dev->name);
1da177e4
LT		 2549 goto end;
2550 }
0425b46a
SH		 2551 if (off && (off == ring->rxd_count)) {
2552 ring->rx_curr_put_info.block_index++;
2553 if (ring->rx_curr_put_info.block_index ==
d44570e4 2554 ring->block_count)
0425b46a
SH		 2555 ring->rx_curr_put_info.block_index = 0;
2556 block_no = ring->rx_curr_put_info.block_index;
2557 off = 0;
2558 ring->rx_curr_put_info.offset = off;
2559 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2560 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2561 ring->dev->name, rxdp);
2562
1da177e4 2563 }
c9fcbf47 2564
da6971d8 2565 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
d44570e4
JP		 2566 ((ring->rxd_mode == RXD_MODE_3B) &&
2567 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2568 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2569 goto end;
2570 }
da6971d8 2571 /* calculate size of skb based on ring mode */
d44570e4
JP		 2572 size = ring->mtu +
2573 HEADER_ETHERNET_II_802_3_SIZE +
2574 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2575 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2576 size += NET_IP_ALIGN;
da6971d8 2577 else
0425b46a 2578 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2579
da6971d8
AR		 2580 /* allocate skb */
2581 skb = dev_alloc_skb(size);
d44570e4 2582 if (!skb) {
9e39f7c5
JP		 2583 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2584 ring->dev->name);
303bcb4b
K		 2585 if (first_rxdp) {
2586 wmb();
2587 first_rxdp->Control_1 |= RXD_OWN_XENA;
2588 }
ffb5df6c 2589 swstats->mem_alloc_fail_cnt++;
7d2e3cb7 2590
da6971d8
AR		 2591 return -ENOMEM ;
2592 }
ffb5df6c 2593 swstats->mem_allocated += skb->truesize;
0425b46a
SH		 2594
2595 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2596 /* 1 buffer mode - normal operation mode */
d44570e4 2597 rxdp1 = (struct RxD1 *)rxdp;
1ee6dd77 2598 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2599 skb_reserve(skb, NET_IP_ALIGN);
d44570e4
JP		 2600 rxdp1->Buffer0_ptr =
2601 pci_map_single(ring->pdev, skb->data,
2602 size - NET_IP_ALIGN,
2603 PCI_DMA_FROMDEVICE);
8d8bb39b 2604 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2605 rxdp1->Buffer0_ptr))
491abf25
VP		 2606 goto pci_map_failed;
2607
8a4bdbaa 2608 rxdp->Control_2 =
491976b2 2609 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
d44570e4 2610 rxdp->Host_Control = (unsigned long)skb;
0425b46a 2611 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2612 /*
6d517a27
VP		 2613 * 2 buffer mode -
2614 * 2 buffer mode provides 128
da6971d8 2615 * byte aligned receive buffers.
da6971d8
AR		 2616 */
2617
d44570e4 2618 rxdp3 = (struct RxD3 *)rxdp;
491976b2 2619 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2620 Buffer0_ptr = rxdp3->Buffer0_ptr;
2621 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2622 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2623 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2624 rxdp3->Buffer0_ptr = Buffer0_ptr;
2625 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2626
0425b46a 2627 ba = &ring->ba[block_no][off];
da6971d8 2628 skb_reserve(skb, BUF0_LEN);
d44570e4 2629 tmp = (u64)(unsigned long)skb->data;
da6971d8
AR		 2630 tmp += ALIGN_SIZE;
2631 tmp &= ~ALIGN_SIZE;
2632 skb->data = (void *) (unsigned long)tmp;
27a884dc 2633 skb_reset_tail_pointer(skb);
da6971d8 2634
3f78d885 2635 if (from_card_up) {
6d517a27 2636 rxdp3->Buffer0_ptr =
d44570e4
JP		 2637 pci_map_single(ring->pdev, ba->ba_0,
2638 BUF0_LEN,
2639 PCI_DMA_FROMDEVICE);
2640 if (pci_dma_mapping_error(nic->pdev,
2641 rxdp3->Buffer0_ptr))
3f78d885
SH		 2642 goto pci_map_failed;
2643 } else
0425b46a 2644 pci_dma_sync_single_for_device(ring->pdev,
d44570e4
JP		 2645 (dma_addr_t)rxdp3->Buffer0_ptr,
2646 BUF0_LEN,
2647 PCI_DMA_FROMDEVICE);
491abf25 2648
da6971d8 2649 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2650 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2651 /* Two buffer mode */
2652
2653 /*
6aa20a22 2654 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2655 * L4 payload
2656 */
d44570e4
JP		 2657 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2658 skb->data,
2659 ring->mtu + 4,
2660 PCI_DMA_FROMDEVICE);
da6971d8 2661
8d8bb39b 2662 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2663 rxdp3->Buffer2_ptr))
491abf25
VP		 2664 goto pci_map_failed;
2665
3f78d885 2666 if (from_card_up) {
0425b46a
SH		 2667 rxdp3->Buffer1_ptr =
2668 pci_map_single(ring->pdev,
d44570e4
JP		 2669 ba->ba_1,
2670 BUF1_LEN,
2671 PCI_DMA_FROMDEVICE);
0425b46a 2672
8d8bb39b 2673 if (pci_dma_mapping_error(nic->pdev,
d44570e4
JP		 2674 rxdp3->Buffer1_ptr)) {
2675 pci_unmap_single(ring->pdev,
2676 (dma_addr_t)(unsigned long)
2677 skb->data,
2678 ring->mtu + 4,
2679 PCI_DMA_FROMDEVICE);
3f78d885
SH		 2680 goto pci_map_failed;
2681 }
75c30b13 2682 }
da6971d8
AR		 2683 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2684 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
d44570e4 2685 (ring->mtu + 4);
da6971d8 2686 }
b7b5a128 2687 rxdp->Control_2 |= s2BIT(0);
0425b46a 2688 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2689 }
303bcb4b
K		 2690 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2691 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2692 off++;
0425b46a 2693 if (off == (ring->rxd_count + 1))
da6971d8 2694 off = 0;
0425b46a 2695 ring->rx_curr_put_info.offset = off;
20346722 2696
da6971d8 2697 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2698 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2699 if (first_rxdp) {
2700 wmb();
2701 first_rxdp->Control_1 |= RXD_OWN_XENA;
2702 }
2703 first_rxdp = rxdp;
2704 }
0425b46a 2705 ring->rx_bufs_left += 1;
1da177e4
LT		 2706 alloc_tab++;
2707 }
2708
d44570e4 2709end:
303bcb4b
K		 2710 /* Transfer ownership of first descriptor to adapter just before
2711 * exiting. Before that, use memory barrier so that ownership
2712 * and other fields are seen by adapter correctly.
2713 */
2714 if (first_rxdp) {
2715 wmb();
2716 first_rxdp->Control_1 |= RXD_OWN_XENA;
2717 }
2718
1da177e4 2719 return SUCCESS;
d44570e4 2720
491abf25 2721pci_map_failed:
ffb5df6c
JP		 2722 swstats->pci_map_fail_cnt++;
2723 swstats->mem_freed += skb->truesize;
491abf25
VP		 2724 dev_kfree_skb_irq(skb);
2725 return -ENOMEM;
1da177e4
LT		 2726}
2727
da6971d8
AR		 2728static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2729{
2730 struct net_device *dev = sp->dev;
2731 int j;
2732 struct sk_buff *skb;
1ee6dd77 2733 struct RxD_t *rxdp;
1ee6dd77 2734 struct buffAdd *ba;
6d517a27
VP		 2735 struct RxD1 *rxdp1;
2736 struct RxD3 *rxdp3;
ffb5df6c
JP		 2737 struct mac_info *mac_control = &sp->mac_control;
2738 struct stat_block *stats = mac_control->stats_info;
2739 struct swStat *swstats = &stats->sw_stat;
da6971d8 2740
da6971d8
AR		 2741 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2742 rxdp = mac_control->rings[ring_no].
d44570e4
JP		 2743 rx_blocks[blk].rxds[j].virt_addr;
2744 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2745 if (!skb)
da6971d8 2746 continue;
da6971d8 2747 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4
JP		 2748 rxdp1 = (struct RxD1 *)rxdp;
2749 pci_unmap_single(sp->pdev,
2750 (dma_addr_t)rxdp1->Buffer0_ptr,
2751 dev->mtu +
2752 HEADER_ETHERNET_II_802_3_SIZE +
2753 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2754 PCI_DMA_FROMDEVICE);
1ee6dd77 2755 memset(rxdp, 0, sizeof(struct RxD1));
d44570e4
JP		 2756 } else if (sp->rxd_mode == RXD_MODE_3B) {
2757 rxdp3 = (struct RxD3 *)rxdp;
2758 ba = &mac_control->rings[ring_no].ba[blk][j];
2759 pci_unmap_single(sp->pdev,
2760 (dma_addr_t)rxdp3->Buffer0_ptr,
2761 BUF0_LEN,
2762 PCI_DMA_FROMDEVICE);
2763 pci_unmap_single(sp->pdev,
2764 (dma_addr_t)rxdp3->Buffer1_ptr,
2765 BUF1_LEN,
2766 PCI_DMA_FROMDEVICE);
2767 pci_unmap_single(sp->pdev,
2768 (dma_addr_t)rxdp3->Buffer2_ptr,
2769 dev->mtu + 4,
2770 PCI_DMA_FROMDEVICE);
1ee6dd77 2771 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2772 }
ffb5df6c 2773 swstats->mem_freed += skb->truesize;
da6971d8 2774 dev_kfree_skb(skb);
0425b46a 2775 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2776 }
2777}
2778
1da177e4 2779/**
20346722 2780 * free_rx_buffers - Frees all Rx buffers
1da177e4 2781 * @sp: device private variable.
20346722 2782 * Description:
1da177e4
LT		 2783 * This function will free all Rx buffers allocated by host.
2784 * Return Value:
2785 * NONE.
2786 */
2787
2788static void free_rx_buffers(struct s2io_nic *sp)
2789{
2790 struct net_device *dev = sp->dev;
da6971d8 2791 int i, blk = 0, buf_cnt = 0;
ffb5df6c
JP		 2792 struct config_param *config = &sp->config;
2793 struct mac_info *mac_control = &sp->mac_control;
1da177e4
LT		 2794
2795 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2796 struct ring_info *ring = &mac_control->rings[i];
2797
da6971d8 2798 for (blk = 0; blk < rx_ring_sz[i]; blk++)
d44570e4 2799 free_rxd_blk(sp, i, blk);
1da177e4 2800
13d866a9
JP		 2801 ring->rx_curr_put_info.block_index = 0;
2802 ring->rx_curr_get_info.block_index = 0;
2803 ring->rx_curr_put_info.offset = 0;
2804 ring->rx_curr_get_info.offset = 0;
2805 ring->rx_bufs_left = 0;
9e39f7c5 2806 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
1da177e4
LT		 2807 dev->name, buf_cnt, i);
2808 }
2809}
2810
8d8bb39b 2811static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2812{
8d8bb39b 2813 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2814 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2815 ring->dev->name);
f61e0a35
SH		 2816 }
2817 return 0;
2818}
2819
1da177e4
LT		 2820/**
2821 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2822 * @napi : pointer to the napi structure.
20346722 2823 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2824 * during one pass through the 'Poll" function.
2825 * Description:
2826 * Comes into picture only if NAPI support has been incorporated. It does
2827 * the same thing that rx_intr_handler does, but not in a interrupt context
2828 * also It will process only a given number of packets.
2829 * Return value:
2830 * 0 on success and 1 if there are No Rx packets to be processed.
2831 */
2832
f61e0a35 2833static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2834{
f61e0a35
SH		 2835 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2836 struct net_device *dev = ring->dev;
f61e0a35 2837 int pkts_processed = 0;
1a79d1c3
AV		 2838 u8 __iomem *addr = NULL;
2839 u8 val8 = 0;
4cf1653a 2840 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2841 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2842 int budget_org = budget;
1da177e4 2843
f61e0a35
SH		 2844 if (unlikely(!is_s2io_card_up(nic)))
2845 return 0;
1da177e4 2846
f61e0a35 2847 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2848 s2io_chk_rx_buffers(nic, ring);
1da177e4 2849
f61e0a35 2850 if (pkts_processed < budget_org) {
288379f0 2851 napi_complete(napi);
f61e0a35 2852 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2853 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2854 addr += 7 - ring->ring_no;
2855 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2856 writeb(val8, addr);
2857 val8 = readb(addr);
1da177e4 2858 }
f61e0a35
SH		 2859 return pkts_processed;
2860}
d44570e4 2861
f61e0a35
SH		 2862static int s2io_poll_inta(struct napi_struct *napi, int budget)
2863{
2864 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2865 int pkts_processed = 0;
2866 int ring_pkts_processed, i;
2867 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2868 int budget_org = budget;
ffb5df6c
JP		 2869 struct config_param *config = &nic->config;
2870 struct mac_info *mac_control = &nic->mac_control;
1da177e4 2871
f61e0a35
SH		 2872 if (unlikely(!is_s2io_card_up(nic)))
2873 return 0;
1da177e4 2874
1da177e4 2875 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2876 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2877 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2878 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2879 pkts_processed += ring_pkts_processed;
2880 budget -= ring_pkts_processed;
2881 if (budget <= 0)
1da177e4 2882 break;
1da177e4 2883 }
f61e0a35 2884 if (pkts_processed < budget_org) {
288379f0 2885 napi_complete(napi);
f61e0a35
SH		 2886 /* Re enable the Rx interrupts for the ring */
2887 writeq(0, &bar0->rx_traffic_mask);
2888 readl(&bar0->rx_traffic_mask);
2889 }
2890 return pkts_processed;
1da177e4 2891}
20346722 2892
b41477f3 2893#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2894/**
b41477f3 2895 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2896 * @dev : pointer to the device structure.
2897 * Description:
b41477f3
AR		 2898 * This function will be called by upper layer to check for events on the
2899 * interface in situations where interrupts are disabled. It is used for
2900 * specific in-kernel networking tasks, such as remote consoles and kernel
2901 * debugging over the network (example netdump in RedHat).
612eff0e 2902 */
612eff0e
BH		 2903static void s2io_netpoll(struct net_device *dev)
2904{
4cf1653a 2905 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2906 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2907 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e 2908 int i;
ffb5df6c
JP		 2909 struct config_param *config = &nic->config;
2910 struct mac_info *mac_control = &nic->mac_control;
612eff0e 2911
d796fdb7
LV		 2912 if (pci_channel_offline(nic->pdev))
2913 return;
2914
612eff0e
BH		 2915 disable_irq(dev->irq);
2916
612eff0e 2917 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2918 writeq(val64, &bar0->tx_traffic_int);
2919
6aa20a22 2920 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2921 * run out of skbs and will fail and eventually netpoll application such
2922 * as netdump will fail.
2923 */
2924 for (i = 0; i < config->tx_fifo_num; i++)
2925 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2926
b41477f3 2927 /* check for received packet and indicate up to network */
13d866a9
JP		 2928 for (i = 0; i < config->rx_ring_num; i++) {
2929 struct ring_info *ring = &mac_control->rings[i];
2930
2931 rx_intr_handler(ring, 0);
2932 }
612eff0e
BH		 2933
2934 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2935 struct ring_info *ring = &mac_control->rings[i];
2936
2937 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2938 DBG_PRINT(INFO_DBG,
2939 "%s: Out of memory in Rx Netpoll!!\n",
2940 dev->name);
612eff0e
BH		 2941 break;
2942 }
2943 }
612eff0e 2944 enable_irq(dev->irq);
612eff0e
BH		 2945}
2946#endif
2947
20346722 2948/**
1da177e4 2949 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2950 * @ring_info: per ring structure.
2951 * @budget: budget for napi processing.
20346722
K		 2952 * Description:
2953 * If the interrupt is because of a received frame or if the
1da177e4 2954 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2955 * called. It picks out the RxD at which place the last Rx processing had
2956 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2957 * the offset.
2958 * Return Value:
f61e0a35 2959 * No. of napi packets processed.
1da177e4 2960 */
f61e0a35 2961static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2962{
c9fcbf47 2963 int get_block, put_block;
1ee6dd77
RB		 2964 struct rx_curr_get_info get_info, put_info;
2965 struct RxD_t *rxdp;
1da177e4 2966 struct sk_buff *skb;
f61e0a35 2967 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 2968 int i;
d44570e4
JP		 2969 struct RxD1 *rxdp1;
2970 struct RxD3 *rxdp3;
7d3d0439 2971
20346722
K		 2972 get_info = ring_data->rx_curr_get_info;
2973 get_block = get_info.block_index;
1ee6dd77 2974 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2975 put_block = put_info.block_index;
da6971d8 2976 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2977
da6971d8 2978 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2979 /*
2980 * If your are next to put index then it's
2981 * FIFO full condition
2982 */
da6971d8
AR		 2983 if ((get_block == put_block) &&
2984 (get_info.offset + 1) == put_info.offset) {
0425b46a 2985 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
d44570e4 2986 ring_data->dev->name);
da6971d8
AR		 2987 break;
2988 }
d44570e4 2989 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
20346722 2990 if (skb == NULL) {
9e39f7c5 2991 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
0425b46a 2992 ring_data->dev->name);
f61e0a35 2993 return 0;
1da177e4 2994 }
0425b46a 2995 if (ring_data->rxd_mode == RXD_MODE_1) {
d44570e4 2996 rxdp1 = (struct RxD1 *)rxdp;
0425b46a 2997 pci_unmap_single(ring_data->pdev, (dma_addr_t)
d44570e4
JP		 2998 rxdp1->Buffer0_ptr,
2999 ring_data->mtu +
3000 HEADER_ETHERNET_II_802_3_SIZE +
3001 HEADER_802_2_SIZE +
3002 HEADER_SNAP_SIZE,
3003 PCI_DMA_FROMDEVICE);
0425b46a 3004 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
d44570e4
JP		 3005 rxdp3 = (struct RxD3 *)rxdp;
3006 pci_dma_sync_single_for_cpu(ring_data->pdev,
3007 (dma_addr_t)rxdp3->Buffer0_ptr,
3008 BUF0_LEN,
3009 PCI_DMA_FROMDEVICE);
3010 pci_unmap_single(ring_data->pdev,
3011 (dma_addr_t)rxdp3->Buffer2_ptr,
3012 ring_data->mtu + 4,
3013 PCI_DMA_FROMDEVICE);
da6971d8 3014 }
863c11a9 3015 prefetch(skb->data);
20346722
K		 3016 rx_osm_handler(ring_data, rxdp);
3017 get_info.offset++;
da6971d8
AR		 3018 ring_data->rx_curr_get_info.offset = get_info.offset;
3019 rxdp = ring_data->rx_blocks[get_block].
d44570e4 3020 rxds[get_info.offset].virt_addr;
0425b46a 3021 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3022 get_info.offset = 0;
da6971d8 3023 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3024 get_block++;
da6971d8
AR		 3025 if (get_block == ring_data->block_count)
3026 get_block = 0;
3027 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 3028 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3029 }
1da177e4 3030
f61e0a35
SH		 3031 if (ring_data->nic->config.napi) {
3032 budget--;
3033 napi_pkts++;
3034 if (!budget)
0425b46a
SH		 3035 break;
3036 }
20346722 3037 pkt_cnt++;
1da177e4
LT		 3038 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3039 break;
3040 }
0425b46a 3041 if (ring_data->lro) {
7d3d0439 3042 /* Clear all LRO sessions before exiting */
d44570e4 3043 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 3044 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3045 if (lro->in_use) {
0425b46a 3046 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3047 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3048 clear_lro_session(lro);
3049 }
3050 }
3051 }
d44570e4 3052 return napi_pkts;
1da177e4 3053}
20346722
K		 3054
3055/**
1da177e4
LT		 3056 * tx_intr_handler - Transmit interrupt handler
3057 * @nic : device private variable
20346722
K		 3058 * Description:
3059 * If an interrupt was raised to indicate DMA complete of the
3060 * Tx packet, this function is called. It identifies the last TxD
3061 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3062 * DMA'ed into the NICs internal memory.
3063 * Return Value:
3064 * NONE
3065 */
3066
1ee6dd77 3067static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3068{
1ee6dd77 3069 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3070 struct tx_curr_get_info get_info, put_info;
3a3d5756 3071 struct sk_buff *skb = NULL;
1ee6dd77 3072 struct TxD *txdlp;
3a3d5756 3073 int pkt_cnt = 0;
2fda096d 3074 unsigned long flags = 0;
f9046eb3 3075 u8 err_mask;
ffb5df6c
JP		 3076 struct stat_block *stats = nic->mac_control.stats_info;
3077 struct swStat *swstats = &stats->sw_stat;
1da177e4 3078
2fda096d 3079 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
d44570e4 3080 return;
2fda096d 3081
20346722 3082 get_info = fifo_data->tx_curr_get_info;
1ee6dd77 3083 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
d44570e4
JP		 3084 txdlp = (struct TxD *)
3085 fifo_data->list_info[get_info.offset].list_virt_addr;
20346722
K		 3086 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3087 (get_info.offset != put_info.offset) &&
3088 (txdlp->Host_Control)) {
3089 /* Check for TxD errors */
3090 if (txdlp->Control_1 & TXD_T_CODE) {
3091 unsigned long long err;
3092 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0 3093 if (err & 0x1) {
ffb5df6c 3094 swstats->parity_err_cnt++;
bd1034f0 3095 }
491976b2
SH		 3096
3097 /* update t_code statistics */
f9046eb3 3098 err_mask = err >> 48;
d44570e4
JP		 3099 switch (err_mask) {
3100 case 2:
ffb5df6c 3101 swstats->tx_buf_abort_cnt++;
491976b2
SH		 3102 break;
3103
d44570e4 3104 case 3:
ffb5df6c 3105 swstats->tx_desc_abort_cnt++;
491976b2
SH		 3106 break;
3107
d44570e4 3108 case 7:
ffb5df6c 3109 swstats->tx_parity_err_cnt++;
491976b2
SH		 3110 break;
3111
d44570e4 3112 case 10:
ffb5df6c 3113 swstats->tx_link_loss_cnt++;
491976b2
SH		 3114 break;
3115
d44570e4 3116 case 15:
ffb5df6c 3117 swstats->tx_list_proc_err_cnt++;
491976b2 3118 break;
d44570e4 3119 }
20346722 3120 }
1da177e4 3121
fed5eccd 3122 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3123 if (skb == NULL) {
2fda096d 3124 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
9e39f7c5
JP		 3125 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3126 __func__);
20346722
K		 3127 return;
3128 }
3a3d5756 3129 pkt_cnt++;
20346722 3130
20346722 3131 /* Updating the statistics block */
ffb5df6c 3132 swstats->mem_freed += skb->truesize;
20346722
K		 3133 dev_kfree_skb_irq(skb);
3134
3135 get_info.offset++;
863c11a9
AR		 3136 if (get_info.offset == get_info.fifo_len + 1)
3137 get_info.offset = 0;
d44570e4
JP		 3138 txdlp = (struct TxD *)
3139 fifo_data->list_info[get_info.offset].list_virt_addr;
3140 fifo_data->tx_curr_get_info.offset = get_info.offset;
1da177e4
LT		 3141 }
3142
3a3d5756 3143 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3144
3145 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3146}
3147
bd1034f0
AR		 3148/**
3149 * s2io_mdio_write - Function to write in to MDIO registers
3150 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3151 * @addr : address value
3152 * @value : data value
3153 * @dev : pointer to net_device structure
3154 * Description:
3155 * This function is used to write values to the MDIO registers
3156 * NONE
3157 */
d44570e4
JP		 3158static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3159 struct net_device *dev)
bd1034f0 3160{
d44570e4 3161 u64 val64;
4cf1653a 3162 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3163 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0 3164
d44570e4
JP		 3165 /* address transaction */
3166 val64 = MDIO_MMD_INDX_ADDR(addr) |
3167 MDIO_MMD_DEV_ADDR(mmd_type) |
3168 MDIO_MMS_PRT_ADDR(0x0);
bd1034f0
AR		 3169 writeq(val64, &bar0->mdio_control);
3170 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3171 writeq(val64, &bar0->mdio_control);
3172 udelay(100);
3173
d44570e4
JP		 3174 /* Data transaction */
3175 val64 = MDIO_MMD_INDX_ADDR(addr) |
3176 MDIO_MMD_DEV_ADDR(mmd_type) |
3177 MDIO_MMS_PRT_ADDR(0x0) |
3178 MDIO_MDIO_DATA(value) |
3179 MDIO_OP(MDIO_OP_WRITE_TRANS);
bd1034f0
AR		 3180 writeq(val64, &bar0->mdio_control);
3181 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3182 writeq(val64, &bar0->mdio_control);
3183 udelay(100);
3184
d44570e4
JP		 3185 val64 = MDIO_MMD_INDX_ADDR(addr) |
3186 MDIO_MMD_DEV_ADDR(mmd_type) |
3187 MDIO_MMS_PRT_ADDR(0x0) |
3188 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3189 writeq(val64, &bar0->mdio_control);
3190 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3191 writeq(val64, &bar0->mdio_control);
3192 udelay(100);
bd1034f0
AR		 3193}
3194
3195/**
3196 * s2io_mdio_read - Function to write in to MDIO registers
3197 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3198 * @addr : address value
3199 * @dev : pointer to net_device structure
3200 * Description:
3201 * This function is used to read values to the MDIO registers
3202 * NONE
3203 */
3204static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3205{
3206 u64 val64 = 0x0;
3207 u64 rval64 = 0x0;
4cf1653a 3208 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3209 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3210
3211 /* address transaction */
d44570e4
JP		 3212 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3213 | MDIO_MMD_DEV_ADDR(mmd_type)
3214 | MDIO_MMS_PRT_ADDR(0x0));
bd1034f0
AR		 3215 writeq(val64, &bar0->mdio_control);
3216 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3217 writeq(val64, &bar0->mdio_control);
3218 udelay(100);
3219
3220 /* Data transaction */
d44570e4
JP		 3221 val64 = MDIO_MMD_INDX_ADDR(addr) |
3222 MDIO_MMD_DEV_ADDR(mmd_type) |
3223 MDIO_MMS_PRT_ADDR(0x0) |
3224 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3225 writeq(val64, &bar0->mdio_control);
3226 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3227 writeq(val64, &bar0->mdio_control);
3228 udelay(100);
3229
3230 /* Read the value from regs */
3231 rval64 = readq(&bar0->mdio_control);
3232 rval64 = rval64 & 0xFFFF0000;
3233 rval64 = rval64 >> 16;
3234 return rval64;
3235}
d44570e4 3236
bd1034f0
AR		 3237/**
3238 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
fbfecd37 3239 * @counter : counter value to be updated
bd1034f0
AR		 3240 * @flag : flag to indicate the status
3241 * @type : counter type
3242 * Description:
3243 * This function is to check the status of the xpak counters value
3244 * NONE
3245 */
3246
d44570e4
JP		 3247static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3248 u16 flag, u16 type)
bd1034f0
AR		 3249{
3250 u64 mask = 0x3;
3251 u64 val64;
3252 int i;
d44570e4 3253 for (i = 0; i < index; i++)
bd1034f0
AR		 3254 mask = mask << 0x2;
3255
d44570e4 3256 if (flag > 0) {
bd1034f0
AR		 3257 *counter = *counter + 1;
3258 val64 = *regs_stat & mask;
3259 val64 = val64 >> (index * 0x2);
3260 val64 = val64 + 1;
d44570e4
JP		 3261 if (val64 == 3) {
3262 switch (type) {
bd1034f0 3263 case 1:
9e39f7c5
JP		 3264 DBG_PRINT(ERR_DBG,
3265 "Take Xframe NIC out of service.\n");
3266 DBG_PRINT(ERR_DBG,
3267"Excessive temperatures may result in premature transceiver failure.\n");
d44570e4 3268 break;
bd1034f0 3269 case 2:
9e39f7c5
JP		 3270 DBG_PRINT(ERR_DBG,
3271 "Take Xframe NIC out of service.\n");
3272 DBG_PRINT(ERR_DBG,
3273"Excessive bias currents may indicate imminent laser diode failure.\n");
d44570e4 3274 break;
bd1034f0 3275 case 3:
9e39f7c5
JP		 3276 DBG_PRINT(ERR_DBG,
3277 "Take Xframe NIC out of service.\n");
3278 DBG_PRINT(ERR_DBG,
3279"Excessive laser output power may saturate far-end receiver.\n");
d44570e4 3280 break;
bd1034f0 3281 default:
d44570e4
JP		 3282 DBG_PRINT(ERR_DBG,
3283 "Incorrect XPAK Alarm type\n");
bd1034f0
AR		 3284 }
3285 val64 = 0x0;
3286 }
3287 val64 = val64 << (index * 0x2);
3288 *regs_stat = (*regs_stat & (~mask)) | (val64);
3289
3290 } else {
3291 *regs_stat = *regs_stat & (~mask);
3292 }
3293}
3294
3295/**
3296 * s2io_updt_xpak_counter - Function to update the xpak counters
3297 * @dev : pointer to net_device struct
3298 * Description:
3299 * This function is to upate the status of the xpak counters value
3300 * NONE
3301 */
3302static void s2io_updt_xpak_counter(struct net_device *dev)
3303{
3304 u16 flag = 0x0;
3305 u16 type = 0x0;
3306 u16 val16 = 0x0;
3307 u64 val64 = 0x0;
3308 u64 addr = 0x0;
3309
4cf1653a 3310 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 3311 struct stat_block *stats = sp->mac_control.stats_info;
3312 struct xpakStat *xstats = &stats->xpak_stat;
bd1034f0
AR		 3313
3314 /* Check the communication with the MDIO slave */
40239396 3315 addr = MDIO_CTRL1;
bd1034f0 3316 val64 = 0x0;
40239396 3317 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
d44570e4 3318 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
9e39f7c5
JP		 3319 DBG_PRINT(ERR_DBG,
3320 "ERR: MDIO slave access failed - Returned %llx\n",
3321 (unsigned long long)val64);
bd1034f0
AR		 3322 return;
3323 }
3324
40239396 3325 /* Check for the expected value of control reg 1 */
d44570e4 3326 if (val64 != MDIO_CTRL1_SPEED10G) {
9e39f7c5
JP		 3327 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3328 "Returned: %llx- Expected: 0x%x\n",
40239396 3329 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3330 return;
3331 }
3332
3333 /* Loading the DOM register to MDIO register */
3334 addr = 0xA100;
40239396
BH		 3335 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3336 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3337
3338 /* Reading the Alarm flags */
3339 addr = 0xA070;
3340 val64 = 0x0;
40239396 3341 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3342
3343 flag = CHECKBIT(val64, 0x7);
3344 type = 1;
ffb5df6c
JP		 3345 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3346 &xstats->xpak_regs_stat,
d44570e4 3347 0x0, flag, type);
bd1034f0 3348
d44570e4 3349 if (CHECKBIT(val64, 0x6))
ffb5df6c 3350 xstats->alarm_transceiver_temp_low++;
bd1034f0
AR		 3351
3352 flag = CHECKBIT(val64, 0x3);
3353 type = 2;
ffb5df6c
JP		 3354 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3355 &xstats->xpak_regs_stat,
d44570e4 3356 0x2, flag, type);
bd1034f0 3357
d44570e4 3358 if (CHECKBIT(val64, 0x2))
ffb5df6c 3359 xstats->alarm_laser_bias_current_low++;
bd1034f0
AR		 3360
3361 flag = CHECKBIT(val64, 0x1);
3362 type = 3;
ffb5df6c
JP		 3363 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3364 &xstats->xpak_regs_stat,
d44570e4 3365 0x4, flag, type);
bd1034f0 3366
d44570e4 3367 if (CHECKBIT(val64, 0x0))
ffb5df6c 3368 xstats->alarm_laser_output_power_low++;
bd1034f0
AR		 3369
3370 /* Reading the Warning flags */
3371 addr = 0xA074;
3372 val64 = 0x0;
40239396 3373 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0 3374
d44570e4 3375 if (CHECKBIT(val64, 0x7))
ffb5df6c 3376 xstats->warn_transceiver_temp_high++;
bd1034f0 3377
d44570e4 3378 if (CHECKBIT(val64, 0x6))
ffb5df6c 3379 xstats->warn_transceiver_temp_low++;
bd1034f0 3380
d44570e4 3381 if (CHECKBIT(val64, 0x3))
ffb5df6c 3382 xstats->warn_laser_bias_current_high++;
bd1034f0 3383
d44570e4 3384 if (CHECKBIT(val64, 0x2))
ffb5df6c 3385 xstats->warn_laser_bias_current_low++;
bd1034f0 3386
d44570e4 3387 if (CHECKBIT(val64, 0x1))
ffb5df6c 3388 xstats->warn_laser_output_power_high++;
bd1034f0 3389
d44570e4 3390 if (CHECKBIT(val64, 0x0))
ffb5df6c 3391 xstats->warn_laser_output_power_low++;
bd1034f0
AR		 3392}
3393
20346722 3394/**
1da177e4 3395 * wait_for_cmd_complete - waits for a command to complete.
20346722 3396 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3397 * s2io_nic structure.
20346722
K		 3398 * Description: Function that waits for a command to Write into RMAC
3399 * ADDR DATA registers to be completed and returns either success or
3400 * error depending on whether the command was complete or not.
1da177e4
LT		 3401 * Return value:
3402 * SUCCESS on success and FAILURE on failure.
3403 */
3404
9fc93a41 3405static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
d44570e4 3406 int bit_state)
1da177e4 3407{
9fc93a41 3408 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3409 u64 val64;
3410
9fc93a41
SS		 3411 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3412 return FAILURE;
3413
3414 do {
c92ca04b 3415 val64 = readq(addr);
9fc93a41
SS		 3416 if (bit_state == S2IO_BIT_RESET) {
3417 if (!(val64 & busy_bit)) {
3418 ret = SUCCESS;
3419 break;
3420 }
3421 } else {
2d146eb1 3422 if (val64 & busy_bit) {
9fc93a41
SS		 3423 ret = SUCCESS;
3424 break;
3425 }
1da177e4 3426 }
c92ca04b 3427
d44570e4 3428 if (in_interrupt())
9fc93a41 3429 mdelay(delay);
c92ca04b 3430 else
9fc93a41 3431 msleep(delay);
c92ca04b 3432
9fc93a41
SS		 3433 if (++cnt >= 10)
3434 delay = 50;
3435 } while (cnt < 20);
1da177e4
LT		 3436 return ret;
3437}
19a60522
SS		 3438/*
3439 * check_pci_device_id - Checks if the device id is supported
3440 * @id : device id
3441 * Description: Function to check if the pci device id is supported by driver.
3442 * Return value: Actual device id if supported else PCI_ANY_ID
3443 */
3444static u16 check_pci_device_id(u16 id)
3445{
3446 switch (id) {
3447 case PCI_DEVICE_ID_HERC_WIN:
3448 case PCI_DEVICE_ID_HERC_UNI:
3449 return XFRAME_II_DEVICE;
3450 case PCI_DEVICE_ID_S2IO_UNI:
3451 case PCI_DEVICE_ID_S2IO_WIN:
3452 return XFRAME_I_DEVICE;
3453 default:
3454 return PCI_ANY_ID;
3455 }
3456}
1da177e4 3457
20346722
K		 3458/**
3459 * s2io_reset - Resets the card.
1da177e4
LT		 3460 * @sp : private member of the device structure.
3461 * Description: Function to Reset the card. This function then also
20346722 3462 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3463 * the card reset also resets the configuration space.
3464 * Return value:
3465 * void.
3466 */
3467
d44570e4 3468static void s2io_reset(struct s2io_nic *sp)
1da177e4 3469{
1ee6dd77 3470 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3471 u64 val64;
5e25b9dd 3472 u16 subid, pci_cmd;
19a60522
SS		 3473 int i;
3474 u16 val16;
491976b2
SH		 3475 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3476 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
ffb5df6c
JP		 3477 struct stat_block *stats;
3478 struct swStat *swstats;
491976b2 3479
9e39f7c5 3480 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3a22813a 3481 __func__, pci_name(sp->pdev));
1da177e4 3482
0b1f7ebe 3483 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3484 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3485
1da177e4
LT		 3486 val64 = SW_RESET_ALL;
3487 writeq(val64, &bar0->sw_reset);
d44570e4 3488 if (strstr(sp->product_name, "CX4"))
c92ca04b 3489 msleep(750);
19a60522
SS		 3490 msleep(250);
3491 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3492
19a60522
SS		 3493 /* Restore the PCI state saved during initialization. */
3494 pci_restore_state(sp->pdev);
b8a623bf 3495 pci_save_state(sp->pdev);
19a60522
SS		 3496 pci_read_config_word(sp->pdev, 0x2, &val16);
3497 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3498 break;
3499 msleep(200);
3500 }
1da177e4 3501
d44570e4
JP		 3502 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3503 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
19a60522
SS		 3504
3505 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3506
3507 s2io_init_pci(sp);
1da177e4 3508
20346722
K		 3509 /* Set swapper to enable I/O register access */
3510 s2io_set_swapper(sp);
3511
faa4f796
SH		 3512 /* restore mac_addr entries */
3513 do_s2io_restore_unicast_mc(sp);
3514
cc6e7c44
RA		 3515 /* Restore the MSIX table entries from local variables */
3516 restore_xmsi_data(sp);
3517
5e25b9dd 3518 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3519 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3520 /* Clear "detected parity error" bit */
303bcb4b 3521 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3522
303bcb4b
K		 3523 /* Clearing PCIX Ecc status register */
3524 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3525
303bcb4b 3526 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3527 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3528 }
5e25b9dd 3529
20346722 3530 /* Reset device statistics maintained by OS */
d44570e4 3531 memset(&sp->stats, 0, sizeof(struct net_device_stats));
8a4bdbaa 3532
ffb5df6c
JP		 3533 stats = sp->mac_control.stats_info;
3534 swstats = &stats->sw_stat;
3535
491976b2 3536 /* save link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3537 up_cnt = swstats->link_up_cnt;
3538 down_cnt = swstats->link_down_cnt;
3539 up_time = swstats->link_up_time;
3540 down_time = swstats->link_down_time;
3541 reset_cnt = swstats->soft_reset_cnt;
3542 mem_alloc_cnt = swstats->mem_allocated;
3543 mem_free_cnt = swstats->mem_freed;
3544 watchdog_cnt = swstats->watchdog_timer_cnt;
3545
3546 memset(stats, 0, sizeof(struct stat_block));
3547
491976b2 3548 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3549 swstats->link_up_cnt = up_cnt;
3550 swstats->link_down_cnt = down_cnt;
3551 swstats->link_up_time = up_time;
3552 swstats->link_down_time = down_time;
3553 swstats->soft_reset_cnt = reset_cnt;
3554 swstats->mem_allocated = mem_alloc_cnt;
3555 swstats->mem_freed = mem_free_cnt;
3556 swstats->watchdog_timer_cnt = watchdog_cnt;
20346722 3557
1da177e4
LT		 3558 /* SXE-002: Configure link and activity LED to turn it off */
3559 subid = sp->pdev->subsystem_device;
541ae68f
K		 3560 if (((subid & 0xFF) >= 0x07) &&
3561 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3562 val64 = readq(&bar0->gpio_control);
3563 val64 |= 0x0000800000000000ULL;
3564 writeq(val64, &bar0->gpio_control);
3565 val64 = 0x0411040400000000ULL;
509a2671 3566 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3567 }
3568
541ae68f
K		 3569 /*
3570 * Clear spurious ECC interrupts that would have occured on
3571 * XFRAME II cards after reset.
3572 */
3573 if (sp->device_type == XFRAME_II_DEVICE) {
3574 val64 = readq(&bar0->pcc_err_reg);
3575 writeq(val64, &bar0->pcc_err_reg);
3576 }
3577
f957bcf0 3578 sp->device_enabled_once = false;
1da177e4
LT		 3579}
3580
3581/**
20346722
K		 3582 * s2io_set_swapper - to set the swapper controle on the card
3583 * @sp : private member of the device structure,
1da177e4 3584 * pointer to the s2io_nic structure.
20346722 3585 * Description: Function to set the swapper control on the card
1da177e4
LT		 3586 * correctly depending on the 'endianness' of the system.
3587 * Return value:
3588 * SUCCESS on success and FAILURE on failure.
3589 */
3590
d44570e4 3591static int s2io_set_swapper(struct s2io_nic *sp)
1da177e4
LT		 3592{
3593 struct net_device *dev = sp->dev;
1ee6dd77 3594 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3595 u64 val64, valt, valr;
3596
20346722 3597 /*
1da177e4
LT		 3598 * Set proper endian settings and verify the same by reading
3599 * the PIF Feed-back register.
3600 */
3601
3602 val64 = readq(&bar0->pif_rd_swapper_fb);
3603 if (val64 != 0x0123456789ABCDEFULL) {
3604 int i = 0;
3605 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3606 0x8100008181000081ULL, /* FE=1, SE=0 */
3607 0x4200004242000042ULL, /* FE=0, SE=1 */
3608 0}; /* FE=0, SE=0 */
3609
d44570e4 3610 while (i < 4) {
1da177e4
LT		 3611 writeq(value[i], &bar0->swapper_ctrl);
3612 val64 = readq(&bar0->pif_rd_swapper_fb);
3613 if (val64 == 0x0123456789ABCDEFULL)
3614 break;
3615 i++;
3616 }
3617 if (i == 4) {
9e39f7c5
JP		 3618 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3619 "feedback read %llx\n",
3620 dev->name, (unsigned long long)val64);
1da177e4
LT		 3621 return FAILURE;
3622 }
3623 valr = value[i];
3624 } else {
3625 valr = readq(&bar0->swapper_ctrl);
3626 }
3627
3628 valt = 0x0123456789ABCDEFULL;
3629 writeq(valt, &bar0->xmsi_address);
3630 val64 = readq(&bar0->xmsi_address);
3631
d44570e4 3632 if (val64 != valt) {
1da177e4
LT		 3633 int i = 0;
3634 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3635 0x0081810000818100ULL, /* FE=1, SE=0 */
3636 0x0042420000424200ULL, /* FE=0, SE=1 */
3637 0}; /* FE=0, SE=0 */
3638
d44570e4 3639 while (i < 4) {
1da177e4
LT		 3640 writeq((value[i] | valr), &bar0->swapper_ctrl);
3641 writeq(valt, &bar0->xmsi_address);
3642 val64 = readq(&bar0->xmsi_address);
d44570e4 3643 if (val64 == valt)
1da177e4
LT		 3644 break;
3645 i++;
3646 }
d44570e4 3647 if (i == 4) {
20346722 3648 unsigned long long x = val64;
9e39f7c5
JP		 3649 DBG_PRINT(ERR_DBG,
3650 "Write failed, Xmsi_addr reads:0x%llx\n", x);
1da177e4
LT		 3651 return FAILURE;
3652 }
3653 }
3654 val64 = readq(&bar0->swapper_ctrl);
3655 val64 &= 0xFFFF000000000000ULL;
3656
d44570e4 3657#ifdef __BIG_ENDIAN
20346722
K		 3658 /*
3659 * The device by default set to a big endian format, so a
1da177e4
LT		 3660 * big endian driver need not set anything.
3661 */
3662 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3663 SWAPPER_CTRL_TXP_SE |
3664 SWAPPER_CTRL_TXD_R_FE |
3665 SWAPPER_CTRL_TXD_W_FE |
3666 SWAPPER_CTRL_TXF_R_FE |
3667 SWAPPER_CTRL_RXD_R_FE |
3668 SWAPPER_CTRL_RXD_W_FE |
3669 SWAPPER_CTRL_RXF_W_FE |
3670 SWAPPER_CTRL_XMSI_FE |
3671 SWAPPER_CTRL_STATS_FE |
3672 SWAPPER_CTRL_STATS_SE);
eaae7f72 3673 if (sp->config.intr_type == INTA)
cc6e7c44 3674 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3675 writeq(val64, &bar0->swapper_ctrl);
3676#else
20346722 3677 /*
1da177e4 3678 * Initially we enable all bits to make it accessible by the
20346722 3679 * driver, then we selectively enable only those bits that
1da177e4
LT		 3680 * we want to set.
3681 */
3682 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3683 SWAPPER_CTRL_TXP_SE |
3684 SWAPPER_CTRL_TXD_R_FE |
3685 SWAPPER_CTRL_TXD_R_SE |
3686 SWAPPER_CTRL_TXD_W_FE |
3687 SWAPPER_CTRL_TXD_W_SE |
3688 SWAPPER_CTRL_TXF_R_FE |
3689 SWAPPER_CTRL_RXD_R_FE |
3690 SWAPPER_CTRL_RXD_R_SE |
3691 SWAPPER_CTRL_RXD_W_FE |
3692 SWAPPER_CTRL_RXD_W_SE |
3693 SWAPPER_CTRL_RXF_W_FE |
3694 SWAPPER_CTRL_XMSI_FE |
3695 SWAPPER_CTRL_STATS_FE |
3696 SWAPPER_CTRL_STATS_SE);
eaae7f72 3697 if (sp->config.intr_type == INTA)
cc6e7c44 3698 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3699 writeq(val64, &bar0->swapper_ctrl);
3700#endif
3701 val64 = readq(&bar0->swapper_ctrl);
3702
20346722
K		 3703 /*
3704 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3705 * feedback register.
3706 */
3707 val64 = readq(&bar0->pif_rd_swapper_fb);
3708 if (val64 != 0x0123456789ABCDEFULL) {
3709 /* Endian settings are incorrect, calls for another dekko. */
9e39f7c5
JP		 3710 DBG_PRINT(ERR_DBG,
3711 "%s: Endian settings are wrong, feedback read %llx\n",
3712 dev->name, (unsigned long long)val64);
1da177e4
LT		 3713 return FAILURE;
3714 }
3715
3716 return SUCCESS;
3717}
3718
1ee6dd77 3719static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3720{
1ee6dd77 3721 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3722 u64 val64;
3723 int ret = 0, cnt = 0;
3724
3725 do {
3726 val64 = readq(&bar0->xmsi_access);
b7b5a128 3727 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3728 break;
3729 mdelay(1);
3730 cnt++;
d44570e4 3731 } while (cnt < 5);
cc6e7c44
RA		 3732 if (cnt == 5) {
3733 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3734 ret = 1;
3735 }
3736
3737 return ret;
3738}
3739
1ee6dd77 3740static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3741{
1ee6dd77 3742 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3743 u64 val64;
f61e0a35
SH		 3744 int i, msix_index;
3745
f61e0a35
SH		 3746 if (nic->device_type == XFRAME_I_DEVICE)
3747 return;
cc6e7c44 3748
d44570e4
JP		 3749 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3750 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
cc6e7c44
RA		 3751 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3752 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3753 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3754 writeq(val64, &bar0->xmsi_access);
f61e0a35 3755 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3756 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3757 __func__, msix_index);
cc6e7c44
RA		 3758 continue;
3759 }
3760 }
3761}
3762
1ee6dd77 3763static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3764{
1ee6dd77 3765 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3766 u64 val64, addr, data;
f61e0a35
SH		 3767 int i, msix_index;
3768
3769 if (nic->device_type == XFRAME_I_DEVICE)
3770 return;
cc6e7c44
RA		 3771
3772 /* Store and display */
d44570e4
JP		 3773 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3774 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
f61e0a35 3775 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3776 writeq(val64, &bar0->xmsi_access);
f61e0a35 3777 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3778 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3779 __func__, msix_index);
cc6e7c44
RA		 3780 continue;
3781 }
3782 addr = readq(&bar0->xmsi_address);
3783 data = readq(&bar0->xmsi_data);
3784 if (addr && data) {
3785 nic->msix_info[i].addr = addr;
3786 nic->msix_info[i].data = data;
3787 }
3788 }
3789}
3790
1ee6dd77 3791static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3792{
1ee6dd77 3793 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3794 u64 rx_mat;
cc6e7c44
RA		 3795 u16 msi_control; /* Temp variable */
3796 int ret, i, j, msix_indx = 1;
4f870320 3797 int size;
ffb5df6c
JP		 3798 struct stat_block *stats = nic->mac_control.stats_info;
3799 struct swStat *swstats = &stats->sw_stat;
cc6e7c44 3800
4f870320 3801 size = nic->num_entries * sizeof(struct msix_entry);
44364a03 3802 nic->entries = kzalloc(size, GFP_KERNEL);
bd684e43 3803 if (!nic->entries) {
d44570e4
JP		 3804 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3805 __func__);
ffb5df6c 3806 swstats->mem_alloc_fail_cnt++;
cc6e7c44
RA		 3807 return -ENOMEM;
3808 }
ffb5df6c 3809 swstats->mem_allocated += size;
f61e0a35 3810
4f870320 3811 size = nic->num_entries * sizeof(struct s2io_msix_entry);
44364a03 3812 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
bd684e43 3813 if (!nic->s2io_entries) {
8a4bdbaa 3814 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
d44570e4 3815 __func__);
ffb5df6c 3816 swstats->mem_alloc_fail_cnt++;
cc6e7c44 3817 kfree(nic->entries);
ffb5df6c 3818 swstats->mem_freed
f61e0a35 3819 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3820 return -ENOMEM;
3821 }
ffb5df6c 3822 swstats->mem_allocated += size;
cc6e7c44 3823
ac731ab6
SH		 3824 nic->entries[0].entry = 0;
3825 nic->s2io_entries[0].entry = 0;
3826 nic->s2io_entries[0].in_use = MSIX_FLG;
3827 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3828 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3829
f61e0a35
SH		 3830 for (i = 1; i < nic->num_entries; i++) {
3831 nic->entries[i].entry = ((i - 1) * 8) + 1;
3832 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3833 nic->s2io_entries[i].arg = NULL;
3834 nic->s2io_entries[i].in_use = 0;
3835 }
3836
8a4bdbaa 3837 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3838 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3839 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3840 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3841 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3842 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3843 msix_indx += 8;
cc6e7c44 3844 }
8a4bdbaa 3845 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3846 readq(&bar0->rx_mat);
cc6e7c44 3847
f61e0a35 3848 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3849 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3850 if (ret) {
9e39f7c5 3851 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
cc6e7c44 3852 kfree(nic->entries);
ffb5df6c
JP		 3853 swstats->mem_freed += nic->num_entries *
3854 sizeof(struct msix_entry);
cc6e7c44 3855 kfree(nic->s2io_entries);
ffb5df6c
JP		 3856 swstats->mem_freed += nic->num_entries *
3857 sizeof(struct s2io_msix_entry);
cc6e7c44
RA		 3858 nic->entries = NULL;
3859 nic->s2io_entries = NULL;
3860 return -ENOMEM;
3861 }
3862
3863 /*
3864 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3865 * in the herc NIC. (Temp change, needs to be removed later)
3866 */
3867 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3868 msi_control |= 0x1; /* Enable MSI */
3869 pci_write_config_word(nic->pdev, 0x42, msi_control);
3870
3871 return 0;
3872}
3873
8abc4d5b 3874/* Handle software interrupt used during MSI(X) test */
33390a70 3875static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3876{
3877 struct s2io_nic *sp = dev_id;
3878
3879 sp->msi_detected = 1;
3880 wake_up(&sp->msi_wait);
3881
3882 return IRQ_HANDLED;
3883}
3884
3885/* Test interrupt path by forcing a a software IRQ */
33390a70 3886static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3887{
3888 struct pci_dev *pdev = sp->pdev;
3889 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3890 int err;
3891 u64 val64, saved64;
3892
3893 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
d44570e4 3894 sp->name, sp);
8abc4d5b
SS		 3895 if (err) {
3896 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
d44570e4 3897 sp->dev->name, pci_name(pdev), pdev->irq);
8abc4d5b
SS		 3898 return err;
3899 }
3900
d44570e4 3901 init_waitqueue_head(&sp->msi_wait);
8abc4d5b
SS		 3902 sp->msi_detected = 0;
3903
3904 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3905 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3906 val64 |= SCHED_INT_CTRL_TIMER_EN;
3907 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3908 writeq(val64, &bar0->scheduled_int_ctrl);
3909
3910 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3911
3912 if (!sp->msi_detected) {
3913 /* MSI(X) test failed, go back to INTx mode */
2450022a 3914 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
9e39f7c5
JP		 3915 "using MSI(X) during test\n",
3916 sp->dev->name, pci_name(pdev));
8abc4d5b
SS		 3917
3918 err = -EOPNOTSUPP;
3919 }
3920
3921 free_irq(sp->entries[1].vector, sp);
3922
3923 writeq(saved64, &bar0->scheduled_int_ctrl);
3924
3925 return err;
3926}
18b2b7bd
SH		 3927
3928static void remove_msix_isr(struct s2io_nic *sp)
3929{
3930 int i;
3931 u16 msi_control;
3932
f61e0a35 3933 for (i = 0; i < sp->num_entries; i++) {
d44570e4 3934 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
18b2b7bd
SH		 3935 int vector = sp->entries[i].vector;
3936 void *arg = sp->s2io_entries[i].arg;
3937 free_irq(vector, arg);
3938 }
3939 }
3940
3941 kfree(sp->entries);
3942 kfree(sp->s2io_entries);
3943 sp->entries = NULL;
3944 sp->s2io_entries = NULL;
3945
3946 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3947 msi_control &= 0xFFFE; /* Disable MSI */
3948 pci_write_config_word(sp->pdev, 0x42, msi_control);
3949
3950 pci_disable_msix(sp->pdev);
3951}
3952
3953static void remove_inta_isr(struct s2io_nic *sp)
3954{
3955 struct net_device *dev = sp->dev;
3956
3957 free_irq(sp->pdev->irq, dev);
3958}
3959
1da177e4
LT		 3960/* ********************************************************* *
3961 * Functions defined below concern the OS part of the driver *
3962 * ********************************************************* */
3963
20346722 3964/**
1da177e4
LT		 3965 * s2io_open - open entry point of the driver
3966 * @dev : pointer to the device structure.
3967 * Description:
3968 * This function is the open entry point of the driver. It mainly calls a
3969 * function to allocate Rx buffers and inserts them into the buffer
20346722 3970 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3971 * Return value:
3972 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3973 * file on failure.
3974 */
3975
ac1f60db 3976static int s2io_open(struct net_device *dev)
1da177e4 3977{
4cf1653a 3978 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 3979 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 3980 int err = 0;
3981
20346722
K		 3982 /*
3983 * Make sure you have link off by default every time
1da177e4
LT		 3984 * Nic is initialized
3985 */
3986 netif_carrier_off(dev);
0b1f7ebe 3987 sp->last_link_state = 0;
1da177e4
LT		 3988
3989 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3990 err = s2io_card_up(sp);
3991 if (err) {
1da177e4
LT		 3992 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3993 dev->name);
e6a8fee2 3994 goto hw_init_failed;
1da177e4
LT		 3995 }
3996
2fd37688 3997 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 3998 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3999 s2io_card_down(sp);
20346722 4000 err = -ENODEV;
e6a8fee2 4001 goto hw_init_failed;
1da177e4 4002 }
3a3d5756 4003 s2io_start_all_tx_queue(sp);
1da177e4 4004 return 0;
20346722 4005
20346722 4006hw_init_failed:
eaae7f72 4007 if (sp->config.intr_type == MSI_X) {
491976b2 4008 if (sp->entries) {
cc6e7c44 4009 kfree(sp->entries);
ffb5df6c
JP		 4010 swstats->mem_freed += sp->num_entries *
4011 sizeof(struct msix_entry);
491976b2
SH		 4012 }
4013 if (sp->s2io_entries) {
cc6e7c44 4014 kfree(sp->s2io_entries);
ffb5df6c
JP		 4015 swstats->mem_freed += sp->num_entries *
4016 sizeof(struct s2io_msix_entry);
491976b2 4017 }
cc6e7c44 4018 }
20346722 4019 return err;
1da177e4
LT		 4020}
4021
4022/**
4023 * s2io_close -close entry point of the driver
4024 * @dev : device pointer.
4025 * Description:
4026 * This is the stop entry point of the driver. It needs to undo exactly
4027 * whatever was done by the open entry point,thus it's usually referred to
4028 * as the close function.Among other things this function mainly stops the
4029 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4030 * Return value:
4031 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4032 * file on failure.
4033 */
4034
ac1f60db 4035static int s2io_close(struct net_device *dev)
1da177e4 4036{
4cf1653a 4037 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4038 struct config_param *config = &sp->config;
4039 u64 tmp64;
4040 int offset;
cc6e7c44 4041
9f74ffde 4042 /* Return if the device is already closed *
d44570e4
JP		 4043 * Can happen when s2io_card_up failed in change_mtu *
4044 */
9f74ffde
SH		 4045 if (!is_s2io_card_up(sp))
4046 return 0;
4047
3a3d5756 4048 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4049 /* delete all populated mac entries */
4050 for (offset = 1; offset < config->max_mc_addr; offset++) {
4051 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4052 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4053 do_s2io_delete_unicast_mc(sp, tmp64);
4054 }
4055
e6a8fee2 4056 s2io_card_down(sp);
cc6e7c44 4057
1da177e4
LT		 4058 return 0;
4059}
4060
4061/**
4062 * s2io_xmit - Tx entry point of te driver
4063 * @skb : the socket buffer containing the Tx data.
4064 * @dev : device pointer.
4065 * Description :
4066 * This function is the Tx entry point of the driver. S2IO NIC supports
4067 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4068 * NOTE: when device cant queue the pkt,just the trans_start variable will
4069 * not be upadted.
4070 * Return value:
4071 * 0 on success & 1 on failure.
4072 */
4073
61357325 4074static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4075{
4cf1653a 4076 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4077 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4078 register u64 val64;
1ee6dd77
RB		 4079 struct TxD *txdp;
4080 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4081 unsigned long flags = 0;
be3a6b02 4082 u16 vlan_tag = 0;
2fda096d 4083 struct fifo_info *fifo = NULL;
6cfc482b 4084 int do_spin_lock = 1;
75c30b13 4085 int offload_type;
6cfc482b 4086 int enable_per_list_interrupt = 0;
ffb5df6c
JP		 4087 struct config_param *config = &sp->config;
4088 struct mac_info *mac_control = &sp->mac_control;
4089 struct stat_block *stats = mac_control->stats_info;
4090 struct swStat *swstats = &stats->sw_stat;
1da177e4 4091
20346722 4092 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4093
4094 if (unlikely(skb->len <= 0)) {
9e39f7c5 4095 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
491976b2 4096 dev_kfree_skb_any(skb);
6ed10654 4097 return NETDEV_TX_OK;
2fda096d 4098 }
491976b2 4099
92b84437 4100 if (!is_s2io_card_up(sp)) {
20346722 4101 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4102 dev->name);
20346722 4103 dev_kfree_skb(skb);
6ed10654 4104 return NETDEV_TX_OK;
1da177e4
LT		 4105 }
4106
4107 queue = 0;
3a3d5756 4108 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4109 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4110 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4111 if (skb->protocol == htons(ETH_P_IP)) {
4112 struct iphdr *ip;
4113 struct tcphdr *th;
4114 ip = ip_hdr(skb);
4115
4116 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4117 th = (struct tcphdr *)(((unsigned char *)ip) +
d44570e4 4118 ip->ihl*4);
6cfc482b
SH		 4119
4120 if (ip->protocol == IPPROTO_TCP) {
4121 queue_len = sp->total_tcp_fifos;
4122 queue = (ntohs(th->source) +
d44570e4
JP		 4123 ntohs(th->dest)) &
4124 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4125 if (queue >= queue_len)
4126 queue = queue_len - 1;
4127 } else if (ip->protocol == IPPROTO_UDP) {
4128 queue_len = sp->total_udp_fifos;
4129 queue = (ntohs(th->source) +
d44570e4
JP		 4130 ntohs(th->dest)) &
4131 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4132 if (queue >= queue_len)
4133 queue = queue_len - 1;
4134 queue += sp->udp_fifo_idx;
4135 if (skb->len > 1024)
4136 enable_per_list_interrupt = 1;
4137 do_spin_lock = 0;
4138 }
4139 }
4140 }
4141 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4142 /* get fifo number based on skb->priority value */
4143 queue = config->fifo_mapping
d44570e4 4144 [skb->priority & (MAX_TX_FIFOS - 1)];
6cfc482b 4145 fifo = &mac_control->fifos[queue];
3a3d5756 4146
6cfc482b
SH		 4147 if (do_spin_lock)
4148 spin_lock_irqsave(&fifo->tx_lock, flags);
4149 else {
4150 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4151 return NETDEV_TX_LOCKED;
4152 }
be3a6b02 4153
3a3d5756
SH		 4154 if (sp->config.multiq) {
4155 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4156 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4157 return NETDEV_TX_BUSY;
4158 }
b19fa1fa 4159 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4160 if (netif_queue_stopped(dev)) {
4161 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4162 return NETDEV_TX_BUSY;
4163 }
4164 }
4165
d44570e4
JP		 4166 put_off = (u16)fifo->tx_curr_put_info.offset;
4167 get_off = (u16)fifo->tx_curr_get_info.offset;
4168 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
20346722 4169
2fda096d 4170 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4171 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4172 if (txdp->Host_Control ||
d44570e4 4173 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4174 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4175 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4176 dev_kfree_skb(skb);
2fda096d 4177 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4178 return NETDEV_TX_OK;
1da177e4 4179 }
0b1f7ebe 4180
75c30b13 4181 offload_type = s2io_offload_type(skb);
75c30b13 4182 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4183 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4184 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4185 }
84fa7933 4186 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d44570e4
JP		 4187 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4188 TXD_TX_CKO_TCP_EN |
4189 TXD_TX_CKO_UDP_EN);
1da177e4 4190 }
fed5eccd
AR		 4191 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4192 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4193 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4194 if (enable_per_list_interrupt)
4195 if (put_off & (queue_len >> 5))
4196 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4197 if (vlan_tag) {
be3a6b02
K		 4198 txdp->Control_2 |= TXD_VLAN_ENABLE;
4199 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4200 }
4201
e743d313 4202 frg_len = skb_headlen(skb);
75c30b13 4203 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4204 int ufo_size;
4205
75c30b13 4206 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4207 ufo_size &= ~7;
4208 txdp->Control_1 |= TXD_UFO_EN;
4209 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4210 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4211#ifdef __BIG_ENDIAN
3459feb8 4212 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4213 fifo->ufo_in_band_v[put_off] =
d44570e4 4214 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4215#else
2fda096d 4216 fifo->ufo_in_band_v[put_off] =
d44570e4 4217 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4218#endif
2fda096d 4219 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4220 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
d44570e4
JP		 4221 fifo->ufo_in_band_v,
4222 sizeof(u64),
4223 PCI_DMA_TODEVICE);
8d8bb39b 4224 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4225 goto pci_map_failed;
fed5eccd 4226 txdp++;
fed5eccd 4227 }
1da177e4 4228
d44570e4
JP		 4229 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4230 frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4231 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4232 goto pci_map_failed;
4233
d44570e4 4234 txdp->Host_Control = (unsigned long)skb;
fed5eccd 4235 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4236 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4237 txdp->Control_1 |= TXD_UFO_EN;
4238
4239 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4240 /* For fragmented SKB. */
4241 for (i = 0; i < frg_cnt; i++) {
4242 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4243 /* A '0' length fragment will be ignored */
4244 if (!frag->size)
4245 continue;
1da177e4 4246 txdp++;
d44570e4
JP		 4247 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4248 frag->page_offset,
4249 frag->size,
4250 PCI_DMA_TODEVICE);
efd51b5c 4251 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4252 if (offload_type == SKB_GSO_UDP)
fed5eccd 4253 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4254 }
4255 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4256
75c30b13 4257 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4258 frg_cnt++; /* as Txd0 was used for inband header */
4259
1da177e4 4260 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4261 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4262 writeq(val64, &tx_fifo->TxDL_Pointer);
4263
4264 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4265 TX_FIFO_LAST_LIST);
75c30b13 4266 if (offload_type)
fed5eccd 4267 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4268
1da177e4
LT		 4269 writeq(val64, &tx_fifo->List_Control);
4270
303bcb4b
K		 4271 mmiowb();
4272
1da177e4 4273 put_off++;
2fda096d 4274 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4275 put_off = 0;
2fda096d 4276 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4277
4278 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4279 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
ffb5df6c 4280 swstats->fifo_full_cnt++;
1da177e4
LT		 4281 DBG_PRINT(TX_DBG,
4282 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4283 put_off, get_off);
3a3d5756 4284 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4285 }
ffb5df6c 4286 swstats->mem_allocated += skb->truesize;
2fda096d 4287 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4288
f6f4bfa3
SH		 4289 if (sp->config.intr_type == MSI_X)
4290 tx_intr_handler(fifo);
4291
6ed10654 4292 return NETDEV_TX_OK;
ffb5df6c 4293
491abf25 4294pci_map_failed:
ffb5df6c 4295 swstats->pci_map_fail_cnt++;
3a3d5756 4296 s2io_stop_tx_queue(sp, fifo->fifo_no);
ffb5df6c 4297 swstats->mem_freed += skb->truesize;
491abf25 4298 dev_kfree_skb(skb);
2fda096d 4299 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4300 return NETDEV_TX_OK;
1da177e4
LT		 4301}
4302
25fff88e
K		 4303static void
4304s2io_alarm_handle(unsigned long data)
4305{
1ee6dd77 4306 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4307 struct net_device *dev = sp->dev;
25fff88e 4308
8116f3cf 4309 s2io_handle_errors(dev);
25fff88e
K		 4310 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4311}
4312
7d12e780 4313static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4314{
1ee6dd77
RB		 4315 struct ring_info *ring = (struct ring_info *)dev_id;
4316 struct s2io_nic *sp = ring->nic;
f61e0a35 4317 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4318
f61e0a35 4319 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4320 return IRQ_HANDLED;
92b84437 4321
f61e0a35 4322 if (sp->config.napi) {
1a79d1c3
AV		 4323 u8 __iomem *addr = NULL;
4324 u8 val8 = 0;
f61e0a35 4325
1a79d1c3 4326 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4327 addr += (7 - ring->ring_no);
4328 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4329 writeb(val8, addr);
4330 val8 = readb(addr);
288379f0 4331 napi_schedule(&ring->napi);
f61e0a35
SH		 4332 } else {
4333 rx_intr_handler(ring, 0);
8d8bb39b 4334 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4335 }
7d3d0439 4336
cc6e7c44
RA		 4337 return IRQ_HANDLED;
4338}
4339
7d12e780 4340static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4341{
ac731ab6
SH		 4342 int i;
4343 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4344 struct s2io_nic *sp = fifos->nic;
4345 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4346 struct config_param *config = &sp->config;
4347 u64 reason;
cc6e7c44 4348
ac731ab6
SH		 4349 if (unlikely(!is_s2io_card_up(sp)))
4350 return IRQ_NONE;
4351
4352 reason = readq(&bar0->general_int_status);
4353 if (unlikely(reason == S2IO_MINUS_ONE))
4354 /* Nothing much can be done. Get out */
92b84437 4355 return IRQ_HANDLED;
92b84437 4356
01e16faa
SH		 4357 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4358 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4359
01e16faa
SH		 4360 if (reason & GEN_INTR_TXPIC)
4361 s2io_txpic_intr_handle(sp);
ac731ab6 4362
01e16faa
SH		 4363 if (reason & GEN_INTR_TXTRAFFIC)
4364 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4365
01e16faa
SH		 4366 for (i = 0; i < config->tx_fifo_num; i++)
4367 tx_intr_handler(&fifos[i]);
ac731ab6 4368
01e16faa
SH		 4369 writeq(sp->general_int_mask, &bar0->general_int_mask);
4370 readl(&bar0->general_int_status);
4371 return IRQ_HANDLED;
4372 }
4373 /* The interrupt was not raised by us */
4374 return IRQ_NONE;
cc6e7c44 4375}
ac731ab6 4376
1ee6dd77 4377static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4378{
1ee6dd77 4379 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4380 u64 val64;
4381
4382 val64 = readq(&bar0->pic_int_status);
4383 if (val64 & PIC_INT_GPIO) {
4384 val64 = readq(&bar0->gpio_int_reg);
4385 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4386 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4387 /*
4388 * This is unstable state so clear both up/down
4389 * interrupt and adapter to re-evaluate the link state.
4390 */
d44570e4 4391 val64 |= GPIO_INT_REG_LINK_DOWN;
a371a07d
K		 4392 val64 |= GPIO_INT_REG_LINK_UP;
4393 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4394 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4395 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4396 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4397 writeq(val64, &bar0->gpio_int_mask);
d44570e4 4398 } else if (val64 & GPIO_INT_REG_LINK_UP) {
c92ca04b 4399 val64 = readq(&bar0->adapter_status);
d44570e4 4400 /* Enable Adapter */
19a60522
SS		 4401 val64 = readq(&bar0->adapter_control);
4402 val64 |= ADAPTER_CNTL_EN;
4403 writeq(val64, &bar0->adapter_control);
4404 val64 |= ADAPTER_LED_ON;
4405 writeq(val64, &bar0->adapter_control);
4406 if (!sp->device_enabled_once)
4407 sp->device_enabled_once = 1;
c92ca04b 4408
19a60522
SS		 4409 s2io_link(sp, LINK_UP);
4410 /*
4411 * unmask link down interrupt and mask link-up
4412 * intr
4413 */
4414 val64 = readq(&bar0->gpio_int_mask);
4415 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4416 val64 |= GPIO_INT_MASK_LINK_UP;
4417 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4418
d44570e4 4419 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
c92ca04b 4420 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4421 s2io_link(sp, LINK_DOWN);
4422 /* Link is down so unmaks link up interrupt */
4423 val64 = readq(&bar0->gpio_int_mask);
4424 val64 &= ~GPIO_INT_MASK_LINK_UP;
4425 val64 |= GPIO_INT_MASK_LINK_DOWN;
4426 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4427
4428 /* turn off LED */
4429 val64 = readq(&bar0->adapter_control);
d44570e4 4430 val64 = val64 & (~ADAPTER_LED_ON);
ac1f90d6 4431 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4432 }
4433 }
c92ca04b 4434 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4435}
4436
8116f3cf
SS		 4437/**
4438 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4439 * @value: alarm bits
4440 * @addr: address value
4441 * @cnt: counter variable
4442 * Description: Check for alarm and increment the counter
4443 * Return Value:
4444 * 1 - if alarm bit set
4445 * 0 - if alarm bit is not set
4446 */
d44570e4
JP		 4447static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4448 unsigned long long *cnt)
8116f3cf
SS		 4449{
4450 u64 val64;
4451 val64 = readq(addr);
d44570e4 4452 if (val64 & value) {
8116f3cf
SS		 4453 writeq(val64, addr);
4454 (*cnt)++;
4455 return 1;
4456 }
4457 return 0;
4458
4459}
4460
4461/**
4462 * s2io_handle_errors - Xframe error indication handler
4463 * @nic: device private variable
4464 * Description: Handle alarms such as loss of link, single or
4465 * double ECC errors, critical and serious errors.
4466 * Return Value:
4467 * NONE
4468 */
d44570e4 4469static void s2io_handle_errors(void *dev_id)
8116f3cf 4470{
d44570e4 4471 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4472 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf 4473 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d44570e4 4474 u64 temp64 = 0, val64 = 0;
8116f3cf
SS		 4475 int i = 0;
4476
4477 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4478 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4479
92b84437 4480 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4481 return;
4482
4483 if (pci_channel_offline(sp->pdev))
4484 return;
4485
4486 memset(&sw_stat->ring_full_cnt, 0,
d44570e4 4487 sizeof(sw_stat->ring_full_cnt));
8116f3cf
SS		 4488
4489 /* Handling the XPAK counters update */
d44570e4 4490 if (stats->xpak_timer_count < 72000) {
8116f3cf
SS		 4491 /* waiting for an hour */
4492 stats->xpak_timer_count++;
4493 } else {
4494 s2io_updt_xpak_counter(dev);
4495 /* reset the count to zero */
4496 stats->xpak_timer_count = 0;
4497 }
4498
4499 /* Handling link status change error Intr */
4500 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4501 val64 = readq(&bar0->mac_rmac_err_reg);
4502 writeq(val64, &bar0->mac_rmac_err_reg);
4503 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4504 schedule_work(&sp->set_link_task);
4505 }
4506
4507 /* In case of a serious error, the device will be Reset. */
4508 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
d44570e4 4509 &sw_stat->serious_err_cnt))
8116f3cf
SS		 4510 goto reset;
4511
4512 /* Check for data parity error */
4513 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
d44570e4 4514 &sw_stat->parity_err_cnt))
8116f3cf
SS		 4515 goto reset;
4516
4517 /* Check for ring full counter */
4518 if (sp->device_type == XFRAME_II_DEVICE) {
4519 val64 = readq(&bar0->ring_bump_counter1);
d44570e4
JP		 4520 for (i = 0; i < 4; i++) {
4521 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf
SS		 4522 temp64 >>= 64 - ((i+1)*16);
4523 sw_stat->ring_full_cnt[i] += temp64;
4524 }
4525
4526 val64 = readq(&bar0->ring_bump_counter2);
d44570e4
JP		 4527 for (i = 0; i < 4; i++) {
4528 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf 4529 temp64 >>= 64 - ((i+1)*16);
d44570e4 4530 sw_stat->ring_full_cnt[i+4] += temp64;
8116f3cf
SS		 4531 }
4532 }
4533
4534 val64 = readq(&bar0->txdma_int_status);
4535 /*check for pfc_err*/
4536 if (val64 & TXDMA_PFC_INT) {
d44570e4
JP		 4537 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4538 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4539 PFC_PCIX_ERR,
4540 &bar0->pfc_err_reg,
4541 &sw_stat->pfc_err_cnt))
8116f3cf 4542 goto reset;
d44570e4
JP		 4543 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4544 &bar0->pfc_err_reg,
4545 &sw_stat->pfc_err_cnt);
8116f3cf
SS		 4546 }
4547
4548 /*check for tda_err*/
4549 if (val64 & TXDMA_TDA_INT) {
d44570e4
JP		 4550 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4551 TDA_SM0_ERR_ALARM |
4552 TDA_SM1_ERR_ALARM,
4553 &bar0->tda_err_reg,
4554 &sw_stat->tda_err_cnt))
8116f3cf
SS		 4555 goto reset;
4556 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
d44570e4
JP		 4557 &bar0->tda_err_reg,
4558 &sw_stat->tda_err_cnt);
8116f3cf
SS		 4559 }
4560 /*check for pcc_err*/
4561 if (val64 & TXDMA_PCC_INT) {
d44570e4
JP		 4562 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4563 PCC_N_SERR | PCC_6_COF_OV_ERR |
4564 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4565 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4566 PCC_TXB_ECC_DB_ERR,
4567 &bar0->pcc_err_reg,
4568 &sw_stat->pcc_err_cnt))
8116f3cf
SS		 4569 goto reset;
4570 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
d44570e4
JP		 4571 &bar0->pcc_err_reg,
4572 &sw_stat->pcc_err_cnt);
8116f3cf
SS		 4573 }
4574
4575 /*check for tti_err*/
4576 if (val64 & TXDMA_TTI_INT) {
d44570e4
JP		 4577 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4578 &bar0->tti_err_reg,
4579 &sw_stat->tti_err_cnt))
8116f3cf
SS		 4580 goto reset;
4581 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
d44570e4
JP		 4582 &bar0->tti_err_reg,
4583 &sw_stat->tti_err_cnt);
8116f3cf
SS		 4584 }
4585
4586 /*check for lso_err*/
4587 if (val64 & TXDMA_LSO_INT) {
d44570e4
JP		 4588 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4589 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4590 &bar0->lso_err_reg,
4591 &sw_stat->lso_err_cnt))
8116f3cf
SS		 4592 goto reset;
4593 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
d44570e4
JP		 4594 &bar0->lso_err_reg,
4595 &sw_stat->lso_err_cnt);
8116f3cf
SS		 4596 }
4597
4598 /*check for tpa_err*/
4599 if (val64 & TXDMA_TPA_INT) {
d44570e4
JP		 4600 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4601 &bar0->tpa_err_reg,
4602 &sw_stat->tpa_err_cnt))
8116f3cf 4603 goto reset;
d44570e4
JP		 4604 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4605 &bar0->tpa_err_reg,
4606 &sw_stat->tpa_err_cnt);
8116f3cf
SS		 4607 }
4608
4609 /*check for sm_err*/
4610 if (val64 & TXDMA_SM_INT) {
d44570e4
JP		 4611 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4612 &bar0->sm_err_reg,
4613 &sw_stat->sm_err_cnt))
8116f3cf
SS		 4614 goto reset;
4615 }
4616
4617 val64 = readq(&bar0->mac_int_status);
4618 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4619 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
d44570e4
JP		 4620 &bar0->mac_tmac_err_reg,
4621 &sw_stat->mac_tmac_err_cnt))
8116f3cf 4622 goto reset;
d44570e4
JP		 4623 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4624 TMAC_DESC_ECC_SG_ERR |
4625 TMAC_DESC_ECC_DB_ERR,
4626 &bar0->mac_tmac_err_reg,
4627 &sw_stat->mac_tmac_err_cnt);
8116f3cf
SS		 4628 }
4629
4630 val64 = readq(&bar0->xgxs_int_status);
4631 if (val64 & XGXS_INT_STATUS_TXGXS) {
4632 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
d44570e4
JP		 4633 &bar0->xgxs_txgxs_err_reg,
4634 &sw_stat->xgxs_txgxs_err_cnt))
8116f3cf
SS		 4635 goto reset;
4636 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
d44570e4
JP		 4637 &bar0->xgxs_txgxs_err_reg,
4638 &sw_stat->xgxs_txgxs_err_cnt);
8116f3cf
SS		 4639 }
4640
4641 val64 = readq(&bar0->rxdma_int_status);
4642 if (val64 & RXDMA_INT_RC_INT_M) {
d44570e4
JP		 4643 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4644 RC_FTC_ECC_DB_ERR |
4645 RC_PRCn_SM_ERR_ALARM |
4646 RC_FTC_SM_ERR_ALARM,
4647 &bar0->rc_err_reg,
4648 &sw_stat->rc_err_cnt))
8116f3cf 4649 goto reset;
d44570e4
JP		 4650 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4651 RC_FTC_ECC_SG_ERR |
4652 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4653 &sw_stat->rc_err_cnt);
4654 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4655 PRC_PCI_AB_WR_Rn |
4656 PRC_PCI_AB_F_WR_Rn,
4657 &bar0->prc_pcix_err_reg,
4658 &sw_stat->prc_pcix_err_cnt))
8116f3cf 4659 goto reset;
d44570e4
JP		 4660 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4661 PRC_PCI_DP_WR_Rn |
4662 PRC_PCI_DP_F_WR_Rn,
4663 &bar0->prc_pcix_err_reg,
4664 &sw_stat->prc_pcix_err_cnt);
8116f3cf
SS		 4665 }
4666
4667 if (val64 & RXDMA_INT_RPA_INT_M) {
4668 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
d44570e4
JP		 4669 &bar0->rpa_err_reg,
4670 &sw_stat->rpa_err_cnt))
8116f3cf
SS		 4671 goto reset;
4672 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
d44570e4
JP		 4673 &bar0->rpa_err_reg,
4674 &sw_stat->rpa_err_cnt);
8116f3cf
SS		 4675 }
4676
4677 if (val64 & RXDMA_INT_RDA_INT_M) {
d44570e4
JP		 4678 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4679 RDA_FRM_ECC_DB_N_AERR |
4680 RDA_SM1_ERR_ALARM |
4681 RDA_SM0_ERR_ALARM |
4682 RDA_RXD_ECC_DB_SERR,
4683 &bar0->rda_err_reg,
4684 &sw_stat->rda_err_cnt))
8116f3cf 4685 goto reset;
d44570e4
JP		 4686 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4687 RDA_FRM_ECC_SG_ERR |
4688 RDA_MISC_ERR |
4689 RDA_PCIX_ERR,
4690 &bar0->rda_err_reg,
4691 &sw_stat->rda_err_cnt);
8116f3cf
SS		 4692 }
4693
4694 if (val64 & RXDMA_INT_RTI_INT_M) {
d44570e4
JP		 4695 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4696 &bar0->rti_err_reg,
4697 &sw_stat->rti_err_cnt))
8116f3cf
SS		 4698 goto reset;
4699 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
d44570e4
JP		 4700 &bar0->rti_err_reg,
4701 &sw_stat->rti_err_cnt);
8116f3cf
SS		 4702 }
4703
4704 val64 = readq(&bar0->mac_int_status);
4705 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4706 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
d44570e4
JP		 4707 &bar0->mac_rmac_err_reg,
4708 &sw_stat->mac_rmac_err_cnt))
8116f3cf 4709 goto reset;
d44570e4
JP		 4710 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4711 RMAC_SINGLE_ECC_ERR |
4712 RMAC_DOUBLE_ECC_ERR,
4713 &bar0->mac_rmac_err_reg,
4714 &sw_stat->mac_rmac_err_cnt);
8116f3cf
SS		 4715 }
4716
4717 val64 = readq(&bar0->xgxs_int_status);
4718 if (val64 & XGXS_INT_STATUS_RXGXS) {
4719 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
d44570e4
JP		 4720 &bar0->xgxs_rxgxs_err_reg,
4721 &sw_stat->xgxs_rxgxs_err_cnt))
8116f3cf
SS		 4722 goto reset;
4723 }
4724
4725 val64 = readq(&bar0->mc_int_status);
d44570e4
JP		 4726 if (val64 & MC_INT_STATUS_MC_INT) {
4727 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4728 &bar0->mc_err_reg,
4729 &sw_stat->mc_err_cnt))
8116f3cf
SS		 4730 goto reset;
4731
4732 /* Handling Ecc errors */
4733 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4734 writeq(val64, &bar0->mc_err_reg);
4735 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4736 sw_stat->double_ecc_errs++;
4737 if (sp->device_type != XFRAME_II_DEVICE) {
4738 /*
4739 * Reset XframeI only if critical error
4740 */
4741 if (val64 &
d44570e4
JP		 4742 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4743 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4744 goto reset;
4745 }
8116f3cf
SS		 4746 } else
4747 sw_stat->single_ecc_errs++;
4748 }
4749 }
4750 return;
4751
4752reset:
3a3d5756 4753 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4754 schedule_work(&sp->rst_timer_task);
4755 sw_stat->soft_reset_cnt++;
8116f3cf
SS		 4756}
4757
1da177e4
LT		 4758/**
4759 * s2io_isr - ISR handler of the device .
4760 * @irq: the irq of the device.
4761 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4762 * Description: This function is the ISR handler of the device. It
4763 * identifies the reason for the interrupt and calls the relevant
4764 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4765 * recv buffers, if their numbers are below the panic value which is
4766 * presently set to 25% of the original number of rcv buffers allocated.
4767 * Return value:
20346722 4768 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4769 * IRQ_NONE: will be returned if interrupt is not from our device
4770 */
7d12e780 4771static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4 4772{
d44570e4 4773 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4774 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4775 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4776 int i;
19a60522 4777 u64 reason = 0;
1ee6dd77 4778 struct mac_info *mac_control;
1da177e4
LT		 4779 struct config_param *config;
4780
d796fdb7
LV		 4781 /* Pretend we handled any irq's from a disconnected card */
4782 if (pci_channel_offline(sp->pdev))
4783 return IRQ_NONE;
4784
596c5c97 4785 if (!is_s2io_card_up(sp))
92b84437 4786 return IRQ_NONE;
92b84437 4787
1da177e4 4788 config = &sp->config;
ffb5df6c 4789 mac_control = &sp->mac_control;
1da177e4 4790
20346722 4791 /*
1da177e4
LT		 4792 * Identify the cause for interrupt and call the appropriate
4793 * interrupt handler. Causes for the interrupt could be;
4794 * 1. Rx of packet.
4795 * 2. Tx complete.
4796 * 3. Link down.
1da177e4
LT		 4797 */
4798 reason = readq(&bar0->general_int_status);
4799
d44570e4
JP		 4800 if (unlikely(reason == S2IO_MINUS_ONE))
4801 return IRQ_HANDLED; /* Nothing much can be done. Get out */
5d3213cc 4802
d44570e4
JP		 4803 if (reason &
4804 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
596c5c97
SS		 4805 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4806
4807 if (config->napi) {
4808 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4809 napi_schedule(&sp->napi);
f61e0a35
SH		 4810 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4811 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4812 readl(&bar0->rx_traffic_int);
db874e65 4813 }
596c5c97
SS		 4814 } else {
4815 /*
4816 * rx_traffic_int reg is an R1 register, writing all 1's
4817 * will ensure that the actual interrupt causing bit
4818 * get's cleared and hence a read can be avoided.
4819 */
4820 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4821 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4822
13d866a9
JP		 4823 for (i = 0; i < config->rx_ring_num; i++) {
4824 struct ring_info *ring = &mac_control->rings[i];
4825
4826 rx_intr_handler(ring, 0);
4827 }
db874e65 4828 }
596c5c97 4829
db874e65 4830 /*
596c5c97 4831 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4832 * will ensure that the actual interrupt causing bit get's
4833 * cleared and hence a read can be avoided.
4834 */
596c5c97
SS		 4835 if (reason & GEN_INTR_TXTRAFFIC)
4836 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4837
596c5c97
SS		 4838 for (i = 0; i < config->tx_fifo_num; i++)
4839 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4840
596c5c97
SS		 4841 if (reason & GEN_INTR_TXPIC)
4842 s2io_txpic_intr_handle(sp);
fe113638 4843
596c5c97
SS		 4844 /*
4845 * Reallocate the buffers from the interrupt handler itself.
4846 */
4847 if (!config->napi) {
13d866a9
JP		 4848 for (i = 0; i < config->rx_ring_num; i++) {
4849 struct ring_info *ring = &mac_control->rings[i];
4850
4851 s2io_chk_rx_buffers(sp, ring);
4852 }
596c5c97
SS		 4853 }
4854 writeq(sp->general_int_mask, &bar0->general_int_mask);
4855 readl(&bar0->general_int_status);
20346722 4856
596c5c97 4857 return IRQ_HANDLED;
db874e65 4858
d44570e4 4859 } else if (!reason) {
596c5c97
SS		 4860 /* The interrupt was not raised by us */
4861 return IRQ_NONE;
4862 }
db874e65 4863
1da177e4
LT		 4864 return IRQ_HANDLED;
4865}
4866
7ba013ac
K		 4867/**
4868 * s2io_updt_stats -
4869 */
1ee6dd77 4870static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4871{
1ee6dd77 4872 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4873 u64 val64;
4874 int cnt = 0;
4875
92b84437 4876 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4877 /* Apprx 30us on a 133 MHz bus */
4878 val64 = SET_UPDT_CLICKS(10) |
4879 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4880 writeq(val64, &bar0->stat_cfg);
4881 do {
4882 udelay(100);
4883 val64 = readq(&bar0->stat_cfg);
b7b5a128 4884 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4885 break;
4886 cnt++;
4887 if (cnt == 5)
4888 break; /* Updt failed */
d44570e4 4889 } while (1);
8a4bdbaa 4890 }
7ba013ac
K		 4891}
4892
1da177e4 4893/**
20346722 4894 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4895 * @dev : pointer to the device structure.
4896 * Description:
20346722 4897 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4898 * structure and returns a pointer to the same.
4899 * Return value:
4900 * pointer to the updated net_device_stats structure.
4901 */
ac1f60db 4902static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4903{
4cf1653a 4904 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 4905 struct mac_info *mac_control = &sp->mac_control;
4906 struct stat_block *stats = mac_control->stats_info;
4a490432 4907 u64 delta;
1da177e4 4908
7ba013ac
K		 4909 /* Configure Stats for immediate updt */
4910 s2io_updt_stats(sp);
4911
4a490432
JM		 4912 /* A device reset will cause the on-adapter statistics to be zero'ed.
4913 * This can be done while running by changing the MTU. To prevent the
4914 * system from having the stats zero'ed, the driver keeps a copy of the
4915 * last update to the system (which is also zero'ed on reset). This
4916 * enables the driver to accurately know the delta between the last
4917 * update and the current update.
4918 */
4919 delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4920 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4921 sp->stats.rx_packets += delta;
4922 dev->stats.rx_packets += delta;
4923
4924 delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4925 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4926 sp->stats.tx_packets += delta;
4927 dev->stats.tx_packets += delta;
4928
4929 delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4930 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4931 sp->stats.rx_bytes += delta;
4932 dev->stats.rx_bytes += delta;
4933
4934 delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4935 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4936 sp->stats.tx_bytes += delta;
4937 dev->stats.tx_bytes += delta;
4938
4939 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4940 sp->stats.rx_errors += delta;
4941 dev->stats.rx_errors += delta;
4942
4943 delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4944 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4945 sp->stats.tx_errors += delta;
4946 dev->stats.tx_errors += delta;
4947
4948 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4949 sp->stats.rx_dropped += delta;
4950 dev->stats.rx_dropped += delta;
4951
4952 delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4953 sp->stats.tx_dropped += delta;
4954 dev->stats.tx_dropped += delta;
4955
4956 /* The adapter MAC interprets pause frames as multicast packets, but
4957 * does not pass them up. This erroneously increases the multicast
4958 * packet count and needs to be deducted when the multicast frame count
4959 * is queried.
4960 */
4961 delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4962 le32_to_cpu(stats->rmac_vld_mcst_frms);
4963 delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4964 delta -= sp->stats.multicast;
4965 sp->stats.multicast += delta;
4966 dev->stats.multicast += delta;
1da177e4 4967
4a490432
JM		 4968 delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4969 le32_to_cpu(stats->rmac_usized_frms)) +
4970 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4971 sp->stats.rx_length_errors += delta;
4972 dev->stats.rx_length_errors += delta;
13d866a9 4973
4a490432
JM		 4974 delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4975 sp->stats.rx_crc_errors += delta;
4976 dev->stats.rx_crc_errors += delta;
0425b46a 4977
d44570e4 4978 return &dev->stats;
1da177e4
LT		 4979}
4980
4981/**
4982 * s2io_set_multicast - entry point for multicast address enable/disable.
4983 * @dev : pointer to the device structure
4984 * Description:
20346722
K		 4985 * This function is a driver entry point which gets called by the kernel
4986 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4987 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4988 * determine, if multicast address must be enabled or if promiscuous mode
4989 * is to be disabled etc.
4990 * Return value:
4991 * void.
4992 */
4993
4994static void s2io_set_multicast(struct net_device *dev)
4995{
4996 int i, j, prev_cnt;
22bedad3 4997 struct netdev_hw_addr *ha;
4cf1653a 4998 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4999 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5000 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
d44570e4 5001 0xfeffffffffffULL;
faa4f796 5002 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 5003 void __iomem *add;
faa4f796 5004 struct config_param *config = &sp->config;
1da177e4
LT		 5005
5006 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5007 /* Enable all Multicast addresses */
5008 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5009 &bar0->rmac_addr_data0_mem);
5010 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5011 &bar0->rmac_addr_data1_mem);
5012 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5013 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5014 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 5015 writeq(val64, &bar0->rmac_addr_cmd_mem);
5016 /* Wait till command completes */
c92ca04b 5017 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5018 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5019 S2IO_BIT_RESET);
1da177e4
LT		 5020
5021 sp->m_cast_flg = 1;
faa4f796 5022 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 5023 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5024 /* Disable all Multicast addresses */
5025 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5026 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 5027 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5028 &bar0->rmac_addr_data1_mem);
1da177e4 5029 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5030 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5031 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
1da177e4
LT		 5032 writeq(val64, &bar0->rmac_addr_cmd_mem);
5033 /* Wait till command completes */
c92ca04b 5034 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5035 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5036 S2IO_BIT_RESET);
1da177e4
LT		 5037
5038 sp->m_cast_flg = 0;
5039 sp->all_multi_pos = 0;
5040 }
5041
5042 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5043 /* Put the NIC into promiscuous mode */
5044 add = &bar0->mac_cfg;
5045 val64 = readq(&bar0->mac_cfg);
5046 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5047
5048 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5049 writel((u32)val64, add);
1da177e4
LT		 5050 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5051 writel((u32) (val64 >> 32), (add + 4));
5052
926930b2
SS		 5053 if (vlan_tag_strip != 1) {
5054 val64 = readq(&bar0->rx_pa_cfg);
5055 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5056 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5057 sp->vlan_strip_flag = 0;
926930b2
SS		 5058 }
5059
1da177e4
LT		 5060 val64 = readq(&bar0->mac_cfg);
5061 sp->promisc_flg = 1;
776bd20f 5062 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5063 dev->name);
5064 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5065 /* Remove the NIC from promiscuous mode */
5066 add = &bar0->mac_cfg;
5067 val64 = readq(&bar0->mac_cfg);
5068 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5069
5070 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5071 writel((u32)val64, add);
1da177e4
LT		 5072 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5073 writel((u32) (val64 >> 32), (add + 4));
5074
926930b2
SS		 5075 if (vlan_tag_strip != 0) {
5076 val64 = readq(&bar0->rx_pa_cfg);
5077 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5078 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5079 sp->vlan_strip_flag = 1;
926930b2
SS		 5080 }
5081
1da177e4
LT		 5082 val64 = readq(&bar0->mac_cfg);
5083 sp->promisc_flg = 0;
9e39f7c5 5084 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
1da177e4
LT		 5085 }
5086
5087 /* Update individual M_CAST address list */
4cd24eaf
JP		 5088 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5089 if (netdev_mc_count(dev) >
faa4f796 5090 (config->max_mc_addr - config->max_mac_addr)) {
9e39f7c5
JP		 5091 DBG_PRINT(ERR_DBG,
5092 "%s: No more Rx filters can be added - "
5093 "please enable ALL_MULTI instead\n",
1da177e4 5094 dev->name);
1da177e4
LT		 5095 return;
5096 }
5097
5098 prev_cnt = sp->mc_addr_count;
4cd24eaf 5099 sp->mc_addr_count = netdev_mc_count(dev);
1da177e4
LT		 5100
5101 /* Clear out the previous list of Mc in the H/W. */
5102 for (i = 0; i < prev_cnt; i++) {
5103 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5104 &bar0->rmac_addr_data0_mem);
5105 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5106 &bar0->rmac_addr_data1_mem);
1da177e4 5107 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5108 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5109 RMAC_ADDR_CMD_MEM_OFFSET
5110 (config->mc_start_offset + i);
1da177e4
LT		 5111 writeq(val64, &bar0->rmac_addr_cmd_mem);
5112
5113 /* Wait for command completes */
c92ca04b 5114 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5115 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5116 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5117 DBG_PRINT(ERR_DBG,
5118 "%s: Adding Multicasts failed\n",
5119 dev->name);
1da177e4
LT		 5120 return;
5121 }
5122 }
5123
5124 /* Create the new Rx filter list and update the same in H/W. */
5508590c 5125 i = 0;
22bedad3
JP		 5126 netdev_for_each_mc_addr(ha, dev) {
5127 memcpy(sp->usr_addrs[i].addr, ha->addr,
1da177e4 5128 ETH_ALEN);
a7a80d5a 5129 mac_addr = 0;
1da177e4 5130 for (j = 0; j < ETH_ALEN; j++) {
22bedad3 5131 mac_addr |= ha->addr[j];
1da177e4
LT		 5132 mac_addr <<= 8;
5133 }
5134 mac_addr >>= 8;
5135 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5136 &bar0->rmac_addr_data0_mem);
5137 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5138 &bar0->rmac_addr_data1_mem);
1da177e4 5139 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5140 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5141 RMAC_ADDR_CMD_MEM_OFFSET
5142 (i + config->mc_start_offset);
1da177e4
LT		 5143 writeq(val64, &bar0->rmac_addr_cmd_mem);
5144
5145 /* Wait for command completes */
c92ca04b 5146 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5147 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5148 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5149 DBG_PRINT(ERR_DBG,
5150 "%s: Adding Multicasts failed\n",
5151 dev->name);
1da177e4
LT		 5152 return;
5153 }
5508590c 5154 i++;
1da177e4
LT		 5155 }
5156 }
5157}
5158
faa4f796
SH		 5159/* read from CAM unicast & multicast addresses and store it in
5160 * def_mac_addr structure
5161 */
dac499f9 5162static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5163{
5164 int offset;
5165 u64 mac_addr = 0x0;
5166 struct config_param *config = &sp->config;
5167
5168 /* store unicast & multicast mac addresses */
5169 for (offset = 0; offset < config->max_mc_addr; offset++) {
5170 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5171 /* if read fails disable the entry */
5172 if (mac_addr == FAILURE)
5173 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5174 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5175 }
5176}
5177
5178/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5179static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5180{
5181 int offset;
5182 struct config_param *config = &sp->config;
5183 /* restore unicast mac address */
5184 for (offset = 0; offset < config->max_mac_addr; offset++)
5185 do_s2io_prog_unicast(sp->dev,
d44570e4 5186 sp->def_mac_addr[offset].mac_addr);
faa4f796
SH		 5187
5188 /* restore multicast mac address */
5189 for (offset = config->mc_start_offset;
d44570e4 5190 offset < config->max_mc_addr; offset++)
faa4f796
SH		 5191 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5192}
5193
5194/* add a multicast MAC address to CAM */
5195static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5196{
5197 int i;
5198 u64 mac_addr = 0;
5199 struct config_param *config = &sp->config;
5200
5201 for (i = 0; i < ETH_ALEN; i++) {
5202 mac_addr <<= 8;
5203 mac_addr |= addr[i];
5204 }
5205 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5206 return SUCCESS;
5207
5208 /* check if the multicast mac already preset in CAM */
5209 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5210 u64 tmp64;
5211 tmp64 = do_s2io_read_unicast_mc(sp, i);
5212 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5213 break;
5214
5215 if (tmp64 == mac_addr)
5216 return SUCCESS;
5217 }
5218 if (i == config->max_mc_addr) {
5219 DBG_PRINT(ERR_DBG,
d44570e4 5220 "CAM full no space left for multicast MAC\n");
faa4f796
SH		 5221 return FAILURE;
5222 }
5223 /* Update the internal structure with this new mac address */
5224 do_s2io_copy_mac_addr(sp, i, mac_addr);
5225
d44570e4 5226 return do_s2io_add_mac(sp, mac_addr, i);
faa4f796
SH		 5227}
5228
5229/* add MAC address to CAM */
5230static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5231{
5232 u64 val64;
5233 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5234
5235 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
d44570e4 5236 &bar0->rmac_addr_data0_mem);
2fd37688 5237
d44570e4 5238 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2fd37688
SS		 5239 RMAC_ADDR_CMD_MEM_OFFSET(off);
5240 writeq(val64, &bar0->rmac_addr_cmd_mem);
5241
5242 /* Wait till command completes */
5243 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5244 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5245 S2IO_BIT_RESET)) {
faa4f796 5246 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5247 return FAILURE;
5248 }
5249 return SUCCESS;
5250}
faa4f796
SH		 5251/* deletes a specified unicast/multicast mac entry from CAM */
5252static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5253{
5254 int offset;
5255 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5256 struct config_param *config = &sp->config;
5257
5258 for (offset = 1;
d44570e4 5259 offset < config->max_mc_addr; offset++) {
faa4f796
SH		 5260 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5261 if (tmp64 == addr) {
5262 /* disable the entry by writing 0xffffffffffffULL */
5263 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5264 return FAILURE;
5265 /* store the new mac list from CAM */
5266 do_s2io_store_unicast_mc(sp);
5267 return SUCCESS;
5268 }
5269 }
5270 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
d44570e4 5271 (unsigned long long)addr);
faa4f796
SH		 5272 return FAILURE;
5273}
5274
5275/* read mac entries from CAM */
5276static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5277{
5278 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5279 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5280
5281 /* read mac addr */
d44570e4 5282 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796
SH		 5283 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5284 writeq(val64, &bar0->rmac_addr_cmd_mem);
5285
5286 /* Wait till command completes */
5287 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5288 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5289 S2IO_BIT_RESET)) {
faa4f796
SH		 5290 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5291 return FAILURE;
5292 }
5293 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4
JP		 5294
5295 return tmp64 >> 16;
faa4f796 5296}
2fd37688
SS		 5297
5298/**
5299 * s2io_set_mac_addr driver entry point
5300 */
faa4f796 5301
2fd37688
SS		 5302static int s2io_set_mac_addr(struct net_device *dev, void *p)
5303{
5304 struct sockaddr *addr = p;
5305
5306 if (!is_valid_ether_addr(addr->sa_data))
5307 return -EINVAL;
5308
5309 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5310
5311 /* store the MAC address in CAM */
d44570e4 5312 return do_s2io_prog_unicast(dev, dev->dev_addr);
2fd37688 5313}
1da177e4 5314/**
2fd37688 5315 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5316 * @dev : pointer to the device structure.
5317 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5318 * Description : This procedure will program the Xframe to receive
1da177e4 5319 * frames with new Mac Address
20346722 5320 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5321 * as defined in errno.h file on failure.
5322 */
faa4f796 5323
2fd37688 5324static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5325{
4cf1653a 5326 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5327 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5328 int i;
faa4f796
SH		 5329 u64 tmp64;
5330 struct config_param *config = &sp->config;
1da177e4 5331
20346722 5332 /*
d44570e4
JP		 5333 * Set the new MAC address as the new unicast filter and reflect this
5334 * change on the device address registered with the OS. It will be
5335 * at offset 0.
5336 */
1da177e4
LT		 5337 for (i = 0; i < ETH_ALEN; i++) {
5338 mac_addr <<= 8;
5339 mac_addr |= addr[i];
2fd37688
SS		 5340 perm_addr <<= 8;
5341 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5342 }
5343
2fd37688
SS		 5344 /* check if the dev_addr is different than perm_addr */
5345 if (mac_addr == perm_addr)
d8d70caf
SS		 5346 return SUCCESS;
5347
faa4f796
SH		 5348 /* check if the mac already preset in CAM */
5349 for (i = 1; i < config->max_mac_addr; i++) {
5350 tmp64 = do_s2io_read_unicast_mc(sp, i);
5351 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5352 break;
5353
5354 if (tmp64 == mac_addr) {
5355 DBG_PRINT(INFO_DBG,
d44570e4
JP		 5356 "MAC addr:0x%llx already present in CAM\n",
5357 (unsigned long long)mac_addr);
faa4f796
SH		 5358 return SUCCESS;
5359 }
5360 }
5361 if (i == config->max_mac_addr) {
5362 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5363 return FAILURE;
5364 }
d8d70caf 5365 /* Update the internal structure with this new mac address */
faa4f796 5366 do_s2io_copy_mac_addr(sp, i, mac_addr);
d44570e4
JP		 5367
5368 return do_s2io_add_mac(sp, mac_addr, i);
1da177e4
LT		 5369}
5370
5371/**
20346722 5372 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5373 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5374 * @info: pointer to the structure with parameters given by ethtool to set
5375 * link information.
5376 * Description:
20346722 5377 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5378 * the NIC.
5379 * Return value:
5380 * 0 on success.
d44570e4 5381 */
1da177e4
LT		 5382
5383static int s2io_ethtool_sset(struct net_device *dev,
5384 struct ethtool_cmd *info)
5385{
4cf1653a 5386 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5387 if ((info->autoneg == AUTONEG_ENABLE) ||
d44570e4
JP		 5388 (info->speed != SPEED_10000) ||
5389 (info->duplex != DUPLEX_FULL))
1da177e4
LT		 5390 return -EINVAL;
5391 else {
5392 s2io_close(sp->dev);
5393 s2io_open(sp->dev);
5394 }
5395
5396 return 0;
5397}
5398
5399/**
20346722 5400 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5401 * @sp : private member of the device structure, pointer to the
5402 * s2io_nic structure.
5403 * @info : pointer to the structure with parameters given by ethtool
5404 * to return link information.
5405 * Description:
5406 * Returns link specific information like speed, duplex etc.. to ethtool.
5407 * Return value :
5408 * return 0 on success.
5409 */
5410
5411static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5412{
4cf1653a 5413 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5414 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5415 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5416 info->port = PORT_FIBRE;
1a7eb72b
SS		 5417
5418 /* info->transceiver */
5419 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5420
5421 if (netif_carrier_ok(sp->dev)) {
5422 info->speed = 10000;
5423 info->duplex = DUPLEX_FULL;
5424 } else {
5425 info->speed = -1;
5426 info->duplex = -1;
5427 }
5428
5429 info->autoneg = AUTONEG_DISABLE;
5430 return 0;
5431}
5432
5433/**
20346722
K		 5434 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5435 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5436 * s2io_nic structure.
5437 * @info : pointer to the structure with parameters given by ethtool to
5438 * return driver information.
5439 * Description:
5440 * Returns driver specefic information like name, version etc.. to ethtool.
5441 * Return value:
5442 * void
5443 */
5444
5445static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5446 struct ethtool_drvinfo *info)
5447{
4cf1653a 5448 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5449
dbc2309d
JL		 5450 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5451 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5452 strncpy(info->fw_version, "", sizeof(info->fw_version));
5453 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5454 info->regdump_len = XENA_REG_SPACE;
5455 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5456}
5457
5458/**
5459 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5460 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5461 * s2io_nic structure.
20346722 5462 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5463 * dumping the registers.
5464 * @reg_space: The input argumnet into which all the registers are dumped.
5465 * Description:
5466 * Dumps the entire register space of xFrame NIC into the user given
5467 * buffer area.
5468 * Return value :
5469 * void .
d44570e4 5470 */
1da177e4
LT		 5471
5472static void s2io_ethtool_gregs(struct net_device *dev,
5473 struct ethtool_regs *regs, void *space)
5474{
5475 int i;
5476 u64 reg;
d44570e4 5477 u8 *reg_space = (u8 *)space;
4cf1653a 5478 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5479
5480 regs->len = XENA_REG_SPACE;
5481 regs->version = sp->pdev->subsystem_device;
5482
5483 for (i = 0; i < regs->len; i += 8) {
5484 reg = readq(sp->bar0 + i);
5485 memcpy((reg_space + i), &reg, 8);
5486 }
5487}
5488
5489/**
5490 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5491 * @data : address of the private member of the device structure, which
1da177e4 5492 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 5493 * Description: This is actually the timer function that alternates the
5494 * adapter LED bit of the adapter control bit to set/reset every time on
5495 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4 5496 * once every second.
d44570e4 5497 */
1da177e4
LT		 5498static void s2io_phy_id(unsigned long data)
5499{
d44570e4 5500 struct s2io_nic *sp = (struct s2io_nic *)data;
1ee6dd77 5501 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5502 u64 val64 = 0;
5503 u16 subid;
5504
5505 subid = sp->pdev->subsystem_device;
541ae68f 5506 if ((sp->device_type == XFRAME_II_DEVICE) ||
d44570e4 5507 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5508 val64 = readq(&bar0->gpio_control);
5509 val64 ^= GPIO_CTRL_GPIO_0;
5510 writeq(val64, &bar0->gpio_control);
5511 } else {
5512 val64 = readq(&bar0->adapter_control);
5513 val64 ^= ADAPTER_LED_ON;
5514 writeq(val64, &bar0->adapter_control);
5515 }
5516
5517 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5518}
5519
5520/**
5521 * s2io_ethtool_idnic - To physically identify the nic on the system.
5522 * @sp : private member of the device structure, which is a pointer to the
5523 * s2io_nic structure.
20346722 5524 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5525 * ethtool.
5526 * Description: Used to physically identify the NIC on the system.
20346722 5527 * The Link LED will blink for a time specified by the user for
1da177e4 5528 * identification.
20346722 5529 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5530 * identification is possible only if it's link is up.
5531 * Return value:
5532 * int , returns 0 on success
5533 */
5534
5535static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5536{
5537 u64 val64 = 0, last_gpio_ctrl_val;
4cf1653a 5538 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5539 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5540 u16 subid;
5541
5542 subid = sp->pdev->subsystem_device;
5543 last_gpio_ctrl_val = readq(&bar0->gpio_control);
d44570e4 5544 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5545 val64 = readq(&bar0->adapter_control);
5546 if (!(val64 & ADAPTER_CNTL_EN)) {
6cef2b8e 5547 pr_err("Adapter Link down, cannot blink LED\n");
1da177e4
LT		 5548 return -EFAULT;
5549 }
5550 }
5551 if (sp->id_timer.function == NULL) {
5552 init_timer(&sp->id_timer);
5553 sp->id_timer.function = s2io_phy_id;
d44570e4 5554 sp->id_timer.data = (unsigned long)sp;
1da177e4
LT		 5555 }
5556 mod_timer(&sp->id_timer, jiffies);
5557 if (data)
20346722 5558 msleep_interruptible(data * HZ);
1da177e4 5559 else
20346722 5560 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5561 del_timer_sync(&sp->id_timer);
5562
541ae68f 5563 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5564 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5565 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5566 }
5567
5568 return 0;
5569}
5570
0cec35eb 5571static void s2io_ethtool_gringparam(struct net_device *dev,
d44570e4 5572 struct ethtool_ringparam *ering)
0cec35eb 5573{
4cf1653a 5574 struct s2io_nic *sp = netdev_priv(dev);
d44570e4 5575 int i, tx_desc_count = 0, rx_desc_count = 0;
0cec35eb
SH		 5576
5577 if (sp->rxd_mode == RXD_MODE_1)
5578 ering->rx_max_pending = MAX_RX_DESC_1;
5579 else if (sp->rxd_mode == RXD_MODE_3B)
5580 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5581
5582 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5583 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5584 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5585
9e39f7c5 5586 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
0cec35eb
SH		 5587 ering->tx_pending = tx_desc_count;
5588 rx_desc_count = 0;
8a4bdbaa 5589 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5590 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5591
0cec35eb
SH		 5592 ering->rx_pending = rx_desc_count;
5593
5594 ering->rx_mini_max_pending = 0;
5595 ering->rx_mini_pending = 0;
d44570e4 5596 if (sp->rxd_mode == RXD_MODE_1)
0cec35eb
SH		 5597 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5598 else if (sp->rxd_mode == RXD_MODE_3B)
5599 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5600 ering->rx_jumbo_pending = rx_desc_count;
5601}
5602
1da177e4
LT		 5603/**
5604 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5605 * @sp : private member of the device structure, which is a pointer to the
5606 * s2io_nic structure.
1da177e4
LT		 5607 * @ep : pointer to the structure with pause parameters given by ethtool.
5608 * Description:
5609 * Returns the Pause frame generation and reception capability of the NIC.
5610 * Return value:
5611 * void
5612 */
5613static void s2io_ethtool_getpause_data(struct net_device *dev,
5614 struct ethtool_pauseparam *ep)
5615{
5616 u64 val64;
4cf1653a 5617 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5618 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5619
5620 val64 = readq(&bar0->rmac_pause_cfg);
5621 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5622 ep->tx_pause = true;
1da177e4 5623 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5624 ep->rx_pause = true;
5625 ep->autoneg = false;
1da177e4
LT		 5626}
5627
5628/**
5629 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5630 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5631 * s2io_nic structure.
5632 * @ep : pointer to the structure with pause parameters given by ethtool.
5633 * Description:
5634 * It can be used to set or reset Pause frame generation or reception
5635 * support of the NIC.
5636 * Return value:
5637 * int, returns 0 on Success
5638 */
5639
5640static int s2io_ethtool_setpause_data(struct net_device *dev,
d44570e4 5641 struct ethtool_pauseparam *ep)
1da177e4
LT		 5642{
5643 u64 val64;
4cf1653a 5644 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5645 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5646
5647 val64 = readq(&bar0->rmac_pause_cfg);
5648 if (ep->tx_pause)
5649 val64 |= RMAC_PAUSE_GEN_ENABLE;
5650 else
5651 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5652 if (ep->rx_pause)
5653 val64 |= RMAC_PAUSE_RX_ENABLE;
5654 else
5655 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5656 writeq(val64, &bar0->rmac_pause_cfg);
5657 return 0;
5658}
5659
5660/**
5661 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5662 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5663 * s2io_nic structure.
5664 * @off : offset at which the data must be written
5665 * @data : Its an output parameter where the data read at the given
20346722 5666 * offset is stored.
1da177e4 5667 * Description:
20346722 5668 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5669 * read data.
5670 * NOTE: Will allow to read only part of the EEPROM visible through the
5671 * I2C bus.
5672 * Return value:
5673 * -1 on failure and 0 on success.
5674 */
5675
5676#define S2IO_DEV_ID 5
d44570e4 5677static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
1da177e4
LT		 5678{
5679 int ret = -1;
5680 u32 exit_cnt = 0;
5681 u64 val64;
1ee6dd77 5682 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5683
ad4ebed0 5684 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5685 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5686 I2C_CONTROL_ADDR(off) |
5687 I2C_CONTROL_BYTE_CNT(0x3) |
5688 I2C_CONTROL_READ |
5689 I2C_CONTROL_CNTL_START;
ad4ebed0 5690 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5691
ad4ebed0 5692 while (exit_cnt < 5) {
5693 val64 = readq(&bar0->i2c_control);
5694 if (I2C_CONTROL_CNTL_END(val64)) {
5695 *data = I2C_CONTROL_GET_DATA(val64);
5696 ret = 0;
5697 break;
5698 }
5699 msleep(50);
5700 exit_cnt++;
1da177e4 5701 }
1da177e4
LT		 5702 }
5703
ad4ebed0 5704 if (sp->device_type == XFRAME_II_DEVICE) {
5705 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5706 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5707 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5708 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5709 val64 |= SPI_CONTROL_REQ;
5710 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5711 while (exit_cnt < 5) {
5712 val64 = readq(&bar0->spi_control);
5713 if (val64 & SPI_CONTROL_NACK) {
5714 ret = 1;
5715 break;
5716 } else if (val64 & SPI_CONTROL_DONE) {
5717 *data = readq(&bar0->spi_data);
5718 *data &= 0xffffff;
5719 ret = 0;
5720 break;
5721 }
5722 msleep(50);
5723 exit_cnt++;
5724 }
5725 }
1da177e4
LT		 5726 return ret;
5727}
5728
5729/**
5730 * write_eeprom - actually writes the relevant part of the data value.
5731 * @sp : private member of the device structure, which is a pointer to the
5732 * s2io_nic structure.
5733 * @off : offset at which the data must be written
5734 * @data : The data that is to be written
20346722 5735 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5736 * the Eeprom. (max of 3)
5737 * Description:
5738 * Actually writes the relevant part of the data value into the Eeprom
5739 * through the I2C bus.
5740 * Return value:
5741 * 0 on success, -1 on failure.
5742 */
5743
d44570e4 5744static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
1da177e4
LT		 5745{
5746 int exit_cnt = 0, ret = -1;
5747 u64 val64;
1ee6dd77 5748 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5749
ad4ebed0 5750 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5751 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5752 I2C_CONTROL_ADDR(off) |
5753 I2C_CONTROL_BYTE_CNT(cnt) |
5754 I2C_CONTROL_SET_DATA((u32)data) |
5755 I2C_CONTROL_CNTL_START;
ad4ebed0 5756 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5757
5758 while (exit_cnt < 5) {
5759 val64 = readq(&bar0->i2c_control);
5760 if (I2C_CONTROL_CNTL_END(val64)) {
5761 if (!(val64 & I2C_CONTROL_NACK))
5762 ret = 0;
5763 break;
5764 }
5765 msleep(50);
5766 exit_cnt++;
5767 }
5768 }
1da177e4 5769
ad4ebed0 5770 if (sp->device_type == XFRAME_II_DEVICE) {
5771 int write_cnt = (cnt == 8) ? 0 : cnt;
d44570e4 5772 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
ad4ebed0 5773
5774 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5775 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5776 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5777 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5778 val64 |= SPI_CONTROL_REQ;
5779 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5780 while (exit_cnt < 5) {
5781 val64 = readq(&bar0->spi_control);
5782 if (val64 & SPI_CONTROL_NACK) {
5783 ret = 1;
5784 break;
5785 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5786 ret = 0;
ad4ebed0 5787 break;
5788 }
5789 msleep(50);
5790 exit_cnt++;
1da177e4 5791 }
1da177e4 5792 }
1da177e4
LT		 5793 return ret;
5794}
1ee6dd77 5795static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5796{
b41477f3
AR		 5797 u8 *vpd_data;
5798 u8 data;
d44570e4 5799 int i = 0, cnt, fail = 0;
9dc737a7 5800 int vpd_addr = 0x80;
ffb5df6c 5801 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
9dc737a7
AR		 5802
5803 if (nic->device_type == XFRAME_II_DEVICE) {
5804 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5805 vpd_addr = 0x80;
d44570e4 5806 } else {
9dc737a7
AR		 5807 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5808 vpd_addr = 0x50;
5809 }
19a60522 5810 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5811
b41477f3 5812 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945 5813 if (!vpd_data) {
ffb5df6c 5814 swstats->mem_alloc_fail_cnt++;
b41477f3 5815 return;
c53d4945 5816 }
ffb5df6c 5817 swstats->mem_allocated += 256;
b41477f3 5818
d44570e4 5819 for (i = 0; i < 256; i += 4) {
9dc737a7
AR		 5820 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5821 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5822 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
d44570e4 5823 for (cnt = 0; cnt < 5; cnt++) {
9dc737a7
AR		 5824 msleep(2);
5825 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5826 if (data == 0x80)
5827 break;
5828 }
5829 if (cnt >= 5) {
5830 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5831 fail = 1;
5832 break;
5833 }
5834 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5835 (u32 *)&vpd_data[i]);
5836 }
19a60522 5837
d44570e4 5838 if (!fail) {
19a60522
SS		 5839 /* read serial number of adapter */
5840 for (cnt = 0; cnt < 256; cnt++) {
d44570e4
JP		 5841 if ((vpd_data[cnt] == 'S') &&
5842 (vpd_data[cnt+1] == 'N') &&
5843 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
19a60522
SS		 5844 memset(nic->serial_num, 0, VPD_STRING_LEN);
5845 memcpy(nic->serial_num, &vpd_data[cnt + 3],
d44570e4 5846 vpd_data[cnt+2]);
19a60522
SS		 5847 break;
5848 }
5849 }
5850 }
5851
876e956f 5852 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN))
9dc737a7 5853 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
b41477f3 5854 kfree(vpd_data);
ffb5df6c 5855 swstats->mem_freed += 256;
9dc737a7
AR		 5856}
5857
1da177e4
LT		 5858/**
5859 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5860 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5861 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5862 * containing all relevant information.
5863 * @data_buf : user defined value to be written into Eeprom.
5864 * Description: Reads the values stored in the Eeprom at given offset
5865 * for a given length. Stores these values int the input argument data
5866 * buffer 'data_buf' and returns these to the caller (ethtool.)
5867 * Return value:
5868 * int 0 on success
5869 */
5870
5871static int s2io_ethtool_geeprom(struct net_device *dev,
d44570e4 5872 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5873{
ad4ebed0 5874 u32 i, valid;
5875 u64 data;
4cf1653a 5876 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5877
5878 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5879
5880 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5881 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5882
5883 for (i = 0; i < eeprom->len; i += 4) {
5884 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5885 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5886 return -EFAULT;
5887 }
5888 valid = INV(data);
5889 memcpy((data_buf + i), &valid, 4);
5890 }
5891 return 0;
5892}
5893
5894/**
5895 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5896 * @sp : private member of the device structure, which is a pointer to the
5897 * s2io_nic structure.
20346722 5898 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5899 * containing all relevant information.
5900 * @data_buf ; user defined value to be written into Eeprom.
5901 * Description:
5902 * Tries to write the user provided value in the Eeprom, at the offset
5903 * given by the user.
5904 * Return value:
5905 * 0 on success, -EFAULT on failure.
5906 */
5907
5908static int s2io_ethtool_seeprom(struct net_device *dev,
5909 struct ethtool_eeprom *eeprom,
d44570e4 5910 u8 *data_buf)
1da177e4
LT		 5911{
5912 int len = eeprom->len, cnt = 0;
ad4ebed0 5913 u64 valid = 0, data;
4cf1653a 5914 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5915
5916 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5917 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5918 "ETHTOOL_WRITE_EEPROM Err: "
5919 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5920 (sp->pdev->vendor | (sp->pdev->device << 16)),
5921 eeprom->magic);
1da177e4
LT		 5922 return -EFAULT;
5923 }
5924
5925 while (len) {
d44570e4
JP		 5926 data = (u32)data_buf[cnt] & 0x000000FF;
5927 if (data)
5928 valid = (u32)(data << 24);
5929 else
1da177e4
LT		 5930 valid = data;
5931
5932 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5933 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5934 "ETHTOOL_WRITE_EEPROM Err: "
5935 "Cannot write into the specified offset\n");
1da177e4
LT		 5936 return -EFAULT;
5937 }
5938 cnt++;
5939 len--;
5940 }
5941
5942 return 0;
5943}
5944
5945/**
20346722
K		 5946 * s2io_register_test - reads and writes into all clock domains.
5947 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5948 * s2io_nic structure.
5949 * @data : variable that returns the result of each of the test conducted b
5950 * by the driver.
5951 * Description:
5952 * Read and write into all clock domains. The NIC has 3 clock domains,
5953 * see that registers in all the three regions are accessible.
5954 * Return value:
5955 * 0 on success.
5956 */
5957
d44570e4 5958static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 5959{
1ee6dd77 5960 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5961 u64 val64 = 0, exp_val;
1da177e4
LT		 5962 int fail = 0;
5963
20346722
K		 5964 val64 = readq(&bar0->pif_rd_swapper_fb);
5965 if (val64 != 0x123456789abcdefULL) {
1da177e4 5966 fail = 1;
9e39f7c5 5967 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
1da177e4
LT		 5968 }
5969
5970 val64 = readq(&bar0->rmac_pause_cfg);
5971 if (val64 != 0xc000ffff00000000ULL) {
5972 fail = 1;
9e39f7c5 5973 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
1da177e4
LT		 5974 }
5975
5976 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5977 if (sp->device_type == XFRAME_II_DEVICE)
5978 exp_val = 0x0404040404040404ULL;
5979 else
5980 exp_val = 0x0808080808080808ULL;
5981 if (val64 != exp_val) {
1da177e4 5982 fail = 1;
9e39f7c5 5983 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
1da177e4
LT		 5984 }
5985
5986 val64 = readq(&bar0->xgxs_efifo_cfg);
5987 if (val64 != 0x000000001923141EULL) {
5988 fail = 1;
9e39f7c5 5989 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
1da177e4
LT		 5990 }
5991
5992 val64 = 0x5A5A5A5A5A5A5A5AULL;
5993 writeq(val64, &bar0->xmsi_data);
5994 val64 = readq(&bar0->xmsi_data);
5995 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5996 fail = 1;
9e39f7c5 5997 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
1da177e4
LT		 5998 }
5999
6000 val64 = 0xA5A5A5A5A5A5A5A5ULL;
6001 writeq(val64, &bar0->xmsi_data);
6002 val64 = readq(&bar0->xmsi_data);
6003 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
6004 fail = 1;
9e39f7c5 6005 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
1da177e4
LT		 6006 }
6007
6008 *data = fail;
ad4ebed0 6009 return fail;
1da177e4
LT		 6010}
6011
6012/**
20346722 6013 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 6014 * @sp : private member of the device structure, which is a pointer to the
6015 * s2io_nic structure.
6016 * @data:variable that returns the result of each of the test conducted by
6017 * the driver.
6018 * Description:
20346722 6019 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 6020 * register.
6021 * Return value:
6022 * 0 on success.
6023 */
6024
d44570e4 6025static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6026{
6027 int fail = 0;
ad4ebed0 6028 u64 ret_data, org_4F0, org_7F0;
6029 u8 saved_4F0 = 0, saved_7F0 = 0;
6030 struct net_device *dev = sp->dev;
1da177e4
LT		 6031
6032 /* Test Write Error at offset 0 */
ad4ebed0 6033 /* Note that SPI interface allows write access to all areas
6034 * of EEPROM. Hence doing all negative testing only for Xframe I.
6035 */
6036 if (sp->device_type == XFRAME_I_DEVICE)
6037 if (!write_eeprom(sp, 0, 0, 3))
6038 fail = 1;
6039
6040 /* Save current values at offsets 0x4F0 and 0x7F0 */
6041 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6042 saved_4F0 = 1;
6043 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6044 saved_7F0 = 1;
1da177e4
LT		 6045
6046 /* Test Write at offset 4f0 */
ad4ebed0 6047 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6048 fail = 1;
6049 if (read_eeprom(sp, 0x4F0, &ret_data))
6050 fail = 1;
6051
ad4ebed0 6052 if (ret_data != 0x012345) {
26b7625c 6053 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
d44570e4
JP		 6054 "Data written %llx Data read %llx\n",
6055 dev->name, (unsigned long long)0x12345,
6056 (unsigned long long)ret_data);
1da177e4 6057 fail = 1;
ad4ebed0 6058 }
1da177e4
LT		 6059
6060 /* Reset the EEPROM data go FFFF */
ad4ebed0 6061 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6062
6063 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6064 if (sp->device_type == XFRAME_I_DEVICE)
6065 if (!write_eeprom(sp, 0x07C, 0, 3))
6066 fail = 1;
1da177e4 6067
ad4ebed0 6068 /* Test Write Request at offset 0x7f0 */
6069 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6070 fail = 1;
ad4ebed0 6071 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6072 fail = 1;
6073
ad4ebed0 6074 if (ret_data != 0x012345) {
26b7625c 6075 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
d44570e4
JP		 6076 "Data written %llx Data read %llx\n",
6077 dev->name, (unsigned long long)0x12345,
6078 (unsigned long long)ret_data);
1da177e4 6079 fail = 1;
ad4ebed0 6080 }
1da177e4
LT		 6081
6082 /* Reset the EEPROM data go FFFF */
ad4ebed0 6083 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6084
ad4ebed0 6085 if (sp->device_type == XFRAME_I_DEVICE) {
6086 /* Test Write Error at offset 0x80 */
6087 if (!write_eeprom(sp, 0x080, 0, 3))
6088 fail = 1;
1da177e4 6089
ad4ebed0 6090 /* Test Write Error at offset 0xfc */
6091 if (!write_eeprom(sp, 0x0FC, 0, 3))
6092 fail = 1;
1da177e4 6093
ad4ebed0 6094 /* Test Write Error at offset 0x100 */
6095 if (!write_eeprom(sp, 0x100, 0, 3))
6096 fail = 1;
1da177e4 6097
ad4ebed0 6098 /* Test Write Error at offset 4ec */
6099 if (!write_eeprom(sp, 0x4EC, 0, 3))
6100 fail = 1;
6101 }
6102
6103 /* Restore values at offsets 0x4F0 and 0x7F0 */
6104 if (saved_4F0)
6105 write_eeprom(sp, 0x4F0, org_4F0, 3);
6106 if (saved_7F0)
6107 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6108
6109 *data = fail;
ad4ebed0 6110 return fail;
1da177e4
LT		 6111}
6112
6113/**
6114 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6115 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6116 * s2io_nic structure.
20346722 6117 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6118 * the driver.
6119 * Description:
6120 * This invokes the MemBist test of the card. We give around
6121 * 2 secs time for the Test to complete. If it's still not complete
20346722 6122 * within this peiod, we consider that the test failed.
1da177e4
LT		 6123 * Return value:
6124 * 0 on success and -1 on failure.
6125 */
6126
d44570e4 6127static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6128{
6129 u8 bist = 0;
6130 int cnt = 0, ret = -1;
6131
6132 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6133 bist |= PCI_BIST_START;
6134 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6135
6136 while (cnt < 20) {
6137 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6138 if (!(bist & PCI_BIST_START)) {
6139 *data = (bist & PCI_BIST_CODE_MASK);
6140 ret = 0;
6141 break;
6142 }
6143 msleep(100);
6144 cnt++;
6145 }
6146
6147 return ret;
6148}
6149
6150/**
20346722
K		 6151 * s2io-link_test - verifies the link state of the nic
6152 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6153 * s2io_nic structure.
6154 * @data: variable that returns the result of each of the test conducted by
6155 * the driver.
6156 * Description:
20346722 6157 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6158 * argument 'data' appropriately.
6159 * Return value:
6160 * 0 on success.
6161 */
6162
d44570e4 6163static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6164{
1ee6dd77 6165 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6166 u64 val64;
6167
6168 val64 = readq(&bar0->adapter_status);
d44570e4 6169 if (!(LINK_IS_UP(val64)))
1da177e4 6170 *data = 1;
c92ca04b
AR		 6171 else
6172 *data = 0;
1da177e4 6173
b41477f3 6174 return *data;
1da177e4
LT		 6175}
6176
6177/**
20346722
K		 6178 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6179 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6180 * s2io_nic structure.
20346722 6181 * @data - variable that returns the result of each of the test
1da177e4
LT		 6182 * conducted by the driver.
6183 * Description:
20346722 6184 * This is one of the offline test that tests the read and write
1da177e4
LT		 6185 * access to the RldRam chip on the NIC.
6186 * Return value:
6187 * 0 on success.
6188 */
6189
d44570e4 6190static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6191{
1ee6dd77 6192 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6193 u64 val64;
ad4ebed0 6194 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6195
6196 val64 = readq(&bar0->adapter_control);
6197 val64 &= ~ADAPTER_ECC_EN;
6198 writeq(val64, &bar0->adapter_control);
6199
6200 val64 = readq(&bar0->mc_rldram_test_ctrl);
6201 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6202 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6203
6204 val64 = readq(&bar0->mc_rldram_mrs);
6205 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6206 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6207
6208 val64 |= MC_RLDRAM_MRS_ENABLE;
6209 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6210
6211 while (iteration < 2) {
6212 val64 = 0x55555555aaaa0000ULL;
d44570e4 6213 if (iteration == 1)
1da177e4 6214 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6215 writeq(val64, &bar0->mc_rldram_test_d0);
6216
6217 val64 = 0xaaaa5a5555550000ULL;
d44570e4 6218 if (iteration == 1)
1da177e4 6219 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6220 writeq(val64, &bar0->mc_rldram_test_d1);
6221
6222 val64 = 0x55aaaaaaaa5a0000ULL;
d44570e4 6223 if (iteration == 1)
1da177e4 6224 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6225 writeq(val64, &bar0->mc_rldram_test_d2);
6226
ad4ebed0 6227 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6228 writeq(val64, &bar0->mc_rldram_test_add);
6229
d44570e4
JP		 6230 val64 = MC_RLDRAM_TEST_MODE |
6231 MC_RLDRAM_TEST_WRITE |
6232 MC_RLDRAM_TEST_GO;
ad4ebed0 6233 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6234
6235 for (cnt = 0; cnt < 5; cnt++) {
6236 val64 = readq(&bar0->mc_rldram_test_ctrl);
6237 if (val64 & MC_RLDRAM_TEST_DONE)
6238 break;
6239 msleep(200);
6240 }
6241
6242 if (cnt == 5)
6243 break;
6244
ad4ebed0 6245 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6246 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6247
6248 for (cnt = 0; cnt < 5; cnt++) {
6249 val64 = readq(&bar0->mc_rldram_test_ctrl);
6250 if (val64 & MC_RLDRAM_TEST_DONE)
6251 break;
6252 msleep(500);
6253 }
6254
6255 if (cnt == 5)
6256 break;
6257
6258 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6259 if (!(val64 & MC_RLDRAM_TEST_PASS))
6260 test_fail = 1;
1da177e4
LT		 6261
6262 iteration++;
6263 }
6264
ad4ebed0 6265 *data = test_fail;
1da177e4 6266
ad4ebed0 6267 /* Bring the adapter out of test mode */
6268 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6269
6270 return test_fail;
1da177e4
LT		 6271}
6272
6273/**
6274 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6275 * @sp : private member of the device structure, which is a pointer to the
6276 * s2io_nic structure.
6277 * @ethtest : pointer to a ethtool command specific structure that will be
6278 * returned to the user.
20346722 6279 * @data : variable that returns the result of each of the test
1da177e4
LT		 6280 * conducted by the driver.
6281 * Description:
6282 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6283 * the health of the card.
6284 * Return value:
6285 * void
6286 */
6287
6288static void s2io_ethtool_test(struct net_device *dev,
6289 struct ethtool_test *ethtest,
d44570e4 6290 uint64_t *data)
1da177e4 6291{
4cf1653a 6292 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6293 int orig_state = netif_running(sp->dev);
6294
6295 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6296 /* Offline Tests. */
20346722 6297 if (orig_state)
1da177e4 6298 s2io_close(sp->dev);
1da177e4
LT		 6299
6300 if (s2io_register_test(sp, &data[0]))
6301 ethtest->flags |= ETH_TEST_FL_FAILED;
6302
6303 s2io_reset(sp);
1da177e4
LT		 6304
6305 if (s2io_rldram_test(sp, &data[3]))
6306 ethtest->flags |= ETH_TEST_FL_FAILED;
6307
6308 s2io_reset(sp);
1da177e4
LT		 6309
6310 if (s2io_eeprom_test(sp, &data[1]))
6311 ethtest->flags |= ETH_TEST_FL_FAILED;
6312
6313 if (s2io_bist_test(sp, &data[4]))
6314 ethtest->flags |= ETH_TEST_FL_FAILED;
6315
6316 if (orig_state)
6317 s2io_open(sp->dev);
6318
6319 data[2] = 0;
6320 } else {
6321 /* Online Tests. */
6322 if (!orig_state) {
d44570e4 6323 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
1da177e4
LT		 6324 dev->name);
6325 data[0] = -1;
6326 data[1] = -1;
6327 data[2] = -1;
6328 data[3] = -1;
6329 data[4] = -1;
6330 }
6331
6332 if (s2io_link_test(sp, &data[2]))
6333 ethtest->flags |= ETH_TEST_FL_FAILED;
6334
6335 data[0] = 0;
6336 data[1] = 0;
6337 data[3] = 0;
6338 data[4] = 0;
6339 }
6340}
6341
6342static void s2io_get_ethtool_stats(struct net_device *dev,
6343 struct ethtool_stats *estats,
d44570e4 6344 u64 *tmp_stats)
1da177e4 6345{
8116f3cf 6346 int i = 0, k;
4cf1653a 6347 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 6348 struct stat_block *stats = sp->mac_control.stats_info;
6349 struct swStat *swstats = &stats->sw_stat;
6350 struct xpakStat *xstats = &stats->xpak_stat;
1da177e4 6351
7ba013ac 6352 s2io_updt_stats(sp);
541ae68f 6353 tmp_stats[i++] =
ffb5df6c
JP		 6354 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6355 le32_to_cpu(stats->tmac_frms);
541ae68f 6356 tmp_stats[i++] =
ffb5df6c
JP		 6357 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6358 le32_to_cpu(stats->tmac_data_octets);
6359 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
541ae68f 6360 tmp_stats[i++] =
ffb5df6c
JP		 6361 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6362 le32_to_cpu(stats->tmac_mcst_frms);
541ae68f 6363 tmp_stats[i++] =
ffb5df6c
JP		 6364 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6365 le32_to_cpu(stats->tmac_bcst_frms);
6366 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
bd1034f0 6367 tmp_stats[i++] =
ffb5df6c
JP		 6368 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6369 le32_to_cpu(stats->tmac_ttl_octets);
bd1034f0 6370 tmp_stats[i++] =
ffb5df6c
JP		 6371 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6372 le32_to_cpu(stats->tmac_ucst_frms);
d44570e4 6373 tmp_stats[i++] =
ffb5df6c
JP		 6374 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6375 le32_to_cpu(stats->tmac_nucst_frms);
541ae68f 6376 tmp_stats[i++] =
ffb5df6c
JP		 6377 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6378 le32_to_cpu(stats->tmac_any_err_frms);
6379 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6380 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
541ae68f 6381 tmp_stats[i++] =
ffb5df6c
JP		 6382 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6383 le32_to_cpu(stats->tmac_vld_ip);
541ae68f 6384 tmp_stats[i++] =
ffb5df6c
JP		 6385 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6386 le32_to_cpu(stats->tmac_drop_ip);
541ae68f 6387 tmp_stats[i++] =
ffb5df6c
JP		 6388 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6389 le32_to_cpu(stats->tmac_icmp);
541ae68f 6390 tmp_stats[i++] =
ffb5df6c
JP		 6391 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6392 le32_to_cpu(stats->tmac_rst_tcp);
6393 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6394 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6395 le32_to_cpu(stats->tmac_udp);
541ae68f 6396 tmp_stats[i++] =
ffb5df6c
JP		 6397 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6398 le32_to_cpu(stats->rmac_vld_frms);
541ae68f 6399 tmp_stats[i++] =
ffb5df6c
JP		 6400 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6401 le32_to_cpu(stats->rmac_data_octets);
6402 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6403 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
541ae68f 6404 tmp_stats[i++] =
ffb5df6c
JP		 6405 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6406 le32_to_cpu(stats->rmac_vld_mcst_frms);
541ae68f 6407 tmp_stats[i++] =
ffb5df6c
JP		 6408 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6409 le32_to_cpu(stats->rmac_vld_bcst_frms);
6410 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6411 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6412 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6413 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6414 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
d44570e4 6415 tmp_stats[i++] =
ffb5df6c
JP		 6416 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6417 le32_to_cpu(stats->rmac_ttl_octets);
bd1034f0 6418 tmp_stats[i++] =
ffb5df6c
JP		 6419 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6420 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
d44570e4 6421 tmp_stats[i++] =
ffb5df6c
JP		 6422 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6423 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
541ae68f 6424 tmp_stats[i++] =
ffb5df6c
JP		 6425 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6426 le32_to_cpu(stats->rmac_discarded_frms);
d44570e4 6427 tmp_stats[i++] =
ffb5df6c
JP		 6428 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6429 << 32 | le32_to_cpu(stats->rmac_drop_events);
6430 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6431 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
541ae68f 6432 tmp_stats[i++] =
ffb5df6c
JP		 6433 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6434 le32_to_cpu(stats->rmac_usized_frms);
541ae68f 6435 tmp_stats[i++] =
ffb5df6c
JP		 6436 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6437 le32_to_cpu(stats->rmac_osized_frms);
541ae68f 6438 tmp_stats[i++] =
ffb5df6c
JP		 6439 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6440 le32_to_cpu(stats->rmac_frag_frms);
541ae68f 6441 tmp_stats[i++] =
ffb5df6c
JP		 6442 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6443 le32_to_cpu(stats->rmac_jabber_frms);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6445 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6446 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6447 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6448 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6449 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
bd1034f0 6450 tmp_stats[i++] =
ffb5df6c
JP		 6451 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6452 le32_to_cpu(stats->rmac_ip);
6453 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6454 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
bd1034f0 6455 tmp_stats[i++] =
ffb5df6c
JP		 6456 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6457 le32_to_cpu(stats->rmac_drop_ip);
bd1034f0 6458 tmp_stats[i++] =
ffb5df6c
JP		 6459 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6460 le32_to_cpu(stats->rmac_icmp);
6461 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
bd1034f0 6462 tmp_stats[i++] =
ffb5df6c
JP		 6463 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6464 le32_to_cpu(stats->rmac_udp);
541ae68f 6465 tmp_stats[i++] =
ffb5df6c
JP		 6466 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6467 le32_to_cpu(stats->rmac_err_drp_udp);
6468 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6469 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6470 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6471 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6472 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6473 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6474 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6475 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6476 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6477 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6478 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6479 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6480 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6481 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6482 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6483 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6484 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
541ae68f 6485 tmp_stats[i++] =
ffb5df6c
JP		 6486 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6487 le32_to_cpu(stats->rmac_pause_cnt);
6488 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6489 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
541ae68f 6490 tmp_stats[i++] =
ffb5df6c
JP		 6491 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6492 le32_to_cpu(stats->rmac_accepted_ip);
6493 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6494 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6495 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6496 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6497 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6498 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6499 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6500 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6501 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6502 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6503 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6504 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6505 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6506 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6507 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6508 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6509 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6510 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6511 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
fa1f0cb3
SS		 6512
6513 /* Enhanced statistics exist only for Hercules */
d44570e4 6514 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6515 tmp_stats[i++] =
ffb5df6c 6516 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
fa1f0cb3 6517 tmp_stats[i++] =
ffb5df6c 6518 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
fa1f0cb3 6519 tmp_stats[i++] =
ffb5df6c
JP		 6520 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6521 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6522 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6523 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6524 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6525 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6526 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6527 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6528 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6529 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6530 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6531 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6532 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6533 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
fa1f0cb3
SS		 6534 }
6535
7ba013ac 6536 tmp_stats[i++] = 0;
ffb5df6c
JP		 6537 tmp_stats[i++] = swstats->single_ecc_errs;
6538 tmp_stats[i++] = swstats->double_ecc_errs;
6539 tmp_stats[i++] = swstats->parity_err_cnt;
6540 tmp_stats[i++] = swstats->serious_err_cnt;
6541 tmp_stats[i++] = swstats->soft_reset_cnt;
6542 tmp_stats[i++] = swstats->fifo_full_cnt;
8116f3cf 6543 for (k = 0; k < MAX_RX_RINGS; k++)
ffb5df6c
JP		 6544 tmp_stats[i++] = swstats->ring_full_cnt[k];
6545 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6546 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6547 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6548 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6549 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6550 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6551 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6552 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6553 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6554 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6555 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6556 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6557 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6558 tmp_stats[i++] = swstats->sending_both;
6559 tmp_stats[i++] = swstats->outof_sequence_pkts;
6560 tmp_stats[i++] = swstats->flush_max_pkts;
6561 if (swstats->num_aggregations) {
6562 u64 tmp = swstats->sum_avg_pkts_aggregated;
bd1034f0 6563 int count = 0;
6aa20a22 6564 /*
bd1034f0
AR		 6565 * Since 64-bit divide does not work on all platforms,
6566 * do repeated subtraction.
6567 */
ffb5df6c
JP		 6568 while (tmp >= swstats->num_aggregations) {
6569 tmp -= swstats->num_aggregations;
bd1034f0
AR		 6570 count++;
6571 }
6572 tmp_stats[i++] = count;
d44570e4 6573 } else
bd1034f0 6574 tmp_stats[i++] = 0;
ffb5df6c
JP		 6575 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6576 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6577 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6578 tmp_stats[i++] = swstats->mem_allocated;
6579 tmp_stats[i++] = swstats->mem_freed;
6580 tmp_stats[i++] = swstats->link_up_cnt;
6581 tmp_stats[i++] = swstats->link_down_cnt;
6582 tmp_stats[i++] = swstats->link_up_time;
6583 tmp_stats[i++] = swstats->link_down_time;
6584
6585 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6586 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6587 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6588 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6589 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6590
6591 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6592 tmp_stats[i++] = swstats->rx_abort_cnt;
6593 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6594 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6595 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6596 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6597 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6598 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6599 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6600 tmp_stats[i++] = swstats->tda_err_cnt;
6601 tmp_stats[i++] = swstats->pfc_err_cnt;
6602 tmp_stats[i++] = swstats->pcc_err_cnt;
6603 tmp_stats[i++] = swstats->tti_err_cnt;
6604 tmp_stats[i++] = swstats->tpa_err_cnt;
6605 tmp_stats[i++] = swstats->sm_err_cnt;
6606 tmp_stats[i++] = swstats->lso_err_cnt;
6607 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6608 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6609 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6610 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6611 tmp_stats[i++] = swstats->rc_err_cnt;
6612 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6613 tmp_stats[i++] = swstats->rpa_err_cnt;
6614 tmp_stats[i++] = swstats->rda_err_cnt;
6615 tmp_stats[i++] = swstats->rti_err_cnt;
6616 tmp_stats[i++] = swstats->mc_err_cnt;
1da177e4
LT		 6617}
6618
ac1f60db 6619static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4 6620{
d44570e4 6621 return XENA_REG_SPACE;
1da177e4
LT		 6622}
6623
6624
d44570e4 6625static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
1da177e4 6626{
4cf1653a 6627 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 6628
d44570e4 6629 return sp->rx_csum;
1da177e4 6630}
ac1f60db
AB		 6631
6632static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6633{
4cf1653a 6634 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6635
6636 if (data)
6637 sp->rx_csum = 1;
6638 else
6639 sp->rx_csum = 0;
6640
6641 return 0;
6642}
ac1f60db
AB		 6643
6644static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4 6645{
d44570e4 6646 return XENA_EEPROM_SPACE;
1da177e4
LT		 6647}
6648
b9f2c044 6649static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6650{
4cf1653a 6651 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6652
6653 switch (sset) {
6654 case ETH_SS_TEST:
6655 return S2IO_TEST_LEN;
6656 case ETH_SS_STATS:
d44570e4 6657 switch (sp->device_type) {
b9f2c044
JG		 6658 case XFRAME_I_DEVICE:
6659 return XFRAME_I_STAT_LEN;
6660 case XFRAME_II_DEVICE:
6661 return XFRAME_II_STAT_LEN;
6662 default:
6663 return 0;
6664 }
6665 default:
6666 return -EOPNOTSUPP;
6667 }
1da177e4 6668}
ac1f60db
AB		 6669
6670static void s2io_ethtool_get_strings(struct net_device *dev,
d44570e4 6671 u32 stringset, u8 *data)
1da177e4 6672{
fa1f0cb3 6673 int stat_size = 0;
4cf1653a 6674 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6675
1da177e4
LT		 6676 switch (stringset) {
6677 case ETH_SS_TEST:
6678 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6679 break;
6680 case ETH_SS_STATS:
fa1f0cb3 6681 stat_size = sizeof(ethtool_xena_stats_keys);
d44570e4
JP		 6682 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6683 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6684 memcpy(data + stat_size,
d44570e4
JP		 6685 &ethtool_enhanced_stats_keys,
6686 sizeof(ethtool_enhanced_stats_keys));
fa1f0cb3
SS		 6687 stat_size += sizeof(ethtool_enhanced_stats_keys);
6688 }
6689
6690 memcpy(data + stat_size, &ethtool_driver_stats_keys,
d44570e4 6691 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6692 }
6693}
1da177e4 6694
ac1f60db 6695static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6696{
6697 if (data)
6698 dev->features |= NETIF_F_IP_CSUM;
6699 else
6700 dev->features &= ~NETIF_F_IP_CSUM;
6701
6702 return 0;
6703}
6704
75c30b13
AR		 6705static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6706{
6707 return (dev->features & NETIF_F_TSO) != 0;
6708}
958de193 6709
75c30b13
AR		 6710static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6711{
6712 if (data)
6713 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6714 else
6715 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6716
6717 return 0;
6718}
1da177e4 6719
958de193
JM		 6720static int s2io_ethtool_set_flags(struct net_device *dev, u32 data)
6721{
6722 struct s2io_nic *sp = netdev_priv(dev);
6723 int rc = 0;
6724 int changed = 0;
6725
6726 if (data & ~ETH_FLAG_LRO)
97d1935a 6727 return -EINVAL;
958de193
JM		 6728
6729 if (data & ETH_FLAG_LRO) {
6730 if (lro_enable) {
6731 if (!(dev->features & NETIF_F_LRO)) {
6732 dev->features |= NETIF_F_LRO;
6733 changed = 1;
6734 }
6735 } else
6736 rc = -EINVAL;
6737 } else if (dev->features & NETIF_F_LRO) {
6738 dev->features &= ~NETIF_F_LRO;
6739 changed = 1;
6740 }
6741
6742 if (changed && netif_running(dev)) {
6743 s2io_stop_all_tx_queue(sp);
6744 s2io_card_down(sp);
6745 sp->lro = !!(dev->features & NETIF_F_LRO);
6746 rc = s2io_card_up(sp);
6747 if (rc)
6748 s2io_reset(sp);
6749 else
6750 s2io_start_all_tx_queue(sp);
6751 }
6752
6753 return rc;
6754}
6755
7282d491 6756static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6757 .get_settings = s2io_ethtool_gset,
6758 .set_settings = s2io_ethtool_sset,
6759 .get_drvinfo = s2io_ethtool_gdrvinfo,
6760 .get_regs_len = s2io_ethtool_get_regs_len,
6761 .get_regs = s2io_ethtool_gregs,
6762 .get_link = ethtool_op_get_link,
6763 .get_eeprom_len = s2io_get_eeprom_len,
6764 .get_eeprom = s2io_ethtool_geeprom,
6765 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6766 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6767 .get_pauseparam = s2io_ethtool_getpause_data,
6768 .set_pauseparam = s2io_ethtool_setpause_data,
6769 .get_rx_csum = s2io_ethtool_get_rx_csum,
6770 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6771 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
958de193
JM		 6772 .set_flags = s2io_ethtool_set_flags,
6773 .get_flags = ethtool_op_get_flags,
1da177e4 6774 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6775 .get_tso = s2io_ethtool_op_get_tso,
6776 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6777 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6778 .self_test = s2io_ethtool_test,
6779 .get_strings = s2io_ethtool_get_strings,
6780 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6781 .get_ethtool_stats = s2io_get_ethtool_stats,
6782 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6783};
6784
6785/**
20346722 6786 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6787 * @dev : Device pointer.
6788 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6789 * a proprietary structure used to pass information to the driver.
6790 * @cmd : This is used to distinguish between the different commands that
6791 * can be passed to the IOCTL functions.
6792 * Description:
20346722
K		 6793 * Currently there are no special functionality supported in IOCTL, hence
6794 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6795 */
6796
ac1f60db 6797static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6798{
6799 return -EOPNOTSUPP;
6800}
6801
6802/**
6803 * s2io_change_mtu - entry point to change MTU size for the device.
6804 * @dev : device pointer.
6805 * @new_mtu : the new MTU size for the device.
6806 * Description: A driver entry point to change MTU size for the device.
6807 * Before changing the MTU the device must be stopped.
6808 * Return value:
6809 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6810 * file on failure.
6811 */
6812
ac1f60db 6813static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6814{
4cf1653a 6815 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6816 int ret = 0;
1da177e4
LT		 6817
6818 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
d44570e4 6819 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
1da177e4
LT		 6820 return -EPERM;
6821 }
6822
1da177e4 6823 dev->mtu = new_mtu;
d8892c6e 6824 if (netif_running(dev)) {
3a3d5756 6825 s2io_stop_all_tx_queue(sp);
e6a8fee2 6826 s2io_card_down(sp);
9f74ffde
SH		 6827 ret = s2io_card_up(sp);
6828 if (ret) {
d8892c6e 6829 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6830 __func__);
9f74ffde 6831 return ret;
d8892c6e 6832 }
3a3d5756 6833 s2io_wake_all_tx_queue(sp);
d8892c6e 6834 } else { /* Device is down */
1ee6dd77 6835 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6836 u64 val64 = new_mtu;
6837
6838 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6839 }
1da177e4 6840
9f74ffde 6841 return ret;
1da177e4
LT		 6842}
6843
1da177e4
LT		 6844/**
6845 * s2io_set_link - Set the LInk status
6846 * @data: long pointer to device private structue
6847 * Description: Sets the link status for the adapter
6848 */
6849
c4028958 6850static void s2io_set_link(struct work_struct *work)
1da177e4 6851{
d44570e4
JP		 6852 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6853 set_link_task);
1da177e4 6854 struct net_device *dev = nic->dev;
1ee6dd77 6855 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6856 register u64 val64;
6857 u16 subid;
6858
22747d6b
FR		 6859 rtnl_lock();
6860
6861 if (!netif_running(dev))
6862 goto out_unlock;
6863
92b84437 6864 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6865 /* The card is being reset, no point doing anything */
22747d6b 6866 goto out_unlock;
1da177e4
LT		 6867 }
6868
6869 subid = nic->pdev->subsystem_device;
a371a07d
K		 6870 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6871 /*
6872 * Allow a small delay for the NICs self initiated
6873 * cleanup to complete.
6874 */
6875 msleep(100);
6876 }
1da177e4
LT		 6877
6878 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6879 if (LINK_IS_UP(val64)) {
6880 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6881 if (verify_xena_quiescence(nic)) {
6882 val64 = readq(&bar0->adapter_control);
6883 val64 |= ADAPTER_CNTL_EN;
1da177e4 6884 writeq(val64, &bar0->adapter_control);
19a60522 6885 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
d44570e4 6886 nic->device_type, subid)) {
19a60522
SS		 6887 val64 = readq(&bar0->gpio_control);
6888 val64 |= GPIO_CTRL_GPIO_0;
6889 writeq(val64, &bar0->gpio_control);
6890 val64 = readq(&bar0->gpio_control);
6891 } else {
6892 val64 |= ADAPTER_LED_ON;
6893 writeq(val64, &bar0->adapter_control);
a371a07d 6894 }
f957bcf0 6895 nic->device_enabled_once = true;
19a60522 6896 } else {
9e39f7c5
JP		 6897 DBG_PRINT(ERR_DBG,
6898 "%s: Error: device is not Quiescent\n",
6899 dev->name);
3a3d5756 6900 s2io_stop_all_tx_queue(nic);
1da177e4 6901 }
19a60522 6902 }
92c48799
SS		 6903 val64 = readq(&bar0->adapter_control);
6904 val64 |= ADAPTER_LED_ON;
6905 writeq(val64, &bar0->adapter_control);
6906 s2io_link(nic, LINK_UP);
19a60522
SS		 6907 } else {
6908 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6909 subid)) {
6910 val64 = readq(&bar0->gpio_control);
6911 val64 &= ~GPIO_CTRL_GPIO_0;
6912 writeq(val64, &bar0->gpio_control);
6913 val64 = readq(&bar0->gpio_control);
1da177e4 6914 }
92c48799
SS		 6915 /* turn off LED */
6916 val64 = readq(&bar0->adapter_control);
d44570e4 6917 val64 = val64 & (~ADAPTER_LED_ON);
92c48799 6918 writeq(val64, &bar0->adapter_control);
19a60522 6919 s2io_link(nic, LINK_DOWN);
1da177e4 6920 }
92b84437 6921 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6922
6923out_unlock:
d8d70caf 6924 rtnl_unlock();
1da177e4
LT		 6925}
6926
1ee6dd77 6927static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
d44570e4
JP		 6928 struct buffAdd *ba,
6929 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6930 u64 *temp2, int size)
5d3213cc
AR		 6931{
6932 struct net_device *dev = sp->dev;
491abf25 6933 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6934
6935 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6936 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6937 /* allocate skb */
6938 if (*skb) {
6939 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6940 /*
6941 * As Rx frame are not going to be processed,
6942 * using same mapped address for the Rxd
6943 * buffer pointer
6944 */
6d517a27 6945 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6946 } else {
6947 *skb = dev_alloc_skb(size);
6948 if (!(*skb)) {
9e39f7c5
JP		 6949 DBG_PRINT(INFO_DBG,
6950 "%s: Out of memory to allocate %s\n",
6951 dev->name, "1 buf mode SKBs");
ffb5df6c 6952 stats->mem_alloc_fail_cnt++;
5d3213cc
AR		 6953 return -ENOMEM ;
6954 }
ffb5df6c 6955 stats->mem_allocated += (*skb)->truesize;
5d3213cc
AR		 6956 /* storing the mapped addr in a temp variable
6957 * such it will be used for next rxd whose
6958 * Host Control is NULL
6959 */
6d517a27 6960 rxdp1->Buffer0_ptr = *temp0 =
d44570e4
JP		 6961 pci_map_single(sp->pdev, (*skb)->data,
6962 size - NET_IP_ALIGN,
6963 PCI_DMA_FROMDEVICE);
8d8bb39b 6964 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6965 goto memalloc_failed;
5d3213cc
AR		 6966 rxdp->Host_Control = (unsigned long) (*skb);
6967 }
6968 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6969 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6970 /* Two buffer Mode */
6971 if (*skb) {
6d517a27
VP		 6972 rxdp3->Buffer2_ptr = *temp2;
6973 rxdp3->Buffer0_ptr = *temp0;
6974 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6975 } else {
6976 *skb = dev_alloc_skb(size);
2ceaac75 6977 if (!(*skb)) {
9e39f7c5
JP		 6978 DBG_PRINT(INFO_DBG,
6979 "%s: Out of memory to allocate %s\n",
6980 dev->name,
6981 "2 buf mode SKBs");
ffb5df6c 6982 stats->mem_alloc_fail_cnt++;
2ceaac75
DR		 6983 return -ENOMEM;
6984 }
ffb5df6c 6985 stats->mem_allocated += (*skb)->truesize;
6d517a27 6986 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6987 pci_map_single(sp->pdev, (*skb)->data,
6988 dev->mtu + 4,
6989 PCI_DMA_FROMDEVICE);
8d8bb39b 6990 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6991 goto memalloc_failed;
6d517a27 6992 rxdp3->Buffer0_ptr = *temp0 =
d44570e4
JP		 6993 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6994 PCI_DMA_FROMDEVICE);
8d8bb39b 6995 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6996 rxdp3->Buffer0_ptr)) {
6997 pci_unmap_single(sp->pdev,
6998 (dma_addr_t)rxdp3->Buffer2_ptr,
6999 dev->mtu + 4,
7000 PCI_DMA_FROMDEVICE);
491abf25
VP		 7001 goto memalloc_failed;
7002 }
5d3213cc
AR		 7003 rxdp->Host_Control = (unsigned long) (*skb);
7004
7005 /* Buffer-1 will be dummy buffer not used */
6d517a27 7006 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 7007 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
d44570e4 7008 PCI_DMA_FROMDEVICE);
8d8bb39b 7009 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 7010 rxdp3->Buffer1_ptr)) {
7011 pci_unmap_single(sp->pdev,
7012 (dma_addr_t)rxdp3->Buffer0_ptr,
7013 BUF0_LEN, PCI_DMA_FROMDEVICE);
7014 pci_unmap_single(sp->pdev,
7015 (dma_addr_t)rxdp3->Buffer2_ptr,
7016 dev->mtu + 4,
7017 PCI_DMA_FROMDEVICE);
491abf25
VP		 7018 goto memalloc_failed;
7019 }
5d3213cc
AR		 7020 }
7021 }
7022 return 0;
d44570e4
JP		 7023
7024memalloc_failed:
7025 stats->pci_map_fail_cnt++;
7026 stats->mem_freed += (*skb)->truesize;
7027 dev_kfree_skb(*skb);
7028 return -ENOMEM;
5d3213cc 7029}
491abf25 7030
1ee6dd77
RB		 7031static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
7032 int size)
5d3213cc
AR		 7033{
7034 struct net_device *dev = sp->dev;
7035 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4 7036 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
5d3213cc
AR		 7037 } else if (sp->rxd_mode == RXD_MODE_3B) {
7038 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
7039 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
d44570e4 7040 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
5d3213cc
AR		 7041 }
7042}
7043
1ee6dd77 7044static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 7045{
7046 int i, j, k, blk_cnt = 0, size;
5d3213cc 7047 struct config_param *config = &sp->config;
ffb5df6c 7048 struct mac_info *mac_control = &sp->mac_control;
5d3213cc 7049 struct net_device *dev = sp->dev;
1ee6dd77 7050 struct RxD_t *rxdp = NULL;
5d3213cc 7051 struct sk_buff *skb = NULL;
1ee6dd77 7052 struct buffAdd *ba = NULL;
5d3213cc
AR		 7053 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
7054
7055 /* Calculate the size based on ring mode */
7056 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7057 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7058 if (sp->rxd_mode == RXD_MODE_1)
7059 size += NET_IP_ALIGN;
7060 else if (sp->rxd_mode == RXD_MODE_3B)
7061 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 7062
7063 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7064 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7065 struct ring_info *ring = &mac_control->rings[i];
7066
d44570e4 7067 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
5d3213cc
AR		 7068
7069 for (j = 0; j < blk_cnt; j++) {
7070 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
d44570e4
JP		 7071 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7072 if (sp->rxd_mode == RXD_MODE_3B)
13d866a9 7073 ba = &ring->ba[j][k];
d44570e4
JP		 7074 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7075 (u64 *)&temp0_64,
7076 (u64 *)&temp1_64,
7077 (u64 *)&temp2_64,
7078 size) == -ENOMEM) {
ac1f90d6
SS		 7079 return 0;
7080 }
5d3213cc
AR		 7081
7082 set_rxd_buffer_size(sp, rxdp, size);
7083 wmb();
7084 /* flip the Ownership bit to Hardware */
7085 rxdp->Control_1 |= RXD_OWN_XENA;
7086 }
7087 }
7088 }
7089 return 0;
7090
7091}
7092
d44570e4 7093static int s2io_add_isr(struct s2io_nic *sp)
1da177e4 7094{
e6a8fee2 7095 int ret = 0;
c92ca04b 7096 struct net_device *dev = sp->dev;
e6a8fee2 7097 int err = 0;
1da177e4 7098
eaae7f72 7099 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7100 ret = s2io_enable_msi_x(sp);
7101 if (ret) {
7102 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7103 sp->config.intr_type = INTA;
20346722 7104 }
1da177e4 7105
d44570e4
JP		 7106 /*
7107 * Store the values of the MSIX table in
7108 * the struct s2io_nic structure
7109 */
e6a8fee2 7110 store_xmsi_data(sp);
c92ca04b 7111
e6a8fee2 7112 /* After proper initialization of H/W, register ISR */
eaae7f72 7113 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7114 int i, msix_rx_cnt = 0;
7115
f61e0a35
SH		 7116 for (i = 0; i < sp->num_entries; i++) {
7117 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7118 if (sp->s2io_entries[i].type ==
d44570e4 7119 MSIX_RING_TYPE) {
ac731ab6
SH		 7120 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7121 dev->name, i);
7122 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7123 s2io_msix_ring_handle,
7124 0,
7125 sp->desc[i],
7126 sp->s2io_entries[i].arg);
ac731ab6 7127 } else if (sp->s2io_entries[i].type ==
d44570e4 7128 MSIX_ALARM_TYPE) {
ac731ab6 7129 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
d44570e4 7130 dev->name, i);
ac731ab6 7131 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7132 s2io_msix_fifo_handle,
7133 0,
7134 sp->desc[i],
7135 sp->s2io_entries[i].arg);
ac731ab6 7136
fb6a825b 7137 }
ac731ab6
SH		 7138 /* if either data or addr is zero print it. */
7139 if (!(sp->msix_info[i].addr &&
d44570e4 7140 sp->msix_info[i].data)) {
ac731ab6 7141 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7142 "%s @Addr:0x%llx Data:0x%llx\n",
7143 sp->desc[i],
7144 (unsigned long long)
7145 sp->msix_info[i].addr,
7146 (unsigned long long)
7147 ntohl(sp->msix_info[i].data));
ac731ab6 7148 } else
fb6a825b 7149 msix_rx_cnt++;
ac731ab6
SH		 7150 if (err) {
7151 remove_msix_isr(sp);
7152
7153 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7154 "%s:MSI-X-%d registration "
7155 "failed\n", dev->name, i);
ac731ab6
SH		 7156
7157 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7158 "%s: Defaulting to INTA\n",
7159 dev->name);
ac731ab6
SH		 7160 sp->config.intr_type = INTA;
7161 break;
fb6a825b 7162 }
ac731ab6
SH		 7163 sp->s2io_entries[i].in_use =
7164 MSIX_REGISTERED_SUCCESS;
c92ca04b 7165 }
e6a8fee2 7166 }
18b2b7bd 7167 if (!err) {
6cef2b8e 7168 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
9e39f7c5
JP		 7169 DBG_PRINT(INFO_DBG,
7170 "MSI-X-TX entries enabled through alarm vector\n");
18b2b7bd 7171 }
e6a8fee2 7172 }
eaae7f72 7173 if (sp->config.intr_type == INTA) {
d44570e4
JP		 7174 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7175 sp->name, dev);
e6a8fee2
AR		 7176 if (err) {
7177 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7178 dev->name);
7179 return -1;
7180 }
7181 }
7182 return 0;
7183}
d44570e4
JP		 7184
7185static void s2io_rem_isr(struct s2io_nic *sp)
e6a8fee2 7186{
18b2b7bd
SH		 7187 if (sp->config.intr_type == MSI_X)
7188 remove_msix_isr(sp);
7189 else
7190 remove_inta_isr(sp);
e6a8fee2
AR		 7191}
7192
d44570e4 7193static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
e6a8fee2
AR		 7194{
7195 int cnt = 0;
1ee6dd77 7196 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7197 register u64 val64 = 0;
5f490c96
SH		 7198 struct config_param *config;
7199 config = &sp->config;
e6a8fee2 7200
9f74ffde
SH		 7201 if (!is_s2io_card_up(sp))
7202 return;
7203
e6a8fee2
AR		 7204 del_timer_sync(&sp->alarm_timer);
7205 /* If s2io_set_link task is executing, wait till it completes. */
d44570e4 7206 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
e6a8fee2 7207 msleep(50);
92b84437 7208 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7209
5f490c96 7210 /* Disable napi */
f61e0a35
SH		 7211 if (sp->config.napi) {
7212 int off = 0;
7213 if (config->intr_type == MSI_X) {
7214 for (; off < sp->config.rx_ring_num; off++)
7215 napi_disable(&sp->mac_control.rings[off].napi);
d44570e4 7216 }
f61e0a35
SH		 7217 else
7218 napi_disable(&sp->napi);
7219 }
5f490c96 7220
e6a8fee2 7221 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7222 if (do_io)
7223 stop_nic(sp);
e6a8fee2
AR		 7224
7225 s2io_rem_isr(sp);
1da177e4 7226
01e16faa
SH		 7227 /* stop the tx queue, indicate link down */
7228 s2io_link(sp, LINK_DOWN);
7229
1da177e4 7230 /* Check if the device is Quiescent and then Reset the NIC */
d44570e4 7231 while (do_io) {
5d3213cc
AR		 7232 /* As per the HW requirement we need to replenish the
7233 * receive buffer to avoid the ring bump. Since there is
7234 * no intention of processing the Rx frame at this pointwe are
7235 * just settting the ownership bit of rxd in Each Rx
7236 * ring to HW and set the appropriate buffer size
7237 * based on the ring mode
7238 */
7239 rxd_owner_bit_reset(sp);
7240
1da177e4 7241 val64 = readq(&bar0->adapter_status);
19a60522 7242 if (verify_xena_quiescence(sp)) {
d44570e4
JP		 7243 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7244 break;
1da177e4
LT		 7245 }
7246
7247 msleep(50);
7248 cnt++;
7249 if (cnt == 10) {
9e39f7c5
JP		 7250 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7251 "adapter status reads 0x%llx\n",
d44570e4 7252 (unsigned long long)val64);
1da177e4
LT		 7253 break;
7254 }
d796fdb7
LV		 7255 }
7256 if (do_io)
7257 s2io_reset(sp);
1da177e4 7258
7ba013ac 7259 /* Free all Tx buffers */
1da177e4 7260 free_tx_buffers(sp);
7ba013ac
K		 7261
7262 /* Free all Rx buffers */
1da177e4
LT		 7263 free_rx_buffers(sp);
7264
92b84437 7265 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7266}
7267
d44570e4 7268static void s2io_card_down(struct s2io_nic *sp)
d796fdb7
LV		 7269{
7270 do_s2io_card_down(sp, 1);
7271}
7272
d44570e4 7273static int s2io_card_up(struct s2io_nic *sp)
1da177e4 7274{
cc6e7c44 7275 int i, ret = 0;
1da177e4 7276 struct config_param *config;
ffb5df6c 7277 struct mac_info *mac_control;
d44570e4 7278 struct net_device *dev = (struct net_device *)sp->dev;
e6a8fee2 7279 u16 interruptible;
1da177e4
LT		 7280
7281 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7282 ret = init_nic(sp);
7283 if (ret != 0) {
1da177e4
LT		 7284 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7285 dev->name);
9f74ffde
SH		 7286 if (ret != -EIO)
7287 s2io_reset(sp);
7288 return ret;
1da177e4
LT		 7289 }
7290
20346722
K		 7291 /*
7292 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7293 * Rx ring and initializing buffers into 30 Rx blocks
7294 */
1da177e4 7295 config = &sp->config;
ffb5df6c 7296 mac_control = &sp->mac_control;
1da177e4
LT		 7297
7298 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7299 struct ring_info *ring = &mac_control->rings[i];
7300
7301 ring->mtu = dev->mtu;
958de193 7302 ring->lro = sp->lro;
13d866a9 7303 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7304 if (ret) {
1da177e4
LT		 7305 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7306 dev->name);
7307 s2io_reset(sp);
7308 free_rx_buffers(sp);
7309 return -ENOMEM;
7310 }
7311 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7312 ring->rx_bufs_left);
1da177e4 7313 }
5f490c96
SH		 7314
7315 /* Initialise napi */
f61e0a35 7316 if (config->napi) {
f61e0a35
SH		 7317 if (config->intr_type == MSI_X) {
7318 for (i = 0; i < sp->config.rx_ring_num; i++)
7319 napi_enable(&sp->mac_control.rings[i].napi);
7320 } else {
7321 napi_enable(&sp->napi);
7322 }
7323 }
5f490c96 7324
19a60522
SS		 7325 /* Maintain the state prior to the open */
7326 if (sp->promisc_flg)
7327 sp->promisc_flg = 0;
7328 if (sp->m_cast_flg) {
7329 sp->m_cast_flg = 0;
d44570e4 7330 sp->all_multi_pos = 0;
19a60522 7331 }
1da177e4
LT		 7332
7333 /* Setting its receive mode */
7334 s2io_set_multicast(dev);
7335
7d3d0439 7336 if (sp->lro) {
b41477f3 7337 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439 7338 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
d44570e4 7339 /* Check if we can use (if specified) user provided value */
7d3d0439
RA		 7340 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7341 sp->lro_max_aggr_per_sess = lro_max_pkts;
7342 }
7343
1da177e4
LT		 7344 /* Enable Rx Traffic and interrupts on the NIC */
7345 if (start_nic(sp)) {
7346 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7347 s2io_reset(sp);
e6a8fee2
AR		 7348 free_rx_buffers(sp);
7349 return -ENODEV;
7350 }
7351
7352 /* Add interrupt service routine */
7353 if (s2io_add_isr(sp) != 0) {
eaae7f72 7354 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7355 s2io_rem_isr(sp);
7356 s2io_reset(sp);
1da177e4
LT		 7357 free_rx_buffers(sp);
7358 return -ENODEV;
7359 }
7360
25fff88e
K		 7361 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7362
01e16faa
SH		 7363 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7364
e6a8fee2 7365 /* Enable select interrupts */
9caab458 7366 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7367 if (sp->config.intr_type != INTA) {
7368 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7369 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7370 } else {
e6a8fee2 7371 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7372 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7373 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7374 }
7375
1da177e4
LT		 7376 return 0;
7377}
7378
20346722 7379/**
1da177e4
LT		 7380 * s2io_restart_nic - Resets the NIC.
7381 * @data : long pointer to the device private structure
7382 * Description:
7383 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7384 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7385 * the run time of the watch dog routine which is run holding a
7386 * spin lock.
7387 */
7388
c4028958 7389static void s2io_restart_nic(struct work_struct *work)
1da177e4 7390{
1ee6dd77 7391 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7392 struct net_device *dev = sp->dev;
1da177e4 7393
22747d6b
FR		 7394 rtnl_lock();
7395
7396 if (!netif_running(dev))
7397 goto out_unlock;
7398
e6a8fee2 7399 s2io_card_down(sp);
1da177e4 7400 if (s2io_card_up(sp)) {
d44570e4 7401 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
1da177e4 7402 }
3a3d5756 7403 s2io_wake_all_tx_queue(sp);
d44570e4 7404 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
22747d6b
FR		 7405out_unlock:
7406 rtnl_unlock();
1da177e4
LT		 7407}
7408
20346722
K		 7409/**
7410 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7411 * @dev : Pointer to net device structure
7412 * Description:
7413 * This function is triggered if the Tx Queue is stopped
7414 * for a pre-defined amount of time when the Interface is still up.
7415 * If the Interface is jammed in such a situation, the hardware is
7416 * reset (by s2io_close) and restarted again (by s2io_open) to
7417 * overcome any problem that might have been caused in the hardware.
7418 * Return value:
7419 * void
7420 */
7421
7422static void s2io_tx_watchdog(struct net_device *dev)
7423{
4cf1653a 7424 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 7425 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7426
7427 if (netif_carrier_ok(dev)) {
ffb5df6c 7428 swstats->watchdog_timer_cnt++;
1da177e4 7429 schedule_work(&sp->rst_timer_task);
ffb5df6c 7430 swstats->soft_reset_cnt++;
1da177e4
LT		 7431 }
7432}
7433
7434/**
7435 * rx_osm_handler - To perform some OS related operations on SKB.
7436 * @sp: private member of the device structure,pointer to s2io_nic structure.
7437 * @skb : the socket buffer pointer.
7438 * @len : length of the packet
7439 * @cksum : FCS checksum of the frame.
7440 * @ring_no : the ring from which this RxD was extracted.
20346722 7441 * Description:
b41477f3 7442 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7443 * some OS related operations on the SKB before passing it to the upper
7444 * layers. It mainly checks if the checksum is OK, if so adds it to the
7445 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7446 * to the upper layer. If the checksum is wrong, it increments the Rx
7447 * packet error count, frees the SKB and returns error.
7448 * Return value:
7449 * SUCCESS on success and -1 on failure.
7450 */
1ee6dd77 7451static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7452{
1ee6dd77 7453 struct s2io_nic *sp = ring_data->nic;
d44570e4 7454 struct net_device *dev = (struct net_device *)ring_data->dev;
20346722 7455 struct sk_buff *skb = (struct sk_buff *)
d44570e4 7456 ((unsigned long)rxdp->Host_Control);
20346722 7457 int ring_no = ring_data->ring_no;
1da177e4 7458 u16 l3_csum, l4_csum;
863c11a9 7459 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7460 struct lro *uninitialized_var(lro);
f9046eb3 7461 u8 err_mask;
ffb5df6c 7462 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
da6971d8 7463
20346722 7464 skb->dev = dev;
c92ca04b 7465
863c11a9 7466 if (err) {
bd1034f0 7467 /* Check for parity error */
d44570e4 7468 if (err & 0x1)
ffb5df6c 7469 swstats->parity_err_cnt++;
d44570e4 7470
f9046eb3 7471 err_mask = err >> 48;
d44570e4
JP		 7472 switch (err_mask) {
7473 case 1:
ffb5df6c 7474 swstats->rx_parity_err_cnt++;
491976b2
SH		 7475 break;
7476
d44570e4 7477 case 2:
ffb5df6c 7478 swstats->rx_abort_cnt++;
491976b2
SH		 7479 break;
7480
d44570e4 7481 case 3:
ffb5df6c 7482 swstats->rx_parity_abort_cnt++;
491976b2
SH		 7483 break;
7484
d44570e4 7485 case 4:
ffb5df6c 7486 swstats->rx_rda_fail_cnt++;
491976b2
SH		 7487 break;
7488
d44570e4 7489 case 5:
ffb5df6c 7490 swstats->rx_unkn_prot_cnt++;
491976b2
SH		 7491 break;
7492
d44570e4 7493 case 6:
ffb5df6c 7494 swstats->rx_fcs_err_cnt++;
491976b2 7495 break;
bd1034f0 7496
d44570e4 7497 case 7:
ffb5df6c 7498 swstats->rx_buf_size_err_cnt++;
491976b2
SH		 7499 break;
7500
d44570e4 7501 case 8:
ffb5df6c 7502 swstats->rx_rxd_corrupt_cnt++;
491976b2
SH		 7503 break;
7504
d44570e4 7505 case 15:
ffb5df6c 7506 swstats->rx_unkn_err_cnt++;
491976b2
SH		 7507 break;
7508 }
863c11a9 7509 /*
d44570e4
JP		 7510 * Drop the packet if bad transfer code. Exception being
7511 * 0x5, which could be due to unsupported IPv6 extension header.
7512 * In this case, we let stack handle the packet.
7513 * Note that in this case, since checksum will be incorrect,
7514 * stack will validate the same.
7515 */
f9046eb3
OH		 7516 if (err_mask != 0x5) {
7517 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
d44570e4 7518 dev->name, err_mask);
dc56e634 7519 dev->stats.rx_crc_errors++;
ffb5df6c 7520 swstats->mem_freed
491976b2 7521 += skb->truesize;
863c11a9 7522 dev_kfree_skb(skb);
0425b46a 7523 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7524 rxdp->Host_Control = 0;
7525 return 0;
7526 }
20346722 7527 }
1da177e4 7528
20346722 7529 rxdp->Host_Control = 0;
da6971d8
AR		 7530 if (sp->rxd_mode == RXD_MODE_1) {
7531 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7532
da6971d8 7533 skb_put(skb, len);
6d517a27 7534 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7535 int get_block = ring_data->rx_curr_get_info.block_index;
7536 int get_off = ring_data->rx_curr_get_info.offset;
7537 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7538 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7539 unsigned char *buff = skb_push(skb, buf0_len);
7540
1ee6dd77 7541 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8 7542 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7543 skb_put(skb, buf2_len);
da6971d8 7544 }
20346722 7545
d44570e4
JP		 7546 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7547 ((!ring_data->lro) ||
7548 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 7549 (sp->rx_csum)) {
7550 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7551 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7552 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7553 /*
1da177e4
LT		 7554 * NIC verifies if the Checksum of the received
7555 * frame is Ok or not and accordingly returns
7556 * a flag in the RxD.
7557 */
7558 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7559 if (ring_data->lro) {
7d3d0439
RA		 7560 u32 tcp_len;
7561 u8 *tcp;
7562 int ret = 0;
7563
0425b46a 7564 ret = s2io_club_tcp_session(ring_data,
d44570e4
JP		 7565 skb->data, &tcp,
7566 &tcp_len, &lro,
7567 rxdp, sp);
7d3d0439 7568 switch (ret) {
d44570e4
JP		 7569 case 3: /* Begin anew */
7570 lro->parent = skb;
7571 goto aggregate;
7572 case 1: /* Aggregate */
7573 lro_append_pkt(sp, lro, skb, tcp_len);
7574 goto aggregate;
7575 case 4: /* Flush session */
7576 lro_append_pkt(sp, lro, skb, tcp_len);
7577 queue_rx_frame(lro->parent,
7578 lro->vlan_tag);
7579 clear_lro_session(lro);
ffb5df6c 7580 swstats->flush_max_pkts++;
d44570e4
JP		 7581 goto aggregate;
7582 case 2: /* Flush both */
7583 lro->parent->data_len = lro->frags_len;
ffb5df6c 7584 swstats->sending_both++;
d44570e4
JP		 7585 queue_rx_frame(lro->parent,
7586 lro->vlan_tag);
7587 clear_lro_session(lro);
7588 goto send_up;
7589 case 0: /* sessions exceeded */
7590 case -1: /* non-TCP or not L2 aggregatable */
7591 case 5: /*
7592 * First pkt in session not
7593 * L3/L4 aggregatable
7594 */
7595 break;
7596 default:
7597 DBG_PRINT(ERR_DBG,
7598 "%s: Samadhana!!\n",
7599 __func__);
7600 BUG();
7d3d0439
RA		 7601 }
7602 }
1da177e4 7603 } else {
20346722
K		 7604 /*
7605 * Packet with erroneous checksum, let the
1da177e4
LT		 7606 * upper layers deal with it.
7607 */
7608 skb->ip_summed = CHECKSUM_NONE;
7609 }
cdb5bf02 7610 } else
1da177e4 7611 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7612
ffb5df6c 7613 swstats->mem_freed += skb->truesize;
7d3d0439 7614send_up:
0c8dfc83 7615 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7616 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7617aggregate:
0425b46a 7618 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7619 return SUCCESS;
7620}
7621
7622/**
7623 * s2io_link - stops/starts the Tx queue.
7624 * @sp : private member of the device structure, which is a pointer to the
7625 * s2io_nic structure.
7626 * @link : inidicates whether link is UP/DOWN.
7627 * Description:
7628 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7629 * status of the NIC is is down or up. This is called by the Alarm
7630 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7631 * Return value:
7632 * void.
7633 */
7634
d44570e4 7635static void s2io_link(struct s2io_nic *sp, int link)
1da177e4 7636{
d44570e4 7637 struct net_device *dev = (struct net_device *)sp->dev;
ffb5df6c 7638 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7639
7640 if (link != sp->last_link_state) {
b7c5678f 7641 init_tti(sp, link);
1da177e4
LT		 7642 if (link == LINK_DOWN) {
7643 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7644 s2io_stop_all_tx_queue(sp);
1da177e4 7645 netif_carrier_off(dev);
ffb5df6c
JP		 7646 if (swstats->link_up_cnt)
7647 swstats->link_up_time =
7648 jiffies - sp->start_time;
7649 swstats->link_down_cnt++;
1da177e4
LT		 7650 } else {
7651 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
ffb5df6c
JP		 7652 if (swstats->link_down_cnt)
7653 swstats->link_down_time =
d44570e4 7654 jiffies - sp->start_time;
ffb5df6c 7655 swstats->link_up_cnt++;
1da177e4 7656 netif_carrier_on(dev);
3a3d5756 7657 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7658 }
7659 }
7660 sp->last_link_state = link;
491976b2 7661 sp->start_time = jiffies;
1da177e4
LT		 7662}
7663
20346722
K		 7664/**
7665 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7666 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7667 * s2io_nic structure.
7668 * Description:
7669 * This function initializes a few of the PCI and PCI-X configuration registers
7670 * with recommended values.
7671 * Return value:
7672 * void
7673 */
7674
d44570e4 7675static void s2io_init_pci(struct s2io_nic *sp)
1da177e4 7676{
20346722 7677 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7678
7679 /* Enable Data Parity Error Recovery in PCI-X command register. */
7680 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7681 &(pcix_cmd));
1da177e4 7682 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7683 (pcix_cmd | 1));
1da177e4 7684 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7685 &(pcix_cmd));
1da177e4
LT		 7686
7687 /* Set the PErr Response bit in PCI command register. */
7688 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7689 pci_write_config_word(sp->pdev, PCI_COMMAND,
7690 (pci_cmd | PCI_COMMAND_PARITY));
7691 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7692}
7693
3a3d5756 7694static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
d44570e4 7695 u8 *dev_multiq)
9dc737a7 7696{
d44570e4 7697 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
9e39f7c5 7698 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
d44570e4 7699 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7700
7701 if (tx_fifo_num < 1)
7702 tx_fifo_num = 1;
7703 else
7704 tx_fifo_num = MAX_TX_FIFOS;
7705
9e39f7c5 7706 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
9dc737a7 7707 }
2fda096d 7708
6cfc482b 7709 if (multiq)
3a3d5756 7710 *dev_multiq = multiq;
6cfc482b
SH		 7711
7712 if (tx_steering_type && (1 == tx_fifo_num)) {
7713 if (tx_steering_type != TX_DEFAULT_STEERING)
7714 DBG_PRINT(ERR_DBG,
9e39f7c5 7715 "Tx steering is not supported with "
d44570e4 7716 "one fifo. Disabling Tx steering.\n");
6cfc482b
SH		 7717 tx_steering_type = NO_STEERING;
7718 }
7719
7720 if ((tx_steering_type < NO_STEERING) ||
d44570e4
JP		 7721 (tx_steering_type > TX_DEFAULT_STEERING)) {
7722 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7723 "Requested transmit steering not supported\n");
7724 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
6cfc482b 7725 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7726 }
7727
0425b46a 7728 if (rx_ring_num > MAX_RX_RINGS) {
d44570e4 7729 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7730 "Requested number of rx rings not supported\n");
7731 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
d44570e4 7732 MAX_RX_RINGS);
0425b46a 7733 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7734 }
0425b46a 7735
eccb8628 7736 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9e39f7c5 7737 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
9dc737a7
AR		 7738 "Defaulting to INTA\n");
7739 *dev_intr_type = INTA;
7740 }
596c5c97 7741
9dc737a7 7742 if ((*dev_intr_type == MSI_X) &&
d44570e4
JP		 7743 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7744 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
9e39f7c5 7745 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
d44570e4 7746 "Defaulting to INTA\n");
9dc737a7
AR		 7747 *dev_intr_type = INTA;
7748 }
fb6a825b 7749
6d517a27 7750 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9e39f7c5
JP		 7751 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7752 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
6d517a27 7753 rx_ring_mode = 1;
9dc737a7
AR		 7754 }
7755 return SUCCESS;
7756}
7757
9fc93a41
SS		 7758/**
7759 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7760 * or Traffic class respectively.
b7c5678f 7761 * @nic: device private variable
9fc93a41
SS		 7762 * Description: The function configures the receive steering to
7763 * desired receive ring.
7764 * Return Value: SUCCESS on success and
7765 * '-1' on failure (endian settings incorrect).
7766 */
7767static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7768{
7769 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7770 register u64 val64 = 0;
7771
7772 if (ds_codepoint > 63)
7773 return FAILURE;
7774
7775 val64 = RTS_DS_MEM_DATA(ring);
7776 writeq(val64, &bar0->rts_ds_mem_data);
7777
7778 val64 = RTS_DS_MEM_CTRL_WE |
7779 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7780 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7781
7782 writeq(val64, &bar0->rts_ds_mem_ctrl);
7783
7784 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
d44570e4
JP		 7785 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7786 S2IO_BIT_RESET);
9fc93a41
SS		 7787}
7788
04025095
SH		 7789static const struct net_device_ops s2io_netdev_ops = {
7790 .ndo_open = s2io_open,
7791 .ndo_stop = s2io_close,
7792 .ndo_get_stats = s2io_get_stats,
7793 .ndo_start_xmit = s2io_xmit,
7794 .ndo_validate_addr = eth_validate_addr,
7795 .ndo_set_multicast_list = s2io_set_multicast,
7796 .ndo_do_ioctl = s2io_ioctl,
7797 .ndo_set_mac_address = s2io_set_mac_addr,
7798 .ndo_change_mtu = s2io_change_mtu,
7799 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7800 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7801 .ndo_tx_timeout = s2io_tx_watchdog,
7802#ifdef CONFIG_NET_POLL_CONTROLLER
7803 .ndo_poll_controller = s2io_netpoll,
7804#endif
7805};
7806
1da177e4 7807/**
20346722 7808 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7809 * @pdev : structure containing the PCI related information of the device.
7810 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7811 * Description:
7812 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7813 * All OS related initialization including memory and device structure and
7814 * initlaization of the device private variable is done. Also the swapper
7815 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7816 * registers of the device.
7817 * Return value:
7818 * returns 0 on success and negative on failure.
7819 */
7820
7821static int __devinit
7822s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7823{
1ee6dd77 7824 struct s2io_nic *sp;
1da177e4 7825 struct net_device *dev;
1da177e4 7826 int i, j, ret;
f957bcf0 7827 int dma_flag = false;
1da177e4
LT		 7828 u32 mac_up, mac_down;
7829 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7830 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7831 u16 subid;
1da177e4 7832 struct config_param *config;
ffb5df6c 7833 struct mac_info *mac_control;
541ae68f 7834 int mode;
cc6e7c44 7835 u8 dev_intr_type = intr_type;
3a3d5756 7836 u8 dev_multiq = 0;
1da177e4 7837
3a3d5756
SH		 7838 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7839 if (ret)
9dc737a7 7840 return ret;
1da177e4 7841
d44570e4
JP		 7842 ret = pci_enable_device(pdev);
7843 if (ret) {
1da177e4 7844 DBG_PRINT(ERR_DBG,
9e39f7c5 7845 "%s: pci_enable_device failed\n", __func__);
1da177e4
LT		 7846 return ret;
7847 }
7848
6a35528a 7849 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
9e39f7c5 7850 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
f957bcf0 7851 dma_flag = true;
d44570e4 7852 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7853 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7854 "Unable to obtain 64bit DMA "
7855 "for consistent allocations\n");
1da177e4
LT		 7856 pci_disable_device(pdev);
7857 return -ENOMEM;
7858 }
284901a9 7859 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
9e39f7c5 7860 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
1da177e4
LT		 7861 } else {
7862 pci_disable_device(pdev);
7863 return -ENOMEM;
7864 }
d44570e4
JP		 7865 ret = pci_request_regions(pdev, s2io_driver_name);
7866 if (ret) {
9e39f7c5 7867 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
d44570e4 7868 __func__, ret);
eccb8628
VP		 7869 pci_disable_device(pdev);
7870 return -ENODEV;
1da177e4 7871 }
3a3d5756 7872 if (dev_multiq)
6cfc482b 7873 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7874 else
b19fa1fa 7875 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7876 if (dev == NULL) {
7877 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7878 pci_disable_device(pdev);
7879 pci_release_regions(pdev);
7880 return -ENODEV;
7881 }
7882
7883 pci_set_master(pdev);
7884 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7885 SET_NETDEV_DEV(dev, &pdev->dev);
7886
7887 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7888 sp = netdev_priv(dev);
1ee6dd77 7889 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7890 sp->dev = dev;
7891 sp->pdev = pdev;
1da177e4 7892 sp->high_dma_flag = dma_flag;
f957bcf0 7893 sp->device_enabled_once = false;
da6971d8
AR		 7894 if (rx_ring_mode == 1)
7895 sp->rxd_mode = RXD_MODE_1;
7896 if (rx_ring_mode == 2)
7897 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7898
eaae7f72 7899 sp->config.intr_type = dev_intr_type;
1da177e4 7900
541ae68f 7901 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
d44570e4 7902 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
541ae68f
K		 7903 sp->device_type = XFRAME_II_DEVICE;
7904 else
7905 sp->device_type = XFRAME_I_DEVICE;
7906
43b7c451 7907 sp->lro = lro_enable;
6aa20a22 7908
1da177e4
LT		 7909 /* Initialize some PCI/PCI-X fields of the NIC. */
7910 s2io_init_pci(sp);
7911
20346722 7912 /*
1da177e4 7913 * Setting the device configuration parameters.
20346722
K		 7914 * Most of these parameters can be specified by the user during
7915 * module insertion as they are module loadable parameters. If
7916 * these parameters are not not specified during load time, they
1da177e4
LT		 7917 * are initialized with default values.
7918 */
1da177e4 7919 config = &sp->config;
ffb5df6c 7920 mac_control = &sp->mac_control;
1da177e4 7921
596c5c97 7922 config->napi = napi;
6cfc482b 7923 config->tx_steering_type = tx_steering_type;
596c5c97 7924
1da177e4 7925 /* Tx side parameters. */
6cfc482b
SH		 7926 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7927 config->tx_fifo_num = MAX_TX_FIFOS;
7928 else
7929 config->tx_fifo_num = tx_fifo_num;
7930
7931 /* Initialize the fifos used for tx steering */
7932 if (config->tx_fifo_num < 5) {
d44570e4
JP		 7933 if (config->tx_fifo_num == 1)
7934 sp->total_tcp_fifos = 1;
7935 else
7936 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7937 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7938 sp->total_udp_fifos = 1;
7939 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
6cfc482b
SH		 7940 } else {
7941 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
d44570e4 7942 FIFO_OTHER_MAX_NUM);
6cfc482b
SH		 7943 sp->udp_fifo_idx = sp->total_tcp_fifos;
7944 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7945 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7946 }
7947
3a3d5756 7948 config->multiq = dev_multiq;
6cfc482b 7949 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7950 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7951
7952 tx_cfg->fifo_len = tx_fifo_len[i];
7953 tx_cfg->fifo_priority = i;
1da177e4
LT		 7954 }
7955
20346722
K		 7956 /* mapping the QoS priority to the configured fifos */
7957 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7958 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7959
6cfc482b
SH		 7960 /* map the hashing selector table to the configured fifos */
7961 for (i = 0; i < config->tx_fifo_num; i++)
7962 sp->fifo_selector[i] = fifo_selector[i];
7963
7964
1da177e4
LT		 7965 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7966 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7967 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7968
7969 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7970 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7971 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7972 break;
7973 }
7974 }
fed5eccd
AR		 7975 /* + 2 because one Txd for skb->data and one Txd for UFO */
7976 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7977
7978 /* Rx side parameters. */
1da177e4 7979 config->rx_ring_num = rx_ring_num;
0425b46a 7980 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7981 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7982 struct ring_info *ring = &mac_control->rings[i];
7983
7984 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7985 rx_cfg->ring_priority = i;
7986 ring->rx_bufs_left = 0;
7987 ring->rxd_mode = sp->rxd_mode;
7988 ring->rxd_count = rxd_count[sp->rxd_mode];
7989 ring->pdev = sp->pdev;
7990 ring->dev = sp->dev;
1da177e4
LT		 7991 }
7992
7993 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7994 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7995
7996 rx_cfg->ring_org = RING_ORG_BUFF1;
7997 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7998 }
7999
8000 /* Setting Mac Control parameters */
8001 mac_control->rmac_pause_time = rmac_pause_time;
8002 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
8003 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
8004
8005
1da177e4
LT		 8006 /* initialize the shared memory used by the NIC and the host */
8007 if (init_shared_mem(sp)) {
d44570e4 8008 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
1da177e4
LT		 8009 ret = -ENOMEM;
8010 goto mem_alloc_failed;
8011 }
8012
275f165f 8013 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 8014 if (!sp->bar0) {
19a60522 8015 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 8016 dev->name);
8017 ret = -ENOMEM;
8018 goto bar0_remap_failed;
8019 }
8020
275f165f 8021 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 8022 if (!sp->bar1) {
19a60522 8023 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 8024 dev->name);
8025 ret = -ENOMEM;
8026 goto bar1_remap_failed;
8027 }
8028
8029 dev->irq = pdev->irq;
d44570e4 8030 dev->base_addr = (unsigned long)sp->bar0;
1da177e4
LT		 8031
8032 /* Initializing the BAR1 address as the start of the FIFO pointer. */
8033 for (j = 0; j < MAX_TX_FIFOS; j++) {
d44570e4
JP		 8034 mac_control->tx_FIFO_start[j] =
8035 (struct TxFIFO_element __iomem *)
8036 (sp->bar1 + (j * 0x00020000));
1da177e4
LT		 8037 }
8038
8039 /* Driver entry points */
04025095 8040 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 8041 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 8042 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
958de193
JM		 8043 if (lro_enable)
8044 dev->features |= NETIF_F_LRO;
1da177e4 8045 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f957bcf0 8046 if (sp->high_dma_flag == true)
1da177e4 8047 dev->features |= NETIF_F_HIGHDMA;
1da177e4 8048 dev->features |= NETIF_F_TSO;
f83ef8c0 8049 dev->features |= NETIF_F_TSO6;
db874e65 8050 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 8051 dev->features |= NETIF_F_UFO;
8052 dev->features |= NETIF_F_HW_CSUM;
8053 }
1da177e4 8054 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 8055 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8056 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 8057
e960fc5c 8058 pci_save_state(sp->pdev);
1da177e4
LT		 8059
8060 /* Setting swapper control on the NIC, for proper reset operation */
8061 if (s2io_set_swapper(sp)) {
9e39f7c5 8062 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
1da177e4
LT		 8063 dev->name);
8064 ret = -EAGAIN;
8065 goto set_swap_failed;
8066 }
8067
541ae68f
K		 8068 /* Verify if the Herc works on the slot its placed into */
8069 if (sp->device_type & XFRAME_II_DEVICE) {
8070 mode = s2io_verify_pci_mode(sp);
8071 if (mode < 0) {
9e39f7c5
JP		 8072 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8073 __func__);
541ae68f
K		 8074 ret = -EBADSLT;
8075 goto set_swap_failed;
8076 }
8077 }
8078
f61e0a35
SH		 8079 if (sp->config.intr_type == MSI_X) {
8080 sp->num_entries = config->rx_ring_num + 1;
8081 ret = s2io_enable_msi_x(sp);
8082
8083 if (!ret) {
8084 ret = s2io_test_msi(sp);
8085 /* rollback MSI-X, will re-enable during add_isr() */
8086 remove_msix_isr(sp);
8087 }
8088 if (ret) {
8089
8090 DBG_PRINT(ERR_DBG,
9e39f7c5 8091 "MSI-X requested but failed to enable\n");
f61e0a35
SH		 8092 sp->config.intr_type = INTA;
8093 }
8094 }
8095
8096 if (config->intr_type == MSI_X) {
13d866a9
JP		 8097 for (i = 0; i < config->rx_ring_num ; i++) {
8098 struct ring_info *ring = &mac_control->rings[i];
8099
8100 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8101 }
f61e0a35
SH		 8102 } else {
8103 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8104 }
8105
541ae68f
K		 8106 /* Not needed for Herc */
8107 if (sp->device_type & XFRAME_I_DEVICE) {
8108 /*
8109 * Fix for all "FFs" MAC address problems observed on
8110 * Alpha platforms
8111 */
8112 fix_mac_address(sp);
8113 s2io_reset(sp);
8114 }
1da177e4
LT		 8115
8116 /*
1da177e4
LT		 8117 * MAC address initialization.
8118 * For now only one mac address will be read and used.
8119 */
8120 bar0 = sp->bar0;
8121 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
d44570e4 8122 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8123 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8124 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 8125 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8126 S2IO_BIT_RESET);
1da177e4 8127 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4 8128 mac_down = (u32)tmp64;
1da177e4
LT		 8129 mac_up = (u32) (tmp64 >> 32);
8130
1da177e4
LT		 8131 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8132 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8133 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8134 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8135 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8136 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8137
1da177e4
LT		 8138 /* Set the factory defined MAC address initially */
8139 dev->addr_len = ETH_ALEN;
8140 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8141 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8142
faa4f796
SH		 8143 /* initialize number of multicast & unicast MAC entries variables */
8144 if (sp->device_type == XFRAME_I_DEVICE) {
8145 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8146 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8147 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8148 } else if (sp->device_type == XFRAME_II_DEVICE) {
8149 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8150 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8151 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8152 }
8153
8154 /* store mac addresses from CAM to s2io_nic structure */
8155 do_s2io_store_unicast_mc(sp);
8156
f61e0a35
SH		 8157 /* Configure MSIX vector for number of rings configured plus one */
8158 if ((sp->device_type == XFRAME_II_DEVICE) &&
d44570e4 8159 (config->intr_type == MSI_X))
f61e0a35
SH		 8160 sp->num_entries = config->rx_ring_num + 1;
8161
d44570e4 8162 /* Store the values of the MSIX table in the s2io_nic structure */
c77dd43e 8163 store_xmsi_data(sp);
b41477f3
AR		 8164 /* reset Nic and bring it to known state */
8165 s2io_reset(sp);
8166
1da177e4 8167 /*
99993af6 8168 * Initialize link state flags
541ae68f 8169 * and the card state parameter
1da177e4 8170 */
92b84437 8171 sp->state = 0;
1da177e4 8172
1da177e4 8173 /* Initialize spinlocks */
13d866a9
JP		 8174 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8175 struct fifo_info *fifo = &mac_control->fifos[i];
8176
8177 spin_lock_init(&fifo->tx_lock);
8178 }
db874e65 8179
20346722
K		 8180 /*
8181 * SXE-002: Configure link and activity LED to init state
8182 * on driver load.
1da177e4
LT		 8183 */
8184 subid = sp->pdev->subsystem_device;
8185 if ((subid & 0xFF) >= 0x07) {
8186 val64 = readq(&bar0->gpio_control);
8187 val64 |= 0x0000800000000000ULL;
8188 writeq(val64, &bar0->gpio_control);
8189 val64 = 0x0411040400000000ULL;
d44570e4 8190 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 8191 val64 = readq(&bar0->gpio_control);
8192 }
8193
8194 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8195
8196 if (register_netdev(dev)) {
8197 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8198 ret = -ENODEV;
8199 goto register_failed;
8200 }
9dc737a7 8201 s2io_vpd_read(sp);
926bd900 8202 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
d44570e4 8203 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
44c10138 8204 sp->product_name, pdev->revision);
b41477f3
AR		 8205 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8206 s2io_driver_version);
9e39f7c5
JP		 8207 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8208 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
9dc737a7 8209 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8210 mode = s2io_print_pci_mode(sp);
541ae68f 8211 if (mode < 0) {
541ae68f 8212 ret = -EBADSLT;
9dc737a7 8213 unregister_netdev(dev);
541ae68f
K		 8214 goto set_swap_failed;
8215 }
541ae68f 8216 }
d44570e4
JP		 8217 switch (sp->rxd_mode) {
8218 case RXD_MODE_1:
8219 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8220 dev->name);
8221 break;
8222 case RXD_MODE_3B:
8223 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8224 dev->name);
8225 break;
9dc737a7 8226 }
db874e65 8227
f61e0a35
SH		 8228 switch (sp->config.napi) {
8229 case 0:
8230 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8231 break;
8232 case 1:
db874e65 8233 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8234 break;
8235 }
3a3d5756
SH		 8236
8237 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
d44570e4 8238 sp->config.tx_fifo_num);
3a3d5756 8239
0425b46a
SH		 8240 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8241 sp->config.rx_ring_num);
8242
d44570e4
JP		 8243 switch (sp->config.intr_type) {
8244 case INTA:
8245 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8246 break;
8247 case MSI_X:
8248 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8249 break;
9dc737a7 8250 }
3a3d5756 8251 if (sp->config.multiq) {
13d866a9
JP		 8252 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8253 struct fifo_info *fifo = &mac_control->fifos[i];
8254
8255 fifo->multiq = config->multiq;
8256 }
3a3d5756 8257 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
d44570e4 8258 dev->name);
3a3d5756
SH		 8259 } else
8260 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
d44570e4 8261 dev->name);
3a3d5756 8262
6cfc482b
SH		 8263 switch (sp->config.tx_steering_type) {
8264 case NO_STEERING:
d44570e4
JP		 8265 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8266 dev->name);
8267 break;
6cfc482b 8268 case TX_PRIORITY_STEERING:
d44570e4
JP		 8269 DBG_PRINT(ERR_DBG,
8270 "%s: Priority steering enabled for transmit\n",
8271 dev->name);
6cfc482b
SH		 8272 break;
8273 case TX_DEFAULT_STEERING:
d44570e4
JP		 8274 DBG_PRINT(ERR_DBG,
8275 "%s: Default steering enabled for transmit\n",
8276 dev->name);
6cfc482b
SH		 8277 }
8278
7d3d0439
RA		 8279 if (sp->lro)
8280 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8281 dev->name);
db874e65 8282 if (ufo)
d44570e4
JP		 8283 DBG_PRINT(ERR_DBG,
8284 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8285 dev->name);
7ba013ac 8286 /* Initialize device name */
9dc737a7 8287 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8288
cd0fce03
BL		 8289 if (vlan_tag_strip)
8290 sp->vlan_strip_flag = 1;
8291 else
8292 sp->vlan_strip_flag = 0;
8293
20346722
K		 8294 /*
8295 * Make Link state as off at this point, when the Link change
8296 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8297 * the right state.
8298 */
8299 netif_carrier_off(dev);
1da177e4
LT		 8300
8301 return 0;
8302
d44570e4
JP		 8303register_failed:
8304set_swap_failed:
1da177e4 8305 iounmap(sp->bar1);
d44570e4 8306bar1_remap_failed:
1da177e4 8307 iounmap(sp->bar0);
d44570e4
JP		 8308bar0_remap_failed:
8309mem_alloc_failed:
1da177e4
LT		 8310 free_shared_mem(sp);
8311 pci_disable_device(pdev);
eccb8628 8312 pci_release_regions(pdev);
1da177e4
LT		 8313 pci_set_drvdata(pdev, NULL);
8314 free_netdev(dev);
8315
8316 return ret;
8317}
8318
8319/**
20346722 8320 * s2io_rem_nic - Free the PCI device
1da177e4 8321 * @pdev: structure containing the PCI related information of the device.
20346722 8322 * Description: This function is called by the Pci subsystem to release a
1da177e4 8323 * PCI device and free up all resource held up by the device. This could
20346722 8324 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8325 * from memory.
8326 */
8327
8328static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8329{
8330 struct net_device *dev =
d44570e4 8331 (struct net_device *)pci_get_drvdata(pdev);
1ee6dd77 8332 struct s2io_nic *sp;
1da177e4
LT		 8333
8334 if (dev == NULL) {
8335 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8336 return;
8337 }
8338
22747d6b
FR		 8339 flush_scheduled_work();
8340
4cf1653a 8341 sp = netdev_priv(dev);
1da177e4
LT		 8342 unregister_netdev(dev);
8343
8344 free_shared_mem(sp);
8345 iounmap(sp->bar0);
8346 iounmap(sp->bar1);
eccb8628 8347 pci_release_regions(pdev);
1da177e4 8348 pci_set_drvdata(pdev, NULL);
1da177e4 8349 free_netdev(dev);
19a60522 8350 pci_disable_device(pdev);
1da177e4
LT		 8351}
8352
8353/**
8354 * s2io_starter - Entry point for the driver
8355 * Description: This function is the entry point for the driver. It verifies
8356 * the module loadable parameters and initializes PCI configuration space.
8357 */
8358
43b7c451 8359static int __init s2io_starter(void)
1da177e4 8360{
29917620 8361 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8362}
8363
8364/**
20346722 8365 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8366 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8367 */
8368
372cc597 8369static __exit void s2io_closer(void)
1da177e4
LT		 8370{
8371 pci_unregister_driver(&s2io_driver);
8372 DBG_PRINT(INIT_DBG, "cleanup done\n");
8373}
8374
8375module_init(s2io_starter);
8376module_exit(s2io_closer);
7d3d0439 8377
6aa20a22 8378static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
d44570e4
JP		 8379 struct tcphdr **tcp, struct RxD_t *rxdp,
8380 struct s2io_nic *sp)
7d3d0439
RA		 8381{
8382 int ip_off;
8383 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8384
8385 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
d44570e4
JP		 8386 DBG_PRINT(INIT_DBG,
8387 "%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8388 __func__);
7d3d0439
RA		 8389 return -1;
8390 }
8391
cdb5bf02 8392 /* Checking for DIX type or DIX type with VLAN */
d44570e4 8393 if ((l2_type == 0) || (l2_type == 4)) {
cdb5bf02
SH		 8394 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8395 /*
8396 * If vlan stripping is disabled and the frame is VLAN tagged,
8397 * shift the offset by the VLAN header size bytes.
8398 */
cd0fce03 8399 if ((!sp->vlan_strip_flag) &&
d44570e4 8400 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
cdb5bf02
SH		 8401 ip_off += HEADER_VLAN_SIZE;
8402 } else {
7d3d0439 8403 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8404 return -1;
7d3d0439
RA		 8405 }
8406
8407 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8408 ip_len = (u8)((*ip)->ihl);
8409 ip_len <<= 2;
8410 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8411
8412 return 0;
8413}
8414
1ee6dd77 8415static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8416 struct tcphdr *tcp)
8417{
d44570e4
JP		 8418 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8419 if ((lro->iph->saddr != ip->saddr) ||
8420 (lro->iph->daddr != ip->daddr) ||
8421 (lro->tcph->source != tcp->source) ||
8422 (lro->tcph->dest != tcp->dest))
7d3d0439
RA		 8423 return -1;
8424 return 0;
8425}
8426
8427static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8428{
d44570e4 8429 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
7d3d0439
RA		 8430}
8431
1ee6dd77 8432static void initiate_new_session(struct lro *lro, u8 *l2h,
d44570e4
JP		 8433 struct iphdr *ip, struct tcphdr *tcp,
8434 u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8435{
d44570e4 8436 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8437 lro->l2h = l2h;
8438 lro->iph = ip;
8439 lro->tcph = tcp;
8440 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8441 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8442 lro->sg_num = 1;
8443 lro->total_len = ntohs(ip->tot_len);
8444 lro->frags_len = 0;
cdb5bf02 8445 lro->vlan_tag = vlan_tag;
6aa20a22 8446 /*
d44570e4
JP		 8447 * Check if we saw TCP timestamp.
8448 * Other consistency checks have already been done.
8449 */
7d3d0439 8450 if (tcp->doff == 8) {
c8855953
SR		 8451 __be32 *ptr;
8452 ptr = (__be32 *)(tcp+1);
7d3d0439 8453 lro->saw_ts = 1;
c8855953 8454 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8455 lro->cur_tsecr = *(ptr+2);
8456 }
8457 lro->in_use = 1;
8458}
8459
1ee6dd77 8460static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8461{
8462 struct iphdr *ip = lro->iph;
8463 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8464 __sum16 nchk;
ffb5df6c
JP		 8465 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8466
d44570e4 8467 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8468
8469 /* Update L3 header */
8470 ip->tot_len = htons(lro->total_len);
8471 ip->check = 0;
8472 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8473 ip->check = nchk;
8474
8475 /* Update L4 header */
8476 tcp->ack_seq = lro->tcp_ack;
8477 tcp->window = lro->window;
8478
8479 /* Update tsecr field if this session has timestamps enabled */
8480 if (lro->saw_ts) {
c8855953 8481 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8482 *(ptr+2) = lro->cur_tsecr;
8483 }
8484
8485 /* Update counters required for calculation of
8486 * average no. of packets aggregated.
8487 */
ffb5df6c
JP		 8488 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8489 swstats->num_aggregations++;
7d3d0439
RA		 8490}
8491
1ee6dd77 8492static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
d44570e4 8493 struct tcphdr *tcp, u32 l4_pyld)
7d3d0439 8494{
d44570e4 8495 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8496 lro->total_len += l4_pyld;
8497 lro->frags_len += l4_pyld;
8498 lro->tcp_next_seq += l4_pyld;
8499 lro->sg_num++;
8500
8501 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8502 lro->tcp_ack = tcp->ack_seq;
8503 lro->window = tcp->window;
6aa20a22 8504
7d3d0439 8505 if (lro->saw_ts) {
c8855953 8506 __be32 *ptr;
7d3d0439 8507 /* Update tsecr and tsval from this packet */
c8855953
SR		 8508 ptr = (__be32 *)(tcp+1);
8509 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8510 lro->cur_tsecr = *(ptr + 2);
8511 }
8512}
8513
1ee6dd77 8514static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8515 struct tcphdr *tcp, u32 tcp_pyld_len)
8516{
7d3d0439
RA		 8517 u8 *ptr;
8518
d44570e4 8519 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
79dc1901 8520
7d3d0439
RA		 8521 if (!tcp_pyld_len) {
8522 /* Runt frame or a pure ack */
8523 return -1;
8524 }
8525
8526 if (ip->ihl != 5) /* IP has options */
8527 return -1;
8528
75c30b13
AR		 8529 /* If we see CE codepoint in IP header, packet is not mergeable */
8530 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8531 return -1;
8532
8533 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
d44570e4
JP		 8534 if (tcp->urg || tcp->psh || tcp->rst ||
8535 tcp->syn || tcp->fin ||
8536 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8537 /*
8538 * Currently recognize only the ack control word and
8539 * any other control field being set would result in
8540 * flushing the LRO session
8541 */
8542 return -1;
8543 }
8544
6aa20a22 8545 /*
7d3d0439
RA		 8546 * Allow only one TCP timestamp option. Don't aggregate if
8547 * any other options are detected.
8548 */
8549 if (tcp->doff != 5 && tcp->doff != 8)
8550 return -1;
8551
8552 if (tcp->doff == 8) {
6aa20a22 8553 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8554 while (*ptr == TCPOPT_NOP)
8555 ptr++;
8556 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8557 return -1;
8558
8559 /* Ensure timestamp value increases monotonically */
8560 if (l_lro)
c8855953 8561 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8562 return -1;
8563
8564 /* timestamp echo reply should be non-zero */
c8855953 8565 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8566 return -1;
8567 }
8568
8569 return 0;
8570}
8571
d44570e4
JP		 8572static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8573 u8 **tcp, u32 *tcp_len, struct lro **lro,
8574 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8575{
8576 struct iphdr *ip;
8577 struct tcphdr *tcph;
8578 int ret = 0, i;
cdb5bf02 8579 u16 vlan_tag = 0;
ffb5df6c 8580 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439 8581
d44570e4
JP		 8582 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8583 rxdp, sp);
8584 if (ret)
7d3d0439 8585 return ret;
7d3d0439 8586
d44570e4
JP		 8587 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8588
cdb5bf02 8589 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8590 tcph = (struct tcphdr *)*tcp;
8591 *tcp_len = get_l4_pyld_length(ip, tcph);
d44570e4 8592 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8593 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8594 if (l_lro->in_use) {
8595 if (check_for_socket_match(l_lro, ip, tcph))
8596 continue;
8597 /* Sock pair matched */
8598 *lro = l_lro;
8599
8600 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
9e39f7c5
JP		 8601 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8602 "expected 0x%x, actual 0x%x\n",
8603 __func__,
7d3d0439
RA		 8604 (*lro)->tcp_next_seq,
8605 ntohl(tcph->seq));
8606
ffb5df6c 8607 swstats->outof_sequence_pkts++;
7d3d0439
RA		 8608 ret = 2;
8609 break;
8610 }
8611
d44570e4
JP		 8612 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8613 *tcp_len))
7d3d0439
RA		 8614 ret = 1; /* Aggregate */
8615 else
8616 ret = 2; /* Flush both */
8617 break;
8618 }
8619 }
8620
8621 if (ret == 0) {
8622 /* Before searching for available LRO objects,
8623 * check if the pkt is L3/L4 aggregatable. If not
8624 * don't create new LRO session. Just send this
8625 * packet up.
8626 */
d44570e4 8627 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
7d3d0439 8628 return 5;
7d3d0439 8629
d44570e4 8630 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8631 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8632 if (!(l_lro->in_use)) {
8633 *lro = l_lro;
8634 ret = 3; /* Begin anew */
8635 break;
8636 }
8637 }
8638 }
8639
8640 if (ret == 0) { /* sessions exceeded */
9e39f7c5 8641 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
b39d66a8 8642 __func__);
7d3d0439
RA		 8643 *lro = NULL;
8644 return ret;
8645 }
8646
8647 switch (ret) {
d44570e4
JP		 8648 case 3:
8649 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8650 vlan_tag);
8651 break;
8652 case 2:
8653 update_L3L4_header(sp, *lro);
8654 break;
8655 case 1:
8656 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8657 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7d3d0439 8658 update_L3L4_header(sp, *lro);
d44570e4
JP		 8659 ret = 4; /* Flush the LRO */
8660 }
8661 break;
8662 default:
9e39f7c5 8663 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
d44570e4 8664 break;
7d3d0439
RA		 8665 }
8666
8667 return ret;
8668}
8669
1ee6dd77 8670static void clear_lro_session(struct lro *lro)
7d3d0439 8671{
1ee6dd77 8672 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8673
8674 memset(lro, 0, lro_struct_size);
8675}
8676
cdb5bf02 8677static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8678{
8679 struct net_device *dev = skb->dev;
4cf1653a 8680 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8681
8682 skb->protocol = eth_type_trans(skb, dev);
d44570e4 8683 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8684 /* Queueing the vlan frame to the upper layer */
8685 if (sp->config.napi)
8686 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8687 else
8688 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8689 } else {
8690 if (sp->config.napi)
8691 netif_receive_skb(skb);
8692 else
8693 netif_rx(skb);
8694 }
7d3d0439
RA		 8695}
8696
1ee6dd77 8697static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
d44570e4 8698 struct sk_buff *skb, u32 tcp_len)
7d3d0439 8699{
75c30b13 8700 struct sk_buff *first = lro->parent;
ffb5df6c 8701 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439
RA		 8702
8703 first->len += tcp_len;
8704 first->data_len = lro->frags_len;
8705 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8706 if (skb_shinfo(first)->frag_list)
8707 lro->last_frag->next = skb;
7d3d0439
RA		 8708 else
8709 skb_shinfo(first)->frag_list = skb;
372cc597 8710 first->truesize += skb->truesize;
75c30b13 8711 lro->last_frag = skb;
ffb5df6c 8712 swstats->clubbed_frms_cnt++;
7d3d0439 8713}
d796fdb7
LV		 8714
8715/**
8716 * s2io_io_error_detected - called when PCI error is detected
8717 * @pdev: Pointer to PCI device
8453d43f 8718 * @state: The current pci connection state
d796fdb7
LV		 8719 *
8720 * This function is called after a PCI bus error affecting
8721 * this device has been detected.
8722 */
8723static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
d44570e4 8724 pci_channel_state_t state)
d796fdb7
LV		 8725{
8726 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8727 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8728
8729 netif_device_detach(netdev);
8730
1e3c8bd6
DN		 8731 if (state == pci_channel_io_perm_failure)
8732 return PCI_ERS_RESULT_DISCONNECT;
8733
d796fdb7
LV		 8734 if (netif_running(netdev)) {
8735 /* Bring down the card, while avoiding PCI I/O */
8736 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8737 }
8738 pci_disable_device(pdev);
8739
8740 return PCI_ERS_RESULT_NEED_RESET;
8741}
8742
8743/**
8744 * s2io_io_slot_reset - called after the pci bus has been reset.
8745 * @pdev: Pointer to PCI device
8746 *
8747 * Restart the card from scratch, as if from a cold-boot.
8748 * At this point, the card has exprienced a hard reset,
8749 * followed by fixups by BIOS, and has its config space
8750 * set up identically to what it was at cold boot.
8751 */
8752static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8753{
8754 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8755 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8756
8757 if (pci_enable_device(pdev)) {
6cef2b8e 8758 pr_err("Cannot re-enable PCI device after reset.\n");
d796fdb7
LV		 8759 return PCI_ERS_RESULT_DISCONNECT;
8760 }
8761
8762 pci_set_master(pdev);
8763 s2io_reset(sp);
8764
8765 return PCI_ERS_RESULT_RECOVERED;
8766}
8767
8768/**
8769 * s2io_io_resume - called when traffic can start flowing again.
8770 * @pdev: Pointer to PCI device
8771 *
8772 * This callback is called when the error recovery driver tells
8773 * us that its OK to resume normal operation.
8774 */
8775static void s2io_io_resume(struct pci_dev *pdev)
8776{
8777 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8778 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8779
8780 if (netif_running(netdev)) {
8781 if (s2io_card_up(sp)) {
6cef2b8e 8782 pr_err("Can't bring device back up after reset.\n");
d796fdb7
LV		 8783 return;
8784 }
8785
8786 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8787 s2io_card_down(sp);
6cef2b8e 8788 pr_err("Can't restore mac addr after reset.\n");
d796fdb7
LV		 8789 return;
8790 }
8791 }
8792
8793 netif_device_attach(netdev);
fd2ea0a7 8794 netif_tx_wake_all_queues(netdev);
d796fdb7 8795}
Clone of davem's net-next-2.6 tree