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ethtool: Change ethtool_op_set_flags to validate flags
[net-next-2.6.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
d44570e4 4 *
1da177e4
LT		 5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4 27 * The module loadable parameters that are supported by the driver and a brief
a2a20aef 28 * explanation of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
958de193 41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
6cef2b8e
JP		 57#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
1da177e4
LT		 59#include <linux/module.h>
60#include <linux/types.h>
61#include <linux/errno.h>
62#include <linux/ioport.h>
63#include <linux/pci.h>
1e7f0bd8 64#include <linux/dma-mapping.h>
1da177e4
LT		 65#include <linux/kernel.h>
66#include <linux/netdevice.h>
67#include <linux/etherdevice.h>
40239396 68#include <linux/mdio.h>
1da177e4
LT		 69#include <linux/skbuff.h>
70#include <linux/init.h>
71#include <linux/delay.h>
72#include <linux/stddef.h>
73#include <linux/ioctl.h>
74#include <linux/timex.h>
1da177e4 75#include <linux/ethtool.h>
1da177e4 76#include <linux/workqueue.h>
be3a6b02 77#include <linux/if_vlan.h>
7d3d0439
RA		 78#include <linux/ip.h>
79#include <linux/tcp.h>
d44570e4
JP		 80#include <linux/uaccess.h>
81#include <linux/io.h>
5a0e3ad6 82#include <linux/slab.h>
7d3d0439 83#include <net/tcp.h>
1da177e4 84
1da177e4 85#include <asm/system.h>
fe931395 86#include <asm/div64.h>
330ce0de 87#include <asm/irq.h>
1da177e4
LT		 88
89/* local include */
90#include "s2io.h"
91#include "s2io-regs.h"
92
958de193 93#define DRV_VERSION "2.0.26.26"
6c1792f4 94
1da177e4 95/* S2io Driver name & version. */
20346722 96static char s2io_driver_name[] = "Neterion";
6c1792f4 97static char s2io_driver_version[] = DRV_VERSION;
1da177e4 98
d44570e4
JP		 99static int rxd_size[2] = {32, 48};
100static int rxd_count[2] = {127, 85};
da6971d8 101
1ee6dd77 102static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 103{
104 int ret;
105
106 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
d44570e4 107 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
5e25b9dd
K		 108
109 return ret;
110}
111
20346722 112/*
1da177e4
LT		 113 * Cards with following subsystem_id have a link state indication
114 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
115 * macro below identifies these cards given the subsystem_id.
116 */
d44570e4
JP		 117#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
118 (dev_type == XFRAME_I_DEVICE) ? \
119 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
120 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 121
122#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
123 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 124
d44570e4 125static inline int is_s2io_card_up(const struct s2io_nic *sp)
92b84437
SS		 126{
127 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
128}
129
1da177e4 130/* Ethtool related variables and Macros. */
6fce365d 131static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 132 "Register test\t(offline)",
133 "Eeprom test\t(offline)",
134 "Link test\t(online)",
135 "RLDRAM test\t(offline)",
136 "BIST Test\t(offline)"
137};
138
6fce365d 139static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 140 {"tmac_frms"},
141 {"tmac_data_octets"},
142 {"tmac_drop_frms"},
143 {"tmac_mcst_frms"},
144 {"tmac_bcst_frms"},
145 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 146 {"tmac_ttl_octets"},
147 {"tmac_ucst_frms"},
148 {"tmac_nucst_frms"},
1da177e4 149 {"tmac_any_err_frms"},
bd1034f0 150 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 151 {"tmac_vld_ip_octets"},
152 {"tmac_vld_ip"},
153 {"tmac_drop_ip"},
154 {"tmac_icmp"},
155 {"tmac_rst_tcp"},
156 {"tmac_tcp"},
157 {"tmac_udp"},
158 {"rmac_vld_frms"},
159 {"rmac_data_octets"},
160 {"rmac_fcs_err_frms"},
161 {"rmac_drop_frms"},
162 {"rmac_vld_mcst_frms"},
163 {"rmac_vld_bcst_frms"},
164 {"rmac_in_rng_len_err_frms"},
bd1034f0 165 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 166 {"rmac_long_frms"},
167 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 168 {"rmac_unsup_ctrl_frms"},
169 {"rmac_ttl_octets"},
170 {"rmac_accepted_ucst_frms"},
171 {"rmac_accepted_nucst_frms"},
1da177e4 172 {"rmac_discarded_frms"},
bd1034f0
AR		 173 {"rmac_drop_events"},
174 {"rmac_ttl_less_fb_octets"},
175 {"rmac_ttl_frms"},
1da177e4
LT		 176 {"rmac_usized_frms"},
177 {"rmac_osized_frms"},
178 {"rmac_frag_frms"},
179 {"rmac_jabber_frms"},
bd1034f0
AR		 180 {"rmac_ttl_64_frms"},
181 {"rmac_ttl_65_127_frms"},
182 {"rmac_ttl_128_255_frms"},
183 {"rmac_ttl_256_511_frms"},
184 {"rmac_ttl_512_1023_frms"},
185 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 186 {"rmac_ip"},
187 {"rmac_ip_octets"},
188 {"rmac_hdr_err_ip"},
189 {"rmac_drop_ip"},
190 {"rmac_icmp"},
191 {"rmac_tcp"},
192 {"rmac_udp"},
193 {"rmac_err_drp_udp"},
bd1034f0
AR		 194 {"rmac_xgmii_err_sym"},
195 {"rmac_frms_q0"},
196 {"rmac_frms_q1"},
197 {"rmac_frms_q2"},
198 {"rmac_frms_q3"},
199 {"rmac_frms_q4"},
200 {"rmac_frms_q5"},
201 {"rmac_frms_q6"},
202 {"rmac_frms_q7"},
203 {"rmac_full_q0"},
204 {"rmac_full_q1"},
205 {"rmac_full_q2"},
206 {"rmac_full_q3"},
207 {"rmac_full_q4"},
208 {"rmac_full_q5"},
209 {"rmac_full_q6"},
210 {"rmac_full_q7"},
1da177e4 211 {"rmac_pause_cnt"},
bd1034f0
AR		 212 {"rmac_xgmii_data_err_cnt"},
213 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 214 {"rmac_accepted_ip"},
215 {"rmac_err_tcp"},
bd1034f0
AR		 216 {"rd_req_cnt"},
217 {"new_rd_req_cnt"},
218 {"new_rd_req_rtry_cnt"},
219 {"rd_rtry_cnt"},
220 {"wr_rtry_rd_ack_cnt"},
221 {"wr_req_cnt"},
222 {"new_wr_req_cnt"},
223 {"new_wr_req_rtry_cnt"},
224 {"wr_rtry_cnt"},
225 {"wr_disc_cnt"},
226 {"rd_rtry_wr_ack_cnt"},
227 {"txp_wr_cnt"},
228 {"txd_rd_cnt"},
229 {"txd_wr_cnt"},
230 {"rxd_rd_cnt"},
231 {"rxd_wr_cnt"},
232 {"txf_rd_cnt"},
fa1f0cb3
SS		 233 {"rxf_wr_cnt"}
234};
235
6fce365d 236static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 237 {"rmac_ttl_1519_4095_frms"},
238 {"rmac_ttl_4096_8191_frms"},
239 {"rmac_ttl_8192_max_frms"},
240 {"rmac_ttl_gt_max_frms"},
241 {"rmac_osized_alt_frms"},
242 {"rmac_jabber_alt_frms"},
243 {"rmac_gt_max_alt_frms"},
244 {"rmac_vlan_frms"},
245 {"rmac_len_discard"},
246 {"rmac_fcs_discard"},
247 {"rmac_pf_discard"},
248 {"rmac_da_discard"},
249 {"rmac_red_discard"},
250 {"rmac_rts_discard"},
251 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 252 {"link_fault_cnt"}
253};
254
6fce365d 255static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 256 {"\n DRIVER STATISTICS"},
257 {"single_bit_ecc_errs"},
258 {"double_bit_ecc_errs"},
bd1034f0
AR		 259 {"parity_err_cnt"},
260 {"serious_err_cnt"},
261 {"soft_reset_cnt"},
262 {"fifo_full_cnt"},
8116f3cf
SS		 263 {"ring_0_full_cnt"},
264 {"ring_1_full_cnt"},
265 {"ring_2_full_cnt"},
266 {"ring_3_full_cnt"},
267 {"ring_4_full_cnt"},
268 {"ring_5_full_cnt"},
269 {"ring_6_full_cnt"},
270 {"ring_7_full_cnt"},
43b7c451
SH		 271 {"alarm_transceiver_temp_high"},
272 {"alarm_transceiver_temp_low"},
273 {"alarm_laser_bias_current_high"},
274 {"alarm_laser_bias_current_low"},
275 {"alarm_laser_output_power_high"},
276 {"alarm_laser_output_power_low"},
277 {"warn_transceiver_temp_high"},
278 {"warn_transceiver_temp_low"},
279 {"warn_laser_bias_current_high"},
280 {"warn_laser_bias_current_low"},
281 {"warn_laser_output_power_high"},
282 {"warn_laser_output_power_low"},
283 {"lro_aggregated_pkts"},
284 {"lro_flush_both_count"},
285 {"lro_out_of_sequence_pkts"},
286 {"lro_flush_due_to_max_pkts"},
287 {"lro_avg_aggr_pkts"},
288 {"mem_alloc_fail_cnt"},
289 {"pci_map_fail_cnt"},
290 {"watchdog_timer_cnt"},
291 {"mem_allocated"},
292 {"mem_freed"},
293 {"link_up_cnt"},
294 {"link_down_cnt"},
295 {"link_up_time"},
296 {"link_down_time"},
297 {"tx_tcode_buf_abort_cnt"},
298 {"tx_tcode_desc_abort_cnt"},
299 {"tx_tcode_parity_err_cnt"},
300 {"tx_tcode_link_loss_cnt"},
301 {"tx_tcode_list_proc_err_cnt"},
302 {"rx_tcode_parity_err_cnt"},
303 {"rx_tcode_abort_cnt"},
304 {"rx_tcode_parity_abort_cnt"},
305 {"rx_tcode_rda_fail_cnt"},
306 {"rx_tcode_unkn_prot_cnt"},
307 {"rx_tcode_fcs_err_cnt"},
308 {"rx_tcode_buf_size_err_cnt"},
309 {"rx_tcode_rxd_corrupt_cnt"},
310 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 311 {"tda_err_cnt"},
312 {"pfc_err_cnt"},
313 {"pcc_err_cnt"},
314 {"tti_err_cnt"},
315 {"tpa_err_cnt"},
316 {"sm_err_cnt"},
317 {"lso_err_cnt"},
318 {"mac_tmac_err_cnt"},
319 {"mac_rmac_err_cnt"},
320 {"xgxs_txgxs_err_cnt"},
321 {"xgxs_rxgxs_err_cnt"},
322 {"rc_err_cnt"},
323 {"prc_pcix_err_cnt"},
324 {"rpa_err_cnt"},
325 {"rda_err_cnt"},
326 {"rti_err_cnt"},
327 {"mc_err_cnt"}
1da177e4
LT		 328};
329
4c3616cd
AMR		 330#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
331#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
332#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3 333
d44570e4
JP		 334#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
335#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
fa1f0cb3 336
d44570e4
JP		 337#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
338#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
1da177e4 339
4c3616cd 340#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
d44570e4 341#define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
1da177e4 342
d44570e4
JP		 343#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
344 init_timer(&timer); \
345 timer.function = handle; \
346 timer.data = (unsigned long)arg; \
347 mod_timer(&timer, (jiffies + exp)) \
25fff88e 348
2fd37688
SS		 349/* copy mac addr to def_mac_addr array */
350static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
351{
352 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
353 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
354 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
355 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
356 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
357 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
358}
04025095 359
be3a6b02
K		 360/* Add the vlan */
361static void s2io_vlan_rx_register(struct net_device *dev,
04025095 362 struct vlan_group *grp)
be3a6b02 363{
2fda096d 364 int i;
4cf1653a 365 struct s2io_nic *nic = netdev_priv(dev);
2fda096d 366 unsigned long flags[MAX_TX_FIFOS];
2fda096d 367 struct config_param *config = &nic->config;
ffb5df6c 368 struct mac_info *mac_control = &nic->mac_control;
2fda096d 369
13d866a9
JP		 370 for (i = 0; i < config->tx_fifo_num; i++) {
371 struct fifo_info *fifo = &mac_control->fifos[i];
372
373 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
374 }
be3a6b02 375
be3a6b02 376 nic->vlgrp = grp;
13d866a9
JP		 377
378 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
379 struct fifo_info *fifo = &mac_control->fifos[i];
380
381 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
382 }
be3a6b02
K		 383}
384
cdb5bf02 385/* Unregister the vlan */
04025095 386static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 387{
388 int i;
4cf1653a 389 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02 390 unsigned long flags[MAX_TX_FIFOS];
cdb5bf02 391 struct config_param *config = &nic->config;
ffb5df6c 392 struct mac_info *mac_control = &nic->mac_control;
cdb5bf02 393
13d866a9
JP		 394 for (i = 0; i < config->tx_fifo_num; i++) {
395 struct fifo_info *fifo = &mac_control->fifos[i];
396
397 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
398 }
cdb5bf02
SH		 399
400 if (nic->vlgrp)
401 vlan_group_set_device(nic->vlgrp, vid, NULL);
402
13d866a9
JP		 403 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
404 struct fifo_info *fifo = &mac_control->fifos[i];
405
406 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
407 }
cdb5bf02
SH		 408}
409
20346722 410/*
1da177e4
LT		 411 * Constants to be programmed into the Xena's registers, to configure
412 * the XAUI.
413 */
414
1da177e4 415#define END_SIGN 0x0
f71e1309 416static const u64 herc_act_dtx_cfg[] = {
541ae68f 417 /* Set address */
e960fc5c 418 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 419 /* Write data */
e960fc5c 420 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 421 /* Set address */
422 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
423 /* Write data */
424 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
425 /* Set address */
e960fc5c 426 0x801205150D440000ULL, 0x801205150D4400E0ULL,
427 /* Write data */
428 0x801205150D440004ULL, 0x801205150D4400E4ULL,
429 /* Set address */
541ae68f
K		 430 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
431 /* Write data */
432 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
433 /* Done */
434 END_SIGN
435};
436
f71e1309 437static const u64 xena_dtx_cfg[] = {
c92ca04b 438 /* Set address */
1da177e4 439 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 440 /* Write data */
441 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
442 /* Set address */
443 0x8001051500000000ULL, 0x80010515000000E0ULL,
444 /* Write data */
445 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
446 /* Set address */
1da177e4 447 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 448 /* Write data */
449 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 450 END_SIGN
451};
452
20346722 453/*
1da177e4
LT		 454 * Constants for Fixing the MacAddress problem seen mostly on
455 * Alpha machines.
456 */
f71e1309 457static const u64 fix_mac[] = {
1da177e4
LT		 458 0x0060000000000000ULL, 0x0060600000000000ULL,
459 0x0040600000000000ULL, 0x0000600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0060600000000000ULL,
470 0x0020600000000000ULL, 0x0000600000000000ULL,
471 0x0040600000000000ULL, 0x0060600000000000ULL,
472 END_SIGN
473};
474
b41477f3
AR		 475MODULE_LICENSE("GPL");
476MODULE_VERSION(DRV_VERSION);
477
478
1da177e4 479/* Module Loadable parameters. */
6cfc482b 480S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 481S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 482S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 483S2IO_PARM_INT(rx_ring_mode, 1);
484S2IO_PARM_INT(use_continuous_tx_intrs, 1);
485S2IO_PARM_INT(rmac_pause_time, 0x100);
486S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
487S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
488S2IO_PARM_INT(shared_splits, 0);
489S2IO_PARM_INT(tmac_util_period, 5);
490S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 491S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 492/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
493S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 494/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 495S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 496/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 497S2IO_PARM_INT(intr_type, 2);
7d3d0439 498/* Large receive offload feature */
958de193 499static unsigned int lro_enable = 1;
43b7c451
SH		 500module_param_named(lro, lro_enable, uint, 0);
501
7d3d0439
RA		 502/* Max pkts to be aggregated by LRO at one time. If not specified,
503 * aggregation happens until we hit max IP pkt size(64K)
504 */
b41477f3 505S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 506S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 507
508S2IO_PARM_INT(napi, 1);
509S2IO_PARM_INT(ufo, 0);
926930b2 510S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 511
512static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
d44570e4 513{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
b41477f3 514static unsigned int rx_ring_sz[MAX_RX_RINGS] =
d44570e4 515{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
b41477f3 516static unsigned int rts_frm_len[MAX_RX_RINGS] =
d44570e4 517{[0 ...(MAX_RX_RINGS - 1)] = 0 };
b41477f3
AR		 518
519module_param_array(tx_fifo_len, uint, NULL, 0);
520module_param_array(rx_ring_sz, uint, NULL, 0);
521module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 522
20346722 523/*
1da177e4 524 * S2IO device table.
20346722 525 * This table lists all the devices that this driver supports.
1da177e4 526 */
a3aa1884 527static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
1da177e4
LT		 528 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
529 PCI_ANY_ID, PCI_ANY_ID},
530 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
531 PCI_ANY_ID, PCI_ANY_ID},
532 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
d44570e4
JP		 533 PCI_ANY_ID, PCI_ANY_ID},
534 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
535 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 536 {0,}
537};
538
539MODULE_DEVICE_TABLE(pci, s2io_tbl);
540
d796fdb7
LV		 541static struct pci_error_handlers s2io_err_handler = {
542 .error_detected = s2io_io_error_detected,
543 .slot_reset = s2io_io_slot_reset,
544 .resume = s2io_io_resume,
545};
546
1da177e4 547static struct pci_driver s2io_driver = {
d44570e4
JP		 548 .name = "S2IO",
549 .id_table = s2io_tbl,
550 .probe = s2io_init_nic,
551 .remove = __devexit_p(s2io_rem_nic),
552 .err_handler = &s2io_err_handler,
1da177e4
LT		 553};
554
555/* A simplifier macro used both by init and free shared_mem Fns(). */
556#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
557
3a3d5756
SH		 558/* netqueue manipulation helper functions */
559static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
560{
fd2ea0a7
DM		 561 if (!sp->config.multiq) {
562 int i;
563
3a3d5756
SH		 564 for (i = 0; i < sp->config.tx_fifo_num; i++)
565 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 566 }
fd2ea0a7 567 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 568}
569
570static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
571{
fd2ea0a7 572 if (!sp->config.multiq)
3a3d5756
SH		 573 sp->mac_control.fifos[fifo_no].queue_state =
574 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 575
576 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 577}
578
579static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
580{
fd2ea0a7
DM		 581 if (!sp->config.multiq) {
582 int i;
583
3a3d5756
SH		 584 for (i = 0; i < sp->config.tx_fifo_num; i++)
585 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 586 }
fd2ea0a7 587 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 588}
589
590static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
591{
fd2ea0a7 592 if (!sp->config.multiq)
3a3d5756
SH		 593 sp->mac_control.fifos[fifo_no].queue_state =
594 FIFO_QUEUE_START;
fd2ea0a7
DM		 595
596 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 597}
598
599static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
600{
fd2ea0a7
DM		 601 if (!sp->config.multiq) {
602 int i;
603
3a3d5756
SH		 604 for (i = 0; i < sp->config.tx_fifo_num; i++)
605 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 606 }
fd2ea0a7 607 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 608}
609
610static inline void s2io_wake_tx_queue(
611 struct fifo_info *fifo, int cnt, u8 multiq)
612{
613
3a3d5756
SH		 614 if (multiq) {
615 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
616 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 617 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 618 if (netif_queue_stopped(fifo->dev)) {
619 fifo->queue_state = FIFO_QUEUE_START;
620 netif_wake_queue(fifo->dev);
621 }
622 }
623}
624
1da177e4
LT		 625/**
626 * init_shared_mem - Allocation and Initialization of Memory
627 * @nic: Device private variable.
20346722
K		 628 * Description: The function allocates all the memory areas shared
629 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 630 * Rx descriptors and the statistics block.
631 */
632
633static int init_shared_mem(struct s2io_nic *nic)
634{
635 u32 size;
636 void *tmp_v_addr, *tmp_v_addr_next;
637 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 638 struct RxD_block *pre_rxd_blk = NULL;
372cc597 639 int i, j, blk_cnt;
1da177e4
LT		 640 int lst_size, lst_per_page;
641 struct net_device *dev = nic->dev;
8ae418cf 642 unsigned long tmp;
1ee6dd77 643 struct buffAdd *ba;
ffb5df6c
JP		 644 struct config_param *config = &nic->config;
645 struct mac_info *mac_control = &nic->mac_control;
491976b2 646 unsigned long long mem_allocated = 0;
1da177e4 647
13d866a9 648 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 649 size = 0;
650 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 651 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
652
653 size += tx_cfg->fifo_len;
1da177e4
LT		 654 }
655 if (size > MAX_AVAILABLE_TXDS) {
9e39f7c5
JP		 656 DBG_PRINT(ERR_DBG,
657 "Too many TxDs requested: %d, max supported: %d\n",
658 size, MAX_AVAILABLE_TXDS);
b41477f3 659 return -EINVAL;
1da177e4
LT		 660 }
661
2fda096d
SR		 662 size = 0;
663 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 664 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
665
666 size = tx_cfg->fifo_len;
2fda096d
SR		 667 /*
668 * Legal values are from 2 to 8192
669 */
670 if (size < 2) {
9e39f7c5
JP		 671 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
672 "Valid lengths are 2 through 8192\n",
673 i, size);
2fda096d
SR		 674 return -EINVAL;
675 }
676 }
677
1ee6dd77 678 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 679 lst_per_page = PAGE_SIZE / lst_size;
680
681 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 682 struct fifo_info *fifo = &mac_control->fifos[i];
683 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 685 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 686
687 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
688 if (!fifo->list_info) {
d44570e4 689 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
1da177e4
LT		 690 return -ENOMEM;
691 }
491976b2 692 mem_allocated += list_holder_size;
1da177e4
LT		 693 }
694 for (i = 0; i < config->tx_fifo_num; i++) {
695 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
696 lst_per_page);
13d866a9
JP		 697 struct fifo_info *fifo = &mac_control->fifos[i];
698 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
699
700 fifo->tx_curr_put_info.offset = 0;
701 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
702 fifo->tx_curr_get_info.offset = 0;
703 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
704 fifo->fifo_no = i;
705 fifo->nic = nic;
706 fifo->max_txds = MAX_SKB_FRAGS + 2;
707 fifo->dev = dev;
20346722 708
1da177e4
LT		 709 for (j = 0; j < page_num; j++) {
710 int k = 0;
711 dma_addr_t tmp_p;
712 void *tmp_v;
713 tmp_v = pci_alloc_consistent(nic->pdev,
714 PAGE_SIZE, &tmp_p);
715 if (!tmp_v) {
9e39f7c5
JP		 716 DBG_PRINT(INFO_DBG,
717 "pci_alloc_consistent failed for TxDL\n");
1da177e4
LT		 718 return -ENOMEM;
719 }
776bd20f 720 /* If we got a zero DMA address(can happen on
721 * certain platforms like PPC), reallocate.
722 * Store virtual address of page we don't want,
723 * to be freed later.
724 */
725 if (!tmp_p) {
726 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 727 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 728 "%s: Zero DMA address for TxDL. "
729 "Virtual address %p\n",
730 dev->name, tmp_v);
776bd20f 731 tmp_v = pci_alloc_consistent(nic->pdev,
d44570e4 732 PAGE_SIZE, &tmp_p);
776bd20f 733 if (!tmp_v) {
0c61ed5f 734 DBG_PRINT(INFO_DBG,
9e39f7c5 735 "pci_alloc_consistent failed for TxDL\n");
776bd20f 736 return -ENOMEM;
737 }
491976b2 738 mem_allocated += PAGE_SIZE;
776bd20f 739 }
1da177e4
LT		 740 while (k < lst_per_page) {
741 int l = (j * lst_per_page) + k;
13d866a9 742 if (l == tx_cfg->fifo_len)
20346722 743 break;
13d866a9 744 fifo->list_info[l].list_virt_addr =
d44570e4 745 tmp_v + (k * lst_size);
13d866a9 746 fifo->list_info[l].list_phy_addr =
d44570e4 747 tmp_p + (k * lst_size);
1da177e4
LT		 748 k++;
749 }
750 }
751 }
1da177e4 752
2fda096d 753 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 754 struct fifo_info *fifo = &mac_control->fifos[i];
755 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
756
757 size = tx_cfg->fifo_len;
758 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
759 if (!fifo->ufo_in_band_v)
2fda096d
SR		 760 return -ENOMEM;
761 mem_allocated += (size * sizeof(u64));
762 }
fed5eccd 763
1da177e4
LT		 764 /* Allocation and initialization of RXDs in Rings */
765 size = 0;
766 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 767 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
768 struct ring_info *ring = &mac_control->rings[i];
769
770 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
9e39f7c5
JP		 771 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
772 "multiple of RxDs per Block\n",
773 dev->name, i);
1da177e4
LT		 774 return FAILURE;
775 }
13d866a9
JP		 776 size += rx_cfg->num_rxd;
777 ring->block_count = rx_cfg->num_rxd /
d44570e4 778 (rxd_count[nic->rxd_mode] + 1);
13d866a9 779 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 780 }
da6971d8 781 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 782 size = (size * (sizeof(struct RxD1)));
da6971d8 783 else
1ee6dd77 784 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 785
786 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 787 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
788 struct ring_info *ring = &mac_control->rings[i];
789
790 ring->rx_curr_get_info.block_index = 0;
791 ring->rx_curr_get_info.offset = 0;
792 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
793 ring->rx_curr_put_info.block_index = 0;
794 ring->rx_curr_put_info.offset = 0;
795 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
796 ring->nic = nic;
797 ring->ring_no = i;
13d866a9
JP		 798
799 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 800 /* Allocating all the Rx blocks */
801 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 802 struct rx_block_info *rx_blocks;
da6971d8
AR		 803 int l;
804
13d866a9 805 rx_blocks = &ring->rx_blocks[j];
d44570e4 806 size = SIZE_OF_BLOCK; /* size is always page size */
1da177e4
LT		 807 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
808 &tmp_p_addr);
809 if (tmp_v_addr == NULL) {
810 /*
20346722
K		 811 * In case of failure, free_shared_mem()
812 * is called, which should free any
813 * memory that was alloced till the
1da177e4
LT		 814 * failure happened.
815 */
da6971d8 816 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 817 return -ENOMEM;
818 }
491976b2 819 mem_allocated += size;
1da177e4 820 memset(tmp_v_addr, 0, size);
4f870320
JP		 821
822 size = sizeof(struct rxd_info) *
823 rxd_count[nic->rxd_mode];
da6971d8
AR		 824 rx_blocks->block_virt_addr = tmp_v_addr;
825 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 826 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 827 if (!rx_blocks->rxds)
828 return -ENOMEM;
4f870320 829 mem_allocated += size;
d44570e4 830 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
da6971d8
AR		 831 rx_blocks->rxds[l].virt_addr =
832 rx_blocks->block_virt_addr +
833 (rxd_size[nic->rxd_mode] * l);
834 rx_blocks->rxds[l].dma_addr =
835 rx_blocks->block_dma_addr +
836 (rxd_size[nic->rxd_mode] * l);
837 }
1da177e4
LT		 838 }
839 /* Interlinking all Rx Blocks */
840 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 841 int next = (j + 1) % blk_cnt;
842 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
843 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
844 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
845 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 846
d44570e4 847 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
1da177e4 848 pre_rxd_blk->reserved_2_pNext_RxD_block =
d44570e4 849 (unsigned long)tmp_v_addr_next;
1da177e4 850 pre_rxd_blk->pNext_RxD_Blk_physical =
d44570e4 851 (u64)tmp_p_addr_next;
1da177e4
LT		 852 }
853 }
6d517a27 854 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 855 /*
856 * Allocation of Storages for buffer addresses in 2BUFF mode
857 * and the buffers as well.
858 */
859 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 860 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
861 struct ring_info *ring = &mac_control->rings[i];
862
863 blk_cnt = rx_cfg->num_rxd /
d44570e4 864 (rxd_count[nic->rxd_mode] + 1);
4f870320
JP		 865 size = sizeof(struct buffAdd *) * blk_cnt;
866 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 867 if (!ring->ba)
1da177e4 868 return -ENOMEM;
4f870320 869 mem_allocated += size;
da6971d8
AR		 870 for (j = 0; j < blk_cnt; j++) {
871 int k = 0;
4f870320
JP		 872
873 size = sizeof(struct buffAdd) *
874 (rxd_count[nic->rxd_mode] + 1);
875 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 876 if (!ring->ba[j])
1da177e4 877 return -ENOMEM;
4f870320 878 mem_allocated += size;
da6971d8 879 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 880 ba = &ring->ba[j][k];
4f870320
JP		 881 size = BUF0_LEN + ALIGN_SIZE;
882 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 883 if (!ba->ba_0_org)
884 return -ENOMEM;
4f870320 885 mem_allocated += size;
da6971d8
AR		 886 tmp = (unsigned long)ba->ba_0_org;
887 tmp += ALIGN_SIZE;
d44570e4
JP		 888 tmp &= ~((unsigned long)ALIGN_SIZE);
889 ba->ba_0 = (void *)tmp;
da6971d8 890
4f870320
JP		 891 size = BUF1_LEN + ALIGN_SIZE;
892 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 893 if (!ba->ba_1_org)
894 return -ENOMEM;
4f870320 895 mem_allocated += size;
d44570e4 896 tmp = (unsigned long)ba->ba_1_org;
da6971d8 897 tmp += ALIGN_SIZE;
d44570e4
JP		 898 tmp &= ~((unsigned long)ALIGN_SIZE);
899 ba->ba_1 = (void *)tmp;
da6971d8
AR		 900 k++;
901 }
1da177e4
LT		 902 }
903 }
904 }
1da177e4
LT		 905
906 /* Allocation and initialization of Statistics block */
1ee6dd77 907 size = sizeof(struct stat_block);
d44570e4
JP		 908 mac_control->stats_mem =
909 pci_alloc_consistent(nic->pdev, size,
910 &mac_control->stats_mem_phy);
1da177e4
LT		 911
912 if (!mac_control->stats_mem) {
20346722
K		 913 /*
914 * In case of failure, free_shared_mem() is called, which
915 * should free any memory that was alloced till the
1da177e4
LT		 916 * failure happened.
917 */
918 return -ENOMEM;
919 }
491976b2 920 mem_allocated += size;
1da177e4
LT		 921 mac_control->stats_mem_sz = size;
922
923 tmp_v_addr = mac_control->stats_mem;
d44570e4 924 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
1da177e4 925 memset(tmp_v_addr, 0, size);
3a22813a
BL		 926 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
927 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
491976b2 928 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 929 return SUCCESS;
930}
931
20346722
K		 932/**
933 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 934 * @nic: Device private variable.
935 * Description: This function is to free all memory locations allocated by
936 * the init_shared_mem() function and return it to the kernel.
937 */
938
939static void free_shared_mem(struct s2io_nic *nic)
940{
941 int i, j, blk_cnt, size;
942 void *tmp_v_addr;
943 dma_addr_t tmp_p_addr;
1da177e4 944 int lst_size, lst_per_page;
8910b49f 945 struct net_device *dev;
491976b2 946 int page_num = 0;
ffb5df6c
JP		 947 struct config_param *config;
948 struct mac_info *mac_control;
949 struct stat_block *stats;
950 struct swStat *swstats;
1da177e4
LT		 951
952 if (!nic)
953 return;
954
8910b49f
MG		 955 dev = nic->dev;
956
1da177e4 957 config = &nic->config;
ffb5df6c
JP		 958 mac_control = &nic->mac_control;
959 stats = mac_control->stats_info;
960 swstats = &stats->sw_stat;
1da177e4 961
d44570e4 962 lst_size = sizeof(struct TxD) * config->max_txds;
1da177e4
LT		 963 lst_per_page = PAGE_SIZE / lst_size;
964
965 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 966 struct fifo_info *fifo = &mac_control->fifos[i];
967 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
968
969 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 970 for (j = 0; j < page_num; j++) {
971 int mem_blks = (j * lst_per_page);
13d866a9
JP		 972 struct list_info_hold *fli;
973
974 if (!fifo->list_info)
6aa20a22 975 return;
13d866a9
JP		 976
977 fli = &fifo->list_info[mem_blks];
978 if (!fli->list_virt_addr)
1da177e4
LT		 979 break;
980 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 981 fli->list_virt_addr,
982 fli->list_phy_addr);
ffb5df6c 983 swstats->mem_freed += PAGE_SIZE;
1da177e4 984 }
776bd20f 985 /* If we got a zero DMA address during allocation,
986 * free the page now
987 */
988 if (mac_control->zerodma_virt_addr) {
989 pci_free_consistent(nic->pdev, PAGE_SIZE,
990 mac_control->zerodma_virt_addr,
991 (dma_addr_t)0);
6aa20a22 992 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 993 "%s: Freeing TxDL with zero DMA address. "
994 "Virtual address %p\n",
995 dev->name, mac_control->zerodma_virt_addr);
ffb5df6c 996 swstats->mem_freed += PAGE_SIZE;
776bd20f 997 }
13d866a9 998 kfree(fifo->list_info);
82c2d023 999 swstats->mem_freed += tx_cfg->fifo_len *
d44570e4 1000 sizeof(struct list_info_hold);
1da177e4
LT		 1001 }
1002
1da177e4 1003 size = SIZE_OF_BLOCK;
1da177e4 1004 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1005 struct ring_info *ring = &mac_control->rings[i];
1006
1007 blk_cnt = ring->block_count;
1da177e4 1008 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1009 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1010 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1011 if (tmp_v_addr == NULL)
1012 break;
1013 pci_free_consistent(nic->pdev, size,
1014 tmp_v_addr, tmp_p_addr);
ffb5df6c 1015 swstats->mem_freed += size;
13d866a9 1016 kfree(ring->rx_blocks[j].rxds);
ffb5df6c
JP		 1017 swstats->mem_freed += sizeof(struct rxd_info) *
1018 rxd_count[nic->rxd_mode];
1da177e4
LT		 1019 }
1020 }
1021
6d517a27 1022 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1023 /* Freeing buffer storage addresses in 2BUFF mode. */
1024 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1025 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1026 struct ring_info *ring = &mac_control->rings[i];
1027
1028 blk_cnt = rx_cfg->num_rxd /
1029 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1030 for (j = 0; j < blk_cnt; j++) {
1031 int k = 0;
13d866a9 1032 if (!ring->ba[j])
da6971d8
AR		 1033 continue;
1034 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1035 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1036 kfree(ba->ba_0_org);
ffb5df6c
JP		 1037 swstats->mem_freed +=
1038 BUF0_LEN + ALIGN_SIZE;
da6971d8 1039 kfree(ba->ba_1_org);
ffb5df6c
JP		 1040 swstats->mem_freed +=
1041 BUF1_LEN + ALIGN_SIZE;
da6971d8
AR		 1042 k++;
1043 }
13d866a9 1044 kfree(ring->ba[j]);
ffb5df6c
JP		 1045 swstats->mem_freed += sizeof(struct buffAdd) *
1046 (rxd_count[nic->rxd_mode] + 1);
1da177e4 1047 }
13d866a9 1048 kfree(ring->ba);
ffb5df6c
JP		 1049 swstats->mem_freed += sizeof(struct buffAdd *) *
1050 blk_cnt;
1da177e4 1051 }
1da177e4 1052 }
1da177e4 1053
2fda096d 1054 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1055 struct fifo_info *fifo = &mac_control->fifos[i];
1056 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1057
1058 if (fifo->ufo_in_band_v) {
ffb5df6c
JP		 1059 swstats->mem_freed += tx_cfg->fifo_len *
1060 sizeof(u64);
13d866a9 1061 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1062 }
1063 }
1064
1da177e4 1065 if (mac_control->stats_mem) {
ffb5df6c 1066 swstats->mem_freed += mac_control->stats_mem_sz;
1da177e4
LT		 1067 pci_free_consistent(nic->pdev,
1068 mac_control->stats_mem_sz,
1069 mac_control->stats_mem,
1070 mac_control->stats_mem_phy);
491976b2 1071 }
1da177e4
LT		 1072}
1073
541ae68f
K		 1074/**
1075 * s2io_verify_pci_mode -
1076 */
1077
1ee6dd77 1078static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1079{
1ee6dd77 1080 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1081 register u64 val64 = 0;
1082 int mode;
1083
1084 val64 = readq(&bar0->pci_mode);
1085 mode = (u8)GET_PCI_MODE(val64);
1086
d44570e4 1087 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1088 return -1; /* Unknown PCI mode */
1089 return mode;
1090}
1091
c92ca04b
AR		 1092#define NEC_VENID 0x1033
1093#define NEC_DEVID 0x0125
1094static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1095{
1096 struct pci_dev *tdev = NULL;
26d36b64
AC		 1097 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1098 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1099 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1100 pci_dev_put(tdev);
c92ca04b 1101 return 1;
7ad62dbc 1102 }
c92ca04b
AR		 1103 }
1104 }
1105 return 0;
1106}
541ae68f 1107
7b32a312 1108static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 1109/**
1110 * s2io_print_pci_mode -
1111 */
1ee6dd77 1112static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1113{
1ee6dd77 1114 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1115 register u64 val64 = 0;
1116 int mode;
1117 struct config_param *config = &nic->config;
9e39f7c5 1118 const char *pcimode;
541ae68f
K		 1119
1120 val64 = readq(&bar0->pci_mode);
1121 mode = (u8)GET_PCI_MODE(val64);
1122
d44570e4 1123 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f
K		 1124 return -1; /* Unknown PCI mode */
1125
c92ca04b
AR		 1126 config->bus_speed = bus_speed[mode];
1127
1128 if (s2io_on_nec_bridge(nic->pdev)) {
1129 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
d44570e4 1130 nic->dev->name);
c92ca04b
AR		 1131 return mode;
1132 }
1133
d44570e4
JP		 1134 switch (mode) {
1135 case PCI_MODE_PCI_33:
9e39f7c5 1136 pcimode = "33MHz PCI bus";
d44570e4
JP		 1137 break;
1138 case PCI_MODE_PCI_66:
9e39f7c5 1139 pcimode = "66MHz PCI bus";
d44570e4
JP		 1140 break;
1141 case PCI_MODE_PCIX_M1_66:
9e39f7c5 1142 pcimode = "66MHz PCIX(M1) bus";
d44570e4
JP		 1143 break;
1144 case PCI_MODE_PCIX_M1_100:
9e39f7c5 1145 pcimode = "100MHz PCIX(M1) bus";
d44570e4
JP		 1146 break;
1147 case PCI_MODE_PCIX_M1_133:
9e39f7c5 1148 pcimode = "133MHz PCIX(M1) bus";
d44570e4
JP		 1149 break;
1150 case PCI_MODE_PCIX_M2_66:
9e39f7c5 1151 pcimode = "133MHz PCIX(M2) bus";
d44570e4
JP		 1152 break;
1153 case PCI_MODE_PCIX_M2_100:
9e39f7c5 1154 pcimode = "200MHz PCIX(M2) bus";
d44570e4
JP		 1155 break;
1156 case PCI_MODE_PCIX_M2_133:
9e39f7c5 1157 pcimode = "266MHz PCIX(M2) bus";
d44570e4
JP		 1158 break;
1159 default:
9e39f7c5
JP		 1160 pcimode = "unsupported bus!";
1161 mode = -1;
541ae68f
K		 1162 }
1163
9e39f7c5
JP		 1164 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1165 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1166
541ae68f
K		 1167 return mode;
1168}
1169
b7c5678f
RV		 1170/**
1171 * init_tti - Initialization transmit traffic interrupt scheme
1172 * @nic: device private variable
1173 * @link: link status (UP/DOWN) used to enable/disable continuous
1174 * transmit interrupts
1175 * Description: The function configures transmit traffic interrupts
1176 * Return Value: SUCCESS on success and
1177 * '-1' on failure
1178 */
1179
0d66afe7 1180static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1181{
1182 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1183 register u64 val64 = 0;
1184 int i;
ffb5df6c 1185 struct config_param *config = &nic->config;
b7c5678f
RV		 1186
1187 for (i = 0; i < config->tx_fifo_num; i++) {
1188 /*
1189 * TTI Initialization. Default Tx timer gets us about
1190 * 250 interrupts per sec. Continuous interrupts are enabled
1191 * by default.
1192 */
1193 if (nic->device_type == XFRAME_II_DEVICE) {
1194 int count = (nic->config.bus_speed * 125)/2;
1195 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1196 } else
1197 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1198
1199 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
d44570e4
JP		 1200 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1201 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1202 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1203 if (i == 0)
1204 if (use_continuous_tx_intrs && (link == LINK_UP))
1205 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1206 writeq(val64, &bar0->tti_data1_mem);
1207
ac731ab6
SH		 1208 if (nic->config.intr_type == MSI_X) {
1209 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1210 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1211 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1212 TTI_DATA2_MEM_TX_UFC_D(0x300);
1213 } else {
1214 if ((nic->config.tx_steering_type ==
d44570e4
JP		 1215 TX_DEFAULT_STEERING) &&
1216 (config->tx_fifo_num > 1) &&
1217 (i >= nic->udp_fifo_idx) &&
1218 (i < (nic->udp_fifo_idx +
1219 nic->total_udp_fifos)))
ac731ab6
SH		 1220 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1221 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1222 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1223 TTI_DATA2_MEM_TX_UFC_D(0x120);
1224 else
1225 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1226 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1227 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1228 TTI_DATA2_MEM_TX_UFC_D(0x80);
1229 }
b7c5678f
RV		 1230
1231 writeq(val64, &bar0->tti_data2_mem);
1232
d44570e4
JP		 1233 val64 = TTI_CMD_MEM_WE |
1234 TTI_CMD_MEM_STROBE_NEW_CMD |
1235 TTI_CMD_MEM_OFFSET(i);
b7c5678f
RV		 1236 writeq(val64, &bar0->tti_command_mem);
1237
1238 if (wait_for_cmd_complete(&bar0->tti_command_mem,
d44570e4
JP		 1239 TTI_CMD_MEM_STROBE_NEW_CMD,
1240 S2IO_BIT_RESET) != SUCCESS)
b7c5678f
RV		 1241 return FAILURE;
1242 }
1243
1244 return SUCCESS;
1245}
1246
20346722
K		 1247/**
1248 * init_nic - Initialization of hardware
b7c5678f 1249 * @nic: device private variable
20346722
K		 1250 * Description: The function sequentially configures every block
1251 * of the H/W from their reset values.
1252 * Return Value: SUCCESS on success and
1da177e4
LT		 1253 * '-1' on failure (endian settings incorrect).
1254 */
1255
1256static int init_nic(struct s2io_nic *nic)
1257{
1ee6dd77 1258 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1259 struct net_device *dev = nic->dev;
1260 register u64 val64 = 0;
1261 void __iomem *add;
1262 u32 time;
1263 int i, j;
c92ca04b 1264 int dtx_cnt = 0;
1da177e4 1265 unsigned long long mem_share;
20346722 1266 int mem_size;
ffb5df6c
JP		 1267 struct config_param *config = &nic->config;
1268 struct mac_info *mac_control = &nic->mac_control;
1da177e4 1269
5e25b9dd 1270 /* to set the swapper controle on the card */
d44570e4
JP		 1271 if (s2io_set_swapper(nic)) {
1272 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
9f74ffde 1273 return -EIO;
1da177e4
LT		 1274 }
1275
541ae68f
K		 1276 /*
1277 * Herc requires EOI to be removed from reset before XGXS, so..
1278 */
1279 if (nic->device_type & XFRAME_II_DEVICE) {
1280 val64 = 0xA500000000ULL;
1281 writeq(val64, &bar0->sw_reset);
1282 msleep(500);
1283 val64 = readq(&bar0->sw_reset);
1284 }
1285
1da177e4
LT		 1286 /* Remove XGXS from reset state */
1287 val64 = 0;
1288 writeq(val64, &bar0->sw_reset);
1da177e4 1289 msleep(500);
20346722 1290 val64 = readq(&bar0->sw_reset);
1da177e4 1291
7962024e
SH		 1292 /* Ensure that it's safe to access registers by checking
1293 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1294 */
1295 if (nic->device_type == XFRAME_II_DEVICE) {
1296 for (i = 0; i < 50; i++) {
1297 val64 = readq(&bar0->adapter_status);
1298 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1299 break;
1300 msleep(10);
1301 }
1302 if (i == 50)
1303 return -ENODEV;
1304 }
1305
1da177e4
LT		 1306 /* Enable Receiving broadcasts */
1307 add = &bar0->mac_cfg;
1308 val64 = readq(&bar0->mac_cfg);
1309 val64 |= MAC_RMAC_BCAST_ENABLE;
1310 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 1311 writel((u32)val64, add);
1da177e4
LT		 1312 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1313 writel((u32) (val64 >> 32), (add + 4));
1314
1315 /* Read registers in all blocks */
1316 val64 = readq(&bar0->mac_int_mask);
1317 val64 = readq(&bar0->mc_int_mask);
1318 val64 = readq(&bar0->xgxs_int_mask);
1319
1320 /* Set MTU */
1321 val64 = dev->mtu;
1322 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1323
541ae68f
K		 1324 if (nic->device_type & XFRAME_II_DEVICE) {
1325 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1326 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1327 &bar0->dtx_control, UF);
541ae68f
K		 1328 if (dtx_cnt & 0x1)
1329 msleep(1); /* Necessary!! */
1da177e4
LT		 1330 dtx_cnt++;
1331 }
541ae68f 1332 } else {
c92ca04b
AR		 1333 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1334 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1335 &bar0->dtx_control, UF);
1336 val64 = readq(&bar0->dtx_control);
1337 dtx_cnt++;
1da177e4
LT		 1338 }
1339 }
1340
1341 /* Tx DMA Initialization */
1342 val64 = 0;
1343 writeq(val64, &bar0->tx_fifo_partition_0);
1344 writeq(val64, &bar0->tx_fifo_partition_1);
1345 writeq(val64, &bar0->tx_fifo_partition_2);
1346 writeq(val64, &bar0->tx_fifo_partition_3);
1347
1da177e4 1348 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1349 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1350
1351 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1352 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1353
1354 if (i == (config->tx_fifo_num - 1)) {
1355 if (i % 2 == 0)
1356 i++;
1357 }
1358
1359 switch (i) {
1360 case 1:
1361 writeq(val64, &bar0->tx_fifo_partition_0);
1362 val64 = 0;
b7c5678f 1363 j = 0;
1da177e4
LT		 1364 break;
1365 case 3:
1366 writeq(val64, &bar0->tx_fifo_partition_1);
1367 val64 = 0;
b7c5678f 1368 j = 0;
1da177e4
LT		 1369 break;
1370 case 5:
1371 writeq(val64, &bar0->tx_fifo_partition_2);
1372 val64 = 0;
b7c5678f 1373 j = 0;
1da177e4
LT		 1374 break;
1375 case 7:
1376 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1377 val64 = 0;
1378 j = 0;
1379 break;
1380 default:
1381 j++;
1da177e4
LT		 1382 break;
1383 }
1384 }
1385
5e25b9dd
K		 1386 /*
1387 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1388 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1389 */
d44570e4 1390 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
5e25b9dd
K		 1391 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1392
1da177e4
LT		 1393 val64 = readq(&bar0->tx_fifo_partition_0);
1394 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
d44570e4 1395 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1da177e4 1396
20346722
K		 1397 /*
1398 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1399 * integrity checking.
1400 */
1401 val64 = readq(&bar0->tx_pa_cfg);
d44570e4
JP		 1402 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1403 TX_PA_CFG_IGNORE_SNAP_OUI |
1404 TX_PA_CFG_IGNORE_LLC_CTRL |
1405 TX_PA_CFG_IGNORE_L2_ERR;
1da177e4
LT		 1406 writeq(val64, &bar0->tx_pa_cfg);
1407
1408 /* Rx DMA intialization. */
1409 val64 = 0;
1410 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1411 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1412
1413 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1414 }
1415 writeq(val64, &bar0->rx_queue_priority);
1416
20346722
K		 1417 /*
1418 * Allocating equal share of memory to all the
1da177e4
LT		 1419 * configured Rings.
1420 */
1421 val64 = 0;
541ae68f
K		 1422 if (nic->device_type & XFRAME_II_DEVICE)
1423 mem_size = 32;
1424 else
1425 mem_size = 64;
1426
1da177e4
LT		 1427 for (i = 0; i < config->rx_ring_num; i++) {
1428 switch (i) {
1429 case 0:
20346722
K		 1430 mem_share = (mem_size / config->rx_ring_num +
1431 mem_size % config->rx_ring_num);
1da177e4
LT		 1432 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1433 continue;
1434 case 1:
20346722 1435 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1436 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1437 continue;
1438 case 2:
20346722 1439 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1440 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1441 continue;
1442 case 3:
20346722 1443 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1444 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1445 continue;
1446 case 4:
20346722 1447 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1448 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1449 continue;
1450 case 5:
20346722 1451 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1452 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1453 continue;
1454 case 6:
20346722 1455 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1456 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1457 continue;
1458 case 7:
20346722 1459 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1460 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1461 continue;
1462 }
1463 }
1464 writeq(val64, &bar0->rx_queue_cfg);
1465
20346722 1466 /*
5e25b9dd 1467 * Filling Tx round robin registers
b7c5678f 1468 * as per the number of FIFOs for equal scheduling priority
1da177e4 1469 */
5e25b9dd
K		 1470 switch (config->tx_fifo_num) {
1471 case 1:
b7c5678f 1472 val64 = 0x0;
5e25b9dd
K		 1473 writeq(val64, &bar0->tx_w_round_robin_0);
1474 writeq(val64, &bar0->tx_w_round_robin_1);
1475 writeq(val64, &bar0->tx_w_round_robin_2);
1476 writeq(val64, &bar0->tx_w_round_robin_3);
1477 writeq(val64, &bar0->tx_w_round_robin_4);
1478 break;
1479 case 2:
b7c5678f 1480 val64 = 0x0001000100010001ULL;
5e25b9dd 1481 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1482 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1483 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1484 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1485 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1486 writeq(val64, &bar0->tx_w_round_robin_4);
1487 break;
1488 case 3:
b7c5678f 1489 val64 = 0x0001020001020001ULL;
5e25b9dd 1490 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1491 val64 = 0x0200010200010200ULL;
5e25b9dd 1492 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1493 val64 = 0x0102000102000102ULL;
5e25b9dd 1494 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1495 val64 = 0x0001020001020001ULL;
5e25b9dd 1496 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1497 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1498 writeq(val64, &bar0->tx_w_round_robin_4);
1499 break;
1500 case 4:
b7c5678f 1501 val64 = 0x0001020300010203ULL;
5e25b9dd 1502 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1503 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1504 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1506 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1507 writeq(val64, &bar0->tx_w_round_robin_4);
1508 break;
1509 case 5:
b7c5678f 1510 val64 = 0x0001020304000102ULL;
5e25b9dd 1511 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1512 val64 = 0x0304000102030400ULL;
5e25b9dd 1513 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1514 val64 = 0x0102030400010203ULL;
5e25b9dd 1515 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1516 val64 = 0x0400010203040001ULL;
5e25b9dd 1517 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1518 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1519 writeq(val64, &bar0->tx_w_round_robin_4);
1520 break;
1521 case 6:
b7c5678f 1522 val64 = 0x0001020304050001ULL;
5e25b9dd 1523 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1524 val64 = 0x0203040500010203ULL;
5e25b9dd 1525 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1526 val64 = 0x0405000102030405ULL;
5e25b9dd 1527 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1528 val64 = 0x0001020304050001ULL;
5e25b9dd 1529 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1530 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1531 writeq(val64, &bar0->tx_w_round_robin_4);
1532 break;
1533 case 7:
b7c5678f 1534 val64 = 0x0001020304050600ULL;
5e25b9dd 1535 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1536 val64 = 0x0102030405060001ULL;
5e25b9dd 1537 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1538 val64 = 0x0203040506000102ULL;
5e25b9dd 1539 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1540 val64 = 0x0304050600010203ULL;
5e25b9dd 1541 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1542 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1543 writeq(val64, &bar0->tx_w_round_robin_4);
1544 break;
1545 case 8:
b7c5678f 1546 val64 = 0x0001020304050607ULL;
5e25b9dd 1547 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1548 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1549 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1551 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1552 writeq(val64, &bar0->tx_w_round_robin_4);
1553 break;
1554 }
1555
b41477f3 1556 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1557 val64 = readq(&bar0->tx_fifo_partition_0);
1558 val64 |= (TX_FIFO_PARTITION_EN);
1559 writeq(val64, &bar0->tx_fifo_partition_0);
1560
5e25b9dd 1561 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1562 * number of Rings and steering based on QoS with
1563 * equal priority.
1564 */
5e25b9dd
K		 1565 switch (config->rx_ring_num) {
1566 case 1:
0425b46a
SH		 1567 val64 = 0x0;
1568 writeq(val64, &bar0->rx_w_round_robin_0);
1569 writeq(val64, &bar0->rx_w_round_robin_1);
1570 writeq(val64, &bar0->rx_w_round_robin_2);
1571 writeq(val64, &bar0->rx_w_round_robin_3);
1572 writeq(val64, &bar0->rx_w_round_robin_4);
1573
5e25b9dd
K		 1574 val64 = 0x8080808080808080ULL;
1575 writeq(val64, &bar0->rts_qos_steering);
1576 break;
1577 case 2:
0425b46a 1578 val64 = 0x0001000100010001ULL;
5e25b9dd 1579 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1580 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1581 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1582 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1583 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1584 writeq(val64, &bar0->rx_w_round_robin_4);
1585
1586 val64 = 0x8080808040404040ULL;
1587 writeq(val64, &bar0->rts_qos_steering);
1588 break;
1589 case 3:
0425b46a 1590 val64 = 0x0001020001020001ULL;
5e25b9dd 1591 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1592 val64 = 0x0200010200010200ULL;
5e25b9dd 1593 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1594 val64 = 0x0102000102000102ULL;
5e25b9dd 1595 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1596 val64 = 0x0001020001020001ULL;
5e25b9dd 1597 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1598 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1599 writeq(val64, &bar0->rx_w_round_robin_4);
1600
1601 val64 = 0x8080804040402020ULL;
1602 writeq(val64, &bar0->rts_qos_steering);
1603 break;
1604 case 4:
0425b46a 1605 val64 = 0x0001020300010203ULL;
5e25b9dd 1606 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1607 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1608 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1609 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1610 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1611 writeq(val64, &bar0->rx_w_round_robin_4);
1612
1613 val64 = 0x8080404020201010ULL;
1614 writeq(val64, &bar0->rts_qos_steering);
1615 break;
1616 case 5:
0425b46a 1617 val64 = 0x0001020304000102ULL;
5e25b9dd 1618 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1619 val64 = 0x0304000102030400ULL;
5e25b9dd 1620 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1621 val64 = 0x0102030400010203ULL;
5e25b9dd 1622 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1623 val64 = 0x0400010203040001ULL;
5e25b9dd 1624 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1625 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1626 writeq(val64, &bar0->rx_w_round_robin_4);
1627
1628 val64 = 0x8080404020201008ULL;
1629 writeq(val64, &bar0->rts_qos_steering);
1630 break;
1631 case 6:
0425b46a 1632 val64 = 0x0001020304050001ULL;
5e25b9dd 1633 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1634 val64 = 0x0203040500010203ULL;
5e25b9dd 1635 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1636 val64 = 0x0405000102030405ULL;
5e25b9dd 1637 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1638 val64 = 0x0001020304050001ULL;
5e25b9dd 1639 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1640 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1641 writeq(val64, &bar0->rx_w_round_robin_4);
1642
1643 val64 = 0x8080404020100804ULL;
1644 writeq(val64, &bar0->rts_qos_steering);
1645 break;
1646 case 7:
0425b46a 1647 val64 = 0x0001020304050600ULL;
5e25b9dd 1648 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1649 val64 = 0x0102030405060001ULL;
5e25b9dd 1650 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1651 val64 = 0x0203040506000102ULL;
5e25b9dd 1652 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1653 val64 = 0x0304050600010203ULL;
5e25b9dd 1654 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1655 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1656 writeq(val64, &bar0->rx_w_round_robin_4);
1657
1658 val64 = 0x8080402010080402ULL;
1659 writeq(val64, &bar0->rts_qos_steering);
1660 break;
1661 case 8:
0425b46a 1662 val64 = 0x0001020304050607ULL;
5e25b9dd 1663 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1664 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1665 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1666 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1667 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1668 writeq(val64, &bar0->rx_w_round_robin_4);
1669
1670 val64 = 0x8040201008040201ULL;
1671 writeq(val64, &bar0->rts_qos_steering);
1672 break;
1673 }
1da177e4
LT		 1674
1675 /* UDP Fix */
1676 val64 = 0;
20346722 1677 for (i = 0; i < 8; i++)
1da177e4
LT		 1678 writeq(val64, &bar0->rts_frm_len_n[i]);
1679
5e25b9dd
K		 1680 /* Set the default rts frame length for the rings configured */
1681 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1682 for (i = 0 ; i < config->rx_ring_num ; i++)
1683 writeq(val64, &bar0->rts_frm_len_n[i]);
1684
1685 /* Set the frame length for the configured rings
1686 * desired by the user
1687 */
1688 for (i = 0; i < config->rx_ring_num; i++) {
1689 /* If rts_frm_len[i] == 0 then it is assumed that user not
1690 * specified frame length steering.
1691 * If the user provides the frame length then program
1692 * the rts_frm_len register for those values or else
1693 * leave it as it is.
1694 */
1695 if (rts_frm_len[i] != 0) {
1696 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
d44570e4 1697 &bar0->rts_frm_len_n[i]);
5e25b9dd
K		 1698 }
1699 }
8a4bdbaa 1700
9fc93a41
SS		 1701 /* Disable differentiated services steering logic */
1702 for (i = 0; i < 64; i++) {
1703 if (rts_ds_steer(nic, i, 0) == FAILURE) {
9e39f7c5
JP		 1704 DBG_PRINT(ERR_DBG,
1705 "%s: rts_ds_steer failed on codepoint %d\n",
1706 dev->name, i);
9f74ffde 1707 return -ENODEV;
9fc93a41
SS		 1708 }
1709 }
1710
20346722 1711 /* Program statistics memory */
1da177e4 1712 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1713
541ae68f
K		 1714 if (nic->device_type == XFRAME_II_DEVICE) {
1715 val64 = STAT_BC(0x320);
1716 writeq(val64, &bar0->stat_byte_cnt);
1717 }
1718
20346722 1719 /*
1da177e4
LT		 1720 * Initializing the sampling rate for the device to calculate the
1721 * bandwidth utilization.
1722 */
1723 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
d44570e4 1724 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1da177e4
LT		 1725 writeq(val64, &bar0->mac_link_util);
1726
20346722
K		 1727 /*
1728 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1729 * Scheme.
1730 */
1da177e4 1731
b7c5678f
RV		 1732 /* Initialize TTI */
1733 if (SUCCESS != init_tti(nic, nic->last_link_state))
1734 return -ENODEV;
1da177e4 1735
8a4bdbaa
SS		 1736 /* RTI Initialization */
1737 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1738 /*
8a4bdbaa
SS		 1739 * Programmed to generate Apprx 500 Intrs per
1740 * second
1741 */
1742 int count = (nic->config.bus_speed * 125)/4;
1743 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1744 } else
1745 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1746 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
d44570e4
JP		 1747 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1748 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1749 RTI_DATA1_MEM_RX_TIMER_AC_EN;
8a4bdbaa
SS		 1750
1751 writeq(val64, &bar0->rti_data1_mem);
1752
1753 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1754 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1755 if (nic->config.intr_type == MSI_X)
d44570e4
JP		 1756 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1757 RTI_DATA2_MEM_RX_UFC_D(0x40));
8a4bdbaa 1758 else
d44570e4
JP		 1759 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1760 RTI_DATA2_MEM_RX_UFC_D(0x80));
8a4bdbaa 1761 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1762
8a4bdbaa 1763 for (i = 0; i < config->rx_ring_num; i++) {
d44570e4
JP		 1764 val64 = RTI_CMD_MEM_WE |
1765 RTI_CMD_MEM_STROBE_NEW_CMD |
1766 RTI_CMD_MEM_OFFSET(i);
8a4bdbaa 1767 writeq(val64, &bar0->rti_command_mem);
1da177e4 1768
8a4bdbaa
SS		 1769 /*
1770 * Once the operation completes, the Strobe bit of the
1771 * command register will be reset. We poll for this
1772 * particular condition. We wait for a maximum of 500ms
1773 * for the operation to complete, if it's not complete
1774 * by then we return error.
1775 */
1776 time = 0;
f957bcf0 1777 while (true) {
8a4bdbaa
SS		 1778 val64 = readq(&bar0->rti_command_mem);
1779 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1780 break;
b6e3f982 1781
8a4bdbaa 1782 if (time > 10) {
9e39f7c5 1783 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
8a4bdbaa 1784 dev->name);
9f74ffde 1785 return -ENODEV;
b6e3f982 1786 }
8a4bdbaa
SS		 1787 time++;
1788 msleep(50);
1da177e4 1789 }
1da177e4
LT		 1790 }
1791
20346722
K		 1792 /*
1793 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1794 * the 8 Queues on Rx side.
1795 */
1796 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1798
1799 /* Disable RMAC PAD STRIPPING */
509a2671 1800 add = &bar0->mac_cfg;
1da177e4
LT		 1801 val64 = readq(&bar0->mac_cfg);
1802 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1803 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1804 writel((u32) (val64), add);
1805 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806 writel((u32) (val64 >> 32), (add + 4));
1807 val64 = readq(&bar0->mac_cfg);
1808
7d3d0439
RA		 1809 /* Enable FCS stripping by adapter */
1810 add = &bar0->mac_cfg;
1811 val64 = readq(&bar0->mac_cfg);
1812 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1813 if (nic->device_type == XFRAME_II_DEVICE)
1814 writeq(val64, &bar0->mac_cfg);
1815 else {
1816 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817 writel((u32) (val64), add);
1818 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1819 writel((u32) (val64 >> 32), (add + 4));
1820 }
1821
20346722
K		 1822 /*
1823 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1824 * generated by xena.
1825 */
1826 val64 = readq(&bar0->rmac_pause_cfg);
1827 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1828 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1829 writeq(val64, &bar0->rmac_pause_cfg);
1830
20346722 1831 /*
1da177e4
LT		 1832 * Set the Threshold Limit for Generating the pause frame
1833 * If the amount of data in any Queue exceeds ratio of
1834 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1835 * pause frame is generated
1836 */
1837 val64 = 0;
1838 for (i = 0; i < 4; i++) {
d44570e4
JP		 1839 val64 |= (((u64)0xFF00 |
1840 nic->mac_control.mc_pause_threshold_q0q3)
1841 << (i * 2 * 8));
1da177e4
LT		 1842 }
1843 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1844
1845 val64 = 0;
1846 for (i = 0; i < 4; i++) {
d44570e4
JP		 1847 val64 |= (((u64)0xFF00 |
1848 nic->mac_control.mc_pause_threshold_q4q7)
1849 << (i * 2 * 8));
1da177e4
LT		 1850 }
1851 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1852
20346722
K		 1853 /*
1854 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1855 * exceeded the limit pointed by shared_splits
1856 */
1857 val64 = readq(&bar0->pic_control);
1858 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1859 writeq(val64, &bar0->pic_control);
1860
863c11a9
AR		 1861 if (nic->config.bus_speed == 266) {
1862 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1863 writeq(0x0, &bar0->read_retry_delay);
1864 writeq(0x0, &bar0->write_retry_delay);
1865 }
1866
541ae68f
K		 1867 /*
1868 * Programming the Herc to split every write transaction
1869 * that does not start on an ADB to reduce disconnects.
1870 */
1871 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1872 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1873 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1874 writeq(val64, &bar0->misc_control);
1875 val64 = readq(&bar0->pic_control2);
b7b5a128 1876 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1877 writeq(val64, &bar0->pic_control2);
541ae68f 1878 }
c92ca04b
AR		 1879 if (strstr(nic->product_name, "CX4")) {
1880 val64 = TMAC_AVG_IPG(0x17);
1881 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1882 }
1883
1da177e4
LT		 1884 return SUCCESS;
1885}
a371a07d
K		 1886#define LINK_UP_DOWN_INTERRUPT 1
1887#define MAC_RMAC_ERR_TIMER 2
1888
1ee6dd77 1889static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d
K		 1890{
1891 if (nic->device_type == XFRAME_II_DEVICE)
1892 return LINK_UP_DOWN_INTERRUPT;
1893 else
1894 return MAC_RMAC_ERR_TIMER;
1895}
8116f3cf 1896
9caab458
SS		 1897/**
1898 * do_s2io_write_bits - update alarm bits in alarm register
1899 * @value: alarm bits
1900 * @flag: interrupt status
1901 * @addr: address value
1902 * Description: update alarm bits in alarm register
1903 * Return Value:
1904 * NONE.
1905 */
1906static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1907{
1908 u64 temp64;
1909
1910 temp64 = readq(addr);
1911
d44570e4
JP		 1912 if (flag == ENABLE_INTRS)
1913 temp64 &= ~((u64)value);
9caab458 1914 else
d44570e4 1915 temp64 |= ((u64)value);
9caab458
SS		 1916 writeq(temp64, addr);
1917}
1da177e4 1918
43b7c451 1919static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1920{
1921 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1922 register u64 gen_int_mask = 0;
01e16faa 1923 u64 interruptible;
9caab458 1924
01e16faa 1925 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458 1926 if (mask & TX_DMA_INTR) {
9caab458
SS		 1927 gen_int_mask |= TXDMA_INT_M;
1928
1929 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
d44570e4
JP		 1930 TXDMA_PCC_INT | TXDMA_TTI_INT |
1931 TXDMA_LSO_INT | TXDMA_TPA_INT |
1932 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
9caab458
SS		 1933
1934 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
d44570e4
JP		 1935 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1936 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1937 &bar0->pfc_err_mask);
9caab458
SS		 1938
1939 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
d44570e4
JP		 1940 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1941 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
9caab458
SS		 1942
1943 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
d44570e4
JP		 1944 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1945 PCC_N_SERR | PCC_6_COF_OV_ERR |
1946 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1947 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1948 PCC_TXB_ECC_SG_ERR,
1949 flag, &bar0->pcc_err_mask);
9caab458
SS		 1950
1951 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
d44570e4 1952 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
9caab458
SS		 1953
1954 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
d44570e4
JP		 1955 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1956 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1957 flag, &bar0->lso_err_mask);
9caab458
SS		 1958
1959 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
d44570e4 1960 flag, &bar0->tpa_err_mask);
9caab458
SS		 1961
1962 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
9caab458
SS		 1963 }
1964
1965 if (mask & TX_MAC_INTR) {
1966 gen_int_mask |= TXMAC_INT_M;
1967 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
d44570e4 1968 &bar0->mac_int_mask);
9caab458 1969 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
d44570e4
JP		 1970 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1971 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1972 flag, &bar0->mac_tmac_err_mask);
9caab458
SS		 1973 }
1974
1975 if (mask & TX_XGXS_INTR) {
1976 gen_int_mask |= TXXGXS_INT_M;
1977 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
d44570e4 1978 &bar0->xgxs_int_mask);
9caab458 1979 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
d44570e4
JP		 1980 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1981 flag, &bar0->xgxs_txgxs_err_mask);
9caab458
SS		 1982 }
1983
1984 if (mask & RX_DMA_INTR) {
1985 gen_int_mask |= RXDMA_INT_M;
1986 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
d44570e4
JP		 1987 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1988 flag, &bar0->rxdma_int_mask);
9caab458 1989 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
d44570e4
JP		 1990 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1991 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1992 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
9caab458 1993 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
d44570e4
JP		 1994 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1995 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1996 &bar0->prc_pcix_err_mask);
9caab458 1997 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
d44570e4
JP		 1998 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1999 &bar0->rpa_err_mask);
9caab458 2000 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
d44570e4
JP		 2001 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2002 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2003 RDA_FRM_ECC_SG_ERR |
2004 RDA_MISC_ERR|RDA_PCIX_ERR,
2005 flag, &bar0->rda_err_mask);
9caab458 2006 do_s2io_write_bits(RTI_SM_ERR_ALARM |
d44570e4
JP		 2007 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2008 flag, &bar0->rti_err_mask);
9caab458
SS		 2009 }
2010
2011 if (mask & RX_MAC_INTR) {
2012 gen_int_mask |= RXMAC_INT_M;
2013 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
d44570e4
JP		 2014 &bar0->mac_int_mask);
2015 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2016 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2017 RMAC_DOUBLE_ECC_ERR);
01e16faa
SH		 2018 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2019 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2020 do_s2io_write_bits(interruptible,
d44570e4 2021 flag, &bar0->mac_rmac_err_mask);
9caab458
SS		 2022 }
2023
d44570e4 2024 if (mask & RX_XGXS_INTR) {
9caab458
SS		 2025 gen_int_mask |= RXXGXS_INT_M;
2026 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
d44570e4 2027 &bar0->xgxs_int_mask);
9caab458 2028 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
d44570e4 2029 &bar0->xgxs_rxgxs_err_mask);
9caab458
SS		 2030 }
2031
2032 if (mask & MC_INTR) {
2033 gen_int_mask |= MC_INT_M;
d44570e4
JP		 2034 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2035 flag, &bar0->mc_int_mask);
9caab458 2036 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
d44570e4
JP		 2037 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2038 &bar0->mc_err_mask);
9caab458
SS		 2039 }
2040 nic->general_int_mask = gen_int_mask;
2041
2042 /* Remove this line when alarm interrupts are enabled */
2043 nic->general_int_mask = 0;
2044}
d44570e4 2045
20346722
K		 2046/**
2047 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2048 * @nic: device private variable,
2049 * @mask: A mask indicating which Intr block must be modified and,
2050 * @flag: A flag indicating whether to enable or disable the Intrs.
2051 * Description: This function will either disable or enable the interrupts
20346722
K		 2052 * depending on the flag argument. The mask argument can be used to
2053 * enable/disable any Intr block.
1da177e4
LT		 2054 * Return Value: NONE.
2055 */
2056
2057static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2058{
1ee6dd77 2059 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2060 register u64 temp64 = 0, intr_mask = 0;
2061
2062 intr_mask = nic->general_int_mask;
1da177e4
LT		 2063
2064 /* Top level interrupt classification */
2065 /* PIC Interrupts */
9caab458 2066 if (mask & TX_PIC_INTR) {
1da177e4 2067 /* Enable PIC Intrs in the general intr mask register */
9caab458 2068 intr_mask |= TXPIC_INT_M;
1da177e4 2069 if (flag == ENABLE_INTRS) {
20346722 2070 /*
a371a07d 2071 * If Hercules adapter enable GPIO otherwise
b41477f3 2072 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 2073 * interrupts for now.
2074 * TODO
1da177e4 2075 */
a371a07d 2076 if (s2io_link_fault_indication(nic) ==
d44570e4 2077 LINK_UP_DOWN_INTERRUPT) {
9caab458 2078 do_s2io_write_bits(PIC_INT_GPIO, flag,
d44570e4 2079 &bar0->pic_int_mask);
9caab458 2080 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
d44570e4 2081 &bar0->gpio_int_mask);
9caab458 2082 } else
a371a07d 2083 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2084 } else if (flag == DISABLE_INTRS) {
20346722
K		 2085 /*
2086 * Disable PIC Intrs in the general
2087 * intr mask register
1da177e4
LT		 2088 */
2089 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2090 }
2091 }
2092
1da177e4
LT		 2093 /* Tx traffic interrupts */
2094 if (mask & TX_TRAFFIC_INTR) {
9caab458 2095 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2096 if (flag == ENABLE_INTRS) {
20346722 2097 /*
1da177e4 2098 * Enable all the Tx side interrupts
20346722 2099 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2100 */
2101 writeq(0x0, &bar0->tx_traffic_mask);
2102 } else if (flag == DISABLE_INTRS) {
20346722
K		 2103 /*
2104 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2105 * register.
2106 */
2107 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2108 }
2109 }
2110
2111 /* Rx traffic interrupts */
2112 if (mask & RX_TRAFFIC_INTR) {
9caab458 2113 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2114 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2115 /* writing 0 Enables all 8 RX interrupt levels */
2116 writeq(0x0, &bar0->rx_traffic_mask);
2117 } else if (flag == DISABLE_INTRS) {
20346722
K		 2118 /*
2119 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2120 * register.
2121 */
2122 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2123 }
2124 }
9caab458
SS		 2125
2126 temp64 = readq(&bar0->general_int_mask);
2127 if (flag == ENABLE_INTRS)
d44570e4 2128 temp64 &= ~((u64)intr_mask);
9caab458
SS		 2129 else
2130 temp64 = DISABLE_ALL_INTRS;
2131 writeq(temp64, &bar0->general_int_mask);
2132
2133 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2134}
2135
19a60522
SS		 2136/**
2137 * verify_pcc_quiescent- Checks for PCC quiescent state
2138 * Return: 1 If PCC is quiescence
2139 * 0 If PCC is not quiescence
2140 */
1ee6dd77 2141static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2142{
19a60522 2143 int ret = 0, herc;
1ee6dd77 2144 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2145 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2146
19a60522 2147 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2148
f957bcf0 2149 if (flag == false) {
44c10138 2150 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2151 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2152 ret = 1;
19a60522
SS		 2153 } else {
2154 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2155 ret = 1;
20346722
K		 2156 }
2157 } else {
44c10138 2158 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2159 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2160 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2161 ret = 1;
5e25b9dd
K		 2162 } else {
2163 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2164 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2165 ret = 1;
20346722
K		 2166 }
2167 }
2168
2169 return ret;
2170}
2171/**
2172 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2173 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2174 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2175 * differs and the calling function passes the input argument flag to
2176 * indicate this.
20346722 2177 * Return: 1 If xena is quiescence
1da177e4
LT		 2178 * 0 If Xena is not quiescence
2179 */
2180
1ee6dd77 2181static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2182{
19a60522 2183 int mode;
1ee6dd77 2184 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2185 u64 val64 = readq(&bar0->adapter_status);
2186 mode = s2io_verify_pci_mode(sp);
1da177e4 2187
19a60522 2188 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
9e39f7c5 2189 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
19a60522
SS		 2190 return 0;
2191 }
2192 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
9e39f7c5 2193 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
19a60522
SS		 2194 return 0;
2195 }
2196 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
9e39f7c5 2197 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
19a60522
SS		 2198 return 0;
2199 }
2200 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
9e39f7c5 2201 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
19a60522
SS		 2202 return 0;
2203 }
2204 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
9e39f7c5 2205 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
19a60522
SS		 2206 return 0;
2207 }
2208 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
9e39f7c5 2209 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
19a60522
SS		 2210 return 0;
2211 }
2212 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
9e39f7c5 2213 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
19a60522
SS		 2214 return 0;
2215 }
2216 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
9e39f7c5 2217 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
19a60522 2218 return 0;
1da177e4
LT		 2219 }
2220
19a60522
SS		 2221 /*
2222 * In PCI 33 mode, the P_PLL is not used, and therefore,
2223 * the the P_PLL_LOCK bit in the adapter_status register will
2224 * not be asserted.
2225 */
2226 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
d44570e4
JP		 2227 sp->device_type == XFRAME_II_DEVICE &&
2228 mode != PCI_MODE_PCI_33) {
9e39f7c5 2229 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
19a60522
SS		 2230 return 0;
2231 }
2232 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
d44570e4 2233 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
9e39f7c5 2234 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
19a60522
SS		 2235 return 0;
2236 }
2237 return 1;
1da177e4
LT		 2238}
2239
2240/**
2241 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2242 * @sp: Pointer to device specifc structure
20346722 2243 * Description :
1da177e4
LT		 2244 * New procedure to clear mac address reading problems on Alpha platforms
2245 *
2246 */
2247
d44570e4 2248static void fix_mac_address(struct s2io_nic *sp)
1da177e4 2249{
1ee6dd77 2250 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2251 u64 val64;
2252 int i = 0;
2253
2254 while (fix_mac[i] != END_SIGN) {
2255 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2256 udelay(10);
1da177e4
LT		 2257 val64 = readq(&bar0->gpio_control);
2258 }
2259}
2260
2261/**
20346722 2262 * start_nic - Turns the device on
1da177e4 2263 * @nic : device private variable.
20346722
K		 2264 * Description:
2265 * This function actually turns the device on. Before this function is
2266 * called,all Registers are configured from their reset states
2267 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2268 * calling this function, the device interrupts are cleared and the NIC is
2269 * literally switched on by writing into the adapter control register.
20346722 2270 * Return Value:
1da177e4
LT		 2271 * SUCCESS on success and -1 on failure.
2272 */
2273
2274static int start_nic(struct s2io_nic *nic)
2275{
1ee6dd77 2276 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2277 struct net_device *dev = nic->dev;
2278 register u64 val64 = 0;
20346722 2279 u16 subid, i;
ffb5df6c
JP		 2280 struct config_param *config = &nic->config;
2281 struct mac_info *mac_control = &nic->mac_control;
1da177e4
LT		 2282
2283 /* PRC Initialization and configuration */
2284 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2285 struct ring_info *ring = &mac_control->rings[i];
2286
d44570e4 2287 writeq((u64)ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2288 &bar0->prc_rxd0_n[i]);
2289
2290 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2291 if (nic->rxd_mode == RXD_MODE_1)
2292 val64 |= PRC_CTRL_RC_ENABLED;
2293 else
2294 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2295 if (nic->device_type == XFRAME_II_DEVICE)
2296 val64 |= PRC_CTRL_GROUP_READS;
2297 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2298 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2299 writeq(val64, &bar0->prc_ctrl_n[i]);
2300 }
2301
da6971d8
AR		 2302 if (nic->rxd_mode == RXD_MODE_3B) {
2303 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2304 val64 = readq(&bar0->rx_pa_cfg);
2305 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2306 writeq(val64, &bar0->rx_pa_cfg);
2307 }
1da177e4 2308
926930b2
SS		 2309 if (vlan_tag_strip == 0) {
2310 val64 = readq(&bar0->rx_pa_cfg);
2311 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2312 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2313 nic->vlan_strip_flag = 0;
926930b2
SS		 2314 }
2315
20346722 2316 /*
1da177e4
LT		 2317 * Enabling MC-RLDRAM. After enabling the device, we timeout
2318 * for around 100ms, which is approximately the time required
2319 * for the device to be ready for operation.
2320 */
2321 val64 = readq(&bar0->mc_rldram_mrs);
2322 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2323 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2324 val64 = readq(&bar0->mc_rldram_mrs);
2325
20346722 2326 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2327
2328 /* Enabling ECC Protection. */
2329 val64 = readq(&bar0->adapter_control);
2330 val64 &= ~ADAPTER_ECC_EN;
2331 writeq(val64, &bar0->adapter_control);
2332
20346722
K		 2333 /*
2334 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2335 * it.
2336 */
2337 val64 = readq(&bar0->adapter_status);
19a60522 2338 if (!verify_xena_quiescence(nic)) {
9e39f7c5
JP		 2339 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2340 "Adapter status reads: 0x%llx\n",
2341 dev->name, (unsigned long long)val64);
1da177e4
LT		 2342 return FAILURE;
2343 }
2344
20346722 2345 /*
1da177e4 2346 * With some switches, link might be already up at this point.
20346722
K		 2347 * Because of this weird behavior, when we enable laser,
2348 * we may not get link. We need to handle this. We cannot
2349 * figure out which switch is misbehaving. So we are forced to
2350 * make a global change.
1da177e4
LT		 2351 */
2352
2353 /* Enabling Laser. */
2354 val64 = readq(&bar0->adapter_control);
2355 val64 |= ADAPTER_EOI_TX_ON;
2356 writeq(val64, &bar0->adapter_control);
2357
c92ca04b
AR		 2358 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2359 /*
2360 * Dont see link state interrupts initally on some switches,
2361 * so directly scheduling the link state task here.
2362 */
2363 schedule_work(&nic->set_link_task);
2364 }
1da177e4
LT		 2365 /* SXE-002: Initialize link and activity LED */
2366 subid = nic->pdev->subsystem_device;
541ae68f
K		 2367 if (((subid & 0xFF) >= 0x07) &&
2368 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2369 val64 = readq(&bar0->gpio_control);
2370 val64 |= 0x0000800000000000ULL;
2371 writeq(val64, &bar0->gpio_control);
2372 val64 = 0x0411040400000000ULL;
509a2671 2373 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2374 }
2375
1da177e4
LT		 2376 return SUCCESS;
2377}
fed5eccd
AR		 2378/**
2379 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2380 */
d44570e4
JP		 2381static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2382 struct TxD *txdlp, int get_off)
fed5eccd 2383{
1ee6dd77 2384 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2385 struct sk_buff *skb;
1ee6dd77 2386 struct TxD *txds;
fed5eccd
AR		 2387 u16 j, frg_cnt;
2388
2389 txds = txdlp;
2fda096d 2390 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
d44570e4
JP		 2391 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2392 sizeof(u64), PCI_DMA_TODEVICE);
fed5eccd
AR		 2393 txds++;
2394 }
2395
d44570e4 2396 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
fed5eccd 2397 if (!skb) {
1ee6dd77 2398 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2399 return NULL;
2400 }
d44570e4 2401 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
e743d313 2402 skb_headlen(skb), PCI_DMA_TODEVICE);
fed5eccd
AR		 2403 frg_cnt = skb_shinfo(skb)->nr_frags;
2404 if (frg_cnt) {
2405 txds++;
2406 for (j = 0; j < frg_cnt; j++, txds++) {
2407 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2408 if (!txds->Buffer_Pointer)
2409 break;
d44570e4
JP		 2410 pci_unmap_page(nic->pdev,
2411 (dma_addr_t)txds->Buffer_Pointer,
fed5eccd
AR		 2412 frag->size, PCI_DMA_TODEVICE);
2413 }
2414 }
d44570e4
JP		 2415 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2416 return skb;
fed5eccd 2417}
1da177e4 2418
20346722
K		 2419/**
2420 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2421 * @nic : device private variable.
20346722 2422 * Description:
1da177e4 2423 * Free all queued Tx buffers.
20346722 2424 * Return Value: void
d44570e4 2425 */
1da177e4
LT		 2426
2427static void free_tx_buffers(struct s2io_nic *nic)
2428{
2429 struct net_device *dev = nic->dev;
2430 struct sk_buff *skb;
1ee6dd77 2431 struct TxD *txdp;
1da177e4 2432 int i, j;
fed5eccd 2433 int cnt = 0;
ffb5df6c
JP		 2434 struct config_param *config = &nic->config;
2435 struct mac_info *mac_control = &nic->mac_control;
2436 struct stat_block *stats = mac_control->stats_info;
2437 struct swStat *swstats = &stats->sw_stat;
1da177e4
LT		 2438
2439 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2440 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2441 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2442 unsigned long flags;
13d866a9
JP		 2443
2444 spin_lock_irqsave(&fifo->tx_lock, flags);
2445 for (j = 0; j < tx_cfg->fifo_len; j++) {
2446 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2447 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2448 if (skb) {
ffb5df6c 2449 swstats->mem_freed += skb->truesize;
fed5eccd
AR		 2450 dev_kfree_skb(skb);
2451 cnt++;
1da177e4 2452 }
1da177e4
LT		 2453 }
2454 DBG_PRINT(INTR_DBG,
9e39f7c5 2455 "%s: forcibly freeing %d skbs on FIFO%d\n",
1da177e4 2456 dev->name, cnt, i);
13d866a9
JP		 2457 fifo->tx_curr_get_info.offset = 0;
2458 fifo->tx_curr_put_info.offset = 0;
2459 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2460 }
2461}
2462
20346722
K		 2463/**
2464 * stop_nic - To stop the nic
1da177e4 2465 * @nic ; device private variable.
20346722
K		 2466 * Description:
2467 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2468 * function does. This function is called to stop the device.
2469 * Return Value:
2470 * void.
2471 */
2472
2473static void stop_nic(struct s2io_nic *nic)
2474{
1ee6dd77 2475 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2476 register u64 val64 = 0;
5d3213cc 2477 u16 interruptible;
1da177e4
LT		 2478
2479 /* Disable all interrupts */
9caab458 2480 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2481 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2482 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2483 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2484
5d3213cc
AR		 2485 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2486 val64 = readq(&bar0->adapter_control);
2487 val64 &= ~(ADAPTER_CNTL_EN);
2488 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2489}
2490
20346722
K		 2491/**
2492 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2493 * @ring_info: per ring structure
3f78d885
SH		 2494 * @from_card_up: If this is true, we will map the buffer to get
2495 * the dma address for buf0 and buf1 to give it to the card.
2496 * Else we will sync the already mapped buffer to give it to the card.
20346722 2497 * Description:
1da177e4
LT		 2498 * The function allocates Rx side skbs and puts the physical
2499 * address of these buffers into the RxD buffer pointers, so that the NIC
2500 * can DMA the received frame into these locations.
2501 * The NIC supports 3 receive modes, viz
2502 * 1. single buffer,
2503 * 2. three buffer and
2504 * 3. Five buffer modes.
20346722
K		 2505 * Each mode defines how many fragments the received frame will be split
2506 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2507 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2508 * is split into 3 fragments. As of now only single buffer mode is
2509 * supported.
2510 * Return Value:
2511 * SUCCESS on success or an appropriate -ve value on failure.
2512 */
8d8bb39b 2513static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
d44570e4 2514 int from_card_up)
1da177e4 2515{
1da177e4 2516 struct sk_buff *skb;
1ee6dd77 2517 struct RxD_t *rxdp;
0425b46a 2518 int off, size, block_no, block_no1;
1da177e4 2519 u32 alloc_tab = 0;
20346722 2520 u32 alloc_cnt;
20346722 2521 u64 tmp;
1ee6dd77 2522 struct buffAdd *ba;
1ee6dd77 2523 struct RxD_t *first_rxdp = NULL;
363dc367 2524 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2525 int rxd_index = 0;
6d517a27
VP		 2526 struct RxD1 *rxdp1;
2527 struct RxD3 *rxdp3;
ffb5df6c 2528 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2529
0425b46a 2530 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2531
0425b46a 2532 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2533 while (alloc_tab < alloc_cnt) {
0425b46a 2534 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2535
0425b46a
SH		 2536 off = ring->rx_curr_put_info.offset;
2537
2538 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2539
2540 rxd_index = off + 1;
2541 if (block_no)
2542 rxd_index += (block_no * ring->rxd_count);
da6971d8 2543
7d2e3cb7 2544 if ((block_no == block_no1) &&
d44570e4
JP		 2545 (off == ring->rx_curr_get_info.offset) &&
2546 (rxdp->Host_Control)) {
9e39f7c5
JP		 2547 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2548 ring->dev->name);
1da177e4
LT		 2549 goto end;
2550 }
0425b46a
SH		 2551 if (off && (off == ring->rxd_count)) {
2552 ring->rx_curr_put_info.block_index++;
2553 if (ring->rx_curr_put_info.block_index ==
d44570e4 2554 ring->block_count)
0425b46a
SH		 2555 ring->rx_curr_put_info.block_index = 0;
2556 block_no = ring->rx_curr_put_info.block_index;
2557 off = 0;
2558 ring->rx_curr_put_info.offset = off;
2559 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2560 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2561 ring->dev->name, rxdp);
2562
1da177e4 2563 }
c9fcbf47 2564
da6971d8 2565 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
d44570e4
JP		 2566 ((ring->rxd_mode == RXD_MODE_3B) &&
2567 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2568 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2569 goto end;
2570 }
da6971d8 2571 /* calculate size of skb based on ring mode */
d44570e4
JP		 2572 size = ring->mtu +
2573 HEADER_ETHERNET_II_802_3_SIZE +
2574 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2575 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2576 size += NET_IP_ALIGN;
da6971d8 2577 else
0425b46a 2578 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2579
da6971d8
AR		 2580 /* allocate skb */
2581 skb = dev_alloc_skb(size);
d44570e4 2582 if (!skb) {
9e39f7c5
JP		 2583 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2584 ring->dev->name);
303bcb4b
K		 2585 if (first_rxdp) {
2586 wmb();
2587 first_rxdp->Control_1 |= RXD_OWN_XENA;
2588 }
ffb5df6c 2589 swstats->mem_alloc_fail_cnt++;
7d2e3cb7 2590
da6971d8
AR		 2591 return -ENOMEM ;
2592 }
ffb5df6c 2593 swstats->mem_allocated += skb->truesize;
0425b46a
SH		 2594
2595 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2596 /* 1 buffer mode - normal operation mode */
d44570e4 2597 rxdp1 = (struct RxD1 *)rxdp;
1ee6dd77 2598 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2599 skb_reserve(skb, NET_IP_ALIGN);
d44570e4
JP		 2600 rxdp1->Buffer0_ptr =
2601 pci_map_single(ring->pdev, skb->data,
2602 size - NET_IP_ALIGN,
2603 PCI_DMA_FROMDEVICE);
8d8bb39b 2604 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2605 rxdp1->Buffer0_ptr))
491abf25
VP		 2606 goto pci_map_failed;
2607
8a4bdbaa 2608 rxdp->Control_2 =
491976b2 2609 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
d44570e4 2610 rxdp->Host_Control = (unsigned long)skb;
0425b46a 2611 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2612 /*
6d517a27
VP		 2613 * 2 buffer mode -
2614 * 2 buffer mode provides 128
da6971d8 2615 * byte aligned receive buffers.
da6971d8
AR		 2616 */
2617
d44570e4 2618 rxdp3 = (struct RxD3 *)rxdp;
491976b2 2619 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2620 Buffer0_ptr = rxdp3->Buffer0_ptr;
2621 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2622 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2623 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2624 rxdp3->Buffer0_ptr = Buffer0_ptr;
2625 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2626
0425b46a 2627 ba = &ring->ba[block_no][off];
da6971d8 2628 skb_reserve(skb, BUF0_LEN);
d44570e4 2629 tmp = (u64)(unsigned long)skb->data;
da6971d8
AR		 2630 tmp += ALIGN_SIZE;
2631 tmp &= ~ALIGN_SIZE;
2632 skb->data = (void *) (unsigned long)tmp;
27a884dc 2633 skb_reset_tail_pointer(skb);
da6971d8 2634
3f78d885 2635 if (from_card_up) {
6d517a27 2636 rxdp3->Buffer0_ptr =
d44570e4
JP		 2637 pci_map_single(ring->pdev, ba->ba_0,
2638 BUF0_LEN,
2639 PCI_DMA_FROMDEVICE);
2640 if (pci_dma_mapping_error(nic->pdev,
2641 rxdp3->Buffer0_ptr))
3f78d885
SH		 2642 goto pci_map_failed;
2643 } else
0425b46a 2644 pci_dma_sync_single_for_device(ring->pdev,
d44570e4
JP		 2645 (dma_addr_t)rxdp3->Buffer0_ptr,
2646 BUF0_LEN,
2647 PCI_DMA_FROMDEVICE);
491abf25 2648
da6971d8 2649 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2650 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2651 /* Two buffer mode */
2652
2653 /*
6aa20a22 2654 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2655 * L4 payload
2656 */
d44570e4
JP		 2657 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2658 skb->data,
2659 ring->mtu + 4,
2660 PCI_DMA_FROMDEVICE);
da6971d8 2661
8d8bb39b 2662 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2663 rxdp3->Buffer2_ptr))
491abf25
VP		 2664 goto pci_map_failed;
2665
3f78d885 2666 if (from_card_up) {
0425b46a
SH		 2667 rxdp3->Buffer1_ptr =
2668 pci_map_single(ring->pdev,
d44570e4
JP		 2669 ba->ba_1,
2670 BUF1_LEN,
2671 PCI_DMA_FROMDEVICE);
0425b46a 2672
8d8bb39b 2673 if (pci_dma_mapping_error(nic->pdev,
d44570e4
JP		 2674 rxdp3->Buffer1_ptr)) {
2675 pci_unmap_single(ring->pdev,
2676 (dma_addr_t)(unsigned long)
2677 skb->data,
2678 ring->mtu + 4,
2679 PCI_DMA_FROMDEVICE);
3f78d885
SH		 2680 goto pci_map_failed;
2681 }
75c30b13 2682 }
da6971d8
AR		 2683 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2684 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
d44570e4 2685 (ring->mtu + 4);
da6971d8 2686 }
b7b5a128 2687 rxdp->Control_2 |= s2BIT(0);
0425b46a 2688 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2689 }
303bcb4b
K		 2690 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2691 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2692 off++;
0425b46a 2693 if (off == (ring->rxd_count + 1))
da6971d8 2694 off = 0;
0425b46a 2695 ring->rx_curr_put_info.offset = off;
20346722 2696
da6971d8 2697 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2698 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2699 if (first_rxdp) {
2700 wmb();
2701 first_rxdp->Control_1 |= RXD_OWN_XENA;
2702 }
2703 first_rxdp = rxdp;
2704 }
0425b46a 2705 ring->rx_bufs_left += 1;
1da177e4
LT		 2706 alloc_tab++;
2707 }
2708
d44570e4 2709end:
303bcb4b
K		 2710 /* Transfer ownership of first descriptor to adapter just before
2711 * exiting. Before that, use memory barrier so that ownership
2712 * and other fields are seen by adapter correctly.
2713 */
2714 if (first_rxdp) {
2715 wmb();
2716 first_rxdp->Control_1 |= RXD_OWN_XENA;
2717 }
2718
1da177e4 2719 return SUCCESS;
d44570e4 2720
491abf25 2721pci_map_failed:
ffb5df6c
JP		 2722 swstats->pci_map_fail_cnt++;
2723 swstats->mem_freed += skb->truesize;
491abf25
VP		 2724 dev_kfree_skb_irq(skb);
2725 return -ENOMEM;
1da177e4
LT		 2726}
2727
da6971d8
AR		 2728static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2729{
2730 struct net_device *dev = sp->dev;
2731 int j;
2732 struct sk_buff *skb;
1ee6dd77 2733 struct RxD_t *rxdp;
1ee6dd77 2734 struct buffAdd *ba;
6d517a27
VP		 2735 struct RxD1 *rxdp1;
2736 struct RxD3 *rxdp3;
ffb5df6c
JP		 2737 struct mac_info *mac_control = &sp->mac_control;
2738 struct stat_block *stats = mac_control->stats_info;
2739 struct swStat *swstats = &stats->sw_stat;
da6971d8 2740
da6971d8
AR		 2741 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2742 rxdp = mac_control->rings[ring_no].
d44570e4
JP		 2743 rx_blocks[blk].rxds[j].virt_addr;
2744 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2745 if (!skb)
da6971d8 2746 continue;
da6971d8 2747 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4
JP		 2748 rxdp1 = (struct RxD1 *)rxdp;
2749 pci_unmap_single(sp->pdev,
2750 (dma_addr_t)rxdp1->Buffer0_ptr,
2751 dev->mtu +
2752 HEADER_ETHERNET_II_802_3_SIZE +
2753 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2754 PCI_DMA_FROMDEVICE);
1ee6dd77 2755 memset(rxdp, 0, sizeof(struct RxD1));
d44570e4
JP		 2756 } else if (sp->rxd_mode == RXD_MODE_3B) {
2757 rxdp3 = (struct RxD3 *)rxdp;
2758 ba = &mac_control->rings[ring_no].ba[blk][j];
2759 pci_unmap_single(sp->pdev,
2760 (dma_addr_t)rxdp3->Buffer0_ptr,
2761 BUF0_LEN,
2762 PCI_DMA_FROMDEVICE);
2763 pci_unmap_single(sp->pdev,
2764 (dma_addr_t)rxdp3->Buffer1_ptr,
2765 BUF1_LEN,
2766 PCI_DMA_FROMDEVICE);
2767 pci_unmap_single(sp->pdev,
2768 (dma_addr_t)rxdp3->Buffer2_ptr,
2769 dev->mtu + 4,
2770 PCI_DMA_FROMDEVICE);
1ee6dd77 2771 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2772 }
ffb5df6c 2773 swstats->mem_freed += skb->truesize;
da6971d8 2774 dev_kfree_skb(skb);
0425b46a 2775 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2776 }
2777}
2778
1da177e4 2779/**
20346722 2780 * free_rx_buffers - Frees all Rx buffers
1da177e4 2781 * @sp: device private variable.
20346722 2782 * Description:
1da177e4
LT		 2783 * This function will free all Rx buffers allocated by host.
2784 * Return Value:
2785 * NONE.
2786 */
2787
2788static void free_rx_buffers(struct s2io_nic *sp)
2789{
2790 struct net_device *dev = sp->dev;
da6971d8 2791 int i, blk = 0, buf_cnt = 0;
ffb5df6c
JP		 2792 struct config_param *config = &sp->config;
2793 struct mac_info *mac_control = &sp->mac_control;
1da177e4
LT		 2794
2795 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2796 struct ring_info *ring = &mac_control->rings[i];
2797
da6971d8 2798 for (blk = 0; blk < rx_ring_sz[i]; blk++)
d44570e4 2799 free_rxd_blk(sp, i, blk);
1da177e4 2800
13d866a9
JP		 2801 ring->rx_curr_put_info.block_index = 0;
2802 ring->rx_curr_get_info.block_index = 0;
2803 ring->rx_curr_put_info.offset = 0;
2804 ring->rx_curr_get_info.offset = 0;
2805 ring->rx_bufs_left = 0;
9e39f7c5 2806 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
1da177e4
LT		 2807 dev->name, buf_cnt, i);
2808 }
2809}
2810
8d8bb39b 2811static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2812{
8d8bb39b 2813 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2814 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2815 ring->dev->name);
f61e0a35
SH		 2816 }
2817 return 0;
2818}
2819
1da177e4
LT		 2820/**
2821 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2822 * @napi : pointer to the napi structure.
20346722 2823 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2824 * during one pass through the 'Poll" function.
2825 * Description:
2826 * Comes into picture only if NAPI support has been incorporated. It does
2827 * the same thing that rx_intr_handler does, but not in a interrupt context
2828 * also It will process only a given number of packets.
2829 * Return value:
2830 * 0 on success and 1 if there are No Rx packets to be processed.
2831 */
2832
f61e0a35 2833static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2834{
f61e0a35
SH		 2835 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2836 struct net_device *dev = ring->dev;
f61e0a35 2837 int pkts_processed = 0;
1a79d1c3
AV		 2838 u8 __iomem *addr = NULL;
2839 u8 val8 = 0;
4cf1653a 2840 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2841 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2842 int budget_org = budget;
1da177e4 2843
f61e0a35
SH		 2844 if (unlikely(!is_s2io_card_up(nic)))
2845 return 0;
1da177e4 2846
f61e0a35 2847 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2848 s2io_chk_rx_buffers(nic, ring);
1da177e4 2849
f61e0a35 2850 if (pkts_processed < budget_org) {
288379f0 2851 napi_complete(napi);
f61e0a35 2852 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2853 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2854 addr += 7 - ring->ring_no;
2855 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2856 writeb(val8, addr);
2857 val8 = readb(addr);
1da177e4 2858 }
f61e0a35
SH		 2859 return pkts_processed;
2860}
d44570e4 2861
f61e0a35
SH		 2862static int s2io_poll_inta(struct napi_struct *napi, int budget)
2863{
2864 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2865 int pkts_processed = 0;
2866 int ring_pkts_processed, i;
2867 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2868 int budget_org = budget;
ffb5df6c
JP		 2869 struct config_param *config = &nic->config;
2870 struct mac_info *mac_control = &nic->mac_control;
1da177e4 2871
f61e0a35
SH		 2872 if (unlikely(!is_s2io_card_up(nic)))
2873 return 0;
1da177e4 2874
1da177e4 2875 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2876 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2877 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2878 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2879 pkts_processed += ring_pkts_processed;
2880 budget -= ring_pkts_processed;
2881 if (budget <= 0)
1da177e4 2882 break;
1da177e4 2883 }
f61e0a35 2884 if (pkts_processed < budget_org) {
288379f0 2885 napi_complete(napi);
f61e0a35
SH		 2886 /* Re enable the Rx interrupts for the ring */
2887 writeq(0, &bar0->rx_traffic_mask);
2888 readl(&bar0->rx_traffic_mask);
2889 }
2890 return pkts_processed;
1da177e4 2891}
20346722 2892
b41477f3 2893#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2894/**
b41477f3 2895 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2896 * @dev : pointer to the device structure.
2897 * Description:
b41477f3
AR		 2898 * This function will be called by upper layer to check for events on the
2899 * interface in situations where interrupts are disabled. It is used for
2900 * specific in-kernel networking tasks, such as remote consoles and kernel
2901 * debugging over the network (example netdump in RedHat).
612eff0e 2902 */
612eff0e
BH		 2903static void s2io_netpoll(struct net_device *dev)
2904{
4cf1653a 2905 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2906 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2907 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e 2908 int i;
ffb5df6c
JP		 2909 struct config_param *config = &nic->config;
2910 struct mac_info *mac_control = &nic->mac_control;
612eff0e 2911
d796fdb7
LV		 2912 if (pci_channel_offline(nic->pdev))
2913 return;
2914
612eff0e
BH		 2915 disable_irq(dev->irq);
2916
612eff0e 2917 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2918 writeq(val64, &bar0->tx_traffic_int);
2919
6aa20a22 2920 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2921 * run out of skbs and will fail and eventually netpoll application such
2922 * as netdump will fail.
2923 */
2924 for (i = 0; i < config->tx_fifo_num; i++)
2925 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2926
b41477f3 2927 /* check for received packet and indicate up to network */
13d866a9
JP		 2928 for (i = 0; i < config->rx_ring_num; i++) {
2929 struct ring_info *ring = &mac_control->rings[i];
2930
2931 rx_intr_handler(ring, 0);
2932 }
612eff0e
BH		 2933
2934 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2935 struct ring_info *ring = &mac_control->rings[i];
2936
2937 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2938 DBG_PRINT(INFO_DBG,
2939 "%s: Out of memory in Rx Netpoll!!\n",
2940 dev->name);
612eff0e
BH		 2941 break;
2942 }
2943 }
612eff0e 2944 enable_irq(dev->irq);
612eff0e
BH		 2945}
2946#endif
2947
20346722 2948/**
1da177e4 2949 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2950 * @ring_info: per ring structure.
2951 * @budget: budget for napi processing.
20346722
K		 2952 * Description:
2953 * If the interrupt is because of a received frame or if the
1da177e4 2954 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2955 * called. It picks out the RxD at which place the last Rx processing had
2956 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2957 * the offset.
2958 * Return Value:
f61e0a35 2959 * No. of napi packets processed.
1da177e4 2960 */
f61e0a35 2961static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2962{
c9fcbf47 2963 int get_block, put_block;
1ee6dd77
RB		 2964 struct rx_curr_get_info get_info, put_info;
2965 struct RxD_t *rxdp;
1da177e4 2966 struct sk_buff *skb;
f61e0a35 2967 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 2968 int i;
d44570e4
JP		 2969 struct RxD1 *rxdp1;
2970 struct RxD3 *rxdp3;
7d3d0439 2971
20346722
K		 2972 get_info = ring_data->rx_curr_get_info;
2973 get_block = get_info.block_index;
1ee6dd77 2974 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2975 put_block = put_info.block_index;
da6971d8 2976 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2977
da6971d8 2978 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2979 /*
2980 * If your are next to put index then it's
2981 * FIFO full condition
2982 */
da6971d8
AR		 2983 if ((get_block == put_block) &&
2984 (get_info.offset + 1) == put_info.offset) {
0425b46a 2985 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
d44570e4 2986 ring_data->dev->name);
da6971d8
AR		 2987 break;
2988 }
d44570e4 2989 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
20346722 2990 if (skb == NULL) {
9e39f7c5 2991 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
0425b46a 2992 ring_data->dev->name);
f61e0a35 2993 return 0;
1da177e4 2994 }
0425b46a 2995 if (ring_data->rxd_mode == RXD_MODE_1) {
d44570e4 2996 rxdp1 = (struct RxD1 *)rxdp;
0425b46a 2997 pci_unmap_single(ring_data->pdev, (dma_addr_t)
d44570e4
JP		 2998 rxdp1->Buffer0_ptr,
2999 ring_data->mtu +
3000 HEADER_ETHERNET_II_802_3_SIZE +
3001 HEADER_802_2_SIZE +
3002 HEADER_SNAP_SIZE,
3003 PCI_DMA_FROMDEVICE);
0425b46a 3004 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
d44570e4
JP		 3005 rxdp3 = (struct RxD3 *)rxdp;
3006 pci_dma_sync_single_for_cpu(ring_data->pdev,
3007 (dma_addr_t)rxdp3->Buffer0_ptr,
3008 BUF0_LEN,
3009 PCI_DMA_FROMDEVICE);
3010 pci_unmap_single(ring_data->pdev,
3011 (dma_addr_t)rxdp3->Buffer2_ptr,
3012 ring_data->mtu + 4,
3013 PCI_DMA_FROMDEVICE);
da6971d8 3014 }
863c11a9 3015 prefetch(skb->data);
20346722
K		 3016 rx_osm_handler(ring_data, rxdp);
3017 get_info.offset++;
da6971d8
AR		 3018 ring_data->rx_curr_get_info.offset = get_info.offset;
3019 rxdp = ring_data->rx_blocks[get_block].
d44570e4 3020 rxds[get_info.offset].virt_addr;
0425b46a 3021 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3022 get_info.offset = 0;
da6971d8 3023 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3024 get_block++;
da6971d8
AR		 3025 if (get_block == ring_data->block_count)
3026 get_block = 0;
3027 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 3028 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3029 }
1da177e4 3030
f61e0a35
SH		 3031 if (ring_data->nic->config.napi) {
3032 budget--;
3033 napi_pkts++;
3034 if (!budget)
0425b46a
SH		 3035 break;
3036 }
20346722 3037 pkt_cnt++;
1da177e4
LT		 3038 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3039 break;
3040 }
0425b46a 3041 if (ring_data->lro) {
7d3d0439 3042 /* Clear all LRO sessions before exiting */
d44570e4 3043 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 3044 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3045 if (lro->in_use) {
0425b46a 3046 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3047 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3048 clear_lro_session(lro);
3049 }
3050 }
3051 }
d44570e4 3052 return napi_pkts;
1da177e4 3053}
20346722
K		 3054
3055/**
1da177e4
LT		 3056 * tx_intr_handler - Transmit interrupt handler
3057 * @nic : device private variable
20346722
K		 3058 * Description:
3059 * If an interrupt was raised to indicate DMA complete of the
3060 * Tx packet, this function is called. It identifies the last TxD
3061 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3062 * DMA'ed into the NICs internal memory.
3063 * Return Value:
3064 * NONE
3065 */
3066
1ee6dd77 3067static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3068{
1ee6dd77 3069 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3070 struct tx_curr_get_info get_info, put_info;
3a3d5756 3071 struct sk_buff *skb = NULL;
1ee6dd77 3072 struct TxD *txdlp;
3a3d5756 3073 int pkt_cnt = 0;
2fda096d 3074 unsigned long flags = 0;
f9046eb3 3075 u8 err_mask;
ffb5df6c
JP		 3076 struct stat_block *stats = nic->mac_control.stats_info;
3077 struct swStat *swstats = &stats->sw_stat;
1da177e4 3078
2fda096d 3079 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
d44570e4 3080 return;
2fda096d 3081
20346722 3082 get_info = fifo_data->tx_curr_get_info;
1ee6dd77 3083 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
d44570e4
JP		 3084 txdlp = (struct TxD *)
3085 fifo_data->list_info[get_info.offset].list_virt_addr;
20346722
K		 3086 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3087 (get_info.offset != put_info.offset) &&
3088 (txdlp->Host_Control)) {
3089 /* Check for TxD errors */
3090 if (txdlp->Control_1 & TXD_T_CODE) {
3091 unsigned long long err;
3092 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0 3093 if (err & 0x1) {
ffb5df6c 3094 swstats->parity_err_cnt++;
bd1034f0 3095 }
491976b2
SH		 3096
3097 /* update t_code statistics */
f9046eb3 3098 err_mask = err >> 48;
d44570e4
JP		 3099 switch (err_mask) {
3100 case 2:
ffb5df6c 3101 swstats->tx_buf_abort_cnt++;
491976b2
SH		 3102 break;
3103
d44570e4 3104 case 3:
ffb5df6c 3105 swstats->tx_desc_abort_cnt++;
491976b2
SH		 3106 break;
3107
d44570e4 3108 case 7:
ffb5df6c 3109 swstats->tx_parity_err_cnt++;
491976b2
SH		 3110 break;
3111
d44570e4 3112 case 10:
ffb5df6c 3113 swstats->tx_link_loss_cnt++;
491976b2
SH		 3114 break;
3115
d44570e4 3116 case 15:
ffb5df6c 3117 swstats->tx_list_proc_err_cnt++;
491976b2 3118 break;
d44570e4 3119 }
20346722 3120 }
1da177e4 3121
fed5eccd 3122 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3123 if (skb == NULL) {
2fda096d 3124 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
9e39f7c5
JP		 3125 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3126 __func__);
20346722
K		 3127 return;
3128 }
3a3d5756 3129 pkt_cnt++;
20346722 3130
20346722 3131 /* Updating the statistics block */
dc56e634 3132 nic->dev->stats.tx_bytes += skb->len;
ffb5df6c 3133 swstats->mem_freed += skb->truesize;
20346722
K		 3134 dev_kfree_skb_irq(skb);
3135
3136 get_info.offset++;
863c11a9
AR		 3137 if (get_info.offset == get_info.fifo_len + 1)
3138 get_info.offset = 0;
d44570e4
JP		 3139 txdlp = (struct TxD *)
3140 fifo_data->list_info[get_info.offset].list_virt_addr;
3141 fifo_data->tx_curr_get_info.offset = get_info.offset;
1da177e4
LT		 3142 }
3143
3a3d5756 3144 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3145
3146 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3147}
3148
bd1034f0
AR		 3149/**
3150 * s2io_mdio_write - Function to write in to MDIO registers
3151 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3152 * @addr : address value
3153 * @value : data value
3154 * @dev : pointer to net_device structure
3155 * Description:
3156 * This function is used to write values to the MDIO registers
3157 * NONE
3158 */
d44570e4
JP		 3159static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3160 struct net_device *dev)
bd1034f0 3161{
d44570e4 3162 u64 val64;
4cf1653a 3163 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3164 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0 3165
d44570e4
JP		 3166 /* address transaction */
3167 val64 = MDIO_MMD_INDX_ADDR(addr) |
3168 MDIO_MMD_DEV_ADDR(mmd_type) |
3169 MDIO_MMS_PRT_ADDR(0x0);
bd1034f0
AR		 3170 writeq(val64, &bar0->mdio_control);
3171 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3172 writeq(val64, &bar0->mdio_control);
3173 udelay(100);
3174
d44570e4
JP		 3175 /* Data transaction */
3176 val64 = MDIO_MMD_INDX_ADDR(addr) |
3177 MDIO_MMD_DEV_ADDR(mmd_type) |
3178 MDIO_MMS_PRT_ADDR(0x0) |
3179 MDIO_MDIO_DATA(value) |
3180 MDIO_OP(MDIO_OP_WRITE_TRANS);
bd1034f0
AR		 3181 writeq(val64, &bar0->mdio_control);
3182 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3183 writeq(val64, &bar0->mdio_control);
3184 udelay(100);
3185
d44570e4
JP		 3186 val64 = MDIO_MMD_INDX_ADDR(addr) |
3187 MDIO_MMD_DEV_ADDR(mmd_type) |
3188 MDIO_MMS_PRT_ADDR(0x0) |
3189 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3190 writeq(val64, &bar0->mdio_control);
3191 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3192 writeq(val64, &bar0->mdio_control);
3193 udelay(100);
bd1034f0
AR		 3194}
3195
3196/**
3197 * s2io_mdio_read - Function to write in to MDIO registers
3198 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3199 * @addr : address value
3200 * @dev : pointer to net_device structure
3201 * Description:
3202 * This function is used to read values to the MDIO registers
3203 * NONE
3204 */
3205static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3206{
3207 u64 val64 = 0x0;
3208 u64 rval64 = 0x0;
4cf1653a 3209 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3210 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3211
3212 /* address transaction */
d44570e4
JP		 3213 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3214 | MDIO_MMD_DEV_ADDR(mmd_type)
3215 | MDIO_MMS_PRT_ADDR(0x0));
bd1034f0
AR		 3216 writeq(val64, &bar0->mdio_control);
3217 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3218 writeq(val64, &bar0->mdio_control);
3219 udelay(100);
3220
3221 /* Data transaction */
d44570e4
JP		 3222 val64 = MDIO_MMD_INDX_ADDR(addr) |
3223 MDIO_MMD_DEV_ADDR(mmd_type) |
3224 MDIO_MMS_PRT_ADDR(0x0) |
3225 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3226 writeq(val64, &bar0->mdio_control);
3227 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3228 writeq(val64, &bar0->mdio_control);
3229 udelay(100);
3230
3231 /* Read the value from regs */
3232 rval64 = readq(&bar0->mdio_control);
3233 rval64 = rval64 & 0xFFFF0000;
3234 rval64 = rval64 >> 16;
3235 return rval64;
3236}
d44570e4 3237
bd1034f0
AR		 3238/**
3239 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
fbfecd37 3240 * @counter : counter value to be updated
bd1034f0
AR		 3241 * @flag : flag to indicate the status
3242 * @type : counter type
3243 * Description:
3244 * This function is to check the status of the xpak counters value
3245 * NONE
3246 */
3247
d44570e4
JP		 3248static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3249 u16 flag, u16 type)
bd1034f0
AR		 3250{
3251 u64 mask = 0x3;
3252 u64 val64;
3253 int i;
d44570e4 3254 for (i = 0; i < index; i++)
bd1034f0
AR		 3255 mask = mask << 0x2;
3256
d44570e4 3257 if (flag > 0) {
bd1034f0
AR		 3258 *counter = *counter + 1;
3259 val64 = *regs_stat & mask;
3260 val64 = val64 >> (index * 0x2);
3261 val64 = val64 + 1;
d44570e4
JP		 3262 if (val64 == 3) {
3263 switch (type) {
bd1034f0 3264 case 1:
9e39f7c5
JP		 3265 DBG_PRINT(ERR_DBG,
3266 "Take Xframe NIC out of service.\n");
3267 DBG_PRINT(ERR_DBG,
3268"Excessive temperatures may result in premature transceiver failure.\n");
d44570e4 3269 break;
bd1034f0 3270 case 2:
9e39f7c5
JP		 3271 DBG_PRINT(ERR_DBG,
3272 "Take Xframe NIC out of service.\n");
3273 DBG_PRINT(ERR_DBG,
3274"Excessive bias currents may indicate imminent laser diode failure.\n");
d44570e4 3275 break;
bd1034f0 3276 case 3:
9e39f7c5
JP		 3277 DBG_PRINT(ERR_DBG,
3278 "Take Xframe NIC out of service.\n");
3279 DBG_PRINT(ERR_DBG,
3280"Excessive laser output power may saturate far-end receiver.\n");
d44570e4 3281 break;
bd1034f0 3282 default:
d44570e4
JP		 3283 DBG_PRINT(ERR_DBG,
3284 "Incorrect XPAK Alarm type\n");
bd1034f0
AR		 3285 }
3286 val64 = 0x0;
3287 }
3288 val64 = val64 << (index * 0x2);
3289 *regs_stat = (*regs_stat & (~mask)) | (val64);
3290
3291 } else {
3292 *regs_stat = *regs_stat & (~mask);
3293 }
3294}
3295
3296/**
3297 * s2io_updt_xpak_counter - Function to update the xpak counters
3298 * @dev : pointer to net_device struct
3299 * Description:
3300 * This function is to upate the status of the xpak counters value
3301 * NONE
3302 */
3303static void s2io_updt_xpak_counter(struct net_device *dev)
3304{
3305 u16 flag = 0x0;
3306 u16 type = 0x0;
3307 u16 val16 = 0x0;
3308 u64 val64 = 0x0;
3309 u64 addr = 0x0;
3310
4cf1653a 3311 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 3312 struct stat_block *stats = sp->mac_control.stats_info;
3313 struct xpakStat *xstats = &stats->xpak_stat;
bd1034f0
AR		 3314
3315 /* Check the communication with the MDIO slave */
40239396 3316 addr = MDIO_CTRL1;
bd1034f0 3317 val64 = 0x0;
40239396 3318 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
d44570e4 3319 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
9e39f7c5
JP		 3320 DBG_PRINT(ERR_DBG,
3321 "ERR: MDIO slave access failed - Returned %llx\n",
3322 (unsigned long long)val64);
bd1034f0
AR		 3323 return;
3324 }
3325
40239396 3326 /* Check for the expected value of control reg 1 */
d44570e4 3327 if (val64 != MDIO_CTRL1_SPEED10G) {
9e39f7c5
JP		 3328 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3329 "Returned: %llx- Expected: 0x%x\n",
40239396 3330 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3331 return;
3332 }
3333
3334 /* Loading the DOM register to MDIO register */
3335 addr = 0xA100;
40239396
BH		 3336 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3337 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3338
3339 /* Reading the Alarm flags */
3340 addr = 0xA070;
3341 val64 = 0x0;
40239396 3342 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3343
3344 flag = CHECKBIT(val64, 0x7);
3345 type = 1;
ffb5df6c
JP		 3346 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3347 &xstats->xpak_regs_stat,
d44570e4 3348 0x0, flag, type);
bd1034f0 3349
d44570e4 3350 if (CHECKBIT(val64, 0x6))
ffb5df6c 3351 xstats->alarm_transceiver_temp_low++;
bd1034f0
AR		 3352
3353 flag = CHECKBIT(val64, 0x3);
3354 type = 2;
ffb5df6c
JP		 3355 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3356 &xstats->xpak_regs_stat,
d44570e4 3357 0x2, flag, type);
bd1034f0 3358
d44570e4 3359 if (CHECKBIT(val64, 0x2))
ffb5df6c 3360 xstats->alarm_laser_bias_current_low++;
bd1034f0
AR		 3361
3362 flag = CHECKBIT(val64, 0x1);
3363 type = 3;
ffb5df6c
JP		 3364 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3365 &xstats->xpak_regs_stat,
d44570e4 3366 0x4, flag, type);
bd1034f0 3367
d44570e4 3368 if (CHECKBIT(val64, 0x0))
ffb5df6c 3369 xstats->alarm_laser_output_power_low++;
bd1034f0
AR		 3370
3371 /* Reading the Warning flags */
3372 addr = 0xA074;
3373 val64 = 0x0;
40239396 3374 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0 3375
d44570e4 3376 if (CHECKBIT(val64, 0x7))
ffb5df6c 3377 xstats->warn_transceiver_temp_high++;
bd1034f0 3378
d44570e4 3379 if (CHECKBIT(val64, 0x6))
ffb5df6c 3380 xstats->warn_transceiver_temp_low++;
bd1034f0 3381
d44570e4 3382 if (CHECKBIT(val64, 0x3))
ffb5df6c 3383 xstats->warn_laser_bias_current_high++;
bd1034f0 3384
d44570e4 3385 if (CHECKBIT(val64, 0x2))
ffb5df6c 3386 xstats->warn_laser_bias_current_low++;
bd1034f0 3387
d44570e4 3388 if (CHECKBIT(val64, 0x1))
ffb5df6c 3389 xstats->warn_laser_output_power_high++;
bd1034f0 3390
d44570e4 3391 if (CHECKBIT(val64, 0x0))
ffb5df6c 3392 xstats->warn_laser_output_power_low++;
bd1034f0
AR		 3393}
3394
20346722 3395/**
1da177e4 3396 * wait_for_cmd_complete - waits for a command to complete.
20346722 3397 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3398 * s2io_nic structure.
20346722
K		 3399 * Description: Function that waits for a command to Write into RMAC
3400 * ADDR DATA registers to be completed and returns either success or
3401 * error depending on whether the command was complete or not.
1da177e4
LT		 3402 * Return value:
3403 * SUCCESS on success and FAILURE on failure.
3404 */
3405
9fc93a41 3406static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
d44570e4 3407 int bit_state)
1da177e4 3408{
9fc93a41 3409 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3410 u64 val64;
3411
9fc93a41
SS		 3412 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3413 return FAILURE;
3414
3415 do {
c92ca04b 3416 val64 = readq(addr);
9fc93a41
SS		 3417 if (bit_state == S2IO_BIT_RESET) {
3418 if (!(val64 & busy_bit)) {
3419 ret = SUCCESS;
3420 break;
3421 }
3422 } else {
2d146eb1 3423 if (val64 & busy_bit) {
9fc93a41
SS		 3424 ret = SUCCESS;
3425 break;
3426 }
1da177e4 3427 }
c92ca04b 3428
d44570e4 3429 if (in_interrupt())
9fc93a41 3430 mdelay(delay);
c92ca04b 3431 else
9fc93a41 3432 msleep(delay);
c92ca04b 3433
9fc93a41
SS		 3434 if (++cnt >= 10)
3435 delay = 50;
3436 } while (cnt < 20);
1da177e4
LT		 3437 return ret;
3438}
19a60522
SS		 3439/*
3440 * check_pci_device_id - Checks if the device id is supported
3441 * @id : device id
3442 * Description: Function to check if the pci device id is supported by driver.
3443 * Return value: Actual device id if supported else PCI_ANY_ID
3444 */
3445static u16 check_pci_device_id(u16 id)
3446{
3447 switch (id) {
3448 case PCI_DEVICE_ID_HERC_WIN:
3449 case PCI_DEVICE_ID_HERC_UNI:
3450 return XFRAME_II_DEVICE;
3451 case PCI_DEVICE_ID_S2IO_UNI:
3452 case PCI_DEVICE_ID_S2IO_WIN:
3453 return XFRAME_I_DEVICE;
3454 default:
3455 return PCI_ANY_ID;
3456 }
3457}
1da177e4 3458
20346722
K		 3459/**
3460 * s2io_reset - Resets the card.
1da177e4
LT		 3461 * @sp : private member of the device structure.
3462 * Description: Function to Reset the card. This function then also
20346722 3463 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3464 * the card reset also resets the configuration space.
3465 * Return value:
3466 * void.
3467 */
3468
d44570e4 3469static void s2io_reset(struct s2io_nic *sp)
1da177e4 3470{
1ee6dd77 3471 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3472 u64 val64;
5e25b9dd 3473 u16 subid, pci_cmd;
19a60522
SS		 3474 int i;
3475 u16 val16;
491976b2
SH		 3476 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3477 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
ffb5df6c
JP		 3478 struct stat_block *stats;
3479 struct swStat *swstats;
491976b2 3480
9e39f7c5 3481 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3a22813a 3482 __func__, pci_name(sp->pdev));
1da177e4 3483
0b1f7ebe 3484 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3485 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3486
1da177e4
LT		 3487 val64 = SW_RESET_ALL;
3488 writeq(val64, &bar0->sw_reset);
d44570e4 3489 if (strstr(sp->product_name, "CX4"))
c92ca04b 3490 msleep(750);
19a60522
SS		 3491 msleep(250);
3492 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3493
19a60522
SS		 3494 /* Restore the PCI state saved during initialization. */
3495 pci_restore_state(sp->pdev);
b8a623bf 3496 pci_save_state(sp->pdev);
19a60522
SS		 3497 pci_read_config_word(sp->pdev, 0x2, &val16);
3498 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3499 break;
3500 msleep(200);
3501 }
1da177e4 3502
d44570e4
JP		 3503 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3504 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
19a60522
SS		 3505
3506 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3507
3508 s2io_init_pci(sp);
1da177e4 3509
20346722
K		 3510 /* Set swapper to enable I/O register access */
3511 s2io_set_swapper(sp);
3512
faa4f796
SH		 3513 /* restore mac_addr entries */
3514 do_s2io_restore_unicast_mc(sp);
3515
cc6e7c44
RA		 3516 /* Restore the MSIX table entries from local variables */
3517 restore_xmsi_data(sp);
3518
5e25b9dd 3519 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3520 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3521 /* Clear "detected parity error" bit */
303bcb4b 3522 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3523
303bcb4b
K		 3524 /* Clearing PCIX Ecc status register */
3525 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3526
303bcb4b 3527 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3528 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3529 }
5e25b9dd 3530
20346722 3531 /* Reset device statistics maintained by OS */
d44570e4 3532 memset(&sp->stats, 0, sizeof(struct net_device_stats));
8a4bdbaa 3533
ffb5df6c
JP		 3534 stats = sp->mac_control.stats_info;
3535 swstats = &stats->sw_stat;
3536
491976b2 3537 /* save link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3538 up_cnt = swstats->link_up_cnt;
3539 down_cnt = swstats->link_down_cnt;
3540 up_time = swstats->link_up_time;
3541 down_time = swstats->link_down_time;
3542 reset_cnt = swstats->soft_reset_cnt;
3543 mem_alloc_cnt = swstats->mem_allocated;
3544 mem_free_cnt = swstats->mem_freed;
3545 watchdog_cnt = swstats->watchdog_timer_cnt;
3546
3547 memset(stats, 0, sizeof(struct stat_block));
3548
491976b2 3549 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3550 swstats->link_up_cnt = up_cnt;
3551 swstats->link_down_cnt = down_cnt;
3552 swstats->link_up_time = up_time;
3553 swstats->link_down_time = down_time;
3554 swstats->soft_reset_cnt = reset_cnt;
3555 swstats->mem_allocated = mem_alloc_cnt;
3556 swstats->mem_freed = mem_free_cnt;
3557 swstats->watchdog_timer_cnt = watchdog_cnt;
20346722 3558
1da177e4
LT		 3559 /* SXE-002: Configure link and activity LED to turn it off */
3560 subid = sp->pdev->subsystem_device;
541ae68f
K		 3561 if (((subid & 0xFF) >= 0x07) &&
3562 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3563 val64 = readq(&bar0->gpio_control);
3564 val64 |= 0x0000800000000000ULL;
3565 writeq(val64, &bar0->gpio_control);
3566 val64 = 0x0411040400000000ULL;
509a2671 3567 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3568 }
3569
541ae68f
K		 3570 /*
3571 * Clear spurious ECC interrupts that would have occured on
3572 * XFRAME II cards after reset.
3573 */
3574 if (sp->device_type == XFRAME_II_DEVICE) {
3575 val64 = readq(&bar0->pcc_err_reg);
3576 writeq(val64, &bar0->pcc_err_reg);
3577 }
3578
f957bcf0 3579 sp->device_enabled_once = false;
1da177e4
LT		 3580}
3581
3582/**
20346722
K		 3583 * s2io_set_swapper - to set the swapper controle on the card
3584 * @sp : private member of the device structure,
1da177e4 3585 * pointer to the s2io_nic structure.
20346722 3586 * Description: Function to set the swapper control on the card
1da177e4
LT		 3587 * correctly depending on the 'endianness' of the system.
3588 * Return value:
3589 * SUCCESS on success and FAILURE on failure.
3590 */
3591
d44570e4 3592static int s2io_set_swapper(struct s2io_nic *sp)
1da177e4
LT		 3593{
3594 struct net_device *dev = sp->dev;
1ee6dd77 3595 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3596 u64 val64, valt, valr;
3597
20346722 3598 /*
1da177e4
LT		 3599 * Set proper endian settings and verify the same by reading
3600 * the PIF Feed-back register.
3601 */
3602
3603 val64 = readq(&bar0->pif_rd_swapper_fb);
3604 if (val64 != 0x0123456789ABCDEFULL) {
3605 int i = 0;
3606 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3607 0x8100008181000081ULL, /* FE=1, SE=0 */
3608 0x4200004242000042ULL, /* FE=0, SE=1 */
3609 0}; /* FE=0, SE=0 */
3610
d44570e4 3611 while (i < 4) {
1da177e4
LT		 3612 writeq(value[i], &bar0->swapper_ctrl);
3613 val64 = readq(&bar0->pif_rd_swapper_fb);
3614 if (val64 == 0x0123456789ABCDEFULL)
3615 break;
3616 i++;
3617 }
3618 if (i == 4) {
9e39f7c5
JP		 3619 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3620 "feedback read %llx\n",
3621 dev->name, (unsigned long long)val64);
1da177e4
LT		 3622 return FAILURE;
3623 }
3624 valr = value[i];
3625 } else {
3626 valr = readq(&bar0->swapper_ctrl);
3627 }
3628
3629 valt = 0x0123456789ABCDEFULL;
3630 writeq(valt, &bar0->xmsi_address);
3631 val64 = readq(&bar0->xmsi_address);
3632
d44570e4 3633 if (val64 != valt) {
1da177e4
LT		 3634 int i = 0;
3635 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3636 0x0081810000818100ULL, /* FE=1, SE=0 */
3637 0x0042420000424200ULL, /* FE=0, SE=1 */
3638 0}; /* FE=0, SE=0 */
3639
d44570e4 3640 while (i < 4) {
1da177e4
LT		 3641 writeq((value[i] | valr), &bar0->swapper_ctrl);
3642 writeq(valt, &bar0->xmsi_address);
3643 val64 = readq(&bar0->xmsi_address);
d44570e4 3644 if (val64 == valt)
1da177e4
LT		 3645 break;
3646 i++;
3647 }
d44570e4 3648 if (i == 4) {
20346722 3649 unsigned long long x = val64;
9e39f7c5
JP		 3650 DBG_PRINT(ERR_DBG,
3651 "Write failed, Xmsi_addr reads:0x%llx\n", x);
1da177e4
LT		 3652 return FAILURE;
3653 }
3654 }
3655 val64 = readq(&bar0->swapper_ctrl);
3656 val64 &= 0xFFFF000000000000ULL;
3657
d44570e4 3658#ifdef __BIG_ENDIAN
20346722
K		 3659 /*
3660 * The device by default set to a big endian format, so a
1da177e4
LT		 3661 * big endian driver need not set anything.
3662 */
3663 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3664 SWAPPER_CTRL_TXP_SE |
3665 SWAPPER_CTRL_TXD_R_FE |
3666 SWAPPER_CTRL_TXD_W_FE |
3667 SWAPPER_CTRL_TXF_R_FE |
3668 SWAPPER_CTRL_RXD_R_FE |
3669 SWAPPER_CTRL_RXD_W_FE |
3670 SWAPPER_CTRL_RXF_W_FE |
3671 SWAPPER_CTRL_XMSI_FE |
3672 SWAPPER_CTRL_STATS_FE |
3673 SWAPPER_CTRL_STATS_SE);
eaae7f72 3674 if (sp->config.intr_type == INTA)
cc6e7c44 3675 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3676 writeq(val64, &bar0->swapper_ctrl);
3677#else
20346722 3678 /*
1da177e4 3679 * Initially we enable all bits to make it accessible by the
20346722 3680 * driver, then we selectively enable only those bits that
1da177e4
LT		 3681 * we want to set.
3682 */
3683 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3684 SWAPPER_CTRL_TXP_SE |
3685 SWAPPER_CTRL_TXD_R_FE |
3686 SWAPPER_CTRL_TXD_R_SE |
3687 SWAPPER_CTRL_TXD_W_FE |
3688 SWAPPER_CTRL_TXD_W_SE |
3689 SWAPPER_CTRL_TXF_R_FE |
3690 SWAPPER_CTRL_RXD_R_FE |
3691 SWAPPER_CTRL_RXD_R_SE |
3692 SWAPPER_CTRL_RXD_W_FE |
3693 SWAPPER_CTRL_RXD_W_SE |
3694 SWAPPER_CTRL_RXF_W_FE |
3695 SWAPPER_CTRL_XMSI_FE |
3696 SWAPPER_CTRL_STATS_FE |
3697 SWAPPER_CTRL_STATS_SE);
eaae7f72 3698 if (sp->config.intr_type == INTA)
cc6e7c44 3699 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3700 writeq(val64, &bar0->swapper_ctrl);
3701#endif
3702 val64 = readq(&bar0->swapper_ctrl);
3703
20346722
K		 3704 /*
3705 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3706 * feedback register.
3707 */
3708 val64 = readq(&bar0->pif_rd_swapper_fb);
3709 if (val64 != 0x0123456789ABCDEFULL) {
3710 /* Endian settings are incorrect, calls for another dekko. */
9e39f7c5
JP		 3711 DBG_PRINT(ERR_DBG,
3712 "%s: Endian settings are wrong, feedback read %llx\n",
3713 dev->name, (unsigned long long)val64);
1da177e4
LT		 3714 return FAILURE;
3715 }
3716
3717 return SUCCESS;
3718}
3719
1ee6dd77 3720static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3721{
1ee6dd77 3722 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3723 u64 val64;
3724 int ret = 0, cnt = 0;
3725
3726 do {
3727 val64 = readq(&bar0->xmsi_access);
b7b5a128 3728 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3729 break;
3730 mdelay(1);
3731 cnt++;
d44570e4 3732 } while (cnt < 5);
cc6e7c44
RA		 3733 if (cnt == 5) {
3734 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3735 ret = 1;
3736 }
3737
3738 return ret;
3739}
3740
1ee6dd77 3741static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3742{
1ee6dd77 3743 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3744 u64 val64;
f61e0a35
SH		 3745 int i, msix_index;
3746
f61e0a35
SH		 3747 if (nic->device_type == XFRAME_I_DEVICE)
3748 return;
cc6e7c44 3749
d44570e4
JP		 3750 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3751 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
cc6e7c44
RA		 3752 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3753 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3754 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3755 writeq(val64, &bar0->xmsi_access);
f61e0a35 3756 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3757 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3758 __func__, msix_index);
cc6e7c44
RA		 3759 continue;
3760 }
3761 }
3762}
3763
1ee6dd77 3764static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3765{
1ee6dd77 3766 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3767 u64 val64, addr, data;
f61e0a35
SH		 3768 int i, msix_index;
3769
3770 if (nic->device_type == XFRAME_I_DEVICE)
3771 return;
cc6e7c44
RA		 3772
3773 /* Store and display */
d44570e4
JP		 3774 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3775 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
f61e0a35 3776 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3777 writeq(val64, &bar0->xmsi_access);
f61e0a35 3778 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3779 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3780 __func__, msix_index);
cc6e7c44
RA		 3781 continue;
3782 }
3783 addr = readq(&bar0->xmsi_address);
3784 data = readq(&bar0->xmsi_data);
3785 if (addr && data) {
3786 nic->msix_info[i].addr = addr;
3787 nic->msix_info[i].data = data;
3788 }
3789 }
3790}
3791
1ee6dd77 3792static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3793{
1ee6dd77 3794 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3795 u64 rx_mat;
cc6e7c44
RA		 3796 u16 msi_control; /* Temp variable */
3797 int ret, i, j, msix_indx = 1;
4f870320 3798 int size;
ffb5df6c
JP		 3799 struct stat_block *stats = nic->mac_control.stats_info;
3800 struct swStat *swstats = &stats->sw_stat;
cc6e7c44 3801
4f870320 3802 size = nic->num_entries * sizeof(struct msix_entry);
44364a03 3803 nic->entries = kzalloc(size, GFP_KERNEL);
bd684e43 3804 if (!nic->entries) {
d44570e4
JP		 3805 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3806 __func__);
ffb5df6c 3807 swstats->mem_alloc_fail_cnt++;
cc6e7c44
RA		 3808 return -ENOMEM;
3809 }
ffb5df6c 3810 swstats->mem_allocated += size;
f61e0a35 3811
4f870320 3812 size = nic->num_entries * sizeof(struct s2io_msix_entry);
44364a03 3813 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
bd684e43 3814 if (!nic->s2io_entries) {
8a4bdbaa 3815 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
d44570e4 3816 __func__);
ffb5df6c 3817 swstats->mem_alloc_fail_cnt++;
cc6e7c44 3818 kfree(nic->entries);
ffb5df6c 3819 swstats->mem_freed
f61e0a35 3820 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3821 return -ENOMEM;
3822 }
ffb5df6c 3823 swstats->mem_allocated += size;
cc6e7c44 3824
ac731ab6
SH		 3825 nic->entries[0].entry = 0;
3826 nic->s2io_entries[0].entry = 0;
3827 nic->s2io_entries[0].in_use = MSIX_FLG;
3828 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3829 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3830
f61e0a35
SH		 3831 for (i = 1; i < nic->num_entries; i++) {
3832 nic->entries[i].entry = ((i - 1) * 8) + 1;
3833 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3834 nic->s2io_entries[i].arg = NULL;
3835 nic->s2io_entries[i].in_use = 0;
3836 }
3837
8a4bdbaa 3838 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3839 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3840 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3841 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3842 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3843 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3844 msix_indx += 8;
cc6e7c44 3845 }
8a4bdbaa 3846 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3847 readq(&bar0->rx_mat);
cc6e7c44 3848
f61e0a35 3849 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3850 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3851 if (ret) {
9e39f7c5 3852 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
cc6e7c44 3853 kfree(nic->entries);
ffb5df6c
JP		 3854 swstats->mem_freed += nic->num_entries *
3855 sizeof(struct msix_entry);
cc6e7c44 3856 kfree(nic->s2io_entries);
ffb5df6c
JP		 3857 swstats->mem_freed += nic->num_entries *
3858 sizeof(struct s2io_msix_entry);
cc6e7c44
RA		 3859 nic->entries = NULL;
3860 nic->s2io_entries = NULL;
3861 return -ENOMEM;
3862 }
3863
3864 /*
3865 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3866 * in the herc NIC. (Temp change, needs to be removed later)
3867 */
3868 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3869 msi_control |= 0x1; /* Enable MSI */
3870 pci_write_config_word(nic->pdev, 0x42, msi_control);
3871
3872 return 0;
3873}
3874
8abc4d5b 3875/* Handle software interrupt used during MSI(X) test */
33390a70 3876static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3877{
3878 struct s2io_nic *sp = dev_id;
3879
3880 sp->msi_detected = 1;
3881 wake_up(&sp->msi_wait);
3882
3883 return IRQ_HANDLED;
3884}
3885
3886/* Test interrupt path by forcing a a software IRQ */
33390a70 3887static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3888{
3889 struct pci_dev *pdev = sp->pdev;
3890 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3891 int err;
3892 u64 val64, saved64;
3893
3894 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
d44570e4 3895 sp->name, sp);
8abc4d5b
SS		 3896 if (err) {
3897 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
d44570e4 3898 sp->dev->name, pci_name(pdev), pdev->irq);
8abc4d5b
SS		 3899 return err;
3900 }
3901
d44570e4 3902 init_waitqueue_head(&sp->msi_wait);
8abc4d5b
SS		 3903 sp->msi_detected = 0;
3904
3905 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3906 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3907 val64 |= SCHED_INT_CTRL_TIMER_EN;
3908 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3909 writeq(val64, &bar0->scheduled_int_ctrl);
3910
3911 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3912
3913 if (!sp->msi_detected) {
3914 /* MSI(X) test failed, go back to INTx mode */
2450022a 3915 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
9e39f7c5
JP		 3916 "using MSI(X) during test\n",
3917 sp->dev->name, pci_name(pdev));
8abc4d5b
SS		 3918
3919 err = -EOPNOTSUPP;
3920 }
3921
3922 free_irq(sp->entries[1].vector, sp);
3923
3924 writeq(saved64, &bar0->scheduled_int_ctrl);
3925
3926 return err;
3927}
18b2b7bd
SH		 3928
3929static void remove_msix_isr(struct s2io_nic *sp)
3930{
3931 int i;
3932 u16 msi_control;
3933
f61e0a35 3934 for (i = 0; i < sp->num_entries; i++) {
d44570e4 3935 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
18b2b7bd
SH		 3936 int vector = sp->entries[i].vector;
3937 void *arg = sp->s2io_entries[i].arg;
3938 free_irq(vector, arg);
3939 }
3940 }
3941
3942 kfree(sp->entries);
3943 kfree(sp->s2io_entries);
3944 sp->entries = NULL;
3945 sp->s2io_entries = NULL;
3946
3947 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3948 msi_control &= 0xFFFE; /* Disable MSI */
3949 pci_write_config_word(sp->pdev, 0x42, msi_control);
3950
3951 pci_disable_msix(sp->pdev);
3952}
3953
3954static void remove_inta_isr(struct s2io_nic *sp)
3955{
3956 struct net_device *dev = sp->dev;
3957
3958 free_irq(sp->pdev->irq, dev);
3959}
3960
1da177e4
LT		 3961/* ********************************************************* *
3962 * Functions defined below concern the OS part of the driver *
3963 * ********************************************************* */
3964
20346722 3965/**
1da177e4
LT		 3966 * s2io_open - open entry point of the driver
3967 * @dev : pointer to the device structure.
3968 * Description:
3969 * This function is the open entry point of the driver. It mainly calls a
3970 * function to allocate Rx buffers and inserts them into the buffer
20346722 3971 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3972 * Return value:
3973 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3974 * file on failure.
3975 */
3976
ac1f60db 3977static int s2io_open(struct net_device *dev)
1da177e4 3978{
4cf1653a 3979 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 3980 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 3981 int err = 0;
3982
20346722
K		 3983 /*
3984 * Make sure you have link off by default every time
1da177e4
LT		 3985 * Nic is initialized
3986 */
3987 netif_carrier_off(dev);
0b1f7ebe 3988 sp->last_link_state = 0;
1da177e4
LT		 3989
3990 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3991 err = s2io_card_up(sp);
3992 if (err) {
1da177e4
LT		 3993 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3994 dev->name);
e6a8fee2 3995 goto hw_init_failed;
1da177e4
LT		 3996 }
3997
2fd37688 3998 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 3999 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4000 s2io_card_down(sp);
20346722 4001 err = -ENODEV;
e6a8fee2 4002 goto hw_init_failed;
1da177e4 4003 }
3a3d5756 4004 s2io_start_all_tx_queue(sp);
1da177e4 4005 return 0;
20346722 4006
20346722 4007hw_init_failed:
eaae7f72 4008 if (sp->config.intr_type == MSI_X) {
491976b2 4009 if (sp->entries) {
cc6e7c44 4010 kfree(sp->entries);
ffb5df6c
JP		 4011 swstats->mem_freed += sp->num_entries *
4012 sizeof(struct msix_entry);
491976b2
SH		 4013 }
4014 if (sp->s2io_entries) {
cc6e7c44 4015 kfree(sp->s2io_entries);
ffb5df6c
JP		 4016 swstats->mem_freed += sp->num_entries *
4017 sizeof(struct s2io_msix_entry);
491976b2 4018 }
cc6e7c44 4019 }
20346722 4020 return err;
1da177e4
LT		 4021}
4022
4023/**
4024 * s2io_close -close entry point of the driver
4025 * @dev : device pointer.
4026 * Description:
4027 * This is the stop entry point of the driver. It needs to undo exactly
4028 * whatever was done by the open entry point,thus it's usually referred to
4029 * as the close function.Among other things this function mainly stops the
4030 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4031 * Return value:
4032 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4033 * file on failure.
4034 */
4035
ac1f60db 4036static int s2io_close(struct net_device *dev)
1da177e4 4037{
4cf1653a 4038 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4039 struct config_param *config = &sp->config;
4040 u64 tmp64;
4041 int offset;
cc6e7c44 4042
9f74ffde 4043 /* Return if the device is already closed *
d44570e4
JP		 4044 * Can happen when s2io_card_up failed in change_mtu *
4045 */
9f74ffde
SH		 4046 if (!is_s2io_card_up(sp))
4047 return 0;
4048
3a3d5756 4049 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4050 /* delete all populated mac entries */
4051 for (offset = 1; offset < config->max_mc_addr; offset++) {
4052 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4053 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4054 do_s2io_delete_unicast_mc(sp, tmp64);
4055 }
4056
e6a8fee2 4057 s2io_card_down(sp);
cc6e7c44 4058
1da177e4
LT		 4059 return 0;
4060}
4061
4062/**
4063 * s2io_xmit - Tx entry point of te driver
4064 * @skb : the socket buffer containing the Tx data.
4065 * @dev : device pointer.
4066 * Description :
4067 * This function is the Tx entry point of the driver. S2IO NIC supports
4068 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4069 * NOTE: when device cant queue the pkt,just the trans_start variable will
4070 * not be upadted.
4071 * Return value:
4072 * 0 on success & 1 on failure.
4073 */
4074
61357325 4075static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4076{
4cf1653a 4077 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4078 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4079 register u64 val64;
1ee6dd77
RB		 4080 struct TxD *txdp;
4081 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4082 unsigned long flags = 0;
be3a6b02 4083 u16 vlan_tag = 0;
2fda096d 4084 struct fifo_info *fifo = NULL;
6cfc482b 4085 int do_spin_lock = 1;
75c30b13 4086 int offload_type;
6cfc482b 4087 int enable_per_list_interrupt = 0;
ffb5df6c
JP		 4088 struct config_param *config = &sp->config;
4089 struct mac_info *mac_control = &sp->mac_control;
4090 struct stat_block *stats = mac_control->stats_info;
4091 struct swStat *swstats = &stats->sw_stat;
1da177e4 4092
20346722 4093 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4094
4095 if (unlikely(skb->len <= 0)) {
9e39f7c5 4096 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
491976b2 4097 dev_kfree_skb_any(skb);
6ed10654 4098 return NETDEV_TX_OK;
2fda096d 4099 }
491976b2 4100
92b84437 4101 if (!is_s2io_card_up(sp)) {
20346722 4102 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4103 dev->name);
20346722 4104 dev_kfree_skb(skb);
6ed10654 4105 return NETDEV_TX_OK;
1da177e4
LT		 4106 }
4107
4108 queue = 0;
3a3d5756 4109 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4110 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4111 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4112 if (skb->protocol == htons(ETH_P_IP)) {
4113 struct iphdr *ip;
4114 struct tcphdr *th;
4115 ip = ip_hdr(skb);
4116
4117 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4118 th = (struct tcphdr *)(((unsigned char *)ip) +
d44570e4 4119 ip->ihl*4);
6cfc482b
SH		 4120
4121 if (ip->protocol == IPPROTO_TCP) {
4122 queue_len = sp->total_tcp_fifos;
4123 queue = (ntohs(th->source) +
d44570e4
JP		 4124 ntohs(th->dest)) &
4125 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4126 if (queue >= queue_len)
4127 queue = queue_len - 1;
4128 } else if (ip->protocol == IPPROTO_UDP) {
4129 queue_len = sp->total_udp_fifos;
4130 queue = (ntohs(th->source) +
d44570e4
JP		 4131 ntohs(th->dest)) &
4132 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4133 if (queue >= queue_len)
4134 queue = queue_len - 1;
4135 queue += sp->udp_fifo_idx;
4136 if (skb->len > 1024)
4137 enable_per_list_interrupt = 1;
4138 do_spin_lock = 0;
4139 }
4140 }
4141 }
4142 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4143 /* get fifo number based on skb->priority value */
4144 queue = config->fifo_mapping
d44570e4 4145 [skb->priority & (MAX_TX_FIFOS - 1)];
6cfc482b 4146 fifo = &mac_control->fifos[queue];
3a3d5756 4147
6cfc482b
SH		 4148 if (do_spin_lock)
4149 spin_lock_irqsave(&fifo->tx_lock, flags);
4150 else {
4151 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4152 return NETDEV_TX_LOCKED;
4153 }
be3a6b02 4154
3a3d5756
SH		 4155 if (sp->config.multiq) {
4156 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4157 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4158 return NETDEV_TX_BUSY;
4159 }
b19fa1fa 4160 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4161 if (netif_queue_stopped(dev)) {
4162 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4163 return NETDEV_TX_BUSY;
4164 }
4165 }
4166
d44570e4
JP		 4167 put_off = (u16)fifo->tx_curr_put_info.offset;
4168 get_off = (u16)fifo->tx_curr_get_info.offset;
4169 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
20346722 4170
2fda096d 4171 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4172 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4173 if (txdp->Host_Control ||
d44570e4 4174 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4175 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4176 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4177 dev_kfree_skb(skb);
2fda096d 4178 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4179 return NETDEV_TX_OK;
1da177e4 4180 }
0b1f7ebe 4181
75c30b13 4182 offload_type = s2io_offload_type(skb);
75c30b13 4183 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4184 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4185 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4186 }
84fa7933 4187 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d44570e4
JP		 4188 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4189 TXD_TX_CKO_TCP_EN |
4190 TXD_TX_CKO_UDP_EN);
1da177e4 4191 }
fed5eccd
AR		 4192 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4193 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4194 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4195 if (enable_per_list_interrupt)
4196 if (put_off & (queue_len >> 5))
4197 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4198 if (vlan_tag) {
be3a6b02
K		 4199 txdp->Control_2 |= TXD_VLAN_ENABLE;
4200 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4201 }
4202
e743d313 4203 frg_len = skb_headlen(skb);
75c30b13 4204 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4205 int ufo_size;
4206
75c30b13 4207 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4208 ufo_size &= ~7;
4209 txdp->Control_1 |= TXD_UFO_EN;
4210 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4211 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4212#ifdef __BIG_ENDIAN
3459feb8 4213 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4214 fifo->ufo_in_band_v[put_off] =
d44570e4 4215 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4216#else
2fda096d 4217 fifo->ufo_in_band_v[put_off] =
d44570e4 4218 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4219#endif
2fda096d 4220 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4221 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
d44570e4
JP		 4222 fifo->ufo_in_band_v,
4223 sizeof(u64),
4224 PCI_DMA_TODEVICE);
8d8bb39b 4225 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4226 goto pci_map_failed;
fed5eccd 4227 txdp++;
fed5eccd 4228 }
1da177e4 4229
d44570e4
JP		 4230 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4231 frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4232 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4233 goto pci_map_failed;
4234
d44570e4 4235 txdp->Host_Control = (unsigned long)skb;
fed5eccd 4236 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4237 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4238 txdp->Control_1 |= TXD_UFO_EN;
4239
4240 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4241 /* For fragmented SKB. */
4242 for (i = 0; i < frg_cnt; i++) {
4243 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4244 /* A '0' length fragment will be ignored */
4245 if (!frag->size)
4246 continue;
1da177e4 4247 txdp++;
d44570e4
JP		 4248 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4249 frag->page_offset,
4250 frag->size,
4251 PCI_DMA_TODEVICE);
efd51b5c 4252 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4253 if (offload_type == SKB_GSO_UDP)
fed5eccd 4254 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4255 }
4256 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4257
75c30b13 4258 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4259 frg_cnt++; /* as Txd0 was used for inband header */
4260
1da177e4 4261 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4262 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4263 writeq(val64, &tx_fifo->TxDL_Pointer);
4264
4265 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4266 TX_FIFO_LAST_LIST);
75c30b13 4267 if (offload_type)
fed5eccd 4268 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4269
1da177e4
LT		 4270 writeq(val64, &tx_fifo->List_Control);
4271
303bcb4b
K		 4272 mmiowb();
4273
1da177e4 4274 put_off++;
2fda096d 4275 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4276 put_off = 0;
2fda096d 4277 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4278
4279 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4280 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
ffb5df6c 4281 swstats->fifo_full_cnt++;
1da177e4
LT		 4282 DBG_PRINT(TX_DBG,
4283 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4284 put_off, get_off);
3a3d5756 4285 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4286 }
ffb5df6c 4287 swstats->mem_allocated += skb->truesize;
2fda096d 4288 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4289
f6f4bfa3
SH		 4290 if (sp->config.intr_type == MSI_X)
4291 tx_intr_handler(fifo);
4292
6ed10654 4293 return NETDEV_TX_OK;
ffb5df6c 4294
491abf25 4295pci_map_failed:
ffb5df6c 4296 swstats->pci_map_fail_cnt++;
3a3d5756 4297 s2io_stop_tx_queue(sp, fifo->fifo_no);
ffb5df6c 4298 swstats->mem_freed += skb->truesize;
491abf25 4299 dev_kfree_skb(skb);
2fda096d 4300 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4301 return NETDEV_TX_OK;
1da177e4
LT		 4302}
4303
25fff88e
K		 4304static void
4305s2io_alarm_handle(unsigned long data)
4306{
1ee6dd77 4307 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4308 struct net_device *dev = sp->dev;
25fff88e 4309
8116f3cf 4310 s2io_handle_errors(dev);
25fff88e
K		 4311 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4312}
4313
7d12e780 4314static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4315{
1ee6dd77
RB		 4316 struct ring_info *ring = (struct ring_info *)dev_id;
4317 struct s2io_nic *sp = ring->nic;
f61e0a35 4318 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4319
f61e0a35 4320 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4321 return IRQ_HANDLED;
92b84437 4322
f61e0a35 4323 if (sp->config.napi) {
1a79d1c3
AV		 4324 u8 __iomem *addr = NULL;
4325 u8 val8 = 0;
f61e0a35 4326
1a79d1c3 4327 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4328 addr += (7 - ring->ring_no);
4329 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4330 writeb(val8, addr);
4331 val8 = readb(addr);
288379f0 4332 napi_schedule(&ring->napi);
f61e0a35
SH		 4333 } else {
4334 rx_intr_handler(ring, 0);
8d8bb39b 4335 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4336 }
7d3d0439 4337
cc6e7c44
RA		 4338 return IRQ_HANDLED;
4339}
4340
7d12e780 4341static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4342{
ac731ab6
SH		 4343 int i;
4344 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4345 struct s2io_nic *sp = fifos->nic;
4346 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4347 struct config_param *config = &sp->config;
4348 u64 reason;
cc6e7c44 4349
ac731ab6
SH		 4350 if (unlikely(!is_s2io_card_up(sp)))
4351 return IRQ_NONE;
4352
4353 reason = readq(&bar0->general_int_status);
4354 if (unlikely(reason == S2IO_MINUS_ONE))
4355 /* Nothing much can be done. Get out */
92b84437 4356 return IRQ_HANDLED;
92b84437 4357
01e16faa
SH		 4358 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4359 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4360
01e16faa
SH		 4361 if (reason & GEN_INTR_TXPIC)
4362 s2io_txpic_intr_handle(sp);
ac731ab6 4363
01e16faa
SH		 4364 if (reason & GEN_INTR_TXTRAFFIC)
4365 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4366
01e16faa
SH		 4367 for (i = 0; i < config->tx_fifo_num; i++)
4368 tx_intr_handler(&fifos[i]);
ac731ab6 4369
01e16faa
SH		 4370 writeq(sp->general_int_mask, &bar0->general_int_mask);
4371 readl(&bar0->general_int_status);
4372 return IRQ_HANDLED;
4373 }
4374 /* The interrupt was not raised by us */
4375 return IRQ_NONE;
cc6e7c44 4376}
ac731ab6 4377
1ee6dd77 4378static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4379{
1ee6dd77 4380 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4381 u64 val64;
4382
4383 val64 = readq(&bar0->pic_int_status);
4384 if (val64 & PIC_INT_GPIO) {
4385 val64 = readq(&bar0->gpio_int_reg);
4386 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4387 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4388 /*
4389 * This is unstable state so clear both up/down
4390 * interrupt and adapter to re-evaluate the link state.
4391 */
d44570e4 4392 val64 |= GPIO_INT_REG_LINK_DOWN;
a371a07d
K		 4393 val64 |= GPIO_INT_REG_LINK_UP;
4394 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4395 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4396 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4397 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4398 writeq(val64, &bar0->gpio_int_mask);
d44570e4 4399 } else if (val64 & GPIO_INT_REG_LINK_UP) {
c92ca04b 4400 val64 = readq(&bar0->adapter_status);
d44570e4 4401 /* Enable Adapter */
19a60522
SS		 4402 val64 = readq(&bar0->adapter_control);
4403 val64 |= ADAPTER_CNTL_EN;
4404 writeq(val64, &bar0->adapter_control);
4405 val64 |= ADAPTER_LED_ON;
4406 writeq(val64, &bar0->adapter_control);
4407 if (!sp->device_enabled_once)
4408 sp->device_enabled_once = 1;
c92ca04b 4409
19a60522
SS		 4410 s2io_link(sp, LINK_UP);
4411 /*
4412 * unmask link down interrupt and mask link-up
4413 * intr
4414 */
4415 val64 = readq(&bar0->gpio_int_mask);
4416 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4417 val64 |= GPIO_INT_MASK_LINK_UP;
4418 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4419
d44570e4 4420 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
c92ca04b 4421 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4422 s2io_link(sp, LINK_DOWN);
4423 /* Link is down so unmaks link up interrupt */
4424 val64 = readq(&bar0->gpio_int_mask);
4425 val64 &= ~GPIO_INT_MASK_LINK_UP;
4426 val64 |= GPIO_INT_MASK_LINK_DOWN;
4427 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4428
4429 /* turn off LED */
4430 val64 = readq(&bar0->adapter_control);
d44570e4 4431 val64 = val64 & (~ADAPTER_LED_ON);
ac1f90d6 4432 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4433 }
4434 }
c92ca04b 4435 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4436}
4437
8116f3cf
SS		 4438/**
4439 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4440 * @value: alarm bits
4441 * @addr: address value
4442 * @cnt: counter variable
4443 * Description: Check for alarm and increment the counter
4444 * Return Value:
4445 * 1 - if alarm bit set
4446 * 0 - if alarm bit is not set
4447 */
d44570e4
JP		 4448static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4449 unsigned long long *cnt)
8116f3cf
SS		 4450{
4451 u64 val64;
4452 val64 = readq(addr);
d44570e4 4453 if (val64 & value) {
8116f3cf
SS		 4454 writeq(val64, addr);
4455 (*cnt)++;
4456 return 1;
4457 }
4458 return 0;
4459
4460}
4461
4462/**
4463 * s2io_handle_errors - Xframe error indication handler
4464 * @nic: device private variable
4465 * Description: Handle alarms such as loss of link, single or
4466 * double ECC errors, critical and serious errors.
4467 * Return Value:
4468 * NONE
4469 */
d44570e4 4470static void s2io_handle_errors(void *dev_id)
8116f3cf 4471{
d44570e4 4472 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4473 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf 4474 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d44570e4 4475 u64 temp64 = 0, val64 = 0;
8116f3cf
SS		 4476 int i = 0;
4477
4478 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4479 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4480
92b84437 4481 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4482 return;
4483
4484 if (pci_channel_offline(sp->pdev))
4485 return;
4486
4487 memset(&sw_stat->ring_full_cnt, 0,
d44570e4 4488 sizeof(sw_stat->ring_full_cnt));
8116f3cf
SS		 4489
4490 /* Handling the XPAK counters update */
d44570e4 4491 if (stats->xpak_timer_count < 72000) {
8116f3cf
SS		 4492 /* waiting for an hour */
4493 stats->xpak_timer_count++;
4494 } else {
4495 s2io_updt_xpak_counter(dev);
4496 /* reset the count to zero */
4497 stats->xpak_timer_count = 0;
4498 }
4499
4500 /* Handling link status change error Intr */
4501 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4502 val64 = readq(&bar0->mac_rmac_err_reg);
4503 writeq(val64, &bar0->mac_rmac_err_reg);
4504 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4505 schedule_work(&sp->set_link_task);
4506 }
4507
4508 /* In case of a serious error, the device will be Reset. */
4509 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
d44570e4 4510 &sw_stat->serious_err_cnt))
8116f3cf
SS		 4511 goto reset;
4512
4513 /* Check for data parity error */
4514 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
d44570e4 4515 &sw_stat->parity_err_cnt))
8116f3cf
SS		 4516 goto reset;
4517
4518 /* Check for ring full counter */
4519 if (sp->device_type == XFRAME_II_DEVICE) {
4520 val64 = readq(&bar0->ring_bump_counter1);
d44570e4
JP		 4521 for (i = 0; i < 4; i++) {
4522 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf
SS		 4523 temp64 >>= 64 - ((i+1)*16);
4524 sw_stat->ring_full_cnt[i] += temp64;
4525 }
4526
4527 val64 = readq(&bar0->ring_bump_counter2);
d44570e4
JP		 4528 for (i = 0; i < 4; i++) {
4529 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf 4530 temp64 >>= 64 - ((i+1)*16);
d44570e4 4531 sw_stat->ring_full_cnt[i+4] += temp64;
8116f3cf
SS		 4532 }
4533 }
4534
4535 val64 = readq(&bar0->txdma_int_status);
4536 /*check for pfc_err*/
4537 if (val64 & TXDMA_PFC_INT) {
d44570e4
JP		 4538 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4539 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4540 PFC_PCIX_ERR,
4541 &bar0->pfc_err_reg,
4542 &sw_stat->pfc_err_cnt))
8116f3cf 4543 goto reset;
d44570e4
JP		 4544 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4545 &bar0->pfc_err_reg,
4546 &sw_stat->pfc_err_cnt);
8116f3cf
SS		 4547 }
4548
4549 /*check for tda_err*/
4550 if (val64 & TXDMA_TDA_INT) {
d44570e4
JP		 4551 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4552 TDA_SM0_ERR_ALARM |
4553 TDA_SM1_ERR_ALARM,
4554 &bar0->tda_err_reg,
4555 &sw_stat->tda_err_cnt))
8116f3cf
SS		 4556 goto reset;
4557 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
d44570e4
JP		 4558 &bar0->tda_err_reg,
4559 &sw_stat->tda_err_cnt);
8116f3cf
SS		 4560 }
4561 /*check for pcc_err*/
4562 if (val64 & TXDMA_PCC_INT) {
d44570e4
JP		 4563 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4564 PCC_N_SERR | PCC_6_COF_OV_ERR |
4565 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4566 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4567 PCC_TXB_ECC_DB_ERR,
4568 &bar0->pcc_err_reg,
4569 &sw_stat->pcc_err_cnt))
8116f3cf
SS		 4570 goto reset;
4571 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
d44570e4
JP		 4572 &bar0->pcc_err_reg,
4573 &sw_stat->pcc_err_cnt);
8116f3cf
SS		 4574 }
4575
4576 /*check for tti_err*/
4577 if (val64 & TXDMA_TTI_INT) {
d44570e4
JP		 4578 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4579 &bar0->tti_err_reg,
4580 &sw_stat->tti_err_cnt))
8116f3cf
SS		 4581 goto reset;
4582 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
d44570e4
JP		 4583 &bar0->tti_err_reg,
4584 &sw_stat->tti_err_cnt);
8116f3cf
SS		 4585 }
4586
4587 /*check for lso_err*/
4588 if (val64 & TXDMA_LSO_INT) {
d44570e4
JP		 4589 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4590 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4591 &bar0->lso_err_reg,
4592 &sw_stat->lso_err_cnt))
8116f3cf
SS		 4593 goto reset;
4594 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
d44570e4
JP		 4595 &bar0->lso_err_reg,
4596 &sw_stat->lso_err_cnt);
8116f3cf
SS		 4597 }
4598
4599 /*check for tpa_err*/
4600 if (val64 & TXDMA_TPA_INT) {
d44570e4
JP		 4601 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4602 &bar0->tpa_err_reg,
4603 &sw_stat->tpa_err_cnt))
8116f3cf 4604 goto reset;
d44570e4
JP		 4605 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4606 &bar0->tpa_err_reg,
4607 &sw_stat->tpa_err_cnt);
8116f3cf
SS		 4608 }
4609
4610 /*check for sm_err*/
4611 if (val64 & TXDMA_SM_INT) {
d44570e4
JP		 4612 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4613 &bar0->sm_err_reg,
4614 &sw_stat->sm_err_cnt))
8116f3cf
SS		 4615 goto reset;
4616 }
4617
4618 val64 = readq(&bar0->mac_int_status);
4619 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4620 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
d44570e4
JP		 4621 &bar0->mac_tmac_err_reg,
4622 &sw_stat->mac_tmac_err_cnt))
8116f3cf 4623 goto reset;
d44570e4
JP		 4624 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4625 TMAC_DESC_ECC_SG_ERR |
4626 TMAC_DESC_ECC_DB_ERR,
4627 &bar0->mac_tmac_err_reg,
4628 &sw_stat->mac_tmac_err_cnt);
8116f3cf
SS		 4629 }
4630
4631 val64 = readq(&bar0->xgxs_int_status);
4632 if (val64 & XGXS_INT_STATUS_TXGXS) {
4633 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
d44570e4
JP		 4634 &bar0->xgxs_txgxs_err_reg,
4635 &sw_stat->xgxs_txgxs_err_cnt))
8116f3cf
SS		 4636 goto reset;
4637 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
d44570e4
JP		 4638 &bar0->xgxs_txgxs_err_reg,
4639 &sw_stat->xgxs_txgxs_err_cnt);
8116f3cf
SS		 4640 }
4641
4642 val64 = readq(&bar0->rxdma_int_status);
4643 if (val64 & RXDMA_INT_RC_INT_M) {
d44570e4
JP		 4644 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4645 RC_FTC_ECC_DB_ERR |
4646 RC_PRCn_SM_ERR_ALARM |
4647 RC_FTC_SM_ERR_ALARM,
4648 &bar0->rc_err_reg,
4649 &sw_stat->rc_err_cnt))
8116f3cf 4650 goto reset;
d44570e4
JP		 4651 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4652 RC_FTC_ECC_SG_ERR |
4653 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4654 &sw_stat->rc_err_cnt);
4655 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4656 PRC_PCI_AB_WR_Rn |
4657 PRC_PCI_AB_F_WR_Rn,
4658 &bar0->prc_pcix_err_reg,
4659 &sw_stat->prc_pcix_err_cnt))
8116f3cf 4660 goto reset;
d44570e4
JP		 4661 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4662 PRC_PCI_DP_WR_Rn |
4663 PRC_PCI_DP_F_WR_Rn,
4664 &bar0->prc_pcix_err_reg,
4665 &sw_stat->prc_pcix_err_cnt);
8116f3cf
SS		 4666 }
4667
4668 if (val64 & RXDMA_INT_RPA_INT_M) {
4669 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
d44570e4
JP		 4670 &bar0->rpa_err_reg,
4671 &sw_stat->rpa_err_cnt))
8116f3cf
SS		 4672 goto reset;
4673 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
d44570e4
JP		 4674 &bar0->rpa_err_reg,
4675 &sw_stat->rpa_err_cnt);
8116f3cf
SS		 4676 }
4677
4678 if (val64 & RXDMA_INT_RDA_INT_M) {
d44570e4
JP		 4679 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4680 RDA_FRM_ECC_DB_N_AERR |
4681 RDA_SM1_ERR_ALARM |
4682 RDA_SM0_ERR_ALARM |
4683 RDA_RXD_ECC_DB_SERR,
4684 &bar0->rda_err_reg,
4685 &sw_stat->rda_err_cnt))
8116f3cf 4686 goto reset;
d44570e4
JP		 4687 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4688 RDA_FRM_ECC_SG_ERR |
4689 RDA_MISC_ERR |
4690 RDA_PCIX_ERR,
4691 &bar0->rda_err_reg,
4692 &sw_stat->rda_err_cnt);
8116f3cf
SS		 4693 }
4694
4695 if (val64 & RXDMA_INT_RTI_INT_M) {
d44570e4
JP		 4696 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4697 &bar0->rti_err_reg,
4698 &sw_stat->rti_err_cnt))
8116f3cf
SS		 4699 goto reset;
4700 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
d44570e4
JP		 4701 &bar0->rti_err_reg,
4702 &sw_stat->rti_err_cnt);
8116f3cf
SS		 4703 }
4704
4705 val64 = readq(&bar0->mac_int_status);
4706 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4707 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
d44570e4
JP		 4708 &bar0->mac_rmac_err_reg,
4709 &sw_stat->mac_rmac_err_cnt))
8116f3cf 4710 goto reset;
d44570e4
JP		 4711 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4712 RMAC_SINGLE_ECC_ERR |
4713 RMAC_DOUBLE_ECC_ERR,
4714 &bar0->mac_rmac_err_reg,
4715 &sw_stat->mac_rmac_err_cnt);
8116f3cf
SS		 4716 }
4717
4718 val64 = readq(&bar0->xgxs_int_status);
4719 if (val64 & XGXS_INT_STATUS_RXGXS) {
4720 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
d44570e4
JP		 4721 &bar0->xgxs_rxgxs_err_reg,
4722 &sw_stat->xgxs_rxgxs_err_cnt))
8116f3cf
SS		 4723 goto reset;
4724 }
4725
4726 val64 = readq(&bar0->mc_int_status);
d44570e4
JP		 4727 if (val64 & MC_INT_STATUS_MC_INT) {
4728 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4729 &bar0->mc_err_reg,
4730 &sw_stat->mc_err_cnt))
8116f3cf
SS		 4731 goto reset;
4732
4733 /* Handling Ecc errors */
4734 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4735 writeq(val64, &bar0->mc_err_reg);
4736 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4737 sw_stat->double_ecc_errs++;
4738 if (sp->device_type != XFRAME_II_DEVICE) {
4739 /*
4740 * Reset XframeI only if critical error
4741 */
4742 if (val64 &
d44570e4
JP		 4743 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4744 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4745 goto reset;
4746 }
8116f3cf
SS		 4747 } else
4748 sw_stat->single_ecc_errs++;
4749 }
4750 }
4751 return;
4752
4753reset:
3a3d5756 4754 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4755 schedule_work(&sp->rst_timer_task);
4756 sw_stat->soft_reset_cnt++;
8116f3cf
SS		 4757}
4758
1da177e4
LT		 4759/**
4760 * s2io_isr - ISR handler of the device .
4761 * @irq: the irq of the device.
4762 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4763 * Description: This function is the ISR handler of the device. It
4764 * identifies the reason for the interrupt and calls the relevant
4765 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4766 * recv buffers, if their numbers are below the panic value which is
4767 * presently set to 25% of the original number of rcv buffers allocated.
4768 * Return value:
20346722 4769 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4770 * IRQ_NONE: will be returned if interrupt is not from our device
4771 */
7d12e780 4772static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4 4773{
d44570e4 4774 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4775 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4776 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4777 int i;
19a60522 4778 u64 reason = 0;
1ee6dd77 4779 struct mac_info *mac_control;
1da177e4
LT		 4780 struct config_param *config;
4781
d796fdb7
LV		 4782 /* Pretend we handled any irq's from a disconnected card */
4783 if (pci_channel_offline(sp->pdev))
4784 return IRQ_NONE;
4785
596c5c97 4786 if (!is_s2io_card_up(sp))
92b84437 4787 return IRQ_NONE;
92b84437 4788
1da177e4 4789 config = &sp->config;
ffb5df6c 4790 mac_control = &sp->mac_control;
1da177e4 4791
20346722 4792 /*
1da177e4
LT		 4793 * Identify the cause for interrupt and call the appropriate
4794 * interrupt handler. Causes for the interrupt could be;
4795 * 1. Rx of packet.
4796 * 2. Tx complete.
4797 * 3. Link down.
1da177e4
LT		 4798 */
4799 reason = readq(&bar0->general_int_status);
4800
d44570e4
JP		 4801 if (unlikely(reason == S2IO_MINUS_ONE))
4802 return IRQ_HANDLED; /* Nothing much can be done. Get out */
5d3213cc 4803
d44570e4
JP		 4804 if (reason &
4805 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
596c5c97
SS		 4806 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4807
4808 if (config->napi) {
4809 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4810 napi_schedule(&sp->napi);
f61e0a35
SH		 4811 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4812 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4813 readl(&bar0->rx_traffic_int);
db874e65 4814 }
596c5c97
SS		 4815 } else {
4816 /*
4817 * rx_traffic_int reg is an R1 register, writing all 1's
4818 * will ensure that the actual interrupt causing bit
4819 * get's cleared and hence a read can be avoided.
4820 */
4821 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4822 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4823
13d866a9
JP		 4824 for (i = 0; i < config->rx_ring_num; i++) {
4825 struct ring_info *ring = &mac_control->rings[i];
4826
4827 rx_intr_handler(ring, 0);
4828 }
db874e65 4829 }
596c5c97 4830
db874e65 4831 /*
596c5c97 4832 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4833 * will ensure that the actual interrupt causing bit get's
4834 * cleared and hence a read can be avoided.
4835 */
596c5c97
SS		 4836 if (reason & GEN_INTR_TXTRAFFIC)
4837 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4838
596c5c97
SS		 4839 for (i = 0; i < config->tx_fifo_num; i++)
4840 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4841
596c5c97
SS		 4842 if (reason & GEN_INTR_TXPIC)
4843 s2io_txpic_intr_handle(sp);
fe113638 4844
596c5c97
SS		 4845 /*
4846 * Reallocate the buffers from the interrupt handler itself.
4847 */
4848 if (!config->napi) {
13d866a9
JP		 4849 for (i = 0; i < config->rx_ring_num; i++) {
4850 struct ring_info *ring = &mac_control->rings[i];
4851
4852 s2io_chk_rx_buffers(sp, ring);
4853 }
596c5c97
SS		 4854 }
4855 writeq(sp->general_int_mask, &bar0->general_int_mask);
4856 readl(&bar0->general_int_status);
20346722 4857
596c5c97 4858 return IRQ_HANDLED;
db874e65 4859
d44570e4 4860 } else if (!reason) {
596c5c97
SS		 4861 /* The interrupt was not raised by us */
4862 return IRQ_NONE;
4863 }
db874e65 4864
1da177e4
LT		 4865 return IRQ_HANDLED;
4866}
4867
7ba013ac
K		 4868/**
4869 * s2io_updt_stats -
4870 */
1ee6dd77 4871static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4872{
1ee6dd77 4873 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4874 u64 val64;
4875 int cnt = 0;
4876
92b84437 4877 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4878 /* Apprx 30us on a 133 MHz bus */
4879 val64 = SET_UPDT_CLICKS(10) |
4880 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4881 writeq(val64, &bar0->stat_cfg);
4882 do {
4883 udelay(100);
4884 val64 = readq(&bar0->stat_cfg);
b7b5a128 4885 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4886 break;
4887 cnt++;
4888 if (cnt == 5)
4889 break; /* Updt failed */
d44570e4 4890 } while (1);
8a4bdbaa 4891 }
7ba013ac
K		 4892}
4893
1da177e4 4894/**
20346722 4895 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4896 * @dev : pointer to the device structure.
4897 * Description:
20346722 4898 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4899 * structure and returns a pointer to the same.
4900 * Return value:
4901 * pointer to the updated net_device_stats structure.
4902 */
4903
ac1f60db 4904static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4905{
4cf1653a 4906 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 4907 struct config_param *config = &sp->config;
4908 struct mac_info *mac_control = &sp->mac_control;
4909 struct stat_block *stats = mac_control->stats_info;
0425b46a 4910 int i;
1da177e4 4911
7ba013ac
K		 4912 /* Configure Stats for immediate updt */
4913 s2io_updt_stats(sp);
4914
dc56e634
BL		 4915 /* Using sp->stats as a staging area, because reset (due to mtu
4916 change, for example) will clear some hardware counters */
ffb5df6c 4917 dev->stats.tx_packets += le32_to_cpu(stats->tmac_frms) -
dc56e634 4918 sp->stats.tx_packets;
ffb5df6c
JP		 4919 sp->stats.tx_packets = le32_to_cpu(stats->tmac_frms);
4920
4921 dev->stats.tx_errors += le32_to_cpu(stats->tmac_any_err_frms) -
dc56e634 4922 sp->stats.tx_errors;
ffb5df6c
JP		 4923 sp->stats.tx_errors = le32_to_cpu(stats->tmac_any_err_frms);
4924
4925 dev->stats.rx_errors += le64_to_cpu(stats->rmac_drop_frms) -
dc56e634 4926 sp->stats.rx_errors;
ffb5df6c
JP		 4927 sp->stats.rx_errors = le64_to_cpu(stats->rmac_drop_frms);
4928
4929 dev->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms) -
dc56e634 4930 sp->stats.multicast;
ffb5df6c
JP		 4931 sp->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms);
4932
4933 dev->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms) -
dc56e634 4934 sp->stats.rx_length_errors;
ffb5df6c 4935 sp->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms);
1da177e4 4936
0425b46a 4937 /* collect per-ring rx_packets and rx_bytes */
dc56e634 4938 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
0425b46a 4939 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 4940 struct ring_info *ring = &mac_control->rings[i];
4941
4942 dev->stats.rx_packets += ring->rx_packets;
4943 dev->stats.rx_bytes += ring->rx_bytes;
0425b46a
SH		 4944 }
4945
d44570e4 4946 return &dev->stats;
1da177e4
LT		 4947}
4948
4949/**
4950 * s2io_set_multicast - entry point for multicast address enable/disable.
4951 * @dev : pointer to the device structure
4952 * Description:
20346722
K		 4953 * This function is a driver entry point which gets called by the kernel
4954 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4955 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4956 * determine, if multicast address must be enabled or if promiscuous mode
4957 * is to be disabled etc.
4958 * Return value:
4959 * void.
4960 */
4961
4962static void s2io_set_multicast(struct net_device *dev)
4963{
4964 int i, j, prev_cnt;
22bedad3 4965 struct netdev_hw_addr *ha;
4cf1653a 4966 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4967 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4968 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
d44570e4 4969 0xfeffffffffffULL;
faa4f796 4970 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4971 void __iomem *add;
faa4f796 4972 struct config_param *config = &sp->config;
1da177e4
LT		 4973
4974 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4975 /* Enable all Multicast addresses */
4976 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4977 &bar0->rmac_addr_data0_mem);
4978 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4979 &bar0->rmac_addr_data1_mem);
4980 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 4981 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4982 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4983 writeq(val64, &bar0->rmac_addr_cmd_mem);
4984 /* Wait till command completes */
c92ca04b 4985 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 4986 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4987 S2IO_BIT_RESET);
1da177e4
LT		 4988
4989 sp->m_cast_flg = 1;
faa4f796 4990 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 4991 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4992 /* Disable all Multicast addresses */
4993 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4994 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4995 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4996 &bar0->rmac_addr_data1_mem);
1da177e4 4997 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 4998 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4999 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
1da177e4
LT		 5000 writeq(val64, &bar0->rmac_addr_cmd_mem);
5001 /* Wait till command completes */
c92ca04b 5002 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5003 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5004 S2IO_BIT_RESET);
1da177e4
LT		 5005
5006 sp->m_cast_flg = 0;
5007 sp->all_multi_pos = 0;
5008 }
5009
5010 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5011 /* Put the NIC into promiscuous mode */
5012 add = &bar0->mac_cfg;
5013 val64 = readq(&bar0->mac_cfg);
5014 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5015
5016 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5017 writel((u32)val64, add);
1da177e4
LT		 5018 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5019 writel((u32) (val64 >> 32), (add + 4));
5020
926930b2
SS		 5021 if (vlan_tag_strip != 1) {
5022 val64 = readq(&bar0->rx_pa_cfg);
5023 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5024 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5025 sp->vlan_strip_flag = 0;
926930b2
SS		 5026 }
5027
1da177e4
LT		 5028 val64 = readq(&bar0->mac_cfg);
5029 sp->promisc_flg = 1;
776bd20f 5030 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5031 dev->name);
5032 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5033 /* Remove the NIC from promiscuous mode */
5034 add = &bar0->mac_cfg;
5035 val64 = readq(&bar0->mac_cfg);
5036 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5037
5038 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5039 writel((u32)val64, add);
1da177e4
LT		 5040 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5041 writel((u32) (val64 >> 32), (add + 4));
5042
926930b2
SS		 5043 if (vlan_tag_strip != 0) {
5044 val64 = readq(&bar0->rx_pa_cfg);
5045 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5046 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5047 sp->vlan_strip_flag = 1;
926930b2
SS		 5048 }
5049
1da177e4
LT		 5050 val64 = readq(&bar0->mac_cfg);
5051 sp->promisc_flg = 0;
9e39f7c5 5052 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
1da177e4
LT		 5053 }
5054
5055 /* Update individual M_CAST address list */
4cd24eaf
JP		 5056 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5057 if (netdev_mc_count(dev) >
faa4f796 5058 (config->max_mc_addr - config->max_mac_addr)) {
9e39f7c5
JP		 5059 DBG_PRINT(ERR_DBG,
5060 "%s: No more Rx filters can be added - "
5061 "please enable ALL_MULTI instead\n",
1da177e4 5062 dev->name);
1da177e4
LT		 5063 return;
5064 }
5065
5066 prev_cnt = sp->mc_addr_count;
4cd24eaf 5067 sp->mc_addr_count = netdev_mc_count(dev);
1da177e4
LT		 5068
5069 /* Clear out the previous list of Mc in the H/W. */
5070 for (i = 0; i < prev_cnt; i++) {
5071 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5072 &bar0->rmac_addr_data0_mem);
5073 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5074 &bar0->rmac_addr_data1_mem);
1da177e4 5075 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5076 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5077 RMAC_ADDR_CMD_MEM_OFFSET
5078 (config->mc_start_offset + i);
1da177e4
LT		 5079 writeq(val64, &bar0->rmac_addr_cmd_mem);
5080
5081 /* Wait for command completes */
c92ca04b 5082 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5083 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5084 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5085 DBG_PRINT(ERR_DBG,
5086 "%s: Adding Multicasts failed\n",
5087 dev->name);
1da177e4
LT		 5088 return;
5089 }
5090 }
5091
5092 /* Create the new Rx filter list and update the same in H/W. */
5508590c 5093 i = 0;
22bedad3
JP		 5094 netdev_for_each_mc_addr(ha, dev) {
5095 memcpy(sp->usr_addrs[i].addr, ha->addr,
1da177e4 5096 ETH_ALEN);
a7a80d5a 5097 mac_addr = 0;
1da177e4 5098 for (j = 0; j < ETH_ALEN; j++) {
22bedad3 5099 mac_addr |= ha->addr[j];
1da177e4
LT		 5100 mac_addr <<= 8;
5101 }
5102 mac_addr >>= 8;
5103 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5104 &bar0->rmac_addr_data0_mem);
5105 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5106 &bar0->rmac_addr_data1_mem);
1da177e4 5107 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5108 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5109 RMAC_ADDR_CMD_MEM_OFFSET
5110 (i + config->mc_start_offset);
1da177e4
LT		 5111 writeq(val64, &bar0->rmac_addr_cmd_mem);
5112
5113 /* Wait for command completes */
c92ca04b 5114 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5115 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5116 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5117 DBG_PRINT(ERR_DBG,
5118 "%s: Adding Multicasts failed\n",
5119 dev->name);
1da177e4
LT		 5120 return;
5121 }
5508590c 5122 i++;
1da177e4
LT		 5123 }
5124 }
5125}
5126
faa4f796
SH		 5127/* read from CAM unicast & multicast addresses and store it in
5128 * def_mac_addr structure
5129 */
dac499f9 5130static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5131{
5132 int offset;
5133 u64 mac_addr = 0x0;
5134 struct config_param *config = &sp->config;
5135
5136 /* store unicast & multicast mac addresses */
5137 for (offset = 0; offset < config->max_mc_addr; offset++) {
5138 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5139 /* if read fails disable the entry */
5140 if (mac_addr == FAILURE)
5141 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5142 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5143 }
5144}
5145
5146/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5147static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5148{
5149 int offset;
5150 struct config_param *config = &sp->config;
5151 /* restore unicast mac address */
5152 for (offset = 0; offset < config->max_mac_addr; offset++)
5153 do_s2io_prog_unicast(sp->dev,
d44570e4 5154 sp->def_mac_addr[offset].mac_addr);
faa4f796
SH		 5155
5156 /* restore multicast mac address */
5157 for (offset = config->mc_start_offset;
d44570e4 5158 offset < config->max_mc_addr; offset++)
faa4f796
SH		 5159 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5160}
5161
5162/* add a multicast MAC address to CAM */
5163static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5164{
5165 int i;
5166 u64 mac_addr = 0;
5167 struct config_param *config = &sp->config;
5168
5169 for (i = 0; i < ETH_ALEN; i++) {
5170 mac_addr <<= 8;
5171 mac_addr |= addr[i];
5172 }
5173 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5174 return SUCCESS;
5175
5176 /* check if the multicast mac already preset in CAM */
5177 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5178 u64 tmp64;
5179 tmp64 = do_s2io_read_unicast_mc(sp, i);
5180 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5181 break;
5182
5183 if (tmp64 == mac_addr)
5184 return SUCCESS;
5185 }
5186 if (i == config->max_mc_addr) {
5187 DBG_PRINT(ERR_DBG,
d44570e4 5188 "CAM full no space left for multicast MAC\n");
faa4f796
SH		 5189 return FAILURE;
5190 }
5191 /* Update the internal structure with this new mac address */
5192 do_s2io_copy_mac_addr(sp, i, mac_addr);
5193
d44570e4 5194 return do_s2io_add_mac(sp, mac_addr, i);
faa4f796
SH		 5195}
5196
5197/* add MAC address to CAM */
5198static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5199{
5200 u64 val64;
5201 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5202
5203 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
d44570e4 5204 &bar0->rmac_addr_data0_mem);
2fd37688 5205
d44570e4 5206 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2fd37688
SS		 5207 RMAC_ADDR_CMD_MEM_OFFSET(off);
5208 writeq(val64, &bar0->rmac_addr_cmd_mem);
5209
5210 /* Wait till command completes */
5211 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5212 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5213 S2IO_BIT_RESET)) {
faa4f796 5214 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5215 return FAILURE;
5216 }
5217 return SUCCESS;
5218}
faa4f796
SH		 5219/* deletes a specified unicast/multicast mac entry from CAM */
5220static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5221{
5222 int offset;
5223 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5224 struct config_param *config = &sp->config;
5225
5226 for (offset = 1;
d44570e4 5227 offset < config->max_mc_addr; offset++) {
faa4f796
SH		 5228 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5229 if (tmp64 == addr) {
5230 /* disable the entry by writing 0xffffffffffffULL */
5231 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5232 return FAILURE;
5233 /* store the new mac list from CAM */
5234 do_s2io_store_unicast_mc(sp);
5235 return SUCCESS;
5236 }
5237 }
5238 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
d44570e4 5239 (unsigned long long)addr);
faa4f796
SH		 5240 return FAILURE;
5241}
5242
5243/* read mac entries from CAM */
5244static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5245{
5246 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5247 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5248
5249 /* read mac addr */
d44570e4 5250 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796
SH		 5251 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5252 writeq(val64, &bar0->rmac_addr_cmd_mem);
5253
5254 /* Wait till command completes */
5255 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5256 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5257 S2IO_BIT_RESET)) {
faa4f796
SH		 5258 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5259 return FAILURE;
5260 }
5261 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4
JP		 5262
5263 return tmp64 >> 16;
faa4f796 5264}
2fd37688
SS		 5265
5266/**
5267 * s2io_set_mac_addr driver entry point
5268 */
faa4f796 5269
2fd37688
SS		 5270static int s2io_set_mac_addr(struct net_device *dev, void *p)
5271{
5272 struct sockaddr *addr = p;
5273
5274 if (!is_valid_ether_addr(addr->sa_data))
5275 return -EINVAL;
5276
5277 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5278
5279 /* store the MAC address in CAM */
d44570e4 5280 return do_s2io_prog_unicast(dev, dev->dev_addr);
2fd37688 5281}
1da177e4 5282/**
2fd37688 5283 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5284 * @dev : pointer to the device structure.
5285 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5286 * Description : This procedure will program the Xframe to receive
1da177e4 5287 * frames with new Mac Address
20346722 5288 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5289 * as defined in errno.h file on failure.
5290 */
faa4f796 5291
2fd37688 5292static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5293{
4cf1653a 5294 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5295 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5296 int i;
faa4f796
SH		 5297 u64 tmp64;
5298 struct config_param *config = &sp->config;
1da177e4 5299
20346722 5300 /*
d44570e4
JP		 5301 * Set the new MAC address as the new unicast filter and reflect this
5302 * change on the device address registered with the OS. It will be
5303 * at offset 0.
5304 */
1da177e4
LT		 5305 for (i = 0; i < ETH_ALEN; i++) {
5306 mac_addr <<= 8;
5307 mac_addr |= addr[i];
2fd37688
SS		 5308 perm_addr <<= 8;
5309 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5310 }
5311
2fd37688
SS		 5312 /* check if the dev_addr is different than perm_addr */
5313 if (mac_addr == perm_addr)
d8d70caf
SS		 5314 return SUCCESS;
5315
faa4f796
SH		 5316 /* check if the mac already preset in CAM */
5317 for (i = 1; i < config->max_mac_addr; i++) {
5318 tmp64 = do_s2io_read_unicast_mc(sp, i);
5319 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5320 break;
5321
5322 if (tmp64 == mac_addr) {
5323 DBG_PRINT(INFO_DBG,
d44570e4
JP		 5324 "MAC addr:0x%llx already present in CAM\n",
5325 (unsigned long long)mac_addr);
faa4f796
SH		 5326 return SUCCESS;
5327 }
5328 }
5329 if (i == config->max_mac_addr) {
5330 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5331 return FAILURE;
5332 }
d8d70caf 5333 /* Update the internal structure with this new mac address */
faa4f796 5334 do_s2io_copy_mac_addr(sp, i, mac_addr);
d44570e4
JP		 5335
5336 return do_s2io_add_mac(sp, mac_addr, i);
1da177e4
LT		 5337}
5338
5339/**
20346722 5340 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5341 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5342 * @info: pointer to the structure with parameters given by ethtool to set
5343 * link information.
5344 * Description:
20346722 5345 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5346 * the NIC.
5347 * Return value:
5348 * 0 on success.
d44570e4 5349 */
1da177e4
LT		 5350
5351static int s2io_ethtool_sset(struct net_device *dev,
5352 struct ethtool_cmd *info)
5353{
4cf1653a 5354 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5355 if ((info->autoneg == AUTONEG_ENABLE) ||
d44570e4
JP		 5356 (info->speed != SPEED_10000) ||
5357 (info->duplex != DUPLEX_FULL))
1da177e4
LT		 5358 return -EINVAL;
5359 else {
5360 s2io_close(sp->dev);
5361 s2io_open(sp->dev);
5362 }
5363
5364 return 0;
5365}
5366
5367/**
20346722 5368 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5369 * @sp : private member of the device structure, pointer to the
5370 * s2io_nic structure.
5371 * @info : pointer to the structure with parameters given by ethtool
5372 * to return link information.
5373 * Description:
5374 * Returns link specific information like speed, duplex etc.. to ethtool.
5375 * Return value :
5376 * return 0 on success.
5377 */
5378
5379static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5380{
4cf1653a 5381 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5382 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5383 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5384 info->port = PORT_FIBRE;
1a7eb72b
SS		 5385
5386 /* info->transceiver */
5387 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5388
5389 if (netif_carrier_ok(sp->dev)) {
5390 info->speed = 10000;
5391 info->duplex = DUPLEX_FULL;
5392 } else {
5393 info->speed = -1;
5394 info->duplex = -1;
5395 }
5396
5397 info->autoneg = AUTONEG_DISABLE;
5398 return 0;
5399}
5400
5401/**
20346722
K		 5402 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5403 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5404 * s2io_nic structure.
5405 * @info : pointer to the structure with parameters given by ethtool to
5406 * return driver information.
5407 * Description:
5408 * Returns driver specefic information like name, version etc.. to ethtool.
5409 * Return value:
5410 * void
5411 */
5412
5413static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5414 struct ethtool_drvinfo *info)
5415{
4cf1653a 5416 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5417
dbc2309d
JL		 5418 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5419 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5420 strncpy(info->fw_version, "", sizeof(info->fw_version));
5421 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5422 info->regdump_len = XENA_REG_SPACE;
5423 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5424}
5425
5426/**
5427 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5428 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5429 * s2io_nic structure.
20346722 5430 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5431 * dumping the registers.
5432 * @reg_space: The input argumnet into which all the registers are dumped.
5433 * Description:
5434 * Dumps the entire register space of xFrame NIC into the user given
5435 * buffer area.
5436 * Return value :
5437 * void .
d44570e4 5438 */
1da177e4
LT		 5439
5440static void s2io_ethtool_gregs(struct net_device *dev,
5441 struct ethtool_regs *regs, void *space)
5442{
5443 int i;
5444 u64 reg;
d44570e4 5445 u8 *reg_space = (u8 *)space;
4cf1653a 5446 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5447
5448 regs->len = XENA_REG_SPACE;
5449 regs->version = sp->pdev->subsystem_device;
5450
5451 for (i = 0; i < regs->len; i += 8) {
5452 reg = readq(sp->bar0 + i);
5453 memcpy((reg_space + i), &reg, 8);
5454 }
5455}
5456
5457/**
5458 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5459 * @data : address of the private member of the device structure, which
1da177e4 5460 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 5461 * Description: This is actually the timer function that alternates the
5462 * adapter LED bit of the adapter control bit to set/reset every time on
5463 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4 5464 * once every second.
d44570e4 5465 */
1da177e4
LT		 5466static void s2io_phy_id(unsigned long data)
5467{
d44570e4 5468 struct s2io_nic *sp = (struct s2io_nic *)data;
1ee6dd77 5469 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5470 u64 val64 = 0;
5471 u16 subid;
5472
5473 subid = sp->pdev->subsystem_device;
541ae68f 5474 if ((sp->device_type == XFRAME_II_DEVICE) ||
d44570e4 5475 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5476 val64 = readq(&bar0->gpio_control);
5477 val64 ^= GPIO_CTRL_GPIO_0;
5478 writeq(val64, &bar0->gpio_control);
5479 } else {
5480 val64 = readq(&bar0->adapter_control);
5481 val64 ^= ADAPTER_LED_ON;
5482 writeq(val64, &bar0->adapter_control);
5483 }
5484
5485 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5486}
5487
5488/**
5489 * s2io_ethtool_idnic - To physically identify the nic on the system.
5490 * @sp : private member of the device structure, which is a pointer to the
5491 * s2io_nic structure.
20346722 5492 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5493 * ethtool.
5494 * Description: Used to physically identify the NIC on the system.
20346722 5495 * The Link LED will blink for a time specified by the user for
1da177e4 5496 * identification.
20346722 5497 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5498 * identification is possible only if it's link is up.
5499 * Return value:
5500 * int , returns 0 on success
5501 */
5502
5503static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5504{
5505 u64 val64 = 0, last_gpio_ctrl_val;
4cf1653a 5506 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5507 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5508 u16 subid;
5509
5510 subid = sp->pdev->subsystem_device;
5511 last_gpio_ctrl_val = readq(&bar0->gpio_control);
d44570e4 5512 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5513 val64 = readq(&bar0->adapter_control);
5514 if (!(val64 & ADAPTER_CNTL_EN)) {
6cef2b8e 5515 pr_err("Adapter Link down, cannot blink LED\n");
1da177e4
LT		 5516 return -EFAULT;
5517 }
5518 }
5519 if (sp->id_timer.function == NULL) {
5520 init_timer(&sp->id_timer);
5521 sp->id_timer.function = s2io_phy_id;
d44570e4 5522 sp->id_timer.data = (unsigned long)sp;
1da177e4
LT		 5523 }
5524 mod_timer(&sp->id_timer, jiffies);
5525 if (data)
20346722 5526 msleep_interruptible(data * HZ);
1da177e4 5527 else
20346722 5528 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5529 del_timer_sync(&sp->id_timer);
5530
541ae68f 5531 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5532 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5533 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5534 }
5535
5536 return 0;
5537}
5538
0cec35eb 5539static void s2io_ethtool_gringparam(struct net_device *dev,
d44570e4 5540 struct ethtool_ringparam *ering)
0cec35eb 5541{
4cf1653a 5542 struct s2io_nic *sp = netdev_priv(dev);
d44570e4 5543 int i, tx_desc_count = 0, rx_desc_count = 0;
0cec35eb
SH		 5544
5545 if (sp->rxd_mode == RXD_MODE_1)
5546 ering->rx_max_pending = MAX_RX_DESC_1;
5547 else if (sp->rxd_mode == RXD_MODE_3B)
5548 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5549
5550 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5551 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5552 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5553
9e39f7c5 5554 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
0cec35eb
SH		 5555 ering->tx_pending = tx_desc_count;
5556 rx_desc_count = 0;
8a4bdbaa 5557 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5558 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5559
0cec35eb
SH		 5560 ering->rx_pending = rx_desc_count;
5561
5562 ering->rx_mini_max_pending = 0;
5563 ering->rx_mini_pending = 0;
d44570e4 5564 if (sp->rxd_mode == RXD_MODE_1)
0cec35eb
SH		 5565 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5566 else if (sp->rxd_mode == RXD_MODE_3B)
5567 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5568 ering->rx_jumbo_pending = rx_desc_count;
5569}
5570
1da177e4
LT		 5571/**
5572 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5573 * @sp : private member of the device structure, which is a pointer to the
5574 * s2io_nic structure.
1da177e4
LT		 5575 * @ep : pointer to the structure with pause parameters given by ethtool.
5576 * Description:
5577 * Returns the Pause frame generation and reception capability of the NIC.
5578 * Return value:
5579 * void
5580 */
5581static void s2io_ethtool_getpause_data(struct net_device *dev,
5582 struct ethtool_pauseparam *ep)
5583{
5584 u64 val64;
4cf1653a 5585 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5586 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5587
5588 val64 = readq(&bar0->rmac_pause_cfg);
5589 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5590 ep->tx_pause = true;
1da177e4 5591 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5592 ep->rx_pause = true;
5593 ep->autoneg = false;
1da177e4
LT		 5594}
5595
5596/**
5597 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5598 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5599 * s2io_nic structure.
5600 * @ep : pointer to the structure with pause parameters given by ethtool.
5601 * Description:
5602 * It can be used to set or reset Pause frame generation or reception
5603 * support of the NIC.
5604 * Return value:
5605 * int, returns 0 on Success
5606 */
5607
5608static int s2io_ethtool_setpause_data(struct net_device *dev,
d44570e4 5609 struct ethtool_pauseparam *ep)
1da177e4
LT		 5610{
5611 u64 val64;
4cf1653a 5612 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5613 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5614
5615 val64 = readq(&bar0->rmac_pause_cfg);
5616 if (ep->tx_pause)
5617 val64 |= RMAC_PAUSE_GEN_ENABLE;
5618 else
5619 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5620 if (ep->rx_pause)
5621 val64 |= RMAC_PAUSE_RX_ENABLE;
5622 else
5623 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5624 writeq(val64, &bar0->rmac_pause_cfg);
5625 return 0;
5626}
5627
5628/**
5629 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5630 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5631 * s2io_nic structure.
5632 * @off : offset at which the data must be written
5633 * @data : Its an output parameter where the data read at the given
20346722 5634 * offset is stored.
1da177e4 5635 * Description:
20346722 5636 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5637 * read data.
5638 * NOTE: Will allow to read only part of the EEPROM visible through the
5639 * I2C bus.
5640 * Return value:
5641 * -1 on failure and 0 on success.
5642 */
5643
5644#define S2IO_DEV_ID 5
d44570e4 5645static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
1da177e4
LT		 5646{
5647 int ret = -1;
5648 u32 exit_cnt = 0;
5649 u64 val64;
1ee6dd77 5650 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5651
ad4ebed0 5652 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5653 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5654 I2C_CONTROL_ADDR(off) |
5655 I2C_CONTROL_BYTE_CNT(0x3) |
5656 I2C_CONTROL_READ |
5657 I2C_CONTROL_CNTL_START;
ad4ebed0 5658 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5659
ad4ebed0 5660 while (exit_cnt < 5) {
5661 val64 = readq(&bar0->i2c_control);
5662 if (I2C_CONTROL_CNTL_END(val64)) {
5663 *data = I2C_CONTROL_GET_DATA(val64);
5664 ret = 0;
5665 break;
5666 }
5667 msleep(50);
5668 exit_cnt++;
1da177e4 5669 }
1da177e4
LT		 5670 }
5671
ad4ebed0 5672 if (sp->device_type == XFRAME_II_DEVICE) {
5673 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5674 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5675 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5676 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5677 val64 |= SPI_CONTROL_REQ;
5678 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5679 while (exit_cnt < 5) {
5680 val64 = readq(&bar0->spi_control);
5681 if (val64 & SPI_CONTROL_NACK) {
5682 ret = 1;
5683 break;
5684 } else if (val64 & SPI_CONTROL_DONE) {
5685 *data = readq(&bar0->spi_data);
5686 *data &= 0xffffff;
5687 ret = 0;
5688 break;
5689 }
5690 msleep(50);
5691 exit_cnt++;
5692 }
5693 }
1da177e4
LT		 5694 return ret;
5695}
5696
5697/**
5698 * write_eeprom - actually writes the relevant part of the data value.
5699 * @sp : private member of the device structure, which is a pointer to the
5700 * s2io_nic structure.
5701 * @off : offset at which the data must be written
5702 * @data : The data that is to be written
20346722 5703 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5704 * the Eeprom. (max of 3)
5705 * Description:
5706 * Actually writes the relevant part of the data value into the Eeprom
5707 * through the I2C bus.
5708 * Return value:
5709 * 0 on success, -1 on failure.
5710 */
5711
d44570e4 5712static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
1da177e4
LT		 5713{
5714 int exit_cnt = 0, ret = -1;
5715 u64 val64;
1ee6dd77 5716 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5717
ad4ebed0 5718 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5719 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5720 I2C_CONTROL_ADDR(off) |
5721 I2C_CONTROL_BYTE_CNT(cnt) |
5722 I2C_CONTROL_SET_DATA((u32)data) |
5723 I2C_CONTROL_CNTL_START;
ad4ebed0 5724 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5725
5726 while (exit_cnt < 5) {
5727 val64 = readq(&bar0->i2c_control);
5728 if (I2C_CONTROL_CNTL_END(val64)) {
5729 if (!(val64 & I2C_CONTROL_NACK))
5730 ret = 0;
5731 break;
5732 }
5733 msleep(50);
5734 exit_cnt++;
5735 }
5736 }
1da177e4 5737
ad4ebed0 5738 if (sp->device_type == XFRAME_II_DEVICE) {
5739 int write_cnt = (cnt == 8) ? 0 : cnt;
d44570e4 5740 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
ad4ebed0 5741
5742 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5743 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5744 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5745 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5746 val64 |= SPI_CONTROL_REQ;
5747 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5748 while (exit_cnt < 5) {
5749 val64 = readq(&bar0->spi_control);
5750 if (val64 & SPI_CONTROL_NACK) {
5751 ret = 1;
5752 break;
5753 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5754 ret = 0;
ad4ebed0 5755 break;
5756 }
5757 msleep(50);
5758 exit_cnt++;
1da177e4 5759 }
1da177e4 5760 }
1da177e4
LT		 5761 return ret;
5762}
1ee6dd77 5763static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5764{
b41477f3
AR		 5765 u8 *vpd_data;
5766 u8 data;
d44570e4 5767 int i = 0, cnt, fail = 0;
9dc737a7 5768 int vpd_addr = 0x80;
ffb5df6c 5769 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
9dc737a7
AR		 5770
5771 if (nic->device_type == XFRAME_II_DEVICE) {
5772 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5773 vpd_addr = 0x80;
d44570e4 5774 } else {
9dc737a7
AR		 5775 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5776 vpd_addr = 0x50;
5777 }
19a60522 5778 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5779
b41477f3 5780 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945 5781 if (!vpd_data) {
ffb5df6c 5782 swstats->mem_alloc_fail_cnt++;
b41477f3 5783 return;
c53d4945 5784 }
ffb5df6c 5785 swstats->mem_allocated += 256;
b41477f3 5786
d44570e4 5787 for (i = 0; i < 256; i += 4) {
9dc737a7
AR		 5788 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5789 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5790 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
d44570e4 5791 for (cnt = 0; cnt < 5; cnt++) {
9dc737a7
AR		 5792 msleep(2);
5793 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5794 if (data == 0x80)
5795 break;
5796 }
5797 if (cnt >= 5) {
5798 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5799 fail = 1;
5800 break;
5801 }
5802 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5803 (u32 *)&vpd_data[i]);
5804 }
19a60522 5805
d44570e4 5806 if (!fail) {
19a60522
SS		 5807 /* read serial number of adapter */
5808 for (cnt = 0; cnt < 256; cnt++) {
d44570e4
JP		 5809 if ((vpd_data[cnt] == 'S') &&
5810 (vpd_data[cnt+1] == 'N') &&
5811 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
19a60522
SS		 5812 memset(nic->serial_num, 0, VPD_STRING_LEN);
5813 memcpy(nic->serial_num, &vpd_data[cnt + 3],
d44570e4 5814 vpd_data[cnt+2]);
19a60522
SS		 5815 break;
5816 }
5817 }
5818 }
5819
876e956f 5820 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN))
9dc737a7 5821 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
b41477f3 5822 kfree(vpd_data);
ffb5df6c 5823 swstats->mem_freed += 256;
9dc737a7
AR		 5824}
5825
1da177e4
LT		 5826/**
5827 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5828 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5829 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5830 * containing all relevant information.
5831 * @data_buf : user defined value to be written into Eeprom.
5832 * Description: Reads the values stored in the Eeprom at given offset
5833 * for a given length. Stores these values int the input argument data
5834 * buffer 'data_buf' and returns these to the caller (ethtool.)
5835 * Return value:
5836 * int 0 on success
5837 */
5838
5839static int s2io_ethtool_geeprom(struct net_device *dev,
d44570e4 5840 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5841{
ad4ebed0 5842 u32 i, valid;
5843 u64 data;
4cf1653a 5844 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5845
5846 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5847
5848 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5849 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5850
5851 for (i = 0; i < eeprom->len; i += 4) {
5852 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5853 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5854 return -EFAULT;
5855 }
5856 valid = INV(data);
5857 memcpy((data_buf + i), &valid, 4);
5858 }
5859 return 0;
5860}
5861
5862/**
5863 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5864 * @sp : private member of the device structure, which is a pointer to the
5865 * s2io_nic structure.
20346722 5866 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5867 * containing all relevant information.
5868 * @data_buf ; user defined value to be written into Eeprom.
5869 * Description:
5870 * Tries to write the user provided value in the Eeprom, at the offset
5871 * given by the user.
5872 * Return value:
5873 * 0 on success, -EFAULT on failure.
5874 */
5875
5876static int s2io_ethtool_seeprom(struct net_device *dev,
5877 struct ethtool_eeprom *eeprom,
d44570e4 5878 u8 *data_buf)
1da177e4
LT		 5879{
5880 int len = eeprom->len, cnt = 0;
ad4ebed0 5881 u64 valid = 0, data;
4cf1653a 5882 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5883
5884 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5885 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5886 "ETHTOOL_WRITE_EEPROM Err: "
5887 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5888 (sp->pdev->vendor | (sp->pdev->device << 16)),
5889 eeprom->magic);
1da177e4
LT		 5890 return -EFAULT;
5891 }
5892
5893 while (len) {
d44570e4
JP		 5894 data = (u32)data_buf[cnt] & 0x000000FF;
5895 if (data)
5896 valid = (u32)(data << 24);
5897 else
1da177e4
LT		 5898 valid = data;
5899
5900 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5901 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5902 "ETHTOOL_WRITE_EEPROM Err: "
5903 "Cannot write into the specified offset\n");
1da177e4
LT		 5904 return -EFAULT;
5905 }
5906 cnt++;
5907 len--;
5908 }
5909
5910 return 0;
5911}
5912
5913/**
20346722
K		 5914 * s2io_register_test - reads and writes into all clock domains.
5915 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5916 * s2io_nic structure.
5917 * @data : variable that returns the result of each of the test conducted b
5918 * by the driver.
5919 * Description:
5920 * Read and write into all clock domains. The NIC has 3 clock domains,
5921 * see that registers in all the three regions are accessible.
5922 * Return value:
5923 * 0 on success.
5924 */
5925
d44570e4 5926static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 5927{
1ee6dd77 5928 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5929 u64 val64 = 0, exp_val;
1da177e4
LT		 5930 int fail = 0;
5931
20346722
K		 5932 val64 = readq(&bar0->pif_rd_swapper_fb);
5933 if (val64 != 0x123456789abcdefULL) {
1da177e4 5934 fail = 1;
9e39f7c5 5935 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
1da177e4
LT		 5936 }
5937
5938 val64 = readq(&bar0->rmac_pause_cfg);
5939 if (val64 != 0xc000ffff00000000ULL) {
5940 fail = 1;
9e39f7c5 5941 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
1da177e4
LT		 5942 }
5943
5944 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5945 if (sp->device_type == XFRAME_II_DEVICE)
5946 exp_val = 0x0404040404040404ULL;
5947 else
5948 exp_val = 0x0808080808080808ULL;
5949 if (val64 != exp_val) {
1da177e4 5950 fail = 1;
9e39f7c5 5951 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
1da177e4
LT		 5952 }
5953
5954 val64 = readq(&bar0->xgxs_efifo_cfg);
5955 if (val64 != 0x000000001923141EULL) {
5956 fail = 1;
9e39f7c5 5957 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
1da177e4
LT		 5958 }
5959
5960 val64 = 0x5A5A5A5A5A5A5A5AULL;
5961 writeq(val64, &bar0->xmsi_data);
5962 val64 = readq(&bar0->xmsi_data);
5963 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5964 fail = 1;
9e39f7c5 5965 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
1da177e4
LT		 5966 }
5967
5968 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5969 writeq(val64, &bar0->xmsi_data);
5970 val64 = readq(&bar0->xmsi_data);
5971 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5972 fail = 1;
9e39f7c5 5973 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
1da177e4
LT		 5974 }
5975
5976 *data = fail;
ad4ebed0 5977 return fail;
1da177e4
LT		 5978}
5979
5980/**
20346722 5981 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5982 * @sp : private member of the device structure, which is a pointer to the
5983 * s2io_nic structure.
5984 * @data:variable that returns the result of each of the test conducted by
5985 * the driver.
5986 * Description:
20346722 5987 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5988 * register.
5989 * Return value:
5990 * 0 on success.
5991 */
5992
d44570e4 5993static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 5994{
5995 int fail = 0;
ad4ebed0 5996 u64 ret_data, org_4F0, org_7F0;
5997 u8 saved_4F0 = 0, saved_7F0 = 0;
5998 struct net_device *dev = sp->dev;
1da177e4
LT		 5999
6000 /* Test Write Error at offset 0 */
ad4ebed0 6001 /* Note that SPI interface allows write access to all areas
6002 * of EEPROM. Hence doing all negative testing only for Xframe I.
6003 */
6004 if (sp->device_type == XFRAME_I_DEVICE)
6005 if (!write_eeprom(sp, 0, 0, 3))
6006 fail = 1;
6007
6008 /* Save current values at offsets 0x4F0 and 0x7F0 */
6009 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6010 saved_4F0 = 1;
6011 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6012 saved_7F0 = 1;
1da177e4
LT		 6013
6014 /* Test Write at offset 4f0 */
ad4ebed0 6015 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6016 fail = 1;
6017 if (read_eeprom(sp, 0x4F0, &ret_data))
6018 fail = 1;
6019
ad4ebed0 6020 if (ret_data != 0x012345) {
26b7625c 6021 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
d44570e4
JP		 6022 "Data written %llx Data read %llx\n",
6023 dev->name, (unsigned long long)0x12345,
6024 (unsigned long long)ret_data);
1da177e4 6025 fail = 1;
ad4ebed0 6026 }
1da177e4
LT		 6027
6028 /* Reset the EEPROM data go FFFF */
ad4ebed0 6029 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6030
6031 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6032 if (sp->device_type == XFRAME_I_DEVICE)
6033 if (!write_eeprom(sp, 0x07C, 0, 3))
6034 fail = 1;
1da177e4 6035
ad4ebed0 6036 /* Test Write Request at offset 0x7f0 */
6037 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6038 fail = 1;
ad4ebed0 6039 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6040 fail = 1;
6041
ad4ebed0 6042 if (ret_data != 0x012345) {
26b7625c 6043 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
d44570e4
JP		 6044 "Data written %llx Data read %llx\n",
6045 dev->name, (unsigned long long)0x12345,
6046 (unsigned long long)ret_data);
1da177e4 6047 fail = 1;
ad4ebed0 6048 }
1da177e4
LT		 6049
6050 /* Reset the EEPROM data go FFFF */
ad4ebed0 6051 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6052
ad4ebed0 6053 if (sp->device_type == XFRAME_I_DEVICE) {
6054 /* Test Write Error at offset 0x80 */
6055 if (!write_eeprom(sp, 0x080, 0, 3))
6056 fail = 1;
1da177e4 6057
ad4ebed0 6058 /* Test Write Error at offset 0xfc */
6059 if (!write_eeprom(sp, 0x0FC, 0, 3))
6060 fail = 1;
1da177e4 6061
ad4ebed0 6062 /* Test Write Error at offset 0x100 */
6063 if (!write_eeprom(sp, 0x100, 0, 3))
6064 fail = 1;
1da177e4 6065
ad4ebed0 6066 /* Test Write Error at offset 4ec */
6067 if (!write_eeprom(sp, 0x4EC, 0, 3))
6068 fail = 1;
6069 }
6070
6071 /* Restore values at offsets 0x4F0 and 0x7F0 */
6072 if (saved_4F0)
6073 write_eeprom(sp, 0x4F0, org_4F0, 3);
6074 if (saved_7F0)
6075 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6076
6077 *data = fail;
ad4ebed0 6078 return fail;
1da177e4
LT		 6079}
6080
6081/**
6082 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6083 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6084 * s2io_nic structure.
20346722 6085 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6086 * the driver.
6087 * Description:
6088 * This invokes the MemBist test of the card. We give around
6089 * 2 secs time for the Test to complete. If it's still not complete
20346722 6090 * within this peiod, we consider that the test failed.
1da177e4
LT		 6091 * Return value:
6092 * 0 on success and -1 on failure.
6093 */
6094
d44570e4 6095static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6096{
6097 u8 bist = 0;
6098 int cnt = 0, ret = -1;
6099
6100 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6101 bist |= PCI_BIST_START;
6102 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6103
6104 while (cnt < 20) {
6105 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6106 if (!(bist & PCI_BIST_START)) {
6107 *data = (bist & PCI_BIST_CODE_MASK);
6108 ret = 0;
6109 break;
6110 }
6111 msleep(100);
6112 cnt++;
6113 }
6114
6115 return ret;
6116}
6117
6118/**
20346722
K		 6119 * s2io-link_test - verifies the link state of the nic
6120 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6121 * s2io_nic structure.
6122 * @data: variable that returns the result of each of the test conducted by
6123 * the driver.
6124 * Description:
20346722 6125 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6126 * argument 'data' appropriately.
6127 * Return value:
6128 * 0 on success.
6129 */
6130
d44570e4 6131static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6132{
1ee6dd77 6133 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6134 u64 val64;
6135
6136 val64 = readq(&bar0->adapter_status);
d44570e4 6137 if (!(LINK_IS_UP(val64)))
1da177e4 6138 *data = 1;
c92ca04b
AR		 6139 else
6140 *data = 0;
1da177e4 6141
b41477f3 6142 return *data;
1da177e4
LT		 6143}
6144
6145/**
20346722
K		 6146 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6147 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6148 * s2io_nic structure.
20346722 6149 * @data - variable that returns the result of each of the test
1da177e4
LT		 6150 * conducted by the driver.
6151 * Description:
20346722 6152 * This is one of the offline test that tests the read and write
1da177e4
LT		 6153 * access to the RldRam chip on the NIC.
6154 * Return value:
6155 * 0 on success.
6156 */
6157
d44570e4 6158static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6159{
1ee6dd77 6160 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6161 u64 val64;
ad4ebed0 6162 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6163
6164 val64 = readq(&bar0->adapter_control);
6165 val64 &= ~ADAPTER_ECC_EN;
6166 writeq(val64, &bar0->adapter_control);
6167
6168 val64 = readq(&bar0->mc_rldram_test_ctrl);
6169 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6170 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6171
6172 val64 = readq(&bar0->mc_rldram_mrs);
6173 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6174 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6175
6176 val64 |= MC_RLDRAM_MRS_ENABLE;
6177 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6178
6179 while (iteration < 2) {
6180 val64 = 0x55555555aaaa0000ULL;
d44570e4 6181 if (iteration == 1)
1da177e4 6182 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6183 writeq(val64, &bar0->mc_rldram_test_d0);
6184
6185 val64 = 0xaaaa5a5555550000ULL;
d44570e4 6186 if (iteration == 1)
1da177e4 6187 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6188 writeq(val64, &bar0->mc_rldram_test_d1);
6189
6190 val64 = 0x55aaaaaaaa5a0000ULL;
d44570e4 6191 if (iteration == 1)
1da177e4 6192 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6193 writeq(val64, &bar0->mc_rldram_test_d2);
6194
ad4ebed0 6195 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6196 writeq(val64, &bar0->mc_rldram_test_add);
6197
d44570e4
JP		 6198 val64 = MC_RLDRAM_TEST_MODE |
6199 MC_RLDRAM_TEST_WRITE |
6200 MC_RLDRAM_TEST_GO;
ad4ebed0 6201 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6202
6203 for (cnt = 0; cnt < 5; cnt++) {
6204 val64 = readq(&bar0->mc_rldram_test_ctrl);
6205 if (val64 & MC_RLDRAM_TEST_DONE)
6206 break;
6207 msleep(200);
6208 }
6209
6210 if (cnt == 5)
6211 break;
6212
ad4ebed0 6213 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6214 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6215
6216 for (cnt = 0; cnt < 5; cnt++) {
6217 val64 = readq(&bar0->mc_rldram_test_ctrl);
6218 if (val64 & MC_RLDRAM_TEST_DONE)
6219 break;
6220 msleep(500);
6221 }
6222
6223 if (cnt == 5)
6224 break;
6225
6226 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6227 if (!(val64 & MC_RLDRAM_TEST_PASS))
6228 test_fail = 1;
1da177e4
LT		 6229
6230 iteration++;
6231 }
6232
ad4ebed0 6233 *data = test_fail;
1da177e4 6234
ad4ebed0 6235 /* Bring the adapter out of test mode */
6236 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6237
6238 return test_fail;
1da177e4
LT		 6239}
6240
6241/**
6242 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6243 * @sp : private member of the device structure, which is a pointer to the
6244 * s2io_nic structure.
6245 * @ethtest : pointer to a ethtool command specific structure that will be
6246 * returned to the user.
20346722 6247 * @data : variable that returns the result of each of the test
1da177e4
LT		 6248 * conducted by the driver.
6249 * Description:
6250 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6251 * the health of the card.
6252 * Return value:
6253 * void
6254 */
6255
6256static void s2io_ethtool_test(struct net_device *dev,
6257 struct ethtool_test *ethtest,
d44570e4 6258 uint64_t *data)
1da177e4 6259{
4cf1653a 6260 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6261 int orig_state = netif_running(sp->dev);
6262
6263 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6264 /* Offline Tests. */
20346722 6265 if (orig_state)
1da177e4 6266 s2io_close(sp->dev);
1da177e4
LT		 6267
6268 if (s2io_register_test(sp, &data[0]))
6269 ethtest->flags |= ETH_TEST_FL_FAILED;
6270
6271 s2io_reset(sp);
1da177e4
LT		 6272
6273 if (s2io_rldram_test(sp, &data[3]))
6274 ethtest->flags |= ETH_TEST_FL_FAILED;
6275
6276 s2io_reset(sp);
1da177e4
LT		 6277
6278 if (s2io_eeprom_test(sp, &data[1]))
6279 ethtest->flags |= ETH_TEST_FL_FAILED;
6280
6281 if (s2io_bist_test(sp, &data[4]))
6282 ethtest->flags |= ETH_TEST_FL_FAILED;
6283
6284 if (orig_state)
6285 s2io_open(sp->dev);
6286
6287 data[2] = 0;
6288 } else {
6289 /* Online Tests. */
6290 if (!orig_state) {
d44570e4 6291 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
1da177e4
LT		 6292 dev->name);
6293 data[0] = -1;
6294 data[1] = -1;
6295 data[2] = -1;
6296 data[3] = -1;
6297 data[4] = -1;
6298 }
6299
6300 if (s2io_link_test(sp, &data[2]))
6301 ethtest->flags |= ETH_TEST_FL_FAILED;
6302
6303 data[0] = 0;
6304 data[1] = 0;
6305 data[3] = 0;
6306 data[4] = 0;
6307 }
6308}
6309
6310static void s2io_get_ethtool_stats(struct net_device *dev,
6311 struct ethtool_stats *estats,
d44570e4 6312 u64 *tmp_stats)
1da177e4 6313{
8116f3cf 6314 int i = 0, k;
4cf1653a 6315 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 6316 struct stat_block *stats = sp->mac_control.stats_info;
6317 struct swStat *swstats = &stats->sw_stat;
6318 struct xpakStat *xstats = &stats->xpak_stat;
1da177e4 6319
7ba013ac 6320 s2io_updt_stats(sp);
541ae68f 6321 tmp_stats[i++] =
ffb5df6c
JP		 6322 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6323 le32_to_cpu(stats->tmac_frms);
541ae68f 6324 tmp_stats[i++] =
ffb5df6c
JP		 6325 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6326 le32_to_cpu(stats->tmac_data_octets);
6327 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
541ae68f 6328 tmp_stats[i++] =
ffb5df6c
JP		 6329 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6330 le32_to_cpu(stats->tmac_mcst_frms);
541ae68f 6331 tmp_stats[i++] =
ffb5df6c
JP		 6332 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6333 le32_to_cpu(stats->tmac_bcst_frms);
6334 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
bd1034f0 6335 tmp_stats[i++] =
ffb5df6c
JP		 6336 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6337 le32_to_cpu(stats->tmac_ttl_octets);
bd1034f0 6338 tmp_stats[i++] =
ffb5df6c
JP		 6339 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6340 le32_to_cpu(stats->tmac_ucst_frms);
d44570e4 6341 tmp_stats[i++] =
ffb5df6c
JP		 6342 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6343 le32_to_cpu(stats->tmac_nucst_frms);
541ae68f 6344 tmp_stats[i++] =
ffb5df6c
JP		 6345 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6346 le32_to_cpu(stats->tmac_any_err_frms);
6347 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6348 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
541ae68f 6349 tmp_stats[i++] =
ffb5df6c
JP		 6350 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6351 le32_to_cpu(stats->tmac_vld_ip);
541ae68f 6352 tmp_stats[i++] =
ffb5df6c
JP		 6353 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6354 le32_to_cpu(stats->tmac_drop_ip);
541ae68f 6355 tmp_stats[i++] =
ffb5df6c
JP		 6356 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6357 le32_to_cpu(stats->tmac_icmp);
541ae68f 6358 tmp_stats[i++] =
ffb5df6c
JP		 6359 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6360 le32_to_cpu(stats->tmac_rst_tcp);
6361 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6362 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6363 le32_to_cpu(stats->tmac_udp);
541ae68f 6364 tmp_stats[i++] =
ffb5df6c
JP		 6365 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6366 le32_to_cpu(stats->rmac_vld_frms);
541ae68f 6367 tmp_stats[i++] =
ffb5df6c
JP		 6368 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6369 le32_to_cpu(stats->rmac_data_octets);
6370 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6371 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
541ae68f 6372 tmp_stats[i++] =
ffb5df6c
JP		 6373 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6374 le32_to_cpu(stats->rmac_vld_mcst_frms);
541ae68f 6375 tmp_stats[i++] =
ffb5df6c
JP		 6376 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6377 le32_to_cpu(stats->rmac_vld_bcst_frms);
6378 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6379 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6380 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6381 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6382 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
d44570e4 6383 tmp_stats[i++] =
ffb5df6c
JP		 6384 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6385 le32_to_cpu(stats->rmac_ttl_octets);
bd1034f0 6386 tmp_stats[i++] =
ffb5df6c
JP		 6387 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6388 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
d44570e4 6389 tmp_stats[i++] =
ffb5df6c
JP		 6390 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6391 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
541ae68f 6392 tmp_stats[i++] =
ffb5df6c
JP		 6393 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6394 le32_to_cpu(stats->rmac_discarded_frms);
d44570e4 6395 tmp_stats[i++] =
ffb5df6c
JP		 6396 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6397 << 32 | le32_to_cpu(stats->rmac_drop_events);
6398 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6399 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
541ae68f 6400 tmp_stats[i++] =
ffb5df6c
JP		 6401 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6402 le32_to_cpu(stats->rmac_usized_frms);
541ae68f 6403 tmp_stats[i++] =
ffb5df6c
JP		 6404 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6405 le32_to_cpu(stats->rmac_osized_frms);
541ae68f 6406 tmp_stats[i++] =
ffb5df6c
JP		 6407 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6408 le32_to_cpu(stats->rmac_frag_frms);
541ae68f 6409 tmp_stats[i++] =
ffb5df6c
JP		 6410 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6411 le32_to_cpu(stats->rmac_jabber_frms);
6412 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6413 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6414 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6416 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6417 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
bd1034f0 6418 tmp_stats[i++] =
ffb5df6c
JP		 6419 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6420 le32_to_cpu(stats->rmac_ip);
6421 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6422 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
bd1034f0 6423 tmp_stats[i++] =
ffb5df6c
JP		 6424 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6425 le32_to_cpu(stats->rmac_drop_ip);
bd1034f0 6426 tmp_stats[i++] =
ffb5df6c
JP		 6427 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6428 le32_to_cpu(stats->rmac_icmp);
6429 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
bd1034f0 6430 tmp_stats[i++] =
ffb5df6c
JP		 6431 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6432 le32_to_cpu(stats->rmac_udp);
541ae68f 6433 tmp_stats[i++] =
ffb5df6c
JP		 6434 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6435 le32_to_cpu(stats->rmac_err_drp_udp);
6436 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6437 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6438 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6439 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6440 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6441 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6442 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6443 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6445 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6446 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6447 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6448 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6449 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6450 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6451 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6452 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
541ae68f 6453 tmp_stats[i++] =
ffb5df6c
JP		 6454 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6455 le32_to_cpu(stats->rmac_pause_cnt);
6456 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6457 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
541ae68f 6458 tmp_stats[i++] =
ffb5df6c
JP		 6459 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6460 le32_to_cpu(stats->rmac_accepted_ip);
6461 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6462 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6463 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6464 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6465 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6466 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6467 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6468 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6469 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6470 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6471 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6472 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6473 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6474 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6475 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6476 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6477 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6478 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6479 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
fa1f0cb3
SS		 6480
6481 /* Enhanced statistics exist only for Hercules */
d44570e4 6482 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6483 tmp_stats[i++] =
ffb5df6c 6484 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
fa1f0cb3 6485 tmp_stats[i++] =
ffb5df6c 6486 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
fa1f0cb3 6487 tmp_stats[i++] =
ffb5df6c
JP		 6488 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6489 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6490 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6491 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6492 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6493 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6494 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6495 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6496 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6497 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6498 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6499 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6500 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6501 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
fa1f0cb3
SS		 6502 }
6503
7ba013ac 6504 tmp_stats[i++] = 0;
ffb5df6c
JP		 6505 tmp_stats[i++] = swstats->single_ecc_errs;
6506 tmp_stats[i++] = swstats->double_ecc_errs;
6507 tmp_stats[i++] = swstats->parity_err_cnt;
6508 tmp_stats[i++] = swstats->serious_err_cnt;
6509 tmp_stats[i++] = swstats->soft_reset_cnt;
6510 tmp_stats[i++] = swstats->fifo_full_cnt;
8116f3cf 6511 for (k = 0; k < MAX_RX_RINGS; k++)
ffb5df6c
JP		 6512 tmp_stats[i++] = swstats->ring_full_cnt[k];
6513 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6514 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6515 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6516 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6517 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6518 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6519 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6520 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6521 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6522 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6523 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6524 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6525 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6526 tmp_stats[i++] = swstats->sending_both;
6527 tmp_stats[i++] = swstats->outof_sequence_pkts;
6528 tmp_stats[i++] = swstats->flush_max_pkts;
6529 if (swstats->num_aggregations) {
6530 u64 tmp = swstats->sum_avg_pkts_aggregated;
bd1034f0 6531 int count = 0;
6aa20a22 6532 /*
bd1034f0
AR		 6533 * Since 64-bit divide does not work on all platforms,
6534 * do repeated subtraction.
6535 */
ffb5df6c
JP		 6536 while (tmp >= swstats->num_aggregations) {
6537 tmp -= swstats->num_aggregations;
bd1034f0
AR		 6538 count++;
6539 }
6540 tmp_stats[i++] = count;
d44570e4 6541 } else
bd1034f0 6542 tmp_stats[i++] = 0;
ffb5df6c
JP		 6543 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6544 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6545 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6546 tmp_stats[i++] = swstats->mem_allocated;
6547 tmp_stats[i++] = swstats->mem_freed;
6548 tmp_stats[i++] = swstats->link_up_cnt;
6549 tmp_stats[i++] = swstats->link_down_cnt;
6550 tmp_stats[i++] = swstats->link_up_time;
6551 tmp_stats[i++] = swstats->link_down_time;
6552
6553 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6554 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6555 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6556 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6557 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6558
6559 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6560 tmp_stats[i++] = swstats->rx_abort_cnt;
6561 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6562 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6563 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6564 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6565 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6566 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6567 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6568 tmp_stats[i++] = swstats->tda_err_cnt;
6569 tmp_stats[i++] = swstats->pfc_err_cnt;
6570 tmp_stats[i++] = swstats->pcc_err_cnt;
6571 tmp_stats[i++] = swstats->tti_err_cnt;
6572 tmp_stats[i++] = swstats->tpa_err_cnt;
6573 tmp_stats[i++] = swstats->sm_err_cnt;
6574 tmp_stats[i++] = swstats->lso_err_cnt;
6575 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6576 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6577 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6578 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6579 tmp_stats[i++] = swstats->rc_err_cnt;
6580 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6581 tmp_stats[i++] = swstats->rpa_err_cnt;
6582 tmp_stats[i++] = swstats->rda_err_cnt;
6583 tmp_stats[i++] = swstats->rti_err_cnt;
6584 tmp_stats[i++] = swstats->mc_err_cnt;
1da177e4
LT		 6585}
6586
ac1f60db 6587static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4 6588{
d44570e4 6589 return XENA_REG_SPACE;
1da177e4
LT		 6590}
6591
6592
d44570e4 6593static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
1da177e4 6594{
4cf1653a 6595 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 6596
d44570e4 6597 return sp->rx_csum;
1da177e4 6598}
ac1f60db
AB		 6599
6600static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6601{
4cf1653a 6602 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6603
6604 if (data)
6605 sp->rx_csum = 1;
6606 else
6607 sp->rx_csum = 0;
6608
6609 return 0;
6610}
ac1f60db
AB		 6611
6612static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4 6613{
d44570e4 6614 return XENA_EEPROM_SPACE;
1da177e4
LT		 6615}
6616
b9f2c044 6617static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6618{
4cf1653a 6619 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6620
6621 switch (sset) {
6622 case ETH_SS_TEST:
6623 return S2IO_TEST_LEN;
6624 case ETH_SS_STATS:
d44570e4 6625 switch (sp->device_type) {
b9f2c044
JG		 6626 case XFRAME_I_DEVICE:
6627 return XFRAME_I_STAT_LEN;
6628 case XFRAME_II_DEVICE:
6629 return XFRAME_II_STAT_LEN;
6630 default:
6631 return 0;
6632 }
6633 default:
6634 return -EOPNOTSUPP;
6635 }
1da177e4 6636}
ac1f60db
AB		 6637
6638static void s2io_ethtool_get_strings(struct net_device *dev,
d44570e4 6639 u32 stringset, u8 *data)
1da177e4 6640{
fa1f0cb3 6641 int stat_size = 0;
4cf1653a 6642 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6643
1da177e4
LT		 6644 switch (stringset) {
6645 case ETH_SS_TEST:
6646 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6647 break;
6648 case ETH_SS_STATS:
fa1f0cb3 6649 stat_size = sizeof(ethtool_xena_stats_keys);
d44570e4
JP		 6650 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6651 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6652 memcpy(data + stat_size,
d44570e4
JP		 6653 &ethtool_enhanced_stats_keys,
6654 sizeof(ethtool_enhanced_stats_keys));
fa1f0cb3
SS		 6655 stat_size += sizeof(ethtool_enhanced_stats_keys);
6656 }
6657
6658 memcpy(data + stat_size, &ethtool_driver_stats_keys,
d44570e4 6659 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6660 }
6661}
1da177e4 6662
ac1f60db 6663static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6664{
6665 if (data)
6666 dev->features |= NETIF_F_IP_CSUM;
6667 else
6668 dev->features &= ~NETIF_F_IP_CSUM;
6669
6670 return 0;
6671}
6672
75c30b13
AR		 6673static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6674{
6675 return (dev->features & NETIF_F_TSO) != 0;
6676}
958de193 6677
75c30b13
AR		 6678static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6679{
6680 if (data)
6681 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6682 else
6683 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6684
6685 return 0;
6686}
1da177e4 6687
958de193
JM		 6688static int s2io_ethtool_set_flags(struct net_device *dev, u32 data)
6689{
6690 struct s2io_nic *sp = netdev_priv(dev);
6691 int rc = 0;
6692 int changed = 0;
6693
6694 if (data & ~ETH_FLAG_LRO)
6695 return -EOPNOTSUPP;
6696
6697 if (data & ETH_FLAG_LRO) {
6698 if (lro_enable) {
6699 if (!(dev->features & NETIF_F_LRO)) {
6700 dev->features |= NETIF_F_LRO;
6701 changed = 1;
6702 }
6703 } else
6704 rc = -EINVAL;
6705 } else if (dev->features & NETIF_F_LRO) {
6706 dev->features &= ~NETIF_F_LRO;
6707 changed = 1;
6708 }
6709
6710 if (changed && netif_running(dev)) {
6711 s2io_stop_all_tx_queue(sp);
6712 s2io_card_down(sp);
6713 sp->lro = !!(dev->features & NETIF_F_LRO);
6714 rc = s2io_card_up(sp);
6715 if (rc)
6716 s2io_reset(sp);
6717 else
6718 s2io_start_all_tx_queue(sp);
6719 }
6720
6721 return rc;
6722}
6723
7282d491 6724static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6725 .get_settings = s2io_ethtool_gset,
6726 .set_settings = s2io_ethtool_sset,
6727 .get_drvinfo = s2io_ethtool_gdrvinfo,
6728 .get_regs_len = s2io_ethtool_get_regs_len,
6729 .get_regs = s2io_ethtool_gregs,
6730 .get_link = ethtool_op_get_link,
6731 .get_eeprom_len = s2io_get_eeprom_len,
6732 .get_eeprom = s2io_ethtool_geeprom,
6733 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6734 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6735 .get_pauseparam = s2io_ethtool_getpause_data,
6736 .set_pauseparam = s2io_ethtool_setpause_data,
6737 .get_rx_csum = s2io_ethtool_get_rx_csum,
6738 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6739 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
958de193
JM		 6740 .set_flags = s2io_ethtool_set_flags,
6741 .get_flags = ethtool_op_get_flags,
1da177e4 6742 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6743 .get_tso = s2io_ethtool_op_get_tso,
6744 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6745 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6746 .self_test = s2io_ethtool_test,
6747 .get_strings = s2io_ethtool_get_strings,
6748 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6749 .get_ethtool_stats = s2io_get_ethtool_stats,
6750 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6751};
6752
6753/**
20346722 6754 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6755 * @dev : Device pointer.
6756 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6757 * a proprietary structure used to pass information to the driver.
6758 * @cmd : This is used to distinguish between the different commands that
6759 * can be passed to the IOCTL functions.
6760 * Description:
20346722
K		 6761 * Currently there are no special functionality supported in IOCTL, hence
6762 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6763 */
6764
ac1f60db 6765static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6766{
6767 return -EOPNOTSUPP;
6768}
6769
6770/**
6771 * s2io_change_mtu - entry point to change MTU size for the device.
6772 * @dev : device pointer.
6773 * @new_mtu : the new MTU size for the device.
6774 * Description: A driver entry point to change MTU size for the device.
6775 * Before changing the MTU the device must be stopped.
6776 * Return value:
6777 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6778 * file on failure.
6779 */
6780
ac1f60db 6781static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6782{
4cf1653a 6783 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6784 int ret = 0;
1da177e4
LT		 6785
6786 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
d44570e4 6787 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
1da177e4
LT		 6788 return -EPERM;
6789 }
6790
1da177e4 6791 dev->mtu = new_mtu;
d8892c6e 6792 if (netif_running(dev)) {
3a3d5756 6793 s2io_stop_all_tx_queue(sp);
e6a8fee2 6794 s2io_card_down(sp);
9f74ffde
SH		 6795 ret = s2io_card_up(sp);
6796 if (ret) {
d8892c6e 6797 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6798 __func__);
9f74ffde 6799 return ret;
d8892c6e 6800 }
3a3d5756 6801 s2io_wake_all_tx_queue(sp);
d8892c6e 6802 } else { /* Device is down */
1ee6dd77 6803 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6804 u64 val64 = new_mtu;
6805
6806 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6807 }
1da177e4 6808
9f74ffde 6809 return ret;
1da177e4
LT		 6810}
6811
1da177e4
LT		 6812/**
6813 * s2io_set_link - Set the LInk status
6814 * @data: long pointer to device private structue
6815 * Description: Sets the link status for the adapter
6816 */
6817
c4028958 6818static void s2io_set_link(struct work_struct *work)
1da177e4 6819{
d44570e4
JP		 6820 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6821 set_link_task);
1da177e4 6822 struct net_device *dev = nic->dev;
1ee6dd77 6823 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6824 register u64 val64;
6825 u16 subid;
6826
22747d6b
FR		 6827 rtnl_lock();
6828
6829 if (!netif_running(dev))
6830 goto out_unlock;
6831
92b84437 6832 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6833 /* The card is being reset, no point doing anything */
22747d6b 6834 goto out_unlock;
1da177e4
LT		 6835 }
6836
6837 subid = nic->pdev->subsystem_device;
a371a07d
K		 6838 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6839 /*
6840 * Allow a small delay for the NICs self initiated
6841 * cleanup to complete.
6842 */
6843 msleep(100);
6844 }
1da177e4
LT		 6845
6846 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6847 if (LINK_IS_UP(val64)) {
6848 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6849 if (verify_xena_quiescence(nic)) {
6850 val64 = readq(&bar0->adapter_control);
6851 val64 |= ADAPTER_CNTL_EN;
1da177e4 6852 writeq(val64, &bar0->adapter_control);
19a60522 6853 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
d44570e4 6854 nic->device_type, subid)) {
19a60522
SS		 6855 val64 = readq(&bar0->gpio_control);
6856 val64 |= GPIO_CTRL_GPIO_0;
6857 writeq(val64, &bar0->gpio_control);
6858 val64 = readq(&bar0->gpio_control);
6859 } else {
6860 val64 |= ADAPTER_LED_ON;
6861 writeq(val64, &bar0->adapter_control);
a371a07d 6862 }
f957bcf0 6863 nic->device_enabled_once = true;
19a60522 6864 } else {
9e39f7c5
JP		 6865 DBG_PRINT(ERR_DBG,
6866 "%s: Error: device is not Quiescent\n",
6867 dev->name);
3a3d5756 6868 s2io_stop_all_tx_queue(nic);
1da177e4 6869 }
19a60522 6870 }
92c48799
SS		 6871 val64 = readq(&bar0->adapter_control);
6872 val64 |= ADAPTER_LED_ON;
6873 writeq(val64, &bar0->adapter_control);
6874 s2io_link(nic, LINK_UP);
19a60522
SS		 6875 } else {
6876 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6877 subid)) {
6878 val64 = readq(&bar0->gpio_control);
6879 val64 &= ~GPIO_CTRL_GPIO_0;
6880 writeq(val64, &bar0->gpio_control);
6881 val64 = readq(&bar0->gpio_control);
1da177e4 6882 }
92c48799
SS		 6883 /* turn off LED */
6884 val64 = readq(&bar0->adapter_control);
d44570e4 6885 val64 = val64 & (~ADAPTER_LED_ON);
92c48799 6886 writeq(val64, &bar0->adapter_control);
19a60522 6887 s2io_link(nic, LINK_DOWN);
1da177e4 6888 }
92b84437 6889 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6890
6891out_unlock:
d8d70caf 6892 rtnl_unlock();
1da177e4
LT		 6893}
6894
1ee6dd77 6895static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
d44570e4
JP		 6896 struct buffAdd *ba,
6897 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6898 u64 *temp2, int size)
5d3213cc
AR		 6899{
6900 struct net_device *dev = sp->dev;
491abf25 6901 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6902
6903 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6904 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6905 /* allocate skb */
6906 if (*skb) {
6907 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6908 /*
6909 * As Rx frame are not going to be processed,
6910 * using same mapped address for the Rxd
6911 * buffer pointer
6912 */
6d517a27 6913 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6914 } else {
6915 *skb = dev_alloc_skb(size);
6916 if (!(*skb)) {
9e39f7c5
JP		 6917 DBG_PRINT(INFO_DBG,
6918 "%s: Out of memory to allocate %s\n",
6919 dev->name, "1 buf mode SKBs");
ffb5df6c 6920 stats->mem_alloc_fail_cnt++;
5d3213cc
AR		 6921 return -ENOMEM ;
6922 }
ffb5df6c 6923 stats->mem_allocated += (*skb)->truesize;
5d3213cc
AR		 6924 /* storing the mapped addr in a temp variable
6925 * such it will be used for next rxd whose
6926 * Host Control is NULL
6927 */
6d517a27 6928 rxdp1->Buffer0_ptr = *temp0 =
d44570e4
JP		 6929 pci_map_single(sp->pdev, (*skb)->data,
6930 size - NET_IP_ALIGN,
6931 PCI_DMA_FROMDEVICE);
8d8bb39b 6932 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6933 goto memalloc_failed;
5d3213cc
AR		 6934 rxdp->Host_Control = (unsigned long) (*skb);
6935 }
6936 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6937 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6938 /* Two buffer Mode */
6939 if (*skb) {
6d517a27
VP		 6940 rxdp3->Buffer2_ptr = *temp2;
6941 rxdp3->Buffer0_ptr = *temp0;
6942 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6943 } else {
6944 *skb = dev_alloc_skb(size);
2ceaac75 6945 if (!(*skb)) {
9e39f7c5
JP		 6946 DBG_PRINT(INFO_DBG,
6947 "%s: Out of memory to allocate %s\n",
6948 dev->name,
6949 "2 buf mode SKBs");
ffb5df6c 6950 stats->mem_alloc_fail_cnt++;
2ceaac75
DR		 6951 return -ENOMEM;
6952 }
ffb5df6c 6953 stats->mem_allocated += (*skb)->truesize;
6d517a27 6954 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6955 pci_map_single(sp->pdev, (*skb)->data,
6956 dev->mtu + 4,
6957 PCI_DMA_FROMDEVICE);
8d8bb39b 6958 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6959 goto memalloc_failed;
6d517a27 6960 rxdp3->Buffer0_ptr = *temp0 =
d44570e4
JP		 6961 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6962 PCI_DMA_FROMDEVICE);
8d8bb39b 6963 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6964 rxdp3->Buffer0_ptr)) {
6965 pci_unmap_single(sp->pdev,
6966 (dma_addr_t)rxdp3->Buffer2_ptr,
6967 dev->mtu + 4,
6968 PCI_DMA_FROMDEVICE);
491abf25
VP		 6969 goto memalloc_failed;
6970 }
5d3213cc
AR		 6971 rxdp->Host_Control = (unsigned long) (*skb);
6972
6973 /* Buffer-1 will be dummy buffer not used */
6d517a27 6974 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6975 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
d44570e4 6976 PCI_DMA_FROMDEVICE);
8d8bb39b 6977 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6978 rxdp3->Buffer1_ptr)) {
6979 pci_unmap_single(sp->pdev,
6980 (dma_addr_t)rxdp3->Buffer0_ptr,
6981 BUF0_LEN, PCI_DMA_FROMDEVICE);
6982 pci_unmap_single(sp->pdev,
6983 (dma_addr_t)rxdp3->Buffer2_ptr,
6984 dev->mtu + 4,
6985 PCI_DMA_FROMDEVICE);
491abf25
VP		 6986 goto memalloc_failed;
6987 }
5d3213cc
AR		 6988 }
6989 }
6990 return 0;
d44570e4
JP		 6991
6992memalloc_failed:
6993 stats->pci_map_fail_cnt++;
6994 stats->mem_freed += (*skb)->truesize;
6995 dev_kfree_skb(*skb);
6996 return -ENOMEM;
5d3213cc 6997}
491abf25 6998
1ee6dd77
RB		 6999static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
7000 int size)
5d3213cc
AR		 7001{
7002 struct net_device *dev = sp->dev;
7003 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4 7004 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
5d3213cc
AR		 7005 } else if (sp->rxd_mode == RXD_MODE_3B) {
7006 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
7007 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
d44570e4 7008 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
5d3213cc
AR		 7009 }
7010}
7011
1ee6dd77 7012static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 7013{
7014 int i, j, k, blk_cnt = 0, size;
5d3213cc 7015 struct config_param *config = &sp->config;
ffb5df6c 7016 struct mac_info *mac_control = &sp->mac_control;
5d3213cc 7017 struct net_device *dev = sp->dev;
1ee6dd77 7018 struct RxD_t *rxdp = NULL;
5d3213cc 7019 struct sk_buff *skb = NULL;
1ee6dd77 7020 struct buffAdd *ba = NULL;
5d3213cc
AR		 7021 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
7022
7023 /* Calculate the size based on ring mode */
7024 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7025 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7026 if (sp->rxd_mode == RXD_MODE_1)
7027 size += NET_IP_ALIGN;
7028 else if (sp->rxd_mode == RXD_MODE_3B)
7029 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 7030
7031 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7032 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7033 struct ring_info *ring = &mac_control->rings[i];
7034
d44570e4 7035 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
5d3213cc
AR		 7036
7037 for (j = 0; j < blk_cnt; j++) {
7038 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
d44570e4
JP		 7039 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7040 if (sp->rxd_mode == RXD_MODE_3B)
13d866a9 7041 ba = &ring->ba[j][k];
d44570e4
JP		 7042 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7043 (u64 *)&temp0_64,
7044 (u64 *)&temp1_64,
7045 (u64 *)&temp2_64,
7046 size) == -ENOMEM) {
ac1f90d6
SS		 7047 return 0;
7048 }
5d3213cc
AR		 7049
7050 set_rxd_buffer_size(sp, rxdp, size);
7051 wmb();
7052 /* flip the Ownership bit to Hardware */
7053 rxdp->Control_1 |= RXD_OWN_XENA;
7054 }
7055 }
7056 }
7057 return 0;
7058
7059}
7060
d44570e4 7061static int s2io_add_isr(struct s2io_nic *sp)
1da177e4 7062{
e6a8fee2 7063 int ret = 0;
c92ca04b 7064 struct net_device *dev = sp->dev;
e6a8fee2 7065 int err = 0;
1da177e4 7066
eaae7f72 7067 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7068 ret = s2io_enable_msi_x(sp);
7069 if (ret) {
7070 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7071 sp->config.intr_type = INTA;
20346722 7072 }
1da177e4 7073
d44570e4
JP		 7074 /*
7075 * Store the values of the MSIX table in
7076 * the struct s2io_nic structure
7077 */
e6a8fee2 7078 store_xmsi_data(sp);
c92ca04b 7079
e6a8fee2 7080 /* After proper initialization of H/W, register ISR */
eaae7f72 7081 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7082 int i, msix_rx_cnt = 0;
7083
f61e0a35
SH		 7084 for (i = 0; i < sp->num_entries; i++) {
7085 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7086 if (sp->s2io_entries[i].type ==
d44570e4 7087 MSIX_RING_TYPE) {
ac731ab6
SH		 7088 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7089 dev->name, i);
7090 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7091 s2io_msix_ring_handle,
7092 0,
7093 sp->desc[i],
7094 sp->s2io_entries[i].arg);
ac731ab6 7095 } else if (sp->s2io_entries[i].type ==
d44570e4 7096 MSIX_ALARM_TYPE) {
ac731ab6 7097 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
d44570e4 7098 dev->name, i);
ac731ab6 7099 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7100 s2io_msix_fifo_handle,
7101 0,
7102 sp->desc[i],
7103 sp->s2io_entries[i].arg);
ac731ab6 7104
fb6a825b 7105 }
ac731ab6
SH		 7106 /* if either data or addr is zero print it. */
7107 if (!(sp->msix_info[i].addr &&
d44570e4 7108 sp->msix_info[i].data)) {
ac731ab6 7109 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7110 "%s @Addr:0x%llx Data:0x%llx\n",
7111 sp->desc[i],
7112 (unsigned long long)
7113 sp->msix_info[i].addr,
7114 (unsigned long long)
7115 ntohl(sp->msix_info[i].data));
ac731ab6 7116 } else
fb6a825b 7117 msix_rx_cnt++;
ac731ab6
SH		 7118 if (err) {
7119 remove_msix_isr(sp);
7120
7121 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7122 "%s:MSI-X-%d registration "
7123 "failed\n", dev->name, i);
ac731ab6
SH		 7124
7125 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7126 "%s: Defaulting to INTA\n",
7127 dev->name);
ac731ab6
SH		 7128 sp->config.intr_type = INTA;
7129 break;
fb6a825b 7130 }
ac731ab6
SH		 7131 sp->s2io_entries[i].in_use =
7132 MSIX_REGISTERED_SUCCESS;
c92ca04b 7133 }
e6a8fee2 7134 }
18b2b7bd 7135 if (!err) {
6cef2b8e 7136 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
9e39f7c5
JP		 7137 DBG_PRINT(INFO_DBG,
7138 "MSI-X-TX entries enabled through alarm vector\n");
18b2b7bd 7139 }
e6a8fee2 7140 }
eaae7f72 7141 if (sp->config.intr_type == INTA) {
d44570e4
JP		 7142 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7143 sp->name, dev);
e6a8fee2
AR		 7144 if (err) {
7145 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7146 dev->name);
7147 return -1;
7148 }
7149 }
7150 return 0;
7151}
d44570e4
JP		 7152
7153static void s2io_rem_isr(struct s2io_nic *sp)
e6a8fee2 7154{
18b2b7bd
SH		 7155 if (sp->config.intr_type == MSI_X)
7156 remove_msix_isr(sp);
7157 else
7158 remove_inta_isr(sp);
e6a8fee2
AR		 7159}
7160
d44570e4 7161static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
e6a8fee2
AR		 7162{
7163 int cnt = 0;
1ee6dd77 7164 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7165 register u64 val64 = 0;
5f490c96
SH		 7166 struct config_param *config;
7167 config = &sp->config;
e6a8fee2 7168
9f74ffde
SH		 7169 if (!is_s2io_card_up(sp))
7170 return;
7171
e6a8fee2
AR		 7172 del_timer_sync(&sp->alarm_timer);
7173 /* If s2io_set_link task is executing, wait till it completes. */
d44570e4 7174 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
e6a8fee2 7175 msleep(50);
92b84437 7176 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7177
5f490c96 7178 /* Disable napi */
f61e0a35
SH		 7179 if (sp->config.napi) {
7180 int off = 0;
7181 if (config->intr_type == MSI_X) {
7182 for (; off < sp->config.rx_ring_num; off++)
7183 napi_disable(&sp->mac_control.rings[off].napi);
d44570e4 7184 }
f61e0a35
SH		 7185 else
7186 napi_disable(&sp->napi);
7187 }
5f490c96 7188
e6a8fee2 7189 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7190 if (do_io)
7191 stop_nic(sp);
e6a8fee2
AR		 7192
7193 s2io_rem_isr(sp);
1da177e4 7194
01e16faa
SH		 7195 /* stop the tx queue, indicate link down */
7196 s2io_link(sp, LINK_DOWN);
7197
1da177e4 7198 /* Check if the device is Quiescent and then Reset the NIC */
d44570e4 7199 while (do_io) {
5d3213cc
AR		 7200 /* As per the HW requirement we need to replenish the
7201 * receive buffer to avoid the ring bump. Since there is
7202 * no intention of processing the Rx frame at this pointwe are
7203 * just settting the ownership bit of rxd in Each Rx
7204 * ring to HW and set the appropriate buffer size
7205 * based on the ring mode
7206 */
7207 rxd_owner_bit_reset(sp);
7208
1da177e4 7209 val64 = readq(&bar0->adapter_status);
19a60522 7210 if (verify_xena_quiescence(sp)) {
d44570e4
JP		 7211 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7212 break;
1da177e4
LT		 7213 }
7214
7215 msleep(50);
7216 cnt++;
7217 if (cnt == 10) {
9e39f7c5
JP		 7218 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7219 "adapter status reads 0x%llx\n",
d44570e4 7220 (unsigned long long)val64);
1da177e4
LT		 7221 break;
7222 }
d796fdb7
LV		 7223 }
7224 if (do_io)
7225 s2io_reset(sp);
1da177e4 7226
7ba013ac 7227 /* Free all Tx buffers */
1da177e4 7228 free_tx_buffers(sp);
7ba013ac
K		 7229
7230 /* Free all Rx buffers */
1da177e4
LT		 7231 free_rx_buffers(sp);
7232
92b84437 7233 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7234}
7235
d44570e4 7236static void s2io_card_down(struct s2io_nic *sp)
d796fdb7
LV		 7237{
7238 do_s2io_card_down(sp, 1);
7239}
7240
d44570e4 7241static int s2io_card_up(struct s2io_nic *sp)
1da177e4 7242{
cc6e7c44 7243 int i, ret = 0;
1da177e4 7244 struct config_param *config;
ffb5df6c 7245 struct mac_info *mac_control;
d44570e4 7246 struct net_device *dev = (struct net_device *)sp->dev;
e6a8fee2 7247 u16 interruptible;
1da177e4
LT		 7248
7249 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7250 ret = init_nic(sp);
7251 if (ret != 0) {
1da177e4
LT		 7252 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7253 dev->name);
9f74ffde
SH		 7254 if (ret != -EIO)
7255 s2io_reset(sp);
7256 return ret;
1da177e4
LT		 7257 }
7258
20346722
K		 7259 /*
7260 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7261 * Rx ring and initializing buffers into 30 Rx blocks
7262 */
1da177e4 7263 config = &sp->config;
ffb5df6c 7264 mac_control = &sp->mac_control;
1da177e4
LT		 7265
7266 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7267 struct ring_info *ring = &mac_control->rings[i];
7268
7269 ring->mtu = dev->mtu;
958de193 7270 ring->lro = sp->lro;
13d866a9 7271 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7272 if (ret) {
1da177e4
LT		 7273 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7274 dev->name);
7275 s2io_reset(sp);
7276 free_rx_buffers(sp);
7277 return -ENOMEM;
7278 }
7279 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7280 ring->rx_bufs_left);
1da177e4 7281 }
5f490c96
SH		 7282
7283 /* Initialise napi */
f61e0a35 7284 if (config->napi) {
f61e0a35
SH		 7285 if (config->intr_type == MSI_X) {
7286 for (i = 0; i < sp->config.rx_ring_num; i++)
7287 napi_enable(&sp->mac_control.rings[i].napi);
7288 } else {
7289 napi_enable(&sp->napi);
7290 }
7291 }
5f490c96 7292
19a60522
SS		 7293 /* Maintain the state prior to the open */
7294 if (sp->promisc_flg)
7295 sp->promisc_flg = 0;
7296 if (sp->m_cast_flg) {
7297 sp->m_cast_flg = 0;
d44570e4 7298 sp->all_multi_pos = 0;
19a60522 7299 }
1da177e4
LT		 7300
7301 /* Setting its receive mode */
7302 s2io_set_multicast(dev);
7303
7d3d0439 7304 if (sp->lro) {
b41477f3 7305 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439 7306 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
d44570e4 7307 /* Check if we can use (if specified) user provided value */
7d3d0439
RA		 7308 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7309 sp->lro_max_aggr_per_sess = lro_max_pkts;
7310 }
7311
1da177e4
LT		 7312 /* Enable Rx Traffic and interrupts on the NIC */
7313 if (start_nic(sp)) {
7314 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7315 s2io_reset(sp);
e6a8fee2
AR		 7316 free_rx_buffers(sp);
7317 return -ENODEV;
7318 }
7319
7320 /* Add interrupt service routine */
7321 if (s2io_add_isr(sp) != 0) {
eaae7f72 7322 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7323 s2io_rem_isr(sp);
7324 s2io_reset(sp);
1da177e4
LT		 7325 free_rx_buffers(sp);
7326 return -ENODEV;
7327 }
7328
25fff88e
K		 7329 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7330
01e16faa
SH		 7331 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7332
e6a8fee2 7333 /* Enable select interrupts */
9caab458 7334 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7335 if (sp->config.intr_type != INTA) {
7336 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7337 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7338 } else {
e6a8fee2 7339 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7340 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7341 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7342 }
7343
1da177e4
LT		 7344 return 0;
7345}
7346
20346722 7347/**
1da177e4
LT		 7348 * s2io_restart_nic - Resets the NIC.
7349 * @data : long pointer to the device private structure
7350 * Description:
7351 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7352 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7353 * the run time of the watch dog routine which is run holding a
7354 * spin lock.
7355 */
7356
c4028958 7357static void s2io_restart_nic(struct work_struct *work)
1da177e4 7358{
1ee6dd77 7359 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7360 struct net_device *dev = sp->dev;
1da177e4 7361
22747d6b
FR		 7362 rtnl_lock();
7363
7364 if (!netif_running(dev))
7365 goto out_unlock;
7366
e6a8fee2 7367 s2io_card_down(sp);
1da177e4 7368 if (s2io_card_up(sp)) {
d44570e4 7369 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
1da177e4 7370 }
3a3d5756 7371 s2io_wake_all_tx_queue(sp);
d44570e4 7372 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
22747d6b
FR		 7373out_unlock:
7374 rtnl_unlock();
1da177e4
LT		 7375}
7376
20346722
K		 7377/**
7378 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7379 * @dev : Pointer to net device structure
7380 * Description:
7381 * This function is triggered if the Tx Queue is stopped
7382 * for a pre-defined amount of time when the Interface is still up.
7383 * If the Interface is jammed in such a situation, the hardware is
7384 * reset (by s2io_close) and restarted again (by s2io_open) to
7385 * overcome any problem that might have been caused in the hardware.
7386 * Return value:
7387 * void
7388 */
7389
7390static void s2io_tx_watchdog(struct net_device *dev)
7391{
4cf1653a 7392 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 7393 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7394
7395 if (netif_carrier_ok(dev)) {
ffb5df6c 7396 swstats->watchdog_timer_cnt++;
1da177e4 7397 schedule_work(&sp->rst_timer_task);
ffb5df6c 7398 swstats->soft_reset_cnt++;
1da177e4
LT		 7399 }
7400}
7401
7402/**
7403 * rx_osm_handler - To perform some OS related operations on SKB.
7404 * @sp: private member of the device structure,pointer to s2io_nic structure.
7405 * @skb : the socket buffer pointer.
7406 * @len : length of the packet
7407 * @cksum : FCS checksum of the frame.
7408 * @ring_no : the ring from which this RxD was extracted.
20346722 7409 * Description:
b41477f3 7410 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7411 * some OS related operations on the SKB before passing it to the upper
7412 * layers. It mainly checks if the checksum is OK, if so adds it to the
7413 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7414 * to the upper layer. If the checksum is wrong, it increments the Rx
7415 * packet error count, frees the SKB and returns error.
7416 * Return value:
7417 * SUCCESS on success and -1 on failure.
7418 */
1ee6dd77 7419static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7420{
1ee6dd77 7421 struct s2io_nic *sp = ring_data->nic;
d44570e4 7422 struct net_device *dev = (struct net_device *)ring_data->dev;
20346722 7423 struct sk_buff *skb = (struct sk_buff *)
d44570e4 7424 ((unsigned long)rxdp->Host_Control);
20346722 7425 int ring_no = ring_data->ring_no;
1da177e4 7426 u16 l3_csum, l4_csum;
863c11a9 7427 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7428 struct lro *uninitialized_var(lro);
f9046eb3 7429 u8 err_mask;
ffb5df6c 7430 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
da6971d8 7431
20346722 7432 skb->dev = dev;
c92ca04b 7433
863c11a9 7434 if (err) {
bd1034f0 7435 /* Check for parity error */
d44570e4 7436 if (err & 0x1)
ffb5df6c 7437 swstats->parity_err_cnt++;
d44570e4 7438
f9046eb3 7439 err_mask = err >> 48;
d44570e4
JP		 7440 switch (err_mask) {
7441 case 1:
ffb5df6c 7442 swstats->rx_parity_err_cnt++;
491976b2
SH		 7443 break;
7444
d44570e4 7445 case 2:
ffb5df6c 7446 swstats->rx_abort_cnt++;
491976b2
SH		 7447 break;
7448
d44570e4 7449 case 3:
ffb5df6c 7450 swstats->rx_parity_abort_cnt++;
491976b2
SH		 7451 break;
7452
d44570e4 7453 case 4:
ffb5df6c 7454 swstats->rx_rda_fail_cnt++;
491976b2
SH		 7455 break;
7456
d44570e4 7457 case 5:
ffb5df6c 7458 swstats->rx_unkn_prot_cnt++;
491976b2
SH		 7459 break;
7460
d44570e4 7461 case 6:
ffb5df6c 7462 swstats->rx_fcs_err_cnt++;
491976b2 7463 break;
bd1034f0 7464
d44570e4 7465 case 7:
ffb5df6c 7466 swstats->rx_buf_size_err_cnt++;
491976b2
SH		 7467 break;
7468
d44570e4 7469 case 8:
ffb5df6c 7470 swstats->rx_rxd_corrupt_cnt++;
491976b2
SH		 7471 break;
7472
d44570e4 7473 case 15:
ffb5df6c 7474 swstats->rx_unkn_err_cnt++;
491976b2
SH		 7475 break;
7476 }
863c11a9 7477 /*
d44570e4
JP		 7478 * Drop the packet if bad transfer code. Exception being
7479 * 0x5, which could be due to unsupported IPv6 extension header.
7480 * In this case, we let stack handle the packet.
7481 * Note that in this case, since checksum will be incorrect,
7482 * stack will validate the same.
7483 */
f9046eb3
OH		 7484 if (err_mask != 0x5) {
7485 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
d44570e4 7486 dev->name, err_mask);
dc56e634 7487 dev->stats.rx_crc_errors++;
ffb5df6c 7488 swstats->mem_freed
491976b2 7489 += skb->truesize;
863c11a9 7490 dev_kfree_skb(skb);
0425b46a 7491 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7492 rxdp->Host_Control = 0;
7493 return 0;
7494 }
20346722 7495 }
1da177e4 7496
20346722 7497 /* Updating statistics */
0425b46a 7498 ring_data->rx_packets++;
20346722 7499 rxdp->Host_Control = 0;
da6971d8
AR		 7500 if (sp->rxd_mode == RXD_MODE_1) {
7501 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7502
0425b46a 7503 ring_data->rx_bytes += len;
da6971d8
AR		 7504 skb_put(skb, len);
7505
6d517a27 7506 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7507 int get_block = ring_data->rx_curr_get_info.block_index;
7508 int get_off = ring_data->rx_curr_get_info.offset;
7509 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7510 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7511 unsigned char *buff = skb_push(skb, buf0_len);
7512
1ee6dd77 7513 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
0425b46a 7514 ring_data->rx_bytes += buf0_len + buf2_len;
da6971d8 7515 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7516 skb_put(skb, buf2_len);
da6971d8 7517 }
20346722 7518
d44570e4
JP		 7519 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7520 ((!ring_data->lro) ||
7521 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 7522 (sp->rx_csum)) {
7523 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7524 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7525 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7526 /*
1da177e4
LT		 7527 * NIC verifies if the Checksum of the received
7528 * frame is Ok or not and accordingly returns
7529 * a flag in the RxD.
7530 */
7531 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7532 if (ring_data->lro) {
7d3d0439
RA		 7533 u32 tcp_len;
7534 u8 *tcp;
7535 int ret = 0;
7536
0425b46a 7537 ret = s2io_club_tcp_session(ring_data,
d44570e4
JP		 7538 skb->data, &tcp,
7539 &tcp_len, &lro,
7540 rxdp, sp);
7d3d0439 7541 switch (ret) {
d44570e4
JP		 7542 case 3: /* Begin anew */
7543 lro->parent = skb;
7544 goto aggregate;
7545 case 1: /* Aggregate */
7546 lro_append_pkt(sp, lro, skb, tcp_len);
7547 goto aggregate;
7548 case 4: /* Flush session */
7549 lro_append_pkt(sp, lro, skb, tcp_len);
7550 queue_rx_frame(lro->parent,
7551 lro->vlan_tag);
7552 clear_lro_session(lro);
ffb5df6c 7553 swstats->flush_max_pkts++;
d44570e4
JP		 7554 goto aggregate;
7555 case 2: /* Flush both */
7556 lro->parent->data_len = lro->frags_len;
ffb5df6c 7557 swstats->sending_both++;
d44570e4
JP		 7558 queue_rx_frame(lro->parent,
7559 lro->vlan_tag);
7560 clear_lro_session(lro);
7561 goto send_up;
7562 case 0: /* sessions exceeded */
7563 case -1: /* non-TCP or not L2 aggregatable */
7564 case 5: /*
7565 * First pkt in session not
7566 * L3/L4 aggregatable
7567 */
7568 break;
7569 default:
7570 DBG_PRINT(ERR_DBG,
7571 "%s: Samadhana!!\n",
7572 __func__);
7573 BUG();
7d3d0439
RA		 7574 }
7575 }
1da177e4 7576 } else {
20346722
K		 7577 /*
7578 * Packet with erroneous checksum, let the
1da177e4
LT		 7579 * upper layers deal with it.
7580 */
7581 skb->ip_summed = CHECKSUM_NONE;
7582 }
cdb5bf02 7583 } else
1da177e4 7584 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7585
ffb5df6c 7586 swstats->mem_freed += skb->truesize;
7d3d0439 7587send_up:
0c8dfc83 7588 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7589 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7590aggregate:
0425b46a 7591 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7592 return SUCCESS;
7593}
7594
7595/**
7596 * s2io_link - stops/starts the Tx queue.
7597 * @sp : private member of the device structure, which is a pointer to the
7598 * s2io_nic structure.
7599 * @link : inidicates whether link is UP/DOWN.
7600 * Description:
7601 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7602 * status of the NIC is is down or up. This is called by the Alarm
7603 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7604 * Return value:
7605 * void.
7606 */
7607
d44570e4 7608static void s2io_link(struct s2io_nic *sp, int link)
1da177e4 7609{
d44570e4 7610 struct net_device *dev = (struct net_device *)sp->dev;
ffb5df6c 7611 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7612
7613 if (link != sp->last_link_state) {
b7c5678f 7614 init_tti(sp, link);
1da177e4
LT		 7615 if (link == LINK_DOWN) {
7616 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7617 s2io_stop_all_tx_queue(sp);
1da177e4 7618 netif_carrier_off(dev);
ffb5df6c
JP		 7619 if (swstats->link_up_cnt)
7620 swstats->link_up_time =
7621 jiffies - sp->start_time;
7622 swstats->link_down_cnt++;
1da177e4
LT		 7623 } else {
7624 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
ffb5df6c
JP		 7625 if (swstats->link_down_cnt)
7626 swstats->link_down_time =
d44570e4 7627 jiffies - sp->start_time;
ffb5df6c 7628 swstats->link_up_cnt++;
1da177e4 7629 netif_carrier_on(dev);
3a3d5756 7630 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7631 }
7632 }
7633 sp->last_link_state = link;
491976b2 7634 sp->start_time = jiffies;
1da177e4
LT		 7635}
7636
20346722
K		 7637/**
7638 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7639 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7640 * s2io_nic structure.
7641 * Description:
7642 * This function initializes a few of the PCI and PCI-X configuration registers
7643 * with recommended values.
7644 * Return value:
7645 * void
7646 */
7647
d44570e4 7648static void s2io_init_pci(struct s2io_nic *sp)
1da177e4 7649{
20346722 7650 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7651
7652 /* Enable Data Parity Error Recovery in PCI-X command register. */
7653 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7654 &(pcix_cmd));
1da177e4 7655 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7656 (pcix_cmd | 1));
1da177e4 7657 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7658 &(pcix_cmd));
1da177e4
LT		 7659
7660 /* Set the PErr Response bit in PCI command register. */
7661 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7662 pci_write_config_word(sp->pdev, PCI_COMMAND,
7663 (pci_cmd | PCI_COMMAND_PARITY));
7664 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7665}
7666
3a3d5756 7667static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
d44570e4 7668 u8 *dev_multiq)
9dc737a7 7669{
d44570e4 7670 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
9e39f7c5 7671 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
d44570e4 7672 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7673
7674 if (tx_fifo_num < 1)
7675 tx_fifo_num = 1;
7676 else
7677 tx_fifo_num = MAX_TX_FIFOS;
7678
9e39f7c5 7679 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
9dc737a7 7680 }
2fda096d 7681
6cfc482b 7682 if (multiq)
3a3d5756 7683 *dev_multiq = multiq;
6cfc482b
SH		 7684
7685 if (tx_steering_type && (1 == tx_fifo_num)) {
7686 if (tx_steering_type != TX_DEFAULT_STEERING)
7687 DBG_PRINT(ERR_DBG,
9e39f7c5 7688 "Tx steering is not supported with "
d44570e4 7689 "one fifo. Disabling Tx steering.\n");
6cfc482b
SH		 7690 tx_steering_type = NO_STEERING;
7691 }
7692
7693 if ((tx_steering_type < NO_STEERING) ||
d44570e4
JP		 7694 (tx_steering_type > TX_DEFAULT_STEERING)) {
7695 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7696 "Requested transmit steering not supported\n");
7697 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
6cfc482b 7698 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7699 }
7700
0425b46a 7701 if (rx_ring_num > MAX_RX_RINGS) {
d44570e4 7702 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7703 "Requested number of rx rings not supported\n");
7704 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
d44570e4 7705 MAX_RX_RINGS);
0425b46a 7706 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7707 }
0425b46a 7708
eccb8628 7709 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9e39f7c5 7710 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
9dc737a7
AR		 7711 "Defaulting to INTA\n");
7712 *dev_intr_type = INTA;
7713 }
596c5c97 7714
9dc737a7 7715 if ((*dev_intr_type == MSI_X) &&
d44570e4
JP		 7716 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7717 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
9e39f7c5 7718 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
d44570e4 7719 "Defaulting to INTA\n");
9dc737a7
AR		 7720 *dev_intr_type = INTA;
7721 }
fb6a825b 7722
6d517a27 7723 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9e39f7c5
JP		 7724 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7725 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
6d517a27 7726 rx_ring_mode = 1;
9dc737a7
AR		 7727 }
7728 return SUCCESS;
7729}
7730
9fc93a41
SS		 7731/**
7732 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7733 * or Traffic class respectively.
b7c5678f 7734 * @nic: device private variable
9fc93a41
SS		 7735 * Description: The function configures the receive steering to
7736 * desired receive ring.
7737 * Return Value: SUCCESS on success and
7738 * '-1' on failure (endian settings incorrect).
7739 */
7740static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7741{
7742 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7743 register u64 val64 = 0;
7744
7745 if (ds_codepoint > 63)
7746 return FAILURE;
7747
7748 val64 = RTS_DS_MEM_DATA(ring);
7749 writeq(val64, &bar0->rts_ds_mem_data);
7750
7751 val64 = RTS_DS_MEM_CTRL_WE |
7752 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7753 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7754
7755 writeq(val64, &bar0->rts_ds_mem_ctrl);
7756
7757 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
d44570e4
JP		 7758 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7759 S2IO_BIT_RESET);
9fc93a41
SS		 7760}
7761
04025095
SH		 7762static const struct net_device_ops s2io_netdev_ops = {
7763 .ndo_open = s2io_open,
7764 .ndo_stop = s2io_close,
7765 .ndo_get_stats = s2io_get_stats,
7766 .ndo_start_xmit = s2io_xmit,
7767 .ndo_validate_addr = eth_validate_addr,
7768 .ndo_set_multicast_list = s2io_set_multicast,
7769 .ndo_do_ioctl = s2io_ioctl,
7770 .ndo_set_mac_address = s2io_set_mac_addr,
7771 .ndo_change_mtu = s2io_change_mtu,
7772 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7773 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7774 .ndo_tx_timeout = s2io_tx_watchdog,
7775#ifdef CONFIG_NET_POLL_CONTROLLER
7776 .ndo_poll_controller = s2io_netpoll,
7777#endif
7778};
7779
1da177e4 7780/**
20346722 7781 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7782 * @pdev : structure containing the PCI related information of the device.
7783 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7784 * Description:
7785 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7786 * All OS related initialization including memory and device structure and
7787 * initlaization of the device private variable is done. Also the swapper
7788 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7789 * registers of the device.
7790 * Return value:
7791 * returns 0 on success and negative on failure.
7792 */
7793
7794static int __devinit
7795s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7796{
1ee6dd77 7797 struct s2io_nic *sp;
1da177e4 7798 struct net_device *dev;
1da177e4 7799 int i, j, ret;
f957bcf0 7800 int dma_flag = false;
1da177e4
LT		 7801 u32 mac_up, mac_down;
7802 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7803 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7804 u16 subid;
1da177e4 7805 struct config_param *config;
ffb5df6c 7806 struct mac_info *mac_control;
541ae68f 7807 int mode;
cc6e7c44 7808 u8 dev_intr_type = intr_type;
3a3d5756 7809 u8 dev_multiq = 0;
1da177e4 7810
3a3d5756
SH		 7811 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7812 if (ret)
9dc737a7 7813 return ret;
1da177e4 7814
d44570e4
JP		 7815 ret = pci_enable_device(pdev);
7816 if (ret) {
1da177e4 7817 DBG_PRINT(ERR_DBG,
9e39f7c5 7818 "%s: pci_enable_device failed\n", __func__);
1da177e4
LT		 7819 return ret;
7820 }
7821
6a35528a 7822 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
9e39f7c5 7823 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
f957bcf0 7824 dma_flag = true;
d44570e4 7825 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7826 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7827 "Unable to obtain 64bit DMA "
7828 "for consistent allocations\n");
1da177e4
LT		 7829 pci_disable_device(pdev);
7830 return -ENOMEM;
7831 }
284901a9 7832 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
9e39f7c5 7833 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
1da177e4
LT		 7834 } else {
7835 pci_disable_device(pdev);
7836 return -ENOMEM;
7837 }
d44570e4
JP		 7838 ret = pci_request_regions(pdev, s2io_driver_name);
7839 if (ret) {
9e39f7c5 7840 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
d44570e4 7841 __func__, ret);
eccb8628
VP		 7842 pci_disable_device(pdev);
7843 return -ENODEV;
1da177e4 7844 }
3a3d5756 7845 if (dev_multiq)
6cfc482b 7846 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7847 else
b19fa1fa 7848 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7849 if (dev == NULL) {
7850 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7851 pci_disable_device(pdev);
7852 pci_release_regions(pdev);
7853 return -ENODEV;
7854 }
7855
7856 pci_set_master(pdev);
7857 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7858 SET_NETDEV_DEV(dev, &pdev->dev);
7859
7860 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7861 sp = netdev_priv(dev);
1ee6dd77 7862 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7863 sp->dev = dev;
7864 sp->pdev = pdev;
1da177e4 7865 sp->high_dma_flag = dma_flag;
f957bcf0 7866 sp->device_enabled_once = false;
da6971d8
AR		 7867 if (rx_ring_mode == 1)
7868 sp->rxd_mode = RXD_MODE_1;
7869 if (rx_ring_mode == 2)
7870 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7871
eaae7f72 7872 sp->config.intr_type = dev_intr_type;
1da177e4 7873
541ae68f 7874 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
d44570e4 7875 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
541ae68f
K		 7876 sp->device_type = XFRAME_II_DEVICE;
7877 else
7878 sp->device_type = XFRAME_I_DEVICE;
7879
43b7c451 7880 sp->lro = lro_enable;
6aa20a22 7881
1da177e4
LT		 7882 /* Initialize some PCI/PCI-X fields of the NIC. */
7883 s2io_init_pci(sp);
7884
20346722 7885 /*
1da177e4 7886 * Setting the device configuration parameters.
20346722
K		 7887 * Most of these parameters can be specified by the user during
7888 * module insertion as they are module loadable parameters. If
7889 * these parameters are not not specified during load time, they
1da177e4
LT		 7890 * are initialized with default values.
7891 */
1da177e4 7892 config = &sp->config;
ffb5df6c 7893 mac_control = &sp->mac_control;
1da177e4 7894
596c5c97 7895 config->napi = napi;
6cfc482b 7896 config->tx_steering_type = tx_steering_type;
596c5c97 7897
1da177e4 7898 /* Tx side parameters. */
6cfc482b
SH		 7899 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7900 config->tx_fifo_num = MAX_TX_FIFOS;
7901 else
7902 config->tx_fifo_num = tx_fifo_num;
7903
7904 /* Initialize the fifos used for tx steering */
7905 if (config->tx_fifo_num < 5) {
d44570e4
JP		 7906 if (config->tx_fifo_num == 1)
7907 sp->total_tcp_fifos = 1;
7908 else
7909 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7910 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7911 sp->total_udp_fifos = 1;
7912 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
6cfc482b
SH		 7913 } else {
7914 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
d44570e4 7915 FIFO_OTHER_MAX_NUM);
6cfc482b
SH		 7916 sp->udp_fifo_idx = sp->total_tcp_fifos;
7917 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7918 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7919 }
7920
3a3d5756 7921 config->multiq = dev_multiq;
6cfc482b 7922 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7923 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7924
7925 tx_cfg->fifo_len = tx_fifo_len[i];
7926 tx_cfg->fifo_priority = i;
1da177e4
LT		 7927 }
7928
20346722
K		 7929 /* mapping the QoS priority to the configured fifos */
7930 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7931 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7932
6cfc482b
SH		 7933 /* map the hashing selector table to the configured fifos */
7934 for (i = 0; i < config->tx_fifo_num; i++)
7935 sp->fifo_selector[i] = fifo_selector[i];
7936
7937
1da177e4
LT		 7938 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7939 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7940 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7941
7942 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7943 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7944 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7945 break;
7946 }
7947 }
fed5eccd
AR		 7948 /* + 2 because one Txd for skb->data and one Txd for UFO */
7949 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7950
7951 /* Rx side parameters. */
1da177e4 7952 config->rx_ring_num = rx_ring_num;
0425b46a 7953 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7954 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7955 struct ring_info *ring = &mac_control->rings[i];
7956
7957 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7958 rx_cfg->ring_priority = i;
7959 ring->rx_bufs_left = 0;
7960 ring->rxd_mode = sp->rxd_mode;
7961 ring->rxd_count = rxd_count[sp->rxd_mode];
7962 ring->pdev = sp->pdev;
7963 ring->dev = sp->dev;
1da177e4
LT		 7964 }
7965
7966 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7967 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7968
7969 rx_cfg->ring_org = RING_ORG_BUFF1;
7970 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7971 }
7972
7973 /* Setting Mac Control parameters */
7974 mac_control->rmac_pause_time = rmac_pause_time;
7975 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7976 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7977
7978
1da177e4
LT		 7979 /* initialize the shared memory used by the NIC and the host */
7980 if (init_shared_mem(sp)) {
d44570e4 7981 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
1da177e4
LT		 7982 ret = -ENOMEM;
7983 goto mem_alloc_failed;
7984 }
7985
275f165f 7986 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7987 if (!sp->bar0) {
19a60522 7988 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7989 dev->name);
7990 ret = -ENOMEM;
7991 goto bar0_remap_failed;
7992 }
7993
275f165f 7994 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7995 if (!sp->bar1) {
19a60522 7996 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7997 dev->name);
7998 ret = -ENOMEM;
7999 goto bar1_remap_failed;
8000 }
8001
8002 dev->irq = pdev->irq;
d44570e4 8003 dev->base_addr = (unsigned long)sp->bar0;
1da177e4
LT		 8004
8005 /* Initializing the BAR1 address as the start of the FIFO pointer. */
8006 for (j = 0; j < MAX_TX_FIFOS; j++) {
d44570e4
JP		 8007 mac_control->tx_FIFO_start[j] =
8008 (struct TxFIFO_element __iomem *)
8009 (sp->bar1 + (j * 0x00020000));
1da177e4
LT		 8010 }
8011
8012 /* Driver entry points */
04025095 8013 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 8014 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 8015 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
958de193
JM		 8016 if (lro_enable)
8017 dev->features |= NETIF_F_LRO;
1da177e4 8018 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f957bcf0 8019 if (sp->high_dma_flag == true)
1da177e4 8020 dev->features |= NETIF_F_HIGHDMA;
1da177e4 8021 dev->features |= NETIF_F_TSO;
f83ef8c0 8022 dev->features |= NETIF_F_TSO6;
db874e65 8023 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 8024 dev->features |= NETIF_F_UFO;
8025 dev->features |= NETIF_F_HW_CSUM;
8026 }
1da177e4 8027 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 8028 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8029 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 8030
e960fc5c 8031 pci_save_state(sp->pdev);
1da177e4
LT		 8032
8033 /* Setting swapper control on the NIC, for proper reset operation */
8034 if (s2io_set_swapper(sp)) {
9e39f7c5 8035 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
1da177e4
LT		 8036 dev->name);
8037 ret = -EAGAIN;
8038 goto set_swap_failed;
8039 }
8040
541ae68f
K		 8041 /* Verify if the Herc works on the slot its placed into */
8042 if (sp->device_type & XFRAME_II_DEVICE) {
8043 mode = s2io_verify_pci_mode(sp);
8044 if (mode < 0) {
9e39f7c5
JP		 8045 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8046 __func__);
541ae68f
K		 8047 ret = -EBADSLT;
8048 goto set_swap_failed;
8049 }
8050 }
8051
f61e0a35
SH		 8052 if (sp->config.intr_type == MSI_X) {
8053 sp->num_entries = config->rx_ring_num + 1;
8054 ret = s2io_enable_msi_x(sp);
8055
8056 if (!ret) {
8057 ret = s2io_test_msi(sp);
8058 /* rollback MSI-X, will re-enable during add_isr() */
8059 remove_msix_isr(sp);
8060 }
8061 if (ret) {
8062
8063 DBG_PRINT(ERR_DBG,
9e39f7c5 8064 "MSI-X requested but failed to enable\n");
f61e0a35
SH		 8065 sp->config.intr_type = INTA;
8066 }
8067 }
8068
8069 if (config->intr_type == MSI_X) {
13d866a9
JP		 8070 for (i = 0; i < config->rx_ring_num ; i++) {
8071 struct ring_info *ring = &mac_control->rings[i];
8072
8073 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8074 }
f61e0a35
SH		 8075 } else {
8076 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8077 }
8078
541ae68f
K		 8079 /* Not needed for Herc */
8080 if (sp->device_type & XFRAME_I_DEVICE) {
8081 /*
8082 * Fix for all "FFs" MAC address problems observed on
8083 * Alpha platforms
8084 */
8085 fix_mac_address(sp);
8086 s2io_reset(sp);
8087 }
1da177e4
LT		 8088
8089 /*
1da177e4
LT		 8090 * MAC address initialization.
8091 * For now only one mac address will be read and used.
8092 */
8093 bar0 = sp->bar0;
8094 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
d44570e4 8095 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8096 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8097 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 8098 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8099 S2IO_BIT_RESET);
1da177e4 8100 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4 8101 mac_down = (u32)tmp64;
1da177e4
LT		 8102 mac_up = (u32) (tmp64 >> 32);
8103
1da177e4
LT		 8104 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8105 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8106 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8107 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8108 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8109 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8110
1da177e4
LT		 8111 /* Set the factory defined MAC address initially */
8112 dev->addr_len = ETH_ALEN;
8113 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8114 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8115
faa4f796
SH		 8116 /* initialize number of multicast & unicast MAC entries variables */
8117 if (sp->device_type == XFRAME_I_DEVICE) {
8118 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8119 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8120 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8121 } else if (sp->device_type == XFRAME_II_DEVICE) {
8122 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8123 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8124 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8125 }
8126
8127 /* store mac addresses from CAM to s2io_nic structure */
8128 do_s2io_store_unicast_mc(sp);
8129
f61e0a35
SH		 8130 /* Configure MSIX vector for number of rings configured plus one */
8131 if ((sp->device_type == XFRAME_II_DEVICE) &&
d44570e4 8132 (config->intr_type == MSI_X))
f61e0a35
SH		 8133 sp->num_entries = config->rx_ring_num + 1;
8134
d44570e4 8135 /* Store the values of the MSIX table in the s2io_nic structure */
c77dd43e 8136 store_xmsi_data(sp);
b41477f3
AR		 8137 /* reset Nic and bring it to known state */
8138 s2io_reset(sp);
8139
1da177e4 8140 /*
99993af6 8141 * Initialize link state flags
541ae68f 8142 * and the card state parameter
1da177e4 8143 */
92b84437 8144 sp->state = 0;
1da177e4 8145
1da177e4 8146 /* Initialize spinlocks */
13d866a9
JP		 8147 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8148 struct fifo_info *fifo = &mac_control->fifos[i];
8149
8150 spin_lock_init(&fifo->tx_lock);
8151 }
db874e65 8152
20346722
K		 8153 /*
8154 * SXE-002: Configure link and activity LED to init state
8155 * on driver load.
1da177e4
LT		 8156 */
8157 subid = sp->pdev->subsystem_device;
8158 if ((subid & 0xFF) >= 0x07) {
8159 val64 = readq(&bar0->gpio_control);
8160 val64 |= 0x0000800000000000ULL;
8161 writeq(val64, &bar0->gpio_control);
8162 val64 = 0x0411040400000000ULL;
d44570e4 8163 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 8164 val64 = readq(&bar0->gpio_control);
8165 }
8166
8167 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8168
8169 if (register_netdev(dev)) {
8170 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8171 ret = -ENODEV;
8172 goto register_failed;
8173 }
9dc737a7 8174 s2io_vpd_read(sp);
0c61ed5f 8175 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
d44570e4 8176 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
44c10138 8177 sp->product_name, pdev->revision);
b41477f3
AR		 8178 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8179 s2io_driver_version);
9e39f7c5
JP		 8180 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8181 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
9dc737a7 8182 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8183 mode = s2io_print_pci_mode(sp);
541ae68f 8184 if (mode < 0) {
541ae68f 8185 ret = -EBADSLT;
9dc737a7 8186 unregister_netdev(dev);
541ae68f
K		 8187 goto set_swap_failed;
8188 }
541ae68f 8189 }
d44570e4
JP		 8190 switch (sp->rxd_mode) {
8191 case RXD_MODE_1:
8192 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8193 dev->name);
8194 break;
8195 case RXD_MODE_3B:
8196 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8197 dev->name);
8198 break;
9dc737a7 8199 }
db874e65 8200
f61e0a35
SH		 8201 switch (sp->config.napi) {
8202 case 0:
8203 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8204 break;
8205 case 1:
db874e65 8206 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8207 break;
8208 }
3a3d5756
SH		 8209
8210 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
d44570e4 8211 sp->config.tx_fifo_num);
3a3d5756 8212
0425b46a
SH		 8213 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8214 sp->config.rx_ring_num);
8215
d44570e4
JP		 8216 switch (sp->config.intr_type) {
8217 case INTA:
8218 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8219 break;
8220 case MSI_X:
8221 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8222 break;
9dc737a7 8223 }
3a3d5756 8224 if (sp->config.multiq) {
13d866a9
JP		 8225 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8226 struct fifo_info *fifo = &mac_control->fifos[i];
8227
8228 fifo->multiq = config->multiq;
8229 }
3a3d5756 8230 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
d44570e4 8231 dev->name);
3a3d5756
SH		 8232 } else
8233 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
d44570e4 8234 dev->name);
3a3d5756 8235
6cfc482b
SH		 8236 switch (sp->config.tx_steering_type) {
8237 case NO_STEERING:
d44570e4
JP		 8238 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8239 dev->name);
8240 break;
6cfc482b 8241 case TX_PRIORITY_STEERING:
d44570e4
JP		 8242 DBG_PRINT(ERR_DBG,
8243 "%s: Priority steering enabled for transmit\n",
8244 dev->name);
6cfc482b
SH		 8245 break;
8246 case TX_DEFAULT_STEERING:
d44570e4
JP		 8247 DBG_PRINT(ERR_DBG,
8248 "%s: Default steering enabled for transmit\n",
8249 dev->name);
6cfc482b
SH		 8250 }
8251
7d3d0439
RA		 8252 if (sp->lro)
8253 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8254 dev->name);
db874e65 8255 if (ufo)
d44570e4
JP		 8256 DBG_PRINT(ERR_DBG,
8257 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8258 dev->name);
7ba013ac 8259 /* Initialize device name */
9dc737a7 8260 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8261
cd0fce03
BL		 8262 if (vlan_tag_strip)
8263 sp->vlan_strip_flag = 1;
8264 else
8265 sp->vlan_strip_flag = 0;
8266
20346722
K		 8267 /*
8268 * Make Link state as off at this point, when the Link change
8269 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8270 * the right state.
8271 */
8272 netif_carrier_off(dev);
1da177e4
LT		 8273
8274 return 0;
8275
d44570e4
JP		 8276register_failed:
8277set_swap_failed:
1da177e4 8278 iounmap(sp->bar1);
d44570e4 8279bar1_remap_failed:
1da177e4 8280 iounmap(sp->bar0);
d44570e4
JP		 8281bar0_remap_failed:
8282mem_alloc_failed:
1da177e4
LT		 8283 free_shared_mem(sp);
8284 pci_disable_device(pdev);
eccb8628 8285 pci_release_regions(pdev);
1da177e4
LT		 8286 pci_set_drvdata(pdev, NULL);
8287 free_netdev(dev);
8288
8289 return ret;
8290}
8291
8292/**
20346722 8293 * s2io_rem_nic - Free the PCI device
1da177e4 8294 * @pdev: structure containing the PCI related information of the device.
20346722 8295 * Description: This function is called by the Pci subsystem to release a
1da177e4 8296 * PCI device and free up all resource held up by the device. This could
20346722 8297 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8298 * from memory.
8299 */
8300
8301static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8302{
8303 struct net_device *dev =
d44570e4 8304 (struct net_device *)pci_get_drvdata(pdev);
1ee6dd77 8305 struct s2io_nic *sp;
1da177e4
LT		 8306
8307 if (dev == NULL) {
8308 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8309 return;
8310 }
8311
22747d6b
FR		 8312 flush_scheduled_work();
8313
4cf1653a 8314 sp = netdev_priv(dev);
1da177e4
LT		 8315 unregister_netdev(dev);
8316
8317 free_shared_mem(sp);
8318 iounmap(sp->bar0);
8319 iounmap(sp->bar1);
eccb8628 8320 pci_release_regions(pdev);
1da177e4 8321 pci_set_drvdata(pdev, NULL);
1da177e4 8322 free_netdev(dev);
19a60522 8323 pci_disable_device(pdev);
1da177e4
LT		 8324}
8325
8326/**
8327 * s2io_starter - Entry point for the driver
8328 * Description: This function is the entry point for the driver. It verifies
8329 * the module loadable parameters and initializes PCI configuration space.
8330 */
8331
43b7c451 8332static int __init s2io_starter(void)
1da177e4 8333{
29917620 8334 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8335}
8336
8337/**
20346722 8338 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8339 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8340 */
8341
372cc597 8342static __exit void s2io_closer(void)
1da177e4
LT		 8343{
8344 pci_unregister_driver(&s2io_driver);
8345 DBG_PRINT(INIT_DBG, "cleanup done\n");
8346}
8347
8348module_init(s2io_starter);
8349module_exit(s2io_closer);
7d3d0439 8350
6aa20a22 8351static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
d44570e4
JP		 8352 struct tcphdr **tcp, struct RxD_t *rxdp,
8353 struct s2io_nic *sp)
7d3d0439
RA		 8354{
8355 int ip_off;
8356 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8357
8358 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
d44570e4
JP		 8359 DBG_PRINT(INIT_DBG,
8360 "%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8361 __func__);
7d3d0439
RA		 8362 return -1;
8363 }
8364
cdb5bf02 8365 /* Checking for DIX type or DIX type with VLAN */
d44570e4 8366 if ((l2_type == 0) || (l2_type == 4)) {
cdb5bf02
SH		 8367 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8368 /*
8369 * If vlan stripping is disabled and the frame is VLAN tagged,
8370 * shift the offset by the VLAN header size bytes.
8371 */
cd0fce03 8372 if ((!sp->vlan_strip_flag) &&
d44570e4 8373 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
cdb5bf02
SH		 8374 ip_off += HEADER_VLAN_SIZE;
8375 } else {
7d3d0439 8376 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8377 return -1;
7d3d0439
RA		 8378 }
8379
8380 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8381 ip_len = (u8)((*ip)->ihl);
8382 ip_len <<= 2;
8383 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8384
8385 return 0;
8386}
8387
1ee6dd77 8388static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8389 struct tcphdr *tcp)
8390{
d44570e4
JP		 8391 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8392 if ((lro->iph->saddr != ip->saddr) ||
8393 (lro->iph->daddr != ip->daddr) ||
8394 (lro->tcph->source != tcp->source) ||
8395 (lro->tcph->dest != tcp->dest))
7d3d0439
RA		 8396 return -1;
8397 return 0;
8398}
8399
8400static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8401{
d44570e4 8402 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
7d3d0439
RA		 8403}
8404
1ee6dd77 8405static void initiate_new_session(struct lro *lro, u8 *l2h,
d44570e4
JP		 8406 struct iphdr *ip, struct tcphdr *tcp,
8407 u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8408{
d44570e4 8409 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8410 lro->l2h = l2h;
8411 lro->iph = ip;
8412 lro->tcph = tcp;
8413 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8414 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8415 lro->sg_num = 1;
8416 lro->total_len = ntohs(ip->tot_len);
8417 lro->frags_len = 0;
cdb5bf02 8418 lro->vlan_tag = vlan_tag;
6aa20a22 8419 /*
d44570e4
JP		 8420 * Check if we saw TCP timestamp.
8421 * Other consistency checks have already been done.
8422 */
7d3d0439 8423 if (tcp->doff == 8) {
c8855953
SR		 8424 __be32 *ptr;
8425 ptr = (__be32 *)(tcp+1);
7d3d0439 8426 lro->saw_ts = 1;
c8855953 8427 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8428 lro->cur_tsecr = *(ptr+2);
8429 }
8430 lro->in_use = 1;
8431}
8432
1ee6dd77 8433static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8434{
8435 struct iphdr *ip = lro->iph;
8436 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8437 __sum16 nchk;
ffb5df6c
JP		 8438 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8439
d44570e4 8440 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8441
8442 /* Update L3 header */
8443 ip->tot_len = htons(lro->total_len);
8444 ip->check = 0;
8445 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8446 ip->check = nchk;
8447
8448 /* Update L4 header */
8449 tcp->ack_seq = lro->tcp_ack;
8450 tcp->window = lro->window;
8451
8452 /* Update tsecr field if this session has timestamps enabled */
8453 if (lro->saw_ts) {
c8855953 8454 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8455 *(ptr+2) = lro->cur_tsecr;
8456 }
8457
8458 /* Update counters required for calculation of
8459 * average no. of packets aggregated.
8460 */
ffb5df6c
JP		 8461 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8462 swstats->num_aggregations++;
7d3d0439
RA		 8463}
8464
1ee6dd77 8465static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
d44570e4 8466 struct tcphdr *tcp, u32 l4_pyld)
7d3d0439 8467{
d44570e4 8468 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8469 lro->total_len += l4_pyld;
8470 lro->frags_len += l4_pyld;
8471 lro->tcp_next_seq += l4_pyld;
8472 lro->sg_num++;
8473
8474 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8475 lro->tcp_ack = tcp->ack_seq;
8476 lro->window = tcp->window;
6aa20a22 8477
7d3d0439 8478 if (lro->saw_ts) {
c8855953 8479 __be32 *ptr;
7d3d0439 8480 /* Update tsecr and tsval from this packet */
c8855953
SR		 8481 ptr = (__be32 *)(tcp+1);
8482 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8483 lro->cur_tsecr = *(ptr + 2);
8484 }
8485}
8486
1ee6dd77 8487static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8488 struct tcphdr *tcp, u32 tcp_pyld_len)
8489{
7d3d0439
RA		 8490 u8 *ptr;
8491
d44570e4 8492 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
79dc1901 8493
7d3d0439
RA		 8494 if (!tcp_pyld_len) {
8495 /* Runt frame or a pure ack */
8496 return -1;
8497 }
8498
8499 if (ip->ihl != 5) /* IP has options */
8500 return -1;
8501
75c30b13
AR		 8502 /* If we see CE codepoint in IP header, packet is not mergeable */
8503 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8504 return -1;
8505
8506 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
d44570e4
JP		 8507 if (tcp->urg || tcp->psh || tcp->rst ||
8508 tcp->syn || tcp->fin ||
8509 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8510 /*
8511 * Currently recognize only the ack control word and
8512 * any other control field being set would result in
8513 * flushing the LRO session
8514 */
8515 return -1;
8516 }
8517
6aa20a22 8518 /*
7d3d0439
RA		 8519 * Allow only one TCP timestamp option. Don't aggregate if
8520 * any other options are detected.
8521 */
8522 if (tcp->doff != 5 && tcp->doff != 8)
8523 return -1;
8524
8525 if (tcp->doff == 8) {
6aa20a22 8526 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8527 while (*ptr == TCPOPT_NOP)
8528 ptr++;
8529 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8530 return -1;
8531
8532 /* Ensure timestamp value increases monotonically */
8533 if (l_lro)
c8855953 8534 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8535 return -1;
8536
8537 /* timestamp echo reply should be non-zero */
c8855953 8538 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8539 return -1;
8540 }
8541
8542 return 0;
8543}
8544
d44570e4
JP		 8545static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8546 u8 **tcp, u32 *tcp_len, struct lro **lro,
8547 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8548{
8549 struct iphdr *ip;
8550 struct tcphdr *tcph;
8551 int ret = 0, i;
cdb5bf02 8552 u16 vlan_tag = 0;
ffb5df6c 8553 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439 8554
d44570e4
JP		 8555 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8556 rxdp, sp);
8557 if (ret)
7d3d0439 8558 return ret;
7d3d0439 8559
d44570e4
JP		 8560 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8561
cdb5bf02 8562 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8563 tcph = (struct tcphdr *)*tcp;
8564 *tcp_len = get_l4_pyld_length(ip, tcph);
d44570e4 8565 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8566 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8567 if (l_lro->in_use) {
8568 if (check_for_socket_match(l_lro, ip, tcph))
8569 continue;
8570 /* Sock pair matched */
8571 *lro = l_lro;
8572
8573 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
9e39f7c5
JP		 8574 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8575 "expected 0x%x, actual 0x%x\n",
8576 __func__,
7d3d0439
RA		 8577 (*lro)->tcp_next_seq,
8578 ntohl(tcph->seq));
8579
ffb5df6c 8580 swstats->outof_sequence_pkts++;
7d3d0439
RA		 8581 ret = 2;
8582 break;
8583 }
8584
d44570e4
JP		 8585 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8586 *tcp_len))
7d3d0439
RA		 8587 ret = 1; /* Aggregate */
8588 else
8589 ret = 2; /* Flush both */
8590 break;
8591 }
8592 }
8593
8594 if (ret == 0) {
8595 /* Before searching for available LRO objects,
8596 * check if the pkt is L3/L4 aggregatable. If not
8597 * don't create new LRO session. Just send this
8598 * packet up.
8599 */
d44570e4 8600 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
7d3d0439 8601 return 5;
7d3d0439 8602
d44570e4 8603 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8604 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8605 if (!(l_lro->in_use)) {
8606 *lro = l_lro;
8607 ret = 3; /* Begin anew */
8608 break;
8609 }
8610 }
8611 }
8612
8613 if (ret == 0) { /* sessions exceeded */
9e39f7c5 8614 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
b39d66a8 8615 __func__);
7d3d0439
RA		 8616 *lro = NULL;
8617 return ret;
8618 }
8619
8620 switch (ret) {
d44570e4
JP		 8621 case 3:
8622 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8623 vlan_tag);
8624 break;
8625 case 2:
8626 update_L3L4_header(sp, *lro);
8627 break;
8628 case 1:
8629 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8630 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7d3d0439 8631 update_L3L4_header(sp, *lro);
d44570e4
JP		 8632 ret = 4; /* Flush the LRO */
8633 }
8634 break;
8635 default:
9e39f7c5 8636 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
d44570e4 8637 break;
7d3d0439
RA		 8638 }
8639
8640 return ret;
8641}
8642
1ee6dd77 8643static void clear_lro_session(struct lro *lro)
7d3d0439 8644{
1ee6dd77 8645 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8646
8647 memset(lro, 0, lro_struct_size);
8648}
8649
cdb5bf02 8650static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8651{
8652 struct net_device *dev = skb->dev;
4cf1653a 8653 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8654
8655 skb->protocol = eth_type_trans(skb, dev);
d44570e4 8656 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8657 /* Queueing the vlan frame to the upper layer */
8658 if (sp->config.napi)
8659 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8660 else
8661 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8662 } else {
8663 if (sp->config.napi)
8664 netif_receive_skb(skb);
8665 else
8666 netif_rx(skb);
8667 }
7d3d0439
RA		 8668}
8669
1ee6dd77 8670static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
d44570e4 8671 struct sk_buff *skb, u32 tcp_len)
7d3d0439 8672{
75c30b13 8673 struct sk_buff *first = lro->parent;
ffb5df6c 8674 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439
RA		 8675
8676 first->len += tcp_len;
8677 first->data_len = lro->frags_len;
8678 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8679 if (skb_shinfo(first)->frag_list)
8680 lro->last_frag->next = skb;
7d3d0439
RA		 8681 else
8682 skb_shinfo(first)->frag_list = skb;
372cc597 8683 first->truesize += skb->truesize;
75c30b13 8684 lro->last_frag = skb;
ffb5df6c 8685 swstats->clubbed_frms_cnt++;
7d3d0439 8686}
d796fdb7
LV		 8687
8688/**
8689 * s2io_io_error_detected - called when PCI error is detected
8690 * @pdev: Pointer to PCI device
8453d43f 8691 * @state: The current pci connection state
d796fdb7
LV		 8692 *
8693 * This function is called after a PCI bus error affecting
8694 * this device has been detected.
8695 */
8696static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
d44570e4 8697 pci_channel_state_t state)
d796fdb7
LV		 8698{
8699 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8700 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8701
8702 netif_device_detach(netdev);
8703
1e3c8bd6
DN		 8704 if (state == pci_channel_io_perm_failure)
8705 return PCI_ERS_RESULT_DISCONNECT;
8706
d796fdb7
LV		 8707 if (netif_running(netdev)) {
8708 /* Bring down the card, while avoiding PCI I/O */
8709 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8710 }
8711 pci_disable_device(pdev);
8712
8713 return PCI_ERS_RESULT_NEED_RESET;
8714}
8715
8716/**
8717 * s2io_io_slot_reset - called after the pci bus has been reset.
8718 * @pdev: Pointer to PCI device
8719 *
8720 * Restart the card from scratch, as if from a cold-boot.
8721 * At this point, the card has exprienced a hard reset,
8722 * followed by fixups by BIOS, and has its config space
8723 * set up identically to what it was at cold boot.
8724 */
8725static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8726{
8727 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8728 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8729
8730 if (pci_enable_device(pdev)) {
6cef2b8e 8731 pr_err("Cannot re-enable PCI device after reset.\n");
d796fdb7
LV		 8732 return PCI_ERS_RESULT_DISCONNECT;
8733 }
8734
8735 pci_set_master(pdev);
8736 s2io_reset(sp);
8737
8738 return PCI_ERS_RESULT_RECOVERED;
8739}
8740
8741/**
8742 * s2io_io_resume - called when traffic can start flowing again.
8743 * @pdev: Pointer to PCI device
8744 *
8745 * This callback is called when the error recovery driver tells
8746 * us that its OK to resume normal operation.
8747 */
8748static void s2io_io_resume(struct pci_dev *pdev)
8749{
8750 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8751 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8752
8753 if (netif_running(netdev)) {
8754 if (s2io_card_up(sp)) {
6cef2b8e 8755 pr_err("Can't bring device back up after reset.\n");
d796fdb7
LV		 8756 return;
8757 }
8758
8759 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8760 s2io_card_down(sp);
6cef2b8e 8761 pr_err("Can't restore mac addr after reset.\n");
d796fdb7
LV		 8762 return;
8763 }
8764 }
8765
8766 netif_device_attach(netdev);
fd2ea0a7 8767 netif_tx_wake_all_queues(netdev);
d796fdb7 8768}
Clone of davem's net-next-2.6 tree