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Merge branch 'fixes-jgarzik' of git://git.kernel.org/pub/scm/linux/kernel/git/linvill...
[net-next-2.6.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
1da177e4
LT		 53 ************************************************************************/
54
1da177e4
LT		 55#include <linux/module.h>
56#include <linux/types.h>
57#include <linux/errno.h>
58#include <linux/ioport.h>
59#include <linux/pci.h>
1e7f0bd8 60#include <linux/dma-mapping.h>
1da177e4
LT		 61#include <linux/kernel.h>
62#include <linux/netdevice.h>
63#include <linux/etherdevice.h>
64#include <linux/skbuff.h>
65#include <linux/init.h>
66#include <linux/delay.h>
67#include <linux/stddef.h>
68#include <linux/ioctl.h>
69#include <linux/timex.h>
1da177e4 70#include <linux/ethtool.h>
1da177e4 71#include <linux/workqueue.h>
be3a6b02 72#include <linux/if_vlan.h>
7d3d0439
RA		 73#include <linux/ip.h>
74#include <linux/tcp.h>
75#include <net/tcp.h>
1da177e4 76
1da177e4
LT		 77#include <asm/system.h>
78#include <asm/uaccess.h>
20346722 79#include <asm/io.h>
fe931395 80#include <asm/div64.h>
330ce0de 81#include <asm/irq.h>
1da177e4
LT		 82
83/* local include */
84#include "s2io.h"
85#include "s2io-regs.h"
86
18b2b7bd 87#define DRV_VERSION "2.0.26.6"
6c1792f4 88
1da177e4 89/* S2io Driver name & version. */
20346722 90static char s2io_driver_name[] = "Neterion";
6c1792f4 91static char s2io_driver_version[] = DRV_VERSION;
1da177e4 92
6d517a27
VP		 93static int rxd_size[2] = {32,48};
94static int rxd_count[2] = {127,85};
da6971d8 95
1ee6dd77 96static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 97{
98 int ret;
99
100 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
101 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
102
103 return ret;
104}
105
20346722 106/*
1da177e4
LT		 107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
110 */
541ae68f
K		 111#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 115
116#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
119#define PANIC 1
120#define LOW 2
1ee6dd77 121static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
1da177e4 122{
1ee6dd77 123 struct mac_info *mac_control;
20346722
K		 124
125 mac_control = &sp->mac_control;
863c11a9
AR		 126 if (rxb_size <= rxd_count[sp->rxd_mode])
127 return PANIC;
128 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
129 return LOW;
130 return 0;
1da177e4
LT		 131}
132
92b84437
SS		 133static inline int is_s2io_card_up(const struct s2io_nic * sp)
134{
135 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
136}
137
1da177e4
LT		 138/* Ethtool related variables and Macros. */
139static char s2io_gstrings[][ETH_GSTRING_LEN] = {
140 "Register test\t(offline)",
141 "Eeprom test\t(offline)",
142 "Link test\t(online)",
143 "RLDRAM test\t(offline)",
144 "BIST Test\t(offline)"
145};
146
fa1f0cb3 147static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 148 {"tmac_frms"},
149 {"tmac_data_octets"},
150 {"tmac_drop_frms"},
151 {"tmac_mcst_frms"},
152 {"tmac_bcst_frms"},
153 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 154 {"tmac_ttl_octets"},
155 {"tmac_ucst_frms"},
156 {"tmac_nucst_frms"},
1da177e4 157 {"tmac_any_err_frms"},
bd1034f0 158 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 159 {"tmac_vld_ip_octets"},
160 {"tmac_vld_ip"},
161 {"tmac_drop_ip"},
162 {"tmac_icmp"},
163 {"tmac_rst_tcp"},
164 {"tmac_tcp"},
165 {"tmac_udp"},
166 {"rmac_vld_frms"},
167 {"rmac_data_octets"},
168 {"rmac_fcs_err_frms"},
169 {"rmac_drop_frms"},
170 {"rmac_vld_mcst_frms"},
171 {"rmac_vld_bcst_frms"},
172 {"rmac_in_rng_len_err_frms"},
bd1034f0 173 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 174 {"rmac_long_frms"},
175 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 176 {"rmac_unsup_ctrl_frms"},
177 {"rmac_ttl_octets"},
178 {"rmac_accepted_ucst_frms"},
179 {"rmac_accepted_nucst_frms"},
1da177e4 180 {"rmac_discarded_frms"},
bd1034f0
AR		 181 {"rmac_drop_events"},
182 {"rmac_ttl_less_fb_octets"},
183 {"rmac_ttl_frms"},
1da177e4
LT		 184 {"rmac_usized_frms"},
185 {"rmac_osized_frms"},
186 {"rmac_frag_frms"},
187 {"rmac_jabber_frms"},
bd1034f0
AR		 188 {"rmac_ttl_64_frms"},
189 {"rmac_ttl_65_127_frms"},
190 {"rmac_ttl_128_255_frms"},
191 {"rmac_ttl_256_511_frms"},
192 {"rmac_ttl_512_1023_frms"},
193 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 194 {"rmac_ip"},
195 {"rmac_ip_octets"},
196 {"rmac_hdr_err_ip"},
197 {"rmac_drop_ip"},
198 {"rmac_icmp"},
199 {"rmac_tcp"},
200 {"rmac_udp"},
201 {"rmac_err_drp_udp"},
bd1034f0
AR		 202 {"rmac_xgmii_err_sym"},
203 {"rmac_frms_q0"},
204 {"rmac_frms_q1"},
205 {"rmac_frms_q2"},
206 {"rmac_frms_q3"},
207 {"rmac_frms_q4"},
208 {"rmac_frms_q5"},
209 {"rmac_frms_q6"},
210 {"rmac_frms_q7"},
211 {"rmac_full_q0"},
212 {"rmac_full_q1"},
213 {"rmac_full_q2"},
214 {"rmac_full_q3"},
215 {"rmac_full_q4"},
216 {"rmac_full_q5"},
217 {"rmac_full_q6"},
218 {"rmac_full_q7"},
1da177e4 219 {"rmac_pause_cnt"},
bd1034f0
AR		 220 {"rmac_xgmii_data_err_cnt"},
221 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 222 {"rmac_accepted_ip"},
223 {"rmac_err_tcp"},
bd1034f0
AR		 224 {"rd_req_cnt"},
225 {"new_rd_req_cnt"},
226 {"new_rd_req_rtry_cnt"},
227 {"rd_rtry_cnt"},
228 {"wr_rtry_rd_ack_cnt"},
229 {"wr_req_cnt"},
230 {"new_wr_req_cnt"},
231 {"new_wr_req_rtry_cnt"},
232 {"wr_rtry_cnt"},
233 {"wr_disc_cnt"},
234 {"rd_rtry_wr_ack_cnt"},
235 {"txp_wr_cnt"},
236 {"txd_rd_cnt"},
237 {"txd_wr_cnt"},
238 {"rxd_rd_cnt"},
239 {"rxd_wr_cnt"},
240 {"txf_rd_cnt"},
fa1f0cb3
SS		 241 {"rxf_wr_cnt"}
242};
243
244static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 245 {"rmac_ttl_1519_4095_frms"},
246 {"rmac_ttl_4096_8191_frms"},
247 {"rmac_ttl_8192_max_frms"},
248 {"rmac_ttl_gt_max_frms"},
249 {"rmac_osized_alt_frms"},
250 {"rmac_jabber_alt_frms"},
251 {"rmac_gt_max_alt_frms"},
252 {"rmac_vlan_frms"},
253 {"rmac_len_discard"},
254 {"rmac_fcs_discard"},
255 {"rmac_pf_discard"},
256 {"rmac_da_discard"},
257 {"rmac_red_discard"},
258 {"rmac_rts_discard"},
259 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 260 {"link_fault_cnt"}
261};
262
263static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 264 {"\n DRIVER STATISTICS"},
265 {"single_bit_ecc_errs"},
266 {"double_bit_ecc_errs"},
bd1034f0
AR		 267 {"parity_err_cnt"},
268 {"serious_err_cnt"},
269 {"soft_reset_cnt"},
270 {"fifo_full_cnt"},
8116f3cf
SS		 271 {"ring_0_full_cnt"},
272 {"ring_1_full_cnt"},
273 {"ring_2_full_cnt"},
274 {"ring_3_full_cnt"},
275 {"ring_4_full_cnt"},
276 {"ring_5_full_cnt"},
277 {"ring_6_full_cnt"},
278 {"ring_7_full_cnt"},
43b7c451
SH		 279 {"alarm_transceiver_temp_high"},
280 {"alarm_transceiver_temp_low"},
281 {"alarm_laser_bias_current_high"},
282 {"alarm_laser_bias_current_low"},
283 {"alarm_laser_output_power_high"},
284 {"alarm_laser_output_power_low"},
285 {"warn_transceiver_temp_high"},
286 {"warn_transceiver_temp_low"},
287 {"warn_laser_bias_current_high"},
288 {"warn_laser_bias_current_low"},
289 {"warn_laser_output_power_high"},
290 {"warn_laser_output_power_low"},
291 {"lro_aggregated_pkts"},
292 {"lro_flush_both_count"},
293 {"lro_out_of_sequence_pkts"},
294 {"lro_flush_due_to_max_pkts"},
295 {"lro_avg_aggr_pkts"},
296 {"mem_alloc_fail_cnt"},
297 {"pci_map_fail_cnt"},
298 {"watchdog_timer_cnt"},
299 {"mem_allocated"},
300 {"mem_freed"},
301 {"link_up_cnt"},
302 {"link_down_cnt"},
303 {"link_up_time"},
304 {"link_down_time"},
305 {"tx_tcode_buf_abort_cnt"},
306 {"tx_tcode_desc_abort_cnt"},
307 {"tx_tcode_parity_err_cnt"},
308 {"tx_tcode_link_loss_cnt"},
309 {"tx_tcode_list_proc_err_cnt"},
310 {"rx_tcode_parity_err_cnt"},
311 {"rx_tcode_abort_cnt"},
312 {"rx_tcode_parity_abort_cnt"},
313 {"rx_tcode_rda_fail_cnt"},
314 {"rx_tcode_unkn_prot_cnt"},
315 {"rx_tcode_fcs_err_cnt"},
316 {"rx_tcode_buf_size_err_cnt"},
317 {"rx_tcode_rxd_corrupt_cnt"},
318 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 319 {"tda_err_cnt"},
320 {"pfc_err_cnt"},
321 {"pcc_err_cnt"},
322 {"tti_err_cnt"},
323 {"tpa_err_cnt"},
324 {"sm_err_cnt"},
325 {"lso_err_cnt"},
326 {"mac_tmac_err_cnt"},
327 {"mac_rmac_err_cnt"},
328 {"xgxs_txgxs_err_cnt"},
329 {"xgxs_rxgxs_err_cnt"},
330 {"rc_err_cnt"},
331 {"prc_pcix_err_cnt"},
332 {"rpa_err_cnt"},
333 {"rda_err_cnt"},
334 {"rti_err_cnt"},
335 {"mc_err_cnt"}
1da177e4
LT		 336};
337
fa1f0cb3
SS		 338#define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
339#define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
340 ETH_GSTRING_LEN
341#define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
342
343#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
344#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
345
346#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
347#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4
LT		 348
349#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
350#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
351
25fff88e
K		 352#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
353 init_timer(&timer); \
354 timer.function = handle; \
355 timer.data = (unsigned long) arg; \
356 mod_timer(&timer, (jiffies + exp)) \
357
2fd37688
SS		 358/* copy mac addr to def_mac_addr array */
359static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
360{
361 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
362 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
363 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
364 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
365 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
366 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
367}
be3a6b02
K		 368/* Add the vlan */
369static void s2io_vlan_rx_register(struct net_device *dev,
370 struct vlan_group *grp)
371{
1ee6dd77 372 struct s2io_nic *nic = dev->priv;
be3a6b02
K		 373 unsigned long flags;
374
375 spin_lock_irqsave(&nic->tx_lock, flags);
376 nic->vlgrp = grp;
377 spin_unlock_irqrestore(&nic->tx_lock, flags);
378}
379
926930b2 380/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
7b490343 381static int vlan_strip_flag;
926930b2 382
20346722 383/*
1da177e4
LT		 384 * Constants to be programmed into the Xena's registers, to configure
385 * the XAUI.
386 */
387
1da177e4 388#define END_SIGN 0x0
f71e1309 389static const u64 herc_act_dtx_cfg[] = {
541ae68f 390 /* Set address */
e960fc5c 391 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 392 /* Write data */
e960fc5c 393 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 394 /* Set address */
395 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
396 /* Write data */
397 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
398 /* Set address */
e960fc5c 399 0x801205150D440000ULL, 0x801205150D4400E0ULL,
400 /* Write data */
401 0x801205150D440004ULL, 0x801205150D4400E4ULL,
402 /* Set address */
541ae68f
K		 403 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
404 /* Write data */
405 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
406 /* Done */
407 END_SIGN
408};
409
f71e1309 410static const u64 xena_dtx_cfg[] = {
c92ca04b 411 /* Set address */
1da177e4 412 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 413 /* Write data */
414 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
415 /* Set address */
416 0x8001051500000000ULL, 0x80010515000000E0ULL,
417 /* Write data */
418 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
419 /* Set address */
1da177e4 420 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 421 /* Write data */
422 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 423 END_SIGN
424};
425
20346722 426/*
1da177e4
LT		 427 * Constants for Fixing the MacAddress problem seen mostly on
428 * Alpha machines.
429 */
f71e1309 430static const u64 fix_mac[] = {
1da177e4
LT		 431 0x0060000000000000ULL, 0x0060600000000000ULL,
432 0x0040600000000000ULL, 0x0000600000000000ULL,
433 0x0020600000000000ULL, 0x0060600000000000ULL,
434 0x0020600000000000ULL, 0x0060600000000000ULL,
435 0x0020600000000000ULL, 0x0060600000000000ULL,
436 0x0020600000000000ULL, 0x0060600000000000ULL,
437 0x0020600000000000ULL, 0x0060600000000000ULL,
438 0x0020600000000000ULL, 0x0060600000000000ULL,
439 0x0020600000000000ULL, 0x0060600000000000ULL,
440 0x0020600000000000ULL, 0x0060600000000000ULL,
441 0x0020600000000000ULL, 0x0060600000000000ULL,
442 0x0020600000000000ULL, 0x0060600000000000ULL,
443 0x0020600000000000ULL, 0x0000600000000000ULL,
444 0x0040600000000000ULL, 0x0060600000000000ULL,
445 END_SIGN
446};
447
b41477f3
AR		 448MODULE_LICENSE("GPL");
449MODULE_VERSION(DRV_VERSION);
450
451
1da177e4 452/* Module Loadable parameters. */
b41477f3
AR		 453S2IO_PARM_INT(tx_fifo_num, 1);
454S2IO_PARM_INT(rx_ring_num, 1);
455
456
457S2IO_PARM_INT(rx_ring_mode, 1);
458S2IO_PARM_INT(use_continuous_tx_intrs, 1);
459S2IO_PARM_INT(rmac_pause_time, 0x100);
460S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
461S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
462S2IO_PARM_INT(shared_splits, 0);
463S2IO_PARM_INT(tmac_util_period, 5);
464S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 465S2IO_PARM_INT(l3l4hdr_size, 128);
303bcb4b 466/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 467S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 468/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 469S2IO_PARM_INT(intr_type, 2);
7d3d0439 470/* Large receive offload feature */
43b7c451
SH		 471static unsigned int lro_enable;
472module_param_named(lro, lro_enable, uint, 0);
473
7d3d0439
RA		 474/* Max pkts to be aggregated by LRO at one time. If not specified,
475 * aggregation happens until we hit max IP pkt size(64K)
476 */
b41477f3 477S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 478S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 479
480S2IO_PARM_INT(napi, 1);
481S2IO_PARM_INT(ufo, 0);
926930b2 482S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 483
484static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
485 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
486static unsigned int rx_ring_sz[MAX_RX_RINGS] =
487 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
488static unsigned int rts_frm_len[MAX_RX_RINGS] =
489 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
490
491module_param_array(tx_fifo_len, uint, NULL, 0);
492module_param_array(rx_ring_sz, uint, NULL, 0);
493module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 494
20346722 495/*
1da177e4 496 * S2IO device table.
20346722 497 * This table lists all the devices that this driver supports.
1da177e4
LT		 498 */
499static struct pci_device_id s2io_tbl[] __devinitdata = {
500 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
501 PCI_ANY_ID, PCI_ANY_ID},
502 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
503 PCI_ANY_ID, PCI_ANY_ID},
504 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722
K		 505 PCI_ANY_ID, PCI_ANY_ID},
506 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
507 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 508 {0,}
509};
510
511MODULE_DEVICE_TABLE(pci, s2io_tbl);
512
d796fdb7
LV		 513static struct pci_error_handlers s2io_err_handler = {
514 .error_detected = s2io_io_error_detected,
515 .slot_reset = s2io_io_slot_reset,
516 .resume = s2io_io_resume,
517};
518
1da177e4
LT		 519static struct pci_driver s2io_driver = {
520 .name = "S2IO",
521 .id_table = s2io_tbl,
522 .probe = s2io_init_nic,
523 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 524 .err_handler = &s2io_err_handler,
1da177e4
LT		 525};
526
527/* A simplifier macro used both by init and free shared_mem Fns(). */
528#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
529
530/**
531 * init_shared_mem - Allocation and Initialization of Memory
532 * @nic: Device private variable.
20346722
K		 533 * Description: The function allocates all the memory areas shared
534 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 535 * Rx descriptors and the statistics block.
536 */
537
538static int init_shared_mem(struct s2io_nic *nic)
539{
540 u32 size;
541 void *tmp_v_addr, *tmp_v_addr_next;
542 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 543 struct RxD_block *pre_rxd_blk = NULL;
372cc597 544 int i, j, blk_cnt;
1da177e4
LT		 545 int lst_size, lst_per_page;
546 struct net_device *dev = nic->dev;
8ae418cf 547 unsigned long tmp;
1ee6dd77 548 struct buffAdd *ba;
1da177e4 549
1ee6dd77 550 struct mac_info *mac_control;
1da177e4 551 struct config_param *config;
491976b2 552 unsigned long long mem_allocated = 0;
1da177e4
LT		 553
554 mac_control = &nic->mac_control;
555 config = &nic->config;
556
557
558 /* Allocation and initialization of TXDLs in FIOFs */
559 size = 0;
560 for (i = 0; i < config->tx_fifo_num; i++) {
561 size += config->tx_cfg[i].fifo_len;
562 }
563 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 564 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 565 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 566 return -EINVAL;
1da177e4
LT		 567 }
568
1ee6dd77 569 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 570 lst_per_page = PAGE_SIZE / lst_size;
571
572 for (i = 0; i < config->tx_fifo_num; i++) {
573 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 574 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
bd684e43 575 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
20346722
K		 576 GFP_KERNEL);
577 if (!mac_control->fifos[i].list_info) {
0c61ed5f 578 DBG_PRINT(INFO_DBG,
1da177e4
LT		 579 "Malloc failed for list_info\n");
580 return -ENOMEM;
581 }
491976b2 582 mem_allocated += list_holder_size;
1da177e4
LT		 583 }
584 for (i = 0; i < config->tx_fifo_num; i++) {
585 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
586 lst_per_page);
20346722
K		 587 mac_control->fifos[i].tx_curr_put_info.offset = 0;
588 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 589 config->tx_cfg[i].fifo_len - 1;
20346722
K		 590 mac_control->fifos[i].tx_curr_get_info.offset = 0;
591 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 592 config->tx_cfg[i].fifo_len - 1;
20346722
K		 593 mac_control->fifos[i].fifo_no = i;
594 mac_control->fifos[i].nic = nic;
fed5eccd 595 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
20346722 596
1da177e4
LT		 597 for (j = 0; j < page_num; j++) {
598 int k = 0;
599 dma_addr_t tmp_p;
600 void *tmp_v;
601 tmp_v = pci_alloc_consistent(nic->pdev,
602 PAGE_SIZE, &tmp_p);
603 if (!tmp_v) {
0c61ed5f 604 DBG_PRINT(INFO_DBG,
1da177e4 605 "pci_alloc_consistent ");
0c61ed5f 606 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 607 return -ENOMEM;
608 }
776bd20f 609 /* If we got a zero DMA address(can happen on
610 * certain platforms like PPC), reallocate.
611 * Store virtual address of page we don't want,
612 * to be freed later.
613 */
614 if (!tmp_p) {
615 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 616 DBG_PRINT(INIT_DBG,
776bd20f 617 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 618 DBG_PRINT(INIT_DBG,
6b4d617d 619 "Virtual address %p\n", tmp_v);
776bd20f 620 tmp_v = pci_alloc_consistent(nic->pdev,
621 PAGE_SIZE, &tmp_p);
622 if (!tmp_v) {
0c61ed5f 623 DBG_PRINT(INFO_DBG,
776bd20f 624 "pci_alloc_consistent ");
0c61ed5f 625 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 626 return -ENOMEM;
627 }
491976b2 628 mem_allocated += PAGE_SIZE;
776bd20f 629 }
1da177e4
LT		 630 while (k < lst_per_page) {
631 int l = (j * lst_per_page) + k;
632 if (l == config->tx_cfg[i].fifo_len)
20346722
K		 633 break;
634 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 635 tmp_v + (k * lst_size);
20346722 636 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 637 tmp_p + (k * lst_size);
638 k++;
639 }
640 }
641 }
1da177e4 642
4384247b 643 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
fed5eccd
AR		 644 if (!nic->ufo_in_band_v)
645 return -ENOMEM;
491976b2 646 mem_allocated += (size * sizeof(u64));
fed5eccd 647
1da177e4
LT		 648 /* Allocation and initialization of RXDs in Rings */
649 size = 0;
650 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 651 if (config->rx_cfg[i].num_rxd %
652 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 653 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
654 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
655 i);
656 DBG_PRINT(ERR_DBG, "RxDs per Block");
657 return FAILURE;
658 }
659 size += config->rx_cfg[i].num_rxd;
20346722 660 mac_control->rings[i].block_count =
da6971d8
AR		 661 config->rx_cfg[i].num_rxd /
662 (rxd_count[nic->rxd_mode] + 1 );
663 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
664 mac_control->rings[i].block_count;
1da177e4 665 }
da6971d8 666 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 667 size = (size * (sizeof(struct RxD1)));
da6971d8 668 else
1ee6dd77 669 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 670
671 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 672 mac_control->rings[i].rx_curr_get_info.block_index = 0;
673 mac_control->rings[i].rx_curr_get_info.offset = 0;
674 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 675 config->rx_cfg[i].num_rxd - 1;
20346722
K		 676 mac_control->rings[i].rx_curr_put_info.block_index = 0;
677 mac_control->rings[i].rx_curr_put_info.offset = 0;
678 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 679 config->rx_cfg[i].num_rxd - 1;
20346722
K		 680 mac_control->rings[i].nic = nic;
681 mac_control->rings[i].ring_no = i;
682
da6971d8
AR		 683 blk_cnt = config->rx_cfg[i].num_rxd /
684 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 685 /* Allocating all the Rx blocks */
686 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 687 struct rx_block_info *rx_blocks;
da6971d8
AR		 688 int l;
689
690 rx_blocks = &mac_control->rings[i].rx_blocks[j];
691 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 692 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
693 &tmp_p_addr);
694 if (tmp_v_addr == NULL) {
695 /*
20346722
K		 696 * In case of failure, free_shared_mem()
697 * is called, which should free any
698 * memory that was alloced till the
1da177e4
LT		 699 * failure happened.
700 */
da6971d8 701 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 702 return -ENOMEM;
703 }
491976b2 704 mem_allocated += size;
1da177e4 705 memset(tmp_v_addr, 0, size);
da6971d8
AR		 706 rx_blocks->block_virt_addr = tmp_v_addr;
707 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 708 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 709 rxd_count[nic->rxd_mode],
710 GFP_KERNEL);
372cc597
SS		 711 if (!rx_blocks->rxds)
712 return -ENOMEM;
8a4bdbaa 713 mem_allocated +=
491976b2 714 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
da6971d8
AR		 715 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
716 rx_blocks->rxds[l].virt_addr =
717 rx_blocks->block_virt_addr +
718 (rxd_size[nic->rxd_mode] * l);
719 rx_blocks->rxds[l].dma_addr =
720 rx_blocks->block_dma_addr +
721 (rxd_size[nic->rxd_mode] * l);
722 }
1da177e4
LT		 723 }
724 /* Interlinking all Rx Blocks */
725 for (j = 0; j < blk_cnt; j++) {
20346722
K		 726 tmp_v_addr =
727 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 728 tmp_v_addr_next =
20346722 729 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 730 blk_cnt].block_virt_addr;
20346722
K		 731 tmp_p_addr =
732 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 733 tmp_p_addr_next =
20346722 734 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 735 blk_cnt].block_dma_addr;
736
1ee6dd77 737 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 738 pre_rxd_blk->reserved_2_pNext_RxD_block =
739 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 740 pre_rxd_blk->pNext_RxD_Blk_physical =
741 (u64) tmp_p_addr_next;
742 }
743 }
6d517a27 744 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 745 /*
746 * Allocation of Storages for buffer addresses in 2BUFF mode
747 * and the buffers as well.
748 */
749 for (i = 0; i < config->rx_ring_num; i++) {
750 blk_cnt = config->rx_cfg[i].num_rxd /
751 (rxd_count[nic->rxd_mode]+ 1);
752 mac_control->rings[i].ba =
1ee6dd77 753 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 754 GFP_KERNEL);
da6971d8 755 if (!mac_control->rings[i].ba)
1da177e4 756 return -ENOMEM;
491976b2 757 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
da6971d8
AR		 758 for (j = 0; j < blk_cnt; j++) {
759 int k = 0;
760 mac_control->rings[i].ba[j] =
1ee6dd77 761 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 762 (rxd_count[nic->rxd_mode] + 1)),
763 GFP_KERNEL);
764 if (!mac_control->rings[i].ba[j])
1da177e4 765 return -ENOMEM;
491976b2
SH		 766 mem_allocated += (sizeof(struct buffAdd) * \
767 (rxd_count[nic->rxd_mode] + 1));
da6971d8
AR		 768 while (k != rxd_count[nic->rxd_mode]) {
769 ba = &mac_control->rings[i].ba[j][k];
770
771 ba->ba_0_org = (void *) kmalloc
772 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
773 if (!ba->ba_0_org)
774 return -ENOMEM;
8a4bdbaa 775 mem_allocated +=
491976b2 776 (BUF0_LEN + ALIGN_SIZE);
da6971d8
AR		 777 tmp = (unsigned long)ba->ba_0_org;
778 tmp += ALIGN_SIZE;
779 tmp &= ~((unsigned long) ALIGN_SIZE);
780 ba->ba_0 = (void *) tmp;
781
782 ba->ba_1_org = (void *) kmalloc
783 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
784 if (!ba->ba_1_org)
785 return -ENOMEM;
8a4bdbaa 786 mem_allocated
491976b2 787 += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 788 tmp = (unsigned long) ba->ba_1_org;
789 tmp += ALIGN_SIZE;
790 tmp &= ~((unsigned long) ALIGN_SIZE);
791 ba->ba_1 = (void *) tmp;
792 k++;
793 }
1da177e4
LT		 794 }
795 }
796 }
1da177e4
LT		 797
798 /* Allocation and initialization of Statistics block */
1ee6dd77 799 size = sizeof(struct stat_block);
1da177e4
LT		 800 mac_control->stats_mem = pci_alloc_consistent
801 (nic->pdev, size, &mac_control->stats_mem_phy);
802
803 if (!mac_control->stats_mem) {
20346722
K		 804 /*
805 * In case of failure, free_shared_mem() is called, which
806 * should free any memory that was alloced till the
1da177e4
LT		 807 * failure happened.
808 */
809 return -ENOMEM;
810 }
491976b2 811 mem_allocated += size;
1da177e4
LT		 812 mac_control->stats_mem_sz = size;
813
814 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 815 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 816 memset(tmp_v_addr, 0, size);
1da177e4
LT		 817 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
818 (unsigned long long) tmp_p_addr);
491976b2 819 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 820 return SUCCESS;
821}
822
20346722
K		 823/**
824 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 825 * @nic: Device private variable.
826 * Description: This function is to free all memory locations allocated by
827 * the init_shared_mem() function and return it to the kernel.
828 */
829
830static void free_shared_mem(struct s2io_nic *nic)
831{
832 int i, j, blk_cnt, size;
491976b2 833 u32 ufo_size = 0;
1da177e4
LT		 834 void *tmp_v_addr;
835 dma_addr_t tmp_p_addr;
1ee6dd77 836 struct mac_info *mac_control;
1da177e4
LT		 837 struct config_param *config;
838 int lst_size, lst_per_page;
8910b49f 839 struct net_device *dev;
491976b2 840 int page_num = 0;
1da177e4
LT		 841
842 if (!nic)
843 return;
844
8910b49f
MG		 845 dev = nic->dev;
846
1da177e4
LT		 847 mac_control = &nic->mac_control;
848 config = &nic->config;
849
1ee6dd77 850 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 851 lst_per_page = PAGE_SIZE / lst_size;
852
853 for (i = 0; i < config->tx_fifo_num; i++) {
491976b2
SH		 854 ufo_size += config->tx_cfg[i].fifo_len;
855 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
856 lst_per_page);
1da177e4
LT		 857 for (j = 0; j < page_num; j++) {
858 int mem_blks = (j * lst_per_page);
776bd20f 859 if (!mac_control->fifos[i].list_info)
6aa20a22 860 return;
776bd20f 861 if (!mac_control->fifos[i].list_info[mem_blks].
862 list_virt_addr)
1da177e4
LT		 863 break;
864 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722
K		 865 mac_control->fifos[i].
866 list_info[mem_blks].
1da177e4 867 list_virt_addr,
20346722
K		 868 mac_control->fifos[i].
869 list_info[mem_blks].
1da177e4 870 list_phy_addr);
8a4bdbaa 871 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 872 += PAGE_SIZE;
1da177e4 873 }
776bd20f 874 /* If we got a zero DMA address during allocation,
875 * free the page now
876 */
877 if (mac_control->zerodma_virt_addr) {
878 pci_free_consistent(nic->pdev, PAGE_SIZE,
879 mac_control->zerodma_virt_addr,
880 (dma_addr_t)0);
6aa20a22 881 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 882 "%s: Freeing TxDL with zero DMA addr. ",
883 dev->name);
884 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
885 mac_control->zerodma_virt_addr);
8a4bdbaa 886 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 887 += PAGE_SIZE;
776bd20f 888 }
20346722 889 kfree(mac_control->fifos[i].list_info);
8a4bdbaa 890 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 891 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 892 }
893
1da177e4 894 size = SIZE_OF_BLOCK;
1da177e4 895 for (i = 0; i < config->rx_ring_num; i++) {
20346722 896 blk_cnt = mac_control->rings[i].block_count;
1da177e4 897 for (j = 0; j < blk_cnt; j++) {
20346722
K		 898 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
899 block_virt_addr;
900 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
901 block_dma_addr;
1da177e4
LT		 902 if (tmp_v_addr == NULL)
903 break;
904 pci_free_consistent(nic->pdev, size,
905 tmp_v_addr, tmp_p_addr);
491976b2 906 nic->mac_control.stats_info->sw_stat.mem_freed += size;
da6971d8 907 kfree(mac_control->rings[i].rx_blocks[j].rxds);
8a4bdbaa 908 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 909 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 910 }
911 }
912
6d517a27 913 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 914 /* Freeing buffer storage addresses in 2BUFF mode. */
915 for (i = 0; i < config->rx_ring_num; i++) {
916 blk_cnt = config->rx_cfg[i].num_rxd /
917 (rxd_count[nic->rxd_mode] + 1);
918 for (j = 0; j < blk_cnt; j++) {
919 int k = 0;
920 if (!mac_control->rings[i].ba[j])
921 continue;
922 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 923 struct buffAdd *ba =
da6971d8
AR		 924 &mac_control->rings[i].ba[j][k];
925 kfree(ba->ba_0_org);
491976b2
SH		 926 nic->mac_control.stats_info->sw_stat.\
927 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 928 kfree(ba->ba_1_org);
491976b2
SH		 929 nic->mac_control.stats_info->sw_stat.\
930 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 931 k++;
932 }
933 kfree(mac_control->rings[i].ba[j]);
9caab458
SS		 934 nic->mac_control.stats_info->sw_stat.mem_freed +=
935 (sizeof(struct buffAdd) *
936 (rxd_count[nic->rxd_mode] + 1));
1da177e4 937 }
da6971d8 938 kfree(mac_control->rings[i].ba);
8a4bdbaa 939 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 940 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 941 }
1da177e4 942 }
1da177e4
LT		 943
944 if (mac_control->stats_mem) {
945 pci_free_consistent(nic->pdev,
946 mac_control->stats_mem_sz,
947 mac_control->stats_mem,
948 mac_control->stats_mem_phy);
8a4bdbaa 949 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 950 mac_control->stats_mem_sz;
1da177e4 951 }
491976b2 952 if (nic->ufo_in_band_v) {
fed5eccd 953 kfree(nic->ufo_in_band_v);
8a4bdbaa 954 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 955 += (ufo_size * sizeof(u64));
956 }
1da177e4
LT		 957}
958
541ae68f
K		 959/**
960 * s2io_verify_pci_mode -
961 */
962
1ee6dd77 963static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 964{
1ee6dd77 965 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 966 register u64 val64 = 0;
967 int mode;
968
969 val64 = readq(&bar0->pci_mode);
970 mode = (u8)GET_PCI_MODE(val64);
971
972 if ( val64 & PCI_MODE_UNKNOWN_MODE)
973 return -1; /* Unknown PCI mode */
974 return mode;
975}
976
c92ca04b
AR		 977#define NEC_VENID 0x1033
978#define NEC_DEVID 0x0125
979static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
980{
981 struct pci_dev *tdev = NULL;
26d36b64
AC		 982 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
983 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 984 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 985 pci_dev_put(tdev);
c92ca04b
AR		 986 return 1;
987 }
988 }
989 return 0;
990}
541ae68f 991
7b32a312 992static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 993/**
994 * s2io_print_pci_mode -
995 */
1ee6dd77 996static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 997{
1ee6dd77 998 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 999 register u64 val64 = 0;
1000 int mode;
1001 struct config_param *config = &nic->config;
1002
1003 val64 = readq(&bar0->pci_mode);
1004 mode = (u8)GET_PCI_MODE(val64);
1005
1006 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1007 return -1; /* Unknown PCI mode */
1008
c92ca04b
AR		 1009 config->bus_speed = bus_speed[mode];
1010
1011 if (s2io_on_nec_bridge(nic->pdev)) {
1012 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1013 nic->dev->name);
1014 return mode;
1015 }
1016
541ae68f
K		 1017 if (val64 & PCI_MODE_32_BITS) {
1018 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1019 } else {
1020 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1021 }
1022
1023 switch(mode) {
1024 case PCI_MODE_PCI_33:
1025 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f
K		 1026 break;
1027 case PCI_MODE_PCI_66:
1028 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f
K		 1029 break;
1030 case PCI_MODE_PCIX_M1_66:
1031 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f
K		 1032 break;
1033 case PCI_MODE_PCIX_M1_100:
1034 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f
K		 1035 break;
1036 case PCI_MODE_PCIX_M1_133:
1037 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f
K		 1038 break;
1039 case PCI_MODE_PCIX_M2_66:
1040 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f
K		 1041 break;
1042 case PCI_MODE_PCIX_M2_100:
1043 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f
K		 1044 break;
1045 case PCI_MODE_PCIX_M2_133:
1046 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f
K		 1047 break;
1048 default:
1049 return -1; /* Unsupported bus speed */
1050 }
1051
1052 return mode;
1053}
1054
20346722
K		 1055/**
1056 * init_nic - Initialization of hardware
1da177e4 1057 * @nic: device peivate variable
20346722
K		 1058 * Description: The function sequentially configures every block
1059 * of the H/W from their reset values.
1060 * Return Value: SUCCESS on success and
1da177e4
LT		 1061 * '-1' on failure (endian settings incorrect).
1062 */
1063
1064static int init_nic(struct s2io_nic *nic)
1065{
1ee6dd77 1066 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1067 struct net_device *dev = nic->dev;
1068 register u64 val64 = 0;
1069 void __iomem *add;
1070 u32 time;
1071 int i, j;
1ee6dd77 1072 struct mac_info *mac_control;
1da177e4 1073 struct config_param *config;
c92ca04b 1074 int dtx_cnt = 0;
1da177e4 1075 unsigned long long mem_share;
20346722 1076 int mem_size;
1da177e4
LT		 1077
1078 mac_control = &nic->mac_control;
1079 config = &nic->config;
1080
5e25b9dd 1081 /* to set the swapper controle on the card */
20346722 1082 if(s2io_set_swapper(nic)) {
1da177e4
LT		 1083 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1084 return -1;
1085 }
1086
541ae68f
K		 1087 /*
1088 * Herc requires EOI to be removed from reset before XGXS, so..
1089 */
1090 if (nic->device_type & XFRAME_II_DEVICE) {
1091 val64 = 0xA500000000ULL;
1092 writeq(val64, &bar0->sw_reset);
1093 msleep(500);
1094 val64 = readq(&bar0->sw_reset);
1095 }
1096
1da177e4
LT		 1097 /* Remove XGXS from reset state */
1098 val64 = 0;
1099 writeq(val64, &bar0->sw_reset);
1da177e4 1100 msleep(500);
20346722 1101 val64 = readq(&bar0->sw_reset);
1da177e4
LT		 1102
1103 /* Enable Receiving broadcasts */
1104 add = &bar0->mac_cfg;
1105 val64 = readq(&bar0->mac_cfg);
1106 val64 |= MAC_RMAC_BCAST_ENABLE;
1107 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1108 writel((u32) val64, add);
1109 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1110 writel((u32) (val64 >> 32), (add + 4));
1111
1112 /* Read registers in all blocks */
1113 val64 = readq(&bar0->mac_int_mask);
1114 val64 = readq(&bar0->mc_int_mask);
1115 val64 = readq(&bar0->xgxs_int_mask);
1116
1117 /* Set MTU */
1118 val64 = dev->mtu;
1119 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1120
541ae68f
K		 1121 if (nic->device_type & XFRAME_II_DEVICE) {
1122 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1123 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1124 &bar0->dtx_control, UF);
541ae68f
K		 1125 if (dtx_cnt & 0x1)
1126 msleep(1); /* Necessary!! */
1da177e4
LT		 1127 dtx_cnt++;
1128 }
541ae68f 1129 } else {
c92ca04b
AR		 1130 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1131 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1132 &bar0->dtx_control, UF);
1133 val64 = readq(&bar0->dtx_control);
1134 dtx_cnt++;
1da177e4
LT		 1135 }
1136 }
1137
1138 /* Tx DMA Initialization */
1139 val64 = 0;
1140 writeq(val64, &bar0->tx_fifo_partition_0);
1141 writeq(val64, &bar0->tx_fifo_partition_1);
1142 writeq(val64, &bar0->tx_fifo_partition_2);
1143 writeq(val64, &bar0->tx_fifo_partition_3);
1144
1145
1146 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1147 val64 |=
1148 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1149 13) | vBIT(config->tx_cfg[i].fifo_priority,
1150 ((i * 32) + 5), 3);
1151
1152 if (i == (config->tx_fifo_num - 1)) {
1153 if (i % 2 == 0)
1154 i++;
1155 }
1156
1157 switch (i) {
1158 case 1:
1159 writeq(val64, &bar0->tx_fifo_partition_0);
1160 val64 = 0;
1161 break;
1162 case 3:
1163 writeq(val64, &bar0->tx_fifo_partition_1);
1164 val64 = 0;
1165 break;
1166 case 5:
1167 writeq(val64, &bar0->tx_fifo_partition_2);
1168 val64 = 0;
1169 break;
1170 case 7:
1171 writeq(val64, &bar0->tx_fifo_partition_3);
1172 break;
1173 }
1174 }
1175
5e25b9dd
K		 1176 /*
1177 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1178 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1179 */
541ae68f 1180 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1181 (nic->pdev->revision < 4))
5e25b9dd
K		 1182 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1183
1da177e4
LT		 1184 val64 = readq(&bar0->tx_fifo_partition_0);
1185 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1186 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1187
20346722
K		 1188 /*
1189 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1190 * integrity checking.
1191 */
1192 val64 = readq(&bar0->tx_pa_cfg);
1193 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1194 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1195 writeq(val64, &bar0->tx_pa_cfg);
1196
1197 /* Rx DMA intialization. */
1198 val64 = 0;
1199 for (i = 0; i < config->rx_ring_num; i++) {
1200 val64 |=
1201 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1202 3);
1203 }
1204 writeq(val64, &bar0->rx_queue_priority);
1205
20346722
K		 1206 /*
1207 * Allocating equal share of memory to all the
1da177e4
LT		 1208 * configured Rings.
1209 */
1210 val64 = 0;
541ae68f
K		 1211 if (nic->device_type & XFRAME_II_DEVICE)
1212 mem_size = 32;
1213 else
1214 mem_size = 64;
1215
1da177e4
LT		 1216 for (i = 0; i < config->rx_ring_num; i++) {
1217 switch (i) {
1218 case 0:
20346722
K		 1219 mem_share = (mem_size / config->rx_ring_num +
1220 mem_size % config->rx_ring_num);
1da177e4
LT		 1221 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1222 continue;
1223 case 1:
20346722 1224 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1225 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1226 continue;
1227 case 2:
20346722 1228 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1229 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1230 continue;
1231 case 3:
20346722 1232 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1233 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1234 continue;
1235 case 4:
20346722 1236 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1237 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1238 continue;
1239 case 5:
20346722 1240 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1241 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1242 continue;
1243 case 6:
20346722 1244 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1245 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1246 continue;
1247 case 7:
20346722 1248 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1249 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1250 continue;
1251 }
1252 }
1253 writeq(val64, &bar0->rx_queue_cfg);
1254
20346722 1255 /*
5e25b9dd
K		 1256 * Filling Tx round robin registers
1257 * as per the number of FIFOs
1da177e4 1258 */
5e25b9dd
K		 1259 switch (config->tx_fifo_num) {
1260 case 1:
1261 val64 = 0x0000000000000000ULL;
1262 writeq(val64, &bar0->tx_w_round_robin_0);
1263 writeq(val64, &bar0->tx_w_round_robin_1);
1264 writeq(val64, &bar0->tx_w_round_robin_2);
1265 writeq(val64, &bar0->tx_w_round_robin_3);
1266 writeq(val64, &bar0->tx_w_round_robin_4);
1267 break;
1268 case 2:
1269 val64 = 0x0000010000010000ULL;
1270 writeq(val64, &bar0->tx_w_round_robin_0);
1271 val64 = 0x0100000100000100ULL;
1272 writeq(val64, &bar0->tx_w_round_robin_1);
1273 val64 = 0x0001000001000001ULL;
1274 writeq(val64, &bar0->tx_w_round_robin_2);
1275 val64 = 0x0000010000010000ULL;
1276 writeq(val64, &bar0->tx_w_round_robin_3);
1277 val64 = 0x0100000000000000ULL;
1278 writeq(val64, &bar0->tx_w_round_robin_4);
1279 break;
1280 case 3:
1281 val64 = 0x0001000102000001ULL;
1282 writeq(val64, &bar0->tx_w_round_robin_0);
1283 val64 = 0x0001020000010001ULL;
1284 writeq(val64, &bar0->tx_w_round_robin_1);
1285 val64 = 0x0200000100010200ULL;
1286 writeq(val64, &bar0->tx_w_round_robin_2);
1287 val64 = 0x0001000102000001ULL;
1288 writeq(val64, &bar0->tx_w_round_robin_3);
1289 val64 = 0x0001020000000000ULL;
1290 writeq(val64, &bar0->tx_w_round_robin_4);
1291 break;
1292 case 4:
1293 val64 = 0x0001020300010200ULL;
1294 writeq(val64, &bar0->tx_w_round_robin_0);
1295 val64 = 0x0100000102030001ULL;
1296 writeq(val64, &bar0->tx_w_round_robin_1);
1297 val64 = 0x0200010000010203ULL;
1298 writeq(val64, &bar0->tx_w_round_robin_2);
1299 val64 = 0x0001020001000001ULL;
1300 writeq(val64, &bar0->tx_w_round_robin_3);
1301 val64 = 0x0203000100000000ULL;
1302 writeq(val64, &bar0->tx_w_round_robin_4);
1303 break;
1304 case 5:
1305 val64 = 0x0001000203000102ULL;
1306 writeq(val64, &bar0->tx_w_round_robin_0);
1307 val64 = 0x0001020001030004ULL;
1308 writeq(val64, &bar0->tx_w_round_robin_1);
1309 val64 = 0x0001000203000102ULL;
1310 writeq(val64, &bar0->tx_w_round_robin_2);
1311 val64 = 0x0001020001030004ULL;
1312 writeq(val64, &bar0->tx_w_round_robin_3);
1313 val64 = 0x0001000000000000ULL;
1314 writeq(val64, &bar0->tx_w_round_robin_4);
1315 break;
1316 case 6:
1317 val64 = 0x0001020304000102ULL;
1318 writeq(val64, &bar0->tx_w_round_robin_0);
1319 val64 = 0x0304050001020001ULL;
1320 writeq(val64, &bar0->tx_w_round_robin_1);
1321 val64 = 0x0203000100000102ULL;
1322 writeq(val64, &bar0->tx_w_round_robin_2);
1323 val64 = 0x0304000102030405ULL;
1324 writeq(val64, &bar0->tx_w_round_robin_3);
1325 val64 = 0x0001000200000000ULL;
1326 writeq(val64, &bar0->tx_w_round_robin_4);
1327 break;
1328 case 7:
1329 val64 = 0x0001020001020300ULL;
1330 writeq(val64, &bar0->tx_w_round_robin_0);
1331 val64 = 0x0102030400010203ULL;
1332 writeq(val64, &bar0->tx_w_round_robin_1);
1333 val64 = 0x0405060001020001ULL;
1334 writeq(val64, &bar0->tx_w_round_robin_2);
1335 val64 = 0x0304050000010200ULL;
1336 writeq(val64, &bar0->tx_w_round_robin_3);
1337 val64 = 0x0102030000000000ULL;
1338 writeq(val64, &bar0->tx_w_round_robin_4);
1339 break;
1340 case 8:
1341 val64 = 0x0001020300040105ULL;
1342 writeq(val64, &bar0->tx_w_round_robin_0);
1343 val64 = 0x0200030106000204ULL;
1344 writeq(val64, &bar0->tx_w_round_robin_1);
1345 val64 = 0x0103000502010007ULL;
1346 writeq(val64, &bar0->tx_w_round_robin_2);
1347 val64 = 0x0304010002060500ULL;
1348 writeq(val64, &bar0->tx_w_round_robin_3);
1349 val64 = 0x0103020400000000ULL;
1350 writeq(val64, &bar0->tx_w_round_robin_4);
1351 break;
1352 }
1353
b41477f3 1354 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1355 val64 = readq(&bar0->tx_fifo_partition_0);
1356 val64 |= (TX_FIFO_PARTITION_EN);
1357 writeq(val64, &bar0->tx_fifo_partition_0);
1358
5e25b9dd
K		 1359 /* Filling the Rx round robin registers as per the
1360 * number of Rings and steering based on QoS.
1361 */
1362 switch (config->rx_ring_num) {
1363 case 1:
1364 val64 = 0x8080808080808080ULL;
1365 writeq(val64, &bar0->rts_qos_steering);
1366 break;
1367 case 2:
1368 val64 = 0x0000010000010000ULL;
1369 writeq(val64, &bar0->rx_w_round_robin_0);
1370 val64 = 0x0100000100000100ULL;
1371 writeq(val64, &bar0->rx_w_round_robin_1);
1372 val64 = 0x0001000001000001ULL;
1373 writeq(val64, &bar0->rx_w_round_robin_2);
1374 val64 = 0x0000010000010000ULL;
1375 writeq(val64, &bar0->rx_w_round_robin_3);
1376 val64 = 0x0100000000000000ULL;
1377 writeq(val64, &bar0->rx_w_round_robin_4);
1378
1379 val64 = 0x8080808040404040ULL;
1380 writeq(val64, &bar0->rts_qos_steering);
1381 break;
1382 case 3:
1383 val64 = 0x0001000102000001ULL;
1384 writeq(val64, &bar0->rx_w_round_robin_0);
1385 val64 = 0x0001020000010001ULL;
1386 writeq(val64, &bar0->rx_w_round_robin_1);
1387 val64 = 0x0200000100010200ULL;
1388 writeq(val64, &bar0->rx_w_round_robin_2);
1389 val64 = 0x0001000102000001ULL;
1390 writeq(val64, &bar0->rx_w_round_robin_3);
1391 val64 = 0x0001020000000000ULL;
1392 writeq(val64, &bar0->rx_w_round_robin_4);
1393
1394 val64 = 0x8080804040402020ULL;
1395 writeq(val64, &bar0->rts_qos_steering);
1396 break;
1397 case 4:
1398 val64 = 0x0001020300010200ULL;
1399 writeq(val64, &bar0->rx_w_round_robin_0);
1400 val64 = 0x0100000102030001ULL;
1401 writeq(val64, &bar0->rx_w_round_robin_1);
1402 val64 = 0x0200010000010203ULL;
1403 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1404 val64 = 0x0001020001000001ULL;
5e25b9dd
K		 1405 writeq(val64, &bar0->rx_w_round_robin_3);
1406 val64 = 0x0203000100000000ULL;
1407 writeq(val64, &bar0->rx_w_round_robin_4);
1408
1409 val64 = 0x8080404020201010ULL;
1410 writeq(val64, &bar0->rts_qos_steering);
1411 break;
1412 case 5:
1413 val64 = 0x0001000203000102ULL;
1414 writeq(val64, &bar0->rx_w_round_robin_0);
1415 val64 = 0x0001020001030004ULL;
1416 writeq(val64, &bar0->rx_w_round_robin_1);
1417 val64 = 0x0001000203000102ULL;
1418 writeq(val64, &bar0->rx_w_round_robin_2);
1419 val64 = 0x0001020001030004ULL;
1420 writeq(val64, &bar0->rx_w_round_robin_3);
1421 val64 = 0x0001000000000000ULL;
1422 writeq(val64, &bar0->rx_w_round_robin_4);
1423
1424 val64 = 0x8080404020201008ULL;
1425 writeq(val64, &bar0->rts_qos_steering);
1426 break;
1427 case 6:
1428 val64 = 0x0001020304000102ULL;
1429 writeq(val64, &bar0->rx_w_round_robin_0);
1430 val64 = 0x0304050001020001ULL;
1431 writeq(val64, &bar0->rx_w_round_robin_1);
1432 val64 = 0x0203000100000102ULL;
1433 writeq(val64, &bar0->rx_w_round_robin_2);
1434 val64 = 0x0304000102030405ULL;
1435 writeq(val64, &bar0->rx_w_round_robin_3);
1436 val64 = 0x0001000200000000ULL;
1437 writeq(val64, &bar0->rx_w_round_robin_4);
1438
1439 val64 = 0x8080404020100804ULL;
1440 writeq(val64, &bar0->rts_qos_steering);
1441 break;
1442 case 7:
1443 val64 = 0x0001020001020300ULL;
1444 writeq(val64, &bar0->rx_w_round_robin_0);
1445 val64 = 0x0102030400010203ULL;
1446 writeq(val64, &bar0->rx_w_round_robin_1);
1447 val64 = 0x0405060001020001ULL;
1448 writeq(val64, &bar0->rx_w_round_robin_2);
1449 val64 = 0x0304050000010200ULL;
1450 writeq(val64, &bar0->rx_w_round_robin_3);
1451 val64 = 0x0102030000000000ULL;
1452 writeq(val64, &bar0->rx_w_round_robin_4);
1453
1454 val64 = 0x8080402010080402ULL;
1455 writeq(val64, &bar0->rts_qos_steering);
1456 break;
1457 case 8:
1458 val64 = 0x0001020300040105ULL;
1459 writeq(val64, &bar0->rx_w_round_robin_0);
1460 val64 = 0x0200030106000204ULL;
1461 writeq(val64, &bar0->rx_w_round_robin_1);
1462 val64 = 0x0103000502010007ULL;
1463 writeq(val64, &bar0->rx_w_round_robin_2);
1464 val64 = 0x0304010002060500ULL;
1465 writeq(val64, &bar0->rx_w_round_robin_3);
1466 val64 = 0x0103020400000000ULL;
1467 writeq(val64, &bar0->rx_w_round_robin_4);
1468
1469 val64 = 0x8040201008040201ULL;
1470 writeq(val64, &bar0->rts_qos_steering);
1471 break;
1472 }
1da177e4
LT		 1473
1474 /* UDP Fix */
1475 val64 = 0;
20346722 1476 for (i = 0; i < 8; i++)
1da177e4
LT		 1477 writeq(val64, &bar0->rts_frm_len_n[i]);
1478
5e25b9dd
K		 1479 /* Set the default rts frame length for the rings configured */
1480 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1481 for (i = 0 ; i < config->rx_ring_num ; i++)
1482 writeq(val64, &bar0->rts_frm_len_n[i]);
1483
1484 /* Set the frame length for the configured rings
1485 * desired by the user
1486 */
1487 for (i = 0; i < config->rx_ring_num; i++) {
1488 /* If rts_frm_len[i] == 0 then it is assumed that user not
1489 * specified frame length steering.
1490 * If the user provides the frame length then program
1491 * the rts_frm_len register for those values or else
1492 * leave it as it is.
1493 */
1494 if (rts_frm_len[i] != 0) {
1495 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1496 &bar0->rts_frm_len_n[i]);
1497 }
1498 }
8a4bdbaa 1499
9fc93a41
SS		 1500 /* Disable differentiated services steering logic */
1501 for (i = 0; i < 64; i++) {
1502 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1503 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1504 dev->name);
1505 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1506 return FAILURE;
1507 }
1508 }
1509
20346722 1510 /* Program statistics memory */
1da177e4 1511 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1512
541ae68f
K		 1513 if (nic->device_type == XFRAME_II_DEVICE) {
1514 val64 = STAT_BC(0x320);
1515 writeq(val64, &bar0->stat_byte_cnt);
1516 }
1517
20346722 1518 /*
1da177e4
LT		 1519 * Initializing the sampling rate for the device to calculate the
1520 * bandwidth utilization.
1521 */
1522 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1523 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1524 writeq(val64, &bar0->mac_link_util);
1525
1526
20346722
K		 1527 /*
1528 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1529 * Scheme.
1530 */
20346722
K		 1531 /*
1532 * TTI Initialization. Default Tx timer gets us about
1da177e4
LT		 1533 * 250 interrupts per sec. Continuous interrupts are enabled
1534 * by default.
1535 */
541ae68f
K		 1536 if (nic->device_type == XFRAME_II_DEVICE) {
1537 int count = (nic->config.bus_speed * 125)/2;
1538 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1539 } else {
1540
1541 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1542 }
1543 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1da177e4 1544 TTI_DATA1_MEM_TX_URNG_B(0x10) |
5e25b9dd 1545 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
541ae68f
K		 1546 if (use_continuous_tx_intrs)
1547 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1da177e4
LT		 1548 writeq(val64, &bar0->tti_data1_mem);
1549
1550 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1551 TTI_DATA2_MEM_TX_UFC_B(0x20) |
19a60522 1552 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1da177e4
LT		 1553 writeq(val64, &bar0->tti_data2_mem);
1554
1555 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1556 writeq(val64, &bar0->tti_command_mem);
1557
20346722 1558 /*
1da177e4
LT		 1559 * Once the operation completes, the Strobe bit of the command
1560 * register will be reset. We poll for this particular condition
1561 * We wait for a maximum of 500ms for the operation to complete,
1562 * if it's not complete by then we return error.
1563 */
1564 time = 0;
1565 while (TRUE) {
1566 val64 = readq(&bar0->tti_command_mem);
1567 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1568 break;
1569 }
1570 if (time > 10) {
1571 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1572 dev->name);
1573 return -1;
1574 }
1575 msleep(50);
1576 time++;
1577 }
1578
8a4bdbaa
SS		 1579 /* RTI Initialization */
1580 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1581 /*
8a4bdbaa
SS		 1582 * Programmed to generate Apprx 500 Intrs per
1583 * second
1584 */
1585 int count = (nic->config.bus_speed * 125)/4;
1586 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1587 } else
1588 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1589 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1590 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1591 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1592
1593 writeq(val64, &bar0->rti_data1_mem);
1594
1595 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1596 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1597 if (nic->config.intr_type == MSI_X)
1598 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1599 RTI_DATA2_MEM_RX_UFC_D(0x40));
1600 else
1601 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1602 RTI_DATA2_MEM_RX_UFC_D(0x80));
1603 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1604
8a4bdbaa
SS		 1605 for (i = 0; i < config->rx_ring_num; i++) {
1606 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1607 | RTI_CMD_MEM_OFFSET(i);
1608 writeq(val64, &bar0->rti_command_mem);
1da177e4 1609
8a4bdbaa
SS		 1610 /*
1611 * Once the operation completes, the Strobe bit of the
1612 * command register will be reset. We poll for this
1613 * particular condition. We wait for a maximum of 500ms
1614 * for the operation to complete, if it's not complete
1615 * by then we return error.
1616 */
1617 time = 0;
1618 while (TRUE) {
1619 val64 = readq(&bar0->rti_command_mem);
1620 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1621 break;
b6e3f982 1622
8a4bdbaa
SS		 1623 if (time > 10) {
1624 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1625 dev->name);
1626 return -1;
b6e3f982 1627 }
8a4bdbaa
SS		 1628 time++;
1629 msleep(50);
1da177e4 1630 }
1da177e4
LT		 1631 }
1632
20346722
K		 1633 /*
1634 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1635 * the 8 Queues on Rx side.
1636 */
1637 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1638 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1639
1640 /* Disable RMAC PAD STRIPPING */
509a2671 1641 add = &bar0->mac_cfg;
1da177e4
LT		 1642 val64 = readq(&bar0->mac_cfg);
1643 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1644 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1645 writel((u32) (val64), add);
1646 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1647 writel((u32) (val64 >> 32), (add + 4));
1648 val64 = readq(&bar0->mac_cfg);
1649
7d3d0439
RA		 1650 /* Enable FCS stripping by adapter */
1651 add = &bar0->mac_cfg;
1652 val64 = readq(&bar0->mac_cfg);
1653 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1654 if (nic->device_type == XFRAME_II_DEVICE)
1655 writeq(val64, &bar0->mac_cfg);
1656 else {
1657 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1658 writel((u32) (val64), add);
1659 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1660 writel((u32) (val64 >> 32), (add + 4));
1661 }
1662
20346722
K		 1663 /*
1664 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1665 * generated by xena.
1666 */
1667 val64 = readq(&bar0->rmac_pause_cfg);
1668 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1669 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1670 writeq(val64, &bar0->rmac_pause_cfg);
1671
20346722 1672 /*
1da177e4
LT		 1673 * Set the Threshold Limit for Generating the pause frame
1674 * If the amount of data in any Queue exceeds ratio of
1675 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1676 * pause frame is generated
1677 */
1678 val64 = 0;
1679 for (i = 0; i < 4; i++) {
1680 val64 |=
1681 (((u64) 0xFF00 | nic->mac_control.
1682 mc_pause_threshold_q0q3)
1683 << (i * 2 * 8));
1684 }
1685 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1686
1687 val64 = 0;
1688 for (i = 0; i < 4; i++) {
1689 val64 |=
1690 (((u64) 0xFF00 | nic->mac_control.
1691 mc_pause_threshold_q4q7)
1692 << (i * 2 * 8));
1693 }
1694 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1695
20346722
K		 1696 /*
1697 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1698 * exceeded the limit pointed by shared_splits
1699 */
1700 val64 = readq(&bar0->pic_control);
1701 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1702 writeq(val64, &bar0->pic_control);
1703
863c11a9
AR		 1704 if (nic->config.bus_speed == 266) {
1705 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1706 writeq(0x0, &bar0->read_retry_delay);
1707 writeq(0x0, &bar0->write_retry_delay);
1708 }
1709
541ae68f
K		 1710 /*
1711 * Programming the Herc to split every write transaction
1712 * that does not start on an ADB to reduce disconnects.
1713 */
1714 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1715 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1716 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1717 writeq(val64, &bar0->misc_control);
1718 val64 = readq(&bar0->pic_control2);
b7b5a128 1719 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1720 writeq(val64, &bar0->pic_control2);
541ae68f 1721 }
c92ca04b
AR		 1722 if (strstr(nic->product_name, "CX4")) {
1723 val64 = TMAC_AVG_IPG(0x17);
1724 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1725 }
1726
1da177e4
LT		 1727 return SUCCESS;
1728}
a371a07d
K		 1729#define LINK_UP_DOWN_INTERRUPT 1
1730#define MAC_RMAC_ERR_TIMER 2
1731
1ee6dd77 1732static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1733{
eaae7f72 1734 if (nic->config.intr_type != INTA)
cc6e7c44 1735 return MAC_RMAC_ERR_TIMER;
a371a07d
K		 1736 if (nic->device_type == XFRAME_II_DEVICE)
1737 return LINK_UP_DOWN_INTERRUPT;
1738 else
1739 return MAC_RMAC_ERR_TIMER;
1740}
8116f3cf 1741
9caab458
SS		 1742/**
1743 * do_s2io_write_bits - update alarm bits in alarm register
1744 * @value: alarm bits
1745 * @flag: interrupt status
1746 * @addr: address value
1747 * Description: update alarm bits in alarm register
1748 * Return Value:
1749 * NONE.
1750 */
1751static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1752{
1753 u64 temp64;
1754
1755 temp64 = readq(addr);
1756
1757 if(flag == ENABLE_INTRS)
1758 temp64 &= ~((u64) value);
1759 else
1760 temp64 |= ((u64) value);
1761 writeq(temp64, addr);
1762}
1da177e4 1763
43b7c451 1764static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1765{
1766 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1767 register u64 gen_int_mask = 0;
1768
1769 if (mask & TX_DMA_INTR) {
1770
1771 gen_int_mask |= TXDMA_INT_M;
1772
1773 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1774 TXDMA_PCC_INT | TXDMA_TTI_INT |
1775 TXDMA_LSO_INT | TXDMA_TPA_INT |
1776 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1777
1778 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1779 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1780 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1781 &bar0->pfc_err_mask);
1782
1783 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1784 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1785 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1786
1787 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1788 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1789 PCC_N_SERR | PCC_6_COF_OV_ERR |
1790 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1791 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1792 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1793
1794 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1795 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1796
1797 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1798 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1799 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1800 flag, &bar0->lso_err_mask);
1801
1802 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1803 flag, &bar0->tpa_err_mask);
1804
1805 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1806
1807 }
1808
1809 if (mask & TX_MAC_INTR) {
1810 gen_int_mask |= TXMAC_INT_M;
1811 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1812 &bar0->mac_int_mask);
1813 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1814 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1815 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1816 flag, &bar0->mac_tmac_err_mask);
1817 }
1818
1819 if (mask & TX_XGXS_INTR) {
1820 gen_int_mask |= TXXGXS_INT_M;
1821 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1822 &bar0->xgxs_int_mask);
1823 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1824 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1825 flag, &bar0->xgxs_txgxs_err_mask);
1826 }
1827
1828 if (mask & RX_DMA_INTR) {
1829 gen_int_mask |= RXDMA_INT_M;
1830 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1831 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1832 flag, &bar0->rxdma_int_mask);
1833 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1834 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1835 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1836 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1837 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1838 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1839 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1840 &bar0->prc_pcix_err_mask);
1841 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1842 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1843 &bar0->rpa_err_mask);
1844 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1845 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1846 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1847 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1848 flag, &bar0->rda_err_mask);
1849 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1850 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1851 flag, &bar0->rti_err_mask);
1852 }
1853
1854 if (mask & RX_MAC_INTR) {
1855 gen_int_mask |= RXMAC_INT_M;
1856 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1857 &bar0->mac_int_mask);
1858 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1859 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1860 RMAC_DOUBLE_ECC_ERR |
1861 RMAC_LINK_STATE_CHANGE_INT,
1862 flag, &bar0->mac_rmac_err_mask);
1863 }
1864
1865 if (mask & RX_XGXS_INTR)
1866 {
1867 gen_int_mask |= RXXGXS_INT_M;
1868 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1869 &bar0->xgxs_int_mask);
1870 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1871 &bar0->xgxs_rxgxs_err_mask);
1872 }
1873
1874 if (mask & MC_INTR) {
1875 gen_int_mask |= MC_INT_M;
1876 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
1877 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1878 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1879 &bar0->mc_err_mask);
1880 }
1881 nic->general_int_mask = gen_int_mask;
1882
1883 /* Remove this line when alarm interrupts are enabled */
1884 nic->general_int_mask = 0;
1885}
20346722
K		 1886/**
1887 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 1888 * @nic: device private variable,
1889 * @mask: A mask indicating which Intr block must be modified and,
1890 * @flag: A flag indicating whether to enable or disable the Intrs.
1891 * Description: This function will either disable or enable the interrupts
20346722
K		 1892 * depending on the flag argument. The mask argument can be used to
1893 * enable/disable any Intr block.
1da177e4
LT		 1894 * Return Value: NONE.
1895 */
1896
1897static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1898{
1ee6dd77 1899 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 1900 register u64 temp64 = 0, intr_mask = 0;
1901
1902 intr_mask = nic->general_int_mask;
1da177e4
LT		 1903
1904 /* Top level interrupt classification */
1905 /* PIC Interrupts */
9caab458 1906 if (mask & TX_PIC_INTR) {
1da177e4 1907 /* Enable PIC Intrs in the general intr mask register */
9caab458 1908 intr_mask |= TXPIC_INT_M;
1da177e4 1909 if (flag == ENABLE_INTRS) {
20346722 1910 /*
a371a07d 1911 * If Hercules adapter enable GPIO otherwise
b41477f3 1912 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 1913 * interrupts for now.
1914 * TODO
1da177e4 1915 */
a371a07d
K		 1916 if (s2io_link_fault_indication(nic) ==
1917 LINK_UP_DOWN_INTERRUPT ) {
9caab458
SS		 1918 do_s2io_write_bits(PIC_INT_GPIO, flag,
1919 &bar0->pic_int_mask);
1920 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
1921 &bar0->gpio_int_mask);
1922 } else
a371a07d 1923 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 1924 } else if (flag == DISABLE_INTRS) {
20346722
K		 1925 /*
1926 * Disable PIC Intrs in the general
1927 * intr mask register
1da177e4
LT		 1928 */
1929 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 1930 }
1931 }
1932
1da177e4
LT		 1933 /* Tx traffic interrupts */
1934 if (mask & TX_TRAFFIC_INTR) {
9caab458 1935 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 1936 if (flag == ENABLE_INTRS) {
20346722 1937 /*
1da177e4 1938 * Enable all the Tx side interrupts
20346722 1939 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 1940 */
1941 writeq(0x0, &bar0->tx_traffic_mask);
1942 } else if (flag == DISABLE_INTRS) {
20346722
K		 1943 /*
1944 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 1945 * register.
1946 */
1947 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 1948 }
1949 }
1950
1951 /* Rx traffic interrupts */
1952 if (mask & RX_TRAFFIC_INTR) {
9caab458 1953 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 1954 if (flag == ENABLE_INTRS) {
1da177e4
LT		 1955 /* writing 0 Enables all 8 RX interrupt levels */
1956 writeq(0x0, &bar0->rx_traffic_mask);
1957 } else if (flag == DISABLE_INTRS) {
20346722
K		 1958 /*
1959 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 1960 * register.
1961 */
1962 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 1963 }
1964 }
9caab458
SS		 1965
1966 temp64 = readq(&bar0->general_int_mask);
1967 if (flag == ENABLE_INTRS)
1968 temp64 &= ~((u64) intr_mask);
1969 else
1970 temp64 = DISABLE_ALL_INTRS;
1971 writeq(temp64, &bar0->general_int_mask);
1972
1973 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 1974}
1975
19a60522
SS		 1976/**
1977 * verify_pcc_quiescent- Checks for PCC quiescent state
1978 * Return: 1 If PCC is quiescence
1979 * 0 If PCC is not quiescence
1980 */
1ee6dd77 1981static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 1982{
19a60522 1983 int ret = 0, herc;
1ee6dd77 1984 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 1985 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 1986
19a60522 1987 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722
K		 1988
1989 if (flag == FALSE) {
44c10138 1990 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 1991 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1992 ret = 1;
19a60522
SS		 1993 } else {
1994 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1995 ret = 1;
20346722
K		 1996 }
1997 } else {
44c10138 1998 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 1999 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2000 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2001 ret = 1;
5e25b9dd
K		 2002 } else {
2003 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2004 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2005 ret = 1;
20346722
K		 2006 }
2007 }
2008
2009 return ret;
2010}
2011/**
2012 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2013 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2014 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2015 * differs and the calling function passes the input argument flag to
2016 * indicate this.
20346722 2017 * Return: 1 If xena is quiescence
1da177e4
LT		 2018 * 0 If Xena is not quiescence
2019 */
2020
1ee6dd77 2021static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2022{
19a60522 2023 int mode;
1ee6dd77 2024 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2025 u64 val64 = readq(&bar0->adapter_status);
2026 mode = s2io_verify_pci_mode(sp);
1da177e4 2027
19a60522
SS		 2028 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2029 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2030 return 0;
2031 }
2032 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2033 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2034 return 0;
2035 }
2036 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2037 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2038 return 0;
2039 }
2040 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2041 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2042 return 0;
2043 }
2044 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2045 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2046 return 0;
2047 }
2048 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2049 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2050 return 0;
2051 }
2052 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2053 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2054 return 0;
2055 }
2056 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2057 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2058 return 0;
1da177e4
LT		 2059 }
2060
19a60522
SS		 2061 /*
2062 * In PCI 33 mode, the P_PLL is not used, and therefore,
2063 * the the P_PLL_LOCK bit in the adapter_status register will
2064 * not be asserted.
2065 */
2066 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2067 sp->device_type == XFRAME_II_DEVICE && mode !=
2068 PCI_MODE_PCI_33) {
2069 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2070 return 0;
2071 }
2072 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2073 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2074 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2075 return 0;
2076 }
2077 return 1;
1da177e4
LT		 2078}
2079
2080/**
2081 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2082 * @sp: Pointer to device specifc structure
20346722 2083 * Description :
1da177e4
LT		 2084 * New procedure to clear mac address reading problems on Alpha platforms
2085 *
2086 */
2087
1ee6dd77 2088static void fix_mac_address(struct s2io_nic * sp)
1da177e4 2089{
1ee6dd77 2090 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2091 u64 val64;
2092 int i = 0;
2093
2094 while (fix_mac[i] != END_SIGN) {
2095 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2096 udelay(10);
1da177e4
LT		 2097 val64 = readq(&bar0->gpio_control);
2098 }
2099}
2100
2101/**
20346722 2102 * start_nic - Turns the device on
1da177e4 2103 * @nic : device private variable.
20346722
K		 2104 * Description:
2105 * This function actually turns the device on. Before this function is
2106 * called,all Registers are configured from their reset states
2107 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2108 * calling this function, the device interrupts are cleared and the NIC is
2109 * literally switched on by writing into the adapter control register.
20346722 2110 * Return Value:
1da177e4
LT		 2111 * SUCCESS on success and -1 on failure.
2112 */
2113
2114static int start_nic(struct s2io_nic *nic)
2115{
1ee6dd77 2116 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2117 struct net_device *dev = nic->dev;
2118 register u64 val64 = 0;
20346722 2119 u16 subid, i;
1ee6dd77 2120 struct mac_info *mac_control;
1da177e4
LT		 2121 struct config_param *config;
2122
2123 mac_control = &nic->mac_control;
2124 config = &nic->config;
2125
2126 /* PRC Initialization and configuration */
2127 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2128 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2129 &bar0->prc_rxd0_n[i]);
2130
2131 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2132 if (nic->rxd_mode == RXD_MODE_1)
2133 val64 |= PRC_CTRL_RC_ENABLED;
2134 else
2135 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2136 if (nic->device_type == XFRAME_II_DEVICE)
2137 val64 |= PRC_CTRL_GROUP_READS;
2138 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2139 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2140 writeq(val64, &bar0->prc_ctrl_n[i]);
2141 }
2142
da6971d8
AR		 2143 if (nic->rxd_mode == RXD_MODE_3B) {
2144 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2145 val64 = readq(&bar0->rx_pa_cfg);
2146 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2147 writeq(val64, &bar0->rx_pa_cfg);
2148 }
1da177e4 2149
926930b2
SS		 2150 if (vlan_tag_strip == 0) {
2151 val64 = readq(&bar0->rx_pa_cfg);
2152 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2153 writeq(val64, &bar0->rx_pa_cfg);
2154 vlan_strip_flag = 0;
2155 }
2156
20346722 2157 /*
1da177e4
LT		 2158 * Enabling MC-RLDRAM. After enabling the device, we timeout
2159 * for around 100ms, which is approximately the time required
2160 * for the device to be ready for operation.
2161 */
2162 val64 = readq(&bar0->mc_rldram_mrs);
2163 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2164 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2165 val64 = readq(&bar0->mc_rldram_mrs);
2166
20346722 2167 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2168
2169 /* Enabling ECC Protection. */
2170 val64 = readq(&bar0->adapter_control);
2171 val64 &= ~ADAPTER_ECC_EN;
2172 writeq(val64, &bar0->adapter_control);
2173
20346722
K		 2174 /*
2175 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2176 * it.
2177 */
2178 val64 = readq(&bar0->adapter_status);
19a60522 2179 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2180 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2181 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2182 (unsigned long long) val64);
2183 return FAILURE;
2184 }
2185
20346722 2186 /*
1da177e4 2187 * With some switches, link might be already up at this point.
20346722
K		 2188 * Because of this weird behavior, when we enable laser,
2189 * we may not get link. We need to handle this. We cannot
2190 * figure out which switch is misbehaving. So we are forced to
2191 * make a global change.
1da177e4
LT		 2192 */
2193
2194 /* Enabling Laser. */
2195 val64 = readq(&bar0->adapter_control);
2196 val64 |= ADAPTER_EOI_TX_ON;
2197 writeq(val64, &bar0->adapter_control);
2198
c92ca04b
AR		 2199 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2200 /*
2201 * Dont see link state interrupts initally on some switches,
2202 * so directly scheduling the link state task here.
2203 */
2204 schedule_work(&nic->set_link_task);
2205 }
1da177e4
LT		 2206 /* SXE-002: Initialize link and activity LED */
2207 subid = nic->pdev->subsystem_device;
541ae68f
K		 2208 if (((subid & 0xFF) >= 0x07) &&
2209 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2210 val64 = readq(&bar0->gpio_control);
2211 val64 |= 0x0000800000000000ULL;
2212 writeq(val64, &bar0->gpio_control);
2213 val64 = 0x0411040400000000ULL;
509a2671 2214 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2215 }
2216
1da177e4
LT		 2217 return SUCCESS;
2218}
fed5eccd
AR		 2219/**
2220 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2221 */
1ee6dd77
RB		 2222static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2223 TxD *txdlp, int get_off)
fed5eccd 2224{
1ee6dd77 2225 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2226 struct sk_buff *skb;
1ee6dd77 2227 struct TxD *txds;
fed5eccd
AR		 2228 u16 j, frg_cnt;
2229
2230 txds = txdlp;
26b7625c 2231 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
fed5eccd
AR		 2232 pci_unmap_single(nic->pdev, (dma_addr_t)
2233 txds->Buffer_Pointer, sizeof(u64),
2234 PCI_DMA_TODEVICE);
2235 txds++;
2236 }
2237
2238 skb = (struct sk_buff *) ((unsigned long)
2239 txds->Host_Control);
2240 if (!skb) {
1ee6dd77 2241 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2242 return NULL;
2243 }
2244 pci_unmap_single(nic->pdev, (dma_addr_t)
2245 txds->Buffer_Pointer,
2246 skb->len - skb->data_len,
2247 PCI_DMA_TODEVICE);
2248 frg_cnt = skb_shinfo(skb)->nr_frags;
2249 if (frg_cnt) {
2250 txds++;
2251 for (j = 0; j < frg_cnt; j++, txds++) {
2252 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2253 if (!txds->Buffer_Pointer)
2254 break;
6aa20a22 2255 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2256 txds->Buffer_Pointer,
2257 frag->size, PCI_DMA_TODEVICE);
2258 }
2259 }
1ee6dd77 2260 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2261 return(skb);
2262}
1da177e4 2263
20346722
K		 2264/**
2265 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2266 * @nic : device private variable.
20346722 2267 * Description:
1da177e4 2268 * Free all queued Tx buffers.
20346722 2269 * Return Value: void
1da177e4
LT		 2270*/
2271
2272static void free_tx_buffers(struct s2io_nic *nic)
2273{
2274 struct net_device *dev = nic->dev;
2275 struct sk_buff *skb;
1ee6dd77 2276 struct TxD *txdp;
1da177e4 2277 int i, j;
1ee6dd77 2278 struct mac_info *mac_control;
1da177e4 2279 struct config_param *config;
fed5eccd 2280 int cnt = 0;
1da177e4
LT		 2281
2282 mac_control = &nic->mac_control;
2283 config = &nic->config;
2284
2285 for (i = 0; i < config->tx_fifo_num; i++) {
2286 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
491976b2
SH		 2287 txdp = (struct TxD *) \
2288 mac_control->fifos[i].list_info[j].list_virt_addr;
fed5eccd
AR		 2289 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2290 if (skb) {
8a4bdbaa 2291 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 2292 += skb->truesize;
fed5eccd
AR		 2293 dev_kfree_skb(skb);
2294 cnt++;
1da177e4 2295 }
1da177e4
LT		 2296 }
2297 DBG_PRINT(INTR_DBG,
2298 "%s:forcibly freeing %d skbs on FIFO%d\n",
2299 dev->name, cnt, i);
20346722
K		 2300 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2301 mac_control->fifos[i].tx_curr_put_info.offset = 0;
1da177e4
LT		 2302 }
2303}
2304
20346722
K		 2305/**
2306 * stop_nic - To stop the nic
1da177e4 2307 * @nic ; device private variable.
20346722
K		 2308 * Description:
2309 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2310 * function does. This function is called to stop the device.
2311 * Return Value:
2312 * void.
2313 */
2314
2315static void stop_nic(struct s2io_nic *nic)
2316{
1ee6dd77 2317 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2318 register u64 val64 = 0;
5d3213cc 2319 u16 interruptible;
1ee6dd77 2320 struct mac_info *mac_control;
1da177e4
LT		 2321 struct config_param *config;
2322
2323 mac_control = &nic->mac_control;
2324 config = &nic->config;
2325
2326 /* Disable all interrupts */
9caab458 2327 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2328 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2329 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2330 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2331
5d3213cc
AR		 2332 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2333 val64 = readq(&bar0->adapter_control);
2334 val64 &= ~(ADAPTER_CNTL_EN);
2335 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2336}
2337
20346722
K		 2338/**
2339 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2340 * @nic: device private variable
20346722
K		 2341 * @ring_no: ring number
2342 * Description:
1da177e4
LT		 2343 * The function allocates Rx side skbs and puts the physical
2344 * address of these buffers into the RxD buffer pointers, so that the NIC
2345 * can DMA the received frame into these locations.
2346 * The NIC supports 3 receive modes, viz
2347 * 1. single buffer,
2348 * 2. three buffer and
2349 * 3. Five buffer modes.
20346722
K		 2350 * Each mode defines how many fragments the received frame will be split
2351 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2352 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2353 * is split into 3 fragments. As of now only single buffer mode is
2354 * supported.
2355 * Return Value:
2356 * SUCCESS on success or an appropriate -ve value on failure.
2357 */
2358
ac1f60db 2359static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2360{
2361 struct net_device *dev = nic->dev;
2362 struct sk_buff *skb;
1ee6dd77 2363 struct RxD_t *rxdp;
1da177e4 2364 int off, off1, size, block_no, block_no1;
1da177e4 2365 u32 alloc_tab = 0;
20346722 2366 u32 alloc_cnt;
1ee6dd77 2367 struct mac_info *mac_control;
1da177e4 2368 struct config_param *config;
20346722 2369 u64 tmp;
1ee6dd77 2370 struct buffAdd *ba;
1da177e4 2371 unsigned long flags;
1ee6dd77 2372 struct RxD_t *first_rxdp = NULL;
363dc367 2373 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
6d517a27
VP		 2374 struct RxD1 *rxdp1;
2375 struct RxD3 *rxdp3;
491abf25 2376 struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
1da177e4
LT		 2377
2378 mac_control = &nic->mac_control;
2379 config = &nic->config;
20346722
K		 2380 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2381 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2382
5d3213cc 2383 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2384 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2385 while (alloc_tab < alloc_cnt) {
20346722 2386 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2387 block_index;
20346722 2388 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2389
da6971d8
AR		 2390 rxdp = mac_control->rings[ring_no].
2391 rx_blocks[block_no].rxds[off].virt_addr;
2392
2393 if ((block_no == block_no1) && (off == off1) &&
2394 (rxdp->Host_Control)) {
2395 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2396 dev->name);
1da177e4
LT		 2397 DBG_PRINT(INTR_DBG, " info equated\n");
2398 goto end;
2399 }
da6971d8 2400 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2401 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2402 block_index++;
da6971d8
AR		 2403 if (mac_control->rings[ring_no].rx_curr_put_info.
2404 block_index == mac_control->rings[ring_no].
2405 block_count)
2406 mac_control->rings[ring_no].rx_curr_put_info.
2407 block_index = 0;
2408 block_no = mac_control->rings[ring_no].
2409 rx_curr_put_info.block_index;
2410 if (off == rxd_count[nic->rxd_mode])
2411 off = 0;
20346722 2412 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2413 offset = off;
2414 rxdp = mac_control->rings[ring_no].
2415 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2416 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2417 dev->name, rxdp);
2418 }
db874e65
SS		 2419 if(!napi) {
2420 spin_lock_irqsave(&nic->put_lock, flags);
2421 mac_control->rings[ring_no].put_pos =
2422 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2423 spin_unlock_irqrestore(&nic->put_lock, flags);
2424 } else {
2425 mac_control->rings[ring_no].put_pos =
2426 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2427 }
da6971d8 2428 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
6d517a27 2429 ((nic->rxd_mode == RXD_MODE_3B) &&
b7b5a128 2430 (rxdp->Control_2 & s2BIT(0)))) {
20346722 2431 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2432 offset = off;
1da177e4
LT		 2433 goto end;
2434 }
da6971d8
AR		 2435 /* calculate size of skb based on ring mode */
2436 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2437 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2438 if (nic->rxd_mode == RXD_MODE_1)
2439 size += NET_IP_ALIGN;
da6971d8 2440 else
6d517a27 2441 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2442
da6971d8
AR		 2443 /* allocate skb */
2444 skb = dev_alloc_skb(size);
2445 if(!skb) {
0c61ed5f
RV		 2446 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2447 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2448 if (first_rxdp) {
2449 wmb();
2450 first_rxdp->Control_1 |= RXD_OWN_XENA;
2451 }
c53d4945
SH		 2452 nic->mac_control.stats_info->sw_stat. \
2453 mem_alloc_fail_cnt++;
da6971d8
AR		 2454 return -ENOMEM ;
2455 }
8a4bdbaa 2456 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 2457 += skb->truesize;
da6971d8
AR		 2458 if (nic->rxd_mode == RXD_MODE_1) {
2459 /* 1 buffer mode - normal operation mode */
6d517a27 2460 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2461 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2462 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2463 rxdp1->Buffer0_ptr = pci_map_single
863c11a9
AR		 2464 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2465 PCI_DMA_FROMDEVICE);
491abf25
VP		 2466 if( (rxdp1->Buffer0_ptr == 0) ||
2467 (rxdp1->Buffer0_ptr ==
2468 DMA_ERROR_CODE))
2469 goto pci_map_failed;
2470
8a4bdbaa 2471 rxdp->Control_2 =
491976b2 2472 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8 2473
6d517a27 2474 } else if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8 2475 /*
6d517a27
VP		 2476 * 2 buffer mode -
2477 * 2 buffer mode provides 128
da6971d8 2478 * byte aligned receive buffers.
da6971d8
AR		 2479 */
2480
6d517a27 2481 rxdp3 = (struct RxD3*)rxdp;
491976b2 2482 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2483 Buffer0_ptr = rxdp3->Buffer0_ptr;
2484 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2485 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2486 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2487 rxdp3->Buffer0_ptr = Buffer0_ptr;
2488 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2489
da6971d8
AR		 2490 ba = &mac_control->rings[ring_no].ba[block_no][off];
2491 skb_reserve(skb, BUF0_LEN);
2492 tmp = (u64)(unsigned long) skb->data;
2493 tmp += ALIGN_SIZE;
2494 tmp &= ~ALIGN_SIZE;
2495 skb->data = (void *) (unsigned long)tmp;
27a884dc 2496 skb_reset_tail_pointer(skb);
da6971d8 2497
6d517a27
VP		 2498 if (!(rxdp3->Buffer0_ptr))
2499 rxdp3->Buffer0_ptr =
75c30b13 2500 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2501 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2502 else
2503 pci_dma_sync_single_for_device(nic->pdev,
6d517a27 2504 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2505 BUF0_LEN, PCI_DMA_FROMDEVICE);
491abf25
VP		 2506 if( (rxdp3->Buffer0_ptr == 0) ||
2507 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2508 goto pci_map_failed;
2509
da6971d8
AR		 2510 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2511 if (nic->rxd_mode == RXD_MODE_3B) {
2512 /* Two buffer mode */
2513
2514 /*
6aa20a22 2515 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2516 * L4 payload
2517 */
6d517a27 2518 rxdp3->Buffer2_ptr = pci_map_single
da6971d8
AR		 2519 (nic->pdev, skb->data, dev->mtu + 4,
2520 PCI_DMA_FROMDEVICE);
2521
491abf25
VP		 2522 if( (rxdp3->Buffer2_ptr == 0) ||
2523 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2524 goto pci_map_failed;
2525
2526 rxdp3->Buffer1_ptr =
6aa20a22 2527 pci_map_single(nic->pdev,
75c30b13
AR		 2528 ba->ba_1, BUF1_LEN,
2529 PCI_DMA_FROMDEVICE);
491abf25
VP		 2530 if( (rxdp3->Buffer1_ptr == 0) ||
2531 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2532 pci_unmap_single
2533 (nic->pdev,
3e847423 2534 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 2535 dev->mtu + 4,
2536 PCI_DMA_FROMDEVICE);
2537 goto pci_map_failed;
75c30b13 2538 }
da6971d8
AR		 2539 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2540 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2541 (dev->mtu + 4);
da6971d8 2542 }
b7b5a128 2543 rxdp->Control_2 |= s2BIT(0);
1da177e4 2544 }
1da177e4 2545 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b
K		 2546 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2547 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2548 off++;
da6971d8
AR		 2549 if (off == (rxd_count[nic->rxd_mode] + 1))
2550 off = 0;
20346722 2551 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2552
da6971d8 2553 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2554 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2555 if (first_rxdp) {
2556 wmb();
2557 first_rxdp->Control_1 |= RXD_OWN_XENA;
2558 }
2559 first_rxdp = rxdp;
2560 }
1da177e4
LT		 2561 atomic_inc(&nic->rx_bufs_left[ring_no]);
2562 alloc_tab++;
2563 }
2564
2565 end:
303bcb4b
K		 2566 /* Transfer ownership of first descriptor to adapter just before
2567 * exiting. Before that, use memory barrier so that ownership
2568 * and other fields are seen by adapter correctly.
2569 */
2570 if (first_rxdp) {
2571 wmb();
2572 first_rxdp->Control_1 |= RXD_OWN_XENA;
2573 }
2574
1da177e4 2575 return SUCCESS;
491abf25
VP		 2576pci_map_failed:
2577 stats->pci_map_fail_cnt++;
2578 stats->mem_freed += skb->truesize;
2579 dev_kfree_skb_irq(skb);
2580 return -ENOMEM;
1da177e4
LT		 2581}
2582
da6971d8
AR		 2583static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2584{
2585 struct net_device *dev = sp->dev;
2586 int j;
2587 struct sk_buff *skb;
1ee6dd77
RB		 2588 struct RxD_t *rxdp;
2589 struct mac_info *mac_control;
2590 struct buffAdd *ba;
6d517a27
VP		 2591 struct RxD1 *rxdp1;
2592 struct RxD3 *rxdp3;
da6971d8
AR		 2593
2594 mac_control = &sp->mac_control;
2595 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2596 rxdp = mac_control->rings[ring_no].
2597 rx_blocks[blk].rxds[j].virt_addr;
2598 skb = (struct sk_buff *)
2599 ((unsigned long) rxdp->Host_Control);
2600 if (!skb) {
2601 continue;
2602 }
2603 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2604 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2605 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2606 rxdp1->Buffer0_ptr,
2607 dev->mtu +
2608 HEADER_ETHERNET_II_802_3_SIZE
2609 + HEADER_802_2_SIZE +
2610 HEADER_SNAP_SIZE,
2611 PCI_DMA_FROMDEVICE);
1ee6dd77 2612 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2613 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2614 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2615 ba = &mac_control->rings[ring_no].
2616 ba[blk][j];
2617 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2618 rxdp3->Buffer0_ptr,
2619 BUF0_LEN,
da6971d8
AR		 2620 PCI_DMA_FROMDEVICE);
2621 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2622 rxdp3->Buffer1_ptr,
2623 BUF1_LEN,
da6971d8
AR		 2624 PCI_DMA_FROMDEVICE);
2625 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2626 rxdp3->Buffer2_ptr,
2627 dev->mtu + 4,
da6971d8 2628 PCI_DMA_FROMDEVICE);
1ee6dd77 2629 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2630 }
491976b2 2631 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8
AR		 2632 dev_kfree_skb(skb);
2633 atomic_dec(&sp->rx_bufs_left[ring_no]);
2634 }
2635}
2636
1da177e4 2637/**
20346722 2638 * free_rx_buffers - Frees all Rx buffers
1da177e4 2639 * @sp: device private variable.
20346722 2640 * Description:
1da177e4
LT		 2641 * This function will free all Rx buffers allocated by host.
2642 * Return Value:
2643 * NONE.
2644 */
2645
2646static void free_rx_buffers(struct s2io_nic *sp)
2647{
2648 struct net_device *dev = sp->dev;
da6971d8 2649 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2650 struct mac_info *mac_control;
1da177e4 2651 struct config_param *config;
1da177e4
LT		 2652
2653 mac_control = &sp->mac_control;
2654 config = &sp->config;
2655
2656 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2657 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2658 free_rxd_blk(sp,i,blk);
1da177e4 2659
20346722
K		 2660 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2661 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2662 mac_control->rings[i].rx_curr_put_info.offset = 0;
2663 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2664 atomic_set(&sp->rx_bufs_left[i], 0);
2665 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2666 dev->name, buf_cnt, i);
2667 }
2668}
2669
2670/**
2671 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2672 * @napi : pointer to the napi structure.
20346722 2673 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2674 * during one pass through the 'Poll" function.
2675 * Description:
2676 * Comes into picture only if NAPI support has been incorporated. It does
2677 * the same thing that rx_intr_handler does, but not in a interrupt context
2678 * also It will process only a given number of packets.
2679 * Return value:
2680 * 0 on success and 1 if there are No Rx packets to be processed.
2681 */
2682
bea3348e 2683static int s2io_poll(struct napi_struct *napi, int budget)
1da177e4 2684{
bea3348e
SH		 2685 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2686 struct net_device *dev = nic->dev;
20346722 2687 int pkt_cnt = 0, org_pkts_to_process;
1ee6dd77 2688 struct mac_info *mac_control;
1da177e4 2689 struct config_param *config;
1ee6dd77 2690 struct XENA_dev_config __iomem *bar0 = nic->bar0;
20346722 2691 int i;
1da177e4 2692
596c5c97 2693 if (!is_s2io_card_up(nic))
92b84437 2694 return 0;
92b84437 2695
1da177e4
LT		 2696 mac_control = &nic->mac_control;
2697 config = &nic->config;
2698
bea3348e 2699 nic->pkts_to_process = budget;
20346722 2700 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2701
19a60522
SS		 2702 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2703 readl(&bar0->rx_traffic_int);
1da177e4
LT		 2704
2705 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 2706 rx_intr_handler(&mac_control->rings[i]);
2707 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2708 if (!nic->pkts_to_process) {
2709 /* Quota for the current iteration has been met */
2710 goto no_rx;
1da177e4 2711 }
1da177e4 2712 }
1da177e4 2713
bea3348e 2714 netif_rx_complete(dev, napi);
1da177e4
LT		 2715
2716 for (i = 0; i < config->rx_ring_num; i++) {
2717 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2718 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2719 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2720 break;
2721 }
2722 }
2723 /* Re enable the Rx interrupts. */
c92ca04b 2724 writeq(0x0, &bar0->rx_traffic_mask);
19a60522 2725 readl(&bar0->rx_traffic_mask);
bea3348e 2726 return pkt_cnt;
1da177e4 2727
20346722 2728no_rx:
1da177e4
LT		 2729 for (i = 0; i < config->rx_ring_num; i++) {
2730 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2731 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2732 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2733 break;
2734 }
2735 }
bea3348e 2736 return pkt_cnt;
1da177e4 2737}
20346722 2738
b41477f3 2739#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2740/**
b41477f3 2741 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2742 * @dev : pointer to the device structure.
2743 * Description:
b41477f3
AR		 2744 * This function will be called by upper layer to check for events on the
2745 * interface in situations where interrupts are disabled. It is used for
2746 * specific in-kernel networking tasks, such as remote consoles and kernel
2747 * debugging over the network (example netdump in RedHat).
612eff0e 2748 */
612eff0e
BH		 2749static void s2io_netpoll(struct net_device *dev)
2750{
1ee6dd77
RB		 2751 struct s2io_nic *nic = dev->priv;
2752 struct mac_info *mac_control;
612eff0e 2753 struct config_param *config;
1ee6dd77 2754 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2755 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2756 int i;
2757
d796fdb7
LV		 2758 if (pci_channel_offline(nic->pdev))
2759 return;
2760
612eff0e
BH		 2761 disable_irq(dev->irq);
2762
612eff0e
BH		 2763 mac_control = &nic->mac_control;
2764 config = &nic->config;
2765
612eff0e 2766 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2767 writeq(val64, &bar0->tx_traffic_int);
2768
6aa20a22 2769 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2770 * run out of skbs and will fail and eventually netpoll application such
2771 * as netdump will fail.
2772 */
2773 for (i = 0; i < config->tx_fifo_num; i++)
2774 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2775
b41477f3 2776 /* check for received packet and indicate up to network */
612eff0e
BH		 2777 for (i = 0; i < config->rx_ring_num; i++)
2778 rx_intr_handler(&mac_control->rings[i]);
2779
2780 for (i = 0; i < config->rx_ring_num; i++) {
2781 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2782 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2783 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2784 break;
2785 }
2786 }
612eff0e
BH		 2787 enable_irq(dev->irq);
2788 return;
2789}
2790#endif
2791
20346722 2792/**
1da177e4
LT		 2793 * rx_intr_handler - Rx interrupt handler
2794 * @nic: device private variable.
20346722
K		 2795 * Description:
2796 * If the interrupt is because of a received frame or if the
1da177e4 2797 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2798 * called. It picks out the RxD at which place the last Rx processing had
2799 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2800 * the offset.
2801 * Return Value:
2802 * NONE.
2803 */
1ee6dd77 2804static void rx_intr_handler(struct ring_info *ring_data)
1da177e4 2805{
1ee6dd77 2806 struct s2io_nic *nic = ring_data->nic;
1da177e4 2807 struct net_device *dev = (struct net_device *) nic->dev;
da6971d8 2808 int get_block, put_block, put_offset;
1ee6dd77
RB		 2809 struct rx_curr_get_info get_info, put_info;
2810 struct RxD_t *rxdp;
1da177e4 2811 struct sk_buff *skb;
20346722 2812 int pkt_cnt = 0;
7d3d0439 2813 int i;
6d517a27
VP		 2814 struct RxD1* rxdp1;
2815 struct RxD3* rxdp3;
7d3d0439 2816
7ba013ac 2817 spin_lock(&nic->rx_lock);
7ba013ac 2818
20346722
K		 2819 get_info = ring_data->rx_curr_get_info;
2820 get_block = get_info.block_index;
1ee6dd77 2821 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2822 put_block = put_info.block_index;
da6971d8 2823 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65
SS		 2824 if (!napi) {
2825 spin_lock(&nic->put_lock);
2826 put_offset = ring_data->put_pos;
2827 spin_unlock(&nic->put_lock);
2828 } else
2829 put_offset = ring_data->put_pos;
2830
da6971d8 2831 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2832 /*
2833 * If your are next to put index then it's
2834 * FIFO full condition
2835 */
da6971d8
AR		 2836 if ((get_block == put_block) &&
2837 (get_info.offset + 1) == put_info.offset) {
75c30b13 2838 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 2839 break;
2840 }
20346722
K		 2841 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2842 if (skb == NULL) {
2843 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2844 dev->name);
2845 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
7ba013ac 2846 spin_unlock(&nic->rx_lock);
20346722 2847 return;
1da177e4 2848 }
da6971d8 2849 if (nic->rxd_mode == RXD_MODE_1) {
6d517a27 2850 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2851 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 2852 rxdp1->Buffer0_ptr,
2853 dev->mtu +
2854 HEADER_ETHERNET_II_802_3_SIZE +
2855 HEADER_802_2_SIZE +
2856 HEADER_SNAP_SIZE,
2857 PCI_DMA_FROMDEVICE);
da6971d8 2858 } else if (nic->rxd_mode == RXD_MODE_3B) {
6d517a27 2859 rxdp3 = (struct RxD3*)rxdp;
75c30b13 2860 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
6d517a27
VP		 2861 rxdp3->Buffer0_ptr,
2862 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8 2863 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 2864 rxdp3->Buffer2_ptr,
2865 dev->mtu + 4,
2866 PCI_DMA_FROMDEVICE);
da6971d8 2867 }
863c11a9 2868 prefetch(skb->data);
20346722
K		 2869 rx_osm_handler(ring_data, rxdp);
2870 get_info.offset++;
da6971d8
AR		 2871 ring_data->rx_curr_get_info.offset = get_info.offset;
2872 rxdp = ring_data->rx_blocks[get_block].
2873 rxds[get_info.offset].virt_addr;
2874 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 2875 get_info.offset = 0;
da6971d8 2876 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 2877 get_block++;
da6971d8
AR		 2878 if (get_block == ring_data->block_count)
2879 get_block = 0;
2880 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 2881 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2882 }
1da177e4 2883
20346722 2884 nic->pkts_to_process -= 1;
db874e65 2885 if ((napi) && (!nic->pkts_to_process))
20346722 2886 break;
20346722 2887 pkt_cnt++;
1da177e4
LT		 2888 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2889 break;
2890 }
7d3d0439
RA		 2891 if (nic->lro) {
2892 /* Clear all LRO sessions before exiting */
2893 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 2894 struct lro *lro = &nic->lro0_n[i];
7d3d0439
RA		 2895 if (lro->in_use) {
2896 update_L3L4_header(nic, lro);
2897 queue_rx_frame(lro->parent);
2898 clear_lro_session(lro);
2899 }
2900 }
2901 }
2902
7ba013ac 2903 spin_unlock(&nic->rx_lock);
1da177e4 2904}
20346722
K		 2905
2906/**
1da177e4
LT		 2907 * tx_intr_handler - Transmit interrupt handler
2908 * @nic : device private variable
20346722
K		 2909 * Description:
2910 * If an interrupt was raised to indicate DMA complete of the
2911 * Tx packet, this function is called. It identifies the last TxD
2912 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 2913 * DMA'ed into the NICs internal memory.
2914 * Return Value:
2915 * NONE
2916 */
2917
1ee6dd77 2918static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 2919{
1ee6dd77 2920 struct s2io_nic *nic = fifo_data->nic;
1da177e4 2921 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 2922 struct tx_curr_get_info get_info, put_info;
1da177e4 2923 struct sk_buff *skb;
1ee6dd77 2924 struct TxD *txdlp;
f9046eb3 2925 u8 err_mask;
1da177e4 2926
20346722 2927 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 2928 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2929 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722
K		 2930 list_virt_addr;
2931 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2932 (get_info.offset != put_info.offset) &&
2933 (txdlp->Host_Control)) {
2934 /* Check for TxD errors */
2935 if (txdlp->Control_1 & TXD_T_CODE) {
2936 unsigned long long err;
2937 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 2938 if (err & 0x1) {
2939 nic->mac_control.stats_info->sw_stat.
2940 parity_err_cnt++;
2941 }
491976b2
SH		 2942
2943 /* update t_code statistics */
f9046eb3
OH		 2944 err_mask = err >> 48;
2945 switch(err_mask) {
491976b2
SH		 2946 case 2:
2947 nic->mac_control.stats_info->sw_stat.
2948 tx_buf_abort_cnt++;
2949 break;
2950
2951 case 3:
2952 nic->mac_control.stats_info->sw_stat.
2953 tx_desc_abort_cnt++;
2954 break;
2955
2956 case 7:
2957 nic->mac_control.stats_info->sw_stat.
2958 tx_parity_err_cnt++;
2959 break;
2960
2961 case 10:
2962 nic->mac_control.stats_info->sw_stat.
2963 tx_link_loss_cnt++;
2964 break;
2965
2966 case 15:
2967 nic->mac_control.stats_info->sw_stat.
2968 tx_list_proc_err_cnt++;
2969 break;
2970 }
20346722 2971 }
1da177e4 2972
fed5eccd 2973 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722
K		 2974 if (skb == NULL) {
2975 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2976 __FUNCTION__);
2977 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2978 return;
2979 }
2980
20346722 2981 /* Updating the statistics block */
20346722 2982 nic->stats.tx_bytes += skb->len;
491976b2 2983 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722
K		 2984 dev_kfree_skb_irq(skb);
2985
2986 get_info.offset++;
863c11a9
AR		 2987 if (get_info.offset == get_info.fifo_len + 1)
2988 get_info.offset = 0;
1ee6dd77 2989 txdlp = (struct TxD *) fifo_data->list_info
20346722
K		 2990 [get_info.offset].list_virt_addr;
2991 fifo_data->tx_curr_get_info.offset =
2992 get_info.offset;
1da177e4
LT		 2993 }
2994
2995 spin_lock(&nic->tx_lock);
2996 if (netif_queue_stopped(dev))
2997 netif_wake_queue(dev);
2998 spin_unlock(&nic->tx_lock);
2999}
3000
bd1034f0
AR		 3001/**
3002 * s2io_mdio_write - Function to write in to MDIO registers
3003 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3004 * @addr : address value
3005 * @value : data value
3006 * @dev : pointer to net_device structure
3007 * Description:
3008 * This function is used to write values to the MDIO registers
3009 * NONE
3010 */
3011static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3012{
3013 u64 val64 = 0x0;
1ee6dd77
RB		 3014 struct s2io_nic *sp = dev->priv;
3015 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3016
3017 //address transaction
3018 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3019 | MDIO_MMD_DEV_ADDR(mmd_type)
3020 | MDIO_MMS_PRT_ADDR(0x0);
3021 writeq(val64, &bar0->mdio_control);
3022 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3023 writeq(val64, &bar0->mdio_control);
3024 udelay(100);
3025
3026 //Data transaction
3027 val64 = 0x0;
3028 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3029 | MDIO_MMD_DEV_ADDR(mmd_type)
3030 | MDIO_MMS_PRT_ADDR(0x0)
3031 | MDIO_MDIO_DATA(value)
3032 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3033 writeq(val64, &bar0->mdio_control);
3034 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3035 writeq(val64, &bar0->mdio_control);
3036 udelay(100);
3037
3038 val64 = 0x0;
3039 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3040 | MDIO_MMD_DEV_ADDR(mmd_type)
3041 | MDIO_MMS_PRT_ADDR(0x0)
3042 | MDIO_OP(MDIO_OP_READ_TRANS);
3043 writeq(val64, &bar0->mdio_control);
3044 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3045 writeq(val64, &bar0->mdio_control);
3046 udelay(100);
3047
3048}
3049
3050/**
3051 * s2io_mdio_read - Function to write in to MDIO registers
3052 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3053 * @addr : address value
3054 * @dev : pointer to net_device structure
3055 * Description:
3056 * This function is used to read values to the MDIO registers
3057 * NONE
3058 */
3059static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3060{
3061 u64 val64 = 0x0;
3062 u64 rval64 = 0x0;
1ee6dd77
RB		 3063 struct s2io_nic *sp = dev->priv;
3064 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3065
3066 /* address transaction */
3067 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3068 | MDIO_MMD_DEV_ADDR(mmd_type)
3069 | MDIO_MMS_PRT_ADDR(0x0);
3070 writeq(val64, &bar0->mdio_control);
3071 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3072 writeq(val64, &bar0->mdio_control);
3073 udelay(100);
3074
3075 /* Data transaction */
3076 val64 = 0x0;
3077 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3078 | MDIO_MMD_DEV_ADDR(mmd_type)
3079 | MDIO_MMS_PRT_ADDR(0x0)
3080 | MDIO_OP(MDIO_OP_READ_TRANS);
3081 writeq(val64, &bar0->mdio_control);
3082 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3083 writeq(val64, &bar0->mdio_control);
3084 udelay(100);
3085
3086 /* Read the value from regs */
3087 rval64 = readq(&bar0->mdio_control);
3088 rval64 = rval64 & 0xFFFF0000;
3089 rval64 = rval64 >> 16;
3090 return rval64;
3091}
3092/**
3093 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3094 * @counter : couter value to be updated
3095 * @flag : flag to indicate the status
3096 * @type : counter type
3097 * Description:
3098 * This function is to check the status of the xpak counters value
3099 * NONE
3100 */
3101
3102static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3103{
3104 u64 mask = 0x3;
3105 u64 val64;
3106 int i;
3107 for(i = 0; i <index; i++)
3108 mask = mask << 0x2;
3109
3110 if(flag > 0)
3111 {
3112 *counter = *counter + 1;
3113 val64 = *regs_stat & mask;
3114 val64 = val64 >> (index * 0x2);
3115 val64 = val64 + 1;
3116 if(val64 == 3)
3117 {
3118 switch(type)
3119 {
3120 case 1:
3121 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3122 "service. Excessive temperatures may "
3123 "result in premature transceiver "
3124 "failure \n");
3125 break;
3126 case 2:
3127 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3128 "service Excessive bias currents may "
3129 "indicate imminent laser diode "
3130 "failure \n");
3131 break;
3132 case 3:
3133 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3134 "service Excessive laser output "
3135 "power may saturate far-end "
3136 "receiver\n");
3137 break;
3138 default:
3139 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3140 "type \n");
3141 }
3142 val64 = 0x0;
3143 }
3144 val64 = val64 << (index * 0x2);
3145 *regs_stat = (*regs_stat & (~mask)) | (val64);
3146
3147 } else {
3148 *regs_stat = *regs_stat & (~mask);
3149 }
3150}
3151
3152/**
3153 * s2io_updt_xpak_counter - Function to update the xpak counters
3154 * @dev : pointer to net_device struct
3155 * Description:
3156 * This function is to upate the status of the xpak counters value
3157 * NONE
3158 */
3159static void s2io_updt_xpak_counter(struct net_device *dev)
3160{
3161 u16 flag = 0x0;
3162 u16 type = 0x0;
3163 u16 val16 = 0x0;
3164 u64 val64 = 0x0;
3165 u64 addr = 0x0;
3166
1ee6dd77
RB		 3167 struct s2io_nic *sp = dev->priv;
3168 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3169
3170 /* Check the communication with the MDIO slave */
3171 addr = 0x0000;
3172 val64 = 0x0;
3173 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3174 if((val64 == 0xFFFF) || (val64 == 0x0000))
3175 {
3176 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3177 "Returned %llx\n", (unsigned long long)val64);
3178 return;
3179 }
3180
3181 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3182 if(val64 != 0x2040)
3183 {
3184 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3185 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3186 (unsigned long long)val64);
3187 return;
3188 }
3189
3190 /* Loading the DOM register to MDIO register */
3191 addr = 0xA100;
3192 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3193 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3194
3195 /* Reading the Alarm flags */
3196 addr = 0xA070;
3197 val64 = 0x0;
3198 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3199
3200 flag = CHECKBIT(val64, 0x7);
3201 type = 1;
3202 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3203 &stat_info->xpak_stat.xpak_regs_stat,
3204 0x0, flag, type);
3205
3206 if(CHECKBIT(val64, 0x6))
3207 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3208
3209 flag = CHECKBIT(val64, 0x3);
3210 type = 2;
3211 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3212 &stat_info->xpak_stat.xpak_regs_stat,
3213 0x2, flag, type);
3214
3215 if(CHECKBIT(val64, 0x2))
3216 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3217
3218 flag = CHECKBIT(val64, 0x1);
3219 type = 3;
3220 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3221 &stat_info->xpak_stat.xpak_regs_stat,
3222 0x4, flag, type);
3223
3224 if(CHECKBIT(val64, 0x0))
3225 stat_info->xpak_stat.alarm_laser_output_power_low++;
3226
3227 /* Reading the Warning flags */
3228 addr = 0xA074;
3229 val64 = 0x0;
3230 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3231
3232 if(CHECKBIT(val64, 0x7))
3233 stat_info->xpak_stat.warn_transceiver_temp_high++;
3234
3235 if(CHECKBIT(val64, 0x6))
3236 stat_info->xpak_stat.warn_transceiver_temp_low++;
3237
3238 if(CHECKBIT(val64, 0x3))
3239 stat_info->xpak_stat.warn_laser_bias_current_high++;
3240
3241 if(CHECKBIT(val64, 0x2))
3242 stat_info->xpak_stat.warn_laser_bias_current_low++;
3243
3244 if(CHECKBIT(val64, 0x1))
3245 stat_info->xpak_stat.warn_laser_output_power_high++;
3246
3247 if(CHECKBIT(val64, 0x0))
3248 stat_info->xpak_stat.warn_laser_output_power_low++;
3249}
3250
20346722 3251/**
1da177e4 3252 * wait_for_cmd_complete - waits for a command to complete.
20346722 3253 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3254 * s2io_nic structure.
20346722
K		 3255 * Description: Function that waits for a command to Write into RMAC
3256 * ADDR DATA registers to be completed and returns either success or
3257 * error depending on whether the command was complete or not.
1da177e4
LT		 3258 * Return value:
3259 * SUCCESS on success and FAILURE on failure.
3260 */
3261
9fc93a41
SS		 3262static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3263 int bit_state)
1da177e4 3264{
9fc93a41 3265 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3266 u64 val64;
3267
9fc93a41
SS		 3268 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3269 return FAILURE;
3270
3271 do {
c92ca04b 3272 val64 = readq(addr);
9fc93a41
SS		 3273 if (bit_state == S2IO_BIT_RESET) {
3274 if (!(val64 & busy_bit)) {
3275 ret = SUCCESS;
3276 break;
3277 }
3278 } else {
3279 if (!(val64 & busy_bit)) {
3280 ret = SUCCESS;
3281 break;
3282 }
1da177e4 3283 }
c92ca04b
AR		 3284
3285 if(in_interrupt())
9fc93a41 3286 mdelay(delay);
c92ca04b 3287 else
9fc93a41 3288 msleep(delay);
c92ca04b 3289
9fc93a41
SS		 3290 if (++cnt >= 10)
3291 delay = 50;
3292 } while (cnt < 20);
1da177e4
LT		 3293 return ret;
3294}
19a60522
SS		 3295/*
3296 * check_pci_device_id - Checks if the device id is supported
3297 * @id : device id
3298 * Description: Function to check if the pci device id is supported by driver.
3299 * Return value: Actual device id if supported else PCI_ANY_ID
3300 */
3301static u16 check_pci_device_id(u16 id)
3302{
3303 switch (id) {
3304 case PCI_DEVICE_ID_HERC_WIN:
3305 case PCI_DEVICE_ID_HERC_UNI:
3306 return XFRAME_II_DEVICE;
3307 case PCI_DEVICE_ID_S2IO_UNI:
3308 case PCI_DEVICE_ID_S2IO_WIN:
3309 return XFRAME_I_DEVICE;
3310 default:
3311 return PCI_ANY_ID;
3312 }
3313}
1da177e4 3314
20346722
K		 3315/**
3316 * s2io_reset - Resets the card.
1da177e4
LT		 3317 * @sp : private member of the device structure.
3318 * Description: Function to Reset the card. This function then also
20346722 3319 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3320 * the card reset also resets the configuration space.
3321 * Return value:
3322 * void.
3323 */
3324
1ee6dd77 3325static void s2io_reset(struct s2io_nic * sp)
1da177e4 3326{
1ee6dd77 3327 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3328 u64 val64;
5e25b9dd 3329 u16 subid, pci_cmd;
19a60522
SS		 3330 int i;
3331 u16 val16;
491976b2
SH		 3332 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3333 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3334
19a60522
SS		 3335 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3336 __FUNCTION__, sp->dev->name);
1da177e4 3337
0b1f7ebe 3338 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3339 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3340
1da177e4
LT		 3341 val64 = SW_RESET_ALL;
3342 writeq(val64, &bar0->sw_reset);
c92ca04b
AR		 3343 if (strstr(sp->product_name, "CX4")) {
3344 msleep(750);
3345 }
19a60522
SS		 3346 msleep(250);
3347 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3348
19a60522
SS		 3349 /* Restore the PCI state saved during initialization. */
3350 pci_restore_state(sp->pdev);
3351 pci_read_config_word(sp->pdev, 0x2, &val16);
3352 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3353 break;
3354 msleep(200);
3355 }
1da177e4 3356
19a60522
SS		 3357 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3358 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3359 }
3360
3361 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3362
3363 s2io_init_pci(sp);
1da177e4 3364
20346722
K		 3365 /* Set swapper to enable I/O register access */
3366 s2io_set_swapper(sp);
3367
cc6e7c44
RA		 3368 /* Restore the MSIX table entries from local variables */
3369 restore_xmsi_data(sp);
3370
5e25b9dd 3371 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3372 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3373 /* Clear "detected parity error" bit */
303bcb4b 3374 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3375
303bcb4b
K		 3376 /* Clearing PCIX Ecc status register */
3377 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3378
303bcb4b 3379 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3380 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3381 }
5e25b9dd 3382
20346722
K		 3383 /* Reset device statistics maintained by OS */
3384 memset(&sp->stats, 0, sizeof (struct net_device_stats));
8a4bdbaa 3385
491976b2
SH		 3386 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3387 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3388 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3389 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3390 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3391 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3392 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3393 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3394 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3395 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3396 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3397 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3398 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3399 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3400 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3401 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3402 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3403 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3404 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3405
1da177e4
LT		 3406 /* SXE-002: Configure link and activity LED to turn it off */
3407 subid = sp->pdev->subsystem_device;
541ae68f
K		 3408 if (((subid & 0xFF) >= 0x07) &&
3409 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3410 val64 = readq(&bar0->gpio_control);
3411 val64 |= 0x0000800000000000ULL;
3412 writeq(val64, &bar0->gpio_control);
3413 val64 = 0x0411040400000000ULL;
509a2671 3414 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3415 }
3416
541ae68f
K		 3417 /*
3418 * Clear spurious ECC interrupts that would have occured on
3419 * XFRAME II cards after reset.
3420 */
3421 if (sp->device_type == XFRAME_II_DEVICE) {
3422 val64 = readq(&bar0->pcc_err_reg);
3423 writeq(val64, &bar0->pcc_err_reg);
3424 }
3425
d8d70caf 3426 /* restore the previously assigned mac address */
2fd37688 3427 do_s2io_prog_unicast(sp->dev, (u8 *)&sp->def_mac_addr[0].mac_addr);
d8d70caf 3428
1da177e4
LT		 3429 sp->device_enabled_once = FALSE;
3430}
3431
3432/**
20346722
K		 3433 * s2io_set_swapper - to set the swapper controle on the card
3434 * @sp : private member of the device structure,
1da177e4 3435 * pointer to the s2io_nic structure.
20346722 3436 * Description: Function to set the swapper control on the card
1da177e4
LT		 3437 * correctly depending on the 'endianness' of the system.
3438 * Return value:
3439 * SUCCESS on success and FAILURE on failure.
3440 */
3441
1ee6dd77 3442static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3443{
3444 struct net_device *dev = sp->dev;
1ee6dd77 3445 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3446 u64 val64, valt, valr;
3447
20346722 3448 /*
1da177e4
LT		 3449 * Set proper endian settings and verify the same by reading
3450 * the PIF Feed-back register.
3451 */
3452
3453 val64 = readq(&bar0->pif_rd_swapper_fb);
3454 if (val64 != 0x0123456789ABCDEFULL) {
3455 int i = 0;
3456 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3457 0x8100008181000081ULL, /* FE=1, SE=0 */
3458 0x4200004242000042ULL, /* FE=0, SE=1 */
3459 0}; /* FE=0, SE=0 */
3460
3461 while(i<4) {
3462 writeq(value[i], &bar0->swapper_ctrl);
3463 val64 = readq(&bar0->pif_rd_swapper_fb);
3464 if (val64 == 0x0123456789ABCDEFULL)
3465 break;
3466 i++;
3467 }
3468 if (i == 4) {
3469 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3470 dev->name);
3471 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3472 (unsigned long long) val64);
3473 return FAILURE;
3474 }
3475 valr = value[i];
3476 } else {
3477 valr = readq(&bar0->swapper_ctrl);
3478 }
3479
3480 valt = 0x0123456789ABCDEFULL;
3481 writeq(valt, &bar0->xmsi_address);
3482 val64 = readq(&bar0->xmsi_address);
3483
3484 if(val64 != valt) {
3485 int i = 0;
3486 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3487 0x0081810000818100ULL, /* FE=1, SE=0 */
3488 0x0042420000424200ULL, /* FE=0, SE=1 */
3489 0}; /* FE=0, SE=0 */
3490
3491 while(i<4) {
3492 writeq((value[i] | valr), &bar0->swapper_ctrl);
3493 writeq(valt, &bar0->xmsi_address);
3494 val64 = readq(&bar0->xmsi_address);
3495 if(val64 == valt)
3496 break;
3497 i++;
3498 }
3499 if(i == 4) {
20346722 3500 unsigned long long x = val64;
1da177e4 3501 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3502 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3503 return FAILURE;
3504 }
3505 }
3506 val64 = readq(&bar0->swapper_ctrl);
3507 val64 &= 0xFFFF000000000000ULL;
3508
3509#ifdef __BIG_ENDIAN
20346722
K		 3510 /*
3511 * The device by default set to a big endian format, so a
1da177e4
LT		 3512 * big endian driver need not set anything.
3513 */
3514 val64 |= (SWAPPER_CTRL_TXP_FE |
3515 SWAPPER_CTRL_TXP_SE |
3516 SWAPPER_CTRL_TXD_R_FE |
3517 SWAPPER_CTRL_TXD_W_FE |
3518 SWAPPER_CTRL_TXF_R_FE |
3519 SWAPPER_CTRL_RXD_R_FE |
3520 SWAPPER_CTRL_RXD_W_FE |
3521 SWAPPER_CTRL_RXF_W_FE |
3522 SWAPPER_CTRL_XMSI_FE |
1da177e4 3523 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3524 if (sp->config.intr_type == INTA)
cc6e7c44 3525 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3526 writeq(val64, &bar0->swapper_ctrl);
3527#else
20346722 3528 /*
1da177e4 3529 * Initially we enable all bits to make it accessible by the
20346722 3530 * driver, then we selectively enable only those bits that
1da177e4
LT		 3531 * we want to set.
3532 */
3533 val64 |= (SWAPPER_CTRL_TXP_FE |
3534 SWAPPER_CTRL_TXP_SE |
3535 SWAPPER_CTRL_TXD_R_FE |
3536 SWAPPER_CTRL_TXD_R_SE |
3537 SWAPPER_CTRL_TXD_W_FE |
3538 SWAPPER_CTRL_TXD_W_SE |
3539 SWAPPER_CTRL_TXF_R_FE |
3540 SWAPPER_CTRL_RXD_R_FE |
3541 SWAPPER_CTRL_RXD_R_SE |
3542 SWAPPER_CTRL_RXD_W_FE |
3543 SWAPPER_CTRL_RXD_W_SE |
3544 SWAPPER_CTRL_RXF_W_FE |
3545 SWAPPER_CTRL_XMSI_FE |
1da177e4 3546 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3547 if (sp->config.intr_type == INTA)
cc6e7c44 3548 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3549 writeq(val64, &bar0->swapper_ctrl);
3550#endif
3551 val64 = readq(&bar0->swapper_ctrl);
3552
20346722
K		 3553 /*
3554 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3555 * feedback register.
3556 */
3557 val64 = readq(&bar0->pif_rd_swapper_fb);
3558 if (val64 != 0x0123456789ABCDEFULL) {
3559 /* Endian settings are incorrect, calls for another dekko. */
3560 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3561 dev->name);
3562 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3563 (unsigned long long) val64);
3564 return FAILURE;
3565 }
3566
3567 return SUCCESS;
3568}
3569
1ee6dd77 3570static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3571{
1ee6dd77 3572 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3573 u64 val64;
3574 int ret = 0, cnt = 0;
3575
3576 do {
3577 val64 = readq(&bar0->xmsi_access);
b7b5a128 3578 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3579 break;
3580 mdelay(1);
3581 cnt++;
3582 } while(cnt < 5);
3583 if (cnt == 5) {
3584 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3585 ret = 1;
3586 }
3587
3588 return ret;
3589}
3590
1ee6dd77 3591static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3592{
1ee6dd77 3593 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3594 u64 val64;
3595 int i;
3596
75c30b13 3597 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3598 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3599 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
b7b5a128 3600 val64 = (s2BIT(7) | s2BIT(15) | vBIT(i, 26, 6));
cc6e7c44
RA		 3601 writeq(val64, &bar0->xmsi_access);
3602 if (wait_for_msix_trans(nic, i)) {
3603 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3604 continue;
3605 }
3606 }
3607}
3608
1ee6dd77 3609static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3610{
1ee6dd77 3611 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3612 u64 val64, addr, data;
3613 int i;
3614
3615 /* Store and display */
75c30b13 3616 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
b7b5a128 3617 val64 = (s2BIT(15) | vBIT(i, 26, 6));
cc6e7c44
RA		 3618 writeq(val64, &bar0->xmsi_access);
3619 if (wait_for_msix_trans(nic, i)) {
3620 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3621 continue;
3622 }
3623 addr = readq(&bar0->xmsi_address);
3624 data = readq(&bar0->xmsi_data);
3625 if (addr && data) {
3626 nic->msix_info[i].addr = addr;
3627 nic->msix_info[i].data = data;
3628 }
3629 }
3630}
3631
1ee6dd77 3632static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3633{
1ee6dd77 3634 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3635 u64 tx_mat, rx_mat;
3636 u16 msi_control; /* Temp variable */
3637 int ret, i, j, msix_indx = 1;
3638
bd684e43 3639 nic->entries = kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct msix_entry),
cc6e7c44 3640 GFP_KERNEL);
bd684e43 3641 if (!nic->entries) {
491976b2
SH		 3642 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3643 __FUNCTION__);
c53d4945 3644 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3645 return -ENOMEM;
3646 }
8a4bdbaa 3647 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 3648 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3649
3650 nic->s2io_entries =
bd684e43 3651 kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct s2io_msix_entry),
cc6e7c44 3652 GFP_KERNEL);
bd684e43 3653 if (!nic->s2io_entries) {
8a4bdbaa 3654 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
491976b2 3655 __FUNCTION__);
c53d4945 3656 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3657 kfree(nic->entries);
8a4bdbaa 3658 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3659 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3660 return -ENOMEM;
3661 }
8a4bdbaa 3662 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 3663 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3664
3665 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3666 nic->entries[i].entry = i;
3667 nic->s2io_entries[i].entry = i;
3668 nic->s2io_entries[i].arg = NULL;
3669 nic->s2io_entries[i].in_use = 0;
3670 }
3671
3672 tx_mat = readq(&bar0->tx_mat0_n[0]);
3673 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3674 tx_mat |= TX_MAT_SET(i, msix_indx);
3675 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3676 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3677 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3678 }
3679 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3680
8a4bdbaa
SS		 3681 rx_mat = readq(&bar0->rx_mat);
3682 for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
3683 rx_mat |= RX_MAT_SET(j, msix_indx);
3684 nic->s2io_entries[msix_indx].arg
3685 = &nic->mac_control.rings[j];
3686 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3687 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
cc6e7c44 3688 }
8a4bdbaa 3689 writeq(rx_mat, &bar0->rx_mat);
cc6e7c44 3690
c92ca04b 3691 nic->avail_msix_vectors = 0;
cc6e7c44 3692 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3693 /* We fail init if error or we get less vectors than min required */
3694 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3695 nic->avail_msix_vectors = ret;
3696 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3697 }
cc6e7c44
RA		 3698 if (ret) {
3699 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3700 kfree(nic->entries);
8a4bdbaa 3701 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3702 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44 3703 kfree(nic->s2io_entries);
8a4bdbaa 3704 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3705 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3706 nic->entries = NULL;
3707 nic->s2io_entries = NULL;
c92ca04b 3708 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3709 return -ENOMEM;
3710 }
c92ca04b
AR		 3711 if (!nic->avail_msix_vectors)
3712 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3713
3714 /*
3715 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3716 * in the herc NIC. (Temp change, needs to be removed later)
3717 */
3718 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3719 msi_control |= 0x1; /* Enable MSI */
3720 pci_write_config_word(nic->pdev, 0x42, msi_control);
3721
3722 return 0;
3723}
3724
8abc4d5b
SS		 3725/* Handle software interrupt used during MSI(X) test */
3726static irqreturn_t __devinit s2io_test_intr(int irq, void *dev_id)
3727{
3728 struct s2io_nic *sp = dev_id;
3729
3730 sp->msi_detected = 1;
3731 wake_up(&sp->msi_wait);
3732
3733 return IRQ_HANDLED;
3734}
3735
3736/* Test interrupt path by forcing a a software IRQ */
3737static int __devinit s2io_test_msi(struct s2io_nic *sp)
3738{
3739 struct pci_dev *pdev = sp->pdev;
3740 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3741 int err;
3742 u64 val64, saved64;
3743
3744 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3745 sp->name, sp);
3746 if (err) {
3747 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3748 sp->dev->name, pci_name(pdev), pdev->irq);
3749 return err;
3750 }
3751
3752 init_waitqueue_head (&sp->msi_wait);
3753 sp->msi_detected = 0;
3754
3755 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3756 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3757 val64 |= SCHED_INT_CTRL_TIMER_EN;
3758 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3759 writeq(val64, &bar0->scheduled_int_ctrl);
3760
3761 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3762
3763 if (!sp->msi_detected) {
3764 /* MSI(X) test failed, go back to INTx mode */
3765 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated"
3766 "using MSI(X) during test\n", sp->dev->name,
3767 pci_name(pdev));
3768
3769 err = -EOPNOTSUPP;
3770 }
3771
3772 free_irq(sp->entries[1].vector, sp);
3773
3774 writeq(saved64, &bar0->scheduled_int_ctrl);
3775
3776 return err;
3777}
18b2b7bd
SH		 3778
3779static void remove_msix_isr(struct s2io_nic *sp)
3780{
3781 int i;
3782 u16 msi_control;
3783
3784 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3785 if (sp->s2io_entries[i].in_use ==
3786 MSIX_REGISTERED_SUCCESS) {
3787 int vector = sp->entries[i].vector;
3788 void *arg = sp->s2io_entries[i].arg;
3789 free_irq(vector, arg);
3790 }
3791 }
3792
3793 kfree(sp->entries);
3794 kfree(sp->s2io_entries);
3795 sp->entries = NULL;
3796 sp->s2io_entries = NULL;
3797
3798 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3799 msi_control &= 0xFFFE; /* Disable MSI */
3800 pci_write_config_word(sp->pdev, 0x42, msi_control);
3801
3802 pci_disable_msix(sp->pdev);
3803}
3804
3805static void remove_inta_isr(struct s2io_nic *sp)
3806{
3807 struct net_device *dev = sp->dev;
3808
3809 free_irq(sp->pdev->irq, dev);
3810}
3811
1da177e4
LT		 3812/* ********************************************************* *
3813 * Functions defined below concern the OS part of the driver *
3814 * ********************************************************* */
3815
20346722 3816/**
1da177e4
LT		 3817 * s2io_open - open entry point of the driver
3818 * @dev : pointer to the device structure.
3819 * Description:
3820 * This function is the open entry point of the driver. It mainly calls a
3821 * function to allocate Rx buffers and inserts them into the buffer
20346722 3822 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3823 * Return value:
3824 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3825 * file on failure.
3826 */
3827
ac1f60db 3828static int s2io_open(struct net_device *dev)
1da177e4 3829{
1ee6dd77 3830 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3831 int err = 0;
3832
20346722
K		 3833 /*
3834 * Make sure you have link off by default every time
1da177e4
LT		 3835 * Nic is initialized
3836 */
3837 netif_carrier_off(dev);
0b1f7ebe 3838 sp->last_link_state = 0;
1da177e4 3839
bea3348e
SH		 3840 napi_enable(&sp->napi);
3841
eaae7f72 3842 if (sp->config.intr_type == MSI_X) {
8abc4d5b
SS		 3843 int ret = s2io_enable_msi_x(sp);
3844
3845 if (!ret) {
8abc4d5b 3846 ret = s2io_test_msi(sp);
8abc4d5b 3847 /* rollback MSI-X, will re-enable during add_isr() */
18b2b7bd 3848 remove_msix_isr(sp);
8abc4d5b
SS		 3849 }
3850 if (ret) {
3851
3852 DBG_PRINT(ERR_DBG,
3853 "%s: MSI-X requested but failed to enable\n",
3854 dev->name);
eaae7f72 3855 sp->config.intr_type = INTA;
8abc4d5b
SS		 3856 }
3857 }
3858
c77dd43e 3859 /* NAPI doesn't work well with MSI(X) */
eaae7f72 3860 if (sp->config.intr_type != INTA) {
c77dd43e
SS		 3861 if(sp->config.napi)
3862 sp->config.napi = 0;
3863 }
3864
1da177e4 3865 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3866 err = s2io_card_up(sp);
3867 if (err) {
1da177e4
LT		 3868 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3869 dev->name);
e6a8fee2 3870 goto hw_init_failed;
1da177e4
LT		 3871 }
3872
2fd37688 3873 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 3874 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3875 s2io_card_down(sp);
20346722 3876 err = -ENODEV;
e6a8fee2 3877 goto hw_init_failed;
1da177e4
LT		 3878 }
3879
3880 netif_start_queue(dev);
3881 return 0;
20346722 3882
20346722 3883hw_init_failed:
bea3348e 3884 napi_disable(&sp->napi);
eaae7f72 3885 if (sp->config.intr_type == MSI_X) {
491976b2 3886 if (sp->entries) {
cc6e7c44 3887 kfree(sp->entries);
8a4bdbaa 3888 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 3889 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3890 }
3891 if (sp->s2io_entries) {
cc6e7c44 3892 kfree(sp->s2io_entries);
8a4bdbaa 3893 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 3894 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3895 }
cc6e7c44 3896 }
20346722 3897 return err;
1da177e4
LT		 3898}
3899
3900/**
3901 * s2io_close -close entry point of the driver
3902 * @dev : device pointer.
3903 * Description:
3904 * This is the stop entry point of the driver. It needs to undo exactly
3905 * whatever was done by the open entry point,thus it's usually referred to
3906 * as the close function.Among other things this function mainly stops the
3907 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3908 * Return value:
3909 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3910 * file on failure.
3911 */
3912
ac1f60db 3913static int s2io_close(struct net_device *dev)
1da177e4 3914{
1ee6dd77 3915 struct s2io_nic *sp = dev->priv;
cc6e7c44 3916
1da177e4 3917 netif_stop_queue(dev);
bea3348e 3918 napi_disable(&sp->napi);
1da177e4 3919 /* Reset card, kill tasklet and free Tx and Rx buffers. */
e6a8fee2 3920 s2io_card_down(sp);
cc6e7c44 3921
1da177e4
LT		 3922 return 0;
3923}
3924
3925/**
3926 * s2io_xmit - Tx entry point of te driver
3927 * @skb : the socket buffer containing the Tx data.
3928 * @dev : device pointer.
3929 * Description :
3930 * This function is the Tx entry point of the driver. S2IO NIC supports
3931 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3932 * NOTE: when device cant queue the pkt,just the trans_start variable will
3933 * not be upadted.
3934 * Return value:
3935 * 0 on success & 1 on failure.
3936 */
3937
ac1f60db 3938static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 3939{
1ee6dd77 3940 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3941 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3942 register u64 val64;
1ee6dd77
RB		 3943 struct TxD *txdp;
3944 struct TxFIFO_element __iomem *tx_fifo;
1da177e4 3945 unsigned long flags;
be3a6b02
K		 3946 u16 vlan_tag = 0;
3947 int vlan_priority = 0;
1ee6dd77 3948 struct mac_info *mac_control;
1da177e4 3949 struct config_param *config;
75c30b13 3950 int offload_type;
491abf25 3951 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 3952
3953 mac_control = &sp->mac_control;
3954 config = &sp->config;
3955
20346722 3956 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 3957
3958 if (unlikely(skb->len <= 0)) {
3959 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3960 dev_kfree_skb_any(skb);
3961 return 0;
3962}
3963
1da177e4 3964 spin_lock_irqsave(&sp->tx_lock, flags);
92b84437 3965 if (!is_s2io_card_up(sp)) {
20346722 3966 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4
LT		 3967 dev->name);
3968 spin_unlock_irqrestore(&sp->tx_lock, flags);
20346722
K		 3969 dev_kfree_skb(skb);
3970 return 0;
1da177e4
LT		 3971 }
3972
3973 queue = 0;
be3a6b02
K		 3974 /* Get Fifo number to Transmit based on vlan priority */
3975 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3976 vlan_tag = vlan_tx_tag_get(skb);
3977 vlan_priority = vlan_tag >> 13;
3978 queue = config->fifo_mapping[vlan_priority];
3979 }
3980
20346722
K		 3981 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3982 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
1ee6dd77 3983 txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
20346722
K		 3984 list_virt_addr;
3985
3986 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
1da177e4 3987 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 3988 if (txdp->Host_Control ||
3989 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 3990 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
1da177e4
LT		 3991 netif_stop_queue(dev);
3992 dev_kfree_skb(skb);
3993 spin_unlock_irqrestore(&sp->tx_lock, flags);
3994 return 0;
3995 }
0b1f7ebe 3996
75c30b13 3997 offload_type = s2io_offload_type(skb);
75c30b13 3998 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 3999 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4000 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4001 }
84fa7933 4002 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 4003 txdp->Control_2 |=
4004 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4005 TXD_TX_CKO_UDP_EN);
4006 }
fed5eccd
AR		 4007 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4008 txdp->Control_1 |= TXD_LIST_OWN_XENA;
1da177e4 4009 txdp->Control_2 |= config->tx_intr_type;
d8892c6e 4010
be3a6b02
K		 4011 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4012 txdp->Control_2 |= TXD_VLAN_ENABLE;
4013 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4014 }
4015
fed5eccd 4016 frg_len = skb->len - skb->data_len;
75c30b13 4017 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4018 int ufo_size;
4019
75c30b13 4020 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4021 ufo_size &= ~7;
4022 txdp->Control_1 |= TXD_UFO_EN;
4023 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4024 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4025#ifdef __BIG_ENDIAN
4026 sp->ufo_in_band_v[put_off] =
4027 (u64)skb_shinfo(skb)->ip6_frag_id;
4028#else
4029 sp->ufo_in_band_v[put_off] =
4030 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
4031#endif
4032 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
4033 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4034 sp->ufo_in_band_v,
4035 sizeof(u64), PCI_DMA_TODEVICE);
491abf25
VP		 4036 if((txdp->Buffer_Pointer == 0) ||
4037 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4038 goto pci_map_failed;
fed5eccd 4039 txdp++;
fed5eccd 4040 }
1da177e4 4041
fed5eccd
AR		 4042 txdp->Buffer_Pointer = pci_map_single
4043 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
491abf25
VP		 4044 if((txdp->Buffer_Pointer == 0) ||
4045 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4046 goto pci_map_failed;
4047
fed5eccd
AR		 4048 txdp->Host_Control = (unsigned long) skb;
4049 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4050 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4051 txdp->Control_1 |= TXD_UFO_EN;
4052
4053 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4054 /* For fragmented SKB. */
4055 for (i = 0; i < frg_cnt; i++) {
4056 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4057 /* A '0' length fragment will be ignored */
4058 if (!frag->size)
4059 continue;
1da177e4
LT		 4060 txdp++;
4061 txdp->Buffer_Pointer = (u64) pci_map_page
4062 (sp->pdev, frag->page, frag->page_offset,
4063 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4064 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4065 if (offload_type == SKB_GSO_UDP)
fed5eccd 4066 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4067 }
4068 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4069
75c30b13 4070 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4071 frg_cnt++; /* as Txd0 was used for inband header */
4072
1da177e4 4073 tx_fifo = mac_control->tx_FIFO_start[queue];
20346722 4074 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
1da177e4
LT		 4075 writeq(val64, &tx_fifo->TxDL_Pointer);
4076
4077 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4078 TX_FIFO_LAST_LIST);
75c30b13 4079 if (offload_type)
fed5eccd 4080 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4081
1da177e4
LT		 4082 writeq(val64, &tx_fifo->List_Control);
4083
303bcb4b
K		 4084 mmiowb();
4085
1da177e4 4086 put_off++;
863c11a9
AR		 4087 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4088 put_off = 0;
20346722 4089 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
1da177e4
LT		 4090
4091 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4092 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4093 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4094 DBG_PRINT(TX_DBG,
4095 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4096 put_off, get_off);
4097 netif_stop_queue(dev);
4098 }
491976b2 4099 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
1da177e4
LT		 4100 dev->trans_start = jiffies;
4101 spin_unlock_irqrestore(&sp->tx_lock, flags);
4102
491abf25
VP		 4103 return 0;
4104pci_map_failed:
4105 stats->pci_map_fail_cnt++;
4106 netif_stop_queue(dev);
4107 stats->mem_freed += skb->truesize;
4108 dev_kfree_skb(skb);
4109 spin_unlock_irqrestore(&sp->tx_lock, flags);
1da177e4
LT		 4110 return 0;
4111}
4112
25fff88e
K		 4113static void
4114s2io_alarm_handle(unsigned long data)
4115{
1ee6dd77 4116 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4117 struct net_device *dev = sp->dev;
25fff88e 4118
8116f3cf 4119 s2io_handle_errors(dev);
25fff88e
K		 4120 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4121}
4122
1ee6dd77 4123static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
75c30b13
AR		 4124{
4125 int rxb_size, level;
4126
4127 if (!sp->lro) {
4128 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4129 level = rx_buffer_level(sp, rxb_size, rng_n);
4130
4131 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4132 int ret;
4133 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4134 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4135 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
0c61ed5f 4136 DBG_PRINT(INFO_DBG, "Out of memory in %s",
75c30b13
AR		 4137 __FUNCTION__);
4138 clear_bit(0, (&sp->tasklet_status));
4139 return -1;
4140 }
4141 clear_bit(0, (&sp->tasklet_status));
4142 } else if (level == LOW)
4143 tasklet_schedule(&sp->task);
4144
4145 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
0c61ed5f
RV		 4146 DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4147 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
75c30b13
AR		 4148 }
4149 return 0;
4150}
4151
7d12e780 4152static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4153{
1ee6dd77
RB		 4154 struct ring_info *ring = (struct ring_info *)dev_id;
4155 struct s2io_nic *sp = ring->nic;
cc6e7c44 4156
596c5c97 4157 if (!is_s2io_card_up(sp))
92b84437 4158 return IRQ_HANDLED;
92b84437 4159
75c30b13
AR		 4160 rx_intr_handler(ring);
4161 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4162
cc6e7c44
RA		 4163 return IRQ_HANDLED;
4164}
4165
7d12e780 4166static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4167{
1ee6dd77
RB		 4168 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4169 struct s2io_nic *sp = fifo->nic;
cc6e7c44 4170
596c5c97 4171 if (!is_s2io_card_up(sp))
92b84437 4172 return IRQ_HANDLED;
92b84437 4173
cc6e7c44 4174 tx_intr_handler(fifo);
cc6e7c44
RA		 4175 return IRQ_HANDLED;
4176}
1ee6dd77 4177static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4178{
1ee6dd77 4179 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4180 u64 val64;
4181
4182 val64 = readq(&bar0->pic_int_status);
4183 if (val64 & PIC_INT_GPIO) {
4184 val64 = readq(&bar0->gpio_int_reg);
4185 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4186 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4187 /*
4188 * This is unstable state so clear both up/down
4189 * interrupt and adapter to re-evaluate the link state.
4190 */
a371a07d
K		 4191 val64 |= GPIO_INT_REG_LINK_DOWN;
4192 val64 |= GPIO_INT_REG_LINK_UP;
4193 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4194 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4195 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4196 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4197 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4198 }
c92ca04b
AR		 4199 else if (val64 & GPIO_INT_REG_LINK_UP) {
4200 val64 = readq(&bar0->adapter_status);
c92ca04b 4201 /* Enable Adapter */
19a60522
SS		 4202 val64 = readq(&bar0->adapter_control);
4203 val64 |= ADAPTER_CNTL_EN;
4204 writeq(val64, &bar0->adapter_control);
4205 val64 |= ADAPTER_LED_ON;
4206 writeq(val64, &bar0->adapter_control);
4207 if (!sp->device_enabled_once)
4208 sp->device_enabled_once = 1;
c92ca04b 4209
19a60522
SS		 4210 s2io_link(sp, LINK_UP);
4211 /*
4212 * unmask link down interrupt and mask link-up
4213 * intr
4214 */
4215 val64 = readq(&bar0->gpio_int_mask);
4216 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4217 val64 |= GPIO_INT_MASK_LINK_UP;
4218 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4219
c92ca04b
AR		 4220 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4221 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4222 s2io_link(sp, LINK_DOWN);
4223 /* Link is down so unmaks link up interrupt */
4224 val64 = readq(&bar0->gpio_int_mask);
4225 val64 &= ~GPIO_INT_MASK_LINK_UP;
4226 val64 |= GPIO_INT_MASK_LINK_DOWN;
4227 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4228
4229 /* turn off LED */
4230 val64 = readq(&bar0->adapter_control);
4231 val64 = val64 &(~ADAPTER_LED_ON);
4232 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4233 }
4234 }
c92ca04b 4235 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4236}
4237
8116f3cf
SS		 4238/**
4239 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4240 * @value: alarm bits
4241 * @addr: address value
4242 * @cnt: counter variable
4243 * Description: Check for alarm and increment the counter
4244 * Return Value:
4245 * 1 - if alarm bit set
4246 * 0 - if alarm bit is not set
4247 */
43b7c451 4248static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
8116f3cf
SS		 4249 unsigned long long *cnt)
4250{
4251 u64 val64;
4252 val64 = readq(addr);
4253 if ( val64 & value ) {
4254 writeq(val64, addr);
4255 (*cnt)++;
4256 return 1;
4257 }
4258 return 0;
4259
4260}
4261
4262/**
4263 * s2io_handle_errors - Xframe error indication handler
4264 * @nic: device private variable
4265 * Description: Handle alarms such as loss of link, single or
4266 * double ECC errors, critical and serious errors.
4267 * Return Value:
4268 * NONE
4269 */
4270static void s2io_handle_errors(void * dev_id)
4271{
4272 struct net_device *dev = (struct net_device *) dev_id;
4273 struct s2io_nic *sp = dev->priv;
4274 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4275 u64 temp64 = 0,val64=0;
4276 int i = 0;
4277
4278 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4279 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4280
92b84437 4281 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4282 return;
4283
4284 if (pci_channel_offline(sp->pdev))
4285 return;
4286
4287 memset(&sw_stat->ring_full_cnt, 0,
4288 sizeof(sw_stat->ring_full_cnt));
4289
4290 /* Handling the XPAK counters update */
4291 if(stats->xpak_timer_count < 72000) {
4292 /* waiting for an hour */
4293 stats->xpak_timer_count++;
4294 } else {
4295 s2io_updt_xpak_counter(dev);
4296 /* reset the count to zero */
4297 stats->xpak_timer_count = 0;
4298 }
4299
4300 /* Handling link status change error Intr */
4301 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4302 val64 = readq(&bar0->mac_rmac_err_reg);
4303 writeq(val64, &bar0->mac_rmac_err_reg);
4304 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4305 schedule_work(&sp->set_link_task);
4306 }
4307
4308 /* In case of a serious error, the device will be Reset. */
4309 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4310 &sw_stat->serious_err_cnt))
4311 goto reset;
4312
4313 /* Check for data parity error */
4314 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4315 &sw_stat->parity_err_cnt))
4316 goto reset;
4317
4318 /* Check for ring full counter */
4319 if (sp->device_type == XFRAME_II_DEVICE) {
4320 val64 = readq(&bar0->ring_bump_counter1);
4321 for (i=0; i<4; i++) {
4322 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4323 temp64 >>= 64 - ((i+1)*16);
4324 sw_stat->ring_full_cnt[i] += temp64;
4325 }
4326
4327 val64 = readq(&bar0->ring_bump_counter2);
4328 for (i=0; i<4; i++) {
4329 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4330 temp64 >>= 64 - ((i+1)*16);
4331 sw_stat->ring_full_cnt[i+4] += temp64;
4332 }
4333 }
4334
4335 val64 = readq(&bar0->txdma_int_status);
4336 /*check for pfc_err*/
4337 if (val64 & TXDMA_PFC_INT) {
4338 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4339 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4340 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4341 &sw_stat->pfc_err_cnt))
4342 goto reset;
4343 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4344 &sw_stat->pfc_err_cnt);
4345 }
4346
4347 /*check for tda_err*/
4348 if (val64 & TXDMA_TDA_INT) {
4349 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4350 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4351 &sw_stat->tda_err_cnt))
4352 goto reset;
4353 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4354 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4355 }
4356 /*check for pcc_err*/
4357 if (val64 & TXDMA_PCC_INT) {
4358 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4359 | PCC_N_SERR | PCC_6_COF_OV_ERR
4360 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4361 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4362 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4363 &sw_stat->pcc_err_cnt))
4364 goto reset;
4365 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4366 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4367 }
4368
4369 /*check for tti_err*/
4370 if (val64 & TXDMA_TTI_INT) {
4371 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4372 &sw_stat->tti_err_cnt))
4373 goto reset;
4374 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4375 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4376 }
4377
4378 /*check for lso_err*/
4379 if (val64 & TXDMA_LSO_INT) {
4380 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4381 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4382 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4383 goto reset;
4384 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4385 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4386 }
4387
4388 /*check for tpa_err*/
4389 if (val64 & TXDMA_TPA_INT) {
4390 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4391 &sw_stat->tpa_err_cnt))
4392 goto reset;
4393 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4394 &sw_stat->tpa_err_cnt);
4395 }
4396
4397 /*check for sm_err*/
4398 if (val64 & TXDMA_SM_INT) {
4399 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4400 &sw_stat->sm_err_cnt))
4401 goto reset;
4402 }
4403
4404 val64 = readq(&bar0->mac_int_status);
4405 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4406 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4407 &bar0->mac_tmac_err_reg,
4408 &sw_stat->mac_tmac_err_cnt))
4409 goto reset;
4410 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4411 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4412 &bar0->mac_tmac_err_reg,
4413 &sw_stat->mac_tmac_err_cnt);
4414 }
4415
4416 val64 = readq(&bar0->xgxs_int_status);
4417 if (val64 & XGXS_INT_STATUS_TXGXS) {
4418 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4419 &bar0->xgxs_txgxs_err_reg,
4420 &sw_stat->xgxs_txgxs_err_cnt))
4421 goto reset;
4422 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4423 &bar0->xgxs_txgxs_err_reg,
4424 &sw_stat->xgxs_txgxs_err_cnt);
4425 }
4426
4427 val64 = readq(&bar0->rxdma_int_status);
4428 if (val64 & RXDMA_INT_RC_INT_M) {
4429 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4430 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4431 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4432 goto reset;
4433 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4434 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4435 &sw_stat->rc_err_cnt);
4436 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4437 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4438 &sw_stat->prc_pcix_err_cnt))
4439 goto reset;
4440 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4441 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4442 &sw_stat->prc_pcix_err_cnt);
4443 }
4444
4445 if (val64 & RXDMA_INT_RPA_INT_M) {
4446 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4447 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4448 goto reset;
4449 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4450 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4451 }
4452
4453 if (val64 & RXDMA_INT_RDA_INT_M) {
4454 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4455 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4456 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4457 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4458 goto reset;
4459 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4460 | RDA_MISC_ERR | RDA_PCIX_ERR,
4461 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4462 }
4463
4464 if (val64 & RXDMA_INT_RTI_INT_M) {
4465 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4466 &sw_stat->rti_err_cnt))
4467 goto reset;
4468 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4469 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4470 }
4471
4472 val64 = readq(&bar0->mac_int_status);
4473 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4474 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4475 &bar0->mac_rmac_err_reg,
4476 &sw_stat->mac_rmac_err_cnt))
4477 goto reset;
4478 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4479 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4480 &sw_stat->mac_rmac_err_cnt);
4481 }
4482
4483 val64 = readq(&bar0->xgxs_int_status);
4484 if (val64 & XGXS_INT_STATUS_RXGXS) {
4485 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4486 &bar0->xgxs_rxgxs_err_reg,
4487 &sw_stat->xgxs_rxgxs_err_cnt))
4488 goto reset;
4489 }
4490
4491 val64 = readq(&bar0->mc_int_status);
4492 if(val64 & MC_INT_STATUS_MC_INT) {
4493 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4494 &sw_stat->mc_err_cnt))
4495 goto reset;
4496
4497 /* Handling Ecc errors */
4498 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4499 writeq(val64, &bar0->mc_err_reg);
4500 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4501 sw_stat->double_ecc_errs++;
4502 if (sp->device_type != XFRAME_II_DEVICE) {
4503 /*
4504 * Reset XframeI only if critical error
4505 */
4506 if (val64 &
4507 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4508 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4509 goto reset;
4510 }
4511 } else
4512 sw_stat->single_ecc_errs++;
4513 }
4514 }
4515 return;
4516
4517reset:
4518 netif_stop_queue(dev);
4519 schedule_work(&sp->rst_timer_task);
4520 sw_stat->soft_reset_cnt++;
4521 return;
4522}
4523
1da177e4
LT		 4524/**
4525 * s2io_isr - ISR handler of the device .
4526 * @irq: the irq of the device.
4527 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4528 * Description: This function is the ISR handler of the device. It
4529 * identifies the reason for the interrupt and calls the relevant
4530 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4531 * recv buffers, if their numbers are below the panic value which is
4532 * presently set to 25% of the original number of rcv buffers allocated.
4533 * Return value:
20346722 4534 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4535 * IRQ_NONE: will be returned if interrupt is not from our device
4536 */
7d12e780 4537static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4538{
4539 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4540 struct s2io_nic *sp = dev->priv;
4541 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4542 int i;
19a60522 4543 u64 reason = 0;
1ee6dd77 4544 struct mac_info *mac_control;
1da177e4
LT		 4545 struct config_param *config;
4546
d796fdb7
LV		 4547 /* Pretend we handled any irq's from a disconnected card */
4548 if (pci_channel_offline(sp->pdev))
4549 return IRQ_NONE;
4550
596c5c97 4551 if (!is_s2io_card_up(sp))
92b84437 4552 return IRQ_NONE;
92b84437 4553
1da177e4
LT		 4554 mac_control = &sp->mac_control;
4555 config = &sp->config;
4556
20346722 4557 /*
1da177e4
LT		 4558 * Identify the cause for interrupt and call the appropriate
4559 * interrupt handler. Causes for the interrupt could be;
4560 * 1. Rx of packet.
4561 * 2. Tx complete.
4562 * 3. Link down.
1da177e4
LT		 4563 */
4564 reason = readq(&bar0->general_int_status);
4565
596c5c97
SS		 4566 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4567 /* Nothing much can be done. Get out */
4568 return IRQ_HANDLED;
1da177e4 4569 }
5d3213cc 4570
596c5c97
SS		 4571 if (reason & (GEN_INTR_RXTRAFFIC |
4572 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4573 {
4574 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4575
4576 if (config->napi) {
4577 if (reason & GEN_INTR_RXTRAFFIC) {
4578 if (likely(netif_rx_schedule_prep(dev,
4579 &sp->napi))) {
4580 __netif_rx_schedule(dev, &sp->napi);
4581 writeq(S2IO_MINUS_ONE,
4582 &bar0->rx_traffic_mask);
4583 } else
4584 writeq(S2IO_MINUS_ONE,
4585 &bar0->rx_traffic_int);
db874e65 4586 }
596c5c97
SS		 4587 } else {
4588 /*
4589 * rx_traffic_int reg is an R1 register, writing all 1's
4590 * will ensure that the actual interrupt causing bit
4591 * get's cleared and hence a read can be avoided.
4592 */
4593 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4594 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97
SS		 4595
4596 for (i = 0; i < config->rx_ring_num; i++)
4597 rx_intr_handler(&mac_control->rings[i]);
db874e65 4598 }
596c5c97 4599
db874e65 4600 /*
596c5c97 4601 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4602 * will ensure that the actual interrupt causing bit get's
4603 * cleared and hence a read can be avoided.
4604 */
596c5c97
SS		 4605 if (reason & GEN_INTR_TXTRAFFIC)
4606 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4607
596c5c97
SS		 4608 for (i = 0; i < config->tx_fifo_num; i++)
4609 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4610
596c5c97
SS		 4611 if (reason & GEN_INTR_TXPIC)
4612 s2io_txpic_intr_handle(sp);
fe113638 4613
596c5c97
SS		 4614 /*
4615 * Reallocate the buffers from the interrupt handler itself.
4616 */
4617 if (!config->napi) {
4618 for (i = 0; i < config->rx_ring_num; i++)
4619 s2io_chk_rx_buffers(sp, i);
4620 }
4621 writeq(sp->general_int_mask, &bar0->general_int_mask);
4622 readl(&bar0->general_int_status);
20346722 4623
596c5c97 4624 return IRQ_HANDLED;
db874e65 4625
596c5c97
SS		 4626 }
4627 else if (!reason) {
4628 /* The interrupt was not raised by us */
4629 return IRQ_NONE;
4630 }
db874e65 4631
1da177e4
LT		 4632 return IRQ_HANDLED;
4633}
4634
7ba013ac
K		 4635/**
4636 * s2io_updt_stats -
4637 */
1ee6dd77 4638static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4639{
1ee6dd77 4640 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4641 u64 val64;
4642 int cnt = 0;
4643
92b84437 4644 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4645 /* Apprx 30us on a 133 MHz bus */
4646 val64 = SET_UPDT_CLICKS(10) |
4647 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4648 writeq(val64, &bar0->stat_cfg);
4649 do {
4650 udelay(100);
4651 val64 = readq(&bar0->stat_cfg);
b7b5a128 4652 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4653 break;
4654 cnt++;
4655 if (cnt == 5)
4656 break; /* Updt failed */
4657 } while(1);
8a4bdbaa 4658 }
7ba013ac
K		 4659}
4660
1da177e4 4661/**
20346722 4662 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4663 * @dev : pointer to the device structure.
4664 * Description:
20346722 4665 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4666 * structure and returns a pointer to the same.
4667 * Return value:
4668 * pointer to the updated net_device_stats structure.
4669 */
4670
ac1f60db 4671static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4672{
1ee6dd77
RB		 4673 struct s2io_nic *sp = dev->priv;
4674 struct mac_info *mac_control;
1da177e4
LT		 4675 struct config_param *config;
4676
20346722 4677
1da177e4
LT		 4678 mac_control = &sp->mac_control;
4679 config = &sp->config;
4680
7ba013ac
K		 4681 /* Configure Stats for immediate updt */
4682 s2io_updt_stats(sp);
4683
4684 sp->stats.tx_packets =
4685 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722
K		 4686 sp->stats.tx_errors =
4687 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4688 sp->stats.rx_errors =
ee705dba 4689 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722
K		 4690 sp->stats.multicast =
4691 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4692 sp->stats.rx_length_errors =
ee705dba 4693 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4694
4695 return (&sp->stats);
4696}
4697
4698/**
4699 * s2io_set_multicast - entry point for multicast address enable/disable.
4700 * @dev : pointer to the device structure
4701 * Description:
20346722
K		 4702 * This function is a driver entry point which gets called by the kernel
4703 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4704 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4705 * determine, if multicast address must be enabled or if promiscuous mode
4706 * is to be disabled etc.
4707 * Return value:
4708 * void.
4709 */
4710
4711static void s2io_set_multicast(struct net_device *dev)
4712{
4713 int i, j, prev_cnt;
4714 struct dev_mc_list *mclist;
1ee6dd77
RB		 4715 struct s2io_nic *sp = dev->priv;
4716 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4717 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4718 0xfeffffffffffULL;
4719 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4720 void __iomem *add;
4721
4722 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4723 /* Enable all Multicast addresses */
4724 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4725 &bar0->rmac_addr_data0_mem);
4726 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4727 &bar0->rmac_addr_data1_mem);
4728 val64 = RMAC_ADDR_CMD_MEM_WE |
4729 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4730 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4731 writeq(val64, &bar0->rmac_addr_cmd_mem);
4732 /* Wait till command completes */
c92ca04b 4733 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4734 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4735 S2IO_BIT_RESET);
1da177e4
LT		 4736
4737 sp->m_cast_flg = 1;
4738 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4739 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4740 /* Disable all Multicast addresses */
4741 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4742 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4743 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4744 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4745 val64 = RMAC_ADDR_CMD_MEM_WE |
4746 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4747 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4748 writeq(val64, &bar0->rmac_addr_cmd_mem);
4749 /* Wait till command completes */
c92ca04b 4750 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4751 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4752 S2IO_BIT_RESET);
1da177e4
LT		 4753
4754 sp->m_cast_flg = 0;
4755 sp->all_multi_pos = 0;
4756 }
4757
4758 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4759 /* Put the NIC into promiscuous mode */
4760 add = &bar0->mac_cfg;
4761 val64 = readq(&bar0->mac_cfg);
4762 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4763
4764 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4765 writel((u32) val64, add);
4766 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4767 writel((u32) (val64 >> 32), (add + 4));
4768
926930b2
SS		 4769 if (vlan_tag_strip != 1) {
4770 val64 = readq(&bar0->rx_pa_cfg);
4771 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4772 writeq(val64, &bar0->rx_pa_cfg);
4773 vlan_strip_flag = 0;
4774 }
4775
1da177e4
LT		 4776 val64 = readq(&bar0->mac_cfg);
4777 sp->promisc_flg = 1;
776bd20f 4778 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4779 dev->name);
4780 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4781 /* Remove the NIC from promiscuous mode */
4782 add = &bar0->mac_cfg;
4783 val64 = readq(&bar0->mac_cfg);
4784 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4785
4786 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4787 writel((u32) val64, add);
4788 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4789 writel((u32) (val64 >> 32), (add + 4));
4790
926930b2
SS		 4791 if (vlan_tag_strip != 0) {
4792 val64 = readq(&bar0->rx_pa_cfg);
4793 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4794 writeq(val64, &bar0->rx_pa_cfg);
4795 vlan_strip_flag = 1;
4796 }
4797
1da177e4
LT		 4798 val64 = readq(&bar0->mac_cfg);
4799 sp->promisc_flg = 0;
776bd20f 4800 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4801 dev->name);
4802 }
4803
4804 /* Update individual M_CAST address list */
4805 if ((!sp->m_cast_flg) && dev->mc_count) {
4806 if (dev->mc_count >
4807 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4808 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4809 dev->name);
4810 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4811 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4812 return;
4813 }
4814
4815 prev_cnt = sp->mc_addr_count;
4816 sp->mc_addr_count = dev->mc_count;
4817
4818 /* Clear out the previous list of Mc in the H/W. */
4819 for (i = 0; i < prev_cnt; i++) {
4820 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4821 &bar0->rmac_addr_data0_mem);
4822 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4823 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4824 val64 = RMAC_ADDR_CMD_MEM_WE |
4825 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4826 RMAC_ADDR_CMD_MEM_OFFSET
4827 (MAC_MC_ADDR_START_OFFSET + i);
4828 writeq(val64, &bar0->rmac_addr_cmd_mem);
4829
4830 /* Wait for command completes */
c92ca04b 4831 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4832 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4833 S2IO_BIT_RESET)) {
1da177e4
LT		 4834 DBG_PRINT(ERR_DBG, "%s: Adding ",
4835 dev->name);
4836 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4837 return;
4838 }
4839 }
4840
4841 /* Create the new Rx filter list and update the same in H/W. */
4842 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4843 i++, mclist = mclist->next) {
4844 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4845 ETH_ALEN);
a7a80d5a 4846 mac_addr = 0;
1da177e4
LT		 4847 for (j = 0; j < ETH_ALEN; j++) {
4848 mac_addr |= mclist->dmi_addr[j];
4849 mac_addr <<= 8;
4850 }
4851 mac_addr >>= 8;
4852 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4853 &bar0->rmac_addr_data0_mem);
4854 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4855 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4856 val64 = RMAC_ADDR_CMD_MEM_WE |
4857 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4858 RMAC_ADDR_CMD_MEM_OFFSET
4859 (i + MAC_MC_ADDR_START_OFFSET);
4860 writeq(val64, &bar0->rmac_addr_cmd_mem);
4861
4862 /* Wait for command completes */
c92ca04b 4863 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4864 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4865 S2IO_BIT_RESET)) {
1da177e4
LT		 4866 DBG_PRINT(ERR_DBG, "%s: Adding ",
4867 dev->name);
4868 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4869 return;
4870 }
4871 }
4872 }
4873}
4874
2fd37688
SS		 4875/* add unicast MAC address to CAM */
4876static int do_s2io_add_unicast(struct s2io_nic *sp, u64 addr, int off)
4877{
4878 u64 val64;
4879 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4880
4881 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
4882 &bar0->rmac_addr_data0_mem);
4883
4884 val64 =
4885 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4886 RMAC_ADDR_CMD_MEM_OFFSET(off);
4887 writeq(val64, &bar0->rmac_addr_cmd_mem);
4888
4889 /* Wait till command completes */
4890 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4891 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4892 S2IO_BIT_RESET)) {
4893 DBG_PRINT(INFO_DBG, "add_mac_addr failed\n");
4894 return FAILURE;
4895 }
4896 return SUCCESS;
4897}
4898
4899/**
4900 * s2io_set_mac_addr driver entry point
4901 */
4902static int s2io_set_mac_addr(struct net_device *dev, void *p)
4903{
4904 struct sockaddr *addr = p;
4905
4906 if (!is_valid_ether_addr(addr->sa_data))
4907 return -EINVAL;
4908
4909 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4910
4911 /* store the MAC address in CAM */
4912 return (do_s2io_prog_unicast(dev, dev->dev_addr));
4913}
4914
1da177e4 4915/**
2fd37688 4916 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 4917 * @dev : pointer to the device structure.
4918 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 4919 * Description : This procedure will program the Xframe to receive
1da177e4 4920 * frames with new Mac Address
20346722 4921 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 4922 * as defined in errno.h file on failure.
4923 */
2fd37688 4924static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 4925{
1ee6dd77 4926 struct s2io_nic *sp = dev->priv;
2fd37688 4927 register u64 mac_addr = 0, perm_addr = 0;
1da177e4
LT		 4928 int i;
4929
20346722 4930 /*
2fd37688
SS		 4931 * Set the new MAC address as the new unicast filter and reflect this
4932 * change on the device address registered with the OS. It will be
4933 * at offset 0.
4934 */
1da177e4
LT		 4935 for (i = 0; i < ETH_ALEN; i++) {
4936 mac_addr <<= 8;
4937 mac_addr |= addr[i];
2fd37688
SS		 4938 perm_addr <<= 8;
4939 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 4940 }
4941
2fd37688
SS		 4942 /* check if the dev_addr is different than perm_addr */
4943 if (mac_addr == perm_addr)
d8d70caf
SS		 4944 return SUCCESS;
4945
4946 /* Update the internal structure with this new mac address */
2fd37688
SS		 4947 do_s2io_copy_mac_addr(sp, 0, mac_addr);
4948 return (do_s2io_add_unicast(sp, mac_addr, 0));
1da177e4
LT		 4949}
4950
4951/**
20346722 4952 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 4953 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4954 * @info: pointer to the structure with parameters given by ethtool to set
4955 * link information.
4956 * Description:
20346722 4957 * The function sets different link parameters provided by the user onto
1da177e4
LT		 4958 * the NIC.
4959 * Return value:
4960 * 0 on success.
4961*/
4962
4963static int s2io_ethtool_sset(struct net_device *dev,
4964 struct ethtool_cmd *info)
4965{
1ee6dd77 4966 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4967 if ((info->autoneg == AUTONEG_ENABLE) ||
4968 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4969 return -EINVAL;
4970 else {
4971 s2io_close(sp->dev);
4972 s2io_open(sp->dev);
4973 }
4974
4975 return 0;
4976}
4977
4978/**
20346722 4979 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 4980 * @sp : private member of the device structure, pointer to the
4981 * s2io_nic structure.
4982 * @info : pointer to the structure with parameters given by ethtool
4983 * to return link information.
4984 * Description:
4985 * Returns link specific information like speed, duplex etc.. to ethtool.
4986 * Return value :
4987 * return 0 on success.
4988 */
4989
4990static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4991{
1ee6dd77 4992 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4993 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4994 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4995 info->port = PORT_FIBRE;
1a7eb72b
SS		 4996
4997 /* info->transceiver */
4998 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 4999
5000 if (netif_carrier_ok(sp->dev)) {
5001 info->speed = 10000;
5002 info->duplex = DUPLEX_FULL;
5003 } else {
5004 info->speed = -1;
5005 info->duplex = -1;
5006 }
5007
5008 info->autoneg = AUTONEG_DISABLE;
5009 return 0;
5010}
5011
5012/**
20346722
K		 5013 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5014 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5015 * s2io_nic structure.
5016 * @info : pointer to the structure with parameters given by ethtool to
5017 * return driver information.
5018 * Description:
5019 * Returns driver specefic information like name, version etc.. to ethtool.
5020 * Return value:
5021 * void
5022 */
5023
5024static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5025 struct ethtool_drvinfo *info)
5026{
1ee6dd77 5027 struct s2io_nic *sp = dev->priv;
1da177e4 5028
dbc2309d
JL		 5029 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5030 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5031 strncpy(info->fw_version, "", sizeof(info->fw_version));
5032 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5033 info->regdump_len = XENA_REG_SPACE;
5034 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5035}
5036
5037/**
5038 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5039 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5040 * s2io_nic structure.
20346722 5041 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5042 * dumping the registers.
5043 * @reg_space: The input argumnet into which all the registers are dumped.
5044 * Description:
5045 * Dumps the entire register space of xFrame NIC into the user given
5046 * buffer area.
5047 * Return value :
5048 * void .
5049*/
5050
5051static void s2io_ethtool_gregs(struct net_device *dev,
5052 struct ethtool_regs *regs, void *space)
5053{
5054 int i;
5055 u64 reg;
5056 u8 *reg_space = (u8 *) space;
1ee6dd77 5057 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5058
5059 regs->len = XENA_REG_SPACE;
5060 regs->version = sp->pdev->subsystem_device;
5061
5062 for (i = 0; i < regs->len; i += 8) {
5063 reg = readq(sp->bar0 + i);
5064 memcpy((reg_space + i), &reg, 8);
5065 }
5066}
5067
5068/**
5069 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5070 * @data : address of the private member of the device structure, which
1da177e4 5071 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 5072 * Description: This is actually the timer function that alternates the
5073 * adapter LED bit of the adapter control bit to set/reset every time on
5074 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 5075 * once every second.
5076*/
5077static void s2io_phy_id(unsigned long data)
5078{
1ee6dd77
RB		 5079 struct s2io_nic *sp = (struct s2io_nic *) data;
5080 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5081 u64 val64 = 0;
5082 u16 subid;
5083
5084 subid = sp->pdev->subsystem_device;
541ae68f
K		 5085 if ((sp->device_type == XFRAME_II_DEVICE) ||
5086 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5087 val64 = readq(&bar0->gpio_control);
5088 val64 ^= GPIO_CTRL_GPIO_0;
5089 writeq(val64, &bar0->gpio_control);
5090 } else {
5091 val64 = readq(&bar0->adapter_control);
5092 val64 ^= ADAPTER_LED_ON;
5093 writeq(val64, &bar0->adapter_control);
5094 }
5095
5096 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5097}
5098
5099/**
5100 * s2io_ethtool_idnic - To physically identify the nic on the system.
5101 * @sp : private member of the device structure, which is a pointer to the
5102 * s2io_nic structure.
20346722 5103 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5104 * ethtool.
5105 * Description: Used to physically identify the NIC on the system.
20346722 5106 * The Link LED will blink for a time specified by the user for
1da177e4 5107 * identification.
20346722 5108 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5109 * identification is possible only if it's link is up.
5110 * Return value:
5111 * int , returns 0 on success
5112 */
5113
5114static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5115{
5116 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 5117 struct s2io_nic *sp = dev->priv;
5118 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5119 u16 subid;
5120
5121 subid = sp->pdev->subsystem_device;
5122 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f
K		 5123 if ((sp->device_type == XFRAME_I_DEVICE) &&
5124 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5125 val64 = readq(&bar0->adapter_control);
5126 if (!(val64 & ADAPTER_CNTL_EN)) {
5127 printk(KERN_ERR
5128 "Adapter Link down, cannot blink LED\n");
5129 return -EFAULT;
5130 }
5131 }
5132 if (sp->id_timer.function == NULL) {
5133 init_timer(&sp->id_timer);
5134 sp->id_timer.function = s2io_phy_id;
5135 sp->id_timer.data = (unsigned long) sp;
5136 }
5137 mod_timer(&sp->id_timer, jiffies);
5138 if (data)
20346722 5139 msleep_interruptible(data * HZ);
1da177e4 5140 else
20346722 5141 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5142 del_timer_sync(&sp->id_timer);
5143
541ae68f 5144 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5145 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5146 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5147 }
5148
5149 return 0;
5150}
5151
0cec35eb
SH		 5152static void s2io_ethtool_gringparam(struct net_device *dev,
5153 struct ethtool_ringparam *ering)
5154{
5155 struct s2io_nic *sp = dev->priv;
5156 int i,tx_desc_count=0,rx_desc_count=0;
5157
5158 if (sp->rxd_mode == RXD_MODE_1)
5159 ering->rx_max_pending = MAX_RX_DESC_1;
5160 else if (sp->rxd_mode == RXD_MODE_3B)
5161 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5162
5163 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5164 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5165 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5166
0cec35eb
SH		 5167 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5168 ering->tx_pending = tx_desc_count;
5169 rx_desc_count = 0;
8a4bdbaa 5170 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5171 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5172
0cec35eb
SH		 5173 ering->rx_pending = rx_desc_count;
5174
5175 ering->rx_mini_max_pending = 0;
5176 ering->rx_mini_pending = 0;
5177 if(sp->rxd_mode == RXD_MODE_1)
5178 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5179 else if (sp->rxd_mode == RXD_MODE_3B)
5180 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5181 ering->rx_jumbo_pending = rx_desc_count;
5182}
5183
1da177e4
LT		 5184/**
5185 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5186 * @sp : private member of the device structure, which is a pointer to the
5187 * s2io_nic structure.
1da177e4
LT		 5188 * @ep : pointer to the structure with pause parameters given by ethtool.
5189 * Description:
5190 * Returns the Pause frame generation and reception capability of the NIC.
5191 * Return value:
5192 * void
5193 */
5194static void s2io_ethtool_getpause_data(struct net_device *dev,
5195 struct ethtool_pauseparam *ep)
5196{
5197 u64 val64;
1ee6dd77
RB		 5198 struct s2io_nic *sp = dev->priv;
5199 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5200
5201 val64 = readq(&bar0->rmac_pause_cfg);
5202 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5203 ep->tx_pause = TRUE;
5204 if (val64 & RMAC_PAUSE_RX_ENABLE)
5205 ep->rx_pause = TRUE;
5206 ep->autoneg = FALSE;
5207}
5208
5209/**
5210 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5211 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5212 * s2io_nic structure.
5213 * @ep : pointer to the structure with pause parameters given by ethtool.
5214 * Description:
5215 * It can be used to set or reset Pause frame generation or reception
5216 * support of the NIC.
5217 * Return value:
5218 * int, returns 0 on Success
5219 */
5220
5221static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 5222 struct ethtool_pauseparam *ep)
1da177e4
LT		 5223{
5224 u64 val64;
1ee6dd77
RB		 5225 struct s2io_nic *sp = dev->priv;
5226 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5227
5228 val64 = readq(&bar0->rmac_pause_cfg);
5229 if (ep->tx_pause)
5230 val64 |= RMAC_PAUSE_GEN_ENABLE;
5231 else
5232 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5233 if (ep->rx_pause)
5234 val64 |= RMAC_PAUSE_RX_ENABLE;
5235 else
5236 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5237 writeq(val64, &bar0->rmac_pause_cfg);
5238 return 0;
5239}
5240
5241/**
5242 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5243 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5244 * s2io_nic structure.
5245 * @off : offset at which the data must be written
5246 * @data : Its an output parameter where the data read at the given
20346722 5247 * offset is stored.
1da177e4 5248 * Description:
20346722 5249 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5250 * read data.
5251 * NOTE: Will allow to read only part of the EEPROM visible through the
5252 * I2C bus.
5253 * Return value:
5254 * -1 on failure and 0 on success.
5255 */
5256
5257#define S2IO_DEV_ID 5
1ee6dd77 5258static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 5259{
5260 int ret = -1;
5261 u32 exit_cnt = 0;
5262 u64 val64;
1ee6dd77 5263 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5264
ad4ebed0 5265 if (sp->device_type == XFRAME_I_DEVICE) {
5266 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5267 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5268 I2C_CONTROL_CNTL_START;
5269 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5270
ad4ebed0 5271 while (exit_cnt < 5) {
5272 val64 = readq(&bar0->i2c_control);
5273 if (I2C_CONTROL_CNTL_END(val64)) {
5274 *data = I2C_CONTROL_GET_DATA(val64);
5275 ret = 0;
5276 break;
5277 }
5278 msleep(50);
5279 exit_cnt++;
1da177e4 5280 }
1da177e4
LT		 5281 }
5282
ad4ebed0 5283 if (sp->device_type == XFRAME_II_DEVICE) {
5284 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5285 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5286 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5287 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5288 val64 |= SPI_CONTROL_REQ;
5289 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5290 while (exit_cnt < 5) {
5291 val64 = readq(&bar0->spi_control);
5292 if (val64 & SPI_CONTROL_NACK) {
5293 ret = 1;
5294 break;
5295 } else if (val64 & SPI_CONTROL_DONE) {
5296 *data = readq(&bar0->spi_data);
5297 *data &= 0xffffff;
5298 ret = 0;
5299 break;
5300 }
5301 msleep(50);
5302 exit_cnt++;
5303 }
5304 }
1da177e4
LT		 5305 return ret;
5306}
5307
5308/**
5309 * write_eeprom - actually writes the relevant part of the data value.
5310 * @sp : private member of the device structure, which is a pointer to the
5311 * s2io_nic structure.
5312 * @off : offset at which the data must be written
5313 * @data : The data that is to be written
20346722 5314 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5315 * the Eeprom. (max of 3)
5316 * Description:
5317 * Actually writes the relevant part of the data value into the Eeprom
5318 * through the I2C bus.
5319 * Return value:
5320 * 0 on success, -1 on failure.
5321 */
5322
1ee6dd77 5323static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5324{
5325 int exit_cnt = 0, ret = -1;
5326 u64 val64;
1ee6dd77 5327 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5328
ad4ebed0 5329 if (sp->device_type == XFRAME_I_DEVICE) {
5330 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5331 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5332 I2C_CONTROL_CNTL_START;
5333 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5334
5335 while (exit_cnt < 5) {
5336 val64 = readq(&bar0->i2c_control);
5337 if (I2C_CONTROL_CNTL_END(val64)) {
5338 if (!(val64 & I2C_CONTROL_NACK))
5339 ret = 0;
5340 break;
5341 }
5342 msleep(50);
5343 exit_cnt++;
5344 }
5345 }
1da177e4 5346
ad4ebed0 5347 if (sp->device_type == XFRAME_II_DEVICE) {
5348 int write_cnt = (cnt == 8) ? 0 : cnt;
5349 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5350
5351 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5352 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5353 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5354 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5355 val64 |= SPI_CONTROL_REQ;
5356 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5357 while (exit_cnt < 5) {
5358 val64 = readq(&bar0->spi_control);
5359 if (val64 & SPI_CONTROL_NACK) {
5360 ret = 1;
5361 break;
5362 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5363 ret = 0;
ad4ebed0 5364 break;
5365 }
5366 msleep(50);
5367 exit_cnt++;
1da177e4 5368 }
1da177e4 5369 }
1da177e4
LT		 5370 return ret;
5371}
1ee6dd77 5372static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5373{
b41477f3
AR		 5374 u8 *vpd_data;
5375 u8 data;
9dc737a7
AR		 5376 int i=0, cnt, fail = 0;
5377 int vpd_addr = 0x80;
5378
5379 if (nic->device_type == XFRAME_II_DEVICE) {
5380 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5381 vpd_addr = 0x80;
5382 }
5383 else {
5384 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5385 vpd_addr = 0x50;
5386 }
19a60522 5387 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5388
b41477f3 5389 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5390 if (!vpd_data) {
5391 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5392 return;
c53d4945 5393 }
491976b2 5394 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5395
9dc737a7
AR		 5396 for (i = 0; i < 256; i +=4 ) {
5397 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5398 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5399 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5400 for (cnt = 0; cnt <5; cnt++) {
5401 msleep(2);
5402 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5403 if (data == 0x80)
5404 break;
5405 }
5406 if (cnt >= 5) {
5407 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5408 fail = 1;
5409 break;
5410 }
5411 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5412 (u32 *)&vpd_data[i]);
5413 }
19a60522
SS		 5414
5415 if(!fail) {
5416 /* read serial number of adapter */
5417 for (cnt = 0; cnt < 256; cnt++) {
5418 if ((vpd_data[cnt] == 'S') &&
5419 (vpd_data[cnt+1] == 'N') &&
5420 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5421 memset(nic->serial_num, 0, VPD_STRING_LEN);
5422 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5423 vpd_data[cnt+2]);
5424 break;
5425 }
5426 }
5427 }
5428
5429 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5430 memset(nic->product_name, 0, vpd_data[1]);
5431 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5432 }
b41477f3 5433 kfree(vpd_data);
491976b2 5434 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5435}
5436
1da177e4
LT		 5437/**
5438 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5439 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5440 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5441 * containing all relevant information.
5442 * @data_buf : user defined value to be written into Eeprom.
5443 * Description: Reads the values stored in the Eeprom at given offset
5444 * for a given length. Stores these values int the input argument data
5445 * buffer 'data_buf' and returns these to the caller (ethtool.)
5446 * Return value:
5447 * int 0 on success
5448 */
5449
5450static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5451 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5452{
ad4ebed0 5453 u32 i, valid;
5454 u64 data;
1ee6dd77 5455 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5456
5457 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5458
5459 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5460 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5461
5462 for (i = 0; i < eeprom->len; i += 4) {
5463 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5464 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5465 return -EFAULT;
5466 }
5467 valid = INV(data);
5468 memcpy((data_buf + i), &valid, 4);
5469 }
5470 return 0;
5471}
5472
5473/**
5474 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5475 * @sp : private member of the device structure, which is a pointer to the
5476 * s2io_nic structure.
20346722 5477 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5478 * containing all relevant information.
5479 * @data_buf ; user defined value to be written into Eeprom.
5480 * Description:
5481 * Tries to write the user provided value in the Eeprom, at the offset
5482 * given by the user.
5483 * Return value:
5484 * 0 on success, -EFAULT on failure.
5485 */
5486
5487static int s2io_ethtool_seeprom(struct net_device *dev,
5488 struct ethtool_eeprom *eeprom,
5489 u8 * data_buf)
5490{
5491 int len = eeprom->len, cnt = 0;
ad4ebed0 5492 u64 valid = 0, data;
1ee6dd77 5493 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5494
5495 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5496 DBG_PRINT(ERR_DBG,
5497 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5498 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5499 eeprom->magic);
5500 return -EFAULT;
5501 }
5502
5503 while (len) {
5504 data = (u32) data_buf[cnt] & 0x000000FF;
5505 if (data) {
5506 valid = (u32) (data << 24);
5507 } else
5508 valid = data;
5509
5510 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5511 DBG_PRINT(ERR_DBG,
5512 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5513 DBG_PRINT(ERR_DBG,
5514 "write into the specified offset\n");
5515 return -EFAULT;
5516 }
5517 cnt++;
5518 len--;
5519 }
5520
5521 return 0;
5522}
5523
5524/**
20346722
K		 5525 * s2io_register_test - reads and writes into all clock domains.
5526 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5527 * s2io_nic structure.
5528 * @data : variable that returns the result of each of the test conducted b
5529 * by the driver.
5530 * Description:
5531 * Read and write into all clock domains. The NIC has 3 clock domains,
5532 * see that registers in all the three regions are accessible.
5533 * Return value:
5534 * 0 on success.
5535 */
5536
1ee6dd77 5537static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5538{
1ee6dd77 5539 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5540 u64 val64 = 0, exp_val;
1da177e4
LT		 5541 int fail = 0;
5542
20346722
K		 5543 val64 = readq(&bar0->pif_rd_swapper_fb);
5544 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5545 fail = 1;
5546 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5547 }
5548
5549 val64 = readq(&bar0->rmac_pause_cfg);
5550 if (val64 != 0xc000ffff00000000ULL) {
5551 fail = 1;
5552 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5553 }
5554
5555 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5556 if (sp->device_type == XFRAME_II_DEVICE)
5557 exp_val = 0x0404040404040404ULL;
5558 else
5559 exp_val = 0x0808080808080808ULL;
5560 if (val64 != exp_val) {
1da177e4
LT		 5561 fail = 1;
5562 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5563 }
5564
5565 val64 = readq(&bar0->xgxs_efifo_cfg);
5566 if (val64 != 0x000000001923141EULL) {
5567 fail = 1;
5568 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5569 }
5570
5571 val64 = 0x5A5A5A5A5A5A5A5AULL;
5572 writeq(val64, &bar0->xmsi_data);
5573 val64 = readq(&bar0->xmsi_data);
5574 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5575 fail = 1;
5576 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5577 }
5578
5579 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5580 writeq(val64, &bar0->xmsi_data);
5581 val64 = readq(&bar0->xmsi_data);
5582 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5583 fail = 1;
5584 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5585 }
5586
5587 *data = fail;
ad4ebed0 5588 return fail;
1da177e4
LT		 5589}
5590
5591/**
20346722 5592 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5593 * @sp : private member of the device structure, which is a pointer to the
5594 * s2io_nic structure.
5595 * @data:variable that returns the result of each of the test conducted by
5596 * the driver.
5597 * Description:
20346722 5598 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5599 * register.
5600 * Return value:
5601 * 0 on success.
5602 */
5603
1ee6dd77 5604static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5605{
5606 int fail = 0;
ad4ebed0 5607 u64 ret_data, org_4F0, org_7F0;
5608 u8 saved_4F0 = 0, saved_7F0 = 0;
5609 struct net_device *dev = sp->dev;
1da177e4
LT		 5610
5611 /* Test Write Error at offset 0 */
ad4ebed0 5612 /* Note that SPI interface allows write access to all areas
5613 * of EEPROM. Hence doing all negative testing only for Xframe I.
5614 */
5615 if (sp->device_type == XFRAME_I_DEVICE)
5616 if (!write_eeprom(sp, 0, 0, 3))
5617 fail = 1;
5618
5619 /* Save current values at offsets 0x4F0 and 0x7F0 */
5620 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5621 saved_4F0 = 1;
5622 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5623 saved_7F0 = 1;
1da177e4
LT		 5624
5625 /* Test Write at offset 4f0 */
ad4ebed0 5626 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5627 fail = 1;
5628 if (read_eeprom(sp, 0x4F0, &ret_data))
5629 fail = 1;
5630
ad4ebed0 5631 if (ret_data != 0x012345) {
26b7625c
AM		 5632 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5633 "Data written %llx Data read %llx\n",
5634 dev->name, (unsigned long long)0x12345,
5635 (unsigned long long)ret_data);
1da177e4 5636 fail = 1;
ad4ebed0 5637 }
1da177e4
LT		 5638
5639 /* Reset the EEPROM data go FFFF */
ad4ebed0 5640 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5641
5642 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5643 if (sp->device_type == XFRAME_I_DEVICE)
5644 if (!write_eeprom(sp, 0x07C, 0, 3))
5645 fail = 1;
1da177e4 5646
ad4ebed0 5647 /* Test Write Request at offset 0x7f0 */
5648 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5649 fail = 1;
ad4ebed0 5650 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5651 fail = 1;
5652
ad4ebed0 5653 if (ret_data != 0x012345) {
26b7625c
AM		 5654 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5655 "Data written %llx Data read %llx\n",
5656 dev->name, (unsigned long long)0x12345,
5657 (unsigned long long)ret_data);
1da177e4 5658 fail = 1;
ad4ebed0 5659 }
1da177e4
LT		 5660
5661 /* Reset the EEPROM data go FFFF */
ad4ebed0 5662 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5663
ad4ebed0 5664 if (sp->device_type == XFRAME_I_DEVICE) {
5665 /* Test Write Error at offset 0x80 */
5666 if (!write_eeprom(sp, 0x080, 0, 3))
5667 fail = 1;
1da177e4 5668
ad4ebed0 5669 /* Test Write Error at offset 0xfc */
5670 if (!write_eeprom(sp, 0x0FC, 0, 3))
5671 fail = 1;
1da177e4 5672
ad4ebed0 5673 /* Test Write Error at offset 0x100 */
5674 if (!write_eeprom(sp, 0x100, 0, 3))
5675 fail = 1;
1da177e4 5676
ad4ebed0 5677 /* Test Write Error at offset 4ec */
5678 if (!write_eeprom(sp, 0x4EC, 0, 3))
5679 fail = 1;
5680 }
5681
5682 /* Restore values at offsets 0x4F0 and 0x7F0 */
5683 if (saved_4F0)
5684 write_eeprom(sp, 0x4F0, org_4F0, 3);
5685 if (saved_7F0)
5686 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 5687
5688 *data = fail;
ad4ebed0 5689 return fail;
1da177e4
LT		 5690}
5691
5692/**
5693 * s2io_bist_test - invokes the MemBist test of the card .
20346722 5694 * @sp : private member of the device structure, which is a pointer to the
1da177e4 5695 * s2io_nic structure.
20346722 5696 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 5697 * the driver.
5698 * Description:
5699 * This invokes the MemBist test of the card. We give around
5700 * 2 secs time for the Test to complete. If it's still not complete
20346722 5701 * within this peiod, we consider that the test failed.
1da177e4
LT		 5702 * Return value:
5703 * 0 on success and -1 on failure.
5704 */
5705
1ee6dd77 5706static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5707{
5708 u8 bist = 0;
5709 int cnt = 0, ret = -1;
5710
5711 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5712 bist |= PCI_BIST_START;
5713 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5714
5715 while (cnt < 20) {
5716 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5717 if (!(bist & PCI_BIST_START)) {
5718 *data = (bist & PCI_BIST_CODE_MASK);
5719 ret = 0;
5720 break;
5721 }
5722 msleep(100);
5723 cnt++;
5724 }
5725
5726 return ret;
5727}
5728
5729/**
20346722
K		 5730 * s2io-link_test - verifies the link state of the nic
5731 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 5732 * s2io_nic structure.
5733 * @data: variable that returns the result of each of the test conducted by
5734 * the driver.
5735 * Description:
20346722 5736 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 5737 * argument 'data' appropriately.
5738 * Return value:
5739 * 0 on success.
5740 */
5741
1ee6dd77 5742static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5743{
1ee6dd77 5744 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5745 u64 val64;
5746
5747 val64 = readq(&bar0->adapter_status);
c92ca04b 5748 if(!(LINK_IS_UP(val64)))
1da177e4 5749 *data = 1;
c92ca04b
AR		 5750 else
5751 *data = 0;
1da177e4 5752
b41477f3 5753 return *data;
1da177e4
LT		 5754}
5755
5756/**
20346722
K		 5757 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5758 * @sp - private member of the device structure, which is a pointer to the
1da177e4 5759 * s2io_nic structure.
20346722 5760 * @data - variable that returns the result of each of the test
1da177e4
LT		 5761 * conducted by the driver.
5762 * Description:
20346722 5763 * This is one of the offline test that tests the read and write
1da177e4
LT		 5764 * access to the RldRam chip on the NIC.
5765 * Return value:
5766 * 0 on success.
5767 */
5768
1ee6dd77 5769static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5770{
1ee6dd77 5771 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5772 u64 val64;
ad4ebed0 5773 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 5774
5775 val64 = readq(&bar0->adapter_control);
5776 val64 &= ~ADAPTER_ECC_EN;
5777 writeq(val64, &bar0->adapter_control);
5778
5779 val64 = readq(&bar0->mc_rldram_test_ctrl);
5780 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 5781 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5782
5783 val64 = readq(&bar0->mc_rldram_mrs);
5784 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5785 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5786
5787 val64 |= MC_RLDRAM_MRS_ENABLE;
5788 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5789
5790 while (iteration < 2) {
5791 val64 = 0x55555555aaaa0000ULL;
5792 if (iteration == 1) {
5793 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5794 }
5795 writeq(val64, &bar0->mc_rldram_test_d0);
5796
5797 val64 = 0xaaaa5a5555550000ULL;
5798 if (iteration == 1) {
5799 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5800 }
5801 writeq(val64, &bar0->mc_rldram_test_d1);
5802
5803 val64 = 0x55aaaaaaaa5a0000ULL;
5804 if (iteration == 1) {
5805 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5806 }
5807 writeq(val64, &bar0->mc_rldram_test_d2);
5808
ad4ebed0 5809 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 5810 writeq(val64, &bar0->mc_rldram_test_add);
5811
ad4ebed0 5812 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5813 MC_RLDRAM_TEST_GO;
5814 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5815
5816 for (cnt = 0; cnt < 5; cnt++) {
5817 val64 = readq(&bar0->mc_rldram_test_ctrl);
5818 if (val64 & MC_RLDRAM_TEST_DONE)
5819 break;
5820 msleep(200);
5821 }
5822
5823 if (cnt == 5)
5824 break;
5825
ad4ebed0 5826 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5827 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5828
5829 for (cnt = 0; cnt < 5; cnt++) {
5830 val64 = readq(&bar0->mc_rldram_test_ctrl);
5831 if (val64 & MC_RLDRAM_TEST_DONE)
5832 break;
5833 msleep(500);
5834 }
5835
5836 if (cnt == 5)
5837 break;
5838
5839 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 5840 if (!(val64 & MC_RLDRAM_TEST_PASS))
5841 test_fail = 1;
1da177e4
LT		 5842
5843 iteration++;
5844 }
5845
ad4ebed0 5846 *data = test_fail;
1da177e4 5847
ad4ebed0 5848 /* Bring the adapter out of test mode */
5849 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5850
5851 return test_fail;
1da177e4
LT		 5852}
5853
5854/**
5855 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5856 * @sp : private member of the device structure, which is a pointer to the
5857 * s2io_nic structure.
5858 * @ethtest : pointer to a ethtool command specific structure that will be
5859 * returned to the user.
20346722 5860 * @data : variable that returns the result of each of the test
1da177e4
LT		 5861 * conducted by the driver.
5862 * Description:
5863 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5864 * the health of the card.
5865 * Return value:
5866 * void
5867 */
5868
5869static void s2io_ethtool_test(struct net_device *dev,
5870 struct ethtool_test *ethtest,
5871 uint64_t * data)
5872{
1ee6dd77 5873 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5874 int orig_state = netif_running(sp->dev);
5875
5876 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5877 /* Offline Tests. */
20346722 5878 if (orig_state)
1da177e4 5879 s2io_close(sp->dev);
1da177e4
LT		 5880
5881 if (s2io_register_test(sp, &data[0]))
5882 ethtest->flags |= ETH_TEST_FL_FAILED;
5883
5884 s2io_reset(sp);
1da177e4
LT		 5885
5886 if (s2io_rldram_test(sp, &data[3]))
5887 ethtest->flags |= ETH_TEST_FL_FAILED;
5888
5889 s2io_reset(sp);
1da177e4
LT		 5890
5891 if (s2io_eeprom_test(sp, &data[1]))
5892 ethtest->flags |= ETH_TEST_FL_FAILED;
5893
5894 if (s2io_bist_test(sp, &data[4]))
5895 ethtest->flags |= ETH_TEST_FL_FAILED;
5896
5897 if (orig_state)
5898 s2io_open(sp->dev);
5899
5900 data[2] = 0;
5901 } else {
5902 /* Online Tests. */
5903 if (!orig_state) {
5904 DBG_PRINT(ERR_DBG,
5905 "%s: is not up, cannot run test\n",
5906 dev->name);
5907 data[0] = -1;
5908 data[1] = -1;
5909 data[2] = -1;
5910 data[3] = -1;
5911 data[4] = -1;
5912 }
5913
5914 if (s2io_link_test(sp, &data[2]))
5915 ethtest->flags |= ETH_TEST_FL_FAILED;
5916
5917 data[0] = 0;
5918 data[1] = 0;
5919 data[3] = 0;
5920 data[4] = 0;
5921 }
5922}
5923
5924static void s2io_get_ethtool_stats(struct net_device *dev,
5925 struct ethtool_stats *estats,
5926 u64 * tmp_stats)
5927{
8116f3cf 5928 int i = 0, k;
1ee6dd77
RB		 5929 struct s2io_nic *sp = dev->priv;
5930 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 5931
7ba013ac 5932 s2io_updt_stats(sp);
541ae68f
K		 5933 tmp_stats[i++] =
5934 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5935 le32_to_cpu(stat_info->tmac_frms);
5936 tmp_stats[i++] =
5937 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5938 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 5939 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 5940 tmp_stats[i++] =
5941 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5942 le32_to_cpu(stat_info->tmac_mcst_frms);
5943 tmp_stats[i++] =
5944 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5945 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 5946 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 5947 tmp_stats[i++] =
5948 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5949 le32_to_cpu(stat_info->tmac_ttl_octets);
5950 tmp_stats[i++] =
5951 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5952 le32_to_cpu(stat_info->tmac_ucst_frms);
5953 tmp_stats[i++] =
5954 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5955 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 5956 tmp_stats[i++] =
5957 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5958 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 5959 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 5960 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 5961 tmp_stats[i++] =
5962 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5963 le32_to_cpu(stat_info->tmac_vld_ip);
5964 tmp_stats[i++] =
5965 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5966 le32_to_cpu(stat_info->tmac_drop_ip);
5967 tmp_stats[i++] =
5968 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5969 le32_to_cpu(stat_info->tmac_icmp);
5970 tmp_stats[i++] =
5971 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5972 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 5973 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 5974 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5975 le32_to_cpu(stat_info->tmac_udp);
5976 tmp_stats[i++] =
5977 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5978 le32_to_cpu(stat_info->rmac_vld_frms);
5979 tmp_stats[i++] =
5980 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5981 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 5982 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5983 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 5984 tmp_stats[i++] =
5985 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5986 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5987 tmp_stats[i++] =
5988 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5989 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 5990 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 5991 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 5992 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5993 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 5994 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5995 tmp_stats[i++] =
5996 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5997 le32_to_cpu(stat_info->rmac_ttl_octets);
5998 tmp_stats[i++] =
5999 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6000 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6001 tmp_stats[i++] =
6002 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6003 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 6004 tmp_stats[i++] =
6005 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6006 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 6007 tmp_stats[i++] =
6008 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6009 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6010 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6011 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 6012 tmp_stats[i++] =
6013 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6014 le32_to_cpu(stat_info->rmac_usized_frms);
6015 tmp_stats[i++] =
6016 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6017 le32_to_cpu(stat_info->rmac_osized_frms);
6018 tmp_stats[i++] =
6019 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6020 le32_to_cpu(stat_info->rmac_frag_frms);
6021 tmp_stats[i++] =
6022 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6023 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 6024 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6025 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6026 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6027 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6028 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6029 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6030 tmp_stats[i++] =
6031 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 6032 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 6033 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6034 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 6035 tmp_stats[i++] =
6036 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 6037 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 6038 tmp_stats[i++] =
6039 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 6040 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 6041 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 6042 tmp_stats[i++] =
6043 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 6044 le32_to_cpu(stat_info->rmac_udp);
6045 tmp_stats[i++] =
6046 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6047 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 6048 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6049 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6050 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6051 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6052 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6053 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6054 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6055 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6056 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6057 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6058 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6059 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6060 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6061 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6062 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6063 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6064 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 6065 tmp_stats[i++] =
6066 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6067 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 6068 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6069 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 6070 tmp_stats[i++] =
6071 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6072 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 6073 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 6074 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6075 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6076 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6077 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6078 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6079 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6080 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6081 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6082 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6083 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6084 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6085 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6086 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6087 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6088 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6089 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6090 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6091 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 6092
6093 /* Enhanced statistics exist only for Hercules */
6094 if(sp->device_type == XFRAME_II_DEVICE) {
6095 tmp_stats[i++] =
6096 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6097 tmp_stats[i++] =
6098 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6099 tmp_stats[i++] =
6100 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6101 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6102 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6103 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6104 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6105 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6106 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6107 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6108 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6109 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6110 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6111 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6112 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6113 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6114 }
6115
7ba013ac
K		 6116 tmp_stats[i++] = 0;
6117 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6118 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 6119 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6120 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6121 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6122 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
8116f3cf
SS		 6123 for (k = 0; k < MAX_RX_RINGS; k++)
6124 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
bd1034f0
AR		 6125 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6126 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6127 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6128 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6129 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6130 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6131 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6132 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6133 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6134 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6135 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6136 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 6137 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6138 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6139 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6140 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 6141 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 6142 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6143 int count = 0;
6aa20a22 6144 /*
bd1034f0
AR		 6145 * Since 64-bit divide does not work on all platforms,
6146 * do repeated subtraction.
6147 */
6148 while (tmp >= stat_info->sw_stat.num_aggregations) {
6149 tmp -= stat_info->sw_stat.num_aggregations;
6150 count++;
6151 }
6152 tmp_stats[i++] = count;
fe931395 6153 }
bd1034f0
AR		 6154 else
6155 tmp_stats[i++] = 0;
c53d4945 6156 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 6157 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 6158 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 6159 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6160 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6161 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6162 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6163 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6164 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6165
6166 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6167 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6168 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6169 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6170 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6171
6172 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6173 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6174 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6175 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6176 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6177 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6178 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6179 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6180 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
8116f3cf
SS		 6181 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6182 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6183 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6184 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6185 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6186 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6187 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6188 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6189 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6190 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6191 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6192 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6193 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6194 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6195 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6196 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6197 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
1da177e4
LT		 6198}
6199
ac1f60db 6200static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 6201{
6202 return (XENA_REG_SPACE);
6203}
6204
6205
ac1f60db 6206static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 6207{
1ee6dd77 6208 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6209
6210 return (sp->rx_csum);
6211}
ac1f60db
AB		 6212
6213static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6214{
1ee6dd77 6215 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6216
6217 if (data)
6218 sp->rx_csum = 1;
6219 else
6220 sp->rx_csum = 0;
6221
6222 return 0;
6223}
ac1f60db
AB		 6224
6225static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 6226{
6227 return (XENA_EEPROM_SPACE);
6228}
6229
b9f2c044 6230static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6231{
b9f2c044
JG		 6232 struct s2io_nic *sp = dev->priv;
6233
6234 switch (sset) {
6235 case ETH_SS_TEST:
6236 return S2IO_TEST_LEN;
6237 case ETH_SS_STATS:
6238 switch(sp->device_type) {
6239 case XFRAME_I_DEVICE:
6240 return XFRAME_I_STAT_LEN;
6241 case XFRAME_II_DEVICE:
6242 return XFRAME_II_STAT_LEN;
6243 default:
6244 return 0;
6245 }
6246 default:
6247 return -EOPNOTSUPP;
6248 }
1da177e4 6249}
ac1f60db
AB		 6250
6251static void s2io_ethtool_get_strings(struct net_device *dev,
6252 u32 stringset, u8 * data)
1da177e4 6253{
fa1f0cb3
SS		 6254 int stat_size = 0;
6255 struct s2io_nic *sp = dev->priv;
6256
1da177e4
LT		 6257 switch (stringset) {
6258 case ETH_SS_TEST:
6259 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6260 break;
6261 case ETH_SS_STATS:
fa1f0cb3
SS		 6262 stat_size = sizeof(ethtool_xena_stats_keys);
6263 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6264 if(sp->device_type == XFRAME_II_DEVICE) {
6265 memcpy(data + stat_size,
6266 &ethtool_enhanced_stats_keys,
6267 sizeof(ethtool_enhanced_stats_keys));
6268 stat_size += sizeof(ethtool_enhanced_stats_keys);
6269 }
6270
6271 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6272 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6273 }
6274}
1da177e4 6275
ac1f60db 6276static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6277{
6278 if (data)
6279 dev->features |= NETIF_F_IP_CSUM;
6280 else
6281 dev->features &= ~NETIF_F_IP_CSUM;
6282
6283 return 0;
6284}
6285
75c30b13
AR		 6286static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6287{
6288 return (dev->features & NETIF_F_TSO) != 0;
6289}
6290static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6291{
6292 if (data)
6293 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6294 else
6295 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6296
6297 return 0;
6298}
1da177e4 6299
7282d491 6300static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6301 .get_settings = s2io_ethtool_gset,
6302 .set_settings = s2io_ethtool_sset,
6303 .get_drvinfo = s2io_ethtool_gdrvinfo,
6304 .get_regs_len = s2io_ethtool_get_regs_len,
6305 .get_regs = s2io_ethtool_gregs,
6306 .get_link = ethtool_op_get_link,
6307 .get_eeprom_len = s2io_get_eeprom_len,
6308 .get_eeprom = s2io_ethtool_geeprom,
6309 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6310 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6311 .get_pauseparam = s2io_ethtool_getpause_data,
6312 .set_pauseparam = s2io_ethtool_setpause_data,
6313 .get_rx_csum = s2io_ethtool_get_rx_csum,
6314 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6315 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6316 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6317 .get_tso = s2io_ethtool_op_get_tso,
6318 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6319 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6320 .self_test = s2io_ethtool_test,
6321 .get_strings = s2io_ethtool_get_strings,
6322 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6323 .get_ethtool_stats = s2io_get_ethtool_stats,
6324 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6325};
6326
6327/**
20346722 6328 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6329 * @dev : Device pointer.
6330 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6331 * a proprietary structure used to pass information to the driver.
6332 * @cmd : This is used to distinguish between the different commands that
6333 * can be passed to the IOCTL functions.
6334 * Description:
20346722
K		 6335 * Currently there are no special functionality supported in IOCTL, hence
6336 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6337 */
6338
ac1f60db 6339static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6340{
6341 return -EOPNOTSUPP;
6342}
6343
6344/**
6345 * s2io_change_mtu - entry point to change MTU size for the device.
6346 * @dev : device pointer.
6347 * @new_mtu : the new MTU size for the device.
6348 * Description: A driver entry point to change MTU size for the device.
6349 * Before changing the MTU the device must be stopped.
6350 * Return value:
6351 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6352 * file on failure.
6353 */
6354
ac1f60db 6355static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6356{
1ee6dd77 6357 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6358
6359 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6360 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6361 dev->name);
6362 return -EPERM;
6363 }
6364
1da177e4 6365 dev->mtu = new_mtu;
d8892c6e 6366 if (netif_running(dev)) {
e6a8fee2 6367 s2io_card_down(sp);
d8892c6e
K		 6368 netif_stop_queue(dev);
6369 if (s2io_card_up(sp)) {
6370 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6371 __FUNCTION__);
6372 }
6373 if (netif_queue_stopped(dev))
6374 netif_wake_queue(dev);
6375 } else { /* Device is down */
1ee6dd77 6376 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6377 u64 val64 = new_mtu;
6378
6379 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6380 }
1da177e4
LT		 6381
6382 return 0;
6383}
6384
6385/**
6386 * s2io_tasklet - Bottom half of the ISR.
6387 * @dev_adr : address of the device structure in dma_addr_t format.
6388 * Description:
6389 * This is the tasklet or the bottom half of the ISR. This is
20346722 6390 * an extension of the ISR which is scheduled by the scheduler to be run
1da177e4 6391 * when the load on the CPU is low. All low priority tasks of the ISR can
20346722 6392 * be pushed into the tasklet. For now the tasklet is used only to
1da177e4
LT		 6393 * replenish the Rx buffers in the Rx buffer descriptors.
6394 * Return value:
6395 * void.
6396 */
6397
6398static void s2io_tasklet(unsigned long dev_addr)
6399{
6400 struct net_device *dev = (struct net_device *) dev_addr;
1ee6dd77 6401 struct s2io_nic *sp = dev->priv;
1da177e4 6402 int i, ret;
1ee6dd77 6403 struct mac_info *mac_control;
1da177e4
LT		 6404 struct config_param *config;
6405
6406 mac_control = &sp->mac_control;
6407 config = &sp->config;
6408
6409 if (!TASKLET_IN_USE) {
6410 for (i = 0; i < config->rx_ring_num; i++) {
6411 ret = fill_rx_buffers(sp, i);
6412 if (ret == -ENOMEM) {
0c61ed5f 6413 DBG_PRINT(INFO_DBG, "%s: Out of ",
1da177e4 6414 dev->name);
491976b2 6415 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
1da177e4
LT		 6416 break;
6417 } else if (ret == -EFILL) {
0c61ed5f 6418 DBG_PRINT(INFO_DBG,
1da177e4
LT		 6419 "%s: Rx Ring %d is full\n",
6420 dev->name, i);
6421 break;
6422 }
6423 }
6424 clear_bit(0, (&sp->tasklet_status));
6425 }
6426}
6427
6428/**
6429 * s2io_set_link - Set the LInk status
6430 * @data: long pointer to device private structue
6431 * Description: Sets the link status for the adapter
6432 */
6433
c4028958 6434static void s2io_set_link(struct work_struct *work)
1da177e4 6435{
1ee6dd77 6436 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6437 struct net_device *dev = nic->dev;
1ee6dd77 6438 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6439 register u64 val64;
6440 u16 subid;
6441
22747d6b
FR		 6442 rtnl_lock();
6443
6444 if (!netif_running(dev))
6445 goto out_unlock;
6446
92b84437 6447 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6448 /* The card is being reset, no point doing anything */
22747d6b 6449 goto out_unlock;
1da177e4
LT		 6450 }
6451
6452 subid = nic->pdev->subsystem_device;
a371a07d
K		 6453 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6454 /*
6455 * Allow a small delay for the NICs self initiated
6456 * cleanup to complete.
6457 */
6458 msleep(100);
6459 }
1da177e4
LT		 6460
6461 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6462 if (LINK_IS_UP(val64)) {
6463 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6464 if (verify_xena_quiescence(nic)) {
6465 val64 = readq(&bar0->adapter_control);
6466 val64 |= ADAPTER_CNTL_EN;
1da177e4 6467 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6468 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6469 nic->device_type, subid)) {
6470 val64 = readq(&bar0->gpio_control);
6471 val64 |= GPIO_CTRL_GPIO_0;
6472 writeq(val64, &bar0->gpio_control);
6473 val64 = readq(&bar0->gpio_control);
6474 } else {
6475 val64 |= ADAPTER_LED_ON;
6476 writeq(val64, &bar0->adapter_control);
a371a07d 6477 }
1da177e4 6478 nic->device_enabled_once = TRUE;
19a60522
SS		 6479 } else {
6480 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6481 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6482 netif_stop_queue(dev);
1da177e4 6483 }
19a60522 6484 }
92c48799
SS		 6485 val64 = readq(&bar0->adapter_control);
6486 val64 |= ADAPTER_LED_ON;
6487 writeq(val64, &bar0->adapter_control);
6488 s2io_link(nic, LINK_UP);
19a60522
SS		 6489 } else {
6490 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6491 subid)) {
6492 val64 = readq(&bar0->gpio_control);
6493 val64 &= ~GPIO_CTRL_GPIO_0;
6494 writeq(val64, &bar0->gpio_control);
6495 val64 = readq(&bar0->gpio_control);
1da177e4 6496 }
92c48799
SS		 6497 /* turn off LED */
6498 val64 = readq(&bar0->adapter_control);
6499 val64 = val64 &(~ADAPTER_LED_ON);
6500 writeq(val64, &bar0->adapter_control);
19a60522 6501 s2io_link(nic, LINK_DOWN);
1da177e4 6502 }
92b84437 6503 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6504
6505out_unlock:
d8d70caf 6506 rtnl_unlock();
1da177e4
LT		 6507}
6508
1ee6dd77
RB		 6509static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6510 struct buffAdd *ba,
6511 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6512 u64 *temp2, int size)
5d3213cc
AR		 6513{
6514 struct net_device *dev = sp->dev;
491abf25 6515 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6516
6517 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6518 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6519 /* allocate skb */
6520 if (*skb) {
6521 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6522 /*
6523 * As Rx frame are not going to be processed,
6524 * using same mapped address for the Rxd
6525 * buffer pointer
6526 */
6d517a27 6527 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6528 } else {
6529 *skb = dev_alloc_skb(size);
6530 if (!(*skb)) {
0c61ed5f 6531 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6532 DBG_PRINT(INFO_DBG, "memory to allocate ");
6533 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6534 sp->mac_control.stats_info->sw_stat. \
6535 mem_alloc_fail_cnt++;
5d3213cc
AR		 6536 return -ENOMEM ;
6537 }
8a4bdbaa 6538 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6539 += (*skb)->truesize;
5d3213cc
AR		 6540 /* storing the mapped addr in a temp variable
6541 * such it will be used for next rxd whose
6542 * Host Control is NULL
6543 */
6d517a27 6544 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6545 pci_map_single( sp->pdev, (*skb)->data,
6546 size - NET_IP_ALIGN,
6547 PCI_DMA_FROMDEVICE);
491abf25
VP		 6548 if( (rxdp1->Buffer0_ptr == 0) ||
6549 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6550 goto memalloc_failed;
6551 }
5d3213cc
AR		 6552 rxdp->Host_Control = (unsigned long) (*skb);
6553 }
6554 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6555 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6556 /* Two buffer Mode */
6557 if (*skb) {
6d517a27
VP		 6558 rxdp3->Buffer2_ptr = *temp2;
6559 rxdp3->Buffer0_ptr = *temp0;
6560 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6561 } else {
6562 *skb = dev_alloc_skb(size);
2ceaac75 6563 if (!(*skb)) {
c53d4945
SH		 6564 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6565 DBG_PRINT(INFO_DBG, "memory to allocate ");
6566 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6567 sp->mac_control.stats_info->sw_stat. \
6568 mem_alloc_fail_cnt++;
2ceaac75
DR		 6569 return -ENOMEM;
6570 }
8a4bdbaa 6571 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6572 += (*skb)->truesize;
6d517a27 6573 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6574 pci_map_single(sp->pdev, (*skb)->data,
6575 dev->mtu + 4,
6576 PCI_DMA_FROMDEVICE);
491abf25
VP		 6577 if( (rxdp3->Buffer2_ptr == 0) ||
6578 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6579 goto memalloc_failed;
6580 }
6d517a27 6581 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6582 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6583 PCI_DMA_FROMDEVICE);
491abf25
VP		 6584 if( (rxdp3->Buffer0_ptr == 0) ||
6585 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6586 pci_unmap_single (sp->pdev,
3e847423 6587 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6588 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6589 goto memalloc_failed;
6590 }
5d3213cc
AR		 6591 rxdp->Host_Control = (unsigned long) (*skb);
6592
6593 /* Buffer-1 will be dummy buffer not used */
6d517a27 6594 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6595 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6596 PCI_DMA_FROMDEVICE);
491abf25
VP		 6597 if( (rxdp3->Buffer1_ptr == 0) ||
6598 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6599 pci_unmap_single (sp->pdev,
3e847423
AV		 6600 (dma_addr_t)rxdp3->Buffer0_ptr,
6601 BUF0_LEN, PCI_DMA_FROMDEVICE);
6602 pci_unmap_single (sp->pdev,
6603 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6604 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6605 goto memalloc_failed;
6606 }
5d3213cc
AR		 6607 }
6608 }
6609 return 0;
491abf25
VP		 6610 memalloc_failed:
6611 stats->pci_map_fail_cnt++;
6612 stats->mem_freed += (*skb)->truesize;
6613 dev_kfree_skb(*skb);
6614 return -ENOMEM;
5d3213cc 6615}
491abf25 6616
1ee6dd77
RB		 6617static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6618 int size)
5d3213cc
AR		 6619{
6620 struct net_device *dev = sp->dev;
6621 if (sp->rxd_mode == RXD_MODE_1) {
6622 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6623 } else if (sp->rxd_mode == RXD_MODE_3B) {
6624 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6625 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6626 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 6627 }
6628}
6629
1ee6dd77 6630static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6631{
6632 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6633 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6634 struct config_param *config = &sp->config;
6635 struct net_device *dev = sp->dev;
1ee6dd77 6636 struct RxD_t *rxdp = NULL;
5d3213cc 6637 struct sk_buff *skb = NULL;
1ee6dd77 6638 struct buffAdd *ba = NULL;
5d3213cc
AR		 6639 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6640
6641 /* Calculate the size based on ring mode */
6642 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6643 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6644 if (sp->rxd_mode == RXD_MODE_1)
6645 size += NET_IP_ALIGN;
6646 else if (sp->rxd_mode == RXD_MODE_3B)
6647 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6648
6649 for (i = 0; i < config->rx_ring_num; i++) {
6650 blk_cnt = config->rx_cfg[i].num_rxd /
6651 (rxd_count[sp->rxd_mode] +1);
6652
6653 for (j = 0; j < blk_cnt; j++) {
6654 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6655 rxdp = mac_control->rings[i].
6656 rx_blocks[j].rxds[k].virt_addr;
6d517a27 6657 if(sp->rxd_mode == RXD_MODE_3B)
5d3213cc 6658 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 6659 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 6660 &skb,(u64 *)&temp0_64,
6661 (u64 *)&temp1_64,
ac1f90d6
SS		 6662 (u64 *)&temp2_64,
6663 size) == ENOMEM) {
6664 return 0;
6665 }
5d3213cc
AR		 6666
6667 set_rxd_buffer_size(sp, rxdp, size);
6668 wmb();
6669 /* flip the Ownership bit to Hardware */
6670 rxdp->Control_1 |= RXD_OWN_XENA;
6671 }
6672 }
6673 }
6674 return 0;
6675
6676}
6677
1ee6dd77 6678static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 6679{
e6a8fee2 6680 int ret = 0;
c92ca04b 6681 struct net_device *dev = sp->dev;
e6a8fee2 6682 int err = 0;
1da177e4 6683
eaae7f72 6684 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 6685 ret = s2io_enable_msi_x(sp);
6686 if (ret) {
6687 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 6688 sp->config.intr_type = INTA;
20346722 6689 }
1da177e4 6690
1ee6dd77 6691 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 6692 store_xmsi_data(sp);
c92ca04b 6693
e6a8fee2 6694 /* After proper initialization of H/W, register ISR */
eaae7f72 6695 if (sp->config.intr_type == MSI_X) {
fb6a825b 6696 int i, msix_tx_cnt=0,msix_rx_cnt=0;
c92ca04b 6697
e6a8fee2
AR		 6698 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6699 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6700 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6701 dev->name, i);
6702 err = request_irq(sp->entries[i].vector,
6703 s2io_msix_fifo_handle, 0, sp->desc[i],
6704 sp->s2io_entries[i].arg);
fb6a825b
SS		 6705 /* If either data or addr is zero print it */
6706 if(!(sp->msix_info[i].addr &&
6707 sp->msix_info[i].data)) {
6708 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6709 "Data:0x%lx\n",sp->desc[i],
6710 (unsigned long long)
6711 sp->msix_info[i].addr,
6712 (unsigned long)
6713 ntohl(sp->msix_info[i].data));
6714 } else {
6715 msix_tx_cnt++;
6716 }
e6a8fee2
AR		 6717 } else {
6718 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6719 dev->name, i);
6720 err = request_irq(sp->entries[i].vector,
6721 s2io_msix_ring_handle, 0, sp->desc[i],
6722 sp->s2io_entries[i].arg);
fb6a825b
SS		 6723 /* If either data or addr is zero print it */
6724 if(!(sp->msix_info[i].addr &&
6725 sp->msix_info[i].data)) {
6726 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6727 "Data:0x%lx\n",sp->desc[i],
6728 (unsigned long long)
6729 sp->msix_info[i].addr,
6730 (unsigned long)
6731 ntohl(sp->msix_info[i].data));
6732 } else {
6733 msix_rx_cnt++;
6734 }
c92ca04b 6735 }
e6a8fee2 6736 if (err) {
18b2b7bd 6737 remove_msix_isr(sp);
e6a8fee2
AR		 6738 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6739 "failed\n", dev->name, i);
18b2b7bd
SH		 6740 DBG_PRINT(ERR_DBG, "%s: defaulting to INTA\n",
6741 dev->name);
6742 sp->config.intr_type = INTA;
6743 break;
e6a8fee2
AR		 6744 }
6745 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6746 }
18b2b7bd
SH		 6747 if (!err) {
6748 printk(KERN_INFO "MSI-X-TX %d entries enabled\n",
6749 msix_tx_cnt);
6750 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
6751 msix_rx_cnt);
6752 }
e6a8fee2 6753 }
eaae7f72 6754 if (sp->config.intr_type == INTA) {
e6a8fee2
AR		 6755 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6756 sp->name, dev);
6757 if (err) {
6758 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6759 dev->name);
6760 return -1;
6761 }
6762 }
6763 return 0;
6764}
1ee6dd77 6765static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2 6766{
18b2b7bd
SH		 6767 if (sp->config.intr_type == MSI_X)
6768 remove_msix_isr(sp);
6769 else
6770 remove_inta_isr(sp);
e6a8fee2
AR		 6771}
6772
d796fdb7 6773static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 6774{
6775 int cnt = 0;
1ee6dd77 6776 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2
AR		 6777 unsigned long flags;
6778 register u64 val64 = 0;
6779
6780 del_timer_sync(&sp->alarm_timer);
6781 /* If s2io_set_link task is executing, wait till it completes. */
92b84437 6782 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
e6a8fee2
AR		 6783 msleep(50);
6784 }
92b84437 6785 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2
AR		 6786
6787 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 6788 if (do_io)
6789 stop_nic(sp);
e6a8fee2
AR		 6790
6791 s2io_rem_isr(sp);
1da177e4
LT		 6792
6793 /* Kill tasklet. */
6794 tasklet_kill(&sp->task);
6795
6796 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 6797 while(do_io) {
5d3213cc
AR		 6798 /* As per the HW requirement we need to replenish the
6799 * receive buffer to avoid the ring bump. Since there is
6800 * no intention of processing the Rx frame at this pointwe are
6801 * just settting the ownership bit of rxd in Each Rx
6802 * ring to HW and set the appropriate buffer size
6803 * based on the ring mode
6804 */
6805 rxd_owner_bit_reset(sp);
6806
1da177e4 6807 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6808 if (verify_xena_quiescence(sp)) {
6809 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 6810 break;
6811 }
6812
6813 msleep(50);
6814 cnt++;
6815 if (cnt == 10) {
6816 DBG_PRINT(ERR_DBG,
6817 "s2io_close:Device not Quiescent ");
6818 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6819 (unsigned long long) val64);
6820 break;
6821 }
d796fdb7
LV		 6822 }
6823 if (do_io)
6824 s2io_reset(sp);
1da177e4 6825
7ba013ac
K		 6826 spin_lock_irqsave(&sp->tx_lock, flags);
6827 /* Free all Tx buffers */
1da177e4 6828 free_tx_buffers(sp);
7ba013ac
K		 6829 spin_unlock_irqrestore(&sp->tx_lock, flags);
6830
6831 /* Free all Rx buffers */
6832 spin_lock_irqsave(&sp->rx_lock, flags);
1da177e4 6833 free_rx_buffers(sp);
7ba013ac 6834 spin_unlock_irqrestore(&sp->rx_lock, flags);
1da177e4 6835
92b84437 6836 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 6837}
6838
d796fdb7
LV		 6839static void s2io_card_down(struct s2io_nic * sp)
6840{
6841 do_s2io_card_down(sp, 1);
6842}
6843
1ee6dd77 6844static int s2io_card_up(struct s2io_nic * sp)
1da177e4 6845{
cc6e7c44 6846 int i, ret = 0;
1ee6dd77 6847 struct mac_info *mac_control;
1da177e4
LT		 6848 struct config_param *config;
6849 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 6850 u16 interruptible;
1da177e4
LT		 6851
6852 /* Initialize the H/W I/O registers */
6853 if (init_nic(sp) != 0) {
6854 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6855 dev->name);
e6a8fee2 6856 s2io_reset(sp);
1da177e4
LT		 6857 return -ENODEV;
6858 }
6859
20346722
K		 6860 /*
6861 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 6862 * Rx ring and initializing buffers into 30 Rx blocks
6863 */
6864 mac_control = &sp->mac_control;
6865 config = &sp->config;
6866
6867 for (i = 0; i < config->rx_ring_num; i++) {
6868 if ((ret = fill_rx_buffers(sp, i))) {
6869 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6870 dev->name);
6871 s2io_reset(sp);
6872 free_rx_buffers(sp);
6873 return -ENOMEM;
6874 }
6875 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6876 atomic_read(&sp->rx_bufs_left[i]));
6877 }
19a60522
SS		 6878 /* Maintain the state prior to the open */
6879 if (sp->promisc_flg)
6880 sp->promisc_flg = 0;
6881 if (sp->m_cast_flg) {
6882 sp->m_cast_flg = 0;
6883 sp->all_multi_pos= 0;
6884 }
1da177e4
LT		 6885
6886 /* Setting its receive mode */
6887 s2io_set_multicast(dev);
6888
7d3d0439 6889 if (sp->lro) {
b41477f3 6890 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 6891 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6892 /* Check if we can use(if specified) user provided value */
6893 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6894 sp->lro_max_aggr_per_sess = lro_max_pkts;
6895 }
6896
1da177e4
LT		 6897 /* Enable Rx Traffic and interrupts on the NIC */
6898 if (start_nic(sp)) {
6899 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 6900 s2io_reset(sp);
e6a8fee2
AR		 6901 free_rx_buffers(sp);
6902 return -ENODEV;
6903 }
6904
6905 /* Add interrupt service routine */
6906 if (s2io_add_isr(sp) != 0) {
eaae7f72 6907 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 6908 s2io_rem_isr(sp);
6909 s2io_reset(sp);
1da177e4
LT		 6910 free_rx_buffers(sp);
6911 return -ENODEV;
6912 }
6913
25fff88e
K		 6914 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6915
e6a8fee2
AR		 6916 /* Enable tasklet for the device */
6917 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6918
6919 /* Enable select interrupts */
9caab458 6920 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
eaae7f72 6921 if (sp->config.intr_type != INTA)
e6a8fee2
AR		 6922 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6923 else {
6924 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 6925 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 6926 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6927 }
6928
92b84437 6929 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
1da177e4
LT		 6930 return 0;
6931}
6932
20346722 6933/**
1da177e4
LT		 6934 * s2io_restart_nic - Resets the NIC.
6935 * @data : long pointer to the device private structure
6936 * Description:
6937 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 6938 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 6939 * the run time of the watch dog routine which is run holding a
6940 * spin lock.
6941 */
6942
c4028958 6943static void s2io_restart_nic(struct work_struct *work)
1da177e4 6944{
1ee6dd77 6945 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 6946 struct net_device *dev = sp->dev;
1da177e4 6947
22747d6b
FR		 6948 rtnl_lock();
6949
6950 if (!netif_running(dev))
6951 goto out_unlock;
6952
e6a8fee2 6953 s2io_card_down(sp);
1da177e4
LT		 6954 if (s2io_card_up(sp)) {
6955 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6956 dev->name);
6957 }
6958 netif_wake_queue(dev);
6959 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6960 dev->name);
22747d6b
FR		 6961out_unlock:
6962 rtnl_unlock();
1da177e4
LT		 6963}
6964
20346722
K		 6965/**
6966 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 6967 * @dev : Pointer to net device structure
6968 * Description:
6969 * This function is triggered if the Tx Queue is stopped
6970 * for a pre-defined amount of time when the Interface is still up.
6971 * If the Interface is jammed in such a situation, the hardware is
6972 * reset (by s2io_close) and restarted again (by s2io_open) to
6973 * overcome any problem that might have been caused in the hardware.
6974 * Return value:
6975 * void
6976 */
6977
6978static void s2io_tx_watchdog(struct net_device *dev)
6979{
1ee6dd77 6980 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6981
6982 if (netif_carrier_ok(dev)) {
c53d4945 6983 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 6984 schedule_work(&sp->rst_timer_task);
bd1034f0 6985 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 6986 }
6987}
6988
6989/**
6990 * rx_osm_handler - To perform some OS related operations on SKB.
6991 * @sp: private member of the device structure,pointer to s2io_nic structure.
6992 * @skb : the socket buffer pointer.
6993 * @len : length of the packet
6994 * @cksum : FCS checksum of the frame.
6995 * @ring_no : the ring from which this RxD was extracted.
20346722 6996 * Description:
b41477f3 6997 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 6998 * some OS related operations on the SKB before passing it to the upper
6999 * layers. It mainly checks if the checksum is OK, if so adds it to the
7000 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7001 * to the upper layer. If the checksum is wrong, it increments the Rx
7002 * packet error count, frees the SKB and returns error.
7003 * Return value:
7004 * SUCCESS on success and -1 on failure.
7005 */
1ee6dd77 7006static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7007{
1ee6dd77 7008 struct s2io_nic *sp = ring_data->nic;
1da177e4 7009 struct net_device *dev = (struct net_device *) sp->dev;
20346722
K		 7010 struct sk_buff *skb = (struct sk_buff *)
7011 ((unsigned long) rxdp->Host_Control);
7012 int ring_no = ring_data->ring_no;
1da177e4 7013 u16 l3_csum, l4_csum;
863c11a9 7014 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 7015 struct lro *lro;
f9046eb3 7016 u8 err_mask;
da6971d8 7017
20346722 7018 skb->dev = dev;
c92ca04b 7019
863c11a9 7020 if (err) {
bd1034f0
AR		 7021 /* Check for parity error */
7022 if (err & 0x1) {
7023 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7024 }
f9046eb3
OH		 7025 err_mask = err >> 48;
7026 switch(err_mask) {
491976b2
SH		 7027 case 1:
7028 sp->mac_control.stats_info->sw_stat.
7029 rx_parity_err_cnt++;
7030 break;
7031
7032 case 2:
7033 sp->mac_control.stats_info->sw_stat.
7034 rx_abort_cnt++;
7035 break;
7036
7037 case 3:
7038 sp->mac_control.stats_info->sw_stat.
7039 rx_parity_abort_cnt++;
7040 break;
7041
7042 case 4:
7043 sp->mac_control.stats_info->sw_stat.
7044 rx_rda_fail_cnt++;
7045 break;
7046
7047 case 5:
7048 sp->mac_control.stats_info->sw_stat.
7049 rx_unkn_prot_cnt++;
7050 break;
7051
7052 case 6:
7053 sp->mac_control.stats_info->sw_stat.
7054 rx_fcs_err_cnt++;
7055 break;
bd1034f0 7056
491976b2
SH		 7057 case 7:
7058 sp->mac_control.stats_info->sw_stat.
7059 rx_buf_size_err_cnt++;
7060 break;
7061
7062 case 8:
7063 sp->mac_control.stats_info->sw_stat.
7064 rx_rxd_corrupt_cnt++;
7065 break;
7066
7067 case 15:
7068 sp->mac_control.stats_info->sw_stat.
7069 rx_unkn_err_cnt++;
7070 break;
7071 }
863c11a9
AR		 7072 /*
7073 * Drop the packet if bad transfer code. Exception being
7074 * 0x5, which could be due to unsupported IPv6 extension header.
7075 * In this case, we let stack handle the packet.
7076 * Note that in this case, since checksum will be incorrect,
7077 * stack will validate the same.
7078 */
f9046eb3
OH		 7079 if (err_mask != 0x5) {
7080 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7081 dev->name, err_mask);
863c11a9 7082 sp->stats.rx_crc_errors++;
8a4bdbaa 7083 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2 7084 += skb->truesize;
863c11a9
AR		 7085 dev_kfree_skb(skb);
7086 atomic_dec(&sp->rx_bufs_left[ring_no]);
7087 rxdp->Host_Control = 0;
7088 return 0;
7089 }
20346722 7090 }
1da177e4 7091
20346722 7092 /* Updating statistics */
573608e4 7093 sp->stats.rx_packets++;
20346722 7094 rxdp->Host_Control = 0;
da6971d8
AR		 7095 if (sp->rxd_mode == RXD_MODE_1) {
7096 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7097
da6971d8
AR		 7098 sp->stats.rx_bytes += len;
7099 skb_put(skb, len);
7100
6d517a27 7101 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7102 int get_block = ring_data->rx_curr_get_info.block_index;
7103 int get_off = ring_data->rx_curr_get_info.offset;
7104 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7105 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7106 unsigned char *buff = skb_push(skb, buf0_len);
7107
1ee6dd77 7108 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8
AR		 7109 sp->stats.rx_bytes += buf0_len + buf2_len;
7110 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7111 skb_put(skb, buf2_len);
da6971d8 7112 }
20346722 7113
7d3d0439
RA		 7114 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
7115 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 7116 (sp->rx_csum)) {
7117 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7118 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7119 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7120 /*
1da177e4
LT		 7121 * NIC verifies if the Checksum of the received
7122 * frame is Ok or not and accordingly returns
7123 * a flag in the RxD.
7124 */
7125 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 7126 if (sp->lro) {
7127 u32 tcp_len;
7128 u8 *tcp;
7129 int ret = 0;
7130
7131 ret = s2io_club_tcp_session(skb->data, &tcp,
43b7c451
SH		 7132 &tcp_len, &lro,
7133 rxdp, sp);
7d3d0439
RA		 7134 switch (ret) {
7135 case 3: /* Begin anew */
7136 lro->parent = skb;
7137 goto aggregate;
7138 case 1: /* Aggregate */
7139 {
7140 lro_append_pkt(sp, lro,
7141 skb, tcp_len);
7142 goto aggregate;
7143 }
7144 case 4: /* Flush session */
7145 {
7146 lro_append_pkt(sp, lro,
7147 skb, tcp_len);
7148 queue_rx_frame(lro->parent);
7149 clear_lro_session(lro);
7150 sp->mac_control.stats_info->
7151 sw_stat.flush_max_pkts++;
7152 goto aggregate;
7153 }
7154 case 2: /* Flush both */
7155 lro->parent->data_len =
7156 lro->frags_len;
7157 sp->mac_control.stats_info->
7158 sw_stat.sending_both++;
7159 queue_rx_frame(lro->parent);
7160 clear_lro_session(lro);
7161 goto send_up;
7162 case 0: /* sessions exceeded */
c92ca04b
AR		 7163 case -1: /* non-TCP or not
7164 * L2 aggregatable
7165 */
7d3d0439
RA		 7166 case 5: /*
7167 * First pkt in session not
7168 * L3/L4 aggregatable
7169 */
7170 break;
7171 default:
7172 DBG_PRINT(ERR_DBG,
7173 "%s: Samadhana!!\n",
7174 __FUNCTION__);
7175 BUG();
7176 }
7177 }
1da177e4 7178 } else {
20346722
K		 7179 /*
7180 * Packet with erroneous checksum, let the
1da177e4
LT		 7181 * upper layers deal with it.
7182 */
7183 skb->ip_summed = CHECKSUM_NONE;
7184 }
7185 } else {
7186 skb->ip_summed = CHECKSUM_NONE;
7187 }
491976b2 7188 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439
RA		 7189 if (!sp->lro) {
7190 skb->protocol = eth_type_trans(skb, dev);
926930b2
SS		 7191 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
7192 vlan_strip_flag)) {
7d3d0439 7193 /* Queueing the vlan frame to the upper layer */
db874e65
SS		 7194 if (napi)
7195 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
7196 RXD_GET_VLAN_TAG(rxdp->Control_2));
7197 else
7198 vlan_hwaccel_rx(skb, sp->vlgrp,
7199 RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7200 } else {
db874e65
SS		 7201 if (napi)
7202 netif_receive_skb(skb);
7203 else
7204 netif_rx(skb);
7d3d0439 7205 }
7d3d0439
RA		 7206 } else {
7207send_up:
7208 queue_rx_frame(skb);
6aa20a22 7209 }
1da177e4 7210 dev->last_rx = jiffies;
7d3d0439 7211aggregate:
1da177e4 7212 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 7213 return SUCCESS;
7214}
7215
7216/**
7217 * s2io_link - stops/starts the Tx queue.
7218 * @sp : private member of the device structure, which is a pointer to the
7219 * s2io_nic structure.
7220 * @link : inidicates whether link is UP/DOWN.
7221 * Description:
7222 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7223 * status of the NIC is is down or up. This is called by the Alarm
7224 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7225 * Return value:
7226 * void.
7227 */
7228
1ee6dd77 7229static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 7230{
7231 struct net_device *dev = (struct net_device *) sp->dev;
7232
7233 if (link != sp->last_link_state) {
7234 if (link == LINK_DOWN) {
7235 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7236 netif_carrier_off(dev);
491976b2 7237 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
8a4bdbaa 7238 sp->mac_control.stats_info->sw_stat.link_up_time =
491976b2
SH		 7239 jiffies - sp->start_time;
7240 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7241 } else {
7242 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2 7243 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
8a4bdbaa 7244 sp->mac_control.stats_info->sw_stat.link_down_time =
491976b2
SH		 7245 jiffies - sp->start_time;
7246 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4
LT		 7247 netif_carrier_on(dev);
7248 }
7249 }
7250 sp->last_link_state = link;
491976b2 7251 sp->start_time = jiffies;
1da177e4
LT		 7252}
7253
20346722
K		 7254/**
7255 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7256 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7257 * s2io_nic structure.
7258 * Description:
7259 * This function initializes a few of the PCI and PCI-X configuration registers
7260 * with recommended values.
7261 * Return value:
7262 * void
7263 */
7264
1ee6dd77 7265static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 7266{
20346722 7267 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7268
7269 /* Enable Data Parity Error Recovery in PCI-X command register. */
7270 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7271 &(pcix_cmd));
1da177e4 7272 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7273 (pcix_cmd | 1));
1da177e4 7274 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7275 &(pcix_cmd));
1da177e4
LT		 7276
7277 /* Set the PErr Response bit in PCI command register. */
7278 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7279 pci_write_config_word(sp->pdev, PCI_COMMAND,
7280 (pci_cmd | PCI_COMMAND_PARITY));
7281 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7282}
7283
9dc737a7
AR		 7284static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
7285{
7286 if ( tx_fifo_num > 8) {
7287 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
7288 "supported\n");
7289 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
7290 tx_fifo_num = 8;
7291 }
7292 if ( rx_ring_num > 8) {
7293 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7294 "supported\n");
7295 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7296 rx_ring_num = 8;
7297 }
db874e65
SS		 7298 if (*dev_intr_type != INTA)
7299 napi = 0;
7300
eccb8628 7301 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7302 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7303 "Defaulting to INTA\n");
7304 *dev_intr_type = INTA;
7305 }
596c5c97 7306
9dc737a7
AR		 7307 if ((*dev_intr_type == MSI_X) &&
7308 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7309 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7310 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7311 "Defaulting to INTA\n");
7312 *dev_intr_type = INTA;
7313 }
fb6a825b 7314
6d517a27 7315 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7316 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7317 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7318 rx_ring_mode = 1;
9dc737a7
AR		 7319 }
7320 return SUCCESS;
7321}
7322
9fc93a41
SS		 7323/**
7324 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7325 * or Traffic class respectively.
7326 * @nic: device peivate variable
7327 * Description: The function configures the receive steering to
7328 * desired receive ring.
7329 * Return Value: SUCCESS on success and
7330 * '-1' on failure (endian settings incorrect).
7331 */
7332static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7333{
7334 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7335 register u64 val64 = 0;
7336
7337 if (ds_codepoint > 63)
7338 return FAILURE;
7339
7340 val64 = RTS_DS_MEM_DATA(ring);
7341 writeq(val64, &bar0->rts_ds_mem_data);
7342
7343 val64 = RTS_DS_MEM_CTRL_WE |
7344 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7345 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7346
7347 writeq(val64, &bar0->rts_ds_mem_ctrl);
7348
7349 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7350 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7351 S2IO_BIT_RESET);
7352}
7353
1da177e4 7354/**
20346722 7355 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7356 * @pdev : structure containing the PCI related information of the device.
7357 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7358 * Description:
7359 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7360 * All OS related initialization including memory and device structure and
7361 * initlaization of the device private variable is done. Also the swapper
7362 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7363 * registers of the device.
7364 * Return value:
7365 * returns 0 on success and negative on failure.
7366 */
7367
7368static int __devinit
7369s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7370{
1ee6dd77 7371 struct s2io_nic *sp;
1da177e4 7372 struct net_device *dev;
1da177e4
LT		 7373 int i, j, ret;
7374 int dma_flag = FALSE;
7375 u32 mac_up, mac_down;
7376 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7377 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7378 u16 subid;
1ee6dd77 7379 struct mac_info *mac_control;
1da177e4 7380 struct config_param *config;
541ae68f 7381 int mode;
cc6e7c44 7382 u8 dev_intr_type = intr_type;
0795af57 7383 DECLARE_MAC_BUF(mac);
1da177e4 7384
9dc737a7
AR		 7385 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7386 return ret;
1da177e4
LT		 7387
7388 if ((ret = pci_enable_device(pdev))) {
7389 DBG_PRINT(ERR_DBG,
7390 "s2io_init_nic: pci_enable_device failed\n");
7391 return ret;
7392 }
7393
1e7f0bd8 7394 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7395 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7396 dma_flag = TRUE;
1da177e4 7397 if (pci_set_consistent_dma_mask
1e7f0bd8 7398 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7399 DBG_PRINT(ERR_DBG,
7400 "Unable to obtain 64bit DMA for \
7401 consistent allocations\n");
7402 pci_disable_device(pdev);
7403 return -ENOMEM;
7404 }
1e7f0bd8 7405 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 7406 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7407 } else {
7408 pci_disable_device(pdev);
7409 return -ENOMEM;
7410 }
eccb8628
VP		 7411 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7412 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7413 pci_disable_device(pdev);
7414 return -ENODEV;
1da177e4
LT		 7415 }
7416
1ee6dd77 7417 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7418 if (dev == NULL) {
7419 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7420 pci_disable_device(pdev);
7421 pci_release_regions(pdev);
7422 return -ENODEV;
7423 }
7424
7425 pci_set_master(pdev);
7426 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7427 SET_NETDEV_DEV(dev, &pdev->dev);
7428
7429 /* Private member variable initialized to s2io NIC structure */
7430 sp = dev->priv;
1ee6dd77 7431 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7432 sp->dev = dev;
7433 sp->pdev = pdev;
1da177e4 7434 sp->high_dma_flag = dma_flag;
1da177e4 7435 sp->device_enabled_once = FALSE;
da6971d8
AR		 7436 if (rx_ring_mode == 1)
7437 sp->rxd_mode = RXD_MODE_1;
7438 if (rx_ring_mode == 2)
7439 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7440
eaae7f72 7441 sp->config.intr_type = dev_intr_type;
1da177e4 7442
541ae68f
K		 7443 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7444 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7445 sp->device_type = XFRAME_II_DEVICE;
7446 else
7447 sp->device_type = XFRAME_I_DEVICE;
7448
43b7c451 7449 sp->lro = lro_enable;
6aa20a22 7450
1da177e4
LT		 7451 /* Initialize some PCI/PCI-X fields of the NIC. */
7452 s2io_init_pci(sp);
7453
20346722 7454 /*
1da177e4 7455 * Setting the device configuration parameters.
20346722
K		 7456 * Most of these parameters can be specified by the user during
7457 * module insertion as they are module loadable parameters. If
7458 * these parameters are not not specified during load time, they
1da177e4
LT		 7459 * are initialized with default values.
7460 */
7461 mac_control = &sp->mac_control;
7462 config = &sp->config;
7463
596c5c97
SS		 7464 config->napi = napi;
7465
1da177e4 7466 /* Tx side parameters. */
1da177e4
LT		 7467 config->tx_fifo_num = tx_fifo_num;
7468 for (i = 0; i < MAX_TX_FIFOS; i++) {
7469 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7470 config->tx_cfg[i].fifo_priority = i;
7471 }
7472
20346722
K		 7473 /* mapping the QoS priority to the configured fifos */
7474 for (i = 0; i < MAX_TX_FIFOS; i++)
7475 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7476
1da177e4
LT		 7477 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7478 for (i = 0; i < config->tx_fifo_num; i++) {
7479 config->tx_cfg[i].f_no_snoop =
7480 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7481 if (config->tx_cfg[i].fifo_len < 65) {
7482 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7483 break;
7484 }
7485 }
fed5eccd
AR		 7486 /* + 2 because one Txd for skb->data and one Txd for UFO */
7487 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7488
7489 /* Rx side parameters. */
1da177e4
LT		 7490 config->rx_ring_num = rx_ring_num;
7491 for (i = 0; i < MAX_RX_RINGS; i++) {
7492 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7493 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 7494 config->rx_cfg[i].ring_priority = i;
7495 }
7496
7497 for (i = 0; i < rx_ring_num; i++) {
7498 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7499 config->rx_cfg[i].f_no_snoop =
7500 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7501 }
7502
7503 /* Setting Mac Control parameters */
7504 mac_control->rmac_pause_time = rmac_pause_time;
7505 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7506 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7507
7508
7509 /* Initialize Ring buffer parameters. */
7510 for (i = 0; i < config->rx_ring_num; i++)
7511 atomic_set(&sp->rx_bufs_left[i], 0);
7512
7513 /* initialize the shared memory used by the NIC and the host */
7514 if (init_shared_mem(sp)) {
7515 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7516 dev->name);
1da177e4
LT		 7517 ret = -ENOMEM;
7518 goto mem_alloc_failed;
7519 }
7520
7521 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7522 pci_resource_len(pdev, 0));
7523 if (!sp->bar0) {
19a60522 7524 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7525 dev->name);
7526 ret = -ENOMEM;
7527 goto bar0_remap_failed;
7528 }
7529
7530 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7531 pci_resource_len(pdev, 2));
7532 if (!sp->bar1) {
19a60522 7533 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7534 dev->name);
7535 ret = -ENOMEM;
7536 goto bar1_remap_failed;
7537 }
7538
7539 dev->irq = pdev->irq;
7540 dev->base_addr = (unsigned long) sp->bar0;
7541
7542 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7543 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7544 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7545 (sp->bar1 + (j * 0x00020000));
7546 }
7547
7548 /* Driver entry points */
7549 dev->open = &s2io_open;
7550 dev->stop = &s2io_close;
7551 dev->hard_start_xmit = &s2io_xmit;
7552 dev->get_stats = &s2io_get_stats;
7553 dev->set_multicast_list = &s2io_set_multicast;
7554 dev->do_ioctl = &s2io_ioctl;
2fd37688 7555 dev->set_mac_address = &s2io_set_mac_addr;
1da177e4
LT		 7556 dev->change_mtu = &s2io_change_mtu;
7557 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02
K		 7558 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7559 dev->vlan_rx_register = s2io_vlan_rx_register;
20346722 7560
1da177e4
LT		 7561 /*
7562 * will use eth_mac_addr() for dev->set_mac_address
7563 * mac address will be set every time dev->open() is called
7564 */
bea3348e 7565 netif_napi_add(dev, &sp->napi, s2io_poll, 32);
1da177e4 7566
612eff0e
BH		 7567#ifdef CONFIG_NET_POLL_CONTROLLER
7568 dev->poll_controller = s2io_netpoll;
7569#endif
7570
1da177e4
LT		 7571 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7572 if (sp->high_dma_flag == TRUE)
7573 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7574 dev->features |= NETIF_F_TSO;
f83ef8c0 7575 dev->features |= NETIF_F_TSO6;
db874e65 7576 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7577 dev->features |= NETIF_F_UFO;
7578 dev->features |= NETIF_F_HW_CSUM;
7579 }
1da177e4
LT		 7580
7581 dev->tx_timeout = &s2io_tx_watchdog;
7582 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7583 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7584 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7585
e960fc5c 7586 pci_save_state(sp->pdev);
1da177e4
LT		 7587
7588 /* Setting swapper control on the NIC, for proper reset operation */
7589 if (s2io_set_swapper(sp)) {
7590 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7591 dev->name);
7592 ret = -EAGAIN;
7593 goto set_swap_failed;
7594 }
7595
541ae68f
K		 7596 /* Verify if the Herc works on the slot its placed into */
7597 if (sp->device_type & XFRAME_II_DEVICE) {
7598 mode = s2io_verify_pci_mode(sp);
7599 if (mode < 0) {
7600 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7601 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7602 ret = -EBADSLT;
7603 goto set_swap_failed;
7604 }
7605 }
7606
7607 /* Not needed for Herc */
7608 if (sp->device_type & XFRAME_I_DEVICE) {
7609 /*
7610 * Fix for all "FFs" MAC address problems observed on
7611 * Alpha platforms
7612 */
7613 fix_mac_address(sp);
7614 s2io_reset(sp);
7615 }
1da177e4
LT		 7616
7617 /*
1da177e4
LT		 7618 * MAC address initialization.
7619 * For now only one mac address will be read and used.
7620 */
7621 bar0 = sp->bar0;
7622 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7623 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7624 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 7625 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 7626 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 7627 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7628 mac_down = (u32) tmp64;
7629 mac_up = (u32) (tmp64 >> 32);
7630
1da177e4
LT		 7631 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7632 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7633 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7634 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7635 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7636 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7637
1da177e4
LT		 7638 /* Set the factory defined MAC address initially */
7639 dev->addr_len = ETH_ALEN;
7640 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 7641 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 7642
c77dd43e
SS		 7643 /* Store the values of the MSIX table in the s2io_nic structure */
7644 store_xmsi_data(sp);
b41477f3
AR		 7645 /* reset Nic and bring it to known state */
7646 s2io_reset(sp);
7647
1da177e4 7648 /*
20346722 7649 * Initialize the tasklet status and link state flags
541ae68f 7650 * and the card state parameter
1da177e4 7651 */
1da177e4 7652 sp->tasklet_status = 0;
92b84437 7653 sp->state = 0;
1da177e4 7654
1da177e4
LT		 7655 /* Initialize spinlocks */
7656 spin_lock_init(&sp->tx_lock);
db874e65
SS		 7657
7658 if (!napi)
7659 spin_lock_init(&sp->put_lock);
7ba013ac 7660 spin_lock_init(&sp->rx_lock);
1da177e4 7661
20346722
K		 7662 /*
7663 * SXE-002: Configure link and activity LED to init state
7664 * on driver load.
1da177e4
LT		 7665 */
7666 subid = sp->pdev->subsystem_device;
7667 if ((subid & 0xFF) >= 0x07) {
7668 val64 = readq(&bar0->gpio_control);
7669 val64 |= 0x0000800000000000ULL;
7670 writeq(val64, &bar0->gpio_control);
7671 val64 = 0x0411040400000000ULL;
7672 writeq(val64, (void __iomem *) bar0 + 0x2700);
7673 val64 = readq(&bar0->gpio_control);
7674 }
7675
7676 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7677
7678 if (register_netdev(dev)) {
7679 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7680 ret = -ENODEV;
7681 goto register_failed;
7682 }
9dc737a7 7683 s2io_vpd_read(sp);
0c61ed5f 7684 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 7685 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 7686 sp->product_name, pdev->revision);
b41477f3
AR		 7687 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7688 s2io_driver_version);
0795af57
JP		 7689 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
7690 dev->name, print_mac(mac, dev->dev_addr));
19a60522 7691 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 7692 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 7693 mode = s2io_print_pci_mode(sp);
541ae68f 7694 if (mode < 0) {
9dc737a7 7695 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 7696 ret = -EBADSLT;
9dc737a7 7697 unregister_netdev(dev);
541ae68f
K		 7698 goto set_swap_failed;
7699 }
541ae68f 7700 }
9dc737a7
AR		 7701 switch(sp->rxd_mode) {
7702 case RXD_MODE_1:
7703 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7704 dev->name);
7705 break;
7706 case RXD_MODE_3B:
7707 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7708 dev->name);
7709 break;
9dc737a7 7710 }
db874e65
SS		 7711
7712 if (napi)
7713 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
eaae7f72 7714 switch(sp->config.intr_type) {
9dc737a7
AR		 7715 case INTA:
7716 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7717 break;
9dc737a7
AR		 7718 case MSI_X:
7719 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7720 break;
7721 }
7d3d0439
RA		 7722 if (sp->lro)
7723 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 7724 dev->name);
db874e65
SS		 7725 if (ufo)
7726 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7727 " enabled\n", dev->name);
7ba013ac 7728 /* Initialize device name */
9dc737a7 7729 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 7730
20346722
K		 7731 /*
7732 * Make Link state as off at this point, when the Link change
7733 * interrupt comes the state will be automatically changed to
1da177e4
LT		 7734 * the right state.
7735 */
7736 netif_carrier_off(dev);
1da177e4
LT		 7737
7738 return 0;
7739
7740 register_failed:
7741 set_swap_failed:
7742 iounmap(sp->bar1);
7743 bar1_remap_failed:
7744 iounmap(sp->bar0);
7745 bar0_remap_failed:
7746 mem_alloc_failed:
7747 free_shared_mem(sp);
7748 pci_disable_device(pdev);
eccb8628 7749 pci_release_regions(pdev);
1da177e4
LT		 7750 pci_set_drvdata(pdev, NULL);
7751 free_netdev(dev);
7752
7753 return ret;
7754}
7755
7756/**
20346722 7757 * s2io_rem_nic - Free the PCI device
1da177e4 7758 * @pdev: structure containing the PCI related information of the device.
20346722 7759 * Description: This function is called by the Pci subsystem to release a
1da177e4 7760 * PCI device and free up all resource held up by the device. This could
20346722 7761 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 7762 * from memory.
7763 */
7764
7765static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7766{
7767 struct net_device *dev =
7768 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 7769 struct s2io_nic *sp;
1da177e4
LT		 7770
7771 if (dev == NULL) {
7772 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7773 return;
7774 }
7775
22747d6b
FR		 7776 flush_scheduled_work();
7777
1da177e4
LT		 7778 sp = dev->priv;
7779 unregister_netdev(dev);
7780
7781 free_shared_mem(sp);
7782 iounmap(sp->bar0);
7783 iounmap(sp->bar1);
eccb8628 7784 pci_release_regions(pdev);
1da177e4 7785 pci_set_drvdata(pdev, NULL);
1da177e4 7786 free_netdev(dev);
19a60522 7787 pci_disable_device(pdev);
1da177e4
LT		 7788}
7789
7790/**
7791 * s2io_starter - Entry point for the driver
7792 * Description: This function is the entry point for the driver. It verifies
7793 * the module loadable parameters and initializes PCI configuration space.
7794 */
7795
43b7c451 7796static int __init s2io_starter(void)
1da177e4 7797{
29917620 7798 return pci_register_driver(&s2io_driver);
1da177e4
LT		 7799}
7800
7801/**
20346722 7802 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 7803 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7804 */
7805
372cc597 7806static __exit void s2io_closer(void)
1da177e4
LT		 7807{
7808 pci_unregister_driver(&s2io_driver);
7809 DBG_PRINT(INIT_DBG, "cleanup done\n");
7810}
7811
7812module_init(s2io_starter);
7813module_exit(s2io_closer);
7d3d0439 7814
6aa20a22 7815static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
1ee6dd77 7816 struct tcphdr **tcp, struct RxD_t *rxdp)
7d3d0439
RA		 7817{
7818 int ip_off;
7819 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7820
7821 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7822 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7823 __FUNCTION__);
7824 return -1;
7825 }
7826
7827 /* TODO:
7828 * By default the VLAN field in the MAC is stripped by the card, if this
7829 * feature is turned off in rx_pa_cfg register, then the ip_off field
7830 * has to be shifted by a further 2 bytes
7831 */
7832 switch (l2_type) {
7833 case 0: /* DIX type */
7834 case 4: /* DIX type with VLAN */
7835 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7836 break;
7837 /* LLC, SNAP etc are considered non-mergeable */
7838 default:
7839 return -1;
7840 }
7841
7842 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7843 ip_len = (u8)((*ip)->ihl);
7844 ip_len <<= 2;
7845 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7846
7847 return 0;
7848}
7849
1ee6dd77 7850static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7851 struct tcphdr *tcp)
7852{
7853 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7854 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7855 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7856 return -1;
7857 return 0;
7858}
7859
7860static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7861{
7862 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7863}
7864
1ee6dd77 7865static void initiate_new_session(struct lro *lro, u8 *l2h,
7d3d0439
RA		 7866 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7867{
7868 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7869 lro->l2h = l2h;
7870 lro->iph = ip;
7871 lro->tcph = tcp;
7872 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7873 lro->tcp_ack = ntohl(tcp->ack_seq);
7874 lro->sg_num = 1;
7875 lro->total_len = ntohs(ip->tot_len);
7876 lro->frags_len = 0;
6aa20a22 7877 /*
7d3d0439
RA		 7878 * check if we saw TCP timestamp. Other consistency checks have
7879 * already been done.
7880 */
7881 if (tcp->doff == 8) {
7882 u32 *ptr;
7883 ptr = (u32 *)(tcp+1);
7884 lro->saw_ts = 1;
7885 lro->cur_tsval = *(ptr+1);
7886 lro->cur_tsecr = *(ptr+2);
7887 }
7888 lro->in_use = 1;
7889}
7890
1ee6dd77 7891static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 7892{
7893 struct iphdr *ip = lro->iph;
7894 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 7895 __sum16 nchk;
1ee6dd77 7896 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 7897 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7898
7899 /* Update L3 header */
7900 ip->tot_len = htons(lro->total_len);
7901 ip->check = 0;
7902 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7903 ip->check = nchk;
7904
7905 /* Update L4 header */
7906 tcp->ack_seq = lro->tcp_ack;
7907 tcp->window = lro->window;
7908
7909 /* Update tsecr field if this session has timestamps enabled */
7910 if (lro->saw_ts) {
7911 u32 *ptr = (u32 *)(tcp + 1);
7912 *(ptr+2) = lro->cur_tsecr;
7913 }
7914
7915 /* Update counters required for calculation of
7916 * average no. of packets aggregated.
7917 */
7918 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7919 statinfo->sw_stat.num_aggregations++;
7920}
7921
1ee6dd77 7922static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7923 struct tcphdr *tcp, u32 l4_pyld)
7924{
7925 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7926 lro->total_len += l4_pyld;
7927 lro->frags_len += l4_pyld;
7928 lro->tcp_next_seq += l4_pyld;
7929 lro->sg_num++;
7930
7931 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7932 lro->tcp_ack = tcp->ack_seq;
7933 lro->window = tcp->window;
6aa20a22 7934
7d3d0439
RA		 7935 if (lro->saw_ts) {
7936 u32 *ptr;
7937 /* Update tsecr and tsval from this packet */
7938 ptr = (u32 *) (tcp + 1);
6aa20a22 7939 lro->cur_tsval = *(ptr + 1);
7d3d0439
RA		 7940 lro->cur_tsecr = *(ptr + 2);
7941 }
7942}
7943
1ee6dd77 7944static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 7945 struct tcphdr *tcp, u32 tcp_pyld_len)
7946{
7d3d0439
RA		 7947 u8 *ptr;
7948
79dc1901
AM		 7949 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7950
7d3d0439
RA		 7951 if (!tcp_pyld_len) {
7952 /* Runt frame or a pure ack */
7953 return -1;
7954 }
7955
7956 if (ip->ihl != 5) /* IP has options */
7957 return -1;
7958
75c30b13
AR		 7959 /* If we see CE codepoint in IP header, packet is not mergeable */
7960 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7961 return -1;
7962
7963 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 7964 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 7965 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 7966 /*
7967 * Currently recognize only the ack control word and
7968 * any other control field being set would result in
7969 * flushing the LRO session
7970 */
7971 return -1;
7972 }
7973
6aa20a22 7974 /*
7d3d0439
RA		 7975 * Allow only one TCP timestamp option. Don't aggregate if
7976 * any other options are detected.
7977 */
7978 if (tcp->doff != 5 && tcp->doff != 8)
7979 return -1;
7980
7981 if (tcp->doff == 8) {
6aa20a22 7982 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 7983 while (*ptr == TCPOPT_NOP)
7984 ptr++;
7985 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7986 return -1;
7987
7988 /* Ensure timestamp value increases monotonically */
7989 if (l_lro)
7990 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7991 return -1;
7992
7993 /* timestamp echo reply should be non-zero */
6aa20a22 7994 if (*((u32 *)(ptr+6)) == 0)
7d3d0439
RA		 7995 return -1;
7996 }
7997
7998 return 0;
7999}
8000
8001static int
1ee6dd77
RB		 8002s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
8003 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8004{
8005 struct iphdr *ip;
8006 struct tcphdr *tcph;
8007 int ret = 0, i;
8008
8009 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8010 rxdp))) {
8011 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8012 ip->saddr, ip->daddr);
8013 } else {
8014 return ret;
8015 }
8016
8017 tcph = (struct tcphdr *)*tcp;
8018 *tcp_len = get_l4_pyld_length(ip, tcph);
8019 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 8020 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 8021 if (l_lro->in_use) {
8022 if (check_for_socket_match(l_lro, ip, tcph))
8023 continue;
8024 /* Sock pair matched */
8025 *lro = l_lro;
8026
8027 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8028 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8029 "0x%x, actual 0x%x\n", __FUNCTION__,
8030 (*lro)->tcp_next_seq,
8031 ntohl(tcph->seq));
8032
8033 sp->mac_control.stats_info->
8034 sw_stat.outof_sequence_pkts++;
8035 ret = 2;
8036 break;
8037 }
8038
8039 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8040 ret = 1; /* Aggregate */
8041 else
8042 ret = 2; /* Flush both */
8043 break;
8044 }
8045 }
8046
8047 if (ret == 0) {
8048 /* Before searching for available LRO objects,
8049 * check if the pkt is L3/L4 aggregatable. If not
8050 * don't create new LRO session. Just send this
8051 * packet up.
8052 */
8053 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8054 return 5;
8055 }
8056
8057 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 8058 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 8059 if (!(l_lro->in_use)) {
8060 *lro = l_lro;
8061 ret = 3; /* Begin anew */
8062 break;
8063 }
8064 }
8065 }
8066
8067 if (ret == 0) { /* sessions exceeded */
8068 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8069 __FUNCTION__);
8070 *lro = NULL;
8071 return ret;
8072 }
8073
8074 switch (ret) {
8075 case 3:
8076 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
8077 break;
8078 case 2:
8079 update_L3L4_header(sp, *lro);
8080 break;
8081 case 1:
8082 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8083 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8084 update_L3L4_header(sp, *lro);
8085 ret = 4; /* Flush the LRO */
8086 }
8087 break;
8088 default:
8089 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8090 __FUNCTION__);
8091 break;
8092 }
8093
8094 return ret;
8095}
8096
1ee6dd77 8097static void clear_lro_session(struct lro *lro)
7d3d0439 8098{
1ee6dd77 8099 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8100
8101 memset(lro, 0, lro_struct_size);
8102}
8103
8104static void queue_rx_frame(struct sk_buff *skb)
8105{
8106 struct net_device *dev = skb->dev;
8107
8108 skb->protocol = eth_type_trans(skb, dev);
db874e65
SS		 8109 if (napi)
8110 netif_receive_skb(skb);
8111 else
8112 netif_rx(skb);
7d3d0439
RA		 8113}
8114
1ee6dd77
RB		 8115static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8116 struct sk_buff *skb,
7d3d0439
RA		 8117 u32 tcp_len)
8118{
75c30b13 8119 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8120
8121 first->len += tcp_len;
8122 first->data_len = lro->frags_len;
8123 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8124 if (skb_shinfo(first)->frag_list)
8125 lro->last_frag->next = skb;
7d3d0439
RA		 8126 else
8127 skb_shinfo(first)->frag_list = skb;
372cc597 8128 first->truesize += skb->truesize;
75c30b13 8129 lro->last_frag = skb;
7d3d0439
RA		 8130 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8131 return;
8132}
d796fdb7
LV		 8133
8134/**
8135 * s2io_io_error_detected - called when PCI error is detected
8136 * @pdev: Pointer to PCI device
8453d43f 8137 * @state: The current pci connection state
d796fdb7
LV		 8138 *
8139 * This function is called after a PCI bus error affecting
8140 * this device has been detected.
8141 */
8142static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8143 pci_channel_state_t state)
8144{
8145 struct net_device *netdev = pci_get_drvdata(pdev);
8146 struct s2io_nic *sp = netdev->priv;
8147
8148 netif_device_detach(netdev);
8149
8150 if (netif_running(netdev)) {
8151 /* Bring down the card, while avoiding PCI I/O */
8152 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8153 }
8154 pci_disable_device(pdev);
8155
8156 return PCI_ERS_RESULT_NEED_RESET;
8157}
8158
8159/**
8160 * s2io_io_slot_reset - called after the pci bus has been reset.
8161 * @pdev: Pointer to PCI device
8162 *
8163 * Restart the card from scratch, as if from a cold-boot.
8164 * At this point, the card has exprienced a hard reset,
8165 * followed by fixups by BIOS, and has its config space
8166 * set up identically to what it was at cold boot.
8167 */
8168static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8169{
8170 struct net_device *netdev = pci_get_drvdata(pdev);
8171 struct s2io_nic *sp = netdev->priv;
8172
8173 if (pci_enable_device(pdev)) {
8174 printk(KERN_ERR "s2io: "
8175 "Cannot re-enable PCI device after reset.\n");
8176 return PCI_ERS_RESULT_DISCONNECT;
8177 }
8178
8179 pci_set_master(pdev);
8180 s2io_reset(sp);
8181
8182 return PCI_ERS_RESULT_RECOVERED;
8183}
8184
8185/**
8186 * s2io_io_resume - called when traffic can start flowing again.
8187 * @pdev: Pointer to PCI device
8188 *
8189 * This callback is called when the error recovery driver tells
8190 * us that its OK to resume normal operation.
8191 */
8192static void s2io_io_resume(struct pci_dev *pdev)
8193{
8194 struct net_device *netdev = pci_get_drvdata(pdev);
8195 struct s2io_nic *sp = netdev->priv;
8196
8197 if (netif_running(netdev)) {
8198 if (s2io_card_up(sp)) {
8199 printk(KERN_ERR "s2io: "
8200 "Can't bring device back up after reset.\n");
8201 return;
8202 }
8203
8204 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8205 s2io_card_down(sp);
8206 printk(KERN_ERR "s2io: "
8207 "Can't resetore mac addr after reset.\n");
8208 return;
8209 }
8210 }
8211
8212 netif_device_attach(netdev);
8213 netif_wake_queue(netdev);
8214}
Clone of davem's net-next-2.6 tree