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ixgbe: Fix interrupt configuration for 82599
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
e8e26350 50#define DRV_VERSION "2.0.8-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
e8e26350 56 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 57};
58
59/* ixgbe_pci_tbl - PCI Device ID Table
60 *
61 * Wildcard entries (PCI_ANY_ID) should come last
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 68 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 board_82598 },
9a799d71 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 73 board_82598 },
0befdb3e
JB		 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 77 board_82598 },
8d792cd9
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 board_82598 },
c4900be0
DS		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 board_82598 },
b95f5fcb
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 board_82598 },
2f21bdd3
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89 board_82598 },
e8e26350
PW		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91 board_82599 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93 board_82599 },
9a799d71
AK		 94
95 /* required last entry */
96 {0, }
97};
98MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
5dd2d332 100#ifdef CONFIG_IXGBE_DCA
bd0362dd 101static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 102 void *p);
bd0362dd
JC		 103static struct notifier_block dca_notifier = {
104 .notifier_call = ixgbe_notify_dca,
105 .next = NULL,
106 .priority = 0
107};
108#endif
109
9a799d71
AK		 110MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112MODULE_LICENSE("GPL");
113MODULE_VERSION(DRV_VERSION);
114
115#define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
5eba3699
AV		 117static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118{
119 u32 ctrl_ext;
120
121 /* Let firmware take over control of h/w */
122 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 124 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 125}
126
127static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128{
129 u32 ctrl_ext;
130
131 /* Let firmware know the driver has taken over */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 134 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 135}
9a799d71 136
e8e26350
PW		 137/*
138 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139 * @adapter: pointer to adapter struct
140 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141 * @queue: queue to map the corresponding interrupt to
142 * @msix_vector: the vector to map to the corresponding queue
143 *
144 */
145static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146 u8 queue, u8 msix_vector)
9a799d71
AK		 147{
148 u32 ivar, index;
e8e26350
PW		 149 struct ixgbe_hw *hw = &adapter->hw;
150 switch (hw->mac.type) {
151 case ixgbe_mac_82598EB:
152 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153 if (direction == -1)
154 direction = 0;
155 index = (((direction * 64) + queue) >> 2) & 0x1F;
156 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158 ivar |= (msix_vector << (8 * (queue & 0x3)));
159 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160 break;
161 case ixgbe_mac_82599EB:
162 if (direction == -1) {
163 /* other causes */
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 index = ((queue & 1) * 8);
166 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167 ivar &= ~(0xFF << index);
168 ivar |= (msix_vector << index);
169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170 break;
171 } else {
172 /* tx or rx causes */
173 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174 index = ((16 * (queue & 1)) + (8 * direction));
175 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176 ivar &= ~(0xFF << index);
177 ivar |= (msix_vector << index);
178 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179 break;
180 }
181 default:
182 break;
183 }
9a799d71
AK		 184}
185
186static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 187 struct ixgbe_tx_buffer
188 *tx_buffer_info)
9a799d71
AK		 189{
190 if (tx_buffer_info->dma) {
e01c31a5 191 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
b4617240 192 tx_buffer_info->length, PCI_DMA_TODEVICE);
9a799d71
AK		 193 tx_buffer_info->dma = 0;
194 }
195 if (tx_buffer_info->skb) {
196 dev_kfree_skb_any(tx_buffer_info->skb);
197 tx_buffer_info->skb = NULL;
198 }
199 /* tx_buffer_info must be completely set up in the transmit path */
200}
201
202static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 203 struct ixgbe_ring *tx_ring,
204 unsigned int eop)
9a799d71 205{
e01c31a5
JB		 206 struct ixgbe_hw *hw = &adapter->hw;
207 u32 head, tail;
208
9a799d71 209 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 210 * check with the clearing of time_stamp and movement of eop */
211 head = IXGBE_READ_REG(hw, tx_ring->head);
212 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 213 adapter->detect_tx_hung = false;
e01c31a5
JB		 214 if ((head != tail) &&
215 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 216 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
217 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
218 /* detected Tx unit hang */
e01c31a5
JB		 219 union ixgbe_adv_tx_desc *tx_desc;
220 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 221 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 222 " Tx Queue <%d>\n"
223 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 224 " next_to_use <%x>\n"
225 " next_to_clean <%x>\n"
226 "tx_buffer_info[next_to_clean]\n"
227 " time_stamp <%lx>\n"
e01c31a5
JB		 228 " jiffies <%lx>\n",
229 tx_ring->queue_index,
230 head, tail,
231 tx_ring->next_to_use, eop,
232 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 233 return true;
234 }
235
236 return false;
237}
238
b4617240
PW		 239#define IXGBE_MAX_TXD_PWR 14
240#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 241
242/* Tx Descriptors needed, worst case */
243#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
244 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
245#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 246 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 247
e01c31a5
JB		 248static void ixgbe_tx_timeout(struct net_device *netdev);
249
9a799d71
AK		 250/**
251 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
252 * @adapter: board private structure
e01c31a5 253 * @tx_ring: tx ring to clean
9a799d71
AK		 254 **/
255static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 256 struct ixgbe_ring *tx_ring)
9a799d71 257{
e01c31a5 258 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 259 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
260 struct ixgbe_tx_buffer *tx_buffer_info;
261 unsigned int i, eop, count = 0;
e01c31a5 262 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 263
264 i = tx_ring->next_to_clean;
12207e49
PWJ		 265 eop = tx_ring->tx_buffer_info[i].next_to_watch;
266 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
267
268 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
269 (count < tx_ring->count)) {
270 bool cleaned = false;
271 for ( ; !cleaned; count++) {
272 struct sk_buff *skb;
9a799d71
AK		 273 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
274 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 275 cleaned = (i == eop);
e01c31a5 276 skb = tx_buffer_info->skb;
9a799d71 277
12207e49 278 if (cleaned && skb) {
e092be60 279 unsigned int segs, bytecount;
e01c31a5
JB		 280
281 /* gso_segs is currently only valid for tcp */
e092be60
AV		 282 segs = skb_shinfo(skb)->gso_segs ?: 1;
283 /* multiply data chunks by size of headers */
284 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 285 skb->len;
286 total_packets += segs;
287 total_bytes += bytecount;
e092be60 288 }
e01c31a5 289
9a799d71 290 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 291 tx_buffer_info);
9a799d71 292
12207e49
PWJ		 293 tx_desc->wb.status = 0;
294
9a799d71
AK		 295 i++;
296 if (i == tx_ring->count)
297 i = 0;
e01c31a5 298 }
12207e49
PWJ		 299
300 eop = tx_ring->tx_buffer_info[i].next_to_watch;
301 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
302 }
303
9a799d71
AK		 304 tx_ring->next_to_clean = i;
305
e092be60 306#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 307 if (unlikely(count && netif_carrier_ok(netdev) &&
308 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 309 /* Make sure that anybody stopping the queue after this
310 * sees the new next_to_clean.
311 */
312 smp_mb();
30eba97a
AV		 313 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
314 !test_bit(__IXGBE_DOWN, &adapter->state)) {
315 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 316 ++adapter->restart_queue;
30eba97a 317 }
e092be60 318 }
9a799d71 319
e01c31a5
JB		 320 if (adapter->detect_tx_hung) {
321 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
322 /* schedule immediate reset if we believe we hung */
323 DPRINTK(PROBE, INFO,
324 "tx hang %d detected, resetting adapter\n",
325 adapter->tx_timeout_count + 1);
326 ixgbe_tx_timeout(adapter->netdev);
327 }
328 }
9a799d71 329
e01c31a5
JB		 330 /* re-arm the interrupt */
331 if ((total_packets >= tx_ring->work_limit) ||
332 (count == tx_ring->count))
333 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 334
e01c31a5
JB		 335 tx_ring->total_bytes += total_bytes;
336 tx_ring->total_packets += total_packets;
e01c31a5 337 tx_ring->stats.packets += total_packets;
12207e49 338 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 339 adapter->net_stats.tx_bytes += total_bytes;
340 adapter->net_stats.tx_packets += total_packets;
341 return (total_packets ? true : false);
9a799d71
AK		 342}
343
5dd2d332 344#ifdef CONFIG_IXGBE_DCA
bd0362dd 345static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 346 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 347{
348 u32 rxctrl;
349 int cpu = get_cpu();
3a581073 350 int q = rx_ring - adapter->rx_ring;
bd0362dd 351
3a581073 352 if (rx_ring->cpu != cpu) {
bd0362dd 353 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 354 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
355 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
356 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
357 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
358 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
359 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
360 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
361 }
bd0362dd
JC		 362 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
363 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 364 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
365 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 366 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 368 rx_ring->cpu = cpu;
bd0362dd
JC		 369 }
370 put_cpu();
371}
372
373static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 374 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 375{
376 u32 txctrl;
377 int cpu = get_cpu();
3a581073 378 int q = tx_ring - adapter->tx_ring;
bd0362dd 379
3a581073 380 if (tx_ring->cpu != cpu) {
bd0362dd 381 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 382 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
383 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
384 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
385 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
386 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
387 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
388 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
389 }
bd0362dd
JC		 390 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 392 tx_ring->cpu = cpu;
bd0362dd
JC		 393 }
394 put_cpu();
395}
396
397static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
398{
399 int i;
400
401 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
402 return;
403
404 for (i = 0; i < adapter->num_tx_queues; i++) {
405 adapter->tx_ring[i].cpu = -1;
406 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
407 }
408 for (i = 0; i < adapter->num_rx_queues; i++) {
409 adapter->rx_ring[i].cpu = -1;
410 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
411 }
412}
413
414static int __ixgbe_notify_dca(struct device *dev, void *data)
415{
416 struct net_device *netdev = dev_get_drvdata(dev);
417 struct ixgbe_adapter *adapter = netdev_priv(netdev);
418 unsigned long event = *(unsigned long *)data;
419
420 switch (event) {
421 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 422 /* if we're already enabled, don't do it again */
423 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
424 break;
bd0362dd
JC		 425 /* Always use CB2 mode, difference is masked
426 * in the CB driver. */
427 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 428 if (dca_add_requester(dev) == 0) {
96b0e0f6 429 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 430 ixgbe_setup_dca(adapter);
431 break;
432 }
433 /* Fall Through since DCA is disabled. */
434 case DCA_PROVIDER_REMOVE:
435 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
436 dca_remove_requester(dev);
437 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
438 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
439 }
440 break;
441 }
442
652f093f 443 return 0;
bd0362dd
JC		 444}
445
5dd2d332 446#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 447/**
448 * ixgbe_receive_skb - Send a completed packet up the stack
449 * @adapter: board private structure
450 * @skb: packet to send up
177db6ff
MC		 451 * @status: hardware indication of status of receive
452 * @rx_ring: rx descriptor ring (for a specific queue) to setup
453 * @rx_desc: rx descriptor
9a799d71 454 **/
78b6f4ce 455static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 456 struct sk_buff *skb, u8 status,
177db6ff 457 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 458{
78b6f4ce
HX		 459 struct ixgbe_adapter *adapter = q_vector->adapter;
460 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 461 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
462 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 463
0c8dfc83 464 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
78b6f4ce 465 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
2f90b865 466 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 467 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 468 else
78b6f4ce 469 napi_gro_receive(napi, skb);
177db6ff
MC		 470 } else {
471 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 472 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 473 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
474 else
475 netif_receive_skb(skb);
476 } else {
2f90b865 477 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 478 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
479 else
480 netif_rx(skb);
481 }
9a799d71
AK		 482 }
483}
484
e59bd25d
AV		 485/**
486 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
487 * @adapter: address of board private structure
488 * @status_err: hardware indication of status of receive
489 * @skb: skb currently being received and modified
490 **/
9a799d71 491static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 492 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 493{
494 skb->ip_summed = CHECKSUM_NONE;
495
712744be
JB		 496 /* Rx csum disabled */
497 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 498 return;
e59bd25d
AV		 499
500 /* if IP and error */
501 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
502 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 503 adapter->hw_csum_rx_error++;
504 return;
505 }
e59bd25d
AV		 506
507 if (!(status_err & IXGBE_RXD_STAT_L4CS))
508 return;
509
510 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
511 adapter->hw_csum_rx_error++;
512 return;
513 }
514
9a799d71 515 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 516 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 517 adapter->hw_csum_rx_good++;
518}
519
e8e26350
PW		 520static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
521 struct ixgbe_ring *rx_ring, u32 val)
522{
523 /*
524 * Force memory writes to complete before letting h/w
525 * know there are new descriptors to fetch. (Only
526 * applicable for weak-ordered memory model archs,
527 * such as IA-64).
528 */
529 wmb();
530 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
531}
532
9a799d71
AK		 533/**
534 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
535 * @adapter: address of board private structure
536 **/
537static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 538 struct ixgbe_ring *rx_ring,
539 int cleaned_count)
9a799d71 540{
9a799d71
AK		 541 struct pci_dev *pdev = adapter->pdev;
542 union ixgbe_adv_rx_desc *rx_desc;
3a581073 543 struct ixgbe_rx_buffer *bi;
9a799d71 544 unsigned int i;
e8e26350 545 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 546
547 i = rx_ring->next_to_use;
3a581073 548 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 549
550 while (cleaned_count--) {
551 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
552
762f4c57 553 if (!bi->page_dma &&
3a581073 554 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 555 if (!bi->page) {
762f4c57
JB		 556 bi->page = alloc_page(GFP_ATOMIC);
557 if (!bi->page) {
558 adapter->alloc_rx_page_failed++;
559 goto no_buffers;
560 }
561 bi->page_offset = 0;
562 } else {
563 /* use a half page if we're re-using */
564 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 565 }
762f4c57
JB		 566
567 bi->page_dma = pci_map_page(pdev, bi->page,
568 bi->page_offset,
569 (PAGE_SIZE / 2),
570 PCI_DMA_FROMDEVICE);
9a799d71
AK		 571 }
572
3a581073 573 if (!bi->skb) {
5ecc3614 574 struct sk_buff *skb;
e8e26350 575 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 576
577 if (!skb) {
578 adapter->alloc_rx_buff_failed++;
579 goto no_buffers;
580 }
581
582 /*
583 * Make buffer alignment 2 beyond a 16 byte boundary
584 * this will result in a 16 byte aligned IP header after
585 * the 14 byte MAC header is removed
586 */
587 skb_reserve(skb, NET_IP_ALIGN);
588
3a581073 589 bi->skb = skb;
e8e26350 590 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 591 PCI_DMA_FROMDEVICE);
9a799d71
AK		 592 }
593 /* Refresh the desc even if buffer_addrs didn't change because
594 * each write-back erases this info. */
595 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 596 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
597 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 598 } else {
3a581073 599 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 600 }
601
602 i++;
603 if (i == rx_ring->count)
604 i = 0;
3a581073 605 bi = &rx_ring->rx_buffer_info[i];
9a799d71 606 }
7c6e0a43 607
9a799d71
AK		 608no_buffers:
609 if (rx_ring->next_to_use != i) {
610 rx_ring->next_to_use = i;
611 if (i-- == 0)
612 i = (rx_ring->count - 1);
613
e8e26350 614 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 615 }
616}
617
7c6e0a43
JB		 618static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
619{
620 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
621}
622
623static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
624{
625 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
626}
627
78b6f4ce 628static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 629 struct ixgbe_ring *rx_ring,
630 int *work_done, int work_to_do)
9a799d71 631{
78b6f4ce 632 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 633 struct pci_dev *pdev = adapter->pdev;
634 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
635 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
636 struct sk_buff *skb;
637 unsigned int i;
7c6e0a43 638 u32 len, staterr;
177db6ff
MC		 639 u16 hdr_info;
640 bool cleaned = false;
9a799d71 641 int cleaned_count = 0;
d2f4fbe2 642 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 643
644 i = rx_ring->next_to_clean;
9a799d71
AK		 645 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
646 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
647 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 648
649 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 650 u32 upper_len = 0;
9a799d71
AK		 651 if (*work_done >= work_to_do)
652 break;
653 (*work_done)++;
654
655 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 656 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
657 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 658 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 659 if (hdr_info & IXGBE_RXDADV_SPH)
660 adapter->rx_hdr_split++;
661 if (len > IXGBE_RX_HDR_SIZE)
662 len = IXGBE_RX_HDR_SIZE;
663 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 664 } else {
9a799d71 665 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 666 }
9a799d71
AK		 667
668 cleaned = true;
669 skb = rx_buffer_info->skb;
670 prefetch(skb->data - NET_IP_ALIGN);
671 rx_buffer_info->skb = NULL;
672
673 if (len && !skb_shinfo(skb)->nr_frags) {
674 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 675 rx_ring->rx_buf_len,
b4617240 676 PCI_DMA_FROMDEVICE);
9a799d71
AK		 677 skb_put(skb, len);
678 }
679
680 if (upper_len) {
681 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 682 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 683 rx_buffer_info->page_dma = 0;
684 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 685 rx_buffer_info->page,
686 rx_buffer_info->page_offset,
687 upper_len);
688
689 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
690 (page_count(rx_buffer_info->page) != 1))
691 rx_buffer_info->page = NULL;
692 else
693 get_page(rx_buffer_info->page);
9a799d71
AK		 694
695 skb->len += upper_len;
696 skb->data_len += upper_len;
697 skb->truesize += upper_len;
698 }
699
700 i++;
701 if (i == rx_ring->count)
702 i = 0;
703 next_buffer = &rx_ring->rx_buffer_info[i];
704
705 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
706 prefetch(next_rxd);
707
708 cleaned_count++;
709 if (staterr & IXGBE_RXD_STAT_EOP) {
710 rx_ring->stats.packets++;
711 rx_ring->stats.bytes += skb->len;
712 } else {
713 rx_buffer_info->skb = next_buffer->skb;
714 rx_buffer_info->dma = next_buffer->dma;
715 next_buffer->skb = skb;
762f4c57 716 next_buffer->dma = 0;
9a799d71
AK		 717 adapter->non_eop_descs++;
718 goto next_desc;
719 }
720
721 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
722 dev_kfree_skb_irq(skb);
723 goto next_desc;
724 }
725
726 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 727
728 /* probably a little skewed due to removing CRC */
729 total_rx_bytes += skb->len;
730 total_rx_packets++;
731
74ce8dd2 732 skb->protocol = eth_type_trans(skb, adapter->netdev);
78b6f4ce 733 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
9a799d71
AK		 734
735next_desc:
736 rx_desc->wb.upper.status_error = 0;
737
738 /* return some buffers to hardware, one at a time is too slow */
739 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
740 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
741 cleaned_count = 0;
742 }
743
744 /* use prefetched values */
745 rx_desc = next_rxd;
746 rx_buffer_info = next_buffer;
747
748 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 749 }
750
9a799d71
AK		 751 rx_ring->next_to_clean = i;
752 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
753
754 if (cleaned_count)
755 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
756
f494e8fa
AV		 757 rx_ring->total_packets += total_rx_packets;
758 rx_ring->total_bytes += total_rx_bytes;
759 adapter->net_stats.rx_bytes += total_rx_bytes;
760 adapter->net_stats.rx_packets += total_rx_packets;
761
9a799d71
AK		 762 return cleaned;
763}
764
021230d4 765static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 766/**
767 * ixgbe_configure_msix - Configure MSI-X hardware
768 * @adapter: board private structure
769 *
770 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
771 * interrupts.
772 **/
773static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
774{
021230d4
AV		 775 struct ixgbe_q_vector *q_vector;
776 int i, j, q_vectors, v_idx, r_idx;
777 u32 mask;
9a799d71 778
021230d4 779 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 780
021230d4
AV		 781 /* Populate the IVAR table and set the ITR values to the
782 * corresponding register.
783 */
784 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
785 q_vector = &adapter->q_vector[v_idx];
786 /* XXX for_each_bit(...) */
787 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 788 adapter->num_rx_queues);
021230d4
AV		 789
790 for (i = 0; i < q_vector->rxr_count; i++) {
791 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 792 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 793 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 794 adapter->num_rx_queues,
795 r_idx + 1);
021230d4
AV		 796 }
797 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 798 adapter->num_tx_queues);
021230d4
AV		 799
800 for (i = 0; i < q_vector->txr_count; i++) {
801 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 802 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 803 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 804 adapter->num_tx_queues,
805 r_idx + 1);
021230d4
AV		 806 }
807
30efa5a3 808 /* if this is a tx only vector halve the interrupt rate */
021230d4 809 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 810 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 811 else if (q_vector->rxr_count)
30efa5a3
JB		 812 /* rx only */
813 q_vector->eitr = adapter->eitr_param;
021230d4 814
509ee935
JB		 815 /*
816 * since ths is initial set up don't need to call
817 * ixgbe_write_eitr helper
818 */
021230d4 819 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 820 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 821 }
822
e8e26350
PW		 823 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
824 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
825 v_idx);
826 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
827 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 828 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
829
41fb9248 830 /* set up to autoclear timer, and the vectors */
021230d4 831 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 832 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 833 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 834}
835
f494e8fa
AV		 836enum latency_range {
837 lowest_latency = 0,
838 low_latency = 1,
839 bulk_latency = 2,
840 latency_invalid = 255
841};
842
843/**
844 * ixgbe_update_itr - update the dynamic ITR value based on statistics
845 * @adapter: pointer to adapter
846 * @eitr: eitr setting (ints per sec) to give last timeslice
847 * @itr_setting: current throttle rate in ints/second
848 * @packets: the number of packets during this measurement interval
849 * @bytes: the number of bytes during this measurement interval
850 *
851 * Stores a new ITR value based on packets and byte
852 * counts during the last interrupt. The advantage of per interrupt
853 * computation is faster updates and more accurate ITR for the current
854 * traffic pattern. Constants in this function were computed
855 * based on theoretical maximum wire speed and thresholds were set based
856 * on testing data as well as attempting to minimize response time
857 * while increasing bulk throughput.
858 * this functionality is controlled by the InterruptThrottleRate module
859 * parameter (see ixgbe_param.c)
860 **/
861static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 862 u32 eitr, u8 itr_setting,
863 int packets, int bytes)
f494e8fa
AV		 864{
865 unsigned int retval = itr_setting;
866 u32 timepassed_us;
867 u64 bytes_perint;
868
869 if (packets == 0)
870 goto update_itr_done;
871
872
873 /* simple throttlerate management
874 * 0-20MB/s lowest (100000 ints/s)
875 * 20-100MB/s low (20000 ints/s)
876 * 100-1249MB/s bulk (8000 ints/s)
877 */
878 /* what was last interrupt timeslice? */
879 timepassed_us = 1000000/eitr;
880 bytes_perint = bytes / timepassed_us; /* bytes/usec */
881
882 switch (itr_setting) {
883 case lowest_latency:
884 if (bytes_perint > adapter->eitr_low)
885 retval = low_latency;
886 break;
887 case low_latency:
888 if (bytes_perint > adapter->eitr_high)
889 retval = bulk_latency;
890 else if (bytes_perint <= adapter->eitr_low)
891 retval = lowest_latency;
892 break;
893 case bulk_latency:
894 if (bytes_perint <= adapter->eitr_high)
895 retval = low_latency;
896 break;
897 }
898
899update_itr_done:
900 return retval;
901}
902
509ee935
JB		 903/**
904 * ixgbe_write_eitr - write EITR register in hardware specific way
905 * @adapter: pointer to adapter struct
906 * @v_idx: vector index into q_vector array
907 * @itr_reg: new value to be written in *register* format, not ints/s
908 *
909 * This function is made to be called by ethtool and by the driver
910 * when it needs to update EITR registers at runtime. Hardware
911 * specific quirks/differences are taken care of here.
912 */
913void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
914{
915 struct ixgbe_hw *hw = &adapter->hw;
916 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
917 /* must write high and low 16 bits to reset counter */
918 itr_reg |= (itr_reg << 16);
919 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
920 /*
921 * set the WDIS bit to not clear the timer bits and cause an
922 * immediate assertion of the interrupt
923 */
924 itr_reg |= IXGBE_EITR_CNT_WDIS;
925 }
926 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
927}
928
f494e8fa
AV		 929static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
930{
931 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 932 u32 new_itr;
933 u8 current_itr, ret_itr;
934 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 935 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 936 struct ixgbe_ring *rx_ring, *tx_ring;
937
938 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
939 for (i = 0; i < q_vector->txr_count; i++) {
940 tx_ring = &(adapter->tx_ring[r_idx]);
941 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 942 q_vector->tx_itr,
943 tx_ring->total_packets,
944 tx_ring->total_bytes);
f494e8fa
AV		 945 /* if the result for this queue would decrease interrupt
946 * rate for this vector then use that result */
30efa5a3 947 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 948 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 949 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 950 r_idx + 1);
f494e8fa
AV		 951 }
952
953 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
954 for (i = 0; i < q_vector->rxr_count; i++) {
955 rx_ring = &(adapter->rx_ring[r_idx]);
956 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 957 q_vector->rx_itr,
958 rx_ring->total_packets,
959 rx_ring->total_bytes);
f494e8fa
AV		 960 /* if the result for this queue would decrease interrupt
961 * rate for this vector then use that result */
30efa5a3 962 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 963 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 964 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 965 r_idx + 1);
f494e8fa
AV		 966 }
967
30efa5a3 968 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 969
970 switch (current_itr) {
971 /* counts and packets in update_itr are dependent on these numbers */
972 case lowest_latency:
973 new_itr = 100000;
974 break;
975 case low_latency:
976 new_itr = 20000; /* aka hwitr = ~200 */
977 break;
978 case bulk_latency:
979 default:
980 new_itr = 8000;
981 break;
982 }
983
984 if (new_itr != q_vector->eitr) {
985 u32 itr_reg;
509ee935
JB		 986
987 /* save the algorithm value here, not the smoothed one */
988 q_vector->eitr = new_itr;
f494e8fa
AV		 989 /* do an exponential smoothing */
990 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 991 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 992 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 993 }
994
995 return;
996}
997
0befdb3e
JB		 998static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
999{
1000 struct ixgbe_hw *hw = &adapter->hw;
1001
1002 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1003 (eicr & IXGBE_EICR_GPI_SDP1)) {
1004 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1005 /* write to clear the interrupt */
1006 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1007 }
1008}
cf8280ee 1009
e8e26350
PW		 1010static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1011{
1012 struct ixgbe_hw *hw = &adapter->hw;
1013
1014 if (eicr & IXGBE_EICR_GPI_SDP1) {
1015 /* Clear the interrupt */
1016 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1017 schedule_work(&adapter->multispeed_fiber_task);
1018 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1019 /* Clear the interrupt */
1020 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1021 schedule_work(&adapter->sfp_config_module_task);
1022 } else {
1023 /* Interrupt isn't for us... */
1024 return;
1025 }
1026}
1027
cf8280ee
JB		 1028static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1029{
1030 struct ixgbe_hw *hw = &adapter->hw;
1031
1032 adapter->lsc_int++;
1033 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1034 adapter->link_check_timeout = jiffies;
1035 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1036 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1037 schedule_work(&adapter->watchdog_task);
1038 }
1039}
1040
9a799d71
AK		 1041static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1042{
1043 struct net_device *netdev = data;
1044 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1045 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1046 u32 eicr;
1047
1048 /*
1049 * Workaround for Silicon errata. Use clear-by-write instead
1050 * of clear-by-read. Reading with EICS will return the
1051 * interrupt causes without clearing, which later be done
1052 * with the write to EICR.
1053 */
1054 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1055 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1056
cf8280ee
JB		 1057 if (eicr & IXGBE_EICR_LSC)
1058 ixgbe_check_lsc(adapter);
d4f80882 1059
e8e26350
PW		 1060 if (hw->mac.type == ixgbe_mac_82598EB)
1061 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1062
e8e26350
PW		 1063 if (hw->mac.type == ixgbe_mac_82599EB)
1064 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1065 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1066 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1067
1068 return IRQ_HANDLED;
1069}
1070
1071static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1072{
021230d4
AV		 1073 struct ixgbe_q_vector *q_vector = data;
1074 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1075 struct ixgbe_ring *tx_ring;
021230d4
AV		 1076 int i, r_idx;
1077
1078 if (!q_vector->txr_count)
1079 return IRQ_HANDLED;
1080
1081 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1082 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1083 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1084#ifdef CONFIG_IXGBE_DCA
bd0362dd 1085 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1086 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1087#endif
3a581073
JB		 1088 tx_ring->total_bytes = 0;
1089 tx_ring->total_packets = 0;
1090 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1091 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1092 r_idx + 1);
021230d4 1093 }
9a799d71 1094
9a799d71
AK		 1095 return IRQ_HANDLED;
1096}
1097
021230d4
AV		 1098/**
1099 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1100 * @irq: unused
1101 * @data: pointer to our q_vector struct for this interrupt vector
1102 **/
9a799d71
AK		 1103static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1104{
021230d4
AV		 1105 struct ixgbe_q_vector *q_vector = data;
1106 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1107 struct ixgbe_ring *rx_ring;
021230d4 1108 int r_idx;
30efa5a3 1109 int i;
021230d4
AV		 1110
1111 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1112 for (i = 0; i < q_vector->rxr_count; i++) {
1113 rx_ring = &(adapter->rx_ring[r_idx]);
1114 rx_ring->total_bytes = 0;
1115 rx_ring->total_packets = 0;
1116 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1117 r_idx + 1);
1118 }
1119
021230d4
AV		 1120 if (!q_vector->rxr_count)
1121 return IRQ_HANDLED;
1122
30efa5a3 1123 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1124 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1125 /* disable interrupts on this vector only */
3a581073 1126 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
288379f0 1127 napi_schedule(&q_vector->napi);
021230d4
AV		 1128
1129 return IRQ_HANDLED;
1130}
1131
1132static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1133{
1134 ixgbe_msix_clean_rx(irq, data);
1135 ixgbe_msix_clean_tx(irq, data);
9a799d71 1136
9a799d71
AK		 1137 return IRQ_HANDLED;
1138}
1139
021230d4
AV		 1140/**
1141 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1142 * @napi: napi struct with our devices info in it
1143 * @budget: amount of work driver is allowed to do this pass, in packets
1144 *
f0848276
JB		 1145 * This function is optimized for cleaning one queue only on a single
1146 * q_vector!!!
021230d4 1147 **/
9a799d71
AK		 1148static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1149{
021230d4 1150 struct ixgbe_q_vector *q_vector =
b4617240 1151 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1152 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1153 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1154 int work_done = 0;
021230d4 1155 long r_idx;
9a799d71 1156
021230d4 1157 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1158 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1159#ifdef CONFIG_IXGBE_DCA
bd0362dd 1160 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1161 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1162#endif
9a799d71 1163
78b6f4ce 1164 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1165
021230d4
AV		 1166 /* If all Rx work done, exit the polling mode */
1167 if (work_done < budget) {
288379f0 1168 napi_complete(napi);
509ee935 1169 if (adapter->itr_setting & 1)
f494e8fa 1170 ixgbe_set_itr_msix(q_vector);
9a799d71 1171 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1172 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1173 }
1174
1175 return work_done;
1176}
1177
f0848276
JB		 1178/**
1179 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1180 * @napi: napi struct with our devices info in it
1181 * @budget: amount of work driver is allowed to do this pass, in packets
1182 *
1183 * This function will clean more than one rx queue associated with a
1184 * q_vector.
1185 **/
1186static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1187{
1188 struct ixgbe_q_vector *q_vector =
1189 container_of(napi, struct ixgbe_q_vector, napi);
1190 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1191 struct ixgbe_ring *rx_ring = NULL;
1192 int work_done = 0, i;
1193 long r_idx;
1194 u16 enable_mask = 0;
1195
1196 /* attempt to distribute budget to each queue fairly, but don't allow
1197 * the budget to go below 1 because we'll exit polling */
1198 budget /= (q_vector->rxr_count ?: 1);
1199 budget = max(budget, 1);
1200 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1201 for (i = 0; i < q_vector->rxr_count; i++) {
1202 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1203#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1204 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1205 ixgbe_update_rx_dca(adapter, rx_ring);
1206#endif
78b6f4ce 1207 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1208 enable_mask |= rx_ring->v_idx;
1209 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1210 r_idx + 1);
1211 }
1212
1213 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1214 rx_ring = &(adapter->rx_ring[r_idx]);
1215 /* If all Rx work done, exit the polling mode */
7f821875 1216 if (work_done < budget) {
288379f0 1217 napi_complete(napi);
509ee935 1218 if (adapter->itr_setting & 1)
f0848276
JB		 1219 ixgbe_set_itr_msix(q_vector);
1220 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1221 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1222 return 0;
1223 }
1224
1225 return work_done;
1226}
021230d4 1227static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1228 int r_idx)
021230d4
AV		 1229{
1230 a->q_vector[v_idx].adapter = a;
1231 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1232 a->q_vector[v_idx].rxr_count++;
1233 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1234}
1235
1236static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1237 int r_idx)
021230d4
AV		 1238{
1239 a->q_vector[v_idx].adapter = a;
1240 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1241 a->q_vector[v_idx].txr_count++;
1242 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1243}
1244
9a799d71 1245/**
021230d4
AV		 1246 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1247 * @adapter: board private structure to initialize
1248 * @vectors: allotted vector count for descriptor rings
9a799d71 1249 *
021230d4
AV		 1250 * This function maps descriptor rings to the queue-specific vectors
1251 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1252 * one vector per ring/queue, but on a constrained vector budget, we
1253 * group the rings as "efficiently" as possible. You would add new
1254 * mapping configurations in here.
9a799d71 1255 **/
021230d4 1256static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1257 int vectors)
021230d4
AV		 1258{
1259 int v_start = 0;
1260 int rxr_idx = 0, txr_idx = 0;
1261 int rxr_remaining = adapter->num_rx_queues;
1262 int txr_remaining = adapter->num_tx_queues;
1263 int i, j;
1264 int rqpv, tqpv;
1265 int err = 0;
1266
1267 /* No mapping required if MSI-X is disabled. */
1268 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1269 goto out;
9a799d71 1270
021230d4
AV		 1271 /*
1272 * The ideal configuration...
1273 * We have enough vectors to map one per queue.
1274 */
1275 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1276 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1277 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1278
021230d4
AV		 1279 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1280 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1281
9a799d71 1282 goto out;
021230d4 1283 }
9a799d71 1284
021230d4
AV		 1285 /*
1286 * If we don't have enough vectors for a 1-to-1
1287 * mapping, we'll have to group them so there are
1288 * multiple queues per vector.
1289 */
1290 /* Re-adjusting *qpv takes care of the remainder. */
1291 for (i = v_start; i < vectors; i++) {
1292 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1293 for (j = 0; j < rqpv; j++) {
1294 map_vector_to_rxq(adapter, i, rxr_idx);
1295 rxr_idx++;
1296 rxr_remaining--;
1297 }
1298 }
1299 for (i = v_start; i < vectors; i++) {
1300 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1301 for (j = 0; j < tqpv; j++) {
1302 map_vector_to_txq(adapter, i, txr_idx);
1303 txr_idx++;
1304 txr_remaining--;
9a799d71 1305 }
9a799d71
AK		 1306 }
1307
021230d4
AV		 1308out:
1309 return err;
1310}
1311
1312/**
1313 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1314 * @adapter: board private structure
1315 *
1316 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1317 * interrupts from the kernel.
1318 **/
1319static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1320{
1321 struct net_device *netdev = adapter->netdev;
1322 irqreturn_t (*handler)(int, void *);
1323 int i, vector, q_vectors, err;
cb13fc20 1324 int ri=0, ti=0;
021230d4
AV		 1325
1326 /* Decrement for Other and TCP Timer vectors */
1327 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1328
1329 /* Map the Tx/Rx rings to the vectors we were allotted. */
1330 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1331 if (err)
1332 goto out;
1333
1334#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1335 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1336 &ixgbe_msix_clean_many)
021230d4
AV		 1337 for (vector = 0; vector < q_vectors; vector++) {
1338 handler = SET_HANDLER(&adapter->q_vector[vector]);
cb13fc20
RO		 1339
1340 if(handler == &ixgbe_msix_clean_rx) {
1341 sprintf(adapter->name[vector], "%s-%s-%d",
1342 netdev->name, "rx", ri++);
1343 }
1344 else if(handler == &ixgbe_msix_clean_tx) {
1345 sprintf(adapter->name[vector], "%s-%s-%d",
1346 netdev->name, "tx", ti++);
1347 }
1348 else
1349 sprintf(adapter->name[vector], "%s-%s-%d",
1350 netdev->name, "TxRx", vector);
1351
021230d4 1352 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1353 handler, 0, adapter->name[vector],
1354 &(adapter->q_vector[vector]));
9a799d71
AK		 1355 if (err) {
1356 DPRINTK(PROBE, ERR,
b4617240
PW		 1357 "request_irq failed for MSIX interrupt "
1358 "Error: %d\n", err);
021230d4 1359 goto free_queue_irqs;
9a799d71 1360 }
9a799d71
AK		 1361 }
1362
021230d4
AV		 1363 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1364 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1365 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1366 if (err) {
1367 DPRINTK(PROBE, ERR,
1368 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1369 goto free_queue_irqs;
9a799d71
AK		 1370 }
1371
9a799d71
AK		 1372 return 0;
1373
021230d4
AV		 1374free_queue_irqs:
1375 for (i = vector - 1; i >= 0; i--)
1376 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1377 &(adapter->q_vector[i]));
021230d4
AV		 1378 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1379 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1380 kfree(adapter->msix_entries);
1381 adapter->msix_entries = NULL;
021230d4 1382out:
9a799d71
AK		 1383 return err;
1384}
1385
f494e8fa
AV		 1386static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1387{
f494e8fa
AV		 1388 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1389 u8 current_itr;
1390 u32 new_itr = q_vector->eitr;
1391 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1392 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1393
30efa5a3 1394 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1395 q_vector->tx_itr,
1396 tx_ring->total_packets,
1397 tx_ring->total_bytes);
30efa5a3 1398 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1399 q_vector->rx_itr,
1400 rx_ring->total_packets,
1401 rx_ring->total_bytes);
f494e8fa 1402
30efa5a3 1403 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1404
1405 switch (current_itr) {
1406 /* counts and packets in update_itr are dependent on these numbers */
1407 case lowest_latency:
1408 new_itr = 100000;
1409 break;
1410 case low_latency:
1411 new_itr = 20000; /* aka hwitr = ~200 */
1412 break;
1413 case bulk_latency:
1414 new_itr = 8000;
1415 break;
1416 default:
1417 break;
1418 }
1419
1420 if (new_itr != q_vector->eitr) {
1421 u32 itr_reg;
509ee935
JB		 1422
1423 /* save the algorithm value here, not the smoothed one */
1424 q_vector->eitr = new_itr;
f494e8fa
AV		 1425 /* do an exponential smoothing */
1426 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1427 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1428 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1429 }
1430
1431 return;
1432}
1433
79aefa45
AD		 1434/**
1435 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1436 * @adapter: board private structure
1437 **/
1438static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1439{
1440 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
e8e26350
PW		 1441 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1442 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1443 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(2), ~0);
1444 }
79aefa45
AD		 1445 IXGBE_WRITE_FLUSH(&adapter->hw);
1446 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1447 int i;
1448 for (i = 0; i < adapter->num_msix_vectors; i++)
1449 synchronize_irq(adapter->msix_entries[i].vector);
1450 } else {
1451 synchronize_irq(adapter->pdev->irq);
1452 }
1453}
1454
1455/**
1456 * ixgbe_irq_enable - Enable default interrupt generation settings
1457 * @adapter: board private structure
1458 **/
1459static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1460{
1461 u32 mask;
1462 mask = IXGBE_EIMS_ENABLE_MASK;
6ab33d51
DM		 1463 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1464 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350
PW		 1465 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1466 mask |= IXGBE_EIMS_GPI_SDP1;
1467 mask |= IXGBE_EIMS_GPI_SDP2;
1468 }
1469
79aefa45 1470 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
e8e26350
PW		 1471 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1472 /* enable the rest of the queue vectors */
1473 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1),
1474 (IXGBE_EIMS_RTX_QUEUE << 16));
1475 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1476 ((IXGBE_EIMS_RTX_QUEUE << 16) |
1477 IXGBE_EIMS_RTX_QUEUE));
1478 }
79aefa45
AD		 1479 IXGBE_WRITE_FLUSH(&adapter->hw);
1480}
021230d4 1481
9a799d71 1482/**
021230d4 1483 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1484 * @irq: interrupt number
1485 * @data: pointer to a network interface device structure
9a799d71
AK		 1486 **/
1487static irqreturn_t ixgbe_intr(int irq, void *data)
1488{
1489 struct net_device *netdev = data;
1490 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1491 struct ixgbe_hw *hw = &adapter->hw;
1492 u32 eicr;
1493
54037505
DS		 1494 /*
1495 * Workaround for silicon errata. Mask the interrupts
1496 * before the read of EICR.
1497 */
1498 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1499
021230d4
AV		 1500 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1501 * therefore no explict interrupt disable is necessary */
1502 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1503 if (!eicr) {
1504 /* shared interrupt alert!
1505 * make sure interrupts are enabled because the read will
1506 * have disabled interrupts due to EIAM */
1507 ixgbe_irq_enable(adapter);
9a799d71 1508 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1509 }
9a799d71 1510
cf8280ee
JB		 1511 if (eicr & IXGBE_EICR_LSC)
1512 ixgbe_check_lsc(adapter);
021230d4 1513
e8e26350
PW		 1514 if (hw->mac.type == ixgbe_mac_82599EB)
1515 ixgbe_check_sfp_event(adapter, eicr);
1516
0befdb3e
JB		 1517 ixgbe_check_fan_failure(adapter, eicr);
1518
288379f0 1519 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
f494e8fa
AV		 1520 adapter->tx_ring[0].total_packets = 0;
1521 adapter->tx_ring[0].total_bytes = 0;
1522 adapter->rx_ring[0].total_packets = 0;
1523 adapter->rx_ring[0].total_bytes = 0;
021230d4 1524 /* would disable interrupts here but EIAM disabled it */
288379f0 1525 __napi_schedule(&adapter->q_vector[0].napi);
9a799d71
AK		 1526 }
1527
1528 return IRQ_HANDLED;
1529}
1530
021230d4
AV		 1531static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1532{
1533 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1534
1535 for (i = 0; i < q_vectors; i++) {
1536 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1537 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1538 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1539 q_vector->rxr_count = 0;
1540 q_vector->txr_count = 0;
1541 }
1542}
1543
9a799d71
AK		 1544/**
1545 * ixgbe_request_irq - initialize interrupts
1546 * @adapter: board private structure
1547 *
1548 * Attempts to configure interrupts using the best available
1549 * capabilities of the hardware and kernel.
1550 **/
021230d4 1551static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1552{
1553 struct net_device *netdev = adapter->netdev;
021230d4 1554 int err;
9a799d71 1555
021230d4
AV		 1556 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1557 err = ixgbe_request_msix_irqs(adapter);
1558 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1559 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1560 netdev->name, netdev);
021230d4
AV		 1561 } else {
1562 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1563 netdev->name, netdev);
9a799d71
AK		 1564 }
1565
9a799d71
AK		 1566 if (err)
1567 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1568
9a799d71
AK		 1569 return err;
1570}
1571
1572static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1573{
1574 struct net_device *netdev = adapter->netdev;
1575
1576 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1577 int i, q_vectors;
9a799d71 1578
021230d4
AV		 1579 q_vectors = adapter->num_msix_vectors;
1580
1581 i = q_vectors - 1;
9a799d71 1582 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1583
021230d4
AV		 1584 i--;
1585 for (; i >= 0; i--) {
1586 free_irq(adapter->msix_entries[i].vector,
b4617240 1587 &(adapter->q_vector[i]));
021230d4
AV		 1588 }
1589
1590 ixgbe_reset_q_vectors(adapter);
1591 } else {
1592 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1593 }
1594}
1595
9a799d71
AK		 1596/**
1597 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1598 *
1599 **/
1600static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1601{
9a799d71
AK		 1602 struct ixgbe_hw *hw = &adapter->hw;
1603
021230d4 1604 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1605 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1606
e8e26350
PW		 1607 ixgbe_set_ivar(adapter, 0, 0, 0);
1608 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1609
1610 map_vector_to_rxq(adapter, 0, 0);
1611 map_vector_to_txq(adapter, 0, 0);
1612
1613 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1614}
1615
1616/**
3a581073 1617 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1618 * @adapter: board private structure
1619 *
1620 * Configure the Tx unit of the MAC after a reset.
1621 **/
1622static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1623{
12207e49 1624 u64 tdba;
9a799d71 1625 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1626 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1627
1628 /* Setup the HW Tx Head and Tail descriptor pointers */
1629 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1630 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1631 j = ring->reg_idx;
1632 tdba = ring->dma;
1633 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1634 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1635 (tdba & DMA_32BIT_MASK));
021230d4
AV		 1636 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1637 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1638 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1639 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1640 adapter->tx_ring[i].head = IXGBE_TDH(j);
1641 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1642 /* Disable Tx Head Writeback RO bit, since this hoses
1643 * bookkeeping if things aren't delivered in order.
1644 */
e01c31a5 1645 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1646 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1647 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1648 }
e8e26350
PW		 1649 if (hw->mac.type == ixgbe_mac_82599EB) {
1650 /* We enable 8 traffic classes, DCB only */
1651 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1652 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1653 IXGBE_MTQC_8TC_8TQ));
1654 }
9a799d71
AK		 1655}
1656
e8e26350 1657#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1658
1659static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1660{
1661 struct ixgbe_ring *rx_ring;
1662 u32 srrctl;
e8e26350 1663 int queue0 = 0;
3be1adfb
AD		 1664 unsigned long mask;
1665
e8e26350
PW		 1666 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1667 queue0 = index;
cc41ac7c 1668 } else {
3be1adfb
AD		 1669 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1670 queue0 = index & mask;
1671 index = index & mask;
cc41ac7c 1672 }
3be1adfb 1673
cc41ac7c
JB		 1674 rx_ring = &adapter->rx_ring[queue0];
1675
1676 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1677
1678 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1679 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1680
1681 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
32344a39
JB		 1682 u16 bufsz = IXGBE_RXBUFFER_2048;
1683 /* grow the amount we can receive on large page machines */
1684 if (bufsz < (PAGE_SIZE / 2))
1685 bufsz = (PAGE_SIZE / 2);
1686 /* cap the bufsz at our largest descriptor size */
1687 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1688
1689 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c
JB		 1690 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1691 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1692 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1693 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1694 } else {
1695 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1696
1697 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1698 srrctl |= IXGBE_RXBUFFER_2048 >>
1699 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1700 else
1701 srrctl |= rx_ring->rx_buf_len >>
1702 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1703 }
e8e26350 1704
cc41ac7c
JB		 1705 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1706}
9a799d71 1707
9a799d71 1708/**
3a581073 1709 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1710 * @adapter: board private structure
1711 *
1712 * Configure the Rx unit of the MAC after a reset.
1713 **/
1714static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1715{
1716 u64 rdba;
1717 struct ixgbe_hw *hw = &adapter->hw;
1718 struct net_device *netdev = adapter->netdev;
1719 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1720 int i, j;
9a799d71 1721 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1722 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1723 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1724 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1725 u32 fctrl, hlreg0;
509ee935 1726 u32 reta = 0, mrqc = 0;
cc41ac7c 1727 u32 rdrxctl;
7c6e0a43 1728 int rx_buf_len;
9a799d71
AK		 1729
1730 /* Decide whether to use packet split mode or not */
762f4c57 1731 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1732
1733 /* Set the RX buffer length according to the mode */
1734 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1735 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1736 if (hw->mac.type == ixgbe_mac_82599EB) {
1737 /* PSRTYPE must be initialized in 82599 */
1738 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1739 IXGBE_PSRTYPE_UDPHDR |
1740 IXGBE_PSRTYPE_IPV4HDR |
1741 IXGBE_PSRTYPE_IPV6HDR;
1742 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1743 }
9a799d71
AK		 1744 } else {
1745 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1746 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1747 else
7c6e0a43 1748 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1749 }
1750
1751 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1752 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1753 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1754 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1755 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1756
1757 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1758 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1759 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1760 else
1761 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1762 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1763
9a799d71
AK		 1764 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1765 /* disable receives while setting up the descriptors */
1766 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1767 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1768
1769 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1770 * the Base and Length of the Rx Descriptor Ring */
1771 for (i = 0; i < adapter->num_rx_queues; i++) {
1772 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1773 j = adapter->rx_ring[i].reg_idx;
1774 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1775 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1776 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1777 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1778 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1779 adapter->rx_ring[i].head = IXGBE_RDH(j);
1780 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1781 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c
JB		 1782
1783 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1784 }
1785
e8e26350
PW		 1786 if (hw->mac.type == ixgbe_mac_82598EB) {
1787 /*
1788 * For VMDq support of different descriptor types or
1789 * buffer sizes through the use of multiple SRRCTL
1790 * registers, RDRXCTL.MVMEN must be set to 1
1791 *
1792 * also, the manual doesn't mention it clearly but DCA hints
1793 * will only use queue 0's tags unless this bit is set. Side
1794 * effects of setting this bit are only that SRRCTL must be
1795 * fully programmed [0..15]
1796 */
1797 if (adapter->flags &
1798 (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) {
1799 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1800 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1801 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1802 }
2f90b865 1803 }
177db6ff 1804
e8e26350
PW		 1805 /* Program MRQC for the distribution of queues */
1806 if (hw->mac.type == ixgbe_mac_82599EB) {
1807 int mask = adapter->flags & (
1808 IXGBE_FLAG_RSS_ENABLED
1809 | IXGBE_FLAG_DCB_ENABLED
1810 );
1811
1812 switch (mask) {
1813 case (IXGBE_FLAG_RSS_ENABLED):
1814 mrqc = IXGBE_MRQC_RSSEN;
1815 break;
1816 case (IXGBE_FLAG_DCB_ENABLED):
1817 mrqc = IXGBE_MRQC_RT8TCEN;
1818 break;
1819 default:
1820 break;
1821 }
1822 }
021230d4 1823 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1824 /* Fill out redirection table */
021230d4
AV		 1825 for (i = 0, j = 0; i < 128; i++, j++) {
1826 if (j == adapter->ring_feature[RING_F_RSS].indices)
1827 j = 0;
1828 /* reta = 4-byte sliding window of
1829 * 0x00..(indices-1)(indices-1)00..etc. */
1830 reta = (reta << 8) | (j * 0x11);
1831 if ((i & 3) == 3)
1832 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1833 }
1834
1835 /* Fill out hash function seeds */
1836 for (i = 0; i < 10; i++)
7c6e0a43 1837 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1838
1839 mrqc = IXGBE_MRQC_RSSEN
1840 /* Perform hash on these packet types */
7c6e0a43
JB		 1841 | IXGBE_MRQC_RSS_FIELD_IPV4
1842 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1843 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
7c6e0a43
JB		 1844 | IXGBE_MRQC_RSS_FIELD_IPV6
1845 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
e8e26350 1846 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
9a799d71 1847 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1848 }
9a799d71 1849
021230d4
AV		 1850 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1851
1852 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1853 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1854 /* Disable indicating checksum in descriptor, enables
1855 * RSS hash */
9a799d71 1856 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1857 }
021230d4
AV		 1858 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1859 /* Enable IPv4 payload checksum for UDP fragments
1860 * if PCSD is not set */
1861 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1862 }
1863
1864 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 1865
1866 if (hw->mac.type == ixgbe_mac_82599EB) {
1867 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1868 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1869 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1870 }
9a799d71
AK		 1871}
1872
068c89b0
DS		 1873static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1874{
1875 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1876 struct ixgbe_hw *hw = &adapter->hw;
1877
1878 /* add VID to filter table */
1879 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1880}
1881
1882static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1883{
1884 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1885 struct ixgbe_hw *hw = &adapter->hw;
1886
1887 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1888 ixgbe_irq_disable(adapter);
1889
1890 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1891
1892 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1893 ixgbe_irq_enable(adapter);
1894
1895 /* remove VID from filter table */
1896 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1897}
1898
9a799d71 1899static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1900 struct vlan_group *grp)
9a799d71
AK		 1901{
1902 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1903 u32 ctrl;
e8e26350 1904 int i, j;
9a799d71 1905
d4f80882
AV		 1906 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1907 ixgbe_irq_disable(adapter);
9a799d71
AK		 1908 adapter->vlgrp = grp;
1909
2f90b865
AD		 1910 /*
1911 * For a DCB driver, always enable VLAN tag stripping so we can
1912 * still receive traffic from a DCB-enabled host even if we're
1913 * not in DCB mode.
1914 */
1915 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 1916 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1917 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1918 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1919 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1920 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1921 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 1922 /* enable VLAN tag insert/strip */
1923 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 1924 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1925 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 1926 for (i = 0; i < adapter->num_rx_queues; i++) {
1927 j = adapter->rx_ring[i].reg_idx;
1928 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
1929 ctrl |= IXGBE_RXDCTL_VME;
1930 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
1931 }
9a799d71 1932 }
e8e26350 1933 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 1934
d4f80882
AV		 1935 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1936 ixgbe_irq_enable(adapter);
9a799d71
AK		 1937}
1938
9a799d71
AK		 1939static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1940{
1941 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1942
1943 if (adapter->vlgrp) {
1944 u16 vid;
1945 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1946 if (!vlan_group_get_device(adapter->vlgrp, vid))
1947 continue;
1948 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1949 }
1950 }
1951}
1952
2c5645cf
CL		 1953static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1954{
1955 struct dev_mc_list *mc_ptr;
1956 u8 *addr = *mc_addr_ptr;
1957 *vmdq = 0;
1958
1959 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1960 if (mc_ptr->next)
1961 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1962 else
1963 *mc_addr_ptr = NULL;
1964
1965 return addr;
1966}
1967
9a799d71 1968/**
2c5645cf 1969 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1970 * @netdev: network interface device structure
1971 *
2c5645cf
CL		 1972 * The set_rx_method entry point is called whenever the unicast/multicast
1973 * address list or the network interface flags are updated. This routine is
1974 * responsible for configuring the hardware for proper unicast, multicast and
1975 * promiscuous mode.
9a799d71 1976 **/
2c5645cf 1977static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1978{
1979 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1980 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1981 u32 fctrl, vlnctrl;
2c5645cf
CL		 1982 u8 *addr_list = NULL;
1983 int addr_count = 0;
9a799d71
AK		 1984
1985 /* Check for Promiscuous and All Multicast modes */
1986
1987 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1988 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1989
1990 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1991 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1992 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1993 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1994 } else {
746b9f02
PM		 1995 if (netdev->flags & IFF_ALLMULTI) {
1996 fctrl |= IXGBE_FCTRL_MPE;
1997 fctrl &= ~IXGBE_FCTRL_UPE;
1998 } else {
1999 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2000 }
3d01625a 2001 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2002 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2003 }
2004
2005 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2006 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2007
2c5645cf
CL		 2008 /* reprogram secondary unicast list */
2009 addr_count = netdev->uc_count;
2010 if (addr_count)
2011 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2012 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2013 ixgbe_addr_list_itr);
9a799d71 2014
2c5645cf
CL		 2015 /* reprogram multicast list */
2016 addr_count = netdev->mc_count;
2017 if (addr_count)
2018 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2019 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2020 ixgbe_addr_list_itr);
9a799d71
AK		 2021}
2022
021230d4
AV		 2023static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2024{
2025 int q_idx;
2026 struct ixgbe_q_vector *q_vector;
2027 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2028
2029 /* legacy and MSI only use one vector */
2030 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2031 q_vectors = 1;
2032
2033 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2034 struct napi_struct *napi;
021230d4
AV		 2035 q_vector = &adapter->q_vector[q_idx];
2036 if (!q_vector->rxr_count)
2037 continue;
f0848276
JB		 2038 napi = &q_vector->napi;
2039 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2040 (q_vector->rxr_count > 1))
2041 napi->poll = &ixgbe_clean_rxonly_many;
2042
2043 napi_enable(napi);
021230d4
AV		 2044 }
2045}
2046
2047static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2048{
2049 int q_idx;
2050 struct ixgbe_q_vector *q_vector;
2051 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2052
2053 /* legacy and MSI only use one vector */
2054 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2055 q_vectors = 1;
2056
2057 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2058 q_vector = &adapter->q_vector[q_idx];
2059 if (!q_vector->rxr_count)
2060 continue;
2061 napi_disable(&q_vector->napi);
2062 }
2063}
2064
7a6b6f51 2065#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2066/*
2067 * ixgbe_configure_dcb - Configure DCB hardware
2068 * @adapter: ixgbe adapter struct
2069 *
2070 * This is called by the driver on open to configure the DCB hardware.
2071 * This is also called by the gennetlink interface when reconfiguring
2072 * the DCB state.
2073 */
2074static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2075{
2076 struct ixgbe_hw *hw = &adapter->hw;
2077 u32 txdctl, vlnctrl;
2078 int i, j;
2079
2080 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2081 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2082 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2083
2084 /* reconfigure the hardware */
2085 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2086
2087 for (i = 0; i < adapter->num_tx_queues; i++) {
2088 j = adapter->tx_ring[i].reg_idx;
2089 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2090 /* PThresh workaround for Tx hang with DFP enabled. */
2091 txdctl |= 32;
2092 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2093 }
2094 /* Enable VLAN tag insert/strip */
2095 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2096 if (hw->mac.type == ixgbe_mac_82598EB) {
2097 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2098 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2099 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2100 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2101 vlnctrl |= IXGBE_VLNCTRL_VFE;
2102 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2103 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2104 for (i = 0; i < adapter->num_rx_queues; i++) {
2105 j = adapter->rx_ring[i].reg_idx;
2106 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2107 vlnctrl |= IXGBE_RXDCTL_VME;
2108 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2109 }
2110 }
2f90b865
AD		 2111 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2112}
2113
2114#endif
9a799d71
AK		 2115static void ixgbe_configure(struct ixgbe_adapter *adapter)
2116{
2117 struct net_device *netdev = adapter->netdev;
2118 int i;
2119
2c5645cf 2120 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2121
2122 ixgbe_restore_vlan(adapter);
7a6b6f51 2123#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2124 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2125 netif_set_gso_max_size(netdev, 32768);
2126 ixgbe_configure_dcb(adapter);
2127 } else {
2128 netif_set_gso_max_size(netdev, 65536);
2129 }
2130#else
2131 netif_set_gso_max_size(netdev, 65536);
2132#endif
9a799d71
AK		 2133
2134 ixgbe_configure_tx(adapter);
2135 ixgbe_configure_rx(adapter);
2136 for (i = 0; i < adapter->num_rx_queues; i++)
2137 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2138 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2139}
2140
e8e26350
PW		 2141static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2142{
2143 switch (hw->phy.type) {
2144 case ixgbe_phy_sfp_avago:
2145 case ixgbe_phy_sfp_ftl:
2146 case ixgbe_phy_sfp_intel:
2147 case ixgbe_phy_sfp_unknown:
2148 case ixgbe_phy_tw_tyco:
2149 case ixgbe_phy_tw_unknown:
2150 return true;
2151 default:
2152 return false;
2153 }
2154}
2155
0ecc061d 2156/**
e8e26350
PW		 2157 * ixgbe_sfp_link_config - set up SFP+ link
2158 * @adapter: pointer to private adapter struct
2159 **/
2160static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2161{
2162 struct ixgbe_hw *hw = &adapter->hw;
2163
2164 if (hw->phy.multispeed_fiber) {
2165 /*
2166 * In multispeed fiber setups, the device may not have
2167 * had a physical connection when the driver loaded.
2168 * If that's the case, the initial link configuration
2169 * couldn't get the MAC into 10G or 1G mode, so we'll
2170 * never have a link status change interrupt fire.
2171 * We need to try and force an autonegotiation
2172 * session, then bring up link.
2173 */
2174 hw->mac.ops.setup_sfp(hw);
2175 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2176 schedule_work(&adapter->multispeed_fiber_task);
2177 } else {
2178 /*
2179 * Direct Attach Cu and non-multispeed fiber modules
2180 * still need to be configured properly prior to
2181 * attempting link.
2182 */
2183 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2184 schedule_work(&adapter->sfp_config_module_task);
2185 }
2186}
2187
2188/**
2189 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2190 * @hw: pointer to private hardware struct
2191 *
2192 * Returns 0 on success, negative on failure
2193 **/
e8e26350 2194static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2195{
2196 u32 autoneg;
2197 bool link_up = false;
2198 u32 ret = IXGBE_ERR_LINK_SETUP;
2199
2200 if (hw->mac.ops.check_link)
2201 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2202
2203 if (ret)
2204 goto link_cfg_out;
2205
2206 if (hw->mac.ops.get_link_capabilities)
2207 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2208 &hw->mac.autoneg);
2209 if (ret)
2210 goto link_cfg_out;
2211
2212 if (hw->mac.ops.setup_link_speed)
2213 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2214link_cfg_out:
2215 return ret;
2216}
2217
e8e26350
PW		 2218#define IXGBE_MAX_RX_DESC_POLL 10
2219static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2220 int rxr)
2221{
2222 int j = adapter->rx_ring[rxr].reg_idx;
2223 int k;
2224
2225 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2226 if (IXGBE_READ_REG(&adapter->hw,
2227 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2228 break;
2229 else
2230 msleep(1);
2231 }
2232 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2233 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2234 "not set within the polling period\n", rxr);
2235 }
2236 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2237 (adapter->rx_ring[rxr].count - 1));
2238}
2239
9a799d71
AK		 2240static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2241{
2242 struct net_device *netdev = adapter->netdev;
9a799d71 2243 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2244 int i, j = 0;
e8e26350 2245 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2246 int err;
9a799d71 2247 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2248 u32 txdctl, rxdctl, mhadd;
e8e26350 2249 u32 dmatxctl;
021230d4 2250 u32 gpie;
9a799d71 2251
5eba3699
AV		 2252 ixgbe_get_hw_control(adapter);
2253
021230d4
AV		 2254 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2255 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2256 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2257 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2258 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2259 } else {
2260 /* MSI only */
021230d4 2261 gpie = 0;
9a799d71 2262 }
021230d4
AV		 2263 /* XXX: to interrupt immediately for EICS writes, enable this */
2264 /* gpie |= IXGBE_GPIE_EIMEN; */
2265 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2266 }
2267
021230d4
AV		 2268 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2269 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2270 * specifically only auto mask tx and rx interrupts */
2271 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2272 }
9a799d71 2273
0befdb3e
JB		 2274 /* Enable fan failure interrupt if media type is copper */
2275 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2276 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2277 gpie |= IXGBE_SDP1_GPIEN;
2278 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2279 }
2280
e8e26350
PW		 2281 if (hw->mac.type == ixgbe_mac_82599EB) {
2282 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2283 gpie |= IXGBE_SDP1_GPIEN;
2284 gpie |= IXGBE_SDP2_GPIEN;
2285 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2286 }
2287
021230d4 2288 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2289 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2290 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2291 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2292
2293 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2294 }
2295
2296 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2297 j = adapter->tx_ring[i].reg_idx;
2298 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2299 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2300 txdctl |= (8 << 16);
e8e26350
PW		 2301 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2302 }
2303
2304 if (hw->mac.type == ixgbe_mac_82599EB) {
2305 /* DMATXCTL.EN must be set after all Tx queue config is done */
2306 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2307 dmatxctl |= IXGBE_DMATXCTL_TE;
2308 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2309 }
2310 for (i = 0; i < adapter->num_tx_queues; i++) {
2311 j = adapter->tx_ring[i].reg_idx;
2312 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2313 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2314 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2315 }
2316
e8e26350 2317 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2318 j = adapter->rx_ring[i].reg_idx;
2319 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2320 /* enable PTHRESH=32 descriptors (half the internal cache)
2321 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2322 * this also removes a pesky rx_no_buffer_count increment */
2323 rxdctl |= 0x0020;
9a799d71 2324 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2325 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2326 if (hw->mac.type == ixgbe_mac_82599EB)
2327 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2328 }
2329 /* enable all receives */
2330 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2331 if (hw->mac.type == ixgbe_mac_82598EB)
2332 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2333 else
2334 rxdctl |= IXGBE_RXCTRL_RXEN;
2335 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2336
2337 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2338 ixgbe_configure_msix(adapter);
2339 else
2340 ixgbe_configure_msi_and_legacy(adapter);
2341
7adf1525
PWJ		 2342 ixgbe_napi_add_all(adapter);
2343
9a799d71 2344 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2345 ixgbe_napi_enable_all(adapter);
2346
2347 /* clear any pending interrupts, may auto mask */
2348 IXGBE_READ_REG(hw, IXGBE_EICR);
2349
9a799d71
AK		 2350 ixgbe_irq_enable(adapter);
2351
e8e26350
PW		 2352 /*
2353 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2354 * arrived before interrupts were enabled. We need to kick off
2355 * the SFP+ module setup first, then try to bring up link.
2356 * If we're not hot-pluggable SFP+, we just need to configure link
2357 * and bring it up.
2358 */
2359 err = hw->phy.ops.identify(hw);
2360 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2361 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2362 ixgbe_down(adapter);
2363 return err;
2364 }
2365
2366 if (ixgbe_is_sfp(hw)) {
2367 ixgbe_sfp_link_config(adapter);
2368 } else {
2369 err = ixgbe_non_sfp_link_config(hw);
2370 if (err)
2371 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2372 }
0ecc061d 2373
1da100bb
PWJ		 2374 /* enable transmits */
2375 netif_tx_start_all_queues(netdev);
2376
9a799d71
AK		 2377 /* bring the link up in the watchdog, this could race with our first
2378 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2379 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2380 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2381 mod_timer(&adapter->watchdog_timer, jiffies);
2382 return 0;
2383}
2384
d4f80882
AV		 2385void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2386{
2387 WARN_ON(in_interrupt());
2388 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2389 msleep(1);
2390 ixgbe_down(adapter);
2391 ixgbe_up(adapter);
2392 clear_bit(__IXGBE_RESETTING, &adapter->state);
2393}
2394
9a799d71
AK		 2395int ixgbe_up(struct ixgbe_adapter *adapter)
2396{
2397 /* hardware has been reset, we need to reload some things */
2398 ixgbe_configure(adapter);
2399
2400 return ixgbe_up_complete(adapter);
2401}
2402
2403void ixgbe_reset(struct ixgbe_adapter *adapter)
2404{
c44ade9e
JB		 2405 struct ixgbe_hw *hw = &adapter->hw;
2406 if (hw->mac.ops.init_hw(hw))
2407 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2408
2409 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2410 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2411
2412}
2413
9a799d71
AK		 2414/**
2415 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2416 * @adapter: board private structure
2417 * @rx_ring: ring to free buffers from
2418 **/
2419static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2420 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2421{
2422 struct pci_dev *pdev = adapter->pdev;
2423 unsigned long size;
2424 unsigned int i;
2425
2426 /* Free all the Rx ring sk_buffs */
2427
2428 for (i = 0; i < rx_ring->count; i++) {
2429 struct ixgbe_rx_buffer *rx_buffer_info;
2430
2431 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2432 if (rx_buffer_info->dma) {
2433 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2434 rx_ring->rx_buf_len,
2435 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2436 rx_buffer_info->dma = 0;
2437 }
2438 if (rx_buffer_info->skb) {
2439 dev_kfree_skb(rx_buffer_info->skb);
2440 rx_buffer_info->skb = NULL;
2441 }
2442 if (!rx_buffer_info->page)
2443 continue;
762f4c57
JB		 2444 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2445 PCI_DMA_FROMDEVICE);
9a799d71 2446 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2447 put_page(rx_buffer_info->page);
2448 rx_buffer_info->page = NULL;
762f4c57 2449 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2450 }
2451
2452 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2453 memset(rx_ring->rx_buffer_info, 0, size);
2454
2455 /* Zero out the descriptor ring */
2456 memset(rx_ring->desc, 0, rx_ring->size);
2457
2458 rx_ring->next_to_clean = 0;
2459 rx_ring->next_to_use = 0;
2460
2461 writel(0, adapter->hw.hw_addr + rx_ring->head);
2462 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2463}
2464
2465/**
2466 * ixgbe_clean_tx_ring - Free Tx Buffers
2467 * @adapter: board private structure
2468 * @tx_ring: ring to be cleaned
2469 **/
2470static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2471 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2472{
2473 struct ixgbe_tx_buffer *tx_buffer_info;
2474 unsigned long size;
2475 unsigned int i;
2476
2477 /* Free all the Tx ring sk_buffs */
2478
2479 for (i = 0; i < tx_ring->count; i++) {
2480 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2481 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2482 }
2483
2484 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2485 memset(tx_ring->tx_buffer_info, 0, size);
2486
2487 /* Zero out the descriptor ring */
2488 memset(tx_ring->desc, 0, tx_ring->size);
2489
2490 tx_ring->next_to_use = 0;
2491 tx_ring->next_to_clean = 0;
2492
2493 writel(0, adapter->hw.hw_addr + tx_ring->head);
2494 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2495}
2496
2497/**
021230d4 2498 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2499 * @adapter: board private structure
2500 **/
021230d4 2501static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2502{
2503 int i;
2504
021230d4
AV		 2505 for (i = 0; i < adapter->num_rx_queues; i++)
2506 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2507}
2508
2509/**
021230d4 2510 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2511 * @adapter: board private structure
2512 **/
021230d4 2513static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2514{
2515 int i;
2516
021230d4
AV		 2517 for (i = 0; i < adapter->num_tx_queues; i++)
2518 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2519}
2520
2521void ixgbe_down(struct ixgbe_adapter *adapter)
2522{
2523 struct net_device *netdev = adapter->netdev;
7f821875 2524 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2525 u32 rxctrl;
7f821875
JB		 2526 u32 txdctl;
2527 int i, j;
9a799d71
AK		 2528
2529 /* signal that we are down to the interrupt handler */
2530 set_bit(__IXGBE_DOWN, &adapter->state);
2531
2532 /* disable receives */
7f821875
JB		 2533 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2534 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2535
2536 netif_tx_disable(netdev);
2537
7f821875 2538 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2539 msleep(10);
2540
7f821875
JB		 2541 netif_tx_stop_all_queues(netdev);
2542
9a799d71
AK		 2543 ixgbe_irq_disable(adapter);
2544
021230d4 2545 ixgbe_napi_disable_all(adapter);
7f821875 2546
9a799d71 2547 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2548 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2549
7f821875
JB		 2550 /* disable transmits in the hardware now that interrupts are off */
2551 for (i = 0; i < adapter->num_tx_queues; i++) {
2552 j = adapter->tx_ring[i].reg_idx;
2553 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2554 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2555 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2556 }
2557
9a799d71 2558 netif_carrier_off(netdev);
9a799d71 2559
5dd2d332 2560#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2561 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2562 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2563 dca_remove_requester(&adapter->pdev->dev);
2564 }
2565
2566#endif
6f4a0e45
PL		 2567 if (!pci_channel_offline(adapter->pdev))
2568 ixgbe_reset(adapter);
9a799d71
AK		 2569 ixgbe_clean_all_tx_rings(adapter);
2570 ixgbe_clean_all_rx_rings(adapter);
2571
5dd2d332 2572#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2573 /* since we reset the hardware DCA settings were cleared */
2574 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2575 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2576 /* always use CB2 mode, difference is masked
2577 * in the CB driver */
b4617240 2578 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2579 ixgbe_setup_dca(adapter);
2580 }
2581#endif
9a799d71
AK		 2582}
2583
9a799d71 2584/**
021230d4
AV		 2585 * ixgbe_poll - NAPI Rx polling callback
2586 * @napi: structure for representing this polling device
2587 * @budget: how many packets driver is allowed to clean
2588 *
2589 * This function is used for legacy and MSI, NAPI mode
9a799d71 2590 **/
021230d4 2591static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2592{
021230d4 2593 struct ixgbe_q_vector *q_vector = container_of(napi,
b4617240 2594 struct ixgbe_q_vector, napi);
021230d4 2595 struct ixgbe_adapter *adapter = q_vector->adapter;
74ce8dd2 2596 int tx_cleaned, work_done = 0;
9a799d71 2597
5dd2d332 2598#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2599 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2600 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2601 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2602 }
2603#endif
2604
d2c7ddd6 2605 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2606 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2607
d2c7ddd6
DM		 2608 if (tx_cleaned)
2609 work_done = budget;
2610
53e52c72
DM		 2611 /* If budget not fully consumed, exit the polling mode */
2612 if (work_done < budget) {
288379f0 2613 napi_complete(napi);
509ee935 2614 if (adapter->itr_setting & 1)
f494e8fa 2615 ixgbe_set_itr(adapter);
d4f80882
AV		 2616 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2617 ixgbe_irq_enable(adapter);
9a799d71 2618 }
9a799d71
AK		 2619 return work_done;
2620}
2621
2622/**
2623 * ixgbe_tx_timeout - Respond to a Tx Hang
2624 * @netdev: network interface device structure
2625 **/
2626static void ixgbe_tx_timeout(struct net_device *netdev)
2627{
2628 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2629
2630 /* Do the reset outside of interrupt context */
2631 schedule_work(&adapter->reset_task);
2632}
2633
2634static void ixgbe_reset_task(struct work_struct *work)
2635{
2636 struct ixgbe_adapter *adapter;
2637 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2638
2f90b865
AD		 2639 /* If we're already down or resetting, just bail */
2640 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2641 test_bit(__IXGBE_RESETTING, &adapter->state))
2642 return;
2643
9a799d71
AK		 2644 adapter->tx_timeout_count++;
2645
d4f80882 2646 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2647}
2648
bc97114d
PWJ		 2649#ifdef CONFIG_IXGBE_DCB
2650static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2651{
bc97114d 2652 bool ret = false;
b9804972 2653
bc97114d
PWJ		 2654 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2655 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2656 adapter->num_rx_queues =
2657 adapter->ring_feature[RING_F_DCB].indices;
2658 adapter->num_tx_queues =
2659 adapter->ring_feature[RING_F_DCB].indices;
2660 ret = true;
2661 } else {
bc97114d
PWJ		 2662 ret = false;
2663 }
2f90b865 2664
bc97114d
PWJ		 2665 return ret;
2666}
2667#endif
2668
2669static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2670{
2671 bool ret = false;
2672
2673 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2674 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2675 adapter->num_rx_queues =
2676 adapter->ring_feature[RING_F_RSS].indices;
2677 adapter->num_tx_queues =
2678 adapter->ring_feature[RING_F_RSS].indices;
2679 ret = true;
2680 } else {
bc97114d 2681 ret = false;
b9804972
JB		 2682 }
2683
bc97114d
PWJ		 2684 return ret;
2685}
2686
2687static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2688{
2689 /* Start with base case */
2690 adapter->num_rx_queues = 1;
2691 adapter->num_tx_queues = 1;
2692
2693#ifdef CONFIG_IXGBE_DCB
2694 if (ixgbe_set_dcb_queues(adapter))
2695 return;
2696
2697#endif
2698 if (ixgbe_set_rss_queues(adapter))
2699 return;
b9804972
JB		 2700}
2701
021230d4 2702static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2703 int vectors)
021230d4
AV		 2704{
2705 int err, vector_threshold;
2706
2707 /* We'll want at least 3 (vector_threshold):
2708 * 1) TxQ[0] Cleanup
2709 * 2) RxQ[0] Cleanup
2710 * 3) Other (Link Status Change, etc.)
2711 * 4) TCP Timer (optional)
2712 */
2713 vector_threshold = MIN_MSIX_COUNT;
2714
2715 /* The more we get, the more we will assign to Tx/Rx Cleanup
2716 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2717 * Right now, we simply care about how many we'll get; we'll
2718 * set them up later while requesting irq's.
2719 */
2720 while (vectors >= vector_threshold) {
2721 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2722 vectors);
021230d4
AV		 2723 if (!err) /* Success in acquiring all requested vectors. */
2724 break;
2725 else if (err < 0)
2726 vectors = 0; /* Nasty failure, quit now */
2727 else /* err == number of vectors we should try again with */
2728 vectors = err;
2729 }
2730
2731 if (vectors < vector_threshold) {
2732 /* Can't allocate enough MSI-X interrupts? Oh well.
2733 * This just means we'll go with either a single MSI
2734 * vector or fall back to legacy interrupts.
2735 */
2736 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2737 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2738 kfree(adapter->msix_entries);
2739 adapter->msix_entries = NULL;
2f90b865 2740 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4 2741 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2742 ixgbe_set_num_queues(adapter);
021230d4
AV		 2743 } else {
2744 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 2745 /*
2746 * Adjust for only the vectors we'll use, which is minimum
2747 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2748 * vectors we were allocated.
2749 */
2750 adapter->num_msix_vectors = min(vectors,
2751 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 2752 }
2753}
2754
021230d4 2755/**
bc97114d 2756 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 2757 * @adapter: board private structure to initialize
2758 *
bc97114d
PWJ		 2759 * Cache the descriptor ring offsets for RSS to the assigned rings.
2760 *
021230d4 2761 **/
bc97114d 2762static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 2763{
bc97114d
PWJ		 2764 int i;
2765 bool ret = false;
2766
2767 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2768 for (i = 0; i < adapter->num_rx_queues; i++)
2769 adapter->rx_ring[i].reg_idx = i;
2770 for (i = 0; i < adapter->num_tx_queues; i++)
2771 adapter->tx_ring[i].reg_idx = i;
2772 ret = true;
2773 } else {
2774 ret = false;
2775 }
2776
2777 return ret;
2778}
2779
2780#ifdef CONFIG_IXGBE_DCB
2781/**
2782 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2783 * @adapter: board private structure to initialize
2784 *
2785 * Cache the descriptor ring offsets for DCB to the assigned rings.
2786 *
2787 **/
2788static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2789{
2790 int i;
2791 bool ret = false;
2792 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2793
2794 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2795 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 2796 /* the number of queues is assumed to be symmetric */
2797 for (i = 0; i < dcb_i; i++) {
2798 adapter->rx_ring[i].reg_idx = i << 3;
2799 adapter->tx_ring[i].reg_idx = i << 2;
2800 }
bc97114d 2801 ret = true;
e8e26350
PW		 2802 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2803 for (i = 0; i < dcb_i; i++) {
2804 adapter->rx_ring[i].reg_idx = i << 4;
2805 adapter->tx_ring[i].reg_idx = i << 4;
2806 }
2807 ret = true;
bc97114d
PWJ		 2808 } else {
2809 ret = false;
021230d4 2810 }
bc97114d
PWJ		 2811 } else {
2812 ret = false;
021230d4 2813 }
bc97114d
PWJ		 2814
2815 return ret;
2816}
2817#endif
2818
2819/**
2820 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2821 * @adapter: board private structure to initialize
2822 *
2823 * Once we know the feature-set enabled for the device, we'll cache
2824 * the register offset the descriptor ring is assigned to.
2825 *
2826 * Note, the order the various feature calls is important. It must start with
2827 * the "most" features enabled at the same time, then trickle down to the
2828 * least amount of features turned on at once.
2829 **/
2830static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2831{
2832 /* start with default case */
2833 adapter->rx_ring[0].reg_idx = 0;
2834 adapter->tx_ring[0].reg_idx = 0;
2835
2836#ifdef CONFIG_IXGBE_DCB
2837 if (ixgbe_cache_ring_dcb(adapter))
2838 return;
2839
2840#endif
2841 if (ixgbe_cache_ring_rss(adapter))
2842 return;
021230d4
AV		 2843}
2844
9a799d71
AK		 2845/**
2846 * ixgbe_alloc_queues - Allocate memory for all rings
2847 * @adapter: board private structure to initialize
2848 *
2849 * We allocate one ring per queue at run-time since we don't know the
a4d2f34b 2850 * number of queues at compile-time.
9a799d71 2851 **/
2f90b865 2852static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 2853{
2854 int i;
2855
2856 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 2857 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 2858 if (!adapter->tx_ring)
021230d4 2859 goto err_tx_ring_allocation;
9a799d71
AK		 2860
2861 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 2862 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2863 if (!adapter->rx_ring)
2864 goto err_rx_ring_allocation;
9a799d71 2865
021230d4 2866 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 2867 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 2868 adapter->tx_ring[i].queue_index = i;
2869 }
b9804972 2870
9a799d71 2871 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 2872 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 2873 adapter->rx_ring[i].queue_index = i;
2874 }
2875
2876 ixgbe_cache_ring_register(adapter);
2877
2878 return 0;
2879
2880err_rx_ring_allocation:
2881 kfree(adapter->tx_ring);
2882err_tx_ring_allocation:
2883 return -ENOMEM;
2884}
2885
2886/**
2887 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2888 * @adapter: board private structure to initialize
2889 *
2890 * Attempt to configure the interrupts using the best available
2891 * capabilities of the hardware and the kernel.
2892 **/
feea6a57 2893static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 2894{
2895 int err = 0;
2896 int vector, v_budget;
2897
2898 /*
2899 * It's easy to be greedy for MSI-X vectors, but it really
2900 * doesn't do us much good if we have a lot more vectors
2901 * than CPU's. So let's be conservative and only ask for
2902 * (roughly) twice the number of vectors as there are CPU's.
2903 */
2904 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 2905 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 2906
2907 /*
2908 * At the same time, hardware can only support a maximum of
2909 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2910 * we can easily reach upwards of 64 Rx descriptor queues and
2911 * 32 Tx queues. Thus, we cap it off in those rare cases where
2912 * the cpu count also exceeds our vector limit.
2913 */
2914 v_budget = min(v_budget, MAX_MSIX_COUNT);
2915
2916 /* A failure in MSI-X entry allocation isn't fatal, but it does
2917 * mean we disable MSI-X capabilities of the adapter. */
2918 adapter->msix_entries = kcalloc(v_budget,
b4617240 2919 sizeof(struct msix_entry), GFP_KERNEL);
021230d4 2920 if (!adapter->msix_entries) {
2f90b865 2921 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 2922 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2923 ixgbe_set_num_queues(adapter);
2924 kfree(adapter->tx_ring);
2925 kfree(adapter->rx_ring);
2926 err = ixgbe_alloc_queues(adapter);
2927 if (err) {
2928 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 2929 "for queues\n");
021230d4
AV		 2930 goto out;
2931 }
2932
2933 goto try_msi;
2934 }
2935
2936 for (vector = 0; vector < v_budget; vector++)
2937 adapter->msix_entries[vector].entry = vector;
2938
2939 ixgbe_acquire_msix_vectors(adapter, v_budget);
2940
2941 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2942 goto out;
2943
2944try_msi:
2945 err = pci_enable_msi(adapter->pdev);
2946 if (!err) {
2947 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2948 } else {
2949 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 2950 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 2951 /* reset err */
2952 err = 0;
2953 }
2954
2955out:
30eba97a 2956 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2957 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2958
2959 return err;
2960}
2961
2f90b865 2962void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 2963{
2964 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2965 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2966 pci_disable_msix(adapter->pdev);
2967 kfree(adapter->msix_entries);
2968 adapter->msix_entries = NULL;
2969 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2970 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2971 pci_disable_msi(adapter->pdev);
2972 }
2973 return;
2974}
2975
2976/**
2977 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2978 * @adapter: board private structure to initialize
2979 *
2980 * We determine which interrupt scheme to use based on...
2981 * - Kernel support (MSI, MSI-X)
2982 * - which can be user-defined (via MODULE_PARAM)
2983 * - Hardware queue count (num_*_queues)
2984 * - defined by miscellaneous hardware support/features (RSS, etc.)
2985 **/
2f90b865 2986int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 2987{
2988 int err;
2989
2990 /* Number of supported queues */
2991 ixgbe_set_num_queues(adapter);
2992
2993 err = ixgbe_alloc_queues(adapter);
2994 if (err) {
2995 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2996 goto err_alloc_queues;
2997 }
2998
2999 err = ixgbe_set_interrupt_capability(adapter);
3000 if (err) {
3001 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3002 goto err_set_interrupt;
9a799d71
AK		 3003 }
3004
021230d4 3005 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3006 "Tx Queue count = %u\n",
3007 (adapter->num_rx_queues > 1) ? "Enabled" :
3008 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3009
3010 set_bit(__IXGBE_DOWN, &adapter->state);
3011
9a799d71 3012 return 0;
021230d4
AV		 3013
3014err_set_interrupt:
3015 kfree(adapter->tx_ring);
3016 kfree(adapter->rx_ring);
3017err_alloc_queues:
3018 return err;
9a799d71
AK		 3019}
3020
c4900be0
DS		 3021/**
3022 * ixgbe_sfp_timer - worker thread to find a missing module
3023 * @data: pointer to our adapter struct
3024 **/
3025static void ixgbe_sfp_timer(unsigned long data)
3026{
3027 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3028
3029 /* Do the sfp_timer outside of interrupt context due to the
3030 * delays that sfp+ detection requires
3031 */
3032 schedule_work(&adapter->sfp_task);
3033}
3034
3035/**
3036 * ixgbe_sfp_task - worker thread to find a missing module
3037 * @work: pointer to work_struct containing our data
3038 **/
3039static void ixgbe_sfp_task(struct work_struct *work)
3040{
3041 struct ixgbe_adapter *adapter = container_of(work,
3042 struct ixgbe_adapter,
3043 sfp_task);
3044 struct ixgbe_hw *hw = &adapter->hw;
3045
3046 if ((hw->phy.type == ixgbe_phy_nl) &&
3047 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3048 s32 ret = hw->phy.ops.identify_sfp(hw);
3049 if (ret)
3050 goto reschedule;
3051 ret = hw->phy.ops.reset(hw);
3052 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3053 DPRINTK(PROBE, ERR, "failed to initialize because an "
3054 "unsupported SFP+ module type was detected.\n"
3055 "Reload the driver after installing a "
3056 "supported module.\n");
3057 unregister_netdev(adapter->netdev);
3058 } else {
3059 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3060 hw->phy.sfp_type);
3061 }
3062 /* don't need this routine any more */
3063 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3064 }
3065 return;
3066reschedule:
3067 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3068 mod_timer(&adapter->sfp_timer,
3069 round_jiffies(jiffies + (2 * HZ)));
3070}
3071
9a799d71
AK		 3072/**
3073 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3074 * @adapter: board private structure to initialize
3075 *
3076 * ixgbe_sw_init initializes the Adapter private data structure.
3077 * Fields are initialized based on PCI device information and
3078 * OS network device settings (MTU size).
3079 **/
3080static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3081{
3082 struct ixgbe_hw *hw = &adapter->hw;
3083 struct pci_dev *pdev = adapter->pdev;
021230d4 3084 unsigned int rss;
7a6b6f51 3085#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3086 int j;
3087 struct tc_configuration *tc;
3088#endif
021230d4 3089
c44ade9e
JB		 3090 /* PCI config space info */
3091
3092 hw->vendor_id = pdev->vendor;
3093 hw->device_id = pdev->device;
3094 hw->revision_id = pdev->revision;
3095 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3096 hw->subsystem_device_id = pdev->subsystem_device;
3097
021230d4
AV		 3098 /* Set capability flags */
3099 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3100 adapter->ring_feature[RING_F_RSS].indices = rss;
3101 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3102 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
e8e26350
PW		 3103 if (hw->mac.type == ixgbe_mac_82598EB)
3104 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3105 else if (hw->mac.type == ixgbe_mac_82599EB)
3106 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
2f90b865 3107
7a6b6f51 3108#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3109 /* Configure DCB traffic classes */
3110 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3111 tc = &adapter->dcb_cfg.tc_config[j];
3112 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3113 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3114 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3115 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3116 tc->dcb_pfc = pfc_disabled;
3117 }
3118 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3119 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3120 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3121 adapter->dcb_cfg.round_robin_enable = false;
3122 adapter->dcb_set_bitmap = 0x00;
3123 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3124 adapter->ring_feature[RING_F_DCB].indices);
3125
3126#endif
9a799d71
AK		 3127
3128 /* default flow control settings */
0ecc061d 3129 hw->fc.requested_mode = ixgbe_fc_none;
2b9ade93
JB		 3130 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3131 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3132 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3133 hw->fc.send_xon = true;
9a799d71 3134
30efa5a3
JB		 3135 /* enable itr by default in dynamic mode */
3136 adapter->itr_setting = 1;
3137 adapter->eitr_param = 20000;
3138
3139 /* set defaults for eitr in MegaBytes */
3140 adapter->eitr_low = 10;
3141 adapter->eitr_high = 20;
3142
3143 /* set default ring sizes */
3144 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3145 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3146
9a799d71 3147 /* initialize eeprom parameters */
c44ade9e 3148 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3149 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3150 return -EIO;
3151 }
3152
021230d4 3153 /* enable rx csum by default */
9a799d71
AK		 3154 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3155
9a799d71
AK		 3156 set_bit(__IXGBE_DOWN, &adapter->state);
3157
3158 return 0;
3159}
3160
3161/**
3162 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3163 * @adapter: board private structure
3a581073 3164 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3165 *
3166 * Return 0 on success, negative on failure
3167 **/
3168int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3169 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3170{
3171 struct pci_dev *pdev = adapter->pdev;
3172 int size;
3173
3a581073
JB		 3174 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3175 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3176 if (!tx_ring->tx_buffer_info)
3177 goto err;
3a581073 3178 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3179
3180 /* round up to nearest 4K */
12207e49 3181 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3182 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3183
3a581073
JB		 3184 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3185 &tx_ring->dma);
e01c31a5
JB		 3186 if (!tx_ring->desc)
3187 goto err;
9a799d71 3188
3a581073
JB		 3189 tx_ring->next_to_use = 0;
3190 tx_ring->next_to_clean = 0;
3191 tx_ring->work_limit = tx_ring->count;
9a799d71 3192 return 0;
e01c31a5
JB		 3193
3194err:
3195 vfree(tx_ring->tx_buffer_info);
3196 tx_ring->tx_buffer_info = NULL;
3197 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3198 "descriptor ring\n");
3199 return -ENOMEM;
9a799d71
AK		 3200}
3201
69888674
AD		 3202/**
3203 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3204 * @adapter: board private structure
3205 *
3206 * If this function returns with an error, then it's possible one or
3207 * more of the rings is populated (while the rest are not). It is the
3208 * callers duty to clean those orphaned rings.
3209 *
3210 * Return 0 on success, negative on failure
3211 **/
3212static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3213{
3214 int i, err = 0;
3215
3216 for (i = 0; i < adapter->num_tx_queues; i++) {
3217 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3218 if (!err)
3219 continue;
3220 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3221 break;
3222 }
3223
3224 return err;
3225}
3226
9a799d71
AK		 3227/**
3228 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3229 * @adapter: board private structure
3a581073 3230 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3231 *
3232 * Returns 0 on success, negative on failure
3233 **/
3234int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3235 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3236{
3237 struct pci_dev *pdev = adapter->pdev;
021230d4 3238 int size;
9a799d71 3239
3a581073
JB		 3240 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3241 rx_ring->rx_buffer_info = vmalloc(size);
3242 if (!rx_ring->rx_buffer_info) {
9a799d71 3243 DPRINTK(PROBE, ERR,
b4617240 3244 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3245 goto alloc_failed;
9a799d71 3246 }
3a581073 3247 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3248
9a799d71 3249 /* Round up to nearest 4K */
3a581073
JB		 3250 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3251 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3252
3a581073 3253 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3254
3a581073 3255 if (!rx_ring->desc) {
9a799d71 3256 DPRINTK(PROBE, ERR,
b4617240 3257 "Memory allocation failed for the rx desc ring\n");
3a581073 3258 vfree(rx_ring->rx_buffer_info);
177db6ff 3259 goto alloc_failed;
9a799d71
AK		 3260 }
3261
3a581073
JB		 3262 rx_ring->next_to_clean = 0;
3263 rx_ring->next_to_use = 0;
9a799d71
AK		 3264
3265 return 0;
177db6ff
MC		 3266
3267alloc_failed:
177db6ff 3268 return -ENOMEM;
9a799d71
AK		 3269}
3270
69888674
AD		 3271/**
3272 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3273 * @adapter: board private structure
3274 *
3275 * If this function returns with an error, then it's possible one or
3276 * more of the rings is populated (while the rest are not). It is the
3277 * callers duty to clean those orphaned rings.
3278 *
3279 * Return 0 on success, negative on failure
3280 **/
3281
3282static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3283{
3284 int i, err = 0;
3285
3286 for (i = 0; i < adapter->num_rx_queues; i++) {
3287 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3288 if (!err)
3289 continue;
3290 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3291 break;
3292 }
3293
3294 return err;
3295}
3296
9a799d71
AK		 3297/**
3298 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3299 * @adapter: board private structure
3300 * @tx_ring: Tx descriptor ring for a specific queue
3301 *
3302 * Free all transmit software resources
3303 **/
c431f97e
JB		 3304void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3305 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3306{
3307 struct pci_dev *pdev = adapter->pdev;
3308
3309 ixgbe_clean_tx_ring(adapter, tx_ring);
3310
3311 vfree(tx_ring->tx_buffer_info);
3312 tx_ring->tx_buffer_info = NULL;
3313
3314 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3315
3316 tx_ring->desc = NULL;
3317}
3318
3319/**
3320 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3321 * @adapter: board private structure
3322 *
3323 * Free all transmit software resources
3324 **/
3325static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3326{
3327 int i;
3328
3329 for (i = 0; i < adapter->num_tx_queues; i++)
3330 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3331}
3332
3333/**
b4617240 3334 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3335 * @adapter: board private structure
3336 * @rx_ring: ring to clean the resources from
3337 *
3338 * Free all receive software resources
3339 **/
c431f97e
JB		 3340void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3341 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3342{
3343 struct pci_dev *pdev = adapter->pdev;
3344
3345 ixgbe_clean_rx_ring(adapter, rx_ring);
3346
3347 vfree(rx_ring->rx_buffer_info);
3348 rx_ring->rx_buffer_info = NULL;
3349
3350 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3351
3352 rx_ring->desc = NULL;
3353}
3354
3355/**
3356 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3357 * @adapter: board private structure
3358 *
3359 * Free all receive software resources
3360 **/
3361static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3362{
3363 int i;
3364
3365 for (i = 0; i < adapter->num_rx_queues; i++)
3366 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3367}
3368
9a799d71
AK		 3369/**
3370 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3371 * @netdev: network interface device structure
3372 * @new_mtu: new value for maximum frame size
3373 *
3374 * Returns 0 on success, negative on failure
3375 **/
3376static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3377{
3378 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3379 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3380
42c783c5
JB		 3381 /* MTU < 68 is an error and causes problems on some kernels */
3382 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3383 return -EINVAL;
3384
021230d4 3385 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3386 netdev->mtu, new_mtu);
021230d4 3387 /* must set new MTU before calling down or up */
9a799d71
AK		 3388 netdev->mtu = new_mtu;
3389
d4f80882
AV		 3390 if (netif_running(netdev))
3391 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3392
3393 return 0;
3394}
3395
3396/**
3397 * ixgbe_open - Called when a network interface is made active
3398 * @netdev: network interface device structure
3399 *
3400 * Returns 0 on success, negative value on failure
3401 *
3402 * The open entry point is called when a network interface is made
3403 * active by the system (IFF_UP). At this point all resources needed
3404 * for transmit and receive operations are allocated, the interrupt
3405 * handler is registered with the OS, the watchdog timer is started,
3406 * and the stack is notified that the interface is ready.
3407 **/
3408static int ixgbe_open(struct net_device *netdev)
3409{
3410 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3411 int err;
4bebfaa5
AK		 3412
3413 /* disallow open during test */
3414 if (test_bit(__IXGBE_TESTING, &adapter->state))
3415 return -EBUSY;
9a799d71 3416
9a799d71
AK		 3417 /* allocate transmit descriptors */
3418 err = ixgbe_setup_all_tx_resources(adapter);
3419 if (err)
3420 goto err_setup_tx;
3421
9a799d71
AK		 3422 /* allocate receive descriptors */
3423 err = ixgbe_setup_all_rx_resources(adapter);
3424 if (err)
3425 goto err_setup_rx;
3426
3427 ixgbe_configure(adapter);
3428
021230d4 3429 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3430 if (err)
3431 goto err_req_irq;
3432
9a799d71
AK		 3433 err = ixgbe_up_complete(adapter);
3434 if (err)
3435 goto err_up;
3436
d55b53ff
JK		 3437 netif_tx_start_all_queues(netdev);
3438
9a799d71
AK		 3439 return 0;
3440
3441err_up:
5eba3699 3442 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3443 ixgbe_free_irq(adapter);
3444err_req_irq:
3445 ixgbe_free_all_rx_resources(adapter);
3446err_setup_rx:
3447 ixgbe_free_all_tx_resources(adapter);
3448err_setup_tx:
3449 ixgbe_reset(adapter);
3450
3451 return err;
3452}
3453
3454/**
3455 * ixgbe_close - Disables a network interface
3456 * @netdev: network interface device structure
3457 *
3458 * Returns 0, this is not allowed to fail
3459 *
3460 * The close entry point is called when an interface is de-activated
3461 * by the OS. The hardware is still under the drivers control, but
3462 * needs to be disabled. A global MAC reset is issued to stop the
3463 * hardware, and all transmit and receive resources are freed.
3464 **/
3465static int ixgbe_close(struct net_device *netdev)
3466{
3467 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3468
3469 ixgbe_down(adapter);
3470 ixgbe_free_irq(adapter);
3471
3472 ixgbe_free_all_tx_resources(adapter);
3473 ixgbe_free_all_rx_resources(adapter);
3474
5eba3699 3475 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3476
3477 return 0;
3478}
3479
b3c8b4ba
AD		 3480/**
3481 * ixgbe_napi_add_all - prep napi structs for use
3482 * @adapter: private struct
3483 * helper function to napi_add each possible q_vector->napi
3484 */
2f90b865 3485void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3486{
3487 int q_idx, q_vectors;
7adf1525 3488 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 3489 int (*poll)(struct napi_struct *, int);
3490
7adf1525
PWJ		 3491 /* check if we already have our netdev->napi_list populated */
3492 if (&netdev->napi_list != netdev->napi_list.next)
3493 return;
3494
b3c8b4ba
AD		 3495 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3496 poll = &ixgbe_clean_rxonly;
3497 /* Only enable as many vectors as we have rx queues. */
3498 q_vectors = adapter->num_rx_queues;
3499 } else {
3500 poll = &ixgbe_poll;
3501 /* only one q_vector for legacy modes */
3502 q_vectors = 1;
3503 }
3504
3505 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3506 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3507 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3508 }
3509}
3510
2f90b865 3511void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3512{
3513 int q_idx;
3514 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3515
3516 /* legacy and MSI only use one vector */
3517 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3518 q_vectors = 1;
3519
3520 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3521 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3522 if (!q_vector->rxr_count)
3523 continue;
3524 netif_napi_del(&q_vector->napi);
3525 }
3526}
3527
3528#ifdef CONFIG_PM
3529static int ixgbe_resume(struct pci_dev *pdev)
3530{
3531 struct net_device *netdev = pci_get_drvdata(pdev);
3532 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3533 u32 err;
3534
3535 pci_set_power_state(pdev, PCI_D0);
3536 pci_restore_state(pdev);
3537 err = pci_enable_device(pdev);
3538 if (err) {
69888674 3539 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3540 "suspend\n");
3541 return err;
3542 }
3543 pci_set_master(pdev);
3544
3545 pci_enable_wake(pdev, PCI_D3hot, 0);
3546 pci_enable_wake(pdev, PCI_D3cold, 0);
3547
3548 err = ixgbe_init_interrupt_scheme(adapter);
3549 if (err) {
3550 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3551 "device\n");
3552 return err;
3553 }
3554
3555 ixgbe_napi_add_all(adapter);
3556 ixgbe_reset(adapter);
3557
3558 if (netif_running(netdev)) {
3559 err = ixgbe_open(adapter->netdev);
3560 if (err)
3561 return err;
3562 }
3563
3564 netif_device_attach(netdev);
3565
3566 return 0;
3567}
3568
3569#endif /* CONFIG_PM */
3570static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3571{
3572 struct net_device *netdev = pci_get_drvdata(pdev);
3573 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3574 struct ixgbe_hw *hw = &adapter->hw;
3575 u32 ctrl, fctrl;
3576 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3577#ifdef CONFIG_PM
3578 int retval = 0;
3579#endif
3580
3581 netif_device_detach(netdev);
3582
3583 if (netif_running(netdev)) {
3584 ixgbe_down(adapter);
3585 ixgbe_free_irq(adapter);
3586 ixgbe_free_all_tx_resources(adapter);
3587 ixgbe_free_all_rx_resources(adapter);
3588 }
3589 ixgbe_reset_interrupt_capability(adapter);
3590 ixgbe_napi_del_all(adapter);
7adf1525 3591 INIT_LIST_HEAD(&netdev->napi_list);
b3c8b4ba
AD		 3592 kfree(adapter->tx_ring);
3593 kfree(adapter->rx_ring);
3594
3595#ifdef CONFIG_PM
3596 retval = pci_save_state(pdev);
3597 if (retval)
3598 return retval;
3599#endif
e8e26350
PW		 3600 if (wufc) {
3601 ixgbe_set_rx_mode(netdev);
b3c8b4ba 3602
e8e26350
PW		 3603 /* turn on all-multi mode if wake on multicast is enabled */
3604 if (wufc & IXGBE_WUFC_MC) {
3605 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3606 fctrl |= IXGBE_FCTRL_MPE;
3607 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3608 }
3609
3610 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3611 ctrl |= IXGBE_CTRL_GIO_DIS;
3612 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3613
3614 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3615 } else {
3616 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3617 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3618 }
3619
3620 if (wufc && hw->mac.type == ixgbe_mac_82599EB) {
3621 pci_enable_wake(pdev, PCI_D3hot, 1);
3622 pci_enable_wake(pdev, PCI_D3cold, 1);
3623 } else {
3624 pci_enable_wake(pdev, PCI_D3hot, 0);
3625 pci_enable_wake(pdev, PCI_D3cold, 0);
3626 }
b3c8b4ba
AD		 3627
3628 ixgbe_release_hw_control(adapter);
3629
3630 pci_disable_device(pdev);
3631
3632 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3633
3634 return 0;
3635}
3636
3637static void ixgbe_shutdown(struct pci_dev *pdev)
3638{
3639 ixgbe_suspend(pdev, PMSG_SUSPEND);
3640}
3641
9a799d71
AK		 3642/**
3643 * ixgbe_update_stats - Update the board statistics counters.
3644 * @adapter: board private structure
3645 **/
3646void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3647{
3648 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3649 u64 total_mpc = 0;
3650 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 3651
d51019a4
PW		 3652 if (hw->mac.type == ixgbe_mac_82599EB) {
3653 for (i = 0; i < 16; i++)
3654 adapter->hw_rx_no_dma_resources +=
3655 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3656 }
3657
9a799d71 3658 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3659 for (i = 0; i < 8; i++) {
3660 /* for packet buffers not used, the register should read 0 */
3661 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3662 missed_rx += mpc;
3663 adapter->stats.mpc[i] += mpc;
3664 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 3665 if (hw->mac.type == ixgbe_mac_82598EB)
3666 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3667 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3668 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3669 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3670 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 3671 if (hw->mac.type == ixgbe_mac_82599EB) {
3672 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3673 IXGBE_PXONRXCNT(i));
3674 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3675 IXGBE_PXOFFRXCNT(i));
3676 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 3677 } else {
3678 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3679 IXGBE_PXONRXC(i));
3680 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3681 IXGBE_PXOFFRXC(i));
3682 }
2f90b865
AD		 3683 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3684 IXGBE_PXONTXC(i));
2f90b865 3685 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 3686 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3687 }
3688 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3689 /* work around hardware counting issue */
3690 adapter->stats.gprc -= missed_rx;
3691
3692 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 3693 if (hw->mac.type == ixgbe_mac_82599EB) {
3694 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3695 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3696 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3697 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3698 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3699 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3700 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3701 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3702 } else {
3703 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3704 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3705 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3706 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3707 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3708 }
9a799d71
AK		 3709 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3710 adapter->stats.bprc += bprc;
3711 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 3712 if (hw->mac.type == ixgbe_mac_82598EB)
3713 adapter->stats.mprc -= bprc;
9a799d71
AK		 3714 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3715 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3716 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3717 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3718 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3719 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3720 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 3721 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 3722 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3723 adapter->stats.lxontxc += lxon;
3724 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3725 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3726 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3727 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3728 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3729 /*
3730 * 82598 errata - tx of flow control packets is included in tx counters
3731 */
3732 xon_off_tot = lxon + lxoff;
3733 adapter->stats.gptc -= xon_off_tot;
3734 adapter->stats.mptc -= xon_off_tot;
3735 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3736 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3737 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3738 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3739 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3740 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3741 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3742 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3743 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3744 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3745 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3746 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3747 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3748
3749 /* Fill out the OS statistics structure */
9a799d71
AK		 3750 adapter->net_stats.multicast = adapter->stats.mprc;
3751
3752 /* Rx Errors */
3753 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3754 adapter->stats.rlec;
9a799d71
AK		 3755 adapter->net_stats.rx_dropped = 0;
3756 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3757 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3758 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3759}
3760
3761/**
3762 * ixgbe_watchdog - Timer Call-back
3763 * @data: pointer to adapter cast into an unsigned long
3764 **/
3765static void ixgbe_watchdog(unsigned long data)
3766{
3767 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3768 struct ixgbe_hw *hw = &adapter->hw;
3769
3770 /* Do the watchdog outside of interrupt context due to the lovely
3771 * delays that some of the newer hardware requires */
3772 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3773 /* Cause software interrupt to ensure rx rings are cleaned */
3774 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3775 u32 eics =
3776 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3777 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3778 } else {
3779 /* For legacy and MSI interrupts don't set any bits that
3780 * are enabled for EIAM, because this operation would
3781 * set *both* EIMS and EICS for any bit in EIAM */
3782 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3783 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3784 }
3785 /* Reset the timer */
3786 mod_timer(&adapter->watchdog_timer,
3787 round_jiffies(jiffies + 2 * HZ));
3788 }
9a799d71 3789
cf8280ee
JB		 3790 schedule_work(&adapter->watchdog_task);
3791}
3792
e8e26350
PW		 3793/**
3794 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
3795 * @work: pointer to work_struct containing our data
3796 **/
3797static void ixgbe_multispeed_fiber_task(struct work_struct *work)
3798{
3799 struct ixgbe_adapter *adapter = container_of(work,
3800 struct ixgbe_adapter,
3801 multispeed_fiber_task);
3802 struct ixgbe_hw *hw = &adapter->hw;
3803 u32 autoneg;
3804
3805 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
3806 if (hw->mac.ops.get_link_capabilities)
3807 hw->mac.ops.get_link_capabilities(hw, &autoneg,
3808 &hw->mac.autoneg);
3809 if (hw->mac.ops.setup_link_speed)
3810 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3811 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3812 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
3813}
3814
3815/**
3816 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
3817 * @work: pointer to work_struct containing our data
3818 **/
3819static void ixgbe_sfp_config_module_task(struct work_struct *work)
3820{
3821 struct ixgbe_adapter *adapter = container_of(work,
3822 struct ixgbe_adapter,
3823 sfp_config_module_task);
3824 struct ixgbe_hw *hw = &adapter->hw;
3825 u32 err;
3826
3827 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
3828 err = hw->phy.ops.identify_sfp(hw);
3829 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3830 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
3831 ixgbe_down(adapter);
3832 return;
3833 }
3834 hw->mac.ops.setup_sfp(hw);
3835
3836 if (!adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)
3837 /* This will also work for DA Twinax connections */
3838 schedule_work(&adapter->multispeed_fiber_task);
3839 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
3840}
3841
cf8280ee 3842/**
69888674
AD		 3843 * ixgbe_watchdog_task - worker thread to bring link up
3844 * @work: pointer to work_struct containing our data
cf8280ee
JB		 3845 **/
3846static void ixgbe_watchdog_task(struct work_struct *work)
3847{
3848 struct ixgbe_adapter *adapter = container_of(work,
3849 struct ixgbe_adapter,
3850 watchdog_task);
3851 struct net_device *netdev = adapter->netdev;
3852 struct ixgbe_hw *hw = &adapter->hw;
3853 u32 link_speed = adapter->link_speed;
3854 bool link_up = adapter->link_up;
3855
3856 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3857
3858 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3859 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3860 if (link_up ||
3861 time_after(jiffies, (adapter->link_check_timeout +
3862 IXGBE_TRY_LINK_TIMEOUT))) {
3863 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3864 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3865 }
3866 adapter->link_up = link_up;
3867 adapter->link_speed = link_speed;
3868 }
9a799d71
AK		 3869
3870 if (link_up) {
3871 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 3872 bool flow_rx, flow_tx;
3873
3874 if (hw->mac.type == ixgbe_mac_82599EB) {
3875 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3876 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3877 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
3878 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
3879 } else {
3880 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3881 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3882 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
3883 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
3884 }
3885
a46e534b
JK		 3886 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3887 "Flow Control: %s\n",
3888 netdev->name,
3889 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3890 "10 Gbps" :
3891 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3892 "1 Gbps" : "unknown speed")),
e8e26350
PW		 3893 ((flow_rx && flow_tx) ? "RX/TX" :
3894 (flow_rx ? "RX" :
3895 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 3896
3897 netif_carrier_on(netdev);
9a799d71
AK		 3898 } else {
3899 /* Force detection of hung controller */
3900 adapter->detect_tx_hung = true;
3901 }
3902 } else {
cf8280ee
JB		 3903 adapter->link_up = false;
3904 adapter->link_speed = 0;
9a799d71 3905 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 3906 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3907 netdev->name);
9a799d71 3908 netif_carrier_off(netdev);
9a799d71
AK		 3909 }
3910 }
3911
3912 ixgbe_update_stats(adapter);
cf8280ee 3913 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 3914}
3915
9a799d71 3916static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 3917 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3918 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 3919{
3920 struct ixgbe_adv_tx_context_desc *context_desc;
3921 unsigned int i;
3922 int err;
3923 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 3924 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3925 u32 mss_l4len_idx, l4len;
9a799d71
AK		 3926
3927 if (skb_is_gso(skb)) {
3928 if (skb_header_cloned(skb)) {
3929 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3930 if (err)
3931 return err;
3932 }
3933 l4len = tcp_hdrlen(skb);
3934 *hdr_len += l4len;
3935
8327d000 3936 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3937 struct iphdr *iph = ip_hdr(skb);
3938 iph->tot_len = 0;
3939 iph->check = 0;
3940 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 3941 iph->daddr, 0,
3942 IPPROTO_TCP,
3943 0);
9a799d71
AK		 3944 adapter->hw_tso_ctxt++;
3945 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3946 ipv6_hdr(skb)->payload_len = 0;
3947 tcp_hdr(skb)->check =
3948 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 3949 &ipv6_hdr(skb)->daddr,
3950 0, IPPROTO_TCP, 0);
9a799d71
AK		 3951 adapter->hw_tso6_ctxt++;
3952 }
3953
3954 i = tx_ring->next_to_use;
3955
3956 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3957 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3958
3959 /* VLAN MACLEN IPLEN */
3960 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3961 vlan_macip_lens |=
3962 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3963 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 3964 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3965 *hdr_len += skb_network_offset(skb);
3966 vlan_macip_lens |=
3967 (skb_transport_header(skb) - skb_network_header(skb));
3968 *hdr_len +=
3969 (skb_transport_header(skb) - skb_network_header(skb));
3970 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3971 context_desc->seqnum_seed = 0;
3972
3973 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 3974 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 3975 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 3976
8327d000 3977 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3978 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3979 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3980 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3981
3982 /* MSS L4LEN IDX */
9f8cdf4f 3983 mss_l4len_idx =
9a799d71
AK		 3984 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3985 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 3986 /* use index 1 for TSO */
3987 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3988 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3989
3990 tx_buffer_info->time_stamp = jiffies;
3991 tx_buffer_info->next_to_watch = i;
3992
3993 i++;
3994 if (i == tx_ring->count)
3995 i = 0;
3996 tx_ring->next_to_use = i;
3997
3998 return true;
3999 }
4000 return false;
4001}
4002
4003static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4004 struct ixgbe_ring *tx_ring,
4005 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4006{
4007 struct ixgbe_adv_tx_context_desc *context_desc;
4008 unsigned int i;
4009 struct ixgbe_tx_buffer *tx_buffer_info;
4010 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4011
4012 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4013 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4014 i = tx_ring->next_to_use;
4015 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4016 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4017
4018 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4019 vlan_macip_lens |=
4020 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4021 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4022 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4023 if (skb->ip_summed == CHECKSUM_PARTIAL)
4024 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4025 skb_network_header(skb));
9a799d71
AK		 4026
4027 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4028 context_desc->seqnum_seed = 0;
4029
4030 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4031 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4032
4033 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4034 switch (skb->protocol) {
09640e63 4035 case cpu_to_be16(ETH_P_IP):
9a799d71 4036 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4037 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4038 type_tucmd_mlhl |=
b4617240 4039 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 4040 break;
09640e63 4041 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4042 /* XXX what about other V6 headers?? */
4043 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4044 type_tucmd_mlhl |=
b4617240 4045 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 4046 break;
41825d71
AK		 4047 default:
4048 if (unlikely(net_ratelimit())) {
4049 DPRINTK(PROBE, WARNING,
4050 "partial checksum but proto=%x!\n",
4051 skb->protocol);
4052 }
4053 break;
4054 }
9a799d71
AK		 4055 }
4056
4057 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4058 /* use index zero for tx checksum offload */
9a799d71
AK		 4059 context_desc->mss_l4len_idx = 0;
4060
4061 tx_buffer_info->time_stamp = jiffies;
4062 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4063
9a799d71
AK		 4064 adapter->hw_csum_tx_good++;
4065 i++;
4066 if (i == tx_ring->count)
4067 i = 0;
4068 tx_ring->next_to_use = i;
4069
4070 return true;
4071 }
9f8cdf4f 4072
9a799d71
AK		 4073 return false;
4074}
4075
4076static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 4077 struct ixgbe_ring *tx_ring,
4078 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 4079{
4080 struct ixgbe_tx_buffer *tx_buffer_info;
4081 unsigned int len = skb->len;
4082 unsigned int offset = 0, size, count = 0, i;
4083 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4084 unsigned int f;
4085
4086 len -= skb->data_len;
4087
4088 i = tx_ring->next_to_use;
4089
4090 while (len) {
4091 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4092 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4093
4094 tx_buffer_info->length = size;
4095 tx_buffer_info->dma = pci_map_single(adapter->pdev,
b4617240
PW		 4096 skb->data + offset,
4097 size, PCI_DMA_TODEVICE);
9a799d71
AK		 4098 tx_buffer_info->time_stamp = jiffies;
4099 tx_buffer_info->next_to_watch = i;
4100
4101 len -= size;
4102 offset += size;
4103 count++;
4104 i++;
4105 if (i == tx_ring->count)
4106 i = 0;
4107 }
4108
4109 for (f = 0; f < nr_frags; f++) {
4110 struct skb_frag_struct *frag;
4111
4112 frag = &skb_shinfo(skb)->frags[f];
4113 len = frag->size;
4114 offset = frag->page_offset;
4115
4116 while (len) {
4117 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4118 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4119
4120 tx_buffer_info->length = size;
4121 tx_buffer_info->dma = pci_map_page(adapter->pdev,
b4617240
PW		 4122 frag->page,
4123 offset,
4124 size,
4125 PCI_DMA_TODEVICE);
9a799d71
AK		 4126 tx_buffer_info->time_stamp = jiffies;
4127 tx_buffer_info->next_to_watch = i;
4128
4129 len -= size;
4130 offset += size;
4131 count++;
4132 i++;
4133 if (i == tx_ring->count)
4134 i = 0;
4135 }
4136 }
4137 if (i == 0)
4138 i = tx_ring->count - 1;
4139 else
4140 i = i - 1;
4141 tx_ring->tx_buffer_info[i].skb = skb;
4142 tx_ring->tx_buffer_info[first].next_to_watch = i;
4143
4144 return count;
4145}
4146
4147static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4148 struct ixgbe_ring *tx_ring,
4149 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4150{
4151 union ixgbe_adv_tx_desc *tx_desc = NULL;
4152 struct ixgbe_tx_buffer *tx_buffer_info;
4153 u32 olinfo_status = 0, cmd_type_len = 0;
4154 unsigned int i;
4155 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4156
4157 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4158
4159 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4160
4161 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4162 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4163
4164 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4165 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4166
4167 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4168 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4169
4eeae6fd
PW		 4170 /* use index 1 context for tso */
4171 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4172 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4173 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4174 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4175
4176 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4177 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4178 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4179
4180 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4181
4182 i = tx_ring->next_to_use;
4183 while (count--) {
4184 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4185 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4186 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4187 tx_desc->read.cmd_type_len =
b4617240 4188 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4189 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4190 i++;
4191 if (i == tx_ring->count)
4192 i = 0;
4193 }
4194
4195 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4196
4197 /*
4198 * Force memory writes to complete before letting h/w
4199 * know there are new descriptors to fetch. (Only
4200 * applicable for weak-ordered memory model archs,
4201 * such as IA-64).
4202 */
4203 wmb();
4204
4205 tx_ring->next_to_use = i;
4206 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4207}
4208
e092be60 4209static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4210 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4211{
4212 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4213
30eba97a 4214 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4215 /* Herbert's original patch had:
4216 * smp_mb__after_netif_stop_queue();
4217 * but since that doesn't exist yet, just open code it. */
4218 smp_mb();
4219
4220 /* We need to check again in a case another CPU has just
4221 * made room available. */
4222 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4223 return -EBUSY;
4224
4225 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4226 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4227 ++adapter->restart_queue;
4228 return 0;
4229}
4230
4231static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4232 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4233{
4234 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4235 return 0;
4236 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4237}
4238
9a799d71
AK		 4239static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4240{
4241 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4242 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4243 unsigned int first;
4244 unsigned int tx_flags = 0;
30eba97a
AV		 4245 u8 hdr_len = 0;
4246 int r_idx = 0, tso;
9a799d71
AK		 4247 int count = 0;
4248 unsigned int f;
9f8cdf4f 4249
30eba97a 4250 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 4251 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4252
9f8cdf4f
JB		 4253 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4254 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4255 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4256 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4257 tx_flags |= (skb->queue_mapping << 13);
4258 }
4259 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4260 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4261 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4262 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4263 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4264 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4265 }
9f8cdf4f
JB		 4266 /* three things can cause us to need a context descriptor */
4267 if (skb_is_gso(skb) ||
4268 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4269 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 4270 count++;
4271
9f8cdf4f
JB		 4272 count += TXD_USE_COUNT(skb_headlen(skb));
4273 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4274 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4275
e092be60 4276 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4277 adapter->tx_busy++;
9a799d71
AK		 4278 return NETDEV_TX_BUSY;
4279 }
9a799d71 4280
8327d000 4281 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4282 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4283 first = tx_ring->next_to_use;
4284 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4285 if (tso < 0) {
4286 dev_kfree_skb_any(skb);
4287 return NETDEV_TX_OK;
4288 }
4289
4290 if (tso)
4291 tx_flags |= IXGBE_TX_FLAGS_TSO;
4292 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 4293 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 4294 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4295
4296 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
b4617240
PW		 4297 ixgbe_tx_map(adapter, tx_ring, skb, first),
4298 skb->len, hdr_len);
9a799d71
AK		 4299
4300 netdev->trans_start = jiffies;
4301
e092be60 4302 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 4303
4304 return NETDEV_TX_OK;
4305}
4306
4307/**
4308 * ixgbe_get_stats - Get System Network Statistics
4309 * @netdev: network interface device structure
4310 *
4311 * Returns the address of the device statistics structure.
4312 * The statistics are actually updated from the timer callback.
4313 **/
4314static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4315{
4316 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4317
4318 /* only return the current stats */
4319 return &adapter->net_stats;
4320}
4321
4322/**
4323 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4324 * @netdev: network interface device structure
4325 * @p: pointer to an address structure
4326 *
4327 * Returns 0 on success, negative on failure
4328 **/
4329static int ixgbe_set_mac(struct net_device *netdev, void *p)
4330{
4331 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4332 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4333 struct sockaddr *addr = p;
4334
4335 if (!is_valid_ether_addr(addr->sa_data))
4336 return -EADDRNOTAVAIL;
4337
4338 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4339 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4340
b4617240 4341 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4342
4343 return 0;
4344}
4345
4346#ifdef CONFIG_NET_POLL_CONTROLLER
4347/*
4348 * Polling 'interrupt' - used by things like netconsole to send skbs
4349 * without having to re-enable interrupts. It's not called while
4350 * the interrupt routine is executing.
4351 */
4352static void ixgbe_netpoll(struct net_device *netdev)
4353{
4354 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4355
4356 disable_irq(adapter->pdev->irq);
4357 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4358 ixgbe_intr(adapter->pdev->irq, netdev);
4359 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4360 enable_irq(adapter->pdev->irq);
4361}
4362#endif
4363
0edc3527
SH		 4364static const struct net_device_ops ixgbe_netdev_ops = {
4365 .ndo_open = ixgbe_open,
4366 .ndo_stop = ixgbe_close,
00829823 4367 .ndo_start_xmit = ixgbe_xmit_frame,
0edc3527
SH		 4368 .ndo_get_stats = ixgbe_get_stats,
4369 .ndo_set_multicast_list = ixgbe_set_rx_mode,
4370 .ndo_validate_addr = eth_validate_addr,
4371 .ndo_set_mac_address = ixgbe_set_mac,
4372 .ndo_change_mtu = ixgbe_change_mtu,
4373 .ndo_tx_timeout = ixgbe_tx_timeout,
4374 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
4375 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
4376 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
4377#ifdef CONFIG_NET_POLL_CONTROLLER
4378 .ndo_poll_controller = ixgbe_netpoll,
4379#endif
4380};
4381
9a799d71
AK		 4382/**
4383 * ixgbe_probe - Device Initialization Routine
4384 * @pdev: PCI device information struct
4385 * @ent: entry in ixgbe_pci_tbl
4386 *
4387 * Returns 0 on success, negative on failure
4388 *
4389 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4390 * The OS initialization, configuring of the adapter private structure,
4391 * and a hardware reset occur.
4392 **/
4393static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 4394 const struct pci_device_id *ent)
9a799d71
AK		 4395{
4396 struct net_device *netdev;
4397 struct ixgbe_adapter *adapter = NULL;
4398 struct ixgbe_hw *hw;
4399 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 4400 static int cards_found;
4401 int i, err, pci_using_dac;
e8e26350 4402 u16 pm_value = 0;
c44ade9e 4403 u32 part_num, eec;
9a799d71
AK		 4404
4405 err = pci_enable_device(pdev);
4406 if (err)
4407 return err;
4408
4409 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
4410 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
4411 pci_using_dac = 1;
4412 } else {
4413 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4414 if (err) {
4415 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4416 if (err) {
b4617240
PW		 4417 dev_err(&pdev->dev, "No usable DMA "
4418 "configuration, aborting\n");
9a799d71
AK		 4419 goto err_dma;
4420 }
4421 }
4422 pci_using_dac = 0;
4423 }
4424
4425 err = pci_request_regions(pdev, ixgbe_driver_name);
4426 if (err) {
4427 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4428 goto err_pci_reg;
4429 }
4430
6fabd715
PWJ		 4431 err = pci_enable_pcie_error_reporting(pdev);
4432 if (err) {
4433 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4434 "0x%x\n", err);
4435 /* non-fatal, continue */
4436 }
4437
9a799d71 4438 pci_set_master(pdev);
fb3b27bc 4439 pci_save_state(pdev);
9a799d71 4440
30eba97a 4441 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 4442 if (!netdev) {
4443 err = -ENOMEM;
4444 goto err_alloc_etherdev;
4445 }
4446
9a799d71
AK		 4447 SET_NETDEV_DEV(netdev, &pdev->dev);
4448
4449 pci_set_drvdata(pdev, netdev);
4450 adapter = netdev_priv(netdev);
4451
4452 adapter->netdev = netdev;
4453 adapter->pdev = pdev;
4454 hw = &adapter->hw;
4455 hw->back = adapter;
4456 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4457
05857980
JK		 4458 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4459 pci_resource_len(pdev, 0));
9a799d71
AK		 4460 if (!hw->hw_addr) {
4461 err = -EIO;
4462 goto err_ioremap;
4463 }
4464
4465 for (i = 1; i <= 5; i++) {
4466 if (pci_resource_len(pdev, i) == 0)
4467 continue;
4468 }
4469
0edc3527 4470 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 4471 ixgbe_set_ethtool_ops(netdev);
9a799d71 4472 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 4473 strcpy(netdev->name, pci_name(pdev));
4474
9a799d71
AK		 4475 adapter->bd_number = cards_found;
4476
9a799d71
AK		 4477 /* Setup hw api */
4478 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 4479 hw->mac.type = ii->mac;
9a799d71 4480
c44ade9e
JB		 4481 /* EEPROM */
4482 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4483 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4484 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4485 if (!(eec & (1 << 8)))
4486 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4487
4488 /* PHY */
4489 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0
DS		 4490 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4491
4492 /* set up this timer and work struct before calling get_invariants
4493 * which might start the timer
4494 */
4495 init_timer(&adapter->sfp_timer);
4496 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4497 adapter->sfp_timer.data = (unsigned long) adapter;
4498
4499 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 4500
e8e26350
PW		 4501 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4502 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4503
4504 /* a new SFP+ module arrival, called from GPI SDP2 context */
4505 INIT_WORK(&adapter->sfp_config_module_task,
4506 ixgbe_sfp_config_module_task);
4507
9a799d71 4508 err = ii->get_invariants(hw);
c4900be0
DS		 4509 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4510 /* start a kernel thread to watch for a module to arrive */
4511 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4512 mod_timer(&adapter->sfp_timer,
4513 round_jiffies(jiffies + (2 * HZ)));
4514 err = 0;
4515 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4516 DPRINTK(PROBE, ERR, "failed to load because an "
4517 "unsupported SFP+ module type was detected.\n");
9a799d71 4518 goto err_hw_init;
c4900be0
DS		 4519 } else if (err) {
4520 goto err_hw_init;
4521 }
9a799d71
AK		 4522
4523 /* setup the private structure */
4524 err = ixgbe_sw_init(adapter);
4525 if (err)
4526 goto err_sw_init;
4527
c44ade9e
JB		 4528 /* reset_hw fills in the perm_addr as well */
4529 err = hw->mac.ops.reset_hw(hw);
4530 if (err) {
4531 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4532 goto err_sw_init;
4533 }
4534
9a799d71 4535 netdev->features = NETIF_F_SG |
b4617240
PW		 4536 NETIF_F_IP_CSUM |
4537 NETIF_F_HW_VLAN_TX |
4538 NETIF_F_HW_VLAN_RX |
4539 NETIF_F_HW_VLAN_FILTER;
9a799d71 4540
e9990a9c 4541 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4542 netdev->features |= NETIF_F_TSO;
9a799d71 4543 netdev->features |= NETIF_F_TSO6;
78b6f4ce 4544 netdev->features |= NETIF_F_GRO;
ad31c402
JK		 4545
4546 netdev->vlan_features |= NETIF_F_TSO;
4547 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4548 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4549 netdev->vlan_features |= NETIF_F_SG;
4550
2f90b865
AD		 4551 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4552 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4553
7a6b6f51 4554#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4555 netdev->dcbnl_ops = &dcbnl_ops;
4556#endif
4557
9a799d71
AK		 4558 if (pci_using_dac)
4559 netdev->features |= NETIF_F_HIGHDMA;
4560
9a799d71 4561 /* make sure the EEPROM is good */
c44ade9e 4562 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4563 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4564 err = -EIO;
4565 goto err_eeprom;
4566 }
4567
4568 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4569 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4570
c44ade9e
JB		 4571 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4572 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4573 err = -EIO;
4574 goto err_eeprom;
4575 }
4576
4577 init_timer(&adapter->watchdog_timer);
4578 adapter->watchdog_timer.function = &ixgbe_watchdog;
4579 adapter->watchdog_timer.data = (unsigned long)adapter;
4580
4581 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 4582 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 4583
021230d4
AV		 4584 err = ixgbe_init_interrupt_scheme(adapter);
4585 if (err)
4586 goto err_sw_init;
9a799d71 4587
e8e26350
PW		 4588 switch (pdev->device) {
4589 case IXGBE_DEV_ID_82599_KX4:
4590#define IXGBE_PCIE_PMCSR 0x44
4591 adapter->wol = IXGBE_WUFC_MAG;
4592 pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value);
4593 pci_write_config_word(pdev, IXGBE_PCIE_PMCSR,
4594 (pm_value | (1 << 8)));
4595 break;
4596 default:
4597 adapter->wol = 0;
4598 break;
4599 }
4600 device_init_wakeup(&adapter->pdev->dev, true);
4601 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4602
9a799d71 4603 /* print bus type/speed/width info */
7c510e4b 4604 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 4605 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4606 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4607 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4608 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4609 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 4610 "Unknown"),
7c510e4b 4611 netdev->dev_addr);
c44ade9e 4612 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 4613 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4614 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4615 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4616 (part_num >> 8), (part_num & 0xff));
4617 else
4618 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4619 hw->mac.type, hw->phy.type,
4620 (part_num >> 8), (part_num & 0xff));
9a799d71 4621
e8e26350 4622 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 4623 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 4624 "this card is not sufficient for optimal "
4625 "performance.\n");
0c254d86 4626 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 4627 "PCI-Express slot is required.\n");
0c254d86
AK		 4628 }
4629
34b0368c
PWJ		 4630 /* save off EEPROM version number */
4631 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4632
9a799d71 4633 /* reset the hardware with the new settings */
c44ade9e
JB		 4634 hw->mac.ops.start_hw(hw);
4635
9a799d71 4636 netif_carrier_off(netdev);
9a799d71
AK		 4637
4638 strcpy(netdev->name, "eth%d");
4639 err = register_netdev(netdev);
4640 if (err)
4641 goto err_register;
4642
5dd2d332 4643#ifdef CONFIG_IXGBE_DCA
652f093f 4644 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 4645 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4646 /* always use CB2 mode, difference is masked
4647 * in the CB driver */
4648 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4649 ixgbe_setup_dca(adapter);
4650 }
4651#endif
9a799d71
AK		 4652
4653 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4654 cards_found++;
4655 return 0;
4656
4657err_register:
5eba3699 4658 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4659err_hw_init:
4660err_sw_init:
021230d4 4661 ixgbe_reset_interrupt_capability(adapter);
9a799d71 4662err_eeprom:
c4900be0
DS		 4663 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4664 del_timer_sync(&adapter->sfp_timer);
4665 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4666 cancel_work_sync(&adapter->multispeed_fiber_task);
4667 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4668 iounmap(hw->hw_addr);
4669err_ioremap:
4670 free_netdev(netdev);
4671err_alloc_etherdev:
4672 pci_release_regions(pdev);
4673err_pci_reg:
4674err_dma:
4675 pci_disable_device(pdev);
4676 return err;
4677}
4678
4679/**
4680 * ixgbe_remove - Device Removal Routine
4681 * @pdev: PCI device information struct
4682 *
4683 * ixgbe_remove is called by the PCI subsystem to alert the driver
4684 * that it should release a PCI device. The could be caused by a
4685 * Hot-Plug event, or because the driver is going to be removed from
4686 * memory.
4687 **/
4688static void __devexit ixgbe_remove(struct pci_dev *pdev)
4689{
4690 struct net_device *netdev = pci_get_drvdata(pdev);
4691 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 4692 int err;
9a799d71
AK		 4693
4694 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 4695 /* clear the module not found bit to make sure the worker won't
4696 * reschedule
4697 */
4698 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 4699 del_timer_sync(&adapter->watchdog_timer);
4700
c4900be0
DS		 4701 del_timer_sync(&adapter->sfp_timer);
4702 cancel_work_sync(&adapter->watchdog_task);
4703 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4704 cancel_work_sync(&adapter->multispeed_fiber_task);
4705 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4706 flush_scheduled_work();
4707
5dd2d332 4708#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4709 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4710 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4711 dca_remove_requester(&pdev->dev);
4712 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4713 }
4714
4715#endif
c4900be0
DS		 4716 if (netdev->reg_state == NETREG_REGISTERED)
4717 unregister_netdev(netdev);
9a799d71 4718
021230d4 4719 ixgbe_reset_interrupt_capability(adapter);
5eba3699 4720
021230d4 4721 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4722
4723 iounmap(adapter->hw.hw_addr);
4724 pci_release_regions(pdev);
4725
021230d4
AV		 4726 DPRINTK(PROBE, INFO, "complete\n");
4727 kfree(adapter->tx_ring);
4728 kfree(adapter->rx_ring);
4729
9a799d71
AK		 4730 free_netdev(netdev);
4731
6fabd715
PWJ		 4732 err = pci_disable_pcie_error_reporting(pdev);
4733 if (err)
4734 dev_err(&pdev->dev,
4735 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4736
9a799d71
AK		 4737 pci_disable_device(pdev);
4738}
4739
4740/**
4741 * ixgbe_io_error_detected - called when PCI error is detected
4742 * @pdev: Pointer to PCI device
4743 * @state: The current pci connection state
4744 *
4745 * This function is called after a PCI bus error affecting
4746 * this device has been detected.
4747 */
4748static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 4749 pci_channel_state_t state)
9a799d71
AK		 4750{
4751 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4753
4754 netif_device_detach(netdev);
4755
4756 if (netif_running(netdev))
4757 ixgbe_down(adapter);
4758 pci_disable_device(pdev);
4759
b4617240 4760 /* Request a slot reset. */
9a799d71
AK		 4761 return PCI_ERS_RESULT_NEED_RESET;
4762}
4763
4764/**
4765 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4766 * @pdev: Pointer to PCI device
4767 *
4768 * Restart the card from scratch, as if from a cold-boot.
4769 */
4770static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4771{
4772 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4773 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 4774 pci_ers_result_t result;
4775 int err;
9a799d71
AK		 4776
4777 if (pci_enable_device(pdev)) {
4778 DPRINTK(PROBE, ERR,
b4617240 4779 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 4780 result = PCI_ERS_RESULT_DISCONNECT;
4781 } else {
4782 pci_set_master(pdev);
4783 pci_restore_state(pdev);
9a799d71 4784
6fabd715
PWJ		 4785 pci_enable_wake(pdev, PCI_D3hot, 0);
4786 pci_enable_wake(pdev, PCI_D3cold, 0);
9a799d71 4787
6fabd715
PWJ		 4788 ixgbe_reset(adapter);
4789
4790 result = PCI_ERS_RESULT_RECOVERED;
4791 }
4792
4793 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4794 if (err) {
4795 dev_err(&pdev->dev,
4796 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4797 /* non-fatal, continue */
4798 }
9a799d71 4799
6fabd715 4800 return result;
9a799d71
AK		 4801}
4802
4803/**
4804 * ixgbe_io_resume - called when traffic can start flowing again.
4805 * @pdev: Pointer to PCI device
4806 *
4807 * This callback is called when the error recovery driver tells us that
4808 * its OK to resume normal operation.
4809 */
4810static void ixgbe_io_resume(struct pci_dev *pdev)
4811{
4812 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4813 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4814
4815 if (netif_running(netdev)) {
4816 if (ixgbe_up(adapter)) {
4817 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4818 return;
4819 }
4820 }
4821
4822 netif_device_attach(netdev);
9a799d71
AK		 4823}
4824
4825static struct pci_error_handlers ixgbe_err_handler = {
4826 .error_detected = ixgbe_io_error_detected,
4827 .slot_reset = ixgbe_io_slot_reset,
4828 .resume = ixgbe_io_resume,
4829};
4830
4831static struct pci_driver ixgbe_driver = {
4832 .name = ixgbe_driver_name,
4833 .id_table = ixgbe_pci_tbl,
4834 .probe = ixgbe_probe,
4835 .remove = __devexit_p(ixgbe_remove),
4836#ifdef CONFIG_PM
4837 .suspend = ixgbe_suspend,
4838 .resume = ixgbe_resume,
4839#endif
4840 .shutdown = ixgbe_shutdown,
4841 .err_handler = &ixgbe_err_handler
4842};
4843
4844/**
4845 * ixgbe_init_module - Driver Registration Routine
4846 *
4847 * ixgbe_init_module is the first routine called when the driver is
4848 * loaded. All it does is register with the PCI subsystem.
4849 **/
4850static int __init ixgbe_init_module(void)
4851{
4852 int ret;
4853 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4854 ixgbe_driver_string, ixgbe_driver_version);
4855
4856 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4857
5dd2d332 4858#ifdef CONFIG_IXGBE_DCA
bd0362dd 4859 dca_register_notify(&dca_notifier);
bd0362dd 4860#endif
5dd2d332 4861
9a799d71
AK		 4862 ret = pci_register_driver(&ixgbe_driver);
4863 return ret;
4864}
b4617240 4865
9a799d71
AK		 4866module_init(ixgbe_init_module);
4867
4868/**
4869 * ixgbe_exit_module - Driver Exit Cleanup Routine
4870 *
4871 * ixgbe_exit_module is called just before the driver is removed
4872 * from memory.
4873 **/
4874static void __exit ixgbe_exit_module(void)
4875{
5dd2d332 4876#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4877 dca_unregister_notify(&dca_notifier);
4878#endif
9a799d71
AK		 4879 pci_unregister_driver(&ixgbe_driver);
4880}
bd0362dd 4881
5dd2d332 4882#ifdef CONFIG_IXGBE_DCA
bd0362dd 4883static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 4884 void *p)
bd0362dd
JC		 4885{
4886 int ret_val;
4887
4888 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 4889 __ixgbe_notify_dca);
bd0362dd
JC		 4890
4891 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4892}
5dd2d332 4893#endif /* CONFIG_IXGBE_DCA */
bd0362dd 4894
9a799d71
AK		 4895module_exit(ixgbe_exit_module);
4896
4897/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree