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[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
b4617240 4 Copyright(c) 1999 - 2008 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
51ac6445 50#define DRV_VERSION "1.3.30-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
b4617240 52static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 56};
57
58/* ixgbe_pci_tbl - PCI Device ID Table
59 *
60 * Wildcard entries (PCI_ANY_ID) should come last
61 * Last entry must be all 0s
62 *
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
65 */
66static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 67 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
68 board_82598 },
9a799d71 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 72 board_82598 },
0befdb3e
JB		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 76 board_82598 },
8d792cd9
JB		 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
78 board_82598 },
c4900be0
DS		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
82 board_82598 },
b95f5fcb
JB		 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
84 board_82598 },
c4900be0
DS		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
86 board_82598 },
9a799d71
AK		 87
88 /* required last entry */
89 {0, }
90};
91MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
92
5dd2d332 93#ifdef CONFIG_IXGBE_DCA
bd0362dd 94static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 95 void *p);
bd0362dd
JC		 96static struct notifier_block dca_notifier = {
97 .notifier_call = ixgbe_notify_dca,
98 .next = NULL,
99 .priority = 0
100};
101#endif
102
9a799d71
AK		 103MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
104MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
105MODULE_LICENSE("GPL");
106MODULE_VERSION(DRV_VERSION);
107
108#define DEFAULT_DEBUG_LEVEL_SHIFT 3
109
5eba3699
AV		 110static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
111{
112 u32 ctrl_ext;
113
114 /* Let firmware take over control of h/w */
115 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 117 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 118}
119
120static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
121{
122 u32 ctrl_ext;
123
124 /* Let firmware know the driver has taken over */
125 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
126 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 127 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 128}
9a799d71 129
9a799d71 130static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
b4617240 131 u8 msix_vector)
9a799d71
AK		 132{
133 u32 ivar, index;
134
135 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
136 index = (int_alloc_entry >> 2) & 0x1F;
137 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
138 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
139 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
140 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
141}
142
143static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 144 struct ixgbe_tx_buffer
145 *tx_buffer_info)
9a799d71
AK		 146{
147 if (tx_buffer_info->dma) {
e01c31a5 148 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
b4617240 149 tx_buffer_info->length, PCI_DMA_TODEVICE);
9a799d71
AK		 150 tx_buffer_info->dma = 0;
151 }
152 if (tx_buffer_info->skb) {
153 dev_kfree_skb_any(tx_buffer_info->skb);
154 tx_buffer_info->skb = NULL;
155 }
156 /* tx_buffer_info must be completely set up in the transmit path */
157}
158
159static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 160 struct ixgbe_ring *tx_ring,
161 unsigned int eop)
9a799d71 162{
e01c31a5
JB		 163 struct ixgbe_hw *hw = &adapter->hw;
164 u32 head, tail;
165
9a799d71 166 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 167 * check with the clearing of time_stamp and movement of eop */
168 head = IXGBE_READ_REG(hw, tx_ring->head);
169 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 170 adapter->detect_tx_hung = false;
e01c31a5
JB		 171 if ((head != tail) &&
172 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 173 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
174 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
175 /* detected Tx unit hang */
e01c31a5
JB		 176 union ixgbe_adv_tx_desc *tx_desc;
177 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 178 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 179 " Tx Queue <%d>\n"
180 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 181 " next_to_use <%x>\n"
182 " next_to_clean <%x>\n"
183 "tx_buffer_info[next_to_clean]\n"
184 " time_stamp <%lx>\n"
e01c31a5
JB		 185 " jiffies <%lx>\n",
186 tx_ring->queue_index,
187 head, tail,
188 tx_ring->next_to_use, eop,
189 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 190 return true;
191 }
192
193 return false;
194}
195
b4617240
PW		 196#define IXGBE_MAX_TXD_PWR 14
197#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 198
199/* Tx Descriptors needed, worst case */
200#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
201 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
202#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 203 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 204
e01c31a5
JB		 205#define GET_TX_HEAD_FROM_RING(ring) (\
206 *(volatile u32 *) \
207 ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
208static void ixgbe_tx_timeout(struct net_device *netdev);
209
9a799d71
AK		 210/**
211 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
212 * @adapter: board private structure
e01c31a5 213 * @tx_ring: tx ring to clean
9a799d71
AK		 214 **/
215static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 216 struct ixgbe_ring *tx_ring)
9a799d71 217{
e01c31a5 218 union ixgbe_adv_tx_desc *tx_desc;
9a799d71 219 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5
JB		 220 struct net_device *netdev = adapter->netdev;
221 struct sk_buff *skb;
222 unsigned int i;
223 u32 head, oldhead;
224 unsigned int count = 0;
225 unsigned int total_bytes = 0, total_packets = 0;
9a799d71 226
e01c31a5
JB		 227 rmb();
228 head = GET_TX_HEAD_FROM_RING(tx_ring);
229 head = le32_to_cpu(head);
9a799d71 230 i = tx_ring->next_to_clean;
e01c31a5
JB		 231 while (1) {
232 while (i != head) {
9a799d71
AK		 233 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
234 tx_buffer_info = &tx_ring->tx_buffer_info[i];
e01c31a5 235 skb = tx_buffer_info->skb;
9a799d71 236
e01c31a5 237 if (skb) {
e092be60 238 unsigned int segs, bytecount;
e01c31a5
JB		 239
240 /* gso_segs is currently only valid for tcp */
e092be60
AV		 241 segs = skb_shinfo(skb)->gso_segs ?: 1;
242 /* multiply data chunks by size of headers */
243 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 244 skb->len;
245 total_packets += segs;
246 total_bytes += bytecount;
e092be60 247 }
e01c31a5 248
9a799d71 249 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 250 tx_buffer_info);
9a799d71
AK		 251
252 i++;
253 if (i == tx_ring->count)
254 i = 0;
9a799d71 255
e01c31a5
JB		 256 count++;
257 if (count == tx_ring->count)
258 goto done_cleaning;
259 }
260 oldhead = head;
261 rmb();
262 head = GET_TX_HEAD_FROM_RING(tx_ring);
263 head = le32_to_cpu(head);
264 if (head == oldhead)
265 goto done_cleaning;
266 } /* while (1) */
267
268done_cleaning:
9a799d71
AK		 269 tx_ring->next_to_clean = i;
270
e092be60 271#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 272 if (unlikely(count && netif_carrier_ok(netdev) &&
273 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 274 /* Make sure that anybody stopping the queue after this
275 * sees the new next_to_clean.
276 */
277 smp_mb();
30eba97a
AV		 278 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
279 !test_bit(__IXGBE_DOWN, &adapter->state)) {
280 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 281 ++adapter->restart_queue;
30eba97a 282 }
e092be60 283 }
9a799d71 284
e01c31a5
JB		 285 if (adapter->detect_tx_hung) {
286 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
287 /* schedule immediate reset if we believe we hung */
288 DPRINTK(PROBE, INFO,
289 "tx hang %d detected, resetting adapter\n",
290 adapter->tx_timeout_count + 1);
291 ixgbe_tx_timeout(adapter->netdev);
292 }
293 }
9a799d71 294
e01c31a5
JB		 295 /* re-arm the interrupt */
296 if ((total_packets >= tx_ring->work_limit) ||
297 (count == tx_ring->count))
298 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 299
e01c31a5
JB		 300 tx_ring->total_bytes += total_bytes;
301 tx_ring->total_packets += total_packets;
302 tx_ring->stats.bytes += total_bytes;
303 tx_ring->stats.packets += total_packets;
304 adapter->net_stats.tx_bytes += total_bytes;
305 adapter->net_stats.tx_packets += total_packets;
306 return (total_packets ? true : false);
9a799d71
AK		 307}
308
5dd2d332 309#ifdef CONFIG_IXGBE_DCA
bd0362dd 310static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 311 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 312{
313 u32 rxctrl;
314 int cpu = get_cpu();
3a581073 315 int q = rx_ring - adapter->rx_ring;
bd0362dd 316
3a581073 317 if (rx_ring->cpu != cpu) {
bd0362dd
JC		 318 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
319 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
96b0e0f6 320 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 321 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
322 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 323 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
324 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
325 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 326 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 327 rx_ring->cpu = cpu;
bd0362dd
JC		 328 }
329 put_cpu();
330}
331
332static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 333 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 334{
335 u32 txctrl;
336 int cpu = get_cpu();
3a581073 337 int q = tx_ring - adapter->tx_ring;
bd0362dd 338
3a581073 339 if (tx_ring->cpu != cpu) {
bd0362dd
JC		 340 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
341 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
96b0e0f6 342 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 343 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
344 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 345 tx_ring->cpu = cpu;
bd0362dd
JC		 346 }
347 put_cpu();
348}
349
350static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
351{
352 int i;
353
354 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
355 return;
356
357 for (i = 0; i < adapter->num_tx_queues; i++) {
358 adapter->tx_ring[i].cpu = -1;
359 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
360 }
361 for (i = 0; i < adapter->num_rx_queues; i++) {
362 adapter->rx_ring[i].cpu = -1;
363 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
364 }
365}
366
367static int __ixgbe_notify_dca(struct device *dev, void *data)
368{
369 struct net_device *netdev = dev_get_drvdata(dev);
370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
371 unsigned long event = *(unsigned long *)data;
372
373 switch (event) {
374 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 375 /* if we're already enabled, don't do it again */
376 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
377 break;
bd0362dd
JC		 378 /* Always use CB2 mode, difference is masked
379 * in the CB driver. */
380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 381 if (dca_add_requester(dev) == 0) {
96b0e0f6 382 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 383 ixgbe_setup_dca(adapter);
384 break;
385 }
386 /* Fall Through since DCA is disabled. */
387 case DCA_PROVIDER_REMOVE:
388 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
389 dca_remove_requester(dev);
390 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
392 }
393 break;
394 }
395
652f093f 396 return 0;
bd0362dd
JC		 397}
398
5dd2d332 399#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 400/**
401 * ixgbe_receive_skb - Send a completed packet up the stack
402 * @adapter: board private structure
403 * @skb: packet to send up
177db6ff
MC		 404 * @status: hardware indication of status of receive
405 * @rx_ring: rx descriptor ring (for a specific queue) to setup
406 * @rx_desc: rx descriptor
9a799d71 407 **/
78b6f4ce 408static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 409 struct sk_buff *skb, u8 status,
177db6ff 410 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 411{
78b6f4ce
HX		 412 struct ixgbe_adapter *adapter = q_vector->adapter;
413 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 414 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
415 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 416
0c8dfc83 417 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
78b6f4ce 418 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
2f90b865 419 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 420 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 421 else
78b6f4ce 422 napi_gro_receive(napi, skb);
177db6ff
MC		 423 } else {
424 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 425 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 426 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
427 else
428 netif_receive_skb(skb);
429 } else {
2f90b865 430 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 431 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
432 else
433 netif_rx(skb);
434 }
9a799d71
AK		 435 }
436}
437
e59bd25d
AV		 438/**
439 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
440 * @adapter: address of board private structure
441 * @status_err: hardware indication of status of receive
442 * @skb: skb currently being received and modified
443 **/
9a799d71 444static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 445 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 446{
447 skb->ip_summed = CHECKSUM_NONE;
448
712744be
JB		 449 /* Rx csum disabled */
450 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 451 return;
e59bd25d
AV		 452
453 /* if IP and error */
454 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
455 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 456 adapter->hw_csum_rx_error++;
457 return;
458 }
e59bd25d
AV		 459
460 if (!(status_err & IXGBE_RXD_STAT_L4CS))
461 return;
462
463 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
464 adapter->hw_csum_rx_error++;
465 return;
466 }
467
9a799d71 468 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 469 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 470 adapter->hw_csum_rx_good++;
471}
472
473/**
474 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
475 * @adapter: address of board private structure
476 **/
477static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 478 struct ixgbe_ring *rx_ring,
479 int cleaned_count)
9a799d71 480{
9a799d71
AK		 481 struct pci_dev *pdev = adapter->pdev;
482 union ixgbe_adv_rx_desc *rx_desc;
3a581073 483 struct ixgbe_rx_buffer *bi;
9a799d71 484 unsigned int i;
9a799d71
AK		 485
486 i = rx_ring->next_to_use;
3a581073 487 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 488
489 while (cleaned_count--) {
490 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
491
762f4c57 492 if (!bi->page_dma &&
3a581073 493 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 494 if (!bi->page) {
762f4c57
JB		 495 bi->page = alloc_page(GFP_ATOMIC);
496 if (!bi->page) {
497 adapter->alloc_rx_page_failed++;
498 goto no_buffers;
499 }
500 bi->page_offset = 0;
501 } else {
502 /* use a half page if we're re-using */
503 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 504 }
762f4c57
JB		 505
506 bi->page_dma = pci_map_page(pdev, bi->page,
507 bi->page_offset,
508 (PAGE_SIZE / 2),
509 PCI_DMA_FROMDEVICE);
9a799d71
AK		 510 }
511
3a581073 512 if (!bi->skb) {
5ecc3614
JB		 513 struct sk_buff *skb;
514 skb = netdev_alloc_skb(adapter->netdev,
515 (rx_ring->rx_buf_len +
516 NET_IP_ALIGN));
9a799d71
AK		 517
518 if (!skb) {
519 adapter->alloc_rx_buff_failed++;
520 goto no_buffers;
521 }
522
523 /*
524 * Make buffer alignment 2 beyond a 16 byte boundary
525 * this will result in a 16 byte aligned IP header after
526 * the 14 byte MAC header is removed
527 */
528 skb_reserve(skb, NET_IP_ALIGN);
529
3a581073 530 bi->skb = skb;
5ecc3614
JB		 531 bi->dma = pci_map_single(pdev, skb->data,
532 rx_ring->rx_buf_len,
3a581073 533 PCI_DMA_FROMDEVICE);
9a799d71
AK		 534 }
535 /* Refresh the desc even if buffer_addrs didn't change because
536 * each write-back erases this info. */
537 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 538 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
539 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 540 } else {
3a581073 541 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 542 }
543
544 i++;
545 if (i == rx_ring->count)
546 i = 0;
3a581073 547 bi = &rx_ring->rx_buffer_info[i];
9a799d71 548 }
7c6e0a43 549
9a799d71
AK		 550no_buffers:
551 if (rx_ring->next_to_use != i) {
552 rx_ring->next_to_use = i;
553 if (i-- == 0)
554 i = (rx_ring->count - 1);
555
556 /*
557 * Force memory writes to complete before letting h/w
558 * know there are new descriptors to fetch. (Only
559 * applicable for weak-ordered memory model archs,
560 * such as IA-64).
561 */
562 wmb();
563 writel(i, adapter->hw.hw_addr + rx_ring->tail);
564 }
565}
566
7c6e0a43
JB		 567static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
568{
569 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
570}
571
572static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
573{
574 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
575}
576
78b6f4ce 577static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 578 struct ixgbe_ring *rx_ring,
579 int *work_done, int work_to_do)
9a799d71 580{
78b6f4ce 581 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 582 struct pci_dev *pdev = adapter->pdev;
583 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
584 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
585 struct sk_buff *skb;
586 unsigned int i;
7c6e0a43 587 u32 len, staterr;
177db6ff
MC		 588 u16 hdr_info;
589 bool cleaned = false;
9a799d71 590 int cleaned_count = 0;
d2f4fbe2 591 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 592
593 i = rx_ring->next_to_clean;
9a799d71
AK		 594 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
595 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
596 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 597
598 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 599 u32 upper_len = 0;
9a799d71
AK		 600 if (*work_done >= work_to_do)
601 break;
602 (*work_done)++;
603
604 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 605 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
606 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 607 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 608 if (hdr_info & IXGBE_RXDADV_SPH)
609 adapter->rx_hdr_split++;
610 if (len > IXGBE_RX_HDR_SIZE)
611 len = IXGBE_RX_HDR_SIZE;
612 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 613 } else {
9a799d71 614 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 615 }
9a799d71
AK		 616
617 cleaned = true;
618 skb = rx_buffer_info->skb;
619 prefetch(skb->data - NET_IP_ALIGN);
620 rx_buffer_info->skb = NULL;
621
622 if (len && !skb_shinfo(skb)->nr_frags) {
623 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 624 rx_ring->rx_buf_len,
b4617240 625 PCI_DMA_FROMDEVICE);
9a799d71
AK		 626 skb_put(skb, len);
627 }
628
629 if (upper_len) {
630 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 631 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 632 rx_buffer_info->page_dma = 0;
633 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 634 rx_buffer_info->page,
635 rx_buffer_info->page_offset,
636 upper_len);
637
638 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
639 (page_count(rx_buffer_info->page) != 1))
640 rx_buffer_info->page = NULL;
641 else
642 get_page(rx_buffer_info->page);
9a799d71
AK		 643
644 skb->len += upper_len;
645 skb->data_len += upper_len;
646 skb->truesize += upper_len;
647 }
648
649 i++;
650 if (i == rx_ring->count)
651 i = 0;
652 next_buffer = &rx_ring->rx_buffer_info[i];
653
654 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
655 prefetch(next_rxd);
656
657 cleaned_count++;
658 if (staterr & IXGBE_RXD_STAT_EOP) {
659 rx_ring->stats.packets++;
660 rx_ring->stats.bytes += skb->len;
661 } else {
662 rx_buffer_info->skb = next_buffer->skb;
663 rx_buffer_info->dma = next_buffer->dma;
664 next_buffer->skb = skb;
762f4c57 665 next_buffer->dma = 0;
9a799d71
AK		 666 adapter->non_eop_descs++;
667 goto next_desc;
668 }
669
670 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
671 dev_kfree_skb_irq(skb);
672 goto next_desc;
673 }
674
675 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 676
677 /* probably a little skewed due to removing CRC */
678 total_rx_bytes += skb->len;
679 total_rx_packets++;
680
74ce8dd2 681 skb->protocol = eth_type_trans(skb, adapter->netdev);
78b6f4ce 682 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
9a799d71
AK		 683
684next_desc:
685 rx_desc->wb.upper.status_error = 0;
686
687 /* return some buffers to hardware, one at a time is too slow */
688 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
689 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
690 cleaned_count = 0;
691 }
692
693 /* use prefetched values */
694 rx_desc = next_rxd;
695 rx_buffer_info = next_buffer;
696
697 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 698 }
699
9a799d71
AK		 700 rx_ring->next_to_clean = i;
701 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
702
703 if (cleaned_count)
704 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
705
f494e8fa
AV		 706 rx_ring->total_packets += total_rx_packets;
707 rx_ring->total_bytes += total_rx_bytes;
708 adapter->net_stats.rx_bytes += total_rx_bytes;
709 adapter->net_stats.rx_packets += total_rx_packets;
710
9a799d71
AK		 711 return cleaned;
712}
713
021230d4 714static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 715/**
716 * ixgbe_configure_msix - Configure MSI-X hardware
717 * @adapter: board private structure
718 *
719 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
720 * interrupts.
721 **/
722static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
723{
021230d4
AV		 724 struct ixgbe_q_vector *q_vector;
725 int i, j, q_vectors, v_idx, r_idx;
726 u32 mask;
9a799d71 727
021230d4 728 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 729
021230d4
AV		 730 /* Populate the IVAR table and set the ITR values to the
731 * corresponding register.
732 */
733 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
734 q_vector = &adapter->q_vector[v_idx];
735 /* XXX for_each_bit(...) */
736 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 737 adapter->num_rx_queues);
021230d4
AV		 738
739 for (i = 0; i < q_vector->rxr_count; i++) {
740 j = adapter->rx_ring[r_idx].reg_idx;
741 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
742 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 743 adapter->num_rx_queues,
744 r_idx + 1);
021230d4
AV		 745 }
746 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 747 adapter->num_tx_queues);
021230d4
AV		 748
749 for (i = 0; i < q_vector->txr_count; i++) {
750 j = adapter->tx_ring[r_idx].reg_idx;
751 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
752 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 753 adapter->num_tx_queues,
754 r_idx + 1);
021230d4
AV		 755 }
756
30efa5a3 757 /* if this is a tx only vector halve the interrupt rate */
021230d4 758 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 759 q_vector->eitr = (adapter->eitr_param >> 1);
021230d4 760 else
30efa5a3
JB		 761 /* rx only */
762 q_vector->eitr = adapter->eitr_param;
021230d4
AV		 763
764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 765 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 766 }
767
021230d4
AV		 768 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
770
41fb9248 771 /* set up to autoclear timer, and the vectors */
021230d4 772 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 773 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 775}
776
f494e8fa
AV		 777enum latency_range {
778 lowest_latency = 0,
779 low_latency = 1,
780 bulk_latency = 2,
781 latency_invalid = 255
782};
783
784/**
785 * ixgbe_update_itr - update the dynamic ITR value based on statistics
786 * @adapter: pointer to adapter
787 * @eitr: eitr setting (ints per sec) to give last timeslice
788 * @itr_setting: current throttle rate in ints/second
789 * @packets: the number of packets during this measurement interval
790 * @bytes: the number of bytes during this measurement interval
791 *
792 * Stores a new ITR value based on packets and byte
793 * counts during the last interrupt. The advantage of per interrupt
794 * computation is faster updates and more accurate ITR for the current
795 * traffic pattern. Constants in this function were computed
796 * based on theoretical maximum wire speed and thresholds were set based
797 * on testing data as well as attempting to minimize response time
798 * while increasing bulk throughput.
799 * this functionality is controlled by the InterruptThrottleRate module
800 * parameter (see ixgbe_param.c)
801 **/
802static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 803 u32 eitr, u8 itr_setting,
804 int packets, int bytes)
f494e8fa
AV		 805{
806 unsigned int retval = itr_setting;
807 u32 timepassed_us;
808 u64 bytes_perint;
809
810 if (packets == 0)
811 goto update_itr_done;
812
813
814 /* simple throttlerate management
815 * 0-20MB/s lowest (100000 ints/s)
816 * 20-100MB/s low (20000 ints/s)
817 * 100-1249MB/s bulk (8000 ints/s)
818 */
819 /* what was last interrupt timeslice? */
820 timepassed_us = 1000000/eitr;
821 bytes_perint = bytes / timepassed_us; /* bytes/usec */
822
823 switch (itr_setting) {
824 case lowest_latency:
825 if (bytes_perint > adapter->eitr_low)
826 retval = low_latency;
827 break;
828 case low_latency:
829 if (bytes_perint > adapter->eitr_high)
830 retval = bulk_latency;
831 else if (bytes_perint <= adapter->eitr_low)
832 retval = lowest_latency;
833 break;
834 case bulk_latency:
835 if (bytes_perint <= adapter->eitr_high)
836 retval = low_latency;
837 break;
838 }
839
840update_itr_done:
841 return retval;
842}
843
844static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
845{
846 struct ixgbe_adapter *adapter = q_vector->adapter;
847 struct ixgbe_hw *hw = &adapter->hw;
848 u32 new_itr;
849 u8 current_itr, ret_itr;
850 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 851 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 852 struct ixgbe_ring *rx_ring, *tx_ring;
853
854 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
855 for (i = 0; i < q_vector->txr_count; i++) {
856 tx_ring = &(adapter->tx_ring[r_idx]);
857 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 858 q_vector->tx_itr,
859 tx_ring->total_packets,
860 tx_ring->total_bytes);
f494e8fa
AV		 861 /* if the result for this queue would decrease interrupt
862 * rate for this vector then use that result */
30efa5a3 863 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 864 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 865 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 866 r_idx + 1);
f494e8fa
AV		 867 }
868
869 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
870 for (i = 0; i < q_vector->rxr_count; i++) {
871 rx_ring = &(adapter->rx_ring[r_idx]);
872 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 873 q_vector->rx_itr,
874 rx_ring->total_packets,
875 rx_ring->total_bytes);
f494e8fa
AV		 876 /* if the result for this queue would decrease interrupt
877 * rate for this vector then use that result */
30efa5a3 878 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 879 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 880 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 881 r_idx + 1);
f494e8fa
AV		 882 }
883
30efa5a3 884 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 885
886 switch (current_itr) {
887 /* counts and packets in update_itr are dependent on these numbers */
888 case lowest_latency:
889 new_itr = 100000;
890 break;
891 case low_latency:
892 new_itr = 20000; /* aka hwitr = ~200 */
893 break;
894 case bulk_latency:
895 default:
896 new_itr = 8000;
897 break;
898 }
899
900 if (new_itr != q_vector->eitr) {
901 u32 itr_reg;
902 /* do an exponential smoothing */
903 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
904 q_vector->eitr = new_itr;
905 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
906 /* must write high and low 16 bits to reset counter */
907 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
b4617240 908 itr_reg);
f494e8fa
AV		 909 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
910 }
911
912 return;
913}
914
0befdb3e
JB		 915static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
916{
917 struct ixgbe_hw *hw = &adapter->hw;
918
919 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
920 (eicr & IXGBE_EICR_GPI_SDP1)) {
921 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
922 /* write to clear the interrupt */
923 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
924 }
925}
cf8280ee
JB		 926
927static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
928{
929 struct ixgbe_hw *hw = &adapter->hw;
930
931 adapter->lsc_int++;
932 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
933 adapter->link_check_timeout = jiffies;
934 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
935 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
936 schedule_work(&adapter->watchdog_task);
937 }
938}
939
9a799d71
AK		 940static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
941{
942 struct net_device *netdev = data;
943 struct ixgbe_adapter *adapter = netdev_priv(netdev);
944 struct ixgbe_hw *hw = &adapter->hw;
945 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
946
cf8280ee
JB		 947 if (eicr & IXGBE_EICR_LSC)
948 ixgbe_check_lsc(adapter);
d4f80882 949
0befdb3e
JB		 950 ixgbe_check_fan_failure(adapter, eicr);
951
d4f80882
AV		 952 if (!test_bit(__IXGBE_DOWN, &adapter->state))
953 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 954
955 return IRQ_HANDLED;
956}
957
958static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
959{
021230d4
AV		 960 struct ixgbe_q_vector *q_vector = data;
961 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 962 struct ixgbe_ring *tx_ring;
021230d4
AV		 963 int i, r_idx;
964
965 if (!q_vector->txr_count)
966 return IRQ_HANDLED;
967
968 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
969 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 970 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 971#ifdef CONFIG_IXGBE_DCA
bd0362dd 972 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 973 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 974#endif
3a581073
JB		 975 tx_ring->total_bytes = 0;
976 tx_ring->total_packets = 0;
977 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 978 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 979 r_idx + 1);
021230d4 980 }
9a799d71 981
9a799d71
AK		 982 return IRQ_HANDLED;
983}
984
021230d4
AV		 985/**
986 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
987 * @irq: unused
988 * @data: pointer to our q_vector struct for this interrupt vector
989 **/
9a799d71
AK		 990static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
991{
021230d4
AV		 992 struct ixgbe_q_vector *q_vector = data;
993 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 994 struct ixgbe_ring *rx_ring;
021230d4 995 int r_idx;
30efa5a3 996 int i;
021230d4
AV		 997
998 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 999 for (i = 0; i < q_vector->rxr_count; i++) {
1000 rx_ring = &(adapter->rx_ring[r_idx]);
1001 rx_ring->total_bytes = 0;
1002 rx_ring->total_packets = 0;
1003 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1004 r_idx + 1);
1005 }
1006
021230d4
AV		 1007 if (!q_vector->rxr_count)
1008 return IRQ_HANDLED;
1009
30efa5a3 1010 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1011 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1012 /* disable interrupts on this vector only */
3a581073 1013 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
288379f0 1014 napi_schedule(&q_vector->napi);
021230d4
AV		 1015
1016 return IRQ_HANDLED;
1017}
1018
1019static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1020{
1021 ixgbe_msix_clean_rx(irq, data);
1022 ixgbe_msix_clean_tx(irq, data);
9a799d71 1023
9a799d71
AK		 1024 return IRQ_HANDLED;
1025}
1026
021230d4
AV		 1027/**
1028 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1029 * @napi: napi struct with our devices info in it
1030 * @budget: amount of work driver is allowed to do this pass, in packets
1031 *
f0848276
JB		 1032 * This function is optimized for cleaning one queue only on a single
1033 * q_vector!!!
021230d4 1034 **/
9a799d71
AK		 1035static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1036{
021230d4 1037 struct ixgbe_q_vector *q_vector =
b4617240 1038 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1039 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1040 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1041 int work_done = 0;
021230d4 1042 long r_idx;
9a799d71 1043
021230d4 1044 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1045 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1046#ifdef CONFIG_IXGBE_DCA
bd0362dd 1047 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1048 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1049#endif
9a799d71 1050
78b6f4ce 1051 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1052
021230d4
AV		 1053 /* If all Rx work done, exit the polling mode */
1054 if (work_done < budget) {
288379f0 1055 napi_complete(napi);
30efa5a3 1056 if (adapter->itr_setting & 3)
f494e8fa 1057 ixgbe_set_itr_msix(q_vector);
9a799d71 1058 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1059 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1060 }
1061
1062 return work_done;
1063}
1064
f0848276
JB		 1065/**
1066 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1067 * @napi: napi struct with our devices info in it
1068 * @budget: amount of work driver is allowed to do this pass, in packets
1069 *
1070 * This function will clean more than one rx queue associated with a
1071 * q_vector.
1072 **/
1073static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1074{
1075 struct ixgbe_q_vector *q_vector =
1076 container_of(napi, struct ixgbe_q_vector, napi);
1077 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1078 struct ixgbe_ring *rx_ring = NULL;
1079 int work_done = 0, i;
1080 long r_idx;
1081 u16 enable_mask = 0;
1082
1083 /* attempt to distribute budget to each queue fairly, but don't allow
1084 * the budget to go below 1 because we'll exit polling */
1085 budget /= (q_vector->rxr_count ?: 1);
1086 budget = max(budget, 1);
1087 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1088 for (i = 0; i < q_vector->rxr_count; i++) {
1089 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1090#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1091 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1092 ixgbe_update_rx_dca(adapter, rx_ring);
1093#endif
78b6f4ce 1094 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1095 enable_mask |= rx_ring->v_idx;
1096 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1097 r_idx + 1);
1098 }
1099
1100 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1101 rx_ring = &(adapter->rx_ring[r_idx]);
1102 /* If all Rx work done, exit the polling mode */
7f821875 1103 if (work_done < budget) {
288379f0 1104 napi_complete(napi);
f0848276
JB		 1105 if (adapter->itr_setting & 3)
1106 ixgbe_set_itr_msix(q_vector);
1107 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1108 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1109 return 0;
1110 }
1111
1112 return work_done;
1113}
021230d4 1114static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1115 int r_idx)
021230d4
AV		 1116{
1117 a->q_vector[v_idx].adapter = a;
1118 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1119 a->q_vector[v_idx].rxr_count++;
1120 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1121}
1122
1123static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1124 int r_idx)
021230d4
AV		 1125{
1126 a->q_vector[v_idx].adapter = a;
1127 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1128 a->q_vector[v_idx].txr_count++;
1129 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1130}
1131
9a799d71 1132/**
021230d4
AV		 1133 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1134 * @adapter: board private structure to initialize
1135 * @vectors: allotted vector count for descriptor rings
9a799d71 1136 *
021230d4
AV		 1137 * This function maps descriptor rings to the queue-specific vectors
1138 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1139 * one vector per ring/queue, but on a constrained vector budget, we
1140 * group the rings as "efficiently" as possible. You would add new
1141 * mapping configurations in here.
9a799d71 1142 **/
021230d4 1143static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1144 int vectors)
021230d4
AV		 1145{
1146 int v_start = 0;
1147 int rxr_idx = 0, txr_idx = 0;
1148 int rxr_remaining = adapter->num_rx_queues;
1149 int txr_remaining = adapter->num_tx_queues;
1150 int i, j;
1151 int rqpv, tqpv;
1152 int err = 0;
1153
1154 /* No mapping required if MSI-X is disabled. */
1155 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1156 goto out;
9a799d71 1157
021230d4
AV		 1158 /*
1159 * The ideal configuration...
1160 * We have enough vectors to map one per queue.
1161 */
1162 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1163 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1164 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1165
021230d4
AV		 1166 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1167 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1168
9a799d71 1169 goto out;
021230d4 1170 }
9a799d71 1171
021230d4
AV		 1172 /*
1173 * If we don't have enough vectors for a 1-to-1
1174 * mapping, we'll have to group them so there are
1175 * multiple queues per vector.
1176 */
1177 /* Re-adjusting *qpv takes care of the remainder. */
1178 for (i = v_start; i < vectors; i++) {
1179 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1180 for (j = 0; j < rqpv; j++) {
1181 map_vector_to_rxq(adapter, i, rxr_idx);
1182 rxr_idx++;
1183 rxr_remaining--;
1184 }
1185 }
1186 for (i = v_start; i < vectors; i++) {
1187 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1188 for (j = 0; j < tqpv; j++) {
1189 map_vector_to_txq(adapter, i, txr_idx);
1190 txr_idx++;
1191 txr_remaining--;
9a799d71 1192 }
9a799d71
AK		 1193 }
1194
021230d4
AV		 1195out:
1196 return err;
1197}
1198
1199/**
1200 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1201 * @adapter: board private structure
1202 *
1203 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1204 * interrupts from the kernel.
1205 **/
1206static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1207{
1208 struct net_device *netdev = adapter->netdev;
1209 irqreturn_t (*handler)(int, void *);
1210 int i, vector, q_vectors, err;
cb13fc20 1211 int ri=0, ti=0;
021230d4
AV		 1212
1213 /* Decrement for Other and TCP Timer vectors */
1214 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1215
1216 /* Map the Tx/Rx rings to the vectors we were allotted. */
1217 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1218 if (err)
1219 goto out;
1220
1221#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1222 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1223 &ixgbe_msix_clean_many)
021230d4
AV		 1224 for (vector = 0; vector < q_vectors; vector++) {
1225 handler = SET_HANDLER(&adapter->q_vector[vector]);
cb13fc20
RO		 1226
1227 if(handler == &ixgbe_msix_clean_rx) {
1228 sprintf(adapter->name[vector], "%s-%s-%d",
1229 netdev->name, "rx", ri++);
1230 }
1231 else if(handler == &ixgbe_msix_clean_tx) {
1232 sprintf(adapter->name[vector], "%s-%s-%d",
1233 netdev->name, "tx", ti++);
1234 }
1235 else
1236 sprintf(adapter->name[vector], "%s-%s-%d",
1237 netdev->name, "TxRx", vector);
1238
021230d4 1239 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1240 handler, 0, adapter->name[vector],
1241 &(adapter->q_vector[vector]));
9a799d71
AK		 1242 if (err) {
1243 DPRINTK(PROBE, ERR,
b4617240
PW		 1244 "request_irq failed for MSIX interrupt "
1245 "Error: %d\n", err);
021230d4 1246 goto free_queue_irqs;
9a799d71 1247 }
9a799d71
AK		 1248 }
1249
021230d4
AV		 1250 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1251 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1252 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1253 if (err) {
1254 DPRINTK(PROBE, ERR,
1255 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1256 goto free_queue_irqs;
9a799d71
AK		 1257 }
1258
9a799d71
AK		 1259 return 0;
1260
021230d4
AV		 1261free_queue_irqs:
1262 for (i = vector - 1; i >= 0; i--)
1263 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1264 &(adapter->q_vector[i]));
021230d4
AV		 1265 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1266 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1267 kfree(adapter->msix_entries);
1268 adapter->msix_entries = NULL;
021230d4 1269out:
9a799d71
AK		 1270 return err;
1271}
1272
f494e8fa
AV		 1273static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1274{
1275 struct ixgbe_hw *hw = &adapter->hw;
1276 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1277 u8 current_itr;
1278 u32 new_itr = q_vector->eitr;
1279 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1280 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1281
30efa5a3 1282 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1283 q_vector->tx_itr,
1284 tx_ring->total_packets,
1285 tx_ring->total_bytes);
30efa5a3 1286 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1287 q_vector->rx_itr,
1288 rx_ring->total_packets,
1289 rx_ring->total_bytes);
f494e8fa 1290
30efa5a3 1291 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1292
1293 switch (current_itr) {
1294 /* counts and packets in update_itr are dependent on these numbers */
1295 case lowest_latency:
1296 new_itr = 100000;
1297 break;
1298 case low_latency:
1299 new_itr = 20000; /* aka hwitr = ~200 */
1300 break;
1301 case bulk_latency:
1302 new_itr = 8000;
1303 break;
1304 default:
1305 break;
1306 }
1307
1308 if (new_itr != q_vector->eitr) {
1309 u32 itr_reg;
1310 /* do an exponential smoothing */
1311 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1312 q_vector->eitr = new_itr;
1313 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1314 /* must write high and low 16 bits to reset counter */
1315 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1316 }
1317
1318 return;
1319}
1320
79aefa45
AD		 1321/**
1322 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1323 * @adapter: board private structure
1324 **/
1325static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1326{
1327 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1328 IXGBE_WRITE_FLUSH(&adapter->hw);
1329 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1330 int i;
1331 for (i = 0; i < adapter->num_msix_vectors; i++)
1332 synchronize_irq(adapter->msix_entries[i].vector);
1333 } else {
1334 synchronize_irq(adapter->pdev->irq);
1335 }
1336}
1337
1338/**
1339 * ixgbe_irq_enable - Enable default interrupt generation settings
1340 * @adapter: board private structure
1341 **/
1342static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1343{
1344 u32 mask;
1345 mask = IXGBE_EIMS_ENABLE_MASK;
6ab33d51
DM		 1346 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1347 mask |= IXGBE_EIMS_GPI_SDP1;
79aefa45
AD		 1348 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1349 IXGBE_WRITE_FLUSH(&adapter->hw);
1350}
021230d4 1351
9a799d71 1352/**
021230d4 1353 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1354 * @irq: interrupt number
1355 * @data: pointer to a network interface device structure
9a799d71
AK		 1356 **/
1357static irqreturn_t ixgbe_intr(int irq, void *data)
1358{
1359 struct net_device *netdev = data;
1360 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1361 struct ixgbe_hw *hw = &adapter->hw;
1362 u32 eicr;
1363
021230d4
AV		 1364 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1365 * therefore no explict interrupt disable is necessary */
1366 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1367 if (!eicr) {
1368 /* shared interrupt alert!
1369 * make sure interrupts are enabled because the read will
1370 * have disabled interrupts due to EIAM */
1371 ixgbe_irq_enable(adapter);
9a799d71 1372 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1373 }
9a799d71 1374
cf8280ee
JB		 1375 if (eicr & IXGBE_EICR_LSC)
1376 ixgbe_check_lsc(adapter);
021230d4 1377
0befdb3e
JB		 1378 ixgbe_check_fan_failure(adapter, eicr);
1379
288379f0 1380 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
f494e8fa
AV		 1381 adapter->tx_ring[0].total_packets = 0;
1382 adapter->tx_ring[0].total_bytes = 0;
1383 adapter->rx_ring[0].total_packets = 0;
1384 adapter->rx_ring[0].total_bytes = 0;
021230d4 1385 /* would disable interrupts here but EIAM disabled it */
288379f0 1386 __napi_schedule(&adapter->q_vector[0].napi);
9a799d71
AK		 1387 }
1388
1389 return IRQ_HANDLED;
1390}
1391
021230d4
AV		 1392static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1393{
1394 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1395
1396 for (i = 0; i < q_vectors; i++) {
1397 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1398 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1399 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1400 q_vector->rxr_count = 0;
1401 q_vector->txr_count = 0;
1402 }
1403}
1404
9a799d71
AK		 1405/**
1406 * ixgbe_request_irq - initialize interrupts
1407 * @adapter: board private structure
1408 *
1409 * Attempts to configure interrupts using the best available
1410 * capabilities of the hardware and kernel.
1411 **/
021230d4 1412static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1413{
1414 struct net_device *netdev = adapter->netdev;
021230d4 1415 int err;
9a799d71 1416
021230d4
AV		 1417 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1418 err = ixgbe_request_msix_irqs(adapter);
1419 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1420 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1421 netdev->name, netdev);
021230d4
AV		 1422 } else {
1423 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1424 netdev->name, netdev);
9a799d71
AK		 1425 }
1426
9a799d71
AK		 1427 if (err)
1428 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1429
9a799d71
AK		 1430 return err;
1431}
1432
1433static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1434{
1435 struct net_device *netdev = adapter->netdev;
1436
1437 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1438 int i, q_vectors;
9a799d71 1439
021230d4
AV		 1440 q_vectors = adapter->num_msix_vectors;
1441
1442 i = q_vectors - 1;
9a799d71 1443 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1444
021230d4
AV		 1445 i--;
1446 for (; i >= 0; i--) {
1447 free_irq(adapter->msix_entries[i].vector,
b4617240 1448 &(adapter->q_vector[i]));
021230d4
AV		 1449 }
1450
1451 ixgbe_reset_q_vectors(adapter);
1452 } else {
1453 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1454 }
1455}
1456
9a799d71
AK		 1457/**
1458 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1459 *
1460 **/
1461static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1462{
9a799d71
AK		 1463 struct ixgbe_hw *hw = &adapter->hw;
1464
021230d4 1465 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1466 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71
AK		 1467
1468 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1469 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1470
1471 map_vector_to_rxq(adapter, 0, 0);
1472 map_vector_to_txq(adapter, 0, 0);
1473
1474 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1475}
1476
1477/**
3a581073 1478 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1479 * @adapter: board private structure
1480 *
1481 * Configure the Tx unit of the MAC after a reset.
1482 **/
1483static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1484{
e01c31a5 1485 u64 tdba, tdwba;
9a799d71 1486 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1487 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1488
1489 /* Setup the HW Tx Head and Tail descriptor pointers */
1490 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1491 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1492 j = ring->reg_idx;
1493 tdba = ring->dma;
1494 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1495 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1496 (tdba & DMA_32BIT_MASK));
021230d4 1497 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
e01c31a5
JB		 1498 tdwba = ring->dma +
1499 (ring->count * sizeof(union ixgbe_adv_tx_desc));
1500 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1501 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1502 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
021230d4
AV		 1503 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1504 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1505 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1506 adapter->tx_ring[i].head = IXGBE_TDH(j);
1507 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1508 /* Disable Tx Head Writeback RO bit, since this hoses
1509 * bookkeeping if things aren't delivered in order.
1510 */
e01c31a5 1511 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1512 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1513 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1514 }
9a799d71
AK		 1515}
1516
cc41ac7c
JB		 1517#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1518
1519static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1520{
1521 struct ixgbe_ring *rx_ring;
1522 u32 srrctl;
1523 int queue0;
3be1adfb
AD		 1524 unsigned long mask;
1525
1526 /* program one srrctl register per VMDq index */
1527 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1528 long shift, len;
1529 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1530 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1531 shift = find_first_bit(&mask, len);
1532 queue0 = index & mask;
1533 index = (index & mask) >> shift;
1534 /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
cc41ac7c 1535 } else {
3be1adfb
AD		 1536 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1537 queue0 = index & mask;
1538 index = index & mask;
cc41ac7c 1539 }
3be1adfb 1540
cc41ac7c
JB		 1541 rx_ring = &adapter->rx_ring[queue0];
1542
1543 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1544
1545 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1546 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1547
1548 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1549 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1550 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1551 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1552 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1553 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1554 } else {
1555 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1556
1557 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1558 srrctl |= IXGBE_RXBUFFER_2048 >>
1559 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1560 else
1561 srrctl |= rx_ring->rx_buf_len >>
1562 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1563 }
1564 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1565}
9a799d71 1566
cc41ac7c 1567#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
b4617240 1568 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
cc41ac7c 1569
9a799d71 1570/**
3a581073 1571 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1572 * @adapter: board private structure
1573 *
1574 * Configure the Rx unit of the MAC after a reset.
1575 **/
1576static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1577{
1578 u64 rdba;
1579 struct ixgbe_hw *hw = &adapter->hw;
1580 struct net_device *netdev = adapter->netdev;
1581 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1582 int i, j;
9a799d71 1583 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1584 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1585 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1586 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1587 u32 fctrl, hlreg0;
9a799d71 1588 u32 pages;
cc41ac7c
JB		 1589 u32 reta = 0, mrqc;
1590 u32 rdrxctl;
7c6e0a43 1591 int rx_buf_len;
9a799d71
AK		 1592
1593 /* Decide whether to use packet split mode or not */
762f4c57 1594 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1595
1596 /* Set the RX buffer length according to the mode */
1597 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1598 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71
AK		 1599 } else {
1600 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1601 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1602 else
7c6e0a43 1603 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1604 }
1605
1606 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1607 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1608 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1609 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1610
1611 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1612 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1613 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1614 else
1615 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1616 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1617
1618 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1619
9a799d71
AK		 1620 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1621 /* disable receives while setting up the descriptors */
1622 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1623 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1624
1625 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1626 * the Base and Length of the Rx Descriptor Ring */
1627 for (i = 0; i < adapter->num_rx_queues; i++) {
1628 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1629 j = adapter->rx_ring[i].reg_idx;
1630 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1631 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1632 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1633 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1634 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1635 adapter->rx_ring[i].head = IXGBE_RDH(j);
1636 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1637 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c
JB		 1638
1639 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1640 }
1641
cc41ac7c
JB		 1642 /*
1643 * For VMDq support of different descriptor types or
1644 * buffer sizes through the use of multiple SRRCTL
1645 * registers, RDRXCTL.MVMEN must be set to 1
1646 *
1647 * also, the manual doesn't mention it clearly but DCA hints
1648 * will only use queue 0's tags unless this bit is set. Side
1649 * effects of setting this bit are only that SRRCTL must be
1650 * fully programmed [0..15]
1651 */
2f90b865
AD		 1652 if (adapter->flags &
1653 (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) {
1654 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1655 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1656 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1657 }
177db6ff 1658
021230d4 1659 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1660 /* Fill out redirection table */
021230d4
AV		 1661 for (i = 0, j = 0; i < 128; i++, j++) {
1662 if (j == adapter->ring_feature[RING_F_RSS].indices)
1663 j = 0;
1664 /* reta = 4-byte sliding window of
1665 * 0x00..(indices-1)(indices-1)00..etc. */
1666 reta = (reta << 8) | (j * 0x11);
1667 if ((i & 3) == 3)
1668 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1669 }
1670
1671 /* Fill out hash function seeds */
1672 for (i = 0; i < 10; i++)
7c6e0a43 1673 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1674
1675 mrqc = IXGBE_MRQC_RSSEN
1676 /* Perform hash on these packet types */
7c6e0a43
JB		 1677 | IXGBE_MRQC_RSS_FIELD_IPV4
1678 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1679 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1680 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1681 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1682 | IXGBE_MRQC_RSS_FIELD_IPV6
1683 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1684 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1685 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
9a799d71 1686 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1687 }
9a799d71 1688
021230d4
AV		 1689 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1690
1691 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1692 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1693 /* Disable indicating checksum in descriptor, enables
1694 * RSS hash */
9a799d71 1695 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1696 }
021230d4
AV		 1697 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1698 /* Enable IPv4 payload checksum for UDP fragments
1699 * if PCSD is not set */
1700 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1701 }
1702
1703 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1704}
1705
068c89b0
DS		 1706static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1707{
1708 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1709 struct ixgbe_hw *hw = &adapter->hw;
1710
1711 /* add VID to filter table */
1712 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1713}
1714
1715static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1716{
1717 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1718 struct ixgbe_hw *hw = &adapter->hw;
1719
1720 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1721 ixgbe_irq_disable(adapter);
1722
1723 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1724
1725 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1726 ixgbe_irq_enable(adapter);
1727
1728 /* remove VID from filter table */
1729 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1730}
1731
9a799d71 1732static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1733 struct vlan_group *grp)
9a799d71
AK		 1734{
1735 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1736 u32 ctrl;
1737
d4f80882
AV		 1738 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1739 ixgbe_irq_disable(adapter);
9a799d71
AK		 1740 adapter->vlgrp = grp;
1741
2f90b865
AD		 1742 /*
1743 * For a DCB driver, always enable VLAN tag stripping so we can
1744 * still receive traffic from a DCB-enabled host even if we're
1745 * not in DCB mode.
1746 */
1747 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1748 ctrl |= IXGBE_VLNCTRL_VME;
1749 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1750 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
068c89b0 1751 ixgbe_vlan_rx_add_vid(netdev, 0);
2f90b865 1752
9a799d71
AK		 1753 if (grp) {
1754 /* enable VLAN tag insert/strip */
1755 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1756 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1757 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1758 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1759 }
1760
d4f80882
AV		 1761 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1762 ixgbe_irq_enable(adapter);
9a799d71
AK		 1763}
1764
9a799d71
AK		 1765static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1766{
1767 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1768
1769 if (adapter->vlgrp) {
1770 u16 vid;
1771 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1772 if (!vlan_group_get_device(adapter->vlgrp, vid))
1773 continue;
1774 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1775 }
1776 }
1777}
1778
2c5645cf
CL		 1779static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1780{
1781 struct dev_mc_list *mc_ptr;
1782 u8 *addr = *mc_addr_ptr;
1783 *vmdq = 0;
1784
1785 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1786 if (mc_ptr->next)
1787 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1788 else
1789 *mc_addr_ptr = NULL;
1790
1791 return addr;
1792}
1793
9a799d71 1794/**
2c5645cf 1795 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1796 * @netdev: network interface device structure
1797 *
2c5645cf
CL		 1798 * The set_rx_method entry point is called whenever the unicast/multicast
1799 * address list or the network interface flags are updated. This routine is
1800 * responsible for configuring the hardware for proper unicast, multicast and
1801 * promiscuous mode.
9a799d71 1802 **/
2c5645cf 1803static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1804{
1805 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1806 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1807 u32 fctrl, vlnctrl;
2c5645cf
CL		 1808 u8 *addr_list = NULL;
1809 int addr_count = 0;
9a799d71
AK		 1810
1811 /* Check for Promiscuous and All Multicast modes */
1812
1813 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1814 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1815
1816 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1817 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1818 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1819 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1820 } else {
746b9f02
PM		 1821 if (netdev->flags & IFF_ALLMULTI) {
1822 fctrl |= IXGBE_FCTRL_MPE;
1823 fctrl &= ~IXGBE_FCTRL_UPE;
1824 } else {
1825 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1826 }
3d01625a 1827 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 1828 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 1829 }
1830
1831 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1832 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 1833
2c5645cf
CL		 1834 /* reprogram secondary unicast list */
1835 addr_count = netdev->uc_count;
1836 if (addr_count)
1837 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 1838 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1839 ixgbe_addr_list_itr);
9a799d71 1840
2c5645cf
CL		 1841 /* reprogram multicast list */
1842 addr_count = netdev->mc_count;
1843 if (addr_count)
1844 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 1845 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1846 ixgbe_addr_list_itr);
9a799d71
AK		 1847}
1848
021230d4
AV		 1849static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1850{
1851 int q_idx;
1852 struct ixgbe_q_vector *q_vector;
1853 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1854
1855 /* legacy and MSI only use one vector */
1856 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1857 q_vectors = 1;
1858
1859 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 1860 struct napi_struct *napi;
021230d4
AV		 1861 q_vector = &adapter->q_vector[q_idx];
1862 if (!q_vector->rxr_count)
1863 continue;
f0848276
JB		 1864 napi = &q_vector->napi;
1865 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1866 (q_vector->rxr_count > 1))
1867 napi->poll = &ixgbe_clean_rxonly_many;
1868
1869 napi_enable(napi);
021230d4
AV		 1870 }
1871}
1872
1873static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1874{
1875 int q_idx;
1876 struct ixgbe_q_vector *q_vector;
1877 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1878
1879 /* legacy and MSI only use one vector */
1880 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1881 q_vectors = 1;
1882
1883 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1884 q_vector = &adapter->q_vector[q_idx];
1885 if (!q_vector->rxr_count)
1886 continue;
1887 napi_disable(&q_vector->napi);
1888 }
1889}
1890
7a6b6f51 1891#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 1892/*
1893 * ixgbe_configure_dcb - Configure DCB hardware
1894 * @adapter: ixgbe adapter struct
1895 *
1896 * This is called by the driver on open to configure the DCB hardware.
1897 * This is also called by the gennetlink interface when reconfiguring
1898 * the DCB state.
1899 */
1900static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
1901{
1902 struct ixgbe_hw *hw = &adapter->hw;
1903 u32 txdctl, vlnctrl;
1904 int i, j;
1905
1906 ixgbe_dcb_check_config(&adapter->dcb_cfg);
1907 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
1908 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
1909
1910 /* reconfigure the hardware */
1911 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
1912
1913 for (i = 0; i < adapter->num_tx_queues; i++) {
1914 j = adapter->tx_ring[i].reg_idx;
1915 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
1916 /* PThresh workaround for Tx hang with DFP enabled. */
1917 txdctl |= 32;
1918 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1919 }
1920 /* Enable VLAN tag insert/strip */
1921 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1922 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1923 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1924 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1925 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
1926}
1927
1928#endif
9a799d71
AK		 1929static void ixgbe_configure(struct ixgbe_adapter *adapter)
1930{
1931 struct net_device *netdev = adapter->netdev;
1932 int i;
1933
2c5645cf 1934 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 1935
1936 ixgbe_restore_vlan(adapter);
7a6b6f51 1937#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 1938 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1939 netif_set_gso_max_size(netdev, 32768);
1940 ixgbe_configure_dcb(adapter);
1941 } else {
1942 netif_set_gso_max_size(netdev, 65536);
1943 }
1944#else
1945 netif_set_gso_max_size(netdev, 65536);
1946#endif
9a799d71
AK		 1947
1948 ixgbe_configure_tx(adapter);
1949 ixgbe_configure_rx(adapter);
1950 for (i = 0; i < adapter->num_rx_queues; i++)
1951 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 1952 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 1953}
1954
1955static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1956{
1957 struct net_device *netdev = adapter->netdev;
9a799d71 1958 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1959 int i, j = 0;
9a799d71 1960 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1961 u32 txdctl, rxdctl, mhadd;
1962 u32 gpie;
9a799d71 1963
5eba3699
AV		 1964 ixgbe_get_hw_control(adapter);
1965
021230d4
AV		 1966 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1967 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1968 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1969 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 1970 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 1971 } else {
1972 /* MSI only */
021230d4 1973 gpie = 0;
9a799d71 1974 }
021230d4
AV		 1975 /* XXX: to interrupt immediately for EICS writes, enable this */
1976 /* gpie |= IXGBE_GPIE_EIMEN; */
1977 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1978 }
1979
021230d4
AV		 1980 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1981 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1982 * specifically only auto mask tx and rx interrupts */
1983 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1984 }
9a799d71 1985
0befdb3e
JB		 1986 /* Enable fan failure interrupt if media type is copper */
1987 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
1988 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
1989 gpie |= IXGBE_SDP1_GPIEN;
1990 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
1991 }
1992
021230d4 1993 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 1994 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1995 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1996 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1997
1998 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1999 }
2000
2001 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2002 j = adapter->tx_ring[i].reg_idx;
2003 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2004 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2005 txdctl |= (8 << 16);
9a799d71 2006 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2007 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2008 }
2009
2010 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 2011 j = adapter->rx_ring[i].reg_idx;
2012 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2013 /* enable PTHRESH=32 descriptors (half the internal cache)
2014 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2015 * this also removes a pesky rx_no_buffer_count increment */
2016 rxdctl |= 0x0020;
9a799d71 2017 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2018 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 2019 }
2020 /* enable all receives */
2021 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2022 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2023 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
2024
2025 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2026 ixgbe_configure_msix(adapter);
2027 else
2028 ixgbe_configure_msi_and_legacy(adapter);
2029
7adf1525
PWJ		 2030 ixgbe_napi_add_all(adapter);
2031
9a799d71 2032 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2033 ixgbe_napi_enable_all(adapter);
2034
2035 /* clear any pending interrupts, may auto mask */
2036 IXGBE_READ_REG(hw, IXGBE_EICR);
2037
9a799d71
AK		 2038 ixgbe_irq_enable(adapter);
2039
1da100bb
PWJ		 2040 /* enable transmits */
2041 netif_tx_start_all_queues(netdev);
2042
9a799d71
AK		 2043 /* bring the link up in the watchdog, this could race with our first
2044 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2045 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2046 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2047 mod_timer(&adapter->watchdog_timer, jiffies);
2048 return 0;
2049}
2050
d4f80882
AV		 2051void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2052{
2053 WARN_ON(in_interrupt());
2054 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2055 msleep(1);
2056 ixgbe_down(adapter);
2057 ixgbe_up(adapter);
2058 clear_bit(__IXGBE_RESETTING, &adapter->state);
2059}
2060
9a799d71
AK		 2061int ixgbe_up(struct ixgbe_adapter *adapter)
2062{
2063 /* hardware has been reset, we need to reload some things */
2064 ixgbe_configure(adapter);
2065
2066 return ixgbe_up_complete(adapter);
2067}
2068
2069void ixgbe_reset(struct ixgbe_adapter *adapter)
2070{
c44ade9e
JB		 2071 struct ixgbe_hw *hw = &adapter->hw;
2072 if (hw->mac.ops.init_hw(hw))
2073 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2074
2075 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2076 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2077
2078}
2079
9a799d71
AK		 2080/**
2081 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2082 * @adapter: board private structure
2083 * @rx_ring: ring to free buffers from
2084 **/
2085static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2086 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2087{
2088 struct pci_dev *pdev = adapter->pdev;
2089 unsigned long size;
2090 unsigned int i;
2091
2092 /* Free all the Rx ring sk_buffs */
2093
2094 for (i = 0; i < rx_ring->count; i++) {
2095 struct ixgbe_rx_buffer *rx_buffer_info;
2096
2097 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2098 if (rx_buffer_info->dma) {
2099 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2100 rx_ring->rx_buf_len,
2101 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2102 rx_buffer_info->dma = 0;
2103 }
2104 if (rx_buffer_info->skb) {
2105 dev_kfree_skb(rx_buffer_info->skb);
2106 rx_buffer_info->skb = NULL;
2107 }
2108 if (!rx_buffer_info->page)
2109 continue;
762f4c57
JB		 2110 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2111 PCI_DMA_FROMDEVICE);
9a799d71 2112 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2113 put_page(rx_buffer_info->page);
2114 rx_buffer_info->page = NULL;
762f4c57 2115 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2116 }
2117
2118 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2119 memset(rx_ring->rx_buffer_info, 0, size);
2120
2121 /* Zero out the descriptor ring */
2122 memset(rx_ring->desc, 0, rx_ring->size);
2123
2124 rx_ring->next_to_clean = 0;
2125 rx_ring->next_to_use = 0;
2126
2127 writel(0, adapter->hw.hw_addr + rx_ring->head);
2128 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2129}
2130
2131/**
2132 * ixgbe_clean_tx_ring - Free Tx Buffers
2133 * @adapter: board private structure
2134 * @tx_ring: ring to be cleaned
2135 **/
2136static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2137 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2138{
2139 struct ixgbe_tx_buffer *tx_buffer_info;
2140 unsigned long size;
2141 unsigned int i;
2142
2143 /* Free all the Tx ring sk_buffs */
2144
2145 for (i = 0; i < tx_ring->count; i++) {
2146 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2147 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2148 }
2149
2150 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2151 memset(tx_ring->tx_buffer_info, 0, size);
2152
2153 /* Zero out the descriptor ring */
2154 memset(tx_ring->desc, 0, tx_ring->size);
2155
2156 tx_ring->next_to_use = 0;
2157 tx_ring->next_to_clean = 0;
2158
2159 writel(0, adapter->hw.hw_addr + tx_ring->head);
2160 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2161}
2162
2163/**
021230d4 2164 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2165 * @adapter: board private structure
2166 **/
021230d4 2167static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2168{
2169 int i;
2170
021230d4
AV		 2171 for (i = 0; i < adapter->num_rx_queues; i++)
2172 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2173}
2174
2175/**
021230d4 2176 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2177 * @adapter: board private structure
2178 **/
021230d4 2179static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2180{
2181 int i;
2182
021230d4
AV		 2183 for (i = 0; i < adapter->num_tx_queues; i++)
2184 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2185}
2186
2187void ixgbe_down(struct ixgbe_adapter *adapter)
2188{
2189 struct net_device *netdev = adapter->netdev;
7f821875 2190 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2191 u32 rxctrl;
7f821875
JB		 2192 u32 txdctl;
2193 int i, j;
9a799d71
AK		 2194
2195 /* signal that we are down to the interrupt handler */
2196 set_bit(__IXGBE_DOWN, &adapter->state);
2197
2198 /* disable receives */
7f821875
JB		 2199 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2200 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2201
2202 netif_tx_disable(netdev);
2203
7f821875 2204 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2205 msleep(10);
2206
7f821875
JB		 2207 netif_tx_stop_all_queues(netdev);
2208
9a799d71
AK		 2209 ixgbe_irq_disable(adapter);
2210
021230d4 2211 ixgbe_napi_disable_all(adapter);
7f821875 2212
9a799d71 2213 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2214 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2215
7f821875
JB		 2216 /* disable transmits in the hardware now that interrupts are off */
2217 for (i = 0; i < adapter->num_tx_queues; i++) {
2218 j = adapter->tx_ring[i].reg_idx;
2219 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2220 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2221 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2222 }
2223
9a799d71 2224 netif_carrier_off(netdev);
9a799d71 2225
5dd2d332 2226#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2227 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2228 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2229 dca_remove_requester(&adapter->pdev->dev);
2230 }
2231
2232#endif
6f4a0e45
PL		 2233 if (!pci_channel_offline(adapter->pdev))
2234 ixgbe_reset(adapter);
9a799d71
AK		 2235 ixgbe_clean_all_tx_rings(adapter);
2236 ixgbe_clean_all_rx_rings(adapter);
2237
5dd2d332 2238#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2239 /* since we reset the hardware DCA settings were cleared */
2240 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2241 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2242 /* always use CB2 mode, difference is masked
2243 * in the CB driver */
b4617240 2244 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2245 ixgbe_setup_dca(adapter);
2246 }
2247#endif
9a799d71
AK		 2248}
2249
9a799d71 2250/**
021230d4
AV		 2251 * ixgbe_poll - NAPI Rx polling callback
2252 * @napi: structure for representing this polling device
2253 * @budget: how many packets driver is allowed to clean
2254 *
2255 * This function is used for legacy and MSI, NAPI mode
9a799d71 2256 **/
021230d4 2257static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2258{
021230d4 2259 struct ixgbe_q_vector *q_vector = container_of(napi,
b4617240 2260 struct ixgbe_q_vector, napi);
021230d4 2261 struct ixgbe_adapter *adapter = q_vector->adapter;
74ce8dd2 2262 int tx_cleaned, work_done = 0;
9a799d71 2263
5dd2d332 2264#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2265 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2266 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2267 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2268 }
2269#endif
2270
d2c7ddd6 2271 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2272 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2273
d2c7ddd6
DM		 2274 if (tx_cleaned)
2275 work_done = budget;
2276
53e52c72
DM		 2277 /* If budget not fully consumed, exit the polling mode */
2278 if (work_done < budget) {
288379f0 2279 napi_complete(napi);
30efa5a3 2280 if (adapter->itr_setting & 3)
f494e8fa 2281 ixgbe_set_itr(adapter);
d4f80882
AV		 2282 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2283 ixgbe_irq_enable(adapter);
9a799d71 2284 }
9a799d71
AK		 2285 return work_done;
2286}
2287
2288/**
2289 * ixgbe_tx_timeout - Respond to a Tx Hang
2290 * @netdev: network interface device structure
2291 **/
2292static void ixgbe_tx_timeout(struct net_device *netdev)
2293{
2294 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2295
2296 /* Do the reset outside of interrupt context */
2297 schedule_work(&adapter->reset_task);
2298}
2299
2300static void ixgbe_reset_task(struct work_struct *work)
2301{
2302 struct ixgbe_adapter *adapter;
2303 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2304
2f90b865
AD		 2305 /* If we're already down or resetting, just bail */
2306 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2307 test_bit(__IXGBE_RESETTING, &adapter->state))
2308 return;
2309
9a799d71
AK		 2310 adapter->tx_timeout_count++;
2311
d4f80882 2312 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2313}
2314
b9804972
JB		 2315static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2316{
2317 int nrq = 1, ntq = 1;
2318 int feature_mask = 0, rss_i, rss_m;
2f90b865 2319 int dcb_i, dcb_m;
b9804972
JB		 2320
2321 /* Number of supported queues */
2322 switch (adapter->hw.mac.type) {
2323 case ixgbe_mac_82598EB:
2f90b865
AD		 2324 dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2325 dcb_m = 0;
b9804972
JB		 2326 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2327 rss_m = 0;
2328 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 2329 feature_mask |= IXGBE_FLAG_DCB_ENABLED;
b9804972
JB		 2330
2331 switch (adapter->flags & feature_mask) {
2f90b865
AD		 2332 case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_DCB_ENABLED):
2333 dcb_m = 0x7 << 3;
2334 rss_i = min(8, rss_i);
2335 rss_m = 0x7;
2336 nrq = dcb_i * rss_i;
2337 ntq = min(MAX_TX_QUEUES, dcb_i * rss_i);
2338 break;
2339 case (IXGBE_FLAG_DCB_ENABLED):
2340 dcb_m = 0x7 << 3;
2341 nrq = dcb_i;
2342 ntq = dcb_i;
2343 break;
b9804972
JB		 2344 case (IXGBE_FLAG_RSS_ENABLED):
2345 rss_m = 0xF;
2346 nrq = rss_i;
2347 ntq = rss_i;
2348 break;
2349 case 0:
2350 default:
2f90b865
AD		 2351 dcb_i = 0;
2352 dcb_m = 0;
b9804972
JB		 2353 rss_i = 0;
2354 rss_m = 0;
2355 nrq = 1;
2356 ntq = 1;
2357 break;
2358 }
2359
2f90b865
AD		 2360 /* Sanity check, we should never have zero queues */
2361 nrq = (nrq ?:1);
2362 ntq = (ntq ?:1);
2363
2364 adapter->ring_feature[RING_F_DCB].indices = dcb_i;
2365 adapter->ring_feature[RING_F_DCB].mask = dcb_m;
b9804972
JB		 2366 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2367 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2368 break;
2369 default:
2370 nrq = 1;
2371 ntq = 1;
2372 break;
2373 }
2374
2375 adapter->num_rx_queues = nrq;
2376 adapter->num_tx_queues = ntq;
2377}
2378
021230d4 2379static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2380 int vectors)
021230d4
AV		 2381{
2382 int err, vector_threshold;
2383
2384 /* We'll want at least 3 (vector_threshold):
2385 * 1) TxQ[0] Cleanup
2386 * 2) RxQ[0] Cleanup
2387 * 3) Other (Link Status Change, etc.)
2388 * 4) TCP Timer (optional)
2389 */
2390 vector_threshold = MIN_MSIX_COUNT;
2391
2392 /* The more we get, the more we will assign to Tx/Rx Cleanup
2393 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2394 * Right now, we simply care about how many we'll get; we'll
2395 * set them up later while requesting irq's.
2396 */
2397 while (vectors >= vector_threshold) {
2398 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2399 vectors);
021230d4
AV		 2400 if (!err) /* Success in acquiring all requested vectors. */
2401 break;
2402 else if (err < 0)
2403 vectors = 0; /* Nasty failure, quit now */
2404 else /* err == number of vectors we should try again with */
2405 vectors = err;
2406 }
2407
2408 if (vectors < vector_threshold) {
2409 /* Can't allocate enough MSI-X interrupts? Oh well.
2410 * This just means we'll go with either a single MSI
2411 * vector or fall back to legacy interrupts.
2412 */
2413 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2414 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2415 kfree(adapter->msix_entries);
2416 adapter->msix_entries = NULL;
2f90b865 2417 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4 2418 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2419 ixgbe_set_num_queues(adapter);
021230d4
AV		 2420 } else {
2421 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2422 adapter->num_msix_vectors = vectors;
2423 }
2424}
2425
021230d4
AV		 2426/**
2427 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2428 * @adapter: board private structure to initialize
2429 *
2430 * Once we know the feature-set enabled for the device, we'll cache
2431 * the register offset the descriptor ring is assigned to.
2432 **/
feea6a57 2433static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
021230d4 2434{
021230d4
AV		 2435 int feature_mask = 0, rss_i;
2436 int i, txr_idx, rxr_idx;
2f90b865 2437 int dcb_i;
021230d4
AV		 2438
2439 /* Number of supported queues */
2440 switch (adapter->hw.mac.type) {
2441 case ixgbe_mac_82598EB:
2f90b865 2442 dcb_i = adapter->ring_feature[RING_F_DCB].indices;
021230d4
AV		 2443 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2444 txr_idx = 0;
2445 rxr_idx = 0;
2f90b865 2446 feature_mask |= IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 2447 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2448 switch (adapter->flags & feature_mask) {
2f90b865
AD		 2449 case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_DCB_ENABLED):
2450 for (i = 0; i < dcb_i; i++) {
2451 int j;
2452 /* Rx first */
2453 for (j = 0; j < adapter->num_rx_queues; j++) {
2454 adapter->rx_ring[rxr_idx].reg_idx =
2455 i << 3 | j;
2456 rxr_idx++;
2457 }
2458 /* Tx now */
2459 for (j = 0; j < adapter->num_tx_queues; j++) {
2460 adapter->tx_ring[txr_idx].reg_idx =
2461 i << 2 | (j >> 1);
2462 if (j & 1)
2463 txr_idx++;
2464 }
2465 }
2466 case (IXGBE_FLAG_DCB_ENABLED):
2467 /* the number of queues is assumed to be symmetric */
2468 for (i = 0; i < dcb_i; i++) {
2469 adapter->rx_ring[i].reg_idx = i << 3;
2470 adapter->tx_ring[i].reg_idx = i << 2;
2471 }
2472 break;
021230d4
AV		 2473 case (IXGBE_FLAG_RSS_ENABLED):
2474 for (i = 0; i < adapter->num_rx_queues; i++)
2475 adapter->rx_ring[i].reg_idx = i;
2476 for (i = 0; i < adapter->num_tx_queues; i++)
2477 adapter->tx_ring[i].reg_idx = i;
2478 break;
2479 case 0:
2480 default:
2481 break;
2482 }
2483 break;
2484 default:
2485 break;
2486 }
2487}
2488
9a799d71
AK		 2489/**
2490 * ixgbe_alloc_queues - Allocate memory for all rings
2491 * @adapter: board private structure to initialize
2492 *
2493 * We allocate one ring per queue at run-time since we don't know the
a4d2f34b 2494 * number of queues at compile-time.
9a799d71 2495 **/
2f90b865 2496static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 2497{
2498 int i;
2499
2500 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 2501 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 2502 if (!adapter->tx_ring)
021230d4 2503 goto err_tx_ring_allocation;
9a799d71
AK		 2504
2505 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 2506 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2507 if (!adapter->rx_ring)
2508 goto err_rx_ring_allocation;
9a799d71 2509
021230d4 2510 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 2511 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 2512 adapter->tx_ring[i].queue_index = i;
2513 }
b9804972 2514
9a799d71 2515 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 2516 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 2517 adapter->rx_ring[i].queue_index = i;
2518 }
2519
2520 ixgbe_cache_ring_register(adapter);
2521
2522 return 0;
2523
2524err_rx_ring_allocation:
2525 kfree(adapter->tx_ring);
2526err_tx_ring_allocation:
2527 return -ENOMEM;
2528}
2529
2530/**
2531 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2532 * @adapter: board private structure to initialize
2533 *
2534 * Attempt to configure the interrupts using the best available
2535 * capabilities of the hardware and the kernel.
2536 **/
feea6a57 2537static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 2538{
2539 int err = 0;
2540 int vector, v_budget;
2541
2542 /*
2543 * It's easy to be greedy for MSI-X vectors, but it really
2544 * doesn't do us much good if we have a lot more vectors
2545 * than CPU's. So let's be conservative and only ask for
2546 * (roughly) twice the number of vectors as there are CPU's.
2547 */
2548 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 2549 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 2550
2551 /*
2552 * At the same time, hardware can only support a maximum of
2553 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2554 * we can easily reach upwards of 64 Rx descriptor queues and
2555 * 32 Tx queues. Thus, we cap it off in those rare cases where
2556 * the cpu count also exceeds our vector limit.
2557 */
2558 v_budget = min(v_budget, MAX_MSIX_COUNT);
2559
2560 /* A failure in MSI-X entry allocation isn't fatal, but it does
2561 * mean we disable MSI-X capabilities of the adapter. */
2562 adapter->msix_entries = kcalloc(v_budget,
b4617240 2563 sizeof(struct msix_entry), GFP_KERNEL);
021230d4 2564 if (!adapter->msix_entries) {
2f90b865 2565 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 2566 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2567 ixgbe_set_num_queues(adapter);
2568 kfree(adapter->tx_ring);
2569 kfree(adapter->rx_ring);
2570 err = ixgbe_alloc_queues(adapter);
2571 if (err) {
2572 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 2573 "for queues\n");
021230d4
AV		 2574 goto out;
2575 }
2576
2577 goto try_msi;
2578 }
2579
2580 for (vector = 0; vector < v_budget; vector++)
2581 adapter->msix_entries[vector].entry = vector;
2582
2583 ixgbe_acquire_msix_vectors(adapter, v_budget);
2584
2585 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2586 goto out;
2587
2588try_msi:
2589 err = pci_enable_msi(adapter->pdev);
2590 if (!err) {
2591 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2592 } else {
2593 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 2594 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 2595 /* reset err */
2596 err = 0;
2597 }
2598
2599out:
30eba97a 2600 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2601 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2602
2603 return err;
2604}
2605
2f90b865 2606void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 2607{
2608 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2609 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2610 pci_disable_msix(adapter->pdev);
2611 kfree(adapter->msix_entries);
2612 adapter->msix_entries = NULL;
2613 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2614 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2615 pci_disable_msi(adapter->pdev);
2616 }
2617 return;
2618}
2619
2620/**
2621 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2622 * @adapter: board private structure to initialize
2623 *
2624 * We determine which interrupt scheme to use based on...
2625 * - Kernel support (MSI, MSI-X)
2626 * - which can be user-defined (via MODULE_PARAM)
2627 * - Hardware queue count (num_*_queues)
2628 * - defined by miscellaneous hardware support/features (RSS, etc.)
2629 **/
2f90b865 2630int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 2631{
2632 int err;
2633
2634 /* Number of supported queues */
2635 ixgbe_set_num_queues(adapter);
2636
2637 err = ixgbe_alloc_queues(adapter);
2638 if (err) {
2639 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2640 goto err_alloc_queues;
2641 }
2642
2643 err = ixgbe_set_interrupt_capability(adapter);
2644 if (err) {
2645 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2646 goto err_set_interrupt;
9a799d71
AK		 2647 }
2648
021230d4 2649 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 2650 "Tx Queue count = %u\n",
2651 (adapter->num_rx_queues > 1) ? "Enabled" :
2652 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 2653
2654 set_bit(__IXGBE_DOWN, &adapter->state);
2655
9a799d71 2656 return 0;
021230d4
AV		 2657
2658err_set_interrupt:
2659 kfree(adapter->tx_ring);
2660 kfree(adapter->rx_ring);
2661err_alloc_queues:
2662 return err;
9a799d71
AK		 2663}
2664
c4900be0
DS		 2665/**
2666 * ixgbe_sfp_timer - worker thread to find a missing module
2667 * @data: pointer to our adapter struct
2668 **/
2669static void ixgbe_sfp_timer(unsigned long data)
2670{
2671 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2672
2673 /* Do the sfp_timer outside of interrupt context due to the
2674 * delays that sfp+ detection requires
2675 */
2676 schedule_work(&adapter->sfp_task);
2677}
2678
2679/**
2680 * ixgbe_sfp_task - worker thread to find a missing module
2681 * @work: pointer to work_struct containing our data
2682 **/
2683static void ixgbe_sfp_task(struct work_struct *work)
2684{
2685 struct ixgbe_adapter *adapter = container_of(work,
2686 struct ixgbe_adapter,
2687 sfp_task);
2688 struct ixgbe_hw *hw = &adapter->hw;
2689
2690 if ((hw->phy.type == ixgbe_phy_nl) &&
2691 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
2692 s32 ret = hw->phy.ops.identify_sfp(hw);
2693 if (ret)
2694 goto reschedule;
2695 ret = hw->phy.ops.reset(hw);
2696 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2697 DPRINTK(PROBE, ERR, "failed to initialize because an "
2698 "unsupported SFP+ module type was detected.\n"
2699 "Reload the driver after installing a "
2700 "supported module.\n");
2701 unregister_netdev(adapter->netdev);
2702 } else {
2703 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
2704 hw->phy.sfp_type);
2705 }
2706 /* don't need this routine any more */
2707 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2708 }
2709 return;
2710reschedule:
2711 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
2712 mod_timer(&adapter->sfp_timer,
2713 round_jiffies(jiffies + (2 * HZ)));
2714}
2715
9a799d71
AK		 2716/**
2717 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2718 * @adapter: board private structure to initialize
2719 *
2720 * ixgbe_sw_init initializes the Adapter private data structure.
2721 * Fields are initialized based on PCI device information and
2722 * OS network device settings (MTU size).
2723 **/
2724static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2725{
2726 struct ixgbe_hw *hw = &adapter->hw;
2727 struct pci_dev *pdev = adapter->pdev;
021230d4 2728 unsigned int rss;
7a6b6f51 2729#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2730 int j;
2731 struct tc_configuration *tc;
2732#endif
021230d4 2733
c44ade9e
JB		 2734 /* PCI config space info */
2735
2736 hw->vendor_id = pdev->vendor;
2737 hw->device_id = pdev->device;
2738 hw->revision_id = pdev->revision;
2739 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2740 hw->subsystem_device_id = pdev->subsystem_device;
2741
021230d4
AV		 2742 /* Set capability flags */
2743 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2744 adapter->ring_feature[RING_F_RSS].indices = rss;
2745 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865
AD		 2746 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
2747
7a6b6f51 2748#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2749 /* Configure DCB traffic classes */
2750 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
2751 tc = &adapter->dcb_cfg.tc_config[j];
2752 tc->path[DCB_TX_CONFIG].bwg_id = 0;
2753 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
2754 tc->path[DCB_RX_CONFIG].bwg_id = 0;
2755 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
2756 tc->dcb_pfc = pfc_disabled;
2757 }
2758 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
2759 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
2760 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
2761 adapter->dcb_cfg.round_robin_enable = false;
2762 adapter->dcb_set_bitmap = 0x00;
2763 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
2764 adapter->ring_feature[RING_F_DCB].indices);
2765
2766#endif
0befdb3e
JB		 2767 if (hw->mac.ops.get_media_type &&
2768 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper))
2769 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
9a799d71
AK		 2770
2771 /* default flow control settings */
2b9ade93
JB		 2772 hw->fc.original_type = ixgbe_fc_none;
2773 hw->fc.type = ixgbe_fc_none;
2774 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2775 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2776 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2777 hw->fc.send_xon = true;
9a799d71 2778
021230d4 2779 /* select 10G link by default */
9a799d71 2780 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
9a799d71 2781
30efa5a3
JB		 2782 /* enable itr by default in dynamic mode */
2783 adapter->itr_setting = 1;
2784 adapter->eitr_param = 20000;
2785
2786 /* set defaults for eitr in MegaBytes */
2787 adapter->eitr_low = 10;
2788 adapter->eitr_high = 20;
2789
2790 /* set default ring sizes */
2791 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2792 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2793
9a799d71 2794 /* initialize eeprom parameters */
c44ade9e 2795 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 2796 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2797 return -EIO;
2798 }
2799
021230d4 2800 /* enable rx csum by default */
9a799d71
AK		 2801 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2802
9a799d71
AK		 2803 set_bit(__IXGBE_DOWN, &adapter->state);
2804
2805 return 0;
2806}
2807
2808/**
2809 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2810 * @adapter: board private structure
3a581073 2811 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2812 *
2813 * Return 0 on success, negative on failure
2814 **/
2815int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2816 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2817{
2818 struct pci_dev *pdev = adapter->pdev;
2819 int size;
2820
3a581073
JB		 2821 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2822 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 2823 if (!tx_ring->tx_buffer_info)
2824 goto err;
3a581073 2825 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 2826
2827 /* round up to nearest 4K */
e01c31a5
JB		 2828 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2829 sizeof(u32);
3a581073 2830 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 2831
3a581073
JB		 2832 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2833 &tx_ring->dma);
e01c31a5
JB		 2834 if (!tx_ring->desc)
2835 goto err;
9a799d71 2836
3a581073
JB		 2837 tx_ring->next_to_use = 0;
2838 tx_ring->next_to_clean = 0;
2839 tx_ring->work_limit = tx_ring->count;
9a799d71 2840 return 0;
e01c31a5
JB		 2841
2842err:
2843 vfree(tx_ring->tx_buffer_info);
2844 tx_ring->tx_buffer_info = NULL;
2845 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2846 "descriptor ring\n");
2847 return -ENOMEM;
9a799d71
AK		 2848}
2849
69888674
AD		 2850/**
2851 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2852 * @adapter: board private structure
2853 *
2854 * If this function returns with an error, then it's possible one or
2855 * more of the rings is populated (while the rest are not). It is the
2856 * callers duty to clean those orphaned rings.
2857 *
2858 * Return 0 on success, negative on failure
2859 **/
2860static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2861{
2862 int i, err = 0;
2863
2864 for (i = 0; i < adapter->num_tx_queues; i++) {
2865 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2866 if (!err)
2867 continue;
2868 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2869 break;
2870 }
2871
2872 return err;
2873}
2874
9a799d71
AK		 2875/**
2876 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2877 * @adapter: board private structure
3a581073 2878 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2879 *
2880 * Returns 0 on success, negative on failure
2881 **/
2882int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 2883 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2884{
2885 struct pci_dev *pdev = adapter->pdev;
021230d4 2886 int size;
9a799d71 2887
3a581073
JB		 2888 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2889 rx_ring->rx_buffer_info = vmalloc(size);
2890 if (!rx_ring->rx_buffer_info) {
9a799d71 2891 DPRINTK(PROBE, ERR,
b4617240 2892 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2893 goto alloc_failed;
9a799d71 2894 }
3a581073 2895 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 2896
9a799d71 2897 /* Round up to nearest 4K */
3a581073
JB		 2898 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2899 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 2900
3a581073 2901 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 2902
3a581073 2903 if (!rx_ring->desc) {
9a799d71 2904 DPRINTK(PROBE, ERR,
b4617240 2905 "Memory allocation failed for the rx desc ring\n");
3a581073 2906 vfree(rx_ring->rx_buffer_info);
177db6ff 2907 goto alloc_failed;
9a799d71
AK		 2908 }
2909
3a581073
JB		 2910 rx_ring->next_to_clean = 0;
2911 rx_ring->next_to_use = 0;
9a799d71
AK		 2912
2913 return 0;
177db6ff
MC		 2914
2915alloc_failed:
177db6ff 2916 return -ENOMEM;
9a799d71
AK		 2917}
2918
69888674
AD		 2919/**
2920 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2921 * @adapter: board private structure
2922 *
2923 * If this function returns with an error, then it's possible one or
2924 * more of the rings is populated (while the rest are not). It is the
2925 * callers duty to clean those orphaned rings.
2926 *
2927 * Return 0 on success, negative on failure
2928 **/
2929
2930static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2931{
2932 int i, err = 0;
2933
2934 for (i = 0; i < adapter->num_rx_queues; i++) {
2935 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2936 if (!err)
2937 continue;
2938 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2939 break;
2940 }
2941
2942 return err;
2943}
2944
9a799d71
AK		 2945/**
2946 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2947 * @adapter: board private structure
2948 * @tx_ring: Tx descriptor ring for a specific queue
2949 *
2950 * Free all transmit software resources
2951 **/
c431f97e
JB		 2952void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2953 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2954{
2955 struct pci_dev *pdev = adapter->pdev;
2956
2957 ixgbe_clean_tx_ring(adapter, tx_ring);
2958
2959 vfree(tx_ring->tx_buffer_info);
2960 tx_ring->tx_buffer_info = NULL;
2961
2962 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2963
2964 tx_ring->desc = NULL;
2965}
2966
2967/**
2968 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2969 * @adapter: board private structure
2970 *
2971 * Free all transmit software resources
2972 **/
2973static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2974{
2975 int i;
2976
2977 for (i = 0; i < adapter->num_tx_queues; i++)
2978 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2979}
2980
2981/**
b4617240 2982 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 2983 * @adapter: board private structure
2984 * @rx_ring: ring to clean the resources from
2985 *
2986 * Free all receive software resources
2987 **/
c431f97e
JB		 2988void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2989 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2990{
2991 struct pci_dev *pdev = adapter->pdev;
2992
2993 ixgbe_clean_rx_ring(adapter, rx_ring);
2994
2995 vfree(rx_ring->rx_buffer_info);
2996 rx_ring->rx_buffer_info = NULL;
2997
2998 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2999
3000 rx_ring->desc = NULL;
3001}
3002
3003/**
3004 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3005 * @adapter: board private structure
3006 *
3007 * Free all receive software resources
3008 **/
3009static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3010{
3011 int i;
3012
3013 for (i = 0; i < adapter->num_rx_queues; i++)
3014 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3015}
3016
9a799d71
AK		 3017/**
3018 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3019 * @netdev: network interface device structure
3020 * @new_mtu: new value for maximum frame size
3021 *
3022 * Returns 0 on success, negative on failure
3023 **/
3024static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3025{
3026 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3027 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3028
42c783c5
JB		 3029 /* MTU < 68 is an error and causes problems on some kernels */
3030 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3031 return -EINVAL;
3032
021230d4 3033 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3034 netdev->mtu, new_mtu);
021230d4 3035 /* must set new MTU before calling down or up */
9a799d71
AK		 3036 netdev->mtu = new_mtu;
3037
d4f80882
AV		 3038 if (netif_running(netdev))
3039 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3040
3041 return 0;
3042}
3043
3044/**
3045 * ixgbe_open - Called when a network interface is made active
3046 * @netdev: network interface device structure
3047 *
3048 * Returns 0 on success, negative value on failure
3049 *
3050 * The open entry point is called when a network interface is made
3051 * active by the system (IFF_UP). At this point all resources needed
3052 * for transmit and receive operations are allocated, the interrupt
3053 * handler is registered with the OS, the watchdog timer is started,
3054 * and the stack is notified that the interface is ready.
3055 **/
3056static int ixgbe_open(struct net_device *netdev)
3057{
3058 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3059 int err;
4bebfaa5
AK		 3060
3061 /* disallow open during test */
3062 if (test_bit(__IXGBE_TESTING, &adapter->state))
3063 return -EBUSY;
9a799d71 3064
9a799d71
AK		 3065 /* allocate transmit descriptors */
3066 err = ixgbe_setup_all_tx_resources(adapter);
3067 if (err)
3068 goto err_setup_tx;
3069
9a799d71
AK		 3070 /* allocate receive descriptors */
3071 err = ixgbe_setup_all_rx_resources(adapter);
3072 if (err)
3073 goto err_setup_rx;
3074
3075 ixgbe_configure(adapter);
3076
021230d4 3077 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3078 if (err)
3079 goto err_req_irq;
3080
9a799d71
AK		 3081 err = ixgbe_up_complete(adapter);
3082 if (err)
3083 goto err_up;
3084
d55b53ff
JK		 3085 netif_tx_start_all_queues(netdev);
3086
9a799d71
AK		 3087 return 0;
3088
3089err_up:
5eba3699 3090 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3091 ixgbe_free_irq(adapter);
3092err_req_irq:
3093 ixgbe_free_all_rx_resources(adapter);
3094err_setup_rx:
3095 ixgbe_free_all_tx_resources(adapter);
3096err_setup_tx:
3097 ixgbe_reset(adapter);
3098
3099 return err;
3100}
3101
3102/**
3103 * ixgbe_close - Disables a network interface
3104 * @netdev: network interface device structure
3105 *
3106 * Returns 0, this is not allowed to fail
3107 *
3108 * The close entry point is called when an interface is de-activated
3109 * by the OS. The hardware is still under the drivers control, but
3110 * needs to be disabled. A global MAC reset is issued to stop the
3111 * hardware, and all transmit and receive resources are freed.
3112 **/
3113static int ixgbe_close(struct net_device *netdev)
3114{
3115 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3116
3117 ixgbe_down(adapter);
3118 ixgbe_free_irq(adapter);
3119
3120 ixgbe_free_all_tx_resources(adapter);
3121 ixgbe_free_all_rx_resources(adapter);
3122
5eba3699 3123 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3124
3125 return 0;
3126}
3127
b3c8b4ba
AD		 3128/**
3129 * ixgbe_napi_add_all - prep napi structs for use
3130 * @adapter: private struct
3131 * helper function to napi_add each possible q_vector->napi
3132 */
2f90b865 3133void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3134{
3135 int q_idx, q_vectors;
7adf1525 3136 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 3137 int (*poll)(struct napi_struct *, int);
3138
7adf1525
PWJ		 3139 /* check if we already have our netdev->napi_list populated */
3140 if (&netdev->napi_list != netdev->napi_list.next)
3141 return;
3142
b3c8b4ba
AD		 3143 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3144 poll = &ixgbe_clean_rxonly;
3145 /* Only enable as many vectors as we have rx queues. */
3146 q_vectors = adapter->num_rx_queues;
3147 } else {
3148 poll = &ixgbe_poll;
3149 /* only one q_vector for legacy modes */
3150 q_vectors = 1;
3151 }
3152
3153 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3154 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3155 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3156 }
3157}
3158
2f90b865 3159void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3160{
3161 int q_idx;
3162 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3163
3164 /* legacy and MSI only use one vector */
3165 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3166 q_vectors = 1;
3167
3168 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3169 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3170 if (!q_vector->rxr_count)
3171 continue;
3172 netif_napi_del(&q_vector->napi);
3173 }
3174}
3175
3176#ifdef CONFIG_PM
3177static int ixgbe_resume(struct pci_dev *pdev)
3178{
3179 struct net_device *netdev = pci_get_drvdata(pdev);
3180 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3181 u32 err;
3182
3183 pci_set_power_state(pdev, PCI_D0);
3184 pci_restore_state(pdev);
3185 err = pci_enable_device(pdev);
3186 if (err) {
69888674 3187 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3188 "suspend\n");
3189 return err;
3190 }
3191 pci_set_master(pdev);
3192
3193 pci_enable_wake(pdev, PCI_D3hot, 0);
3194 pci_enable_wake(pdev, PCI_D3cold, 0);
3195
3196 err = ixgbe_init_interrupt_scheme(adapter);
3197 if (err) {
3198 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3199 "device\n");
3200 return err;
3201 }
3202
3203 ixgbe_napi_add_all(adapter);
3204 ixgbe_reset(adapter);
3205
3206 if (netif_running(netdev)) {
3207 err = ixgbe_open(adapter->netdev);
3208 if (err)
3209 return err;
3210 }
3211
3212 netif_device_attach(netdev);
3213
3214 return 0;
3215}
3216
3217#endif /* CONFIG_PM */
3218static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3219{
3220 struct net_device *netdev = pci_get_drvdata(pdev);
3221 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3222#ifdef CONFIG_PM
3223 int retval = 0;
3224#endif
3225
3226 netif_device_detach(netdev);
3227
3228 if (netif_running(netdev)) {
3229 ixgbe_down(adapter);
3230 ixgbe_free_irq(adapter);
3231 ixgbe_free_all_tx_resources(adapter);
3232 ixgbe_free_all_rx_resources(adapter);
3233 }
3234 ixgbe_reset_interrupt_capability(adapter);
3235 ixgbe_napi_del_all(adapter);
7adf1525 3236 INIT_LIST_HEAD(&netdev->napi_list);
b3c8b4ba
AD		 3237 kfree(adapter->tx_ring);
3238 kfree(adapter->rx_ring);
3239
3240#ifdef CONFIG_PM
3241 retval = pci_save_state(pdev);
3242 if (retval)
3243 return retval;
3244#endif
3245
3246 pci_enable_wake(pdev, PCI_D3hot, 0);
3247 pci_enable_wake(pdev, PCI_D3cold, 0);
3248
3249 ixgbe_release_hw_control(adapter);
3250
3251 pci_disable_device(pdev);
3252
3253 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3254
3255 return 0;
3256}
3257
3258static void ixgbe_shutdown(struct pci_dev *pdev)
3259{
3260 ixgbe_suspend(pdev, PMSG_SUSPEND);
3261}
3262
9a799d71
AK		 3263/**
3264 * ixgbe_update_stats - Update the board statistics counters.
3265 * @adapter: board private structure
3266 **/
3267void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3268{
3269 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3270 u64 total_mpc = 0;
3271 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 3272
3273 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3274 for (i = 0; i < 8; i++) {
3275 /* for packet buffers not used, the register should read 0 */
3276 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3277 missed_rx += mpc;
3278 adapter->stats.mpc[i] += mpc;
3279 total_mpc += adapter->stats.mpc[i];
3280 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3281 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3282 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3283 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3284 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3285 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3286 IXGBE_PXONRXC(i));
3287 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3288 IXGBE_PXONTXC(i));
3289 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3290 IXGBE_PXOFFRXC(i));
3291 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3292 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3293 }
3294 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3295 /* work around hardware counting issue */
3296 adapter->stats.gprc -= missed_rx;
3297
3298 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 3299 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 3300 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3301 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 3302 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3303 adapter->stats.bprc += bprc;
3304 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3305 adapter->stats.mprc -= bprc;
3306 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3307 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3308 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3309 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3310 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3311 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3312 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 3313 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3314 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 3315 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 3316 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3317 adapter->stats.lxontxc += lxon;
3318 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3319 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3320 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3321 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3322 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3323 /*
3324 * 82598 errata - tx of flow control packets is included in tx counters
3325 */
3326 xon_off_tot = lxon + lxoff;
3327 adapter->stats.gptc -= xon_off_tot;
3328 adapter->stats.mptc -= xon_off_tot;
3329 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3330 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3331 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3332 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3333 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3334 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3335 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3336 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3337 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3338 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3339 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3340 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3341 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3342
3343 /* Fill out the OS statistics structure */
9a799d71
AK		 3344 adapter->net_stats.multicast = adapter->stats.mprc;
3345
3346 /* Rx Errors */
3347 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3348 adapter->stats.rlec;
9a799d71
AK		 3349 adapter->net_stats.rx_dropped = 0;
3350 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3351 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3352 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3353}
3354
3355/**
3356 * ixgbe_watchdog - Timer Call-back
3357 * @data: pointer to adapter cast into an unsigned long
3358 **/
3359static void ixgbe_watchdog(unsigned long data)
3360{
3361 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3362 struct ixgbe_hw *hw = &adapter->hw;
3363
3364 /* Do the watchdog outside of interrupt context due to the lovely
3365 * delays that some of the newer hardware requires */
3366 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3367 /* Cause software interrupt to ensure rx rings are cleaned */
3368 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3369 u32 eics =
3370 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3371 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3372 } else {
3373 /* For legacy and MSI interrupts don't set any bits that
3374 * are enabled for EIAM, because this operation would
3375 * set *both* EIMS and EICS for any bit in EIAM */
3376 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3377 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3378 }
3379 /* Reset the timer */
3380 mod_timer(&adapter->watchdog_timer,
3381 round_jiffies(jiffies + 2 * HZ));
3382 }
9a799d71 3383
cf8280ee
JB		 3384 schedule_work(&adapter->watchdog_task);
3385}
3386
3387/**
69888674
AD		 3388 * ixgbe_watchdog_task - worker thread to bring link up
3389 * @work: pointer to work_struct containing our data
cf8280ee
JB		 3390 **/
3391static void ixgbe_watchdog_task(struct work_struct *work)
3392{
3393 struct ixgbe_adapter *adapter = container_of(work,
3394 struct ixgbe_adapter,
3395 watchdog_task);
3396 struct net_device *netdev = adapter->netdev;
3397 struct ixgbe_hw *hw = &adapter->hw;
3398 u32 link_speed = adapter->link_speed;
3399 bool link_up = adapter->link_up;
3400
3401 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3402
3403 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3404 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3405 if (link_up ||
3406 time_after(jiffies, (adapter->link_check_timeout +
3407 IXGBE_TRY_LINK_TIMEOUT))) {
3408 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3409 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3410 }
3411 adapter->link_up = link_up;
3412 adapter->link_speed = link_speed;
3413 }
9a799d71
AK		 3414
3415 if (link_up) {
3416 if (!netif_carrier_ok(netdev)) {
cf8280ee
JB		 3417 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3418 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
9a799d71
AK		 3419#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3420#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
a46e534b
JK		 3421 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3422 "Flow Control: %s\n",
3423 netdev->name,
3424 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3425 "10 Gbps" :
3426 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3427 "1 Gbps" : "unknown speed")),
3428 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3429 (FLOW_RX ? "RX" :
3430 (FLOW_TX ? "TX" : "None"))));
9a799d71
AK		 3431
3432 netif_carrier_on(netdev);
9a799d71
AK		 3433 } else {
3434 /* Force detection of hung controller */
3435 adapter->detect_tx_hung = true;
3436 }
3437 } else {
cf8280ee
JB		 3438 adapter->link_up = false;
3439 adapter->link_speed = 0;
9a799d71 3440 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 3441 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3442 netdev->name);
9a799d71 3443 netif_carrier_off(netdev);
9a799d71
AK		 3444 }
3445 }
3446
3447 ixgbe_update_stats(adapter);
cf8280ee 3448 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 3449}
3450
9a799d71 3451static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 3452 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3453 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 3454{
3455 struct ixgbe_adv_tx_context_desc *context_desc;
3456 unsigned int i;
3457 int err;
3458 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 3459 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3460 u32 mss_l4len_idx, l4len;
9a799d71
AK		 3461
3462 if (skb_is_gso(skb)) {
3463 if (skb_header_cloned(skb)) {
3464 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3465 if (err)
3466 return err;
3467 }
3468 l4len = tcp_hdrlen(skb);
3469 *hdr_len += l4len;
3470
8327d000 3471 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3472 struct iphdr *iph = ip_hdr(skb);
3473 iph->tot_len = 0;
3474 iph->check = 0;
3475 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 3476 iph->daddr, 0,
3477 IPPROTO_TCP,
3478 0);
9a799d71
AK		 3479 adapter->hw_tso_ctxt++;
3480 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3481 ipv6_hdr(skb)->payload_len = 0;
3482 tcp_hdr(skb)->check =
3483 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 3484 &ipv6_hdr(skb)->daddr,
3485 0, IPPROTO_TCP, 0);
9a799d71
AK		 3486 adapter->hw_tso6_ctxt++;
3487 }
3488
3489 i = tx_ring->next_to_use;
3490
3491 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3492 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3493
3494 /* VLAN MACLEN IPLEN */
3495 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3496 vlan_macip_lens |=
3497 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3498 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 3499 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3500 *hdr_len += skb_network_offset(skb);
3501 vlan_macip_lens |=
3502 (skb_transport_header(skb) - skb_network_header(skb));
3503 *hdr_len +=
3504 (skb_transport_header(skb) - skb_network_header(skb));
3505 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3506 context_desc->seqnum_seed = 0;
3507
3508 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 3509 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 3510 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 3511
8327d000 3512 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3513 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3514 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3515 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3516
3517 /* MSS L4LEN IDX */
9f8cdf4f 3518 mss_l4len_idx =
9a799d71
AK		 3519 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3520 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 3521 /* use index 1 for TSO */
3522 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3523 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3524
3525 tx_buffer_info->time_stamp = jiffies;
3526 tx_buffer_info->next_to_watch = i;
3527
3528 i++;
3529 if (i == tx_ring->count)
3530 i = 0;
3531 tx_ring->next_to_use = i;
3532
3533 return true;
3534 }
3535 return false;
3536}
3537
3538static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 3539 struct ixgbe_ring *tx_ring,
3540 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 3541{
3542 struct ixgbe_adv_tx_context_desc *context_desc;
3543 unsigned int i;
3544 struct ixgbe_tx_buffer *tx_buffer_info;
3545 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3546
3547 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3548 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3549 i = tx_ring->next_to_use;
3550 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3551 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3552
3553 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3554 vlan_macip_lens |=
3555 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3556 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 3557 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3558 if (skb->ip_summed == CHECKSUM_PARTIAL)
3559 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 3560 skb_network_header(skb));
9a799d71
AK		 3561
3562 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3563 context_desc->seqnum_seed = 0;
3564
3565 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 3566 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 3567
3568 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 3569 switch (skb->protocol) {
09640e63 3570 case cpu_to_be16(ETH_P_IP):
9a799d71 3571 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3572 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3573 type_tucmd_mlhl |=
b4617240 3574 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3575 break;
09640e63 3576 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 3577 /* XXX what about other V6 headers?? */
3578 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3579 type_tucmd_mlhl |=
b4617240 3580 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3581 break;
41825d71
AK		 3582 default:
3583 if (unlikely(net_ratelimit())) {
3584 DPRINTK(PROBE, WARNING,
3585 "partial checksum but proto=%x!\n",
3586 skb->protocol);
3587 }
3588 break;
3589 }
9a799d71
AK		 3590 }
3591
3592 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 3593 /* use index zero for tx checksum offload */
9a799d71
AK		 3594 context_desc->mss_l4len_idx = 0;
3595
3596 tx_buffer_info->time_stamp = jiffies;
3597 tx_buffer_info->next_to_watch = i;
9f8cdf4f 3598
9a799d71
AK		 3599 adapter->hw_csum_tx_good++;
3600 i++;
3601 if (i == tx_ring->count)
3602 i = 0;
3603 tx_ring->next_to_use = i;
3604
3605 return true;
3606 }
9f8cdf4f 3607
9a799d71
AK		 3608 return false;
3609}
3610
3611static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 3612 struct ixgbe_ring *tx_ring,
3613 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 3614{
3615 struct ixgbe_tx_buffer *tx_buffer_info;
3616 unsigned int len = skb->len;
3617 unsigned int offset = 0, size, count = 0, i;
3618 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3619 unsigned int f;
3620
3621 len -= skb->data_len;
3622
3623 i = tx_ring->next_to_use;
3624
3625 while (len) {
3626 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3627 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3628
3629 tx_buffer_info->length = size;
3630 tx_buffer_info->dma = pci_map_single(adapter->pdev,
b4617240
PW		 3631 skb->data + offset,
3632 size, PCI_DMA_TODEVICE);
9a799d71
AK		 3633 tx_buffer_info->time_stamp = jiffies;
3634 tx_buffer_info->next_to_watch = i;
3635
3636 len -= size;
3637 offset += size;
3638 count++;
3639 i++;
3640 if (i == tx_ring->count)
3641 i = 0;
3642 }
3643
3644 for (f = 0; f < nr_frags; f++) {
3645 struct skb_frag_struct *frag;
3646
3647 frag = &skb_shinfo(skb)->frags[f];
3648 len = frag->size;
3649 offset = frag->page_offset;
3650
3651 while (len) {
3652 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3653 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3654
3655 tx_buffer_info->length = size;
3656 tx_buffer_info->dma = pci_map_page(adapter->pdev,
b4617240
PW		 3657 frag->page,
3658 offset,
3659 size,
3660 PCI_DMA_TODEVICE);
9a799d71
AK		 3661 tx_buffer_info->time_stamp = jiffies;
3662 tx_buffer_info->next_to_watch = i;
3663
3664 len -= size;
3665 offset += size;
3666 count++;
3667 i++;
3668 if (i == tx_ring->count)
3669 i = 0;
3670 }
3671 }
3672 if (i == 0)
3673 i = tx_ring->count - 1;
3674 else
3675 i = i - 1;
3676 tx_ring->tx_buffer_info[i].skb = skb;
3677 tx_ring->tx_buffer_info[first].next_to_watch = i;
3678
3679 return count;
3680}
3681
3682static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 3683 struct ixgbe_ring *tx_ring,
3684 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 3685{
3686 union ixgbe_adv_tx_desc *tx_desc = NULL;
3687 struct ixgbe_tx_buffer *tx_buffer_info;
3688 u32 olinfo_status = 0, cmd_type_len = 0;
3689 unsigned int i;
3690 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3691
3692 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3693
3694 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3695
3696 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3697 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3698
3699 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3700 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3701
3702 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3703 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 3704
4eeae6fd
PW		 3705 /* use index 1 context for tso */
3706 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3707 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3708 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 3709 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3710
3711 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3712 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3713 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3714
3715 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3716
3717 i = tx_ring->next_to_use;
3718 while (count--) {
3719 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3720 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3721 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3722 tx_desc->read.cmd_type_len =
b4617240 3723 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 3724 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 3725 i++;
3726 if (i == tx_ring->count)
3727 i = 0;
3728 }
3729
3730 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3731
3732 /*
3733 * Force memory writes to complete before letting h/w
3734 * know there are new descriptors to fetch. (Only
3735 * applicable for weak-ordered memory model archs,
3736 * such as IA-64).
3737 */
3738 wmb();
3739
3740 tx_ring->next_to_use = i;
3741 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3742}
3743
e092be60 3744static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3745 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3746{
3747 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3748
30eba97a 3749 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3750 /* Herbert's original patch had:
3751 * smp_mb__after_netif_stop_queue();
3752 * but since that doesn't exist yet, just open code it. */
3753 smp_mb();
3754
3755 /* We need to check again in a case another CPU has just
3756 * made room available. */
3757 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3758 return -EBUSY;
3759
3760 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 3761 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3762 ++adapter->restart_queue;
3763 return 0;
3764}
3765
3766static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3767 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3768{
3769 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3770 return 0;
3771 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3772}
3773
9a799d71
AK		 3774static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3775{
3776 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3777 struct ixgbe_ring *tx_ring;
9a799d71
AK		 3778 unsigned int first;
3779 unsigned int tx_flags = 0;
30eba97a
AV		 3780 u8 hdr_len = 0;
3781 int r_idx = 0, tso;
9a799d71
AK		 3782 int count = 0;
3783 unsigned int f;
9f8cdf4f 3784
30eba97a 3785 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3786 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3787
9f8cdf4f
JB		 3788 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3789 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 3790 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3791 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
3792 tx_flags |= (skb->queue_mapping << 13);
3793 }
3794 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3795 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3796 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3797 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 3798 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3799 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 3800 }
9f8cdf4f
JB		 3801 /* three things can cause us to need a context descriptor */
3802 if (skb_is_gso(skb) ||
3803 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3804 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 3805 count++;
3806
9f8cdf4f
JB		 3807 count += TXD_USE_COUNT(skb_headlen(skb));
3808 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 3809 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3810
e092be60 3811 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3812 adapter->tx_busy++;
9a799d71
AK		 3813 return NETDEV_TX_BUSY;
3814 }
9a799d71 3815
8327d000 3816 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3817 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3818 first = tx_ring->next_to_use;
3819 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3820 if (tso < 0) {
3821 dev_kfree_skb_any(skb);
3822 return NETDEV_TX_OK;
3823 }
3824
3825 if (tso)
3826 tx_flags |= IXGBE_TX_FLAGS_TSO;
3827 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 3828 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 3829 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3830
3831 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
b4617240
PW		 3832 ixgbe_tx_map(adapter, tx_ring, skb, first),
3833 skb->len, hdr_len);
9a799d71
AK		 3834
3835 netdev->trans_start = jiffies;
3836
e092be60 3837 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3838
3839 return NETDEV_TX_OK;
3840}
3841
3842/**
3843 * ixgbe_get_stats - Get System Network Statistics
3844 * @netdev: network interface device structure
3845 *
3846 * Returns the address of the device statistics structure.
3847 * The statistics are actually updated from the timer callback.
3848 **/
3849static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3850{
3851 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3852
3853 /* only return the current stats */
3854 return &adapter->net_stats;
3855}
3856
3857/**
3858 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3859 * @netdev: network interface device structure
3860 * @p: pointer to an address structure
3861 *
3862 * Returns 0 on success, negative on failure
3863 **/
3864static int ixgbe_set_mac(struct net_device *netdev, void *p)
3865{
3866 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 3867 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3868 struct sockaddr *addr = p;
3869
3870 if (!is_valid_ether_addr(addr->sa_data))
3871 return -EADDRNOTAVAIL;
3872
3873 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 3874 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 3875
b4617240 3876 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 3877
3878 return 0;
3879}
3880
3881#ifdef CONFIG_NET_POLL_CONTROLLER
3882/*
3883 * Polling 'interrupt' - used by things like netconsole to send skbs
3884 * without having to re-enable interrupts. It's not called while
3885 * the interrupt routine is executing.
3886 */
3887static void ixgbe_netpoll(struct net_device *netdev)
3888{
3889 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3890
3891 disable_irq(adapter->pdev->irq);
3892 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3893 ixgbe_intr(adapter->pdev->irq, netdev);
3894 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3895 enable_irq(adapter->pdev->irq);
3896}
3897#endif
3898
c44ade9e
JB		 3899/**
3900 * ixgbe_link_config - set up initial link with default speed and duplex
3901 * @hw: pointer to private hardware struct
3902 *
3903 * Returns 0 on success, negative on failure
3904 **/
3905static int ixgbe_link_config(struct ixgbe_hw *hw)
3906{
5b9c3cdd
DS		 3907 u32 autoneg;
3908 bool link_up = false;
3909 u32 ret = IXGBE_ERR_LINK_SETUP;
c44ade9e 3910
5b9c3cdd
DS		 3911 if (hw->mac.ops.check_link)
3912 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
c44ade9e 3913
5b9c3cdd
DS		 3914 if (ret || !link_up)
3915 goto link_cfg_out;
0befdb3e 3916
5b9c3cdd
DS		 3917 if (hw->mac.ops.get_link_capabilities)
3918 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3919 &hw->mac.autoneg);
3920 if (ret)
3921 goto link_cfg_out;
3922
3923 if (hw->mac.ops.setup_link_speed)
3924 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3925
3926link_cfg_out:
3927 return ret;
c44ade9e
JB		 3928}
3929
0edc3527
SH		 3930static const struct net_device_ops ixgbe_netdev_ops = {
3931 .ndo_open = ixgbe_open,
3932 .ndo_stop = ixgbe_close,
00829823 3933 .ndo_start_xmit = ixgbe_xmit_frame,
0edc3527
SH		 3934 .ndo_get_stats = ixgbe_get_stats,
3935 .ndo_set_multicast_list = ixgbe_set_rx_mode,
3936 .ndo_validate_addr = eth_validate_addr,
3937 .ndo_set_mac_address = ixgbe_set_mac,
3938 .ndo_change_mtu = ixgbe_change_mtu,
3939 .ndo_tx_timeout = ixgbe_tx_timeout,
3940 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
3941 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
3942 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
3943#ifdef CONFIG_NET_POLL_CONTROLLER
3944 .ndo_poll_controller = ixgbe_netpoll,
3945#endif
3946};
3947
9a799d71
AK		 3948/**
3949 * ixgbe_probe - Device Initialization Routine
3950 * @pdev: PCI device information struct
3951 * @ent: entry in ixgbe_pci_tbl
3952 *
3953 * Returns 0 on success, negative on failure
3954 *
3955 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3956 * The OS initialization, configuring of the adapter private structure,
3957 * and a hardware reset occur.
3958 **/
3959static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 3960 const struct pci_device_id *ent)
9a799d71
AK		 3961{
3962 struct net_device *netdev;
3963 struct ixgbe_adapter *adapter = NULL;
3964 struct ixgbe_hw *hw;
3965 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 3966 static int cards_found;
3967 int i, err, pci_using_dac;
3968 u16 link_status, link_speed, link_width;
c44ade9e 3969 u32 part_num, eec;
9a799d71
AK		 3970
3971 err = pci_enable_device(pdev);
3972 if (err)
3973 return err;
3974
3975 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3976 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3977 pci_using_dac = 1;
3978 } else {
3979 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3980 if (err) {
3981 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3982 if (err) {
b4617240
PW		 3983 dev_err(&pdev->dev, "No usable DMA "
3984 "configuration, aborting\n");
9a799d71
AK		 3985 goto err_dma;
3986 }
3987 }
3988 pci_using_dac = 0;
3989 }
3990
3991 err = pci_request_regions(pdev, ixgbe_driver_name);
3992 if (err) {
3993 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3994 goto err_pci_reg;
3995 }
3996
6fabd715
PWJ		 3997 err = pci_enable_pcie_error_reporting(pdev);
3998 if (err) {
3999 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4000 "0x%x\n", err);
4001 /* non-fatal, continue */
4002 }
4003
9a799d71 4004 pci_set_master(pdev);
fb3b27bc 4005 pci_save_state(pdev);
9a799d71 4006
30eba97a 4007 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 4008 if (!netdev) {
4009 err = -ENOMEM;
4010 goto err_alloc_etherdev;
4011 }
4012
9a799d71
AK		 4013 SET_NETDEV_DEV(netdev, &pdev->dev);
4014
4015 pci_set_drvdata(pdev, netdev);
4016 adapter = netdev_priv(netdev);
4017
4018 adapter->netdev = netdev;
4019 adapter->pdev = pdev;
4020 hw = &adapter->hw;
4021 hw->back = adapter;
4022 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4023
05857980
JK		 4024 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4025 pci_resource_len(pdev, 0));
9a799d71
AK		 4026 if (!hw->hw_addr) {
4027 err = -EIO;
4028 goto err_ioremap;
4029 }
4030
4031 for (i = 1; i <= 5; i++) {
4032 if (pci_resource_len(pdev, i) == 0)
4033 continue;
4034 }
4035
0edc3527 4036 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 4037 ixgbe_set_ethtool_ops(netdev);
9a799d71 4038 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 4039 strcpy(netdev->name, pci_name(pdev));
4040
9a799d71
AK		 4041 adapter->bd_number = cards_found;
4042
9a799d71
AK		 4043 /* Setup hw api */
4044 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 4045 hw->mac.type = ii->mac;
9a799d71 4046
c44ade9e
JB		 4047 /* EEPROM */
4048 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4049 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4050 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4051 if (!(eec & (1 << 8)))
4052 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4053
4054 /* PHY */
4055 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0
DS		 4056 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4057
4058 /* set up this timer and work struct before calling get_invariants
4059 * which might start the timer
4060 */
4061 init_timer(&adapter->sfp_timer);
4062 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4063 adapter->sfp_timer.data = (unsigned long) adapter;
4064
4065 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 4066
9a799d71 4067 err = ii->get_invariants(hw);
c4900be0
DS		 4068 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4069 /* start a kernel thread to watch for a module to arrive */
4070 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4071 mod_timer(&adapter->sfp_timer,
4072 round_jiffies(jiffies + (2 * HZ)));
4073 err = 0;
4074 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4075 DPRINTK(PROBE, ERR, "failed to load because an "
4076 "unsupported SFP+ module type was detected.\n");
9a799d71 4077 goto err_hw_init;
c4900be0
DS		 4078 } else if (err) {
4079 goto err_hw_init;
4080 }
9a799d71
AK		 4081
4082 /* setup the private structure */
4083 err = ixgbe_sw_init(adapter);
4084 if (err)
4085 goto err_sw_init;
4086
c44ade9e
JB		 4087 /* reset_hw fills in the perm_addr as well */
4088 err = hw->mac.ops.reset_hw(hw);
4089 if (err) {
4090 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4091 goto err_sw_init;
4092 }
4093
9a799d71 4094 netdev->features = NETIF_F_SG |
b4617240
PW		 4095 NETIF_F_IP_CSUM |
4096 NETIF_F_HW_VLAN_TX |
4097 NETIF_F_HW_VLAN_RX |
4098 NETIF_F_HW_VLAN_FILTER;
9a799d71 4099
e9990a9c 4100 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4101 netdev->features |= NETIF_F_TSO;
9a799d71 4102 netdev->features |= NETIF_F_TSO6;
78b6f4ce 4103 netdev->features |= NETIF_F_GRO;
ad31c402
JK		 4104
4105 netdev->vlan_features |= NETIF_F_TSO;
4106 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4107 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4108 netdev->vlan_features |= NETIF_F_SG;
4109
2f90b865
AD		 4110 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4111 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4112
7a6b6f51 4113#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4114 netdev->dcbnl_ops = &dcbnl_ops;
4115#endif
4116
9a799d71
AK		 4117 if (pci_using_dac)
4118 netdev->features |= NETIF_F_HIGHDMA;
4119
9a799d71 4120 /* make sure the EEPROM is good */
c44ade9e 4121 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4122 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4123 err = -EIO;
4124 goto err_eeprom;
4125 }
4126
4127 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4128 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4129
c44ade9e
JB		 4130 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4131 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4132 err = -EIO;
4133 goto err_eeprom;
4134 }
4135
4136 init_timer(&adapter->watchdog_timer);
4137 adapter->watchdog_timer.function = &ixgbe_watchdog;
4138 adapter->watchdog_timer.data = (unsigned long)adapter;
4139
4140 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 4141 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 4142
021230d4
AV		 4143 err = ixgbe_init_interrupt_scheme(adapter);
4144 if (err)
4145 goto err_sw_init;
9a799d71
AK		 4146
4147 /* print bus type/speed/width info */
4148 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
4149 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
4150 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
7c510e4b 4151 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
b4617240
PW		 4152 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
4153 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
4154 "Unknown"),
4155 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
4156 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
4157 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
4158 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
4159 "Unknown"),
7c510e4b 4160 netdev->dev_addr);
c44ade9e 4161 ixgbe_read_pba_num_generic(hw, &part_num);
9a799d71 4162 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
b4617240
PW		 4163 hw->mac.type, hw->phy.type,
4164 (part_num >> 8), (part_num & 0xff));
9a799d71 4165
0c254d86
AK		 4166 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
4167 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 4168 "this card is not sufficient for optimal "
4169 "performance.\n");
0c254d86 4170 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 4171 "PCI-Express slot is required.\n");
0c254d86
AK		 4172 }
4173
9a799d71 4174 /* reset the hardware with the new settings */
c44ade9e
JB		 4175 hw->mac.ops.start_hw(hw);
4176
4177 /* link_config depends on start_hw being called at least once */
4178 err = ixgbe_link_config(hw);
4179 if (err) {
4180 dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err);
4181 goto err_register;
4182 }
9a799d71
AK		 4183
4184 netif_carrier_off(netdev);
9a799d71
AK		 4185
4186 strcpy(netdev->name, "eth%d");
4187 err = register_netdev(netdev);
4188 if (err)
4189 goto err_register;
4190
5dd2d332 4191#ifdef CONFIG_IXGBE_DCA
652f093f 4192 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 4193 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4194 /* always use CB2 mode, difference is masked
4195 * in the CB driver */
4196 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4197 ixgbe_setup_dca(adapter);
4198 }
4199#endif
9a799d71
AK		 4200
4201 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4202 cards_found++;
4203 return 0;
4204
4205err_register:
5eba3699 4206 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4207err_hw_init:
4208err_sw_init:
021230d4 4209 ixgbe_reset_interrupt_capability(adapter);
9a799d71 4210err_eeprom:
c4900be0
DS		 4211 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4212 del_timer_sync(&adapter->sfp_timer);
4213 cancel_work_sync(&adapter->sfp_task);
9a799d71
AK		 4214 iounmap(hw->hw_addr);
4215err_ioremap:
4216 free_netdev(netdev);
4217err_alloc_etherdev:
4218 pci_release_regions(pdev);
4219err_pci_reg:
4220err_dma:
4221 pci_disable_device(pdev);
4222 return err;
4223}
4224
4225/**
4226 * ixgbe_remove - Device Removal Routine
4227 * @pdev: PCI device information struct
4228 *
4229 * ixgbe_remove is called by the PCI subsystem to alert the driver
4230 * that it should release a PCI device. The could be caused by a
4231 * Hot-Plug event, or because the driver is going to be removed from
4232 * memory.
4233 **/
4234static void __devexit ixgbe_remove(struct pci_dev *pdev)
4235{
4236 struct net_device *netdev = pci_get_drvdata(pdev);
4237 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 4238 int err;
9a799d71
AK		 4239
4240 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 4241 /* clear the module not found bit to make sure the worker won't
4242 * reschedule
4243 */
4244 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 4245 del_timer_sync(&adapter->watchdog_timer);
4246
c4900be0
DS		 4247 del_timer_sync(&adapter->sfp_timer);
4248 cancel_work_sync(&adapter->watchdog_task);
4249 cancel_work_sync(&adapter->sfp_task);
9a799d71
AK		 4250 flush_scheduled_work();
4251
5dd2d332 4252#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4253 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4254 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4255 dca_remove_requester(&pdev->dev);
4256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4257 }
4258
4259#endif
c4900be0
DS		 4260 if (netdev->reg_state == NETREG_REGISTERED)
4261 unregister_netdev(netdev);
9a799d71 4262
021230d4 4263 ixgbe_reset_interrupt_capability(adapter);
5eba3699 4264
021230d4 4265 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4266
4267 iounmap(adapter->hw.hw_addr);
4268 pci_release_regions(pdev);
4269
021230d4
AV		 4270 DPRINTK(PROBE, INFO, "complete\n");
4271 kfree(adapter->tx_ring);
4272 kfree(adapter->rx_ring);
4273
9a799d71
AK		 4274 free_netdev(netdev);
4275
6fabd715
PWJ		 4276 err = pci_disable_pcie_error_reporting(pdev);
4277 if (err)
4278 dev_err(&pdev->dev,
4279 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4280
9a799d71
AK		 4281 pci_disable_device(pdev);
4282}
4283
4284/**
4285 * ixgbe_io_error_detected - called when PCI error is detected
4286 * @pdev: Pointer to PCI device
4287 * @state: The current pci connection state
4288 *
4289 * This function is called after a PCI bus error affecting
4290 * this device has been detected.
4291 */
4292static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 4293 pci_channel_state_t state)
9a799d71
AK		 4294{
4295 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4296 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4297
4298 netif_device_detach(netdev);
4299
4300 if (netif_running(netdev))
4301 ixgbe_down(adapter);
4302 pci_disable_device(pdev);
4303
b4617240 4304 /* Request a slot reset. */
9a799d71
AK		 4305 return PCI_ERS_RESULT_NEED_RESET;
4306}
4307
4308/**
4309 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4310 * @pdev: Pointer to PCI device
4311 *
4312 * Restart the card from scratch, as if from a cold-boot.
4313 */
4314static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4315{
4316 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4317 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 4318 pci_ers_result_t result;
4319 int err;
9a799d71
AK		 4320
4321 if (pci_enable_device(pdev)) {
4322 DPRINTK(PROBE, ERR,
b4617240 4323 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 4324 result = PCI_ERS_RESULT_DISCONNECT;
4325 } else {
4326 pci_set_master(pdev);
4327 pci_restore_state(pdev);
9a799d71 4328
6fabd715
PWJ		 4329 pci_enable_wake(pdev, PCI_D3hot, 0);
4330 pci_enable_wake(pdev, PCI_D3cold, 0);
9a799d71 4331
6fabd715
PWJ		 4332 ixgbe_reset(adapter);
4333
4334 result = PCI_ERS_RESULT_RECOVERED;
4335 }
4336
4337 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4338 if (err) {
4339 dev_err(&pdev->dev,
4340 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4341 /* non-fatal, continue */
4342 }
9a799d71 4343
6fabd715 4344 return result;
9a799d71
AK		 4345}
4346
4347/**
4348 * ixgbe_io_resume - called when traffic can start flowing again.
4349 * @pdev: Pointer to PCI device
4350 *
4351 * This callback is called when the error recovery driver tells us that
4352 * its OK to resume normal operation.
4353 */
4354static void ixgbe_io_resume(struct pci_dev *pdev)
4355{
4356 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4357 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4358
4359 if (netif_running(netdev)) {
4360 if (ixgbe_up(adapter)) {
4361 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4362 return;
4363 }
4364 }
4365
4366 netif_device_attach(netdev);
9a799d71
AK		 4367}
4368
4369static struct pci_error_handlers ixgbe_err_handler = {
4370 .error_detected = ixgbe_io_error_detected,
4371 .slot_reset = ixgbe_io_slot_reset,
4372 .resume = ixgbe_io_resume,
4373};
4374
4375static struct pci_driver ixgbe_driver = {
4376 .name = ixgbe_driver_name,
4377 .id_table = ixgbe_pci_tbl,
4378 .probe = ixgbe_probe,
4379 .remove = __devexit_p(ixgbe_remove),
4380#ifdef CONFIG_PM
4381 .suspend = ixgbe_suspend,
4382 .resume = ixgbe_resume,
4383#endif
4384 .shutdown = ixgbe_shutdown,
4385 .err_handler = &ixgbe_err_handler
4386};
4387
4388/**
4389 * ixgbe_init_module - Driver Registration Routine
4390 *
4391 * ixgbe_init_module is the first routine called when the driver is
4392 * loaded. All it does is register with the PCI subsystem.
4393 **/
4394static int __init ixgbe_init_module(void)
4395{
4396 int ret;
4397 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4398 ixgbe_driver_string, ixgbe_driver_version);
4399
4400 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4401
5dd2d332 4402#ifdef CONFIG_IXGBE_DCA
bd0362dd 4403 dca_register_notify(&dca_notifier);
bd0362dd 4404#endif
5dd2d332 4405
9a799d71
AK		 4406 ret = pci_register_driver(&ixgbe_driver);
4407 return ret;
4408}
b4617240 4409
9a799d71
AK		 4410module_init(ixgbe_init_module);
4411
4412/**
4413 * ixgbe_exit_module - Driver Exit Cleanup Routine
4414 *
4415 * ixgbe_exit_module is called just before the driver is removed
4416 * from memory.
4417 **/
4418static void __exit ixgbe_exit_module(void)
4419{
5dd2d332 4420#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4421 dca_unregister_notify(&dca_notifier);
4422#endif
9a799d71
AK		 4423 pci_unregister_driver(&ixgbe_driver);
4424}
bd0362dd 4425
5dd2d332 4426#ifdef CONFIG_IXGBE_DCA
bd0362dd 4427static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 4428 void *p)
bd0362dd
JC		 4429{
4430 int ret_val;
4431
4432 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 4433 __ixgbe_notify_dca);
bd0362dd
JC		 4434
4435 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4436}
5dd2d332 4437#endif /* CONFIG_IXGBE_DCA */
bd0362dd 4438
9a799d71
AK		 4439module_exit(ixgbe_exit_module);
4440
4441/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree