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Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[net-next-2.6.git] / drivers / net / gianfar.c
CommitLineData
0bbaf069 1/*
1da177e4
LT		 2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
a12f801d 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 12 *
a12f801d
SG		 13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
0bbaf069 28 *
b31a1d8b
AF		 29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
0bbaf069 39 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
bb40dcbb 43 * of frames or amount of time have passed). In NAPI, the
1da177e4 44 * interrupt handler will signal there is work to be done, and
0aa1538f 45 * exit. This method will start at the last known empty
0bbaf069 46 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
1da177e4 65#include <linux/kernel.h>
1da177e4
LT		 66#include <linux/string.h>
67#include <linux/errno.h>
bb40dcbb 68#include <linux/unistd.h>
1da177e4
LT		 69#include <linux/slab.h>
70#include <linux/interrupt.h>
71#include <linux/init.h>
72#include <linux/delay.h>
73#include <linux/netdevice.h>
74#include <linux/etherdevice.h>
75#include <linux/skbuff.h>
0bbaf069 76#include <linux/if_vlan.h>
1da177e4
LT		 77#include <linux/spinlock.h>
78#include <linux/mm.h>
fe192a49 79#include <linux/of_mdio.h>
b31a1d8b 80#include <linux/of_platform.h>
0bbaf069
KG		 81#include <linux/ip.h>
82#include <linux/tcp.h>
83#include <linux/udp.h>
9c07b884 84#include <linux/in.h>
cc772ab7 85#include <linux/net_tstamp.h>
1da177e4
LT		 86
87#include <asm/io.h>
88#include <asm/irq.h>
89#include <asm/uaccess.h>
90#include <linux/module.h>
1da177e4
LT		 91#include <linux/dma-mapping.h>
92#include <linux/crc32.h>
bb40dcbb
AF		 93#include <linux/mii.h>
94#include <linux/phy.h>
b31a1d8b
AF		 95#include <linux/phy_fixed.h>
96#include <linux/of.h>
1da177e4
LT		 97
98#include "gianfar.h"
1577ecef 99#include "fsl_pq_mdio.h"
1da177e4
LT		 100
101#define TX_TIMEOUT (1*HZ)
1da177e4
LT		 102#undef BRIEF_GFAR_ERRORS
103#undef VERBOSE_GFAR_ERRORS
104
1da177e4 105const char gfar_driver_name[] = "Gianfar Ethernet";
7f7f5316 106const char gfar_driver_version[] = "1.3";
1da177e4 107
1da177e4
LT		 108static int gfar_enet_open(struct net_device *dev);
109static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 110static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 111static void gfar_timeout(struct net_device *dev);
112static int gfar_close(struct net_device *dev);
815b97c6 113struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 114static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6 115 struct sk_buff *skb);
1da177e4
LT		 116static int gfar_set_mac_address(struct net_device *dev);
117static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 118static irqreturn_t gfar_error(int irq, void *dev_id);
119static irqreturn_t gfar_transmit(int irq, void *dev_id);
120static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 121static void adjust_link(struct net_device *dev);
122static void init_registers(struct net_device *dev);
123static int init_phy(struct net_device *dev);
b31a1d8b
AF		 124static int gfar_probe(struct of_device *ofdev,
125 const struct of_device_id *match);
126static int gfar_remove(struct of_device *ofdev);
bb40dcbb 127static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 128static void gfar_set_multi(struct net_device *dev);
129static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 130static void gfar_configure_serdes(struct net_device *dev);
bea3348e 131static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 132#ifdef CONFIG_NET_POLL_CONTROLLER
133static void gfar_netpoll(struct net_device *dev);
134#endif
a12f801d
SG		 135int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
136static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a
DH		 137static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
138 int amount_pull);
0bbaf069
KG		 139static void gfar_vlan_rx_register(struct net_device *netdev,
140 struct vlan_group *grp);
7f7f5316 141void gfar_halt(struct net_device *dev);
d87eb127 142static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 143void gfar_start(struct net_device *dev);
144static void gfar_clear_exact_match(struct net_device *dev);
145static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
26ccfc37 146static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 147
1da177e4
LT		 148MODULE_AUTHOR("Freescale Semiconductor, Inc");
149MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150MODULE_LICENSE("GPL");
151
a12f801d 152static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 153 dma_addr_t buf)
154{
8a102fe0
AV		 155 u32 lstatus;
156
157 bdp->bufPtr = buf;
158
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 161 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163 eieio();
164
165 bdp->lstatus = lstatus;
166}
167
8728327e 168static int gfar_init_bds(struct net_device *ndev)
826aa4a0 169{
8728327e 170 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 173 struct txbd8 *txbdp;
174 struct rxbd8 *rxbdp;
fba4ed03 175 int i, j;
a12f801d 176
fba4ed03
SG		 177 for (i = 0; i < priv->num_tx_queues; i++) {
178 tx_queue = priv->tx_queue[i];
179 /* Initialize some variables in our dev structure */
180 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182 tx_queue->cur_tx = tx_queue->tx_bd_base;
183 tx_queue->skb_curtx = 0;
184 tx_queue->skb_dirtytx = 0;
185
186 /* Initialize Transmit Descriptor Ring */
187 txbdp = tx_queue->tx_bd_base;
188 for (j = 0; j < tx_queue->tx_ring_size; j++) {
189 txbdp->lstatus = 0;
190 txbdp->bufPtr = 0;
191 txbdp++;
192 }
8728327e 193
fba4ed03
SG		 194 /* Set the last descriptor in the ring to indicate wrap */
195 txbdp--;
196 txbdp->status |= TXBD_WRAP;
8728327e
AV		 197 }
198
fba4ed03
SG		 199 for (i = 0; i < priv->num_rx_queues; i++) {
200 rx_queue = priv->rx_queue[i];
201 rx_queue->cur_rx = rx_queue->rx_bd_base;
202 rx_queue->skb_currx = 0;
203 rxbdp = rx_queue->rx_bd_base;
8728327e 204
fba4ed03
SG		 205 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 207
fba4ed03
SG		 208 if (skb) {
209 gfar_init_rxbdp(rx_queue, rxbdp,
210 rxbdp->bufPtr);
211 } else {
212 skb = gfar_new_skb(ndev);
213 if (!skb) {
214 pr_err("%s: Can't allocate RX buffers\n",
215 ndev->name);
216 goto err_rxalloc_fail;
217 }
218 rx_queue->rx_skbuff[j] = skb;
219
220 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 221 }
8728327e 222
fba4ed03 223 rxbdp++;
8728327e
AV		 224 }
225
8728327e
AV		 226 }
227
228 return 0;
fba4ed03
SG		 229
230err_rxalloc_fail:
231 free_skb_resources(priv);
232 return -ENOMEM;
8728327e
AV		 233}
234
235static int gfar_alloc_skb_resources(struct net_device *ndev)
236{
826aa4a0 237 void *vaddr;
fba4ed03
SG		 238 dma_addr_t addr;
239 int i, j, k;
826aa4a0
AV		 240 struct gfar_private *priv = netdev_priv(ndev);
241 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 242 struct gfar_priv_tx_q *tx_queue = NULL;
243 struct gfar_priv_rx_q *rx_queue = NULL;
244
fba4ed03
SG		 245 priv->total_tx_ring_size = 0;
246 for (i = 0; i < priv->num_tx_queues; i++)
247 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
248
249 priv->total_rx_ring_size = 0;
250 for (i = 0; i < priv->num_rx_queues; i++)
251 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 252
253 /* Allocate memory for the buffer descriptors */
8728327e 254 vaddr = dma_alloc_coherent(dev,
fba4ed03
SG		 255 sizeof(struct txbd8) * priv->total_tx_ring_size +
256 sizeof(struct rxbd8) * priv->total_rx_ring_size,
257 &addr, GFP_KERNEL);
826aa4a0
AV		 258 if (!vaddr) {
259 if (netif_msg_ifup(priv))
260 pr_err("%s: Could not allocate buffer descriptors!\n",
261 ndev->name);
262 return -ENOMEM;
263 }
264
fba4ed03
SG		 265 for (i = 0; i < priv->num_tx_queues; i++) {
266 tx_queue = priv->tx_queue[i];
267 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
268 tx_queue->tx_bd_dma_base = addr;
269 tx_queue->dev = ndev;
270 /* enet DMA only understands physical addresses */
271 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
272 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
273 }
826aa4a0 274
826aa4a0 275 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 276 for (i = 0; i < priv->num_rx_queues; i++) {
277 rx_queue = priv->rx_queue[i];
278 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
279 rx_queue->rx_bd_dma_base = addr;
280 rx_queue->dev = ndev;
281 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
282 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
283 }
826aa4a0
AV		 284
285 /* Setup the skbuff rings */
fba4ed03
SG		 286 for (i = 0; i < priv->num_tx_queues; i++) {
287 tx_queue = priv->tx_queue[i];
288 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
a12f801d 289 tx_queue->tx_ring_size, GFP_KERNEL);
fba4ed03
SG		 290 if (!tx_queue->tx_skbuff) {
291 if (netif_msg_ifup(priv))
292 pr_err("%s: Could not allocate tx_skbuff\n",
293 ndev->name);
294 goto cleanup;
295 }
826aa4a0 296
fba4ed03
SG		 297 for (k = 0; k < tx_queue->tx_ring_size; k++)
298 tx_queue->tx_skbuff[k] = NULL;
299 }
826aa4a0 300
fba4ed03
SG		 301 for (i = 0; i < priv->num_rx_queues; i++) {
302 rx_queue = priv->rx_queue[i];
303 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
a12f801d 304 rx_queue->rx_ring_size, GFP_KERNEL);
826aa4a0 305
fba4ed03
SG		 306 if (!rx_queue->rx_skbuff) {
307 if (netif_msg_ifup(priv))
308 pr_err("%s: Could not allocate rx_skbuff\n",
309 ndev->name);
310 goto cleanup;
311 }
312
313 for (j = 0; j < rx_queue->rx_ring_size; j++)
314 rx_queue->rx_skbuff[j] = NULL;
315 }
826aa4a0 316
8728327e
AV		 317 if (gfar_init_bds(ndev))
318 goto cleanup;
826aa4a0
AV		 319
320 return 0;
321
322cleanup:
323 free_skb_resources(priv);
324 return -ENOMEM;
325}
326
fba4ed03
SG		 327static void gfar_init_tx_rx_base(struct gfar_private *priv)
328{
46ceb60c 329 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 330 u32 __iomem *baddr;
fba4ed03
SG		 331 int i;
332
333 baddr = &regs->tbase0;
334 for(i = 0; i < priv->num_tx_queues; i++) {
335 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
336 baddr += 2;
337 }
338
339 baddr = &regs->rbase0;
340 for(i = 0; i < priv->num_rx_queues; i++) {
341 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
342 baddr += 2;
343 }
344}
345
826aa4a0
AV		 346static void gfar_init_mac(struct net_device *ndev)
347{
348 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 349 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 350 u32 rctrl = 0;
351 u32 tctrl = 0;
352 u32 attrs = 0;
353
fba4ed03
SG		 354 /* write the tx/rx base registers */
355 gfar_init_tx_rx_base(priv);
32c513bc 356
826aa4a0 357 /* Configure the coalescing support */
46ceb60c 358 gfar_configure_coalescing(priv, 0xFF, 0xFF);
fba4ed03 359
1ccb8389 360 if (priv->rx_filer_enable) {
fba4ed03 361 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 362 /* Program the RIR0 reg with the required distribution */
363 gfar_write(&regs->rir0, DEFAULT_RIR0);
364 }
826aa4a0
AV		 365
366 if (priv->rx_csum_enable)
367 rctrl |= RCTRL_CHECKSUMMING;
368
369 if (priv->extended_hash) {
370 rctrl |= RCTRL_EXTHASH;
371
372 gfar_clear_exact_match(ndev);
373 rctrl |= RCTRL_EMEN;
374 }
375
376 if (priv->padding) {
377 rctrl &= ~RCTRL_PAL_MASK;
378 rctrl |= RCTRL_PADDING(priv->padding);
379 }
380
cc772ab7
MR		 381 /* Insert receive time stamps into padding alignment bytes */
382 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
383 rctrl &= ~RCTRL_PAL_MASK;
97553f7f 384 rctrl |= RCTRL_PADDING(8);
cc772ab7
MR		 385 priv->padding = 8;
386 }
387
97553f7f
MR		 388 /* Enable HW time stamping if requested from user space */
389 if (priv->hwts_rx_en)
390 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
391
826aa4a0
AV		 392 /* keep vlan related bits if it's enabled */
393 if (priv->vlgrp) {
394 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
395 tctrl |= TCTRL_VLINS;
396 }
397
398 /* Init rctrl based on our settings */
399 gfar_write(&regs->rctrl, rctrl);
400
401 if (ndev->features & NETIF_F_IP_CSUM)
402 tctrl |= TCTRL_INIT_CSUM;
403
fba4ed03
SG		 404 tctrl |= TCTRL_TXSCHED_PRIO;
405
826aa4a0
AV		 406 gfar_write(&regs->tctrl, tctrl);
407
408 /* Set the extraction length and index */
409 attrs = ATTRELI_EL(priv->rx_stash_size) |
410 ATTRELI_EI(priv->rx_stash_index);
411
412 gfar_write(&regs->attreli, attrs);
413
414 /* Start with defaults, and add stashing or locking
415 * depending on the approprate variables */
416 attrs = ATTR_INIT_SETTINGS;
417
418 if (priv->bd_stash_en)
419 attrs |= ATTR_BDSTASH;
420
421 if (priv->rx_stash_size != 0)
422 attrs |= ATTR_BUFSTASH;
423
424 gfar_write(&regs->attr, attrs);
425
426 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
427 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
428 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
429}
430
a7f38041
SG		 431static struct net_device_stats *gfar_get_stats(struct net_device *dev)
432{
433 struct gfar_private *priv = netdev_priv(dev);
434 struct netdev_queue *txq;
435 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
436 unsigned long tx_packets = 0, tx_bytes = 0;
437 int i = 0;
438
439 for (i = 0; i < priv->num_rx_queues; i++) {
440 rx_packets += priv->rx_queue[i]->stats.rx_packets;
441 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
442 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
443 }
444
445 dev->stats.rx_packets = rx_packets;
446 dev->stats.rx_bytes = rx_bytes;
447 dev->stats.rx_dropped = rx_dropped;
448
449 for (i = 0; i < priv->num_tx_queues; i++) {
450 txq = netdev_get_tx_queue(dev, i);
451 tx_bytes += txq->tx_bytes;
452 tx_packets += txq->tx_packets;
453 }
454
455 dev->stats.tx_bytes = tx_bytes;
456 dev->stats.tx_packets = tx_packets;
457
458 return &dev->stats;
459}
460
26ccfc37
AF		 461static const struct net_device_ops gfar_netdev_ops = {
462 .ndo_open = gfar_enet_open,
463 .ndo_start_xmit = gfar_start_xmit,
464 .ndo_stop = gfar_close,
465 .ndo_change_mtu = gfar_change_mtu,
466 .ndo_set_multicast_list = gfar_set_multi,
467 .ndo_tx_timeout = gfar_timeout,
468 .ndo_do_ioctl = gfar_ioctl,
a7f38041 469 .ndo_get_stats = gfar_get_stats,
26ccfc37 470 .ndo_vlan_rx_register = gfar_vlan_rx_register,
240c102d
BH		 471 .ndo_set_mac_address = eth_mac_addr,
472 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 473#ifdef CONFIG_NET_POLL_CONTROLLER
474 .ndo_poll_controller = gfar_netpoll,
475#endif
476};
477
7a8b3372
SG		 478unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
479unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
480
fba4ed03
SG		 481void lock_rx_qs(struct gfar_private *priv)
482{
483 int i = 0x0;
484
485 for (i = 0; i < priv->num_rx_queues; i++)
486 spin_lock(&priv->rx_queue[i]->rxlock);
487}
488
489void lock_tx_qs(struct gfar_private *priv)
490{
491 int i = 0x0;
492
493 for (i = 0; i < priv->num_tx_queues; i++)
494 spin_lock(&priv->tx_queue[i]->txlock);
495}
496
497void unlock_rx_qs(struct gfar_private *priv)
498{
499 int i = 0x0;
500
501 for (i = 0; i < priv->num_rx_queues; i++)
502 spin_unlock(&priv->rx_queue[i]->rxlock);
503}
504
505void unlock_tx_qs(struct gfar_private *priv)
506{
507 int i = 0x0;
508
509 for (i = 0; i < priv->num_tx_queues; i++)
510 spin_unlock(&priv->tx_queue[i]->txlock);
511}
512
7f7f5316
AF		 513/* Returns 1 if incoming frames use an FCB */
514static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 515{
cc772ab7
MR		 516 return priv->vlgrp || priv->rx_csum_enable ||
517 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
0bbaf069 518}
bb40dcbb 519
fba4ed03
SG		 520static void free_tx_pointers(struct gfar_private *priv)
521{
522 int i = 0;
523
524 for (i = 0; i < priv->num_tx_queues; i++)
525 kfree(priv->tx_queue[i]);
526}
527
528static void free_rx_pointers(struct gfar_private *priv)
529{
530 int i = 0;
531
532 for (i = 0; i < priv->num_rx_queues; i++)
533 kfree(priv->rx_queue[i]);
534}
535
46ceb60c
SG		 536static void unmap_group_regs(struct gfar_private *priv)
537{
538 int i = 0;
539
540 for (i = 0; i < MAXGROUPS; i++)
541 if (priv->gfargrp[i].regs)
542 iounmap(priv->gfargrp[i].regs);
543}
544
545static void disable_napi(struct gfar_private *priv)
546{
547 int i = 0;
548
549 for (i = 0; i < priv->num_grps; i++)
550 napi_disable(&priv->gfargrp[i].napi);
551}
552
553static void enable_napi(struct gfar_private *priv)
554{
555 int i = 0;
556
557 for (i = 0; i < priv->num_grps; i++)
558 napi_enable(&priv->gfargrp[i].napi);
559}
560
561static int gfar_parse_group(struct device_node *np,
562 struct gfar_private *priv, const char *model)
563{
564 u32 *queue_mask;
46ceb60c 565
7ce97d4f 566 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
46ceb60c
SG		 567 if (!priv->gfargrp[priv->num_grps].regs)
568 return -ENOMEM;
569
570 priv->gfargrp[priv->num_grps].interruptTransmit =
571 irq_of_parse_and_map(np, 0);
572
573 /* If we aren't the FEC we have multiple interrupts */
574 if (model && strcasecmp(model, "FEC")) {
575 priv->gfargrp[priv->num_grps].interruptReceive =
576 irq_of_parse_and_map(np, 1);
577 priv->gfargrp[priv->num_grps].interruptError =
578 irq_of_parse_and_map(np,2);
579 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
580 priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
581 priv->gfargrp[priv->num_grps].interruptError < 0) {
582 return -EINVAL;
583 }
584 }
585
586 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
587 priv->gfargrp[priv->num_grps].priv = priv;
588 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
589 if(priv->mode == MQ_MG_MODE) {
590 queue_mask = (u32 *)of_get_property(np,
591 "fsl,rx-bit-map", NULL);
592 priv->gfargrp[priv->num_grps].rx_bit_map =
593 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
594 queue_mask = (u32 *)of_get_property(np,
595 "fsl,tx-bit-map", NULL);
596 priv->gfargrp[priv->num_grps].tx_bit_map =
597 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
598 } else {
599 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
600 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
601 }
602 priv->num_grps++;
603
604 return 0;
605}
606
fba4ed03 607static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
b31a1d8b 608{
b31a1d8b
AF		 609 const char *model;
610 const char *ctype;
611 const void *mac_addr;
fba4ed03
SG		 612 int err = 0, i;
613 struct net_device *dev = NULL;
614 struct gfar_private *priv = NULL;
61c7a080 615 struct device_node *np = ofdev->dev.of_node;
46ceb60c 616 struct device_node *child = NULL;
4d7902f2
AF		 617 const u32 *stash;
618 const u32 *stash_len;
619 const u32 *stash_idx;
fba4ed03
SG		 620 unsigned int num_tx_qs, num_rx_qs;
621 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 622
623 if (!np || !of_device_is_available(np))
624 return -ENODEV;
625
fba4ed03
SG		 626 /* parse the num of tx and rx queues */
627 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
628 num_tx_qs = tx_queues ? *tx_queues : 1;
629
630 if (num_tx_qs > MAX_TX_QS) {
631 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
632 num_tx_qs, MAX_TX_QS);
633 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
634 return -EINVAL;
635 }
636
637 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
638 num_rx_qs = rx_queues ? *rx_queues : 1;
639
640 if (num_rx_qs > MAX_RX_QS) {
641 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
642 num_tx_qs, MAX_TX_QS);
643 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
644 return -EINVAL;
645 }
646
647 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
648 dev = *pdev;
649 if (NULL == dev)
650 return -ENOMEM;
651
652 priv = netdev_priv(dev);
61c7a080 653 priv->node = ofdev->dev.of_node;
fba4ed03
SG		 654 priv->ndev = dev;
655
656 dev->num_tx_queues = num_tx_qs;
657 dev->real_num_tx_queues = num_tx_qs;
658 priv->num_tx_queues = num_tx_qs;
659 priv->num_rx_queues = num_rx_qs;
46ceb60c 660 priv->num_grps = 0x0;
b31a1d8b
AF		 661
662 model = of_get_property(np, "model", NULL);
663
46ceb60c
SG		 664 for (i = 0; i < MAXGROUPS; i++)
665 priv->gfargrp[i].regs = NULL;
b31a1d8b 666
46ceb60c
SG		 667 /* Parse and initialize group specific information */
668 if (of_device_is_compatible(np, "fsl,etsec2")) {
669 priv->mode = MQ_MG_MODE;
670 for_each_child_of_node(np, child) {
671 err = gfar_parse_group(child, priv, model);
672 if (err)
673 goto err_grp_init;
b31a1d8b 674 }
46ceb60c
SG		 675 } else {
676 priv->mode = SQ_SG_MODE;
677 err = gfar_parse_group(np, priv, model);
678 if(err)
679 goto err_grp_init;
b31a1d8b
AF		 680 }
681
fba4ed03
SG		 682 for (i = 0; i < priv->num_tx_queues; i++)
683 priv->tx_queue[i] = NULL;
684 for (i = 0; i < priv->num_rx_queues; i++)
685 priv->rx_queue[i] = NULL;
686
687 for (i = 0; i < priv->num_tx_queues; i++) {
ed130589 688 priv->tx_queue[i] = (struct gfar_priv_tx_q *)kzalloc(
fba4ed03
SG		 689 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
690 if (!priv->tx_queue[i]) {
691 err = -ENOMEM;
692 goto tx_alloc_failed;
693 }
694 priv->tx_queue[i]->tx_skbuff = NULL;
695 priv->tx_queue[i]->qindex = i;
696 priv->tx_queue[i]->dev = dev;
697 spin_lock_init(&(priv->tx_queue[i]->txlock));
698 }
699
700 for (i = 0; i < priv->num_rx_queues; i++) {
ed130589 701 priv->rx_queue[i] = (struct gfar_priv_rx_q *)kzalloc(
fba4ed03
SG		 702 sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
703 if (!priv->rx_queue[i]) {
704 err = -ENOMEM;
705 goto rx_alloc_failed;
706 }
707 priv->rx_queue[i]->rx_skbuff = NULL;
708 priv->rx_queue[i]->qindex = i;
709 priv->rx_queue[i]->dev = dev;
710 spin_lock_init(&(priv->rx_queue[i]->rxlock));
711 }
712
713
4d7902f2
AF		 714 stash = of_get_property(np, "bd-stash", NULL);
715
a12f801d 716 if (stash) {
4d7902f2
AF		 717 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
718 priv->bd_stash_en = 1;
719 }
720
721 stash_len = of_get_property(np, "rx-stash-len", NULL);
722
723 if (stash_len)
724 priv->rx_stash_size = *stash_len;
725
726 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
727
728 if (stash_idx)
729 priv->rx_stash_index = *stash_idx;
730
731 if (stash_len || stash_idx)
732 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
733
b31a1d8b
AF		 734 mac_addr = of_get_mac_address(np);
735 if (mac_addr)
736 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
737
738 if (model && !strcasecmp(model, "TSEC"))
739 priv->device_flags =
740 FSL_GIANFAR_DEV_HAS_GIGABIT |
741 FSL_GIANFAR_DEV_HAS_COALESCE |
742 FSL_GIANFAR_DEV_HAS_RMON |
743 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
744 if (model && !strcasecmp(model, "eTSEC"))
745 priv->device_flags =
746 FSL_GIANFAR_DEV_HAS_GIGABIT |
747 FSL_GIANFAR_DEV_HAS_COALESCE |
748 FSL_GIANFAR_DEV_HAS_RMON |
749 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
2c2db48a 750 FSL_GIANFAR_DEV_HAS_PADDING |
b31a1d8b
AF		 751 FSL_GIANFAR_DEV_HAS_CSUM |
752 FSL_GIANFAR_DEV_HAS_VLAN |
753 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
97553f7f
MR		 754 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
755 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 756
757 ctype = of_get_property(np, "phy-connection-type", NULL);
758
759 /* We only care about rgmii-id. The rest are autodetected */
760 if (ctype && !strcmp(ctype, "rgmii-id"))
761 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
762 else
763 priv->interface = PHY_INTERFACE_MODE_MII;
764
765 if (of_get_property(np, "fsl,magic-packet", NULL))
766 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
767
fe192a49 768 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 769
770 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 771 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 772
773 return 0;
774
fba4ed03
SG		 775rx_alloc_failed:
776 free_rx_pointers(priv);
777tx_alloc_failed:
778 free_tx_pointers(priv);
46ceb60c
SG		 779err_grp_init:
780 unmap_group_regs(priv);
fba4ed03 781 free_netdev(dev);
b31a1d8b
AF		 782 return err;
783}
784
cc772ab7
MR		 785static int gfar_hwtstamp_ioctl(struct net_device *netdev,
786 struct ifreq *ifr, int cmd)
787{
788 struct hwtstamp_config config;
789 struct gfar_private *priv = netdev_priv(netdev);
790
791 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
792 return -EFAULT;
793
794 /* reserved for future extensions */
795 if (config.flags)
796 return -EINVAL;
797
f0ee7acf
MR		 798 switch (config.tx_type) {
799 case HWTSTAMP_TX_OFF:
800 priv->hwts_tx_en = 0;
801 break;
802 case HWTSTAMP_TX_ON:
803 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
804 return -ERANGE;
805 priv->hwts_tx_en = 1;
806 break;
807 default:
cc772ab7 808 return -ERANGE;
f0ee7acf 809 }
cc772ab7
MR		 810
811 switch (config.rx_filter) {
812 case HWTSTAMP_FILTER_NONE:
97553f7f
MR		 813 if (priv->hwts_rx_en) {
814 stop_gfar(netdev);
815 priv->hwts_rx_en = 0;
816 startup_gfar(netdev);
817 }
cc772ab7
MR		 818 break;
819 default:
820 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
821 return -ERANGE;
97553f7f
MR		 822 if (!priv->hwts_rx_en) {
823 stop_gfar(netdev);
824 priv->hwts_rx_en = 1;
825 startup_gfar(netdev);
826 }
cc772ab7
MR		 827 config.rx_filter = HWTSTAMP_FILTER_ALL;
828 break;
829 }
830
831 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
832 -EFAULT : 0;
833}
834
0faac9f7
CW		 835/* Ioctl MII Interface */
836static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
837{
838 struct gfar_private *priv = netdev_priv(dev);
839
840 if (!netif_running(dev))
841 return -EINVAL;
842
cc772ab7
MR		 843 if (cmd == SIOCSHWTSTAMP)
844 return gfar_hwtstamp_ioctl(dev, rq, cmd);
845
0faac9f7
CW		 846 if (!priv->phydev)
847 return -ENODEV;
848
849 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
850}
851
fba4ed03
SG		 852static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
853{
854 unsigned int new_bit_map = 0x0;
855 int mask = 0x1 << (max_qs - 1), i;
856 for (i = 0; i < max_qs; i++) {
857 if (bit_map & mask)
858 new_bit_map = new_bit_map + (1 << i);
859 mask = mask >> 0x1;
860 }
861 return new_bit_map;
862}
7a8b3372 863
18294ad1
AV		 864static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
865 u32 class)
7a8b3372
SG		 866{
867 u32 rqfpr = FPR_FILER_MASK;
868 u32 rqfcr = 0x0;
869
870 rqfar--;
871 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
872 ftp_rqfpr[rqfar] = rqfpr;
873 ftp_rqfcr[rqfar] = rqfcr;
874 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
875
876 rqfar--;
877 rqfcr = RQFCR_CMP_NOMATCH;
878 ftp_rqfpr[rqfar] = rqfpr;
879 ftp_rqfcr[rqfar] = rqfcr;
880 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
881
882 rqfar--;
883 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
884 rqfpr = class;
885 ftp_rqfcr[rqfar] = rqfcr;
886 ftp_rqfpr[rqfar] = rqfpr;
887 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
888
889 rqfar--;
890 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
891 rqfpr = class;
892 ftp_rqfcr[rqfar] = rqfcr;
893 ftp_rqfpr[rqfar] = rqfpr;
894 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
895
896 return rqfar;
897}
898
899static void gfar_init_filer_table(struct gfar_private *priv)
900{
901 int i = 0x0;
902 u32 rqfar = MAX_FILER_IDX;
903 u32 rqfcr = 0x0;
904 u32 rqfpr = FPR_FILER_MASK;
905
906 /* Default rule */
907 rqfcr = RQFCR_CMP_MATCH;
908 ftp_rqfcr[rqfar] = rqfcr;
909 ftp_rqfpr[rqfar] = rqfpr;
910 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
911
912 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
913 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
914 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
915 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
916 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
917 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
918
919 /* cur_filer_idx indicated the fisrt non-masked rule */
920 priv->cur_filer_idx = rqfar;
921
922 /* Rest are masked rules */
923 rqfcr = RQFCR_CMP_NOMATCH;
924 for (i = 0; i < rqfar; i++) {
925 ftp_rqfcr[i] = rqfcr;
926 ftp_rqfpr[i] = rqfpr;
927 gfar_write_filer(priv, i, rqfcr, rqfpr);
928 }
929}
930
bb40dcbb
AF		 931/* Set up the ethernet device structure, private data,
932 * and anything else we need before we start */
b31a1d8b
AF		 933static int gfar_probe(struct of_device *ofdev,
934 const struct of_device_id *match)
1da177e4
LT		 935{
936 u32 tempval;
937 struct net_device *dev = NULL;
938 struct gfar_private *priv = NULL;
f4983704 939 struct gfar __iomem *regs = NULL;
46ceb60c 940 int err = 0, i, grp_idx = 0;
c50a5d9a 941 int len_devname;
fba4ed03 942 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 943 u32 isrg = 0;
18294ad1 944 u32 __iomem *baddr;
1da177e4 945
fba4ed03 946 err = gfar_of_init(ofdev, &dev);
1da177e4 947
fba4ed03
SG		 948 if (err)
949 return err;
1da177e4
LT		 950
951 priv = netdev_priv(dev);
4826857f
KG		 952 priv->ndev = dev;
953 priv->ofdev = ofdev;
61c7a080 954 priv->node = ofdev->dev.of_node;
4826857f 955 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 956
d87eb127 957 spin_lock_init(&priv->bflock);
ab939905 958 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 959
b31a1d8b 960 dev_set_drvdata(&ofdev->dev, priv);
46ceb60c 961 regs = priv->gfargrp[0].regs;
1da177e4
LT		 962
963 /* Stop the DMA engine now, in case it was running before */
964 /* (The firmware could have used it, and left it running). */
257d938a 965 gfar_halt(dev);
1da177e4
LT		 966
967 /* Reset MAC layer */
f4983704 968 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 969
b98ac702
AF		 970 /* We need to delay at least 3 TX clocks */
971 udelay(2);
972
1da177e4 973 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 974 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 975
976 /* Initialize MACCFG2. */
f4983704 977 gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
1da177e4
LT		 978
979 /* Initialize ECNTRL */
f4983704 980 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 981
1da177e4 982 /* Set the dev->base_addr to the gfar reg region */
f4983704 983 dev->base_addr = (unsigned long) regs;
1da177e4 984
b31a1d8b 985 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 986
987 /* Fill in the dev structure */
1da177e4 988 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 989 dev->mtu = 1500;
26ccfc37 990 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 991 dev->ethtool_ops = &gfar_ethtool_ops;
992
fba4ed03 993 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c
SG		 994 for (i = 0; i < priv->num_grps; i++)
995 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
a12f801d 996
b31a1d8b 997 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
0bbaf069 998 priv->rx_csum_enable = 1;
4669bc90 999 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
0bbaf069
KG		 1000 } else
1001 priv->rx_csum_enable = 0;
1002
1003 priv->vlgrp = NULL;
1da177e4 1004
26ccfc37 1005 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
0bbaf069 1006 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
0bbaf069 1007
b31a1d8b 1008 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 1009 priv->extended_hash = 1;
1010 priv->hash_width = 9;
1011
f4983704
SG		 1012 priv->hash_regs[0] = &regs->igaddr0;
1013 priv->hash_regs[1] = &regs->igaddr1;
1014 priv->hash_regs[2] = &regs->igaddr2;
1015 priv->hash_regs[3] = &regs->igaddr3;
1016 priv->hash_regs[4] = &regs->igaddr4;
1017 priv->hash_regs[5] = &regs->igaddr5;
1018 priv->hash_regs[6] = &regs->igaddr6;
1019 priv->hash_regs[7] = &regs->igaddr7;
1020 priv->hash_regs[8] = &regs->gaddr0;
1021 priv->hash_regs[9] = &regs->gaddr1;
1022 priv->hash_regs[10] = &regs->gaddr2;
1023 priv->hash_regs[11] = &regs->gaddr3;
1024 priv->hash_regs[12] = &regs->gaddr4;
1025 priv->hash_regs[13] = &regs->gaddr5;
1026 priv->hash_regs[14] = &regs->gaddr6;
1027 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 1028
1029 } else {
1030 priv->extended_hash = 0;
1031 priv->hash_width = 8;
1032
f4983704
SG		 1033 priv->hash_regs[0] = &regs->gaddr0;
1034 priv->hash_regs[1] = &regs->gaddr1;
1035 priv->hash_regs[2] = &regs->gaddr2;
1036 priv->hash_regs[3] = &regs->gaddr3;
1037 priv->hash_regs[4] = &regs->gaddr4;
1038 priv->hash_regs[5] = &regs->gaddr5;
1039 priv->hash_regs[6] = &regs->gaddr6;
1040 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 1041 }
1042
b31a1d8b 1043 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 1044 priv->padding = DEFAULT_PADDING;
1045 else
1046 priv->padding = 0;
1047
cc772ab7
MR		 1048 if (dev->features & NETIF_F_IP_CSUM ||
1049 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
0bbaf069 1050 dev->hard_header_len += GMAC_FCB_LEN;
1da177e4 1051
46ceb60c
SG		 1052 /* Program the isrg regs only if number of grps > 1 */
1053 if (priv->num_grps > 1) {
1054 baddr = &regs->isrg0;
1055 for (i = 0; i < priv->num_grps; i++) {
1056 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1057 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1058 gfar_write(baddr, isrg);
1059 baddr++;
1060 isrg = 0x0;
1061 }
1062 }
1063
fba4ed03 1064 /* Need to reverse the bit maps as bit_map's MSB is q0
984b3f57 1065 * but, for_each_set_bit parses from right to left, which
fba4ed03 1066 * basically reverses the queue numbers */
46ceb60c
SG		 1067 for (i = 0; i< priv->num_grps; i++) {
1068 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1069 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1070 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1071 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1072 }
1073
1074 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1075 * also assign queues to groups */
1076 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1077 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
984b3f57 1078 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
46ceb60c
SG		 1079 priv->num_rx_queues) {
1080 priv->gfargrp[grp_idx].num_rx_queues++;
1081 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1082 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1083 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1084 }
1085 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
984b3f57 1086 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
46ceb60c
SG		 1087 priv->num_tx_queues) {
1088 priv->gfargrp[grp_idx].num_tx_queues++;
1089 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1090 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1091 tqueue = tqueue | (TQUEUE_EN0 >> i);
1092 }
1093 priv->gfargrp[grp_idx].rstat = rstat;
1094 priv->gfargrp[grp_idx].tstat = tstat;
1095 rstat = tstat =0;
fba4ed03 1096 }
fba4ed03
SG		 1097
1098 gfar_write(&regs->rqueue, rqueue);
1099 gfar_write(&regs->tqueue, tqueue);
1100
1da177e4 1101 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1102
a12f801d 1103 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1104 for (i = 0; i < priv->num_tx_queues; i++) {
1105 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1106 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1107 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1108 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1109 }
a12f801d 1110
fba4ed03
SG		 1111 for (i = 0; i < priv->num_rx_queues; i++) {
1112 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1113 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1114 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1115 }
1da177e4 1116
1ccb8389
SG		 1117 /* enable filer if using multiple RX queues*/
1118 if(priv->num_rx_queues > 1)
1119 priv->rx_filer_enable = 1;
0bbaf069
KG		 1120 /* Enable most messages by default */
1121 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1122
d3eab82b
TP		 1123 /* Carrier starts down, phylib will bring it up */
1124 netif_carrier_off(dev);
1125
1da177e4
LT		 1126 err = register_netdev(dev);
1127
1128 if (err) {
1129 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1130 dev->name);
1131 goto register_fail;
1132 }
1133
2884e5cc
AV		 1134 device_init_wakeup(&dev->dev,
1135 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1136
c50a5d9a
DH		 1137 /* fill out IRQ number and name fields */
1138 len_devname = strlen(dev->name);
46ceb60c
SG		 1139 for (i = 0; i < priv->num_grps; i++) {
1140 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1141 len_devname);
1142 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1143 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1144 "_g", sizeof("_g"));
1145 priv->gfargrp[i].int_name_tx[
1146 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1147 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1148 priv->gfargrp[i].int_name_tx)],
1149 "_tx", sizeof("_tx") + 1);
1150
1151 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1152 len_devname);
1153 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1154 "_g", sizeof("_g"));
1155 priv->gfargrp[i].int_name_rx[
1156 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1157 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1158 priv->gfargrp[i].int_name_rx)],
1159 "_rx", sizeof("_rx") + 1);
1160
1161 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1162 len_devname);
1163 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1164 "_g", sizeof("_g"));
1165 priv->gfargrp[i].int_name_er[strlen(
1166 priv->gfargrp[i].int_name_er)] = i+48;
1167 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1168 priv->gfargrp[i].int_name_er)],
1169 "_er", sizeof("_er") + 1);
1170 } else
1171 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1172 }
c50a5d9a 1173
7a8b3372
SG		 1174 /* Initialize the filer table */
1175 gfar_init_filer_table(priv);
1176
7f7f5316
AF		 1177 /* Create all the sysfs files */
1178 gfar_init_sysfs(dev);
1179
1da177e4 1180 /* Print out the device info */
e174961c 1181 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1da177e4
LT		 1182
1183 /* Even more device info helps when determining which kernel */
7f7f5316 1184 /* provided which set of benchmarks. */
1da177e4 1185 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
fba4ed03 1186 for (i = 0; i < priv->num_rx_queues; i++)
ddc01b3b 1187 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
fba4ed03
SG		 1188 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1189 for(i = 0; i < priv->num_tx_queues; i++)
ddc01b3b 1190 printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
fba4ed03 1191 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1192
1193 return 0;
1194
1195register_fail:
46ceb60c 1196 unmap_group_regs(priv);
fba4ed03
SG		 1197 free_tx_pointers(priv);
1198 free_rx_pointers(priv);
fe192a49
GL		 1199 if (priv->phy_node)
1200 of_node_put(priv->phy_node);
1201 if (priv->tbi_node)
1202 of_node_put(priv->tbi_node);
1da177e4 1203 free_netdev(dev);
bb40dcbb 1204 return err;
1da177e4
LT		 1205}
1206
b31a1d8b 1207static int gfar_remove(struct of_device *ofdev)
1da177e4 1208{
b31a1d8b 1209 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 1210
fe192a49
GL		 1211 if (priv->phy_node)
1212 of_node_put(priv->phy_node);
1213 if (priv->tbi_node)
1214 of_node_put(priv->tbi_node);
1215
b31a1d8b 1216 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 1217
d9d8e041 1218 unregister_netdev(priv->ndev);
46ceb60c 1219 unmap_group_regs(priv);
4826857f 1220 free_netdev(priv->ndev);
1da177e4
LT		 1221
1222 return 0;
1223}
1224
d87eb127 1225#ifdef CONFIG_PM
be926fc4
AV		 1226
1227static int gfar_suspend(struct device *dev)
d87eb127 1228{
be926fc4
AV		 1229 struct gfar_private *priv = dev_get_drvdata(dev);
1230 struct net_device *ndev = priv->ndev;
46ceb60c 1231 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1232 unsigned long flags;
1233 u32 tempval;
1234
1235 int magic_packet = priv->wol_en &&
b31a1d8b 1236 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1237
be926fc4 1238 netif_device_detach(ndev);
d87eb127 1239
be926fc4 1240 if (netif_running(ndev)) {
fba4ed03
SG		 1241
1242 local_irq_save(flags);
1243 lock_tx_qs(priv);
1244 lock_rx_qs(priv);
d87eb127 1245
be926fc4 1246 gfar_halt_nodisable(ndev);
d87eb127
SW		 1247
1248 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1249 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1250
1251 tempval &= ~MACCFG1_TX_EN;
1252
1253 if (!magic_packet)
1254 tempval &= ~MACCFG1_RX_EN;
1255
f4983704 1256 gfar_write(&regs->maccfg1, tempval);
d87eb127 1257
fba4ed03
SG		 1258 unlock_rx_qs(priv);
1259 unlock_tx_qs(priv);
1260 local_irq_restore(flags);
d87eb127 1261
46ceb60c 1262 disable_napi(priv);
d87eb127
SW		 1263
1264 if (magic_packet) {
1265 /* Enable interrupt on Magic Packet */
f4983704 1266 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1267
1268 /* Enable Magic Packet mode */
f4983704 1269 tempval = gfar_read(&regs->maccfg2);
d87eb127 1270 tempval |= MACCFG2_MPEN;
f4983704 1271 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1272 } else {
1273 phy_stop(priv->phydev);
1274 }
1275 }
1276
1277 return 0;
1278}
1279
be926fc4 1280static int gfar_resume(struct device *dev)
d87eb127 1281{
be926fc4
AV		 1282 struct gfar_private *priv = dev_get_drvdata(dev);
1283 struct net_device *ndev = priv->ndev;
46ceb60c 1284 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1285 unsigned long flags;
1286 u32 tempval;
1287 int magic_packet = priv->wol_en &&
b31a1d8b 1288 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1289
be926fc4
AV		 1290 if (!netif_running(ndev)) {
1291 netif_device_attach(ndev);
d87eb127
SW		 1292 return 0;
1293 }
1294
1295 if (!magic_packet && priv->phydev)
1296 phy_start(priv->phydev);
1297
1298 /* Disable Magic Packet mode, in case something
1299 * else woke us up.
1300 */
fba4ed03
SG		 1301 local_irq_save(flags);
1302 lock_tx_qs(priv);
1303 lock_rx_qs(priv);
d87eb127 1304
f4983704 1305 tempval = gfar_read(&regs->maccfg2);
d87eb127 1306 tempval &= ~MACCFG2_MPEN;
f4983704 1307 gfar_write(&regs->maccfg2, tempval);
d87eb127 1308
be926fc4 1309 gfar_start(ndev);
d87eb127 1310
fba4ed03
SG		 1311 unlock_rx_qs(priv);
1312 unlock_tx_qs(priv);
1313 local_irq_restore(flags);
d87eb127 1314
be926fc4
AV		 1315 netif_device_attach(ndev);
1316
46ceb60c 1317 enable_napi(priv);
be926fc4
AV		 1318
1319 return 0;
1320}
1321
1322static int gfar_restore(struct device *dev)
1323{
1324 struct gfar_private *priv = dev_get_drvdata(dev);
1325 struct net_device *ndev = priv->ndev;
1326
1327 if (!netif_running(ndev))
1328 return 0;
1329
1330 gfar_init_bds(ndev);
1331 init_registers(ndev);
1332 gfar_set_mac_address(ndev);
1333 gfar_init_mac(ndev);
1334 gfar_start(ndev);
1335
1336 priv->oldlink = 0;
1337 priv->oldspeed = 0;
1338 priv->oldduplex = -1;
1339
1340 if (priv->phydev)
1341 phy_start(priv->phydev);
d87eb127 1342
be926fc4 1343 netif_device_attach(ndev);
5ea681d4 1344 enable_napi(priv);
d87eb127
SW		 1345
1346 return 0;
1347}
be926fc4
AV		 1348
1349static struct dev_pm_ops gfar_pm_ops = {
1350 .suspend = gfar_suspend,
1351 .resume = gfar_resume,
1352 .freeze = gfar_suspend,
1353 .thaw = gfar_resume,
1354 .restore = gfar_restore,
1355};
1356
1357#define GFAR_PM_OPS (&gfar_pm_ops)
1358
d87eb127 1359#else
be926fc4
AV		 1360
1361#define GFAR_PM_OPS NULL
be926fc4 1362
d87eb127 1363#endif
1da177e4 1364
e8a2b6a4
AF		 1365/* Reads the controller's registers to determine what interface
1366 * connects it to the PHY.
1367 */
1368static phy_interface_t gfar_get_interface(struct net_device *dev)
1369{
1370 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1371 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1372 u32 ecntrl;
1373
f4983704 1374 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1375
1376 if (ecntrl & ECNTRL_SGMII_MODE)
1377 return PHY_INTERFACE_MODE_SGMII;
1378
1379 if (ecntrl & ECNTRL_TBI_MODE) {
1380 if (ecntrl & ECNTRL_REDUCED_MODE)
1381 return PHY_INTERFACE_MODE_RTBI;
1382 else
1383 return PHY_INTERFACE_MODE_TBI;
1384 }
1385
1386 if (ecntrl & ECNTRL_REDUCED_MODE) {
1387 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1388 return PHY_INTERFACE_MODE_RMII;
7132ab7f 1389 else {
b31a1d8b 1390 phy_interface_t interface = priv->interface;
7132ab7f
AF		 1391
1392 /*
1393 * This isn't autodetected right now, so it must
1394 * be set by the device tree or platform code.
1395 */
1396 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1397 return PHY_INTERFACE_MODE_RGMII_ID;
1398
e8a2b6a4 1399 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1400 }
e8a2b6a4
AF		 1401 }
1402
b31a1d8b 1403 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1404 return PHY_INTERFACE_MODE_GMII;
1405
1406 return PHY_INTERFACE_MODE_MII;
1407}
1408
1409
bb40dcbb
AF		 1410/* Initializes driver's PHY state, and attaches to the PHY.
1411 * Returns 0 on success.
1da177e4
LT		 1412 */
1413static int init_phy(struct net_device *dev)
1414{
1415 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1416 uint gigabit_support =
b31a1d8b 1417 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1418 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1419 phy_interface_t interface;
1da177e4
LT		 1420
1421 priv->oldlink = 0;
1422 priv->oldspeed = 0;
1423 priv->oldduplex = -1;
1424
e8a2b6a4
AF		 1425 interface = gfar_get_interface(dev);
1426
1db780f8
AV		 1427 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1428 interface);
1429 if (!priv->phydev)
1430 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1431 interface);
1432 if (!priv->phydev) {
1433 dev_err(&dev->dev, "could not attach to PHY\n");
1434 return -ENODEV;
fe192a49 1435 }
1da177e4 1436
d3c12873
KJ		 1437 if (interface == PHY_INTERFACE_MODE_SGMII)
1438 gfar_configure_serdes(dev);
1439
bb40dcbb 1440 /* Remove any features not supported by the controller */
fe192a49
GL		 1441 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1442 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1443
1444 return 0;
1da177e4
LT		 1445}
1446
d0313587
PG		 1447/*
1448 * Initialize TBI PHY interface for communicating with the
1449 * SERDES lynx PHY on the chip. We communicate with this PHY
1450 * through the MDIO bus on each controller, treating it as a
1451 * "normal" PHY at the address found in the TBIPA register. We assume
1452 * that the TBIPA register is valid. Either the MDIO bus code will set
1453 * it to a value that doesn't conflict with other PHYs on the bus, or the
1454 * value doesn't matter, as there are no other PHYs on the bus.
1455 */
d3c12873
KJ		 1456static void gfar_configure_serdes(struct net_device *dev)
1457{
1458 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1459 struct phy_device *tbiphy;
1460
1461 if (!priv->tbi_node) {
1462 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1463 "device tree specify a tbi-handle\n");
1464 return;
1465 }
c132419e 1466
fe192a49
GL		 1467 tbiphy = of_phy_find_device(priv->tbi_node);
1468 if (!tbiphy) {
1469 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1470 return;
1471 }
d3c12873 1472
b31a1d8b
AF		 1473 /*
1474 * If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1475 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1476 * everything for us? Resetting it takes the link down and requires
1477 * several seconds for it to come back.
1478 */
fe192a49 1479 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1480 return;
d3c12873 1481
d0313587 1482 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1483 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1484
fe192a49 1485 phy_write(tbiphy, MII_ADVERTISE,
d3c12873
KJ		 1486 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1487 ADVERTISE_1000XPSE_ASYM);
1488
fe192a49 1489 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
d3c12873
KJ		 1490 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1491}
1492
1da177e4
LT		 1493static void init_registers(struct net_device *dev)
1494{
1495 struct gfar_private *priv = netdev_priv(dev);
f4983704 1496 struct gfar __iomem *regs = NULL;
46ceb60c 1497 int i = 0;
1da177e4 1498
46ceb60c
SG		 1499 for (i = 0; i < priv->num_grps; i++) {
1500 regs = priv->gfargrp[i].regs;
1501 /* Clear IEVENT */
1502 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1503
46ceb60c
SG		 1504 /* Initialize IMASK */
1505 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1506 }
1da177e4 1507
46ceb60c 1508 regs = priv->gfargrp[0].regs;
1da177e4 1509 /* Init hash registers to zero */
f4983704
SG		 1510 gfar_write(&regs->igaddr0, 0);
1511 gfar_write(&regs->igaddr1, 0);
1512 gfar_write(&regs->igaddr2, 0);
1513 gfar_write(&regs->igaddr3, 0);
1514 gfar_write(&regs->igaddr4, 0);
1515 gfar_write(&regs->igaddr5, 0);
1516 gfar_write(&regs->igaddr6, 0);
1517 gfar_write(&regs->igaddr7, 0);
1518
1519 gfar_write(&regs->gaddr0, 0);
1520 gfar_write(&regs->gaddr1, 0);
1521 gfar_write(&regs->gaddr2, 0);
1522 gfar_write(&regs->gaddr3, 0);
1523 gfar_write(&regs->gaddr4, 0);
1524 gfar_write(&regs->gaddr5, 0);
1525 gfar_write(&regs->gaddr6, 0);
1526 gfar_write(&regs->gaddr7, 0);
1da177e4 1527
1da177e4 1528 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1529 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1530 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1531
1532 /* Mask off the CAM interrupts */
f4983704
SG		 1533 gfar_write(&regs->rmon.cam1, 0xffffffff);
1534 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1535 }
1536
1537 /* Initialize the max receive buffer length */
f4983704 1538 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1539
1da177e4 1540 /* Initialize the Minimum Frame Length Register */
f4983704 1541 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1542}
1543
0bbaf069
KG		 1544
1545/* Halt the receive and transmit queues */
d87eb127 1546static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1547{
1548 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1549 struct gfar __iomem *regs = NULL;
1da177e4 1550 u32 tempval;
46ceb60c 1551 int i = 0;
1da177e4 1552
46ceb60c
SG		 1553 for (i = 0; i < priv->num_grps; i++) {
1554 regs = priv->gfargrp[i].regs;
1555 /* Mask all interrupts */
1556 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1557
46ceb60c
SG		 1558 /* Clear all interrupts */
1559 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1560 }
1da177e4 1561
46ceb60c 1562 regs = priv->gfargrp[0].regs;
1da177e4 1563 /* Stop the DMA, and wait for it to stop */
f4983704 1564 tempval = gfar_read(&regs->dmactrl);
1da177e4
LT		 1565 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1566 != (DMACTRL_GRS | DMACTRL_GTS)) {
1567 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1568 gfar_write(&regs->dmactrl, tempval);
1da177e4 1569
761ed01b
AF		 1570 spin_event_timeout(((gfar_read(&regs->ievent) &
1571 (IEVENT_GRSC | IEVENT_GTSC)) ==
1572 (IEVENT_GRSC | IEVENT_GTSC)), -1, 0);
1da177e4 1573 }
d87eb127 1574}
d87eb127
SW		 1575
1576/* Halt the receive and transmit queues */
1577void gfar_halt(struct net_device *dev)
1578{
1579 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1580 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1581 u32 tempval;
1da177e4 1582
2a54adc3
SW		 1583 gfar_halt_nodisable(dev);
1584
1da177e4
LT		 1585 /* Disable Rx and Tx */
1586 tempval = gfar_read(&regs->maccfg1);
1587 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1588 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1589}
1590
46ceb60c
SG		 1591static void free_grp_irqs(struct gfar_priv_grp *grp)
1592{
1593 free_irq(grp->interruptError, grp);
1594 free_irq(grp->interruptTransmit, grp);
1595 free_irq(grp->interruptReceive, grp);
1596}
1597
0bbaf069
KG		 1598void stop_gfar(struct net_device *dev)
1599{
1600 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1601 unsigned long flags;
46ceb60c 1602 int i;
0bbaf069 1603
bb40dcbb
AF		 1604 phy_stop(priv->phydev);
1605
a12f801d 1606
0bbaf069 1607 /* Lock it down */
fba4ed03
SG		 1608 local_irq_save(flags);
1609 lock_tx_qs(priv);
1610 lock_rx_qs(priv);
0bbaf069 1611
0bbaf069 1612 gfar_halt(dev);
1da177e4 1613
fba4ed03
SG		 1614 unlock_rx_qs(priv);
1615 unlock_tx_qs(priv);
1616 local_irq_restore(flags);
1da177e4
LT		 1617
1618 /* Free the IRQs */
b31a1d8b 1619 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1620 for (i = 0; i < priv->num_grps; i++)
1621 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1622 } else {
46ceb60c
SG		 1623 for (i = 0; i < priv->num_grps; i++)
1624 free_irq(priv->gfargrp[i].interruptTransmit,
1625 &priv->gfargrp[i]);
1da177e4
LT		 1626 }
1627
1628 free_skb_resources(priv);
1da177e4
LT		 1629}
1630
fba4ed03 1631static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1632{
1da177e4 1633 struct txbd8 *txbdp;
fba4ed03 1634 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1635 int i, j;
1da177e4 1636
a12f801d 1637 txbdp = tx_queue->tx_bd_base;
1da177e4 1638
a12f801d
SG		 1639 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1640 if (!tx_queue->tx_skbuff[i])
4669bc90 1641 continue;
1da177e4 1642
4826857f 1643 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90
DH		 1644 txbdp->length, DMA_TO_DEVICE);
1645 txbdp->lstatus = 0;
fba4ed03
SG		 1646 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1647 j++) {
4669bc90 1648 txbdp++;
4826857f 1649 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90 1650 txbdp->length, DMA_TO_DEVICE);
1da177e4 1651 }
ad5da7ab 1652 txbdp++;
a12f801d
SG		 1653 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1654 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1655 }
a12f801d 1656 kfree(tx_queue->tx_skbuff);
fba4ed03 1657}
1da177e4 1658
fba4ed03
SG		 1659static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1660{
1661 struct rxbd8 *rxbdp;
1662 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1663 int i;
1da177e4 1664
fba4ed03 1665 rxbdp = rx_queue->rx_bd_base;
1da177e4 1666
a12f801d
SG		 1667 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1668 if (rx_queue->rx_skbuff[i]) {
fba4ed03
SG		 1669 dma_unmap_single(&priv->ofdev->dev,
1670 rxbdp->bufPtr, priv->rx_buffer_size,
e69edd21 1671 DMA_FROM_DEVICE);
a12f801d
SG		 1672 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1673 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1674 }
e69edd21
AV		 1675 rxbdp->lstatus = 0;
1676 rxbdp->bufPtr = 0;
1677 rxbdp++;
1da177e4 1678 }
a12f801d 1679 kfree(rx_queue->rx_skbuff);
fba4ed03 1680}
e69edd21 1681
fba4ed03
SG		 1682/* If there are any tx skbs or rx skbs still around, free them.
1683 * Then free tx_skbuff and rx_skbuff */
1684static void free_skb_resources(struct gfar_private *priv)
1685{
1686 struct gfar_priv_tx_q *tx_queue = NULL;
1687 struct gfar_priv_rx_q *rx_queue = NULL;
1688 int i;
1689
1690 /* Go through all the buffer descriptors and free their data buffers */
1691 for (i = 0; i < priv->num_tx_queues; i++) {
1692 tx_queue = priv->tx_queue[i];
7c0d10d3 1693 if(tx_queue->tx_skbuff)
fba4ed03
SG		 1694 free_skb_tx_queue(tx_queue);
1695 }
1696
1697 for (i = 0; i < priv->num_rx_queues; i++) {
1698 rx_queue = priv->rx_queue[i];
7c0d10d3 1699 if(rx_queue->rx_skbuff)
fba4ed03
SG		 1700 free_skb_rx_queue(rx_queue);
1701 }
1702
1703 dma_free_coherent(&priv->ofdev->dev,
1704 sizeof(struct txbd8) * priv->total_tx_ring_size +
1705 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1706 priv->tx_queue[0]->tx_bd_base,
1707 priv->tx_queue[0]->tx_bd_dma_base);
7df9c43f 1708 skb_queue_purge(&priv->rx_recycle);
1da177e4
LT		 1709}
1710
0bbaf069
KG		 1711void gfar_start(struct net_device *dev)
1712{
1713 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1714 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1715 u32 tempval;
46ceb60c 1716 int i = 0;
0bbaf069
KG		 1717
1718 /* Enable Rx and Tx in MACCFG1 */
1719 tempval = gfar_read(&regs->maccfg1);
1720 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1721 gfar_write(&regs->maccfg1, tempval);
1722
1723 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1724 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1725 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1726 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1727
0bbaf069 1728 /* Make sure we aren't stopped */
f4983704 1729 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1730 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1731 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1732
46ceb60c
SG		 1733 for (i = 0; i < priv->num_grps; i++) {
1734 regs = priv->gfargrp[i].regs;
1735 /* Clear THLT/RHLT, so that the DMA starts polling now */
1736 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1737 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1738 /* Unmask the interrupts we look for */
1739 gfar_write(&regs->imask, IMASK_DEFAULT);
1740 }
12dea57b 1741
1ae5dc34 1742 dev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1743}
1744
46ceb60c 1745void gfar_configure_coalescing(struct gfar_private *priv,
18294ad1 1746 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1747{
46ceb60c 1748 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1749 u32 __iomem *baddr;
46ceb60c 1750 int i = 0;
1da177e4 1751
46ceb60c
SG		 1752 /* Backward compatible case ---- even if we enable
1753 * multiple queues, there's only single reg to program
1754 */
1755 gfar_write(&regs->txic, 0);
1756 if(likely(priv->tx_queue[0]->txcoalescing))
1757 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1da177e4 1758
46ceb60c
SG		 1759 gfar_write(&regs->rxic, 0);
1760 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1761 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
815b97c6 1762
46ceb60c
SG		 1763 if (priv->mode == MQ_MG_MODE) {
1764 baddr = &regs->txic0;
984b3f57 1765 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
46ceb60c
SG		 1766 if (likely(priv->tx_queue[i]->txcoalescing)) {
1767 gfar_write(baddr + i, 0);
1768 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1769 }
1770 }
1771
1772 baddr = &regs->rxic0;
984b3f57 1773 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
46ceb60c
SG		 1774 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1775 gfar_write(baddr + i, 0);
1776 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1777 }
1778 }
1779 }
1780}
1781
1782static int register_grp_irqs(struct gfar_priv_grp *grp)
1783{
1784 struct gfar_private *priv = grp->priv;
1785 struct net_device *dev = priv->ndev;
1786 int err;
1da177e4 1787
1da177e4
LT		 1788 /* If the device has multiple interrupts, register for
1789 * them. Otherwise, only register for the one */
b31a1d8b 1790 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1791 /* Install our interrupt handlers for Error,
1da177e4 1792 * Transmit, and Receive */
46ceb60c
SG		 1793 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1794 grp->int_name_er,grp)) < 0) {
0bbaf069 1795 if (netif_msg_intr(priv))
46ceb60c
SG		 1796 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1797 dev->name, grp->interruptError);
1798
1799 goto err_irq_fail;
1da177e4
LT		 1800 }
1801
46ceb60c
SG		 1802 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1803 0, grp->int_name_tx, grp)) < 0) {
0bbaf069 1804 if (netif_msg_intr(priv))
46ceb60c
SG		 1805 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1806 dev->name, grp->interruptTransmit);
1da177e4
LT		 1807 goto tx_irq_fail;
1808 }
1809
46ceb60c
SG		 1810 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1811 grp->int_name_rx, grp)) < 0) {
0bbaf069 1812 if (netif_msg_intr(priv))
46ceb60c
SG		 1813 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1814 dev->name, grp->interruptReceive);
1da177e4
LT		 1815 goto rx_irq_fail;
1816 }
1817 } else {
46ceb60c
SG		 1818 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1819 grp->int_name_tx, grp)) < 0) {
0bbaf069 1820 if (netif_msg_intr(priv))
46ceb60c
SG		 1821 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1822 dev->name, grp->interruptTransmit);
1da177e4
LT		 1823 goto err_irq_fail;
1824 }
1825 }
1826
46ceb60c
SG		 1827 return 0;
1828
1829rx_irq_fail:
1830 free_irq(grp->interruptTransmit, grp);
1831tx_irq_fail:
1832 free_irq(grp->interruptError, grp);
1833err_irq_fail:
1834 return err;
1835
1836}
1837
1838/* Bring the controller up and running */
1839int startup_gfar(struct net_device *ndev)
1840{
1841 struct gfar_private *priv = netdev_priv(ndev);
1842 struct gfar __iomem *regs = NULL;
1843 int err, i, j;
1844
1845 for (i = 0; i < priv->num_grps; i++) {
1846 regs= priv->gfargrp[i].regs;
1847 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1848 }
1849
1850 regs= priv->gfargrp[0].regs;
1851 err = gfar_alloc_skb_resources(ndev);
1852 if (err)
1853 return err;
1854
1855 gfar_init_mac(ndev);
1856
1857 for (i = 0; i < priv->num_grps; i++) {
1858 err = register_grp_irqs(&priv->gfargrp[i]);
1859 if (err) {
1860 for (j = 0; j < i; j++)
1861 free_grp_irqs(&priv->gfargrp[j]);
1862 goto irq_fail;
1863 }
1864 }
1865
7f7f5316 1866 /* Start the controller */
ccc05c6e 1867 gfar_start(ndev);
1da177e4 1868
826aa4a0
AV		 1869 phy_start(priv->phydev);
1870
46ceb60c
SG		 1871 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1872
1da177e4
LT		 1873 return 0;
1874
46ceb60c 1875irq_fail:
e69edd21 1876 free_skb_resources(priv);
1da177e4
LT		 1877 return err;
1878}
1879
1880/* Called when something needs to use the ethernet device */
1881/* Returns 0 for success. */
1882static int gfar_enet_open(struct net_device *dev)
1883{
94e8cc35 1884 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1885 int err;
1886
46ceb60c 1887 enable_napi(priv);
bea3348e 1888
0fd56bb5
AF		 1889 skb_queue_head_init(&priv->rx_recycle);
1890
1da177e4
LT		 1891 /* Initialize a bunch of registers */
1892 init_registers(dev);
1893
1894 gfar_set_mac_address(dev);
1895
1896 err = init_phy(dev);
1897
a12f801d 1898 if (err) {
46ceb60c 1899 disable_napi(priv);
1da177e4 1900 return err;
bea3348e 1901 }
1da177e4
LT		 1902
1903 err = startup_gfar(dev);
db0e8e3f 1904 if (err) {
46ceb60c 1905 disable_napi(priv);
db0e8e3f
AV		 1906 return err;
1907 }
1da177e4 1908
fba4ed03 1909 netif_tx_start_all_queues(dev);
1da177e4 1910
2884e5cc
AV		 1911 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1912
1da177e4
LT		 1913 return err;
1914}
1915
54dc79fe 1916static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1917{
54dc79fe 1918 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1919
1920 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1921
0bbaf069
KG		 1922 return fcb;
1923}
1924
1925static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1926{
7f7f5316 1927 u8 flags = 0;
0bbaf069
KG		 1928
1929 /* If we're here, it's a IP packet with a TCP or UDP
1930 * payload. We set it to checksum, using a pseudo-header
1931 * we provide
1932 */
7f7f5316 1933 flags = TXFCB_DEFAULT;
0bbaf069 1934
7f7f5316
AF		 1935 /* Tell the controller what the protocol is */
1936 /* And provide the already calculated phcs */
eddc9ec5 1937 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 1938 flags |= TXFCB_UDP;
4bedb452 1939 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 1940 } else
8da32de5 1941 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 1942
1943 /* l3os is the distance between the start of the
1944 * frame (skb->data) and the start of the IP hdr.
1945 * l4os is the distance between the start of the
1946 * l3 hdr and the l4 hdr */
bbe735e4 1947 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
cfe1fc77 1948 fcb->l4os = skb_network_header_len(skb);
0bbaf069 1949
7f7f5316 1950 fcb->flags = flags;
0bbaf069
KG		 1951}
1952
7f7f5316 1953void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 1954{
7f7f5316 1955 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 1956 fcb->vlctl = vlan_tx_tag_get(skb);
1957}
1958
4669bc90
DH		 1959static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1960 struct txbd8 *base, int ring_size)
1961{
1962 struct txbd8 *new_bd = bdp + stride;
1963
1964 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1965}
1966
1967static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1968 int ring_size)
1969{
1970 return skip_txbd(bdp, 1, base, ring_size);
1971}
1972
1da177e4
LT		 1973/* This is called by the kernel when a frame is ready for transmission. */
1974/* It is pointed to by the dev->hard_start_xmit function pointer */
1975static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1976{
1977 struct gfar_private *priv = netdev_priv(dev);
a12f801d 1978 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 1979 struct netdev_queue *txq;
f4983704 1980 struct gfar __iomem *regs = NULL;
0bbaf069 1981 struct txfcb *fcb = NULL;
f0ee7acf 1982 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 1983 u32 lstatus;
f0ee7acf 1984 int i, rq = 0, do_tstamp = 0;
4669bc90 1985 u32 bufaddr;
fef6108d 1986 unsigned long flags;
f0ee7acf
MR		 1987 unsigned int nr_frags, nr_txbds, length;
1988 union skb_shared_tx *shtx;
fba4ed03
SG		 1989
1990 rq = skb->queue_mapping;
1991 tx_queue = priv->tx_queue[rq];
1992 txq = netdev_get_tx_queue(dev, rq);
a12f801d 1993 base = tx_queue->tx_bd_base;
46ceb60c 1994 regs = tx_queue->grp->regs;
f0ee7acf
MR		 1995 shtx = skb_tx(skb);
1996
1997 /* check if time stamp should be generated */
1998 if (unlikely(shtx->hardware && priv->hwts_tx_en))
1999 do_tstamp = 1;
4669bc90 2000
5b28beaf
LY		 2001 /* make space for additional header when fcb is needed */
2002 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
f0ee7acf
MR		 2003 (priv->vlgrp && vlan_tx_tag_present(skb)) ||
2004 unlikely(do_tstamp)) &&
5b28beaf 2005 (skb_headroom(skb) < GMAC_FCB_LEN)) {
54dc79fe
SH		 2006 struct sk_buff *skb_new;
2007
2008 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2009 if (!skb_new) {
2010 dev->stats.tx_errors++;
bd14ba84 2011 kfree_skb(skb);
54dc79fe
SH		 2012 return NETDEV_TX_OK;
2013 }
2014 kfree_skb(skb);
2015 skb = skb_new;
2016 }
2017
4669bc90
DH		 2018 /* total number of fragments in the SKB */
2019 nr_frags = skb_shinfo(skb)->nr_frags;
2020
f0ee7acf
MR		 2021 /* calculate the required number of TxBDs for this skb */
2022 if (unlikely(do_tstamp))
2023 nr_txbds = nr_frags + 2;
2024 else
2025 nr_txbds = nr_frags + 1;
2026
4669bc90 2027 /* check if there is space to queue this packet */
f0ee7acf 2028 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2029 /* no space, stop the queue */
fba4ed03 2030 netif_tx_stop_queue(txq);
4669bc90 2031 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2032 return NETDEV_TX_BUSY;
2033 }
1da177e4
LT		 2034
2035 /* Update transmit stats */
a7f38041
SG		 2036 txq->tx_bytes += skb->len;
2037 txq->tx_packets ++;
1da177e4 2038
a12f801d 2039 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2040 lstatus = txbdp->lstatus;
2041
2042 /* Time stamp insertion requires one additional TxBD */
2043 if (unlikely(do_tstamp))
2044 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2045 tx_queue->tx_ring_size);
1da177e4 2046
4669bc90 2047 if (nr_frags == 0) {
f0ee7acf
MR		 2048 if (unlikely(do_tstamp))
2049 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2050 TXBD_INTERRUPT);
2051 else
2052 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2053 } else {
2054 /* Place the fragment addresses and lengths into the TxBDs */
2055 for (i = 0; i < nr_frags; i++) {
2056 /* Point at the next BD, wrapping as needed */
a12f801d 2057 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2058
2059 length = skb_shinfo(skb)->frags[i].size;
2060
2061 lstatus = txbdp->lstatus | length |
2062 BD_LFLAG(TXBD_READY);
2063
2064 /* Handle the last BD specially */
2065 if (i == nr_frags - 1)
2066 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2067
4826857f 2068 bufaddr = dma_map_page(&priv->ofdev->dev,
4669bc90
DH		 2069 skb_shinfo(skb)->frags[i].page,
2070 skb_shinfo(skb)->frags[i].page_offset,
2071 length,
2072 DMA_TO_DEVICE);
2073
2074 /* set the TxBD length and buffer pointer */
2075 txbdp->bufPtr = bufaddr;
2076 txbdp->lstatus = lstatus;
2077 }
2078
2079 lstatus = txbdp_start->lstatus;
2080 }
1da177e4 2081
0bbaf069 2082 /* Set up checksumming */
12dea57b 2083 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe
SH		 2084 fcb = gfar_add_fcb(skb);
2085 lstatus |= BD_LFLAG(TXBD_TOE);
2086 gfar_tx_checksum(skb, fcb);
0bbaf069
KG		 2087 }
2088
77ecaf2d 2089 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
54dc79fe
SH		 2090 if (unlikely(NULL == fcb)) {
2091 fcb = gfar_add_fcb(skb);
5a5efed4 2092 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 2093 }
54dc79fe
SH		 2094
2095 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 2096 }
2097
f0ee7acf
MR		 2098 /* Setup tx hardware time stamping if requested */
2099 if (unlikely(do_tstamp)) {
2100 shtx->in_progress = 1;
2101 if (fcb == NULL)
2102 fcb = gfar_add_fcb(skb);
2103 fcb->ptp = 1;
2104 lstatus |= BD_LFLAG(TXBD_TOE);
2105 }
2106
4826857f 2107 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
4669bc90 2108 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2109
f0ee7acf
MR		 2110 /*
2111 * If time stamping is requested one additional TxBD must be set up. The
2112 * first TxBD points to the FCB and must have a data length of
2113 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2114 * the full frame length.
2115 */
2116 if (unlikely(do_tstamp)) {
2117 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2118 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2119 (skb_headlen(skb) - GMAC_FCB_LEN);
2120 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2121 } else {
2122 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2123 }
1da177e4 2124
a3bc1f11
AV		 2125 /*
2126 * We can work in parallel with gfar_clean_tx_ring(), except
2127 * when modifying num_txbdfree. Note that we didn't grab the lock
2128 * when we were reading the num_txbdfree and checking for available
2129 * space, that's because outside of this function it can only grow,
2130 * and once we've got needed space, it cannot suddenly disappear.
2131 *
2132 * The lock also protects us from gfar_error(), which can modify
2133 * regs->tstat and thus retrigger the transfers, which is why we
2134 * also must grab the lock before setting ready bit for the first
2135 * to be transmitted BD.
2136 */
2137 spin_lock_irqsave(&tx_queue->txlock, flags);
2138
4669bc90
DH		 2139 /*
2140 * The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2141 * semantics (it requires synchronization between cacheable and
2142 * uncacheable mappings, which eieio doesn't provide and which we
2143 * don't need), thus requiring a more expensive sync instruction. At
2144 * some point, the set of architecture-independent barrier functions
2145 * should be expanded to include weaker barriers.
2146 */
3b6330ce 2147 eieio();
7f7f5316 2148
4669bc90
DH		 2149 txbdp_start->lstatus = lstatus;
2150
0eddba52
AV		 2151 eieio(); /* force lstatus write before tx_skbuff */
2152
2153 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2154
4669bc90
DH		 2155 /* Update the current skb pointer to the next entry we will use
2156 * (wrapping if necessary) */
a12f801d
SG		 2157 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2158 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2159
a12f801d 2160 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2161
2162 /* reduce TxBD free count */
f0ee7acf 2163 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2164
2165 /* If the next BD still needs to be cleaned up, then the bds
2166 are full. We need to tell the kernel to stop sending us stuff. */
a12f801d 2167 if (!tx_queue->num_txbdfree) {
fba4ed03 2168 netif_tx_stop_queue(txq);
1da177e4 2169
09f75cd7 2170 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2171 }
2172
1da177e4 2173 /* Tell the DMA to go go go */
fba4ed03 2174 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2175
2176 /* Unlock priv */
a12f801d 2177 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2178
54dc79fe 2179 return NETDEV_TX_OK;
1da177e4
LT		 2180}
2181
2182/* Stops the kernel queue, and halts the controller */
2183static int gfar_close(struct net_device *dev)
2184{
2185 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2186
46ceb60c 2187 disable_napi(priv);
bea3348e 2188
ab939905 2189 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2190 stop_gfar(dev);
2191
bb40dcbb
AF		 2192 /* Disconnect from the PHY */
2193 phy_disconnect(priv->phydev);
2194 priv->phydev = NULL;
1da177e4 2195
fba4ed03 2196 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2197
2198 return 0;
2199}
2200
1da177e4 2201/* Changes the mac address if the controller is not running. */
f162b9d5 2202static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2203{
7f7f5316 2204 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2205
2206 return 0;
2207}
2208
2209
0bbaf069
KG		 2210/* Enables and disables VLAN insertion/extraction */
2211static void gfar_vlan_rx_register(struct net_device *dev,
2212 struct vlan_group *grp)
2213{
2214 struct gfar_private *priv = netdev_priv(dev);
f4983704 2215 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2216 unsigned long flags;
2217 u32 tempval;
2218
46ceb60c 2219 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2220 local_irq_save(flags);
2221 lock_rx_qs(priv);
0bbaf069 2222
cd1f55a5 2223 priv->vlgrp = grp;
0bbaf069
KG		 2224
2225 if (grp) {
2226 /* Enable VLAN tag insertion */
f4983704 2227 tempval = gfar_read(&regs->tctrl);
0bbaf069
KG		 2228 tempval |= TCTRL_VLINS;
2229
f4983704 2230 gfar_write(&regs->tctrl, tempval);
6aa20a22 2231
0bbaf069 2232 /* Enable VLAN tag extraction */
f4983704 2233 tempval = gfar_read(&regs->rctrl);
77ecaf2d 2234 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
f4983704 2235 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2236 } else {
2237 /* Disable VLAN tag insertion */
f4983704 2238 tempval = gfar_read(&regs->tctrl);
0bbaf069 2239 tempval &= ~TCTRL_VLINS;
f4983704 2240 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2241
2242 /* Disable VLAN tag extraction */
f4983704 2243 tempval = gfar_read(&regs->rctrl);
0bbaf069 2244 tempval &= ~RCTRL_VLEX;
77ecaf2d
DH		 2245 /* If parse is no longer required, then disable parser */
2246 if (tempval & RCTRL_REQ_PARSER)
2247 tempval |= RCTRL_PRSDEP_INIT;
2248 else
2249 tempval &= ~RCTRL_PRSDEP_INIT;
f4983704 2250 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2251 }
2252
77ecaf2d
DH		 2253 gfar_change_mtu(dev, dev->mtu);
2254
fba4ed03
SG		 2255 unlock_rx_qs(priv);
2256 local_irq_restore(flags);
0bbaf069
KG		 2257}
2258
1da177e4
LT		 2259static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2260{
2261 int tempsize, tempval;
2262 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2263 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2264 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2265 int frame_size = new_mtu + ETH_HLEN;
2266
77ecaf2d 2267 if (priv->vlgrp)
faa89577 2268 frame_size += VLAN_HLEN;
0bbaf069 2269
1da177e4 2270 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
0bbaf069
KG		 2271 if (netif_msg_drv(priv))
2272 printk(KERN_ERR "%s: Invalid MTU setting\n",
2273 dev->name);
1da177e4
LT		 2274 return -EINVAL;
2275 }
2276
77ecaf2d
DH		 2277 if (gfar_uses_fcb(priv))
2278 frame_size += GMAC_FCB_LEN;
2279
2280 frame_size += priv->padding;
2281
1da177e4
LT		 2282 tempsize =
2283 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2284 INCREMENTAL_BUFFER_SIZE;
2285
2286 /* Only stop and start the controller if it isn't already
7f7f5316 2287 * stopped, and we changed something */
1da177e4
LT		 2288 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2289 stop_gfar(dev);
2290
2291 priv->rx_buffer_size = tempsize;
2292
2293 dev->mtu = new_mtu;
2294
f4983704
SG		 2295 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2296 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2297
2298 /* If the mtu is larger than the max size for standard
2299 * ethernet frames (ie, a jumbo frame), then set maccfg2
2300 * to allow huge frames, and to check the length */
f4983704 2301 tempval = gfar_read(&regs->maccfg2);
1da177e4
LT		 2302
2303 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
2304 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2305 else
2306 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2307
f4983704 2308 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2309
2310 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2311 startup_gfar(dev);
2312
2313 return 0;
2314}
2315
ab939905 2316/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2317 * transmitted after a set amount of time.
2318 * For now, assume that clearing out all the structures, and
ab939905
SS		 2319 * starting over will fix the problem.
2320 */
2321static void gfar_reset_task(struct work_struct *work)
1da177e4 2322{
ab939905
SS		 2323 struct gfar_private *priv = container_of(work, struct gfar_private,
2324 reset_task);
4826857f 2325 struct net_device *dev = priv->ndev;
1da177e4
LT		 2326
2327 if (dev->flags & IFF_UP) {
fba4ed03 2328 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2329 stop_gfar(dev);
2330 startup_gfar(dev);
fba4ed03 2331 netif_tx_start_all_queues(dev);
1da177e4
LT		 2332 }
2333
263ba320 2334 netif_tx_schedule_all(dev);
1da177e4
LT		 2335}
2336
ab939905
SS		 2337static void gfar_timeout(struct net_device *dev)
2338{
2339 struct gfar_private *priv = netdev_priv(dev);
2340
2341 dev->stats.tx_errors++;
2342 schedule_work(&priv->reset_task);
2343}
2344
1da177e4 2345/* Interrupt Handler for Transmit complete */
a12f801d 2346static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2347{
a12f801d 2348 struct net_device *dev = tx_queue->dev;
d080cd63 2349 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2350 struct gfar_priv_rx_q *rx_queue = NULL;
f0ee7acf 2351 struct txbd8 *bdp, *next = NULL;
4669bc90 2352 struct txbd8 *lbdp = NULL;
a12f801d 2353 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2354 struct sk_buff *skb;
2355 int skb_dirtytx;
a12f801d 2356 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2357 int frags = 0, nr_txbds = 0;
4669bc90 2358 int i;
d080cd63 2359 int howmany = 0;
4669bc90 2360 u32 lstatus;
f0ee7acf
MR		 2361 size_t buflen;
2362 union skb_shared_tx *shtx;
1da177e4 2363
fba4ed03 2364 rx_queue = priv->rx_queue[tx_queue->qindex];
a12f801d
SG		 2365 bdp = tx_queue->dirty_tx;
2366 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2367
a12f801d 2368 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2369 unsigned long flags;
2370
4669bc90 2371 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf
MR		 2372
2373 /*
2374 * When time stamping, one additional TxBD must be freed.
2375 * Also, we need to dma_unmap_single() the TxPAL.
2376 */
2377 shtx = skb_tx(skb);
2378 if (unlikely(shtx->in_progress))
2379 nr_txbds = frags + 2;
2380 else
2381 nr_txbds = frags + 1;
2382
2383 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2384
4669bc90 2385 lstatus = lbdp->lstatus;
1da177e4 2386
4669bc90
DH		 2387 /* Only clean completed frames */
2388 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2389 (lstatus & BD_LENGTH_MASK))
2390 break;
2391
f0ee7acf
MR		 2392 if (unlikely(shtx->in_progress)) {
2393 next = next_txbd(bdp, base, tx_ring_size);
2394 buflen = next->length + GMAC_FCB_LEN;
2395 } else
2396 buflen = bdp->length;
2397
2398 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2399 buflen, DMA_TO_DEVICE);
2400
2401 if (unlikely(shtx->in_progress)) {
2402 struct skb_shared_hwtstamps shhwtstamps;
2403 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2404 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2405 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2406 skb_tstamp_tx(skb, &shhwtstamps);
2407 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2408 bdp = next;
2409 }
81183059 2410
4669bc90
DH		 2411 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2412 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2413
4669bc90 2414 for (i = 0; i < frags; i++) {
4826857f 2415 dma_unmap_page(&priv->ofdev->dev,
4669bc90
DH		 2416 bdp->bufPtr,
2417 bdp->length,
2418 DMA_TO_DEVICE);
2419 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2420 bdp = next_txbd(bdp, base, tx_ring_size);
2421 }
1da177e4 2422
0fd56bb5
AF		 2423 /*
2424 * If there's room in the queue (limit it to rx_buffer_size)
2425 * we add this skb back into the pool, if it's the right size
2426 */
a12f801d 2427 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
0fd56bb5
AF		 2428 skb_recycle_check(skb, priv->rx_buffer_size +
2429 RXBUF_ALIGNMENT))
2430 __skb_queue_head(&priv->rx_recycle, skb);
2431 else
2432 dev_kfree_skb_any(skb);
2433
a12f801d 2434 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2435
4669bc90
DH		 2436 skb_dirtytx = (skb_dirtytx + 1) &
2437 TX_RING_MOD_MASK(tx_ring_size);
2438
2439 howmany++;
a3bc1f11 2440 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2441 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2442 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2443 }
1da177e4 2444
4669bc90 2445 /* If we freed a buffer, we can restart transmission, if necessary */
fba4ed03
SG		 2446 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2447 netif_wake_subqueue(dev, tx_queue->qindex);
1da177e4 2448
4669bc90 2449 /* Update dirty indicators */
a12f801d
SG		 2450 tx_queue->skb_dirtytx = skb_dirtytx;
2451 tx_queue->dirty_tx = bdp;
1da177e4 2452
d080cd63
DH		 2453 return howmany;
2454}
2455
f4983704 2456static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2457{
a6d0b91a
AV		 2458 unsigned long flags;
2459
fba4ed03
SG		 2460 spin_lock_irqsave(&gfargrp->grplock, flags);
2461 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2462 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2463 __napi_schedule(&gfargrp->napi);
8707bdd4
JP		 2464 } else {
2465 /*
2466 * Clear IEVENT, so interrupts aren't called again
2467 * because of the packets that have already arrived.
2468 */
f4983704 2469 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2470 }
fba4ed03 2471 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2472
8c7396ae 2473}
1da177e4 2474
8c7396ae 2475/* Interrupt Handler for Transmit complete */
f4983704 2476static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2477{
f4983704 2478 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2479 return IRQ_HANDLED;
2480}
2481
a12f801d 2482static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6
AF		 2483 struct sk_buff *skb)
2484{
a12f801d 2485 struct net_device *dev = rx_queue->dev;
815b97c6 2486 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2487 dma_addr_t buf;
815b97c6 2488
8a102fe0
AV		 2489 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2490 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2491 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2492}
2493
2494
2495struct sk_buff * gfar_new_skb(struct net_device *dev)
1da177e4 2496{
7f7f5316 2497 unsigned int alignamount;
1da177e4
LT		 2498 struct gfar_private *priv = netdev_priv(dev);
2499 struct sk_buff *skb = NULL;
1da177e4 2500
0fd56bb5
AF		 2501 skb = __skb_dequeue(&priv->rx_recycle);
2502 if (!skb)
2503 skb = netdev_alloc_skb(dev,
2504 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1da177e4 2505
815b97c6 2506 if (!skb)
1da177e4
LT		 2507 return NULL;
2508
7f7f5316 2509 alignamount = RXBUF_ALIGNMENT -
bea3348e 2510 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
7f7f5316 2511
1da177e4
LT		 2512 /* We need the data buffer to be aligned properly. We will reserve
2513 * as many bytes as needed to align the data properly
2514 */
7f7f5316 2515 skb_reserve(skb, alignamount);
a6d36d56 2516 GFAR_CB(skb)->alignamount = alignamount;
1da177e4 2517
1da177e4
LT		 2518 return skb;
2519}
2520
298e1a9e 2521static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2522{
298e1a9e 2523 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2524 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2525 struct gfar_extra_stats *estats = &priv->extra_stats;
2526
2527 /* If the packet was truncated, none of the other errors
2528 * matter */
2529 if (status & RXBD_TRUNCATED) {
2530 stats->rx_length_errors++;
2531
2532 estats->rx_trunc++;
2533
2534 return;
2535 }
2536 /* Count the errors, if there were any */
2537 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2538 stats->rx_length_errors++;
2539
2540 if (status & RXBD_LARGE)
2541 estats->rx_large++;
2542 else
2543 estats->rx_short++;
2544 }
2545 if (status & RXBD_NONOCTET) {
2546 stats->rx_frame_errors++;
2547 estats->rx_nonoctet++;
2548 }
2549 if (status & RXBD_CRCERR) {
2550 estats->rx_crcerr++;
2551 stats->rx_crc_errors++;
2552 }
2553 if (status & RXBD_OVERRUN) {
2554 estats->rx_overrun++;
2555 stats->rx_crc_errors++;
2556 }
2557}
2558
f4983704 2559irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2560{
f4983704 2561 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2562 return IRQ_HANDLED;
2563}
2564
0bbaf069
KG		 2565static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2566{
2567 /* If valid headers were found, and valid sums
2568 * were verified, then we tell the kernel that no
2569 * checksumming is necessary. Otherwise, it is */
7f7f5316 2570 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2571 skb->ip_summed = CHECKSUM_UNNECESSARY;
2572 else
2573 skb->ip_summed = CHECKSUM_NONE;
2574}
2575
2576
1da177e4
LT		 2577/* gfar_process_frame() -- handle one incoming packet if skb
2578 * isn't NULL. */
2579static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2c2db48a 2580 int amount_pull)
1da177e4
LT		 2581{
2582 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2583 struct rxfcb *fcb = NULL;
1da177e4 2584
2c2db48a 2585 int ret;
1da177e4 2586
2c2db48a
DH		 2587 /* fcb is at the beginning if exists */
2588 fcb = (struct rxfcb *)skb->data;
0bbaf069 2589
2c2db48a
DH		 2590 /* Remove the FCB from the skb */
2591 /* Remove the padded bytes, if there are any */
f74dac08
SG		 2592 if (amount_pull) {
2593 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2594 skb_pull(skb, amount_pull);
f74dac08 2595 }
0bbaf069 2596
cc772ab7
MR		 2597 /* Get receive timestamp from the skb */
2598 if (priv->hwts_rx_en) {
2599 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2600 u64 *ns = (u64 *) skb->data;
2601 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2602 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2603 }
2604
2605 if (priv->padding)
2606 skb_pull(skb, priv->padding);
2607
2c2db48a
DH		 2608 if (priv->rx_csum_enable)
2609 gfar_rx_checksum(skb, fcb);
0bbaf069 2610
2c2db48a
DH		 2611 /* Tell the skb what kind of packet this is */
2612 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2613
2c2db48a
DH		 2614 /* Send the packet up the stack */
2615 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2616 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2617 else
2618 ret = netif_receive_skb(skb);
0bbaf069 2619
2c2db48a
DH		 2620 if (NET_RX_DROP == ret)
2621 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 2622
2623 return 0;
2624}
2625
2626/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 2627 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 2628 * of frames handled
2629 */
a12f801d 2630int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2631{
a12f801d 2632 struct net_device *dev = rx_queue->dev;
31de198b 2633 struct rxbd8 *bdp, *base;
1da177e4 2634 struct sk_buff *skb;
2c2db48a
DH		 2635 int pkt_len;
2636 int amount_pull;
1da177e4
LT		 2637 int howmany = 0;
2638 struct gfar_private *priv = netdev_priv(dev);
2639
2640 /* Get the first full descriptor */
a12f801d
SG		 2641 bdp = rx_queue->cur_rx;
2642 base = rx_queue->rx_bd_base;
1da177e4 2643
cc772ab7 2644 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2c2db48a 2645
1da177e4 2646 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2647 struct sk_buff *newskb;
3b6330ce 2648 rmb();
815b97c6
AF		 2649
2650 /* Add another skb for the future */
2651 newskb = gfar_new_skb(dev);
2652
a12f801d 2653 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2654
4826857f 2655 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
81183059
AF		 2656 priv->rx_buffer_size, DMA_FROM_DEVICE);
2657
63b88b90
AV		 2658 if (unlikely(!(bdp->status & RXBD_ERR) &&
2659 bdp->length > priv->rx_buffer_size))
2660 bdp->status = RXBD_LARGE;
2661
815b97c6
AF		 2662 /* We drop the frame if we failed to allocate a new buffer */
2663 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2664 bdp->status & RXBD_ERR)) {
2665 count_errors(bdp->status, dev);
2666
2667 if (unlikely(!newskb))
2668 newskb = skb;
4e2fd555
LB		 2669 else if (skb) {
2670 /*
a6d36d56 2671 * We need to un-reserve() the skb to what it
4e2fd555
LB		 2672 * was before gfar_new_skb() re-aligned
2673 * it to an RXBUF_ALIGNMENT boundary
2674 * before we put the skb back on the
2675 * recycle list.
2676 */
a6d36d56 2677 skb_reserve(skb, -GFAR_CB(skb)->alignamount);
0fd56bb5 2678 __skb_queue_head(&priv->rx_recycle, skb);
4e2fd555 2679 }
815b97c6 2680 } else {
1da177e4 2681 /* Increment the number of packets */
a7f38041 2682 rx_queue->stats.rx_packets++;
1da177e4
LT		 2683 howmany++;
2684
2c2db48a
DH		 2685 if (likely(skb)) {
2686 pkt_len = bdp->length - ETH_FCS_LEN;
2687 /* Remove the FCS from the packet length */
2688 skb_put(skb, pkt_len);
a7f38041 2689 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2690 skb_record_rx_queue(skb, rx_queue->qindex);
2c2db48a
DH		 2691 gfar_process_frame(dev, skb, amount_pull);
2692
2693 } else {
2694 if (netif_msg_rx_err(priv))
2695 printk(KERN_WARNING
2696 "%s: Missing skb!\n", dev->name);
a7f38041 2697 rx_queue->stats.rx_dropped++;
2c2db48a
DH		 2698 priv->extra_stats.rx_skbmissing++;
2699 }
1da177e4 2700
1da177e4
LT		 2701 }
2702
a12f801d 2703 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2704
815b97c6 2705 /* Setup the new bdp */
a12f801d 2706 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2707
2708 /* Update to the next pointer */
a12f801d 2709 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2710
2711 /* update to point at the next skb */
a12f801d
SG		 2712 rx_queue->skb_currx =
2713 (rx_queue->skb_currx + 1) &
2714 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2715 }
2716
2717 /* Update the current rxbd pointer to be the next one */
a12f801d 2718 rx_queue->cur_rx = bdp;
1da177e4 2719
1da177e4
LT		 2720 return howmany;
2721}
2722
bea3348e 2723static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2724{
fba4ed03
SG		 2725 struct gfar_priv_grp *gfargrp = container_of(napi,
2726 struct gfar_priv_grp, napi);
2727 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2728 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2729 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03
SG		 2730 struct gfar_priv_rx_q *rx_queue = NULL;
2731 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
18294ad1
AV		 2732 int tx_cleaned = 0, i, left_over_budget = budget;
2733 unsigned long serviced_queues = 0;
fba4ed03 2734 int num_queues = 0;
d080cd63 2735
fba4ed03
SG		 2736 num_queues = gfargrp->num_rx_queues;
2737 budget_per_queue = budget/num_queues;
2738
8c7396ae
DH		 2739 /* Clear IEVENT, so interrupts aren't called again
2740 * because of the packets that have already arrived */
f4983704 2741 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2742
fba4ed03 2743 while (num_queues && left_over_budget) {
1da177e4 2744
fba4ed03
SG		 2745 budget_per_queue = left_over_budget/num_queues;
2746 left_over_budget = 0;
2747
984b3f57 2748 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
fba4ed03
SG		 2749 if (test_bit(i, &serviced_queues))
2750 continue;
2751 rx_queue = priv->rx_queue[i];
2752 tx_queue = priv->tx_queue[rx_queue->qindex];
2753
a3bc1f11 2754 tx_cleaned += gfar_clean_tx_ring(tx_queue);
fba4ed03
SG		 2755 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2756 budget_per_queue);
2757 rx_cleaned += rx_cleaned_per_queue;
2758 if(rx_cleaned_per_queue < budget_per_queue) {
2759 left_over_budget = left_over_budget +
2760 (budget_per_queue - rx_cleaned_per_queue);
2761 set_bit(i, &serviced_queues);
2762 num_queues--;
2763 }
2764 }
2765 }
1da177e4 2766
42199884
AF		 2767 if (tx_cleaned)
2768 return budget;
2769
2770 if (rx_cleaned < budget) {
288379f0 2771 napi_complete(napi);
1da177e4
LT		 2772
2773 /* Clear the halt bit in RSTAT */
fba4ed03 2774 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2775
f4983704 2776 gfar_write(&regs->imask, IMASK_DEFAULT);
1da177e4
LT		 2777
2778 /* If we are coalescing interrupts, update the timer */
2779 /* Otherwise, clear it */
46ceb60c
SG		 2780 gfar_configure_coalescing(priv,
2781 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
1da177e4
LT		 2782 }
2783
42199884 2784 return rx_cleaned;
1da177e4 2785}
1da177e4 2786
f2d71c2d
VW		 2787#ifdef CONFIG_NET_POLL_CONTROLLER
2788/*
2789 * Polling 'interrupt' - used by things like netconsole to send skbs
2790 * without having to re-enable interrupts. It's not called while
2791 * the interrupt routine is executing.
2792 */
2793static void gfar_netpoll(struct net_device *dev)
2794{
2795 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2796 int i = 0;
f2d71c2d
VW		 2797
2798 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2799 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 2800 for (i = 0; i < priv->num_grps; i++) {
2801 disable_irq(priv->gfargrp[i].interruptTransmit);
2802 disable_irq(priv->gfargrp[i].interruptReceive);
2803 disable_irq(priv->gfargrp[i].interruptError);
2804 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2805 &priv->gfargrp[i]);
2806 enable_irq(priv->gfargrp[i].interruptError);
2807 enable_irq(priv->gfargrp[i].interruptReceive);
2808 enable_irq(priv->gfargrp[i].interruptTransmit);
2809 }
f2d71c2d 2810 } else {
46ceb60c
SG		 2811 for (i = 0; i < priv->num_grps; i++) {
2812 disable_irq(priv->gfargrp[i].interruptTransmit);
2813 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2814 &priv->gfargrp[i]);
2815 enable_irq(priv->gfargrp[i].interruptTransmit);
43de004b 2816 }
f2d71c2d
VW		 2817 }
2818}
2819#endif
2820
1da177e4 2821/* The interrupt handler for devices with one interrupt */
f4983704 2822static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2823{
f4983704 2824 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2825
2826 /* Save ievent for future reference */
f4983704 2827 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2828
1da177e4 2829 /* Check for reception */
538cc7ee 2830 if (events & IEVENT_RX_MASK)
f4983704 2831 gfar_receive(irq, grp_id);
1da177e4
LT		 2832
2833 /* Check for transmit completion */
538cc7ee 2834 if (events & IEVENT_TX_MASK)
f4983704 2835 gfar_transmit(irq, grp_id);
1da177e4 2836
538cc7ee
SS		 2837 /* Check for errors */
2838 if (events & IEVENT_ERR_MASK)
f4983704 2839 gfar_error(irq, grp_id);
1da177e4
LT		 2840
2841 return IRQ_HANDLED;
2842}
2843
1da177e4
LT		 2844/* Called every time the controller might need to be made
2845 * aware of new link state. The PHY code conveys this
bb40dcbb 2846 * information through variables in the phydev structure, and this
1da177e4
LT		 2847 * function converts those variables into the appropriate
2848 * register values, and can bring down the device if needed.
2849 */
2850static void adjust_link(struct net_device *dev)
2851{
2852 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2853 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2854 unsigned long flags;
2855 struct phy_device *phydev = priv->phydev;
2856 int new_state = 0;
2857
fba4ed03
SG		 2858 local_irq_save(flags);
2859 lock_tx_qs(priv);
2860
bb40dcbb
AF		 2861 if (phydev->link) {
2862 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2863 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2864
1da177e4
LT		 2865 /* Now we make sure that we can be in full duplex mode.
2866 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 2867 if (phydev->duplex != priv->oldduplex) {
2868 new_state = 1;
2869 if (!(phydev->duplex))
1da177e4 2870 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2871 else
1da177e4 2872 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2873
bb40dcbb 2874 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2875 }
2876
bb40dcbb
AF		 2877 if (phydev->speed != priv->oldspeed) {
2878 new_state = 1;
2879 switch (phydev->speed) {
1da177e4 2880 case 1000:
1da177e4
LT		 2881 tempval =
2882 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 2883
2884 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2885 break;
2886 case 100:
2887 case 10:
1da177e4
LT		 2888 tempval =
2889 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 2890
2891 /* Reduced mode distinguishes
2892 * between 10 and 100 */
2893 if (phydev->speed == SPEED_100)
2894 ecntrl |= ECNTRL_R100;
2895 else
2896 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2897 break;
2898 default:
0bbaf069
KG		 2899 if (netif_msg_link(priv))
2900 printk(KERN_WARNING
bb40dcbb
AF		 2901 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2902 dev->name, phydev->speed);
1da177e4
LT		 2903 break;
2904 }
2905
bb40dcbb 2906 priv->oldspeed = phydev->speed;
1da177e4
LT		 2907 }
2908
bb40dcbb 2909 gfar_write(&regs->maccfg2, tempval);
7f7f5316 2910 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 2911
1da177e4 2912 if (!priv->oldlink) {
bb40dcbb 2913 new_state = 1;
1da177e4 2914 priv->oldlink = 1;
1da177e4 2915 }
bb40dcbb
AF		 2916 } else if (priv->oldlink) {
2917 new_state = 1;
2918 priv->oldlink = 0;
2919 priv->oldspeed = 0;
2920 priv->oldduplex = -1;
1da177e4 2921 }
1da177e4 2922
bb40dcbb
AF		 2923 if (new_state && netif_msg_link(priv))
2924 phy_print_status(phydev);
fba4ed03
SG		 2925 unlock_tx_qs(priv);
2926 local_irq_restore(flags);
bb40dcbb 2927}
1da177e4
LT		 2928
2929/* Update the hash table based on the current list of multicast
2930 * addresses we subscribe to. Also, change the promiscuity of
2931 * the device based on the flags (this function is called
2932 * whenever dev->flags is changed */
2933static void gfar_set_multi(struct net_device *dev)
2934{
22bedad3 2935 struct netdev_hw_addr *ha;
1da177e4 2936 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2937 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 2938 u32 tempval;
2939
a12f801d 2940 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 2941 /* Set RCTRL to PROM */
2942 tempval = gfar_read(&regs->rctrl);
2943 tempval |= RCTRL_PROM;
2944 gfar_write(&regs->rctrl, tempval);
2945 } else {
2946 /* Set RCTRL to not PROM */
2947 tempval = gfar_read(&regs->rctrl);
2948 tempval &= ~(RCTRL_PROM);
2949 gfar_write(&regs->rctrl, tempval);
2950 }
6aa20a22 2951
a12f801d 2952 if (dev->flags & IFF_ALLMULTI) {
1da177e4 2953 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 2954 gfar_write(&regs->igaddr0, 0xffffffff);
2955 gfar_write(&regs->igaddr1, 0xffffffff);
2956 gfar_write(&regs->igaddr2, 0xffffffff);
2957 gfar_write(&regs->igaddr3, 0xffffffff);
2958 gfar_write(&regs->igaddr4, 0xffffffff);
2959 gfar_write(&regs->igaddr5, 0xffffffff);
2960 gfar_write(&regs->igaddr6, 0xffffffff);
2961 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 2962 gfar_write(&regs->gaddr0, 0xffffffff);
2963 gfar_write(&regs->gaddr1, 0xffffffff);
2964 gfar_write(&regs->gaddr2, 0xffffffff);
2965 gfar_write(&regs->gaddr3, 0xffffffff);
2966 gfar_write(&regs->gaddr4, 0xffffffff);
2967 gfar_write(&regs->gaddr5, 0xffffffff);
2968 gfar_write(&regs->gaddr6, 0xffffffff);
2969 gfar_write(&regs->gaddr7, 0xffffffff);
2970 } else {
7f7f5316
AF		 2971 int em_num;
2972 int idx;
2973
1da177e4 2974 /* zero out the hash */
0bbaf069
KG		 2975 gfar_write(&regs->igaddr0, 0x0);
2976 gfar_write(&regs->igaddr1, 0x0);
2977 gfar_write(&regs->igaddr2, 0x0);
2978 gfar_write(&regs->igaddr3, 0x0);
2979 gfar_write(&regs->igaddr4, 0x0);
2980 gfar_write(&regs->igaddr5, 0x0);
2981 gfar_write(&regs->igaddr6, 0x0);
2982 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 2983 gfar_write(&regs->gaddr0, 0x0);
2984 gfar_write(&regs->gaddr1, 0x0);
2985 gfar_write(&regs->gaddr2, 0x0);
2986 gfar_write(&regs->gaddr3, 0x0);
2987 gfar_write(&regs->gaddr4, 0x0);
2988 gfar_write(&regs->gaddr5, 0x0);
2989 gfar_write(&regs->gaddr6, 0x0);
2990 gfar_write(&regs->gaddr7, 0x0);
2991
7f7f5316
AF		 2992 /* If we have extended hash tables, we need to
2993 * clear the exact match registers to prepare for
2994 * setting them */
2995 if (priv->extended_hash) {
2996 em_num = GFAR_EM_NUM + 1;
2997 gfar_clear_exact_match(dev);
2998 idx = 1;
2999 } else {
3000 idx = 0;
3001 em_num = 0;
3002 }
3003
4cd24eaf 3004 if (netdev_mc_empty(dev))
1da177e4
LT		 3005 return;
3006
3007 /* Parse the list, and set the appropriate bits */
22bedad3 3008 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3009 if (idx < em_num) {
22bedad3 3010 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3011 idx++;
3012 } else
22bedad3 3013 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3014 }
3015 }
1da177e4
LT		 3016}
3017
7f7f5316
AF		 3018
3019/* Clears each of the exact match registers to zero, so they
3020 * don't interfere with normal reception */
3021static void gfar_clear_exact_match(struct net_device *dev)
3022{
3023 int idx;
3024 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
3025
3026 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3027 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
3028}
3029
1da177e4
LT		 3030/* Set the appropriate hash bit for the given addr */
3031/* The algorithm works like so:
3032 * 1) Take the Destination Address (ie the multicast address), and
3033 * do a CRC on it (little endian), and reverse the bits of the
3034 * result.
3035 * 2) Use the 8 most significant bits as a hash into a 256-entry
3036 * table. The table is controlled through 8 32-bit registers:
3037 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3038 * gaddr7. This means that the 3 most significant bits in the
3039 * hash index which gaddr register to use, and the 5 other bits
3040 * indicate which bit (assuming an IBM numbering scheme, which
3041 * for PowerPC (tm) is usually the case) in the register holds
3042 * the entry. */
3043static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3044{
3045 u32 tempval;
3046 struct gfar_private *priv = netdev_priv(dev);
1da177e4 3047 u32 result = ether_crc(MAC_ADDR_LEN, addr);
0bbaf069
KG		 3048 int width = priv->hash_width;
3049 u8 whichbit = (result >> (32 - width)) & 0x1f;
3050 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3051 u32 value = (1 << (31-whichbit));
3052
0bbaf069 3053 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3054 tempval |= value;
0bbaf069 3055 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3056}
3057
7f7f5316
AF		 3058
3059/* There are multiple MAC Address register pairs on some controllers
3060 * This function sets the numth pair to a given address
3061 */
3062static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
3063{
3064 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3065 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316
AF		 3066 int idx;
3067 char tmpbuf[MAC_ADDR_LEN];
3068 u32 tempval;
f4983704 3069 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3070
3071 macptr += num*2;
3072
3073 /* Now copy it into the mac registers backwards, cuz */
3074 /* little endian is silly */
3075 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3076 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3077
3078 gfar_write(macptr, *((u32 *) (tmpbuf)));
3079
3080 tempval = *((u32 *) (tmpbuf + 4));
3081
3082 gfar_write(macptr+1, tempval);
3083}
3084
1da177e4 3085/* GFAR error interrupt handler */
f4983704 3086static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3087{
f4983704
SG		 3088 struct gfar_priv_grp *gfargrp = grp_id;
3089 struct gfar __iomem *regs = gfargrp->regs;
3090 struct gfar_private *priv= gfargrp->priv;
3091 struct net_device *dev = priv->ndev;
1da177e4
LT		 3092
3093 /* Save ievent for future reference */
f4983704 3094 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3095
3096 /* Clear IEVENT */
f4983704 3097 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3098
3099 /* Magic Packet is not an error. */
b31a1d8b 3100 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3101 (events & IEVENT_MAG))
3102 events &= ~IEVENT_MAG;
1da177e4
LT		 3103
3104 /* Hmm... */
0bbaf069
KG		 3105 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3106 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
f4983704 3107 dev->name, events, gfar_read(&regs->imask));
1da177e4
LT		 3108
3109 /* Update the error counters */
3110 if (events & IEVENT_TXE) {
09f75cd7 3111 dev->stats.tx_errors++;
1da177e4
LT		 3112
3113 if (events & IEVENT_LC)
09f75cd7 3114 dev->stats.tx_window_errors++;
1da177e4 3115 if (events & IEVENT_CRL)
09f75cd7 3116 dev->stats.tx_aborted_errors++;
1da177e4 3117 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3118 unsigned long flags;
3119
0bbaf069 3120 if (netif_msg_tx_err(priv))
538cc7ee
SS		 3121 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3122 "packet dropped.\n", dev->name);
09f75cd7 3123 dev->stats.tx_dropped++;
1da177e4
LT		 3124 priv->extra_stats.tx_underrun++;
3125
836cf7fa
AV		 3126 local_irq_save(flags);
3127 lock_tx_qs(priv);
3128
1da177e4 3129 /* Reactivate the Tx Queues */
fba4ed03 3130 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3131
3132 unlock_tx_qs(priv);
3133 local_irq_restore(flags);
1da177e4 3134 }
0bbaf069
KG		 3135 if (netif_msg_tx_err(priv))
3136 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1da177e4
LT		 3137 }
3138 if (events & IEVENT_BSY) {
09f75cd7 3139 dev->stats.rx_errors++;
1da177e4
LT		 3140 priv->extra_stats.rx_bsy++;
3141
f4983704 3142 gfar_receive(irq, grp_id);
1da177e4 3143
0bbaf069 3144 if (netif_msg_rx_err(priv))
538cc7ee 3145 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
f4983704 3146 dev->name, gfar_read(&regs->rstat));
1da177e4
LT		 3147 }
3148 if (events & IEVENT_BABR) {
09f75cd7 3149 dev->stats.rx_errors++;
1da177e4
LT		 3150 priv->extra_stats.rx_babr++;
3151
0bbaf069 3152 if (netif_msg_rx_err(priv))
538cc7ee 3153 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1da177e4
LT		 3154 }
3155 if (events & IEVENT_EBERR) {
3156 priv->extra_stats.eberr++;
0bbaf069 3157 if (netif_msg_rx_err(priv))
538cc7ee 3158 printk(KERN_DEBUG "%s: bus error\n", dev->name);
1da177e4 3159 }
0bbaf069 3160 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
538cc7ee 3161 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1da177e4
LT		 3162
3163 if (events & IEVENT_BABT) {
3164 priv->extra_stats.tx_babt++;
0bbaf069 3165 if (netif_msg_tx_err(priv))
538cc7ee 3166 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1da177e4
LT		 3167 }
3168 return IRQ_HANDLED;
3169}
3170
b31a1d8b
AF		 3171static struct of_device_id gfar_match[] =
3172{
3173 {
3174 .type = "network",
3175 .compatible = "gianfar",
3176 },
46ceb60c
SG		 3177 {
3178 .compatible = "fsl,etsec2",
3179 },
b31a1d8b
AF		 3180 {},
3181};
e72701ac 3182MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3183
1da177e4 3184/* Structure for a device driver */
b31a1d8b 3185static struct of_platform_driver gfar_driver = {
4018294b
GL		 3186 .driver = {
3187 .name = "fsl-gianfar",
3188 .owner = THIS_MODULE,
3189 .pm = GFAR_PM_OPS,
3190 .of_match_table = gfar_match,
3191 },
1da177e4
LT		 3192 .probe = gfar_probe,
3193 .remove = gfar_remove,
3194};
3195
3196static int __init gfar_init(void)
3197{
1577ecef 3198 return of_register_platform_driver(&gfar_driver);
1da177e4
LT		 3199}
3200
3201static void __exit gfar_exit(void)
3202{
b31a1d8b 3203 of_unregister_platform_driver(&gfar_driver);
1da177e4
LT		 3204}
3205
3206module_init(gfar_init);
3207module_exit(gfar_exit);
3208
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