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net: simplify flags for tx timestamping
[net-next-2.6.git] / drivers / net / gianfar.c
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0bbaf069 1/*
1da177e4
LT		 2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
a12f801d 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 12 *
a12f801d
SG		 13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
0bbaf069 28 *
b31a1d8b
AF		 29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
0bbaf069 39 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
bb40dcbb 43 * of frames or amount of time have passed). In NAPI, the
1da177e4 44 * interrupt handler will signal there is work to be done, and
0aa1538f 45 * exit. This method will start at the last known empty
0bbaf069 46 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
1da177e4 65#include <linux/kernel.h>
1da177e4
LT		 66#include <linux/string.h>
67#include <linux/errno.h>
bb40dcbb 68#include <linux/unistd.h>
1da177e4
LT		 69#include <linux/slab.h>
70#include <linux/interrupt.h>
71#include <linux/init.h>
72#include <linux/delay.h>
73#include <linux/netdevice.h>
74#include <linux/etherdevice.h>
75#include <linux/skbuff.h>
0bbaf069 76#include <linux/if_vlan.h>
1da177e4
LT		 77#include <linux/spinlock.h>
78#include <linux/mm.h>
fe192a49 79#include <linux/of_mdio.h>
b31a1d8b 80#include <linux/of_platform.h>
0bbaf069
KG		 81#include <linux/ip.h>
82#include <linux/tcp.h>
83#include <linux/udp.h>
9c07b884 84#include <linux/in.h>
cc772ab7 85#include <linux/net_tstamp.h>
1da177e4
LT		 86
87#include <asm/io.h>
7d350977 88#include <asm/reg.h>
1da177e4
LT		 89#include <asm/irq.h>
90#include <asm/uaccess.h>
91#include <linux/module.h>
1da177e4
LT		 92#include <linux/dma-mapping.h>
93#include <linux/crc32.h>
bb40dcbb
AF		 94#include <linux/mii.h>
95#include <linux/phy.h>
b31a1d8b
AF		 96#include <linux/phy_fixed.h>
97#include <linux/of.h>
1da177e4
LT		 98
99#include "gianfar.h"
1577ecef 100#include "fsl_pq_mdio.h"
1da177e4
LT		 101
102#define TX_TIMEOUT (1*HZ)
1da177e4
LT		 103#undef BRIEF_GFAR_ERRORS
104#undef VERBOSE_GFAR_ERRORS
105
1da177e4 106const char gfar_driver_name[] = "Gianfar Ethernet";
7f7f5316 107const char gfar_driver_version[] = "1.3";
1da177e4 108
1da177e4
LT		 109static int gfar_enet_open(struct net_device *dev);
110static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 111static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 112static void gfar_timeout(struct net_device *dev);
113static int gfar_close(struct net_device *dev);
815b97c6 114struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 115static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6 116 struct sk_buff *skb);
1da177e4
LT		 117static int gfar_set_mac_address(struct net_device *dev);
118static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 119static irqreturn_t gfar_error(int irq, void *dev_id);
120static irqreturn_t gfar_transmit(int irq, void *dev_id);
121static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 122static void adjust_link(struct net_device *dev);
123static void init_registers(struct net_device *dev);
124static int init_phy(struct net_device *dev);
2dc11581 125static int gfar_probe(struct platform_device *ofdev,
b31a1d8b 126 const struct of_device_id *match);
2dc11581 127static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 128static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 129static void gfar_set_multi(struct net_device *dev);
130static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 131static void gfar_configure_serdes(struct net_device *dev);
bea3348e 132static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 133#ifdef CONFIG_NET_POLL_CONTROLLER
134static void gfar_netpoll(struct net_device *dev);
135#endif
a12f801d
SG		 136int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
137static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a
DH		 138static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
139 int amount_pull);
0bbaf069
KG		 140static void gfar_vlan_rx_register(struct net_device *netdev,
141 struct vlan_group *grp);
7f7f5316 142void gfar_halt(struct net_device *dev);
d87eb127 143static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 144void gfar_start(struct net_device *dev);
145static void gfar_clear_exact_match(struct net_device *dev);
146static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
26ccfc37 147static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 148
1da177e4
LT		 149MODULE_AUTHOR("Freescale Semiconductor, Inc");
150MODULE_DESCRIPTION("Gianfar Ethernet Driver");
151MODULE_LICENSE("GPL");
152
a12f801d 153static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 154 dma_addr_t buf)
155{
8a102fe0
AV		 156 u32 lstatus;
157
158 bdp->bufPtr = buf;
159
160 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 161 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 162 lstatus |= BD_LFLAG(RXBD_WRAP);
163
164 eieio();
165
166 bdp->lstatus = lstatus;
167}
168
8728327e 169static int gfar_init_bds(struct net_device *ndev)
826aa4a0 170{
8728327e 171 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 172 struct gfar_priv_tx_q *tx_queue = NULL;
173 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 174 struct txbd8 *txbdp;
175 struct rxbd8 *rxbdp;
fba4ed03 176 int i, j;
a12f801d 177
fba4ed03
SG		 178 for (i = 0; i < priv->num_tx_queues; i++) {
179 tx_queue = priv->tx_queue[i];
180 /* Initialize some variables in our dev structure */
181 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
182 tx_queue->dirty_tx = tx_queue->tx_bd_base;
183 tx_queue->cur_tx = tx_queue->tx_bd_base;
184 tx_queue->skb_curtx = 0;
185 tx_queue->skb_dirtytx = 0;
186
187 /* Initialize Transmit Descriptor Ring */
188 txbdp = tx_queue->tx_bd_base;
189 for (j = 0; j < tx_queue->tx_ring_size; j++) {
190 txbdp->lstatus = 0;
191 txbdp->bufPtr = 0;
192 txbdp++;
193 }
8728327e 194
fba4ed03
SG		 195 /* Set the last descriptor in the ring to indicate wrap */
196 txbdp--;
197 txbdp->status |= TXBD_WRAP;
8728327e
AV		 198 }
199
fba4ed03
SG		 200 for (i = 0; i < priv->num_rx_queues; i++) {
201 rx_queue = priv->rx_queue[i];
202 rx_queue->cur_rx = rx_queue->rx_bd_base;
203 rx_queue->skb_currx = 0;
204 rxbdp = rx_queue->rx_bd_base;
8728327e 205
fba4ed03
SG		 206 for (j = 0; j < rx_queue->rx_ring_size; j++) {
207 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 208
fba4ed03
SG		 209 if (skb) {
210 gfar_init_rxbdp(rx_queue, rxbdp,
211 rxbdp->bufPtr);
212 } else {
213 skb = gfar_new_skb(ndev);
214 if (!skb) {
215 pr_err("%s: Can't allocate RX buffers\n",
216 ndev->name);
217 goto err_rxalloc_fail;
218 }
219 rx_queue->rx_skbuff[j] = skb;
220
221 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 222 }
8728327e 223
fba4ed03 224 rxbdp++;
8728327e
AV		 225 }
226
8728327e
AV		 227 }
228
229 return 0;
fba4ed03
SG		 230
231err_rxalloc_fail:
232 free_skb_resources(priv);
233 return -ENOMEM;
8728327e
AV		 234}
235
236static int gfar_alloc_skb_resources(struct net_device *ndev)
237{
826aa4a0 238 void *vaddr;
fba4ed03
SG		 239 dma_addr_t addr;
240 int i, j, k;
826aa4a0
AV		 241 struct gfar_private *priv = netdev_priv(ndev);
242 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 243 struct gfar_priv_tx_q *tx_queue = NULL;
244 struct gfar_priv_rx_q *rx_queue = NULL;
245
fba4ed03
SG		 246 priv->total_tx_ring_size = 0;
247 for (i = 0; i < priv->num_tx_queues; i++)
248 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
249
250 priv->total_rx_ring_size = 0;
251 for (i = 0; i < priv->num_rx_queues; i++)
252 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 253
254 /* Allocate memory for the buffer descriptors */
8728327e 255 vaddr = dma_alloc_coherent(dev,
fba4ed03
SG		 256 sizeof(struct txbd8) * priv->total_tx_ring_size +
257 sizeof(struct rxbd8) * priv->total_rx_ring_size,
258 &addr, GFP_KERNEL);
826aa4a0
AV		 259 if (!vaddr) {
260 if (netif_msg_ifup(priv))
261 pr_err("%s: Could not allocate buffer descriptors!\n",
262 ndev->name);
263 return -ENOMEM;
264 }
265
fba4ed03
SG		 266 for (i = 0; i < priv->num_tx_queues; i++) {
267 tx_queue = priv->tx_queue[i];
268 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
269 tx_queue->tx_bd_dma_base = addr;
270 tx_queue->dev = ndev;
271 /* enet DMA only understands physical addresses */
272 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
273 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
274 }
826aa4a0 275
826aa4a0 276 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 277 for (i = 0; i < priv->num_rx_queues; i++) {
278 rx_queue = priv->rx_queue[i];
279 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
280 rx_queue->rx_bd_dma_base = addr;
281 rx_queue->dev = ndev;
282 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
283 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
284 }
826aa4a0
AV		 285
286 /* Setup the skbuff rings */
fba4ed03
SG		 287 for (i = 0; i < priv->num_tx_queues; i++) {
288 tx_queue = priv->tx_queue[i];
289 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
a12f801d 290 tx_queue->tx_ring_size, GFP_KERNEL);
fba4ed03
SG		 291 if (!tx_queue->tx_skbuff) {
292 if (netif_msg_ifup(priv))
293 pr_err("%s: Could not allocate tx_skbuff\n",
294 ndev->name);
295 goto cleanup;
296 }
826aa4a0 297
fba4ed03
SG		 298 for (k = 0; k < tx_queue->tx_ring_size; k++)
299 tx_queue->tx_skbuff[k] = NULL;
300 }
826aa4a0 301
fba4ed03
SG		 302 for (i = 0; i < priv->num_rx_queues; i++) {
303 rx_queue = priv->rx_queue[i];
304 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
a12f801d 305 rx_queue->rx_ring_size, GFP_KERNEL);
826aa4a0 306
fba4ed03
SG		 307 if (!rx_queue->rx_skbuff) {
308 if (netif_msg_ifup(priv))
309 pr_err("%s: Could not allocate rx_skbuff\n",
310 ndev->name);
311 goto cleanup;
312 }
313
314 for (j = 0; j < rx_queue->rx_ring_size; j++)
315 rx_queue->rx_skbuff[j] = NULL;
316 }
826aa4a0 317
8728327e
AV		 318 if (gfar_init_bds(ndev))
319 goto cleanup;
826aa4a0
AV		 320
321 return 0;
322
323cleanup:
324 free_skb_resources(priv);
325 return -ENOMEM;
326}
327
fba4ed03
SG		 328static void gfar_init_tx_rx_base(struct gfar_private *priv)
329{
46ceb60c 330 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 331 u32 __iomem *baddr;
fba4ed03
SG		 332 int i;
333
334 baddr = &regs->tbase0;
335 for(i = 0; i < priv->num_tx_queues; i++) {
336 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
337 baddr += 2;
338 }
339
340 baddr = &regs->rbase0;
341 for(i = 0; i < priv->num_rx_queues; i++) {
342 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
343 baddr += 2;
344 }
345}
346
826aa4a0
AV		 347static void gfar_init_mac(struct net_device *ndev)
348{
349 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 350 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 351 u32 rctrl = 0;
352 u32 tctrl = 0;
353 u32 attrs = 0;
354
fba4ed03
SG		 355 /* write the tx/rx base registers */
356 gfar_init_tx_rx_base(priv);
32c513bc 357
826aa4a0 358 /* Configure the coalescing support */
46ceb60c 359 gfar_configure_coalescing(priv, 0xFF, 0xFF);
fba4ed03 360
1ccb8389 361 if (priv->rx_filer_enable) {
fba4ed03 362 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 363 /* Program the RIR0 reg with the required distribution */
364 gfar_write(&regs->rir0, DEFAULT_RIR0);
365 }
826aa4a0
AV		 366
367 if (priv->rx_csum_enable)
368 rctrl |= RCTRL_CHECKSUMMING;
369
370 if (priv->extended_hash) {
371 rctrl |= RCTRL_EXTHASH;
372
373 gfar_clear_exact_match(ndev);
374 rctrl |= RCTRL_EMEN;
375 }
376
377 if (priv->padding) {
378 rctrl &= ~RCTRL_PAL_MASK;
379 rctrl |= RCTRL_PADDING(priv->padding);
380 }
381
cc772ab7
MR		 382 /* Insert receive time stamps into padding alignment bytes */
383 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
384 rctrl &= ~RCTRL_PAL_MASK;
97553f7f 385 rctrl |= RCTRL_PADDING(8);
cc772ab7
MR		 386 priv->padding = 8;
387 }
388
97553f7f
MR		 389 /* Enable HW time stamping if requested from user space */
390 if (priv->hwts_rx_en)
391 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
392
826aa4a0
AV		 393 /* keep vlan related bits if it's enabled */
394 if (priv->vlgrp) {
395 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
396 tctrl |= TCTRL_VLINS;
397 }
398
399 /* Init rctrl based on our settings */
400 gfar_write(&regs->rctrl, rctrl);
401
402 if (ndev->features & NETIF_F_IP_CSUM)
403 tctrl |= TCTRL_INIT_CSUM;
404
fba4ed03
SG		 405 tctrl |= TCTRL_TXSCHED_PRIO;
406
826aa4a0
AV		 407 gfar_write(&regs->tctrl, tctrl);
408
409 /* Set the extraction length and index */
410 attrs = ATTRELI_EL(priv->rx_stash_size) |
411 ATTRELI_EI(priv->rx_stash_index);
412
413 gfar_write(&regs->attreli, attrs);
414
415 /* Start with defaults, and add stashing or locking
416 * depending on the approprate variables */
417 attrs = ATTR_INIT_SETTINGS;
418
419 if (priv->bd_stash_en)
420 attrs |= ATTR_BDSTASH;
421
422 if (priv->rx_stash_size != 0)
423 attrs |= ATTR_BUFSTASH;
424
425 gfar_write(&regs->attr, attrs);
426
427 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
428 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
429 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
430}
431
a7f38041
SG		 432static struct net_device_stats *gfar_get_stats(struct net_device *dev)
433{
434 struct gfar_private *priv = netdev_priv(dev);
435 struct netdev_queue *txq;
436 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
437 unsigned long tx_packets = 0, tx_bytes = 0;
438 int i = 0;
439
440 for (i = 0; i < priv->num_rx_queues; i++) {
441 rx_packets += priv->rx_queue[i]->stats.rx_packets;
442 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
443 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
444 }
445
446 dev->stats.rx_packets = rx_packets;
447 dev->stats.rx_bytes = rx_bytes;
448 dev->stats.rx_dropped = rx_dropped;
449
450 for (i = 0; i < priv->num_tx_queues; i++) {
451 txq = netdev_get_tx_queue(dev, i);
452 tx_bytes += txq->tx_bytes;
453 tx_packets += txq->tx_packets;
454 }
455
456 dev->stats.tx_bytes = tx_bytes;
457 dev->stats.tx_packets = tx_packets;
458
459 return &dev->stats;
460}
461
26ccfc37
AF		 462static const struct net_device_ops gfar_netdev_ops = {
463 .ndo_open = gfar_enet_open,
464 .ndo_start_xmit = gfar_start_xmit,
465 .ndo_stop = gfar_close,
466 .ndo_change_mtu = gfar_change_mtu,
467 .ndo_set_multicast_list = gfar_set_multi,
468 .ndo_tx_timeout = gfar_timeout,
469 .ndo_do_ioctl = gfar_ioctl,
a7f38041 470 .ndo_get_stats = gfar_get_stats,
26ccfc37 471 .ndo_vlan_rx_register = gfar_vlan_rx_register,
240c102d
BH		 472 .ndo_set_mac_address = eth_mac_addr,
473 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 474#ifdef CONFIG_NET_POLL_CONTROLLER
475 .ndo_poll_controller = gfar_netpoll,
476#endif
477};
478
7a8b3372
SG		 479unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
480unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
481
fba4ed03
SG		 482void lock_rx_qs(struct gfar_private *priv)
483{
484 int i = 0x0;
485
486 for (i = 0; i < priv->num_rx_queues; i++)
487 spin_lock(&priv->rx_queue[i]->rxlock);
488}
489
490void lock_tx_qs(struct gfar_private *priv)
491{
492 int i = 0x0;
493
494 for (i = 0; i < priv->num_tx_queues; i++)
495 spin_lock(&priv->tx_queue[i]->txlock);
496}
497
498void unlock_rx_qs(struct gfar_private *priv)
499{
500 int i = 0x0;
501
502 for (i = 0; i < priv->num_rx_queues; i++)
503 spin_unlock(&priv->rx_queue[i]->rxlock);
504}
505
506void unlock_tx_qs(struct gfar_private *priv)
507{
508 int i = 0x0;
509
510 for (i = 0; i < priv->num_tx_queues; i++)
511 spin_unlock(&priv->tx_queue[i]->txlock);
512}
513
7f7f5316
AF		 514/* Returns 1 if incoming frames use an FCB */
515static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 516{
cc772ab7
MR		 517 return priv->vlgrp || priv->rx_csum_enable ||
518 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
0bbaf069 519}
bb40dcbb 520
fba4ed03
SG		 521static void free_tx_pointers(struct gfar_private *priv)
522{
523 int i = 0;
524
525 for (i = 0; i < priv->num_tx_queues; i++)
526 kfree(priv->tx_queue[i]);
527}
528
529static void free_rx_pointers(struct gfar_private *priv)
530{
531 int i = 0;
532
533 for (i = 0; i < priv->num_rx_queues; i++)
534 kfree(priv->rx_queue[i]);
535}
536
46ceb60c
SG		 537static void unmap_group_regs(struct gfar_private *priv)
538{
539 int i = 0;
540
541 for (i = 0; i < MAXGROUPS; i++)
542 if (priv->gfargrp[i].regs)
543 iounmap(priv->gfargrp[i].regs);
544}
545
546static void disable_napi(struct gfar_private *priv)
547{
548 int i = 0;
549
550 for (i = 0; i < priv->num_grps; i++)
551 napi_disable(&priv->gfargrp[i].napi);
552}
553
554static void enable_napi(struct gfar_private *priv)
555{
556 int i = 0;
557
558 for (i = 0; i < priv->num_grps; i++)
559 napi_enable(&priv->gfargrp[i].napi);
560}
561
562static int gfar_parse_group(struct device_node *np,
563 struct gfar_private *priv, const char *model)
564{
565 u32 *queue_mask;
46ceb60c 566
7ce97d4f 567 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
46ceb60c
SG		 568 if (!priv->gfargrp[priv->num_grps].regs)
569 return -ENOMEM;
570
571 priv->gfargrp[priv->num_grps].interruptTransmit =
572 irq_of_parse_and_map(np, 0);
573
574 /* If we aren't the FEC we have multiple interrupts */
575 if (model && strcasecmp(model, "FEC")) {
576 priv->gfargrp[priv->num_grps].interruptReceive =
577 irq_of_parse_and_map(np, 1);
578 priv->gfargrp[priv->num_grps].interruptError =
579 irq_of_parse_and_map(np,2);
580 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
581 priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
582 priv->gfargrp[priv->num_grps].interruptError < 0) {
583 return -EINVAL;
584 }
585 }
586
587 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
588 priv->gfargrp[priv->num_grps].priv = priv;
589 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
590 if(priv->mode == MQ_MG_MODE) {
591 queue_mask = (u32 *)of_get_property(np,
592 "fsl,rx-bit-map", NULL);
593 priv->gfargrp[priv->num_grps].rx_bit_map =
594 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
595 queue_mask = (u32 *)of_get_property(np,
596 "fsl,tx-bit-map", NULL);
597 priv->gfargrp[priv->num_grps].tx_bit_map =
598 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
599 } else {
600 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
601 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
602 }
603 priv->num_grps++;
604
605 return 0;
606}
607
2dc11581 608static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 609{
b31a1d8b
AF		 610 const char *model;
611 const char *ctype;
612 const void *mac_addr;
fba4ed03
SG		 613 int err = 0, i;
614 struct net_device *dev = NULL;
615 struct gfar_private *priv = NULL;
61c7a080 616 struct device_node *np = ofdev->dev.of_node;
46ceb60c 617 struct device_node *child = NULL;
4d7902f2
AF		 618 const u32 *stash;
619 const u32 *stash_len;
620 const u32 *stash_idx;
fba4ed03
SG		 621 unsigned int num_tx_qs, num_rx_qs;
622 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 623
624 if (!np || !of_device_is_available(np))
625 return -ENODEV;
626
fba4ed03
SG		 627 /* parse the num of tx and rx queues */
628 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
629 num_tx_qs = tx_queues ? *tx_queues : 1;
630
631 if (num_tx_qs > MAX_TX_QS) {
632 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
633 num_tx_qs, MAX_TX_QS);
634 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
635 return -EINVAL;
636 }
637
638 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
639 num_rx_qs = rx_queues ? *rx_queues : 1;
640
641 if (num_rx_qs > MAX_RX_QS) {
642 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
643 num_tx_qs, MAX_TX_QS);
644 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
645 return -EINVAL;
646 }
647
648 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
649 dev = *pdev;
650 if (NULL == dev)
651 return -ENOMEM;
652
653 priv = netdev_priv(dev);
61c7a080 654 priv->node = ofdev->dev.of_node;
fba4ed03
SG		 655 priv->ndev = dev;
656
657 dev->num_tx_queues = num_tx_qs;
658 dev->real_num_tx_queues = num_tx_qs;
659 priv->num_tx_queues = num_tx_qs;
660 priv->num_rx_queues = num_rx_qs;
46ceb60c 661 priv->num_grps = 0x0;
b31a1d8b
AF		 662
663 model = of_get_property(np, "model", NULL);
664
46ceb60c
SG		 665 for (i = 0; i < MAXGROUPS; i++)
666 priv->gfargrp[i].regs = NULL;
b31a1d8b 667
46ceb60c
SG		 668 /* Parse and initialize group specific information */
669 if (of_device_is_compatible(np, "fsl,etsec2")) {
670 priv->mode = MQ_MG_MODE;
671 for_each_child_of_node(np, child) {
672 err = gfar_parse_group(child, priv, model);
673 if (err)
674 goto err_grp_init;
b31a1d8b 675 }
46ceb60c
SG		 676 } else {
677 priv->mode = SQ_SG_MODE;
678 err = gfar_parse_group(np, priv, model);
679 if(err)
680 goto err_grp_init;
b31a1d8b
AF		 681 }
682
fba4ed03
SG		 683 for (i = 0; i < priv->num_tx_queues; i++)
684 priv->tx_queue[i] = NULL;
685 for (i = 0; i < priv->num_rx_queues; i++)
686 priv->rx_queue[i] = NULL;
687
688 for (i = 0; i < priv->num_tx_queues; i++) {
de47f072
JP		 689 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
690 GFP_KERNEL);
fba4ed03
SG		 691 if (!priv->tx_queue[i]) {
692 err = -ENOMEM;
693 goto tx_alloc_failed;
694 }
695 priv->tx_queue[i]->tx_skbuff = NULL;
696 priv->tx_queue[i]->qindex = i;
697 priv->tx_queue[i]->dev = dev;
698 spin_lock_init(&(priv->tx_queue[i]->txlock));
699 }
700
701 for (i = 0; i < priv->num_rx_queues; i++) {
de47f072
JP		 702 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
703 GFP_KERNEL);
fba4ed03
SG		 704 if (!priv->rx_queue[i]) {
705 err = -ENOMEM;
706 goto rx_alloc_failed;
707 }
708 priv->rx_queue[i]->rx_skbuff = NULL;
709 priv->rx_queue[i]->qindex = i;
710 priv->rx_queue[i]->dev = dev;
711 spin_lock_init(&(priv->rx_queue[i]->rxlock));
712 }
713
714
4d7902f2
AF		 715 stash = of_get_property(np, "bd-stash", NULL);
716
a12f801d 717 if (stash) {
4d7902f2
AF		 718 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
719 priv->bd_stash_en = 1;
720 }
721
722 stash_len = of_get_property(np, "rx-stash-len", NULL);
723
724 if (stash_len)
725 priv->rx_stash_size = *stash_len;
726
727 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
728
729 if (stash_idx)
730 priv->rx_stash_index = *stash_idx;
731
732 if (stash_len || stash_idx)
733 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
734
b31a1d8b
AF		 735 mac_addr = of_get_mac_address(np);
736 if (mac_addr)
737 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
738
739 if (model && !strcasecmp(model, "TSEC"))
740 priv->device_flags =
741 FSL_GIANFAR_DEV_HAS_GIGABIT |
742 FSL_GIANFAR_DEV_HAS_COALESCE |
743 FSL_GIANFAR_DEV_HAS_RMON |
744 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
745 if (model && !strcasecmp(model, "eTSEC"))
746 priv->device_flags =
747 FSL_GIANFAR_DEV_HAS_GIGABIT |
748 FSL_GIANFAR_DEV_HAS_COALESCE |
749 FSL_GIANFAR_DEV_HAS_RMON |
750 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
2c2db48a 751 FSL_GIANFAR_DEV_HAS_PADDING |
b31a1d8b
AF		 752 FSL_GIANFAR_DEV_HAS_CSUM |
753 FSL_GIANFAR_DEV_HAS_VLAN |
754 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
97553f7f
MR		 755 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
756 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 757
758 ctype = of_get_property(np, "phy-connection-type", NULL);
759
760 /* We only care about rgmii-id. The rest are autodetected */
761 if (ctype && !strcmp(ctype, "rgmii-id"))
762 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
763 else
764 priv->interface = PHY_INTERFACE_MODE_MII;
765
766 if (of_get_property(np, "fsl,magic-packet", NULL))
767 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
768
fe192a49 769 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 770
771 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 772 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 773
774 return 0;
775
fba4ed03
SG		 776rx_alloc_failed:
777 free_rx_pointers(priv);
778tx_alloc_failed:
779 free_tx_pointers(priv);
46ceb60c
SG		 780err_grp_init:
781 unmap_group_regs(priv);
fba4ed03 782 free_netdev(dev);
b31a1d8b
AF		 783 return err;
784}
785
cc772ab7
MR		 786static int gfar_hwtstamp_ioctl(struct net_device *netdev,
787 struct ifreq *ifr, int cmd)
788{
789 struct hwtstamp_config config;
790 struct gfar_private *priv = netdev_priv(netdev);
791
792 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
793 return -EFAULT;
794
795 /* reserved for future extensions */
796 if (config.flags)
797 return -EINVAL;
798
f0ee7acf
MR		 799 switch (config.tx_type) {
800 case HWTSTAMP_TX_OFF:
801 priv->hwts_tx_en = 0;
802 break;
803 case HWTSTAMP_TX_ON:
804 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
805 return -ERANGE;
806 priv->hwts_tx_en = 1;
807 break;
808 default:
cc772ab7 809 return -ERANGE;
f0ee7acf 810 }
cc772ab7
MR		 811
812 switch (config.rx_filter) {
813 case HWTSTAMP_FILTER_NONE:
97553f7f
MR		 814 if (priv->hwts_rx_en) {
815 stop_gfar(netdev);
816 priv->hwts_rx_en = 0;
817 startup_gfar(netdev);
818 }
cc772ab7
MR		 819 break;
820 default:
821 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
822 return -ERANGE;
97553f7f
MR		 823 if (!priv->hwts_rx_en) {
824 stop_gfar(netdev);
825 priv->hwts_rx_en = 1;
826 startup_gfar(netdev);
827 }
cc772ab7
MR		 828 config.rx_filter = HWTSTAMP_FILTER_ALL;
829 break;
830 }
831
832 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
833 -EFAULT : 0;
834}
835
0faac9f7
CW		 836/* Ioctl MII Interface */
837static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
838{
839 struct gfar_private *priv = netdev_priv(dev);
840
841 if (!netif_running(dev))
842 return -EINVAL;
843
cc772ab7
MR		 844 if (cmd == SIOCSHWTSTAMP)
845 return gfar_hwtstamp_ioctl(dev, rq, cmd);
846
0faac9f7
CW		 847 if (!priv->phydev)
848 return -ENODEV;
849
28b04113 850 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 851}
852
fba4ed03
SG		 853static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
854{
855 unsigned int new_bit_map = 0x0;
856 int mask = 0x1 << (max_qs - 1), i;
857 for (i = 0; i < max_qs; i++) {
858 if (bit_map & mask)
859 new_bit_map = new_bit_map + (1 << i);
860 mask = mask >> 0x1;
861 }
862 return new_bit_map;
863}
7a8b3372 864
18294ad1
AV		 865static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
866 u32 class)
7a8b3372
SG		 867{
868 u32 rqfpr = FPR_FILER_MASK;
869 u32 rqfcr = 0x0;
870
871 rqfar--;
872 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
873 ftp_rqfpr[rqfar] = rqfpr;
874 ftp_rqfcr[rqfar] = rqfcr;
875 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
876
877 rqfar--;
878 rqfcr = RQFCR_CMP_NOMATCH;
879 ftp_rqfpr[rqfar] = rqfpr;
880 ftp_rqfcr[rqfar] = rqfcr;
881 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
882
883 rqfar--;
884 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
885 rqfpr = class;
886 ftp_rqfcr[rqfar] = rqfcr;
887 ftp_rqfpr[rqfar] = rqfpr;
888 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
889
890 rqfar--;
891 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
892 rqfpr = class;
893 ftp_rqfcr[rqfar] = rqfcr;
894 ftp_rqfpr[rqfar] = rqfpr;
895 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
896
897 return rqfar;
898}
899
900static void gfar_init_filer_table(struct gfar_private *priv)
901{
902 int i = 0x0;
903 u32 rqfar = MAX_FILER_IDX;
904 u32 rqfcr = 0x0;
905 u32 rqfpr = FPR_FILER_MASK;
906
907 /* Default rule */
908 rqfcr = RQFCR_CMP_MATCH;
909 ftp_rqfcr[rqfar] = rqfcr;
910 ftp_rqfpr[rqfar] = rqfpr;
911 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
912
913 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
914 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
915 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
916 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
917 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
918 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
919
85dd08eb 920 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 921 priv->cur_filer_idx = rqfar;
922
923 /* Rest are masked rules */
924 rqfcr = RQFCR_CMP_NOMATCH;
925 for (i = 0; i < rqfar; i++) {
926 ftp_rqfcr[i] = rqfcr;
927 ftp_rqfpr[i] = rqfpr;
928 gfar_write_filer(priv, i, rqfcr, rqfpr);
929 }
930}
931
7d350977
AV		 932static void gfar_detect_errata(struct gfar_private *priv)
933{
934 struct device *dev = &priv->ofdev->dev;
935 unsigned int pvr = mfspr(SPRN_PVR);
936 unsigned int svr = mfspr(SPRN_SVR);
937 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
938 unsigned int rev = svr & 0xffff;
939
940 /* MPC8313 Rev 2.0 and higher; All MPC837x */
941 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
942 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
943 priv->errata |= GFAR_ERRATA_74;
944
deb90eac
AV		 945 /* MPC8313 and MPC837x all rev */
946 if ((pvr == 0x80850010 && mod == 0x80b0) ||
947 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
948 priv->errata |= GFAR_ERRATA_76;
949
511d934f
AV		 950 /* MPC8313 and MPC837x all rev */
951 if ((pvr == 0x80850010 && mod == 0x80b0) ||
952 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
953 priv->errata |= GFAR_ERRATA_A002;
954
7d350977
AV		 955 if (priv->errata)
956 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
957 priv->errata);
958}
959
bb40dcbb
AF		 960/* Set up the ethernet device structure, private data,
961 * and anything else we need before we start */
2dc11581 962static int gfar_probe(struct platform_device *ofdev,
b31a1d8b 963 const struct of_device_id *match)
1da177e4
LT		 964{
965 u32 tempval;
966 struct net_device *dev = NULL;
967 struct gfar_private *priv = NULL;
f4983704 968 struct gfar __iomem *regs = NULL;
46ceb60c 969 int err = 0, i, grp_idx = 0;
c50a5d9a 970 int len_devname;
fba4ed03 971 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 972 u32 isrg = 0;
18294ad1 973 u32 __iomem *baddr;
1da177e4 974
fba4ed03 975 err = gfar_of_init(ofdev, &dev);
1da177e4 976
fba4ed03
SG		 977 if (err)
978 return err;
1da177e4
LT		 979
980 priv = netdev_priv(dev);
4826857f
KG		 981 priv->ndev = dev;
982 priv->ofdev = ofdev;
61c7a080 983 priv->node = ofdev->dev.of_node;
4826857f 984 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 985
d87eb127 986 spin_lock_init(&priv->bflock);
ab939905 987 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 988
b31a1d8b 989 dev_set_drvdata(&ofdev->dev, priv);
46ceb60c 990 regs = priv->gfargrp[0].regs;
1da177e4 991
7d350977
AV		 992 gfar_detect_errata(priv);
993
1da177e4
LT		 994 /* Stop the DMA engine now, in case it was running before */
995 /* (The firmware could have used it, and left it running). */
257d938a 996 gfar_halt(dev);
1da177e4
LT		 997
998 /* Reset MAC layer */
f4983704 999 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 1000
b98ac702
AF		 1001 /* We need to delay at least 3 TX clocks */
1002 udelay(2);
1003
1da177e4 1004 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 1005 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 1006
1007 /* Initialize MACCFG2. */
7d350977
AV		 1008 tempval = MACCFG2_INIT_SETTINGS;
1009 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1010 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1011 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 1012
1013 /* Initialize ECNTRL */
f4983704 1014 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 1015
1da177e4 1016 /* Set the dev->base_addr to the gfar reg region */
f4983704 1017 dev->base_addr = (unsigned long) regs;
1da177e4 1018
b31a1d8b 1019 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 1020
1021 /* Fill in the dev structure */
1da177e4 1022 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1023 dev->mtu = 1500;
26ccfc37 1024 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1025 dev->ethtool_ops = &gfar_ethtool_ops;
1026
fba4ed03 1027 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c
SG		 1028 for (i = 0; i < priv->num_grps; i++)
1029 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
a12f801d 1030
b31a1d8b 1031 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
0bbaf069 1032 priv->rx_csum_enable = 1;
4669bc90 1033 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
0bbaf069
KG		 1034 } else
1035 priv->rx_csum_enable = 0;
1036
1037 priv->vlgrp = NULL;
1da177e4 1038
26ccfc37 1039 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
0bbaf069 1040 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
0bbaf069 1041
b31a1d8b 1042 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 1043 priv->extended_hash = 1;
1044 priv->hash_width = 9;
1045
f4983704
SG		 1046 priv->hash_regs[0] = &regs->igaddr0;
1047 priv->hash_regs[1] = &regs->igaddr1;
1048 priv->hash_regs[2] = &regs->igaddr2;
1049 priv->hash_regs[3] = &regs->igaddr3;
1050 priv->hash_regs[4] = &regs->igaddr4;
1051 priv->hash_regs[5] = &regs->igaddr5;
1052 priv->hash_regs[6] = &regs->igaddr6;
1053 priv->hash_regs[7] = &regs->igaddr7;
1054 priv->hash_regs[8] = &regs->gaddr0;
1055 priv->hash_regs[9] = &regs->gaddr1;
1056 priv->hash_regs[10] = &regs->gaddr2;
1057 priv->hash_regs[11] = &regs->gaddr3;
1058 priv->hash_regs[12] = &regs->gaddr4;
1059 priv->hash_regs[13] = &regs->gaddr5;
1060 priv->hash_regs[14] = &regs->gaddr6;
1061 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 1062
1063 } else {
1064 priv->extended_hash = 0;
1065 priv->hash_width = 8;
1066
f4983704
SG		 1067 priv->hash_regs[0] = &regs->gaddr0;
1068 priv->hash_regs[1] = &regs->gaddr1;
1069 priv->hash_regs[2] = &regs->gaddr2;
1070 priv->hash_regs[3] = &regs->gaddr3;
1071 priv->hash_regs[4] = &regs->gaddr4;
1072 priv->hash_regs[5] = &regs->gaddr5;
1073 priv->hash_regs[6] = &regs->gaddr6;
1074 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 1075 }
1076
b31a1d8b 1077 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 1078 priv->padding = DEFAULT_PADDING;
1079 else
1080 priv->padding = 0;
1081
cc772ab7
MR		 1082 if (dev->features & NETIF_F_IP_CSUM ||
1083 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
0bbaf069 1084 dev->hard_header_len += GMAC_FCB_LEN;
1da177e4 1085
46ceb60c
SG		 1086 /* Program the isrg regs only if number of grps > 1 */
1087 if (priv->num_grps > 1) {
1088 baddr = &regs->isrg0;
1089 for (i = 0; i < priv->num_grps; i++) {
1090 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1091 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1092 gfar_write(baddr, isrg);
1093 baddr++;
1094 isrg = 0x0;
1095 }
1096 }
1097
fba4ed03 1098 /* Need to reverse the bit maps as bit_map's MSB is q0
984b3f57 1099 * but, for_each_set_bit parses from right to left, which
fba4ed03 1100 * basically reverses the queue numbers */
46ceb60c
SG		 1101 for (i = 0; i< priv->num_grps; i++) {
1102 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1103 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1104 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1105 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1106 }
1107
1108 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1109 * also assign queues to groups */
1110 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1111 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
984b3f57 1112 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
46ceb60c
SG		 1113 priv->num_rx_queues) {
1114 priv->gfargrp[grp_idx].num_rx_queues++;
1115 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1116 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1117 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1118 }
1119 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
984b3f57 1120 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
46ceb60c
SG		 1121 priv->num_tx_queues) {
1122 priv->gfargrp[grp_idx].num_tx_queues++;
1123 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1124 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1125 tqueue = tqueue | (TQUEUE_EN0 >> i);
1126 }
1127 priv->gfargrp[grp_idx].rstat = rstat;
1128 priv->gfargrp[grp_idx].tstat = tstat;
1129 rstat = tstat =0;
fba4ed03 1130 }
fba4ed03
SG		 1131
1132 gfar_write(&regs->rqueue, rqueue);
1133 gfar_write(&regs->tqueue, tqueue);
1134
1da177e4 1135 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1136
a12f801d 1137 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1138 for (i = 0; i < priv->num_tx_queues; i++) {
1139 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1140 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1141 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1142 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1143 }
a12f801d 1144
fba4ed03
SG		 1145 for (i = 0; i < priv->num_rx_queues; i++) {
1146 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1147 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1148 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1149 }
1da177e4 1150
1ccb8389
SG		 1151 /* enable filer if using multiple RX queues*/
1152 if(priv->num_rx_queues > 1)
1153 priv->rx_filer_enable = 1;
0bbaf069
KG		 1154 /* Enable most messages by default */
1155 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1156
d3eab82b
TP		 1157 /* Carrier starts down, phylib will bring it up */
1158 netif_carrier_off(dev);
1159
1da177e4
LT		 1160 err = register_netdev(dev);
1161
1162 if (err) {
1163 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1164 dev->name);
1165 goto register_fail;
1166 }
1167
2884e5cc
AV		 1168 device_init_wakeup(&dev->dev,
1169 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1170
c50a5d9a
DH		 1171 /* fill out IRQ number and name fields */
1172 len_devname = strlen(dev->name);
46ceb60c
SG		 1173 for (i = 0; i < priv->num_grps; i++) {
1174 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1175 len_devname);
1176 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1177 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1178 "_g", sizeof("_g"));
1179 priv->gfargrp[i].int_name_tx[
1180 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1181 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1182 priv->gfargrp[i].int_name_tx)],
1183 "_tx", sizeof("_tx") + 1);
1184
1185 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1186 len_devname);
1187 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1188 "_g", sizeof("_g"));
1189 priv->gfargrp[i].int_name_rx[
1190 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1191 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1192 priv->gfargrp[i].int_name_rx)],
1193 "_rx", sizeof("_rx") + 1);
1194
1195 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1196 len_devname);
1197 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1198 "_g", sizeof("_g"));
1199 priv->gfargrp[i].int_name_er[strlen(
1200 priv->gfargrp[i].int_name_er)] = i+48;
1201 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1202 priv->gfargrp[i].int_name_er)],
1203 "_er", sizeof("_er") + 1);
1204 } else
1205 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1206 }
c50a5d9a 1207
7a8b3372
SG		 1208 /* Initialize the filer table */
1209 gfar_init_filer_table(priv);
1210
7f7f5316
AF		 1211 /* Create all the sysfs files */
1212 gfar_init_sysfs(dev);
1213
1da177e4 1214 /* Print out the device info */
e174961c 1215 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1da177e4
LT		 1216
1217 /* Even more device info helps when determining which kernel */
7f7f5316 1218 /* provided which set of benchmarks. */
1da177e4 1219 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
fba4ed03 1220 for (i = 0; i < priv->num_rx_queues; i++)
ddc01b3b 1221 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
fba4ed03
SG		 1222 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1223 for(i = 0; i < priv->num_tx_queues; i++)
ddc01b3b 1224 printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
fba4ed03 1225 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1226
1227 return 0;
1228
1229register_fail:
46ceb60c 1230 unmap_group_regs(priv);
fba4ed03
SG		 1231 free_tx_pointers(priv);
1232 free_rx_pointers(priv);
fe192a49
GL		 1233 if (priv->phy_node)
1234 of_node_put(priv->phy_node);
1235 if (priv->tbi_node)
1236 of_node_put(priv->tbi_node);
1da177e4 1237 free_netdev(dev);
bb40dcbb 1238 return err;
1da177e4
LT		 1239}
1240
2dc11581 1241static int gfar_remove(struct platform_device *ofdev)
1da177e4 1242{
b31a1d8b 1243 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 1244
fe192a49
GL		 1245 if (priv->phy_node)
1246 of_node_put(priv->phy_node);
1247 if (priv->tbi_node)
1248 of_node_put(priv->tbi_node);
1249
b31a1d8b 1250 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 1251
d9d8e041 1252 unregister_netdev(priv->ndev);
46ceb60c 1253 unmap_group_regs(priv);
4826857f 1254 free_netdev(priv->ndev);
1da177e4
LT		 1255
1256 return 0;
1257}
1258
d87eb127 1259#ifdef CONFIG_PM
be926fc4
AV		 1260
1261static int gfar_suspend(struct device *dev)
d87eb127 1262{
be926fc4
AV		 1263 struct gfar_private *priv = dev_get_drvdata(dev);
1264 struct net_device *ndev = priv->ndev;
46ceb60c 1265 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1266 unsigned long flags;
1267 u32 tempval;
1268
1269 int magic_packet = priv->wol_en &&
b31a1d8b 1270 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1271
be926fc4 1272 netif_device_detach(ndev);
d87eb127 1273
be926fc4 1274 if (netif_running(ndev)) {
fba4ed03
SG		 1275
1276 local_irq_save(flags);
1277 lock_tx_qs(priv);
1278 lock_rx_qs(priv);
d87eb127 1279
be926fc4 1280 gfar_halt_nodisable(ndev);
d87eb127
SW		 1281
1282 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1283 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1284
1285 tempval &= ~MACCFG1_TX_EN;
1286
1287 if (!magic_packet)
1288 tempval &= ~MACCFG1_RX_EN;
1289
f4983704 1290 gfar_write(&regs->maccfg1, tempval);
d87eb127 1291
fba4ed03
SG		 1292 unlock_rx_qs(priv);
1293 unlock_tx_qs(priv);
1294 local_irq_restore(flags);
d87eb127 1295
46ceb60c 1296 disable_napi(priv);
d87eb127
SW		 1297
1298 if (magic_packet) {
1299 /* Enable interrupt on Magic Packet */
f4983704 1300 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1301
1302 /* Enable Magic Packet mode */
f4983704 1303 tempval = gfar_read(&regs->maccfg2);
d87eb127 1304 tempval |= MACCFG2_MPEN;
f4983704 1305 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1306 } else {
1307 phy_stop(priv->phydev);
1308 }
1309 }
1310
1311 return 0;
1312}
1313
be926fc4 1314static int gfar_resume(struct device *dev)
d87eb127 1315{
be926fc4
AV		 1316 struct gfar_private *priv = dev_get_drvdata(dev);
1317 struct net_device *ndev = priv->ndev;
46ceb60c 1318 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1319 unsigned long flags;
1320 u32 tempval;
1321 int magic_packet = priv->wol_en &&
b31a1d8b 1322 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1323
be926fc4
AV		 1324 if (!netif_running(ndev)) {
1325 netif_device_attach(ndev);
d87eb127
SW		 1326 return 0;
1327 }
1328
1329 if (!magic_packet && priv->phydev)
1330 phy_start(priv->phydev);
1331
1332 /* Disable Magic Packet mode, in case something
1333 * else woke us up.
1334 */
fba4ed03
SG		 1335 local_irq_save(flags);
1336 lock_tx_qs(priv);
1337 lock_rx_qs(priv);
d87eb127 1338
f4983704 1339 tempval = gfar_read(&regs->maccfg2);
d87eb127 1340 tempval &= ~MACCFG2_MPEN;
f4983704 1341 gfar_write(&regs->maccfg2, tempval);
d87eb127 1342
be926fc4 1343 gfar_start(ndev);
d87eb127 1344
fba4ed03
SG		 1345 unlock_rx_qs(priv);
1346 unlock_tx_qs(priv);
1347 local_irq_restore(flags);
d87eb127 1348
be926fc4
AV		 1349 netif_device_attach(ndev);
1350
46ceb60c 1351 enable_napi(priv);
be926fc4
AV		 1352
1353 return 0;
1354}
1355
1356static int gfar_restore(struct device *dev)
1357{
1358 struct gfar_private *priv = dev_get_drvdata(dev);
1359 struct net_device *ndev = priv->ndev;
1360
1361 if (!netif_running(ndev))
1362 return 0;
1363
1364 gfar_init_bds(ndev);
1365 init_registers(ndev);
1366 gfar_set_mac_address(ndev);
1367 gfar_init_mac(ndev);
1368 gfar_start(ndev);
1369
1370 priv->oldlink = 0;
1371 priv->oldspeed = 0;
1372 priv->oldduplex = -1;
1373
1374 if (priv->phydev)
1375 phy_start(priv->phydev);
d87eb127 1376
be926fc4 1377 netif_device_attach(ndev);
5ea681d4 1378 enable_napi(priv);
d87eb127
SW		 1379
1380 return 0;
1381}
be926fc4
AV		 1382
1383static struct dev_pm_ops gfar_pm_ops = {
1384 .suspend = gfar_suspend,
1385 .resume = gfar_resume,
1386 .freeze = gfar_suspend,
1387 .thaw = gfar_resume,
1388 .restore = gfar_restore,
1389};
1390
1391#define GFAR_PM_OPS (&gfar_pm_ops)
1392
d87eb127 1393#else
be926fc4
AV		 1394
1395#define GFAR_PM_OPS NULL
be926fc4 1396
d87eb127 1397#endif
1da177e4 1398
e8a2b6a4
AF		 1399/* Reads the controller's registers to determine what interface
1400 * connects it to the PHY.
1401 */
1402static phy_interface_t gfar_get_interface(struct net_device *dev)
1403{
1404 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1405 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1406 u32 ecntrl;
1407
f4983704 1408 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1409
1410 if (ecntrl & ECNTRL_SGMII_MODE)
1411 return PHY_INTERFACE_MODE_SGMII;
1412
1413 if (ecntrl & ECNTRL_TBI_MODE) {
1414 if (ecntrl & ECNTRL_REDUCED_MODE)
1415 return PHY_INTERFACE_MODE_RTBI;
1416 else
1417 return PHY_INTERFACE_MODE_TBI;
1418 }
1419
1420 if (ecntrl & ECNTRL_REDUCED_MODE) {
1421 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1422 return PHY_INTERFACE_MODE_RMII;
7132ab7f 1423 else {
b31a1d8b 1424 phy_interface_t interface = priv->interface;
7132ab7f
AF		 1425
1426 /*
1427 * This isn't autodetected right now, so it must
1428 * be set by the device tree or platform code.
1429 */
1430 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1431 return PHY_INTERFACE_MODE_RGMII_ID;
1432
e8a2b6a4 1433 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1434 }
e8a2b6a4
AF		 1435 }
1436
b31a1d8b 1437 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1438 return PHY_INTERFACE_MODE_GMII;
1439
1440 return PHY_INTERFACE_MODE_MII;
1441}
1442
1443
bb40dcbb
AF		 1444/* Initializes driver's PHY state, and attaches to the PHY.
1445 * Returns 0 on success.
1da177e4
LT		 1446 */
1447static int init_phy(struct net_device *dev)
1448{
1449 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1450 uint gigabit_support =
b31a1d8b 1451 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1452 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1453 phy_interface_t interface;
1da177e4
LT		 1454
1455 priv->oldlink = 0;
1456 priv->oldspeed = 0;
1457 priv->oldduplex = -1;
1458
e8a2b6a4
AF		 1459 interface = gfar_get_interface(dev);
1460
1db780f8
AV		 1461 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1462 interface);
1463 if (!priv->phydev)
1464 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1465 interface);
1466 if (!priv->phydev) {
1467 dev_err(&dev->dev, "could not attach to PHY\n");
1468 return -ENODEV;
fe192a49 1469 }
1da177e4 1470
d3c12873
KJ		 1471 if (interface == PHY_INTERFACE_MODE_SGMII)
1472 gfar_configure_serdes(dev);
1473
bb40dcbb 1474 /* Remove any features not supported by the controller */
fe192a49
GL		 1475 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1476 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1477
1478 return 0;
1da177e4
LT		 1479}
1480
d0313587
PG		 1481/*
1482 * Initialize TBI PHY interface for communicating with the
1483 * SERDES lynx PHY on the chip. We communicate with this PHY
1484 * through the MDIO bus on each controller, treating it as a
1485 * "normal" PHY at the address found in the TBIPA register. We assume
1486 * that the TBIPA register is valid. Either the MDIO bus code will set
1487 * it to a value that doesn't conflict with other PHYs on the bus, or the
1488 * value doesn't matter, as there are no other PHYs on the bus.
1489 */
d3c12873
KJ		 1490static void gfar_configure_serdes(struct net_device *dev)
1491{
1492 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1493 struct phy_device *tbiphy;
1494
1495 if (!priv->tbi_node) {
1496 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1497 "device tree specify a tbi-handle\n");
1498 return;
1499 }
c132419e 1500
fe192a49
GL		 1501 tbiphy = of_phy_find_device(priv->tbi_node);
1502 if (!tbiphy) {
1503 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1504 return;
1505 }
d3c12873 1506
b31a1d8b
AF		 1507 /*
1508 * If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1509 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1510 * everything for us? Resetting it takes the link down and requires
1511 * several seconds for it to come back.
1512 */
fe192a49 1513 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1514 return;
d3c12873 1515
d0313587 1516 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1517 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1518
fe192a49 1519 phy_write(tbiphy, MII_ADVERTISE,
d3c12873
KJ		 1520 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1521 ADVERTISE_1000XPSE_ASYM);
1522
fe192a49 1523 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
d3c12873
KJ		 1524 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1525}
1526
1da177e4
LT		 1527static void init_registers(struct net_device *dev)
1528{
1529 struct gfar_private *priv = netdev_priv(dev);
f4983704 1530 struct gfar __iomem *regs = NULL;
46ceb60c 1531 int i = 0;
1da177e4 1532
46ceb60c
SG		 1533 for (i = 0; i < priv->num_grps; i++) {
1534 regs = priv->gfargrp[i].regs;
1535 /* Clear IEVENT */
1536 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1537
46ceb60c
SG		 1538 /* Initialize IMASK */
1539 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1540 }
1da177e4 1541
46ceb60c 1542 regs = priv->gfargrp[0].regs;
1da177e4 1543 /* Init hash registers to zero */
f4983704
SG		 1544 gfar_write(&regs->igaddr0, 0);
1545 gfar_write(&regs->igaddr1, 0);
1546 gfar_write(&regs->igaddr2, 0);
1547 gfar_write(&regs->igaddr3, 0);
1548 gfar_write(&regs->igaddr4, 0);
1549 gfar_write(&regs->igaddr5, 0);
1550 gfar_write(&regs->igaddr6, 0);
1551 gfar_write(&regs->igaddr7, 0);
1552
1553 gfar_write(&regs->gaddr0, 0);
1554 gfar_write(&regs->gaddr1, 0);
1555 gfar_write(&regs->gaddr2, 0);
1556 gfar_write(&regs->gaddr3, 0);
1557 gfar_write(&regs->gaddr4, 0);
1558 gfar_write(&regs->gaddr5, 0);
1559 gfar_write(&regs->gaddr6, 0);
1560 gfar_write(&regs->gaddr7, 0);
1da177e4 1561
1da177e4 1562 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1563 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1564 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1565
1566 /* Mask off the CAM interrupts */
f4983704
SG		 1567 gfar_write(&regs->rmon.cam1, 0xffffffff);
1568 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1569 }
1570
1571 /* Initialize the max receive buffer length */
f4983704 1572 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1573
1da177e4 1574 /* Initialize the Minimum Frame Length Register */
f4983704 1575 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1576}
1577
511d934f
AV		 1578static int __gfar_is_rx_idle(struct gfar_private *priv)
1579{
1580 u32 res;
1581
1582 /*
1583 * Normaly TSEC should not hang on GRS commands, so we should
1584 * actually wait for IEVENT_GRSC flag.
1585 */
1586 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1587 return 0;
1588
1589 /*
1590 * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1591 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1592 * and the Rx can be safely reset.
1593 */
1594 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1595 res &= 0x7f807f80;
1596 if ((res & 0xffff) == (res >> 16))
1597 return 1;
1598
1599 return 0;
1600}
0bbaf069
KG		 1601
1602/* Halt the receive and transmit queues */
d87eb127 1603static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1604{
1605 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1606 struct gfar __iomem *regs = NULL;
1da177e4 1607 u32 tempval;
46ceb60c 1608 int i = 0;
1da177e4 1609
46ceb60c
SG		 1610 for (i = 0; i < priv->num_grps; i++) {
1611 regs = priv->gfargrp[i].regs;
1612 /* Mask all interrupts */
1613 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1614
46ceb60c
SG		 1615 /* Clear all interrupts */
1616 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1617 }
1da177e4 1618
46ceb60c 1619 regs = priv->gfargrp[0].regs;
1da177e4 1620 /* Stop the DMA, and wait for it to stop */
f4983704 1621 tempval = gfar_read(&regs->dmactrl);
1da177e4
LT		 1622 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1623 != (DMACTRL_GRS | DMACTRL_GTS)) {
511d934f
AV		 1624 int ret;
1625
1da177e4 1626 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1627 gfar_write(&regs->dmactrl, tempval);
1da177e4 1628
511d934f
AV		 1629 do {
1630 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1631 (IEVENT_GRSC | IEVENT_GTSC)) ==
1632 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1633 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1634 ret = __gfar_is_rx_idle(priv);
1635 } while (!ret);
1da177e4 1636 }
d87eb127 1637}
d87eb127
SW		 1638
1639/* Halt the receive and transmit queues */
1640void gfar_halt(struct net_device *dev)
1641{
1642 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1643 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1644 u32 tempval;
1da177e4 1645
2a54adc3
SW		 1646 gfar_halt_nodisable(dev);
1647
1da177e4
LT		 1648 /* Disable Rx and Tx */
1649 tempval = gfar_read(&regs->maccfg1);
1650 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1651 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1652}
1653
46ceb60c
SG		 1654static void free_grp_irqs(struct gfar_priv_grp *grp)
1655{
1656 free_irq(grp->interruptError, grp);
1657 free_irq(grp->interruptTransmit, grp);
1658 free_irq(grp->interruptReceive, grp);
1659}
1660
0bbaf069
KG		 1661void stop_gfar(struct net_device *dev)
1662{
1663 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1664 unsigned long flags;
46ceb60c 1665 int i;
0bbaf069 1666
bb40dcbb
AF		 1667 phy_stop(priv->phydev);
1668
a12f801d 1669
0bbaf069 1670 /* Lock it down */
fba4ed03
SG		 1671 local_irq_save(flags);
1672 lock_tx_qs(priv);
1673 lock_rx_qs(priv);
0bbaf069 1674
0bbaf069 1675 gfar_halt(dev);
1da177e4 1676
fba4ed03
SG		 1677 unlock_rx_qs(priv);
1678 unlock_tx_qs(priv);
1679 local_irq_restore(flags);
1da177e4
LT		 1680
1681 /* Free the IRQs */
b31a1d8b 1682 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1683 for (i = 0; i < priv->num_grps; i++)
1684 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1685 } else {
46ceb60c
SG		 1686 for (i = 0; i < priv->num_grps; i++)
1687 free_irq(priv->gfargrp[i].interruptTransmit,
1688 &priv->gfargrp[i]);
1da177e4
LT		 1689 }
1690
1691 free_skb_resources(priv);
1da177e4
LT		 1692}
1693
fba4ed03 1694static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1695{
1da177e4 1696 struct txbd8 *txbdp;
fba4ed03 1697 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1698 int i, j;
1da177e4 1699
a12f801d 1700 txbdp = tx_queue->tx_bd_base;
1da177e4 1701
a12f801d
SG		 1702 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1703 if (!tx_queue->tx_skbuff[i])
4669bc90 1704 continue;
1da177e4 1705
4826857f 1706 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90
DH		 1707 txbdp->length, DMA_TO_DEVICE);
1708 txbdp->lstatus = 0;
fba4ed03
SG		 1709 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1710 j++) {
4669bc90 1711 txbdp++;
4826857f 1712 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90 1713 txbdp->length, DMA_TO_DEVICE);
1da177e4 1714 }
ad5da7ab 1715 txbdp++;
a12f801d
SG		 1716 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1717 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1718 }
a12f801d 1719 kfree(tx_queue->tx_skbuff);
fba4ed03 1720}
1da177e4 1721
fba4ed03
SG		 1722static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1723{
1724 struct rxbd8 *rxbdp;
1725 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1726 int i;
1da177e4 1727
fba4ed03 1728 rxbdp = rx_queue->rx_bd_base;
1da177e4 1729
a12f801d
SG		 1730 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1731 if (rx_queue->rx_skbuff[i]) {
fba4ed03
SG		 1732 dma_unmap_single(&priv->ofdev->dev,
1733 rxbdp->bufPtr, priv->rx_buffer_size,
e69edd21 1734 DMA_FROM_DEVICE);
a12f801d
SG		 1735 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1736 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1737 }
e69edd21
AV		 1738 rxbdp->lstatus = 0;
1739 rxbdp->bufPtr = 0;
1740 rxbdp++;
1da177e4 1741 }
a12f801d 1742 kfree(rx_queue->rx_skbuff);
fba4ed03 1743}
e69edd21 1744
fba4ed03
SG		 1745/* If there are any tx skbs or rx skbs still around, free them.
1746 * Then free tx_skbuff and rx_skbuff */
1747static void free_skb_resources(struct gfar_private *priv)
1748{
1749 struct gfar_priv_tx_q *tx_queue = NULL;
1750 struct gfar_priv_rx_q *rx_queue = NULL;
1751 int i;
1752
1753 /* Go through all the buffer descriptors and free their data buffers */
1754 for (i = 0; i < priv->num_tx_queues; i++) {
1755 tx_queue = priv->tx_queue[i];
7c0d10d3 1756 if(tx_queue->tx_skbuff)
fba4ed03
SG		 1757 free_skb_tx_queue(tx_queue);
1758 }
1759
1760 for (i = 0; i < priv->num_rx_queues; i++) {
1761 rx_queue = priv->rx_queue[i];
7c0d10d3 1762 if(rx_queue->rx_skbuff)
fba4ed03
SG		 1763 free_skb_rx_queue(rx_queue);
1764 }
1765
1766 dma_free_coherent(&priv->ofdev->dev,
1767 sizeof(struct txbd8) * priv->total_tx_ring_size +
1768 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1769 priv->tx_queue[0]->tx_bd_base,
1770 priv->tx_queue[0]->tx_bd_dma_base);
7df9c43f 1771 skb_queue_purge(&priv->rx_recycle);
1da177e4
LT		 1772}
1773
0bbaf069
KG		 1774void gfar_start(struct net_device *dev)
1775{
1776 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1777 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1778 u32 tempval;
46ceb60c 1779 int i = 0;
0bbaf069
KG		 1780
1781 /* Enable Rx and Tx in MACCFG1 */
1782 tempval = gfar_read(&regs->maccfg1);
1783 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1784 gfar_write(&regs->maccfg1, tempval);
1785
1786 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1787 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1788 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1789 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1790
0bbaf069 1791 /* Make sure we aren't stopped */
f4983704 1792 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1793 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1794 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1795
46ceb60c
SG		 1796 for (i = 0; i < priv->num_grps; i++) {
1797 regs = priv->gfargrp[i].regs;
1798 /* Clear THLT/RHLT, so that the DMA starts polling now */
1799 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1800 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1801 /* Unmask the interrupts we look for */
1802 gfar_write(&regs->imask, IMASK_DEFAULT);
1803 }
12dea57b 1804
1ae5dc34 1805 dev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1806}
1807
46ceb60c 1808void gfar_configure_coalescing(struct gfar_private *priv,
18294ad1 1809 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1810{
46ceb60c 1811 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1812 u32 __iomem *baddr;
46ceb60c 1813 int i = 0;
1da177e4 1814
46ceb60c
SG		 1815 /* Backward compatible case ---- even if we enable
1816 * multiple queues, there's only single reg to program
1817 */
1818 gfar_write(&regs->txic, 0);
1819 if(likely(priv->tx_queue[0]->txcoalescing))
1820 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1da177e4 1821
46ceb60c
SG		 1822 gfar_write(&regs->rxic, 0);
1823 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1824 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
815b97c6 1825
46ceb60c
SG		 1826 if (priv->mode == MQ_MG_MODE) {
1827 baddr = &regs->txic0;
984b3f57 1828 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
46ceb60c
SG		 1829 if (likely(priv->tx_queue[i]->txcoalescing)) {
1830 gfar_write(baddr + i, 0);
1831 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1832 }
1833 }
1834
1835 baddr = &regs->rxic0;
984b3f57 1836 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
46ceb60c
SG		 1837 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1838 gfar_write(baddr + i, 0);
1839 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1840 }
1841 }
1842 }
1843}
1844
1845static int register_grp_irqs(struct gfar_priv_grp *grp)
1846{
1847 struct gfar_private *priv = grp->priv;
1848 struct net_device *dev = priv->ndev;
1849 int err;
1da177e4 1850
1da177e4
LT		 1851 /* If the device has multiple interrupts, register for
1852 * them. Otherwise, only register for the one */
b31a1d8b 1853 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1854 /* Install our interrupt handlers for Error,
1da177e4 1855 * Transmit, and Receive */
46ceb60c
SG		 1856 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1857 grp->int_name_er,grp)) < 0) {
0bbaf069 1858 if (netif_msg_intr(priv))
46ceb60c
SG		 1859 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1860 dev->name, grp->interruptError);
1861
2145f1af 1862 goto err_irq_fail;
1da177e4
LT		 1863 }
1864
46ceb60c
SG		 1865 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1866 0, grp->int_name_tx, grp)) < 0) {
0bbaf069 1867 if (netif_msg_intr(priv))
46ceb60c
SG		 1868 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1869 dev->name, grp->interruptTransmit);
1da177e4
LT		 1870 goto tx_irq_fail;
1871 }
1872
46ceb60c
SG		 1873 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1874 grp->int_name_rx, grp)) < 0) {
0bbaf069 1875 if (netif_msg_intr(priv))
46ceb60c
SG		 1876 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1877 dev->name, grp->interruptReceive);
1da177e4
LT		 1878 goto rx_irq_fail;
1879 }
1880 } else {
46ceb60c
SG		 1881 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1882 grp->int_name_tx, grp)) < 0) {
0bbaf069 1883 if (netif_msg_intr(priv))
46ceb60c
SG		 1884 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1885 dev->name, grp->interruptTransmit);
1da177e4
LT		 1886 goto err_irq_fail;
1887 }
1888 }
1889
46ceb60c
SG		 1890 return 0;
1891
1892rx_irq_fail:
1893 free_irq(grp->interruptTransmit, grp);
1894tx_irq_fail:
1895 free_irq(grp->interruptError, grp);
1896err_irq_fail:
1897 return err;
1898
1899}
1900
1901/* Bring the controller up and running */
1902int startup_gfar(struct net_device *ndev)
1903{
1904 struct gfar_private *priv = netdev_priv(ndev);
1905 struct gfar __iomem *regs = NULL;
1906 int err, i, j;
1907
1908 for (i = 0; i < priv->num_grps; i++) {
1909 regs= priv->gfargrp[i].regs;
1910 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1911 }
1912
1913 regs= priv->gfargrp[0].regs;
1914 err = gfar_alloc_skb_resources(ndev);
1915 if (err)
1916 return err;
1917
1918 gfar_init_mac(ndev);
1919
1920 for (i = 0; i < priv->num_grps; i++) {
1921 err = register_grp_irqs(&priv->gfargrp[i]);
1922 if (err) {
1923 for (j = 0; j < i; j++)
1924 free_grp_irqs(&priv->gfargrp[j]);
1925 goto irq_fail;
1926 }
1927 }
1928
7f7f5316 1929 /* Start the controller */
ccc05c6e 1930 gfar_start(ndev);
1da177e4 1931
826aa4a0
AV		 1932 phy_start(priv->phydev);
1933
46ceb60c
SG		 1934 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1935
1da177e4
LT		 1936 return 0;
1937
46ceb60c 1938irq_fail:
e69edd21 1939 free_skb_resources(priv);
1da177e4
LT		 1940 return err;
1941}
1942
1943/* Called when something needs to use the ethernet device */
1944/* Returns 0 for success. */
1945static int gfar_enet_open(struct net_device *dev)
1946{
94e8cc35 1947 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1948 int err;
1949
46ceb60c 1950 enable_napi(priv);
bea3348e 1951
0fd56bb5
AF		 1952 skb_queue_head_init(&priv->rx_recycle);
1953
1da177e4
LT		 1954 /* Initialize a bunch of registers */
1955 init_registers(dev);
1956
1957 gfar_set_mac_address(dev);
1958
1959 err = init_phy(dev);
1960
a12f801d 1961 if (err) {
46ceb60c 1962 disable_napi(priv);
1da177e4 1963 return err;
bea3348e 1964 }
1da177e4
LT		 1965
1966 err = startup_gfar(dev);
db0e8e3f 1967 if (err) {
46ceb60c 1968 disable_napi(priv);
db0e8e3f
AV		 1969 return err;
1970 }
1da177e4 1971
fba4ed03 1972 netif_tx_start_all_queues(dev);
1da177e4 1973
2884e5cc
AV		 1974 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1975
1da177e4
LT		 1976 return err;
1977}
1978
54dc79fe 1979static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1980{
54dc79fe 1981 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1982
1983 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1984
0bbaf069
KG		 1985 return fcb;
1986}
1987
1988static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1989{
7f7f5316 1990 u8 flags = 0;
0bbaf069
KG		 1991
1992 /* If we're here, it's a IP packet with a TCP or UDP
1993 * payload. We set it to checksum, using a pseudo-header
1994 * we provide
1995 */
7f7f5316 1996 flags = TXFCB_DEFAULT;
0bbaf069 1997
7f7f5316
AF		 1998 /* Tell the controller what the protocol is */
1999 /* And provide the already calculated phcs */
eddc9ec5 2000 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 2001 flags |= TXFCB_UDP;
4bedb452 2002 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 2003 } else
8da32de5 2004 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 2005
2006 /* l3os is the distance between the start of the
2007 * frame (skb->data) and the start of the IP hdr.
2008 * l4os is the distance between the start of the
2009 * l3 hdr and the l4 hdr */
bbe735e4 2010 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
cfe1fc77 2011 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2012
7f7f5316 2013 fcb->flags = flags;
0bbaf069
KG		 2014}
2015
7f7f5316 2016void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2017{
7f7f5316 2018 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 2019 fcb->vlctl = vlan_tx_tag_get(skb);
2020}
2021
4669bc90
DH		 2022static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2023 struct txbd8 *base, int ring_size)
2024{
2025 struct txbd8 *new_bd = bdp + stride;
2026
2027 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2028}
2029
2030static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2031 int ring_size)
2032{
2033 return skip_txbd(bdp, 1, base, ring_size);
2034}
2035
1da177e4
LT		 2036/* This is called by the kernel when a frame is ready for transmission. */
2037/* It is pointed to by the dev->hard_start_xmit function pointer */
2038static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2039{
2040 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2041 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2042 struct netdev_queue *txq;
f4983704 2043 struct gfar __iomem *regs = NULL;
0bbaf069 2044 struct txfcb *fcb = NULL;
f0ee7acf 2045 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2046 u32 lstatus;
f0ee7acf 2047 int i, rq = 0, do_tstamp = 0;
4669bc90 2048 u32 bufaddr;
fef6108d 2049 unsigned long flags;
f0ee7acf 2050 unsigned int nr_frags, nr_txbds, length;
fba4ed03 2051
deb90eac
AV		 2052 /*
2053 * TOE=1 frames larger than 2500 bytes may see excess delays
2054 * before start of transmission.
2055 */
2056 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2057 skb->ip_summed == CHECKSUM_PARTIAL &&
2058 skb->len > 2500)) {
2059 int ret;
2060
2061 ret = skb_checksum_help(skb);
2062 if (ret)
2063 return ret;
2064 }
2065
fba4ed03
SG		 2066 rq = skb->queue_mapping;
2067 tx_queue = priv->tx_queue[rq];
2068 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2069 base = tx_queue->tx_bd_base;
46ceb60c 2070 regs = tx_queue->grp->regs;
f0ee7acf
MR		 2071
2072 /* check if time stamp should be generated */
2244d07b
OH		 2073 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2074 priv->hwts_tx_en))
f0ee7acf 2075 do_tstamp = 1;
4669bc90 2076
5b28beaf
LY		 2077 /* make space for additional header when fcb is needed */
2078 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
f0ee7acf
MR		 2079 (priv->vlgrp && vlan_tx_tag_present(skb)) ||
2080 unlikely(do_tstamp)) &&
5b28beaf 2081 (skb_headroom(skb) < GMAC_FCB_LEN)) {
54dc79fe
SH		 2082 struct sk_buff *skb_new;
2083
2084 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2085 if (!skb_new) {
2086 dev->stats.tx_errors++;
bd14ba84 2087 kfree_skb(skb);
54dc79fe
SH		 2088 return NETDEV_TX_OK;
2089 }
2090 kfree_skb(skb);
2091 skb = skb_new;
2092 }
2093
4669bc90
DH		 2094 /* total number of fragments in the SKB */
2095 nr_frags = skb_shinfo(skb)->nr_frags;
2096
f0ee7acf
MR		 2097 /* calculate the required number of TxBDs for this skb */
2098 if (unlikely(do_tstamp))
2099 nr_txbds = nr_frags + 2;
2100 else
2101 nr_txbds = nr_frags + 1;
2102
4669bc90 2103 /* check if there is space to queue this packet */
f0ee7acf 2104 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2105 /* no space, stop the queue */
fba4ed03 2106 netif_tx_stop_queue(txq);
4669bc90 2107 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2108 return NETDEV_TX_BUSY;
2109 }
1da177e4
LT		 2110
2111 /* Update transmit stats */
a7f38041
SG		 2112 txq->tx_bytes += skb->len;
2113 txq->tx_packets ++;
1da177e4 2114
a12f801d 2115 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2116 lstatus = txbdp->lstatus;
2117
2118 /* Time stamp insertion requires one additional TxBD */
2119 if (unlikely(do_tstamp))
2120 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2121 tx_queue->tx_ring_size);
1da177e4 2122
4669bc90 2123 if (nr_frags == 0) {
f0ee7acf
MR		 2124 if (unlikely(do_tstamp))
2125 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2126 TXBD_INTERRUPT);
2127 else
2128 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2129 } else {
2130 /* Place the fragment addresses and lengths into the TxBDs */
2131 for (i = 0; i < nr_frags; i++) {
2132 /* Point at the next BD, wrapping as needed */
a12f801d 2133 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2134
2135 length = skb_shinfo(skb)->frags[i].size;
2136
2137 lstatus = txbdp->lstatus | length |
2138 BD_LFLAG(TXBD_READY);
2139
2140 /* Handle the last BD specially */
2141 if (i == nr_frags - 1)
2142 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2143
4826857f 2144 bufaddr = dma_map_page(&priv->ofdev->dev,
4669bc90
DH		 2145 skb_shinfo(skb)->frags[i].page,
2146 skb_shinfo(skb)->frags[i].page_offset,
2147 length,
2148 DMA_TO_DEVICE);
2149
2150 /* set the TxBD length and buffer pointer */
2151 txbdp->bufPtr = bufaddr;
2152 txbdp->lstatus = lstatus;
2153 }
2154
2155 lstatus = txbdp_start->lstatus;
2156 }
1da177e4 2157
0bbaf069 2158 /* Set up checksumming */
12dea57b 2159 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe
SH		 2160 fcb = gfar_add_fcb(skb);
2161 lstatus |= BD_LFLAG(TXBD_TOE);
2162 gfar_tx_checksum(skb, fcb);
0bbaf069
KG		 2163 }
2164
77ecaf2d 2165 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
54dc79fe
SH		 2166 if (unlikely(NULL == fcb)) {
2167 fcb = gfar_add_fcb(skb);
5a5efed4 2168 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 2169 }
54dc79fe
SH		 2170
2171 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 2172 }
2173
f0ee7acf
MR		 2174 /* Setup tx hardware time stamping if requested */
2175 if (unlikely(do_tstamp)) {
2244d07b 2176 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf
MR		 2177 if (fcb == NULL)
2178 fcb = gfar_add_fcb(skb);
2179 fcb->ptp = 1;
2180 lstatus |= BD_LFLAG(TXBD_TOE);
2181 }
2182
4826857f 2183 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
4669bc90 2184 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2185
f0ee7acf
MR		 2186 /*
2187 * If time stamping is requested one additional TxBD must be set up. The
2188 * first TxBD points to the FCB and must have a data length of
2189 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2190 * the full frame length.
2191 */
2192 if (unlikely(do_tstamp)) {
2193 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2194 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2195 (skb_headlen(skb) - GMAC_FCB_LEN);
2196 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2197 } else {
2198 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2199 }
1da177e4 2200
a3bc1f11
AV		 2201 /*
2202 * We can work in parallel with gfar_clean_tx_ring(), except
2203 * when modifying num_txbdfree. Note that we didn't grab the lock
2204 * when we were reading the num_txbdfree and checking for available
2205 * space, that's because outside of this function it can only grow,
2206 * and once we've got needed space, it cannot suddenly disappear.
2207 *
2208 * The lock also protects us from gfar_error(), which can modify
2209 * regs->tstat and thus retrigger the transfers, which is why we
2210 * also must grab the lock before setting ready bit for the first
2211 * to be transmitted BD.
2212 */
2213 spin_lock_irqsave(&tx_queue->txlock, flags);
2214
4669bc90
DH		 2215 /*
2216 * The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2217 * semantics (it requires synchronization between cacheable and
2218 * uncacheable mappings, which eieio doesn't provide and which we
2219 * don't need), thus requiring a more expensive sync instruction. At
2220 * some point, the set of architecture-independent barrier functions
2221 * should be expanded to include weaker barriers.
2222 */
3b6330ce 2223 eieio();
7f7f5316 2224
4669bc90
DH		 2225 txbdp_start->lstatus = lstatus;
2226
0eddba52
AV		 2227 eieio(); /* force lstatus write before tx_skbuff */
2228
2229 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2230
4669bc90
DH		 2231 /* Update the current skb pointer to the next entry we will use
2232 * (wrapping if necessary) */
a12f801d
SG		 2233 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2234 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2235
a12f801d 2236 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2237
2238 /* reduce TxBD free count */
f0ee7acf 2239 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2240
2241 /* If the next BD still needs to be cleaned up, then the bds
2242 are full. We need to tell the kernel to stop sending us stuff. */
a12f801d 2243 if (!tx_queue->num_txbdfree) {
fba4ed03 2244 netif_tx_stop_queue(txq);
1da177e4 2245
09f75cd7 2246 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2247 }
2248
1da177e4 2249 /* Tell the DMA to go go go */
fba4ed03 2250 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2251
2252 /* Unlock priv */
a12f801d 2253 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2254
54dc79fe 2255 return NETDEV_TX_OK;
1da177e4
LT		 2256}
2257
2258/* Stops the kernel queue, and halts the controller */
2259static int gfar_close(struct net_device *dev)
2260{
2261 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2262
46ceb60c 2263 disable_napi(priv);
bea3348e 2264
ab939905 2265 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2266 stop_gfar(dev);
2267
bb40dcbb
AF		 2268 /* Disconnect from the PHY */
2269 phy_disconnect(priv->phydev);
2270 priv->phydev = NULL;
1da177e4 2271
fba4ed03 2272 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2273
2274 return 0;
2275}
2276
1da177e4 2277/* Changes the mac address if the controller is not running. */
f162b9d5 2278static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2279{
7f7f5316 2280 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2281
2282 return 0;
2283}
2284
2285
0bbaf069
KG		 2286/* Enables and disables VLAN insertion/extraction */
2287static void gfar_vlan_rx_register(struct net_device *dev,
2288 struct vlan_group *grp)
2289{
2290 struct gfar_private *priv = netdev_priv(dev);
f4983704 2291 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2292 unsigned long flags;
2293 u32 tempval;
2294
46ceb60c 2295 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2296 local_irq_save(flags);
2297 lock_rx_qs(priv);
0bbaf069 2298
cd1f55a5 2299 priv->vlgrp = grp;
0bbaf069
KG		 2300
2301 if (grp) {
2302 /* Enable VLAN tag insertion */
f4983704 2303 tempval = gfar_read(&regs->tctrl);
0bbaf069
KG		 2304 tempval |= TCTRL_VLINS;
2305
f4983704 2306 gfar_write(&regs->tctrl, tempval);
6aa20a22 2307
0bbaf069 2308 /* Enable VLAN tag extraction */
f4983704 2309 tempval = gfar_read(&regs->rctrl);
77ecaf2d 2310 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
f4983704 2311 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2312 } else {
2313 /* Disable VLAN tag insertion */
f4983704 2314 tempval = gfar_read(&regs->tctrl);
0bbaf069 2315 tempval &= ~TCTRL_VLINS;
f4983704 2316 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2317
2318 /* Disable VLAN tag extraction */
f4983704 2319 tempval = gfar_read(&regs->rctrl);
0bbaf069 2320 tempval &= ~RCTRL_VLEX;
77ecaf2d
DH		 2321 /* If parse is no longer required, then disable parser */
2322 if (tempval & RCTRL_REQ_PARSER)
2323 tempval |= RCTRL_PRSDEP_INIT;
2324 else
2325 tempval &= ~RCTRL_PRSDEP_INIT;
f4983704 2326 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2327 }
2328
77ecaf2d
DH		 2329 gfar_change_mtu(dev, dev->mtu);
2330
fba4ed03
SG		 2331 unlock_rx_qs(priv);
2332 local_irq_restore(flags);
0bbaf069
KG		 2333}
2334
1da177e4
LT		 2335static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2336{
2337 int tempsize, tempval;
2338 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2339 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2340 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2341 int frame_size = new_mtu + ETH_HLEN;
2342
77ecaf2d 2343 if (priv->vlgrp)
faa89577 2344 frame_size += VLAN_HLEN;
0bbaf069 2345
1da177e4 2346 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
0bbaf069
KG		 2347 if (netif_msg_drv(priv))
2348 printk(KERN_ERR "%s: Invalid MTU setting\n",
2349 dev->name);
1da177e4
LT		 2350 return -EINVAL;
2351 }
2352
77ecaf2d
DH		 2353 if (gfar_uses_fcb(priv))
2354 frame_size += GMAC_FCB_LEN;
2355
2356 frame_size += priv->padding;
2357
1da177e4
LT		 2358 tempsize =
2359 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2360 INCREMENTAL_BUFFER_SIZE;
2361
2362 /* Only stop and start the controller if it isn't already
7f7f5316 2363 * stopped, and we changed something */
1da177e4
LT		 2364 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2365 stop_gfar(dev);
2366
2367 priv->rx_buffer_size = tempsize;
2368
2369 dev->mtu = new_mtu;
2370
f4983704
SG		 2371 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2372 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2373
2374 /* If the mtu is larger than the max size for standard
2375 * ethernet frames (ie, a jumbo frame), then set maccfg2
2376 * to allow huge frames, and to check the length */
f4983704 2377 tempval = gfar_read(&regs->maccfg2);
1da177e4 2378
7d350977
AV		 2379 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2380 gfar_has_errata(priv, GFAR_ERRATA_74))
1da177e4
LT		 2381 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2382 else
2383 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2384
f4983704 2385 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2386
2387 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2388 startup_gfar(dev);
2389
2390 return 0;
2391}
2392
ab939905 2393/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2394 * transmitted after a set amount of time.
2395 * For now, assume that clearing out all the structures, and
ab939905
SS		 2396 * starting over will fix the problem.
2397 */
2398static void gfar_reset_task(struct work_struct *work)
1da177e4 2399{
ab939905
SS		 2400 struct gfar_private *priv = container_of(work, struct gfar_private,
2401 reset_task);
4826857f 2402 struct net_device *dev = priv->ndev;
1da177e4
LT		 2403
2404 if (dev->flags & IFF_UP) {
fba4ed03 2405 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2406 stop_gfar(dev);
2407 startup_gfar(dev);
fba4ed03 2408 netif_tx_start_all_queues(dev);
1da177e4
LT		 2409 }
2410
263ba320 2411 netif_tx_schedule_all(dev);
1da177e4
LT		 2412}
2413
ab939905
SS		 2414static void gfar_timeout(struct net_device *dev)
2415{
2416 struct gfar_private *priv = netdev_priv(dev);
2417
2418 dev->stats.tx_errors++;
2419 schedule_work(&priv->reset_task);
2420}
2421
acbc0f03
EL		 2422static void gfar_align_skb(struct sk_buff *skb)
2423{
2424 /* We need the data buffer to be aligned properly. We will reserve
2425 * as many bytes as needed to align the data properly
2426 */
2427 skb_reserve(skb, RXBUF_ALIGNMENT -
2428 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2429}
2430
1da177e4 2431/* Interrupt Handler for Transmit complete */
a12f801d 2432static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2433{
a12f801d 2434 struct net_device *dev = tx_queue->dev;
d080cd63 2435 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2436 struct gfar_priv_rx_q *rx_queue = NULL;
f0ee7acf 2437 struct txbd8 *bdp, *next = NULL;
4669bc90 2438 struct txbd8 *lbdp = NULL;
a12f801d 2439 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2440 struct sk_buff *skb;
2441 int skb_dirtytx;
a12f801d 2442 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2443 int frags = 0, nr_txbds = 0;
4669bc90 2444 int i;
d080cd63 2445 int howmany = 0;
4669bc90 2446 u32 lstatus;
f0ee7acf 2447 size_t buflen;
1da177e4 2448
fba4ed03 2449 rx_queue = priv->rx_queue[tx_queue->qindex];
a12f801d
SG		 2450 bdp = tx_queue->dirty_tx;
2451 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2452
a12f801d 2453 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2454 unsigned long flags;
2455
4669bc90 2456 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf
MR		 2457
2458 /*
2459 * When time stamping, one additional TxBD must be freed.
2460 * Also, we need to dma_unmap_single() the TxPAL.
2461 */
2244d07b 2462 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2463 nr_txbds = frags + 2;
2464 else
2465 nr_txbds = frags + 1;
2466
2467 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2468
4669bc90 2469 lstatus = lbdp->lstatus;
1da177e4 2470
4669bc90
DH		 2471 /* Only clean completed frames */
2472 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2473 (lstatus & BD_LENGTH_MASK))
2474 break;
2475
2244d07b 2476 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2477 next = next_txbd(bdp, base, tx_ring_size);
2478 buflen = next->length + GMAC_FCB_LEN;
2479 } else
2480 buflen = bdp->length;
2481
2482 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2483 buflen, DMA_TO_DEVICE);
2484
2244d07b 2485 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2486 struct skb_shared_hwtstamps shhwtstamps;
2487 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2488 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2489 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2490 skb_tstamp_tx(skb, &shhwtstamps);
2491 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2492 bdp = next;
2493 }
81183059 2494
4669bc90
DH		 2495 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2496 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2497
4669bc90 2498 for (i = 0; i < frags; i++) {
4826857f 2499 dma_unmap_page(&priv->ofdev->dev,
4669bc90
DH		 2500 bdp->bufPtr,
2501 bdp->length,
2502 DMA_TO_DEVICE);
2503 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2504 bdp = next_txbd(bdp, base, tx_ring_size);
2505 }
1da177e4 2506
0fd56bb5
AF		 2507 /*
2508 * If there's room in the queue (limit it to rx_buffer_size)
2509 * we add this skb back into the pool, if it's the right size
2510 */
a12f801d 2511 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
0fd56bb5 2512 skb_recycle_check(skb, priv->rx_buffer_size +
acbc0f03
EL		 2513 RXBUF_ALIGNMENT)) {
2514 gfar_align_skb(skb);
0fd56bb5 2515 __skb_queue_head(&priv->rx_recycle, skb);
acbc0f03 2516 } else
0fd56bb5
AF		 2517 dev_kfree_skb_any(skb);
2518
a12f801d 2519 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2520
4669bc90
DH		 2521 skb_dirtytx = (skb_dirtytx + 1) &
2522 TX_RING_MOD_MASK(tx_ring_size);
2523
2524 howmany++;
a3bc1f11 2525 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2526 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2527 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2528 }
1da177e4 2529
4669bc90 2530 /* If we freed a buffer, we can restart transmission, if necessary */
fba4ed03
SG		 2531 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2532 netif_wake_subqueue(dev, tx_queue->qindex);
1da177e4 2533
4669bc90 2534 /* Update dirty indicators */
a12f801d
SG		 2535 tx_queue->skb_dirtytx = skb_dirtytx;
2536 tx_queue->dirty_tx = bdp;
1da177e4 2537
d080cd63
DH		 2538 return howmany;
2539}
2540
f4983704 2541static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2542{
a6d0b91a
AV		 2543 unsigned long flags;
2544
fba4ed03
SG		 2545 spin_lock_irqsave(&gfargrp->grplock, flags);
2546 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2547 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2548 __napi_schedule(&gfargrp->napi);
8707bdd4
JP		 2549 } else {
2550 /*
2551 * Clear IEVENT, so interrupts aren't called again
2552 * because of the packets that have already arrived.
2553 */
f4983704 2554 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2555 }
fba4ed03 2556 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2557
8c7396ae 2558}
1da177e4 2559
8c7396ae 2560/* Interrupt Handler for Transmit complete */
f4983704 2561static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2562{
f4983704 2563 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2564 return IRQ_HANDLED;
2565}
2566
a12f801d 2567static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6
AF		 2568 struct sk_buff *skb)
2569{
a12f801d 2570 struct net_device *dev = rx_queue->dev;
815b97c6 2571 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2572 dma_addr_t buf;
815b97c6 2573
8a102fe0
AV		 2574 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2575 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2576 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2577}
2578
acbc0f03 2579static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2580{
2581 struct gfar_private *priv = netdev_priv(dev);
2582 struct sk_buff *skb = NULL;
1da177e4 2583
acbc0f03 2584 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2585 if (!skb)
1da177e4
LT		 2586 return NULL;
2587
acbc0f03 2588 gfar_align_skb(skb);
7f7f5316 2589
acbc0f03
EL		 2590 return skb;
2591}
2592
2593struct sk_buff * gfar_new_skb(struct net_device *dev)
2594{
2595 struct gfar_private *priv = netdev_priv(dev);
2596 struct sk_buff *skb = NULL;
2597
2598 skb = __skb_dequeue(&priv->rx_recycle);
2599 if (!skb)
2600 skb = gfar_alloc_skb(dev);
1da177e4 2601
1da177e4
LT		 2602 return skb;
2603}
2604
298e1a9e 2605static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2606{
298e1a9e 2607 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2608 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2609 struct gfar_extra_stats *estats = &priv->extra_stats;
2610
2611 /* If the packet was truncated, none of the other errors
2612 * matter */
2613 if (status & RXBD_TRUNCATED) {
2614 stats->rx_length_errors++;
2615
2616 estats->rx_trunc++;
2617
2618 return;
2619 }
2620 /* Count the errors, if there were any */
2621 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2622 stats->rx_length_errors++;
2623
2624 if (status & RXBD_LARGE)
2625 estats->rx_large++;
2626 else
2627 estats->rx_short++;
2628 }
2629 if (status & RXBD_NONOCTET) {
2630 stats->rx_frame_errors++;
2631 estats->rx_nonoctet++;
2632 }
2633 if (status & RXBD_CRCERR) {
2634 estats->rx_crcerr++;
2635 stats->rx_crc_errors++;
2636 }
2637 if (status & RXBD_OVERRUN) {
2638 estats->rx_overrun++;
2639 stats->rx_crc_errors++;
2640 }
2641}
2642
f4983704 2643irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2644{
f4983704 2645 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2646 return IRQ_HANDLED;
2647}
2648
0bbaf069
KG		 2649static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2650{
2651 /* If valid headers were found, and valid sums
2652 * were verified, then we tell the kernel that no
2653 * checksumming is necessary. Otherwise, it is */
7f7f5316 2654 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2655 skb->ip_summed = CHECKSUM_UNNECESSARY;
2656 else
2657 skb->ip_summed = CHECKSUM_NONE;
2658}
2659
2660
1da177e4
LT		 2661/* gfar_process_frame() -- handle one incoming packet if skb
2662 * isn't NULL. */
2663static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2c2db48a 2664 int amount_pull)
1da177e4
LT		 2665{
2666 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2667 struct rxfcb *fcb = NULL;
1da177e4 2668
2c2db48a 2669 int ret;
1da177e4 2670
2c2db48a
DH		 2671 /* fcb is at the beginning if exists */
2672 fcb = (struct rxfcb *)skb->data;
0bbaf069 2673
2c2db48a
DH		 2674 /* Remove the FCB from the skb */
2675 /* Remove the padded bytes, if there are any */
f74dac08
SG		 2676 if (amount_pull) {
2677 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2678 skb_pull(skb, amount_pull);
f74dac08 2679 }
0bbaf069 2680
cc772ab7
MR		 2681 /* Get receive timestamp from the skb */
2682 if (priv->hwts_rx_en) {
2683 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2684 u64 *ns = (u64 *) skb->data;
2685 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2686 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2687 }
2688
2689 if (priv->padding)
2690 skb_pull(skb, priv->padding);
2691
2c2db48a
DH		 2692 if (priv->rx_csum_enable)
2693 gfar_rx_checksum(skb, fcb);
0bbaf069 2694
2c2db48a
DH		 2695 /* Tell the skb what kind of packet this is */
2696 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2697
2c2db48a
DH		 2698 /* Send the packet up the stack */
2699 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2700 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2701 else
2702 ret = netif_receive_skb(skb);
0bbaf069 2703
2c2db48a
DH		 2704 if (NET_RX_DROP == ret)
2705 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 2706
2707 return 0;
2708}
2709
2710/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 2711 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 2712 * of frames handled
2713 */
a12f801d 2714int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2715{
a12f801d 2716 struct net_device *dev = rx_queue->dev;
31de198b 2717 struct rxbd8 *bdp, *base;
1da177e4 2718 struct sk_buff *skb;
2c2db48a
DH		 2719 int pkt_len;
2720 int amount_pull;
1da177e4
LT		 2721 int howmany = 0;
2722 struct gfar_private *priv = netdev_priv(dev);
2723
2724 /* Get the first full descriptor */
a12f801d
SG		 2725 bdp = rx_queue->cur_rx;
2726 base = rx_queue->rx_bd_base;
1da177e4 2727
cc772ab7 2728 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2c2db48a 2729
1da177e4 2730 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2731 struct sk_buff *newskb;
3b6330ce 2732 rmb();
815b97c6
AF		 2733
2734 /* Add another skb for the future */
2735 newskb = gfar_new_skb(dev);
2736
a12f801d 2737 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2738
4826857f 2739 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
81183059
AF		 2740 priv->rx_buffer_size, DMA_FROM_DEVICE);
2741
63b88b90
AV		 2742 if (unlikely(!(bdp->status & RXBD_ERR) &&
2743 bdp->length > priv->rx_buffer_size))
2744 bdp->status = RXBD_LARGE;
2745
815b97c6
AF		 2746 /* We drop the frame if we failed to allocate a new buffer */
2747 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2748 bdp->status & RXBD_ERR)) {
2749 count_errors(bdp->status, dev);
2750
2751 if (unlikely(!newskb))
2752 newskb = skb;
acbc0f03 2753 else if (skb)
0fd56bb5 2754 __skb_queue_head(&priv->rx_recycle, skb);
815b97c6 2755 } else {
1da177e4 2756 /* Increment the number of packets */
a7f38041 2757 rx_queue->stats.rx_packets++;
1da177e4
LT		 2758 howmany++;
2759
2c2db48a
DH		 2760 if (likely(skb)) {
2761 pkt_len = bdp->length - ETH_FCS_LEN;
2762 /* Remove the FCS from the packet length */
2763 skb_put(skb, pkt_len);
a7f38041 2764 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2765 skb_record_rx_queue(skb, rx_queue->qindex);
2c2db48a
DH		 2766 gfar_process_frame(dev, skb, amount_pull);
2767
2768 } else {
2769 if (netif_msg_rx_err(priv))
2770 printk(KERN_WARNING
2771 "%s: Missing skb!\n", dev->name);
a7f38041 2772 rx_queue->stats.rx_dropped++;
2c2db48a
DH		 2773 priv->extra_stats.rx_skbmissing++;
2774 }
1da177e4 2775
1da177e4
LT		 2776 }
2777
a12f801d 2778 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2779
815b97c6 2780 /* Setup the new bdp */
a12f801d 2781 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2782
2783 /* Update to the next pointer */
a12f801d 2784 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2785
2786 /* update to point at the next skb */
a12f801d
SG		 2787 rx_queue->skb_currx =
2788 (rx_queue->skb_currx + 1) &
2789 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2790 }
2791
2792 /* Update the current rxbd pointer to be the next one */
a12f801d 2793 rx_queue->cur_rx = bdp;
1da177e4 2794
1da177e4
LT		 2795 return howmany;
2796}
2797
bea3348e 2798static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2799{
fba4ed03
SG		 2800 struct gfar_priv_grp *gfargrp = container_of(napi,
2801 struct gfar_priv_grp, napi);
2802 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2803 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2804 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03
SG		 2805 struct gfar_priv_rx_q *rx_queue = NULL;
2806 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
18294ad1
AV		 2807 int tx_cleaned = 0, i, left_over_budget = budget;
2808 unsigned long serviced_queues = 0;
fba4ed03 2809 int num_queues = 0;
d080cd63 2810
fba4ed03
SG		 2811 num_queues = gfargrp->num_rx_queues;
2812 budget_per_queue = budget/num_queues;
2813
8c7396ae
DH		 2814 /* Clear IEVENT, so interrupts aren't called again
2815 * because of the packets that have already arrived */
f4983704 2816 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2817
fba4ed03 2818 while (num_queues && left_over_budget) {
1da177e4 2819
fba4ed03
SG		 2820 budget_per_queue = left_over_budget/num_queues;
2821 left_over_budget = 0;
2822
984b3f57 2823 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
fba4ed03
SG		 2824 if (test_bit(i, &serviced_queues))
2825 continue;
2826 rx_queue = priv->rx_queue[i];
2827 tx_queue = priv->tx_queue[rx_queue->qindex];
2828
a3bc1f11 2829 tx_cleaned += gfar_clean_tx_ring(tx_queue);
fba4ed03
SG		 2830 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2831 budget_per_queue);
2832 rx_cleaned += rx_cleaned_per_queue;
2833 if(rx_cleaned_per_queue < budget_per_queue) {
2834 left_over_budget = left_over_budget +
2835 (budget_per_queue - rx_cleaned_per_queue);
2836 set_bit(i, &serviced_queues);
2837 num_queues--;
2838 }
2839 }
2840 }
1da177e4 2841
42199884
AF		 2842 if (tx_cleaned)
2843 return budget;
2844
2845 if (rx_cleaned < budget) {
288379f0 2846 napi_complete(napi);
1da177e4
LT		 2847
2848 /* Clear the halt bit in RSTAT */
fba4ed03 2849 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2850
f4983704 2851 gfar_write(&regs->imask, IMASK_DEFAULT);
1da177e4
LT		 2852
2853 /* If we are coalescing interrupts, update the timer */
2854 /* Otherwise, clear it */
46ceb60c
SG		 2855 gfar_configure_coalescing(priv,
2856 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
1da177e4
LT		 2857 }
2858
42199884 2859 return rx_cleaned;
1da177e4 2860}
1da177e4 2861
f2d71c2d
VW		 2862#ifdef CONFIG_NET_POLL_CONTROLLER
2863/*
2864 * Polling 'interrupt' - used by things like netconsole to send skbs
2865 * without having to re-enable interrupts. It's not called while
2866 * the interrupt routine is executing.
2867 */
2868static void gfar_netpoll(struct net_device *dev)
2869{
2870 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2871 int i = 0;
f2d71c2d
VW		 2872
2873 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2874 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 2875 for (i = 0; i < priv->num_grps; i++) {
2876 disable_irq(priv->gfargrp[i].interruptTransmit);
2877 disable_irq(priv->gfargrp[i].interruptReceive);
2878 disable_irq(priv->gfargrp[i].interruptError);
2879 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2880 &priv->gfargrp[i]);
2881 enable_irq(priv->gfargrp[i].interruptError);
2882 enable_irq(priv->gfargrp[i].interruptReceive);
2883 enable_irq(priv->gfargrp[i].interruptTransmit);
2884 }
f2d71c2d 2885 } else {
46ceb60c
SG		 2886 for (i = 0; i < priv->num_grps; i++) {
2887 disable_irq(priv->gfargrp[i].interruptTransmit);
2888 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2889 &priv->gfargrp[i]);
2890 enable_irq(priv->gfargrp[i].interruptTransmit);
43de004b 2891 }
f2d71c2d
VW		 2892 }
2893}
2894#endif
2895
1da177e4 2896/* The interrupt handler for devices with one interrupt */
f4983704 2897static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2898{
f4983704 2899 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2900
2901 /* Save ievent for future reference */
f4983704 2902 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2903
1da177e4 2904 /* Check for reception */
538cc7ee 2905 if (events & IEVENT_RX_MASK)
f4983704 2906 gfar_receive(irq, grp_id);
1da177e4
LT		 2907
2908 /* Check for transmit completion */
538cc7ee 2909 if (events & IEVENT_TX_MASK)
f4983704 2910 gfar_transmit(irq, grp_id);
1da177e4 2911
538cc7ee
SS		 2912 /* Check for errors */
2913 if (events & IEVENT_ERR_MASK)
f4983704 2914 gfar_error(irq, grp_id);
1da177e4
LT		 2915
2916 return IRQ_HANDLED;
2917}
2918
1da177e4
LT		 2919/* Called every time the controller might need to be made
2920 * aware of new link state. The PHY code conveys this
bb40dcbb 2921 * information through variables in the phydev structure, and this
1da177e4
LT		 2922 * function converts those variables into the appropriate
2923 * register values, and can bring down the device if needed.
2924 */
2925static void adjust_link(struct net_device *dev)
2926{
2927 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2928 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2929 unsigned long flags;
2930 struct phy_device *phydev = priv->phydev;
2931 int new_state = 0;
2932
fba4ed03
SG		 2933 local_irq_save(flags);
2934 lock_tx_qs(priv);
2935
bb40dcbb
AF		 2936 if (phydev->link) {
2937 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2938 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2939
1da177e4
LT		 2940 /* Now we make sure that we can be in full duplex mode.
2941 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 2942 if (phydev->duplex != priv->oldduplex) {
2943 new_state = 1;
2944 if (!(phydev->duplex))
1da177e4 2945 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2946 else
1da177e4 2947 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2948
bb40dcbb 2949 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2950 }
2951
bb40dcbb
AF		 2952 if (phydev->speed != priv->oldspeed) {
2953 new_state = 1;
2954 switch (phydev->speed) {
1da177e4 2955 case 1000:
1da177e4
LT		 2956 tempval =
2957 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 2958
2959 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2960 break;
2961 case 100:
2962 case 10:
1da177e4
LT		 2963 tempval =
2964 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 2965
2966 /* Reduced mode distinguishes
2967 * between 10 and 100 */
2968 if (phydev->speed == SPEED_100)
2969 ecntrl |= ECNTRL_R100;
2970 else
2971 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2972 break;
2973 default:
0bbaf069
KG		 2974 if (netif_msg_link(priv))
2975 printk(KERN_WARNING
bb40dcbb
AF		 2976 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2977 dev->name, phydev->speed);
1da177e4
LT		 2978 break;
2979 }
2980
bb40dcbb 2981 priv->oldspeed = phydev->speed;
1da177e4
LT		 2982 }
2983
bb40dcbb 2984 gfar_write(&regs->maccfg2, tempval);
7f7f5316 2985 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 2986
1da177e4 2987 if (!priv->oldlink) {
bb40dcbb 2988 new_state = 1;
1da177e4 2989 priv->oldlink = 1;
1da177e4 2990 }
bb40dcbb
AF		 2991 } else if (priv->oldlink) {
2992 new_state = 1;
2993 priv->oldlink = 0;
2994 priv->oldspeed = 0;
2995 priv->oldduplex = -1;
1da177e4 2996 }
1da177e4 2997
bb40dcbb
AF		 2998 if (new_state && netif_msg_link(priv))
2999 phy_print_status(phydev);
fba4ed03
SG		 3000 unlock_tx_qs(priv);
3001 local_irq_restore(flags);
bb40dcbb 3002}
1da177e4
LT		 3003
3004/* Update the hash table based on the current list of multicast
3005 * addresses we subscribe to. Also, change the promiscuity of
3006 * the device based on the flags (this function is called
3007 * whenever dev->flags is changed */
3008static void gfar_set_multi(struct net_device *dev)
3009{
22bedad3 3010 struct netdev_hw_addr *ha;
1da177e4 3011 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3012 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3013 u32 tempval;
3014
a12f801d 3015 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3016 /* Set RCTRL to PROM */
3017 tempval = gfar_read(&regs->rctrl);
3018 tempval |= RCTRL_PROM;
3019 gfar_write(&regs->rctrl, tempval);
3020 } else {
3021 /* Set RCTRL to not PROM */
3022 tempval = gfar_read(&regs->rctrl);
3023 tempval &= ~(RCTRL_PROM);
3024 gfar_write(&regs->rctrl, tempval);
3025 }
6aa20a22 3026
a12f801d 3027 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3028 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3029 gfar_write(&regs->igaddr0, 0xffffffff);
3030 gfar_write(&regs->igaddr1, 0xffffffff);
3031 gfar_write(&regs->igaddr2, 0xffffffff);
3032 gfar_write(&regs->igaddr3, 0xffffffff);
3033 gfar_write(&regs->igaddr4, 0xffffffff);
3034 gfar_write(&regs->igaddr5, 0xffffffff);
3035 gfar_write(&regs->igaddr6, 0xffffffff);
3036 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3037 gfar_write(&regs->gaddr0, 0xffffffff);
3038 gfar_write(&regs->gaddr1, 0xffffffff);
3039 gfar_write(&regs->gaddr2, 0xffffffff);
3040 gfar_write(&regs->gaddr3, 0xffffffff);
3041 gfar_write(&regs->gaddr4, 0xffffffff);
3042 gfar_write(&regs->gaddr5, 0xffffffff);
3043 gfar_write(&regs->gaddr6, 0xffffffff);
3044 gfar_write(&regs->gaddr7, 0xffffffff);
3045 } else {
7f7f5316
AF		 3046 int em_num;
3047 int idx;
3048
1da177e4 3049 /* zero out the hash */
0bbaf069
KG		 3050 gfar_write(&regs->igaddr0, 0x0);
3051 gfar_write(&regs->igaddr1, 0x0);
3052 gfar_write(&regs->igaddr2, 0x0);
3053 gfar_write(&regs->igaddr3, 0x0);
3054 gfar_write(&regs->igaddr4, 0x0);
3055 gfar_write(&regs->igaddr5, 0x0);
3056 gfar_write(&regs->igaddr6, 0x0);
3057 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3058 gfar_write(&regs->gaddr0, 0x0);
3059 gfar_write(&regs->gaddr1, 0x0);
3060 gfar_write(&regs->gaddr2, 0x0);
3061 gfar_write(&regs->gaddr3, 0x0);
3062 gfar_write(&regs->gaddr4, 0x0);
3063 gfar_write(&regs->gaddr5, 0x0);
3064 gfar_write(&regs->gaddr6, 0x0);
3065 gfar_write(&regs->gaddr7, 0x0);
3066
7f7f5316
AF		 3067 /* If we have extended hash tables, we need to
3068 * clear the exact match registers to prepare for
3069 * setting them */
3070 if (priv->extended_hash) {
3071 em_num = GFAR_EM_NUM + 1;
3072 gfar_clear_exact_match(dev);
3073 idx = 1;
3074 } else {
3075 idx = 0;
3076 em_num = 0;
3077 }
3078
4cd24eaf 3079 if (netdev_mc_empty(dev))
1da177e4
LT		 3080 return;
3081
3082 /* Parse the list, and set the appropriate bits */
22bedad3 3083 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3084 if (idx < em_num) {
22bedad3 3085 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3086 idx++;
3087 } else
22bedad3 3088 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3089 }
3090 }
1da177e4
LT		 3091}
3092
7f7f5316
AF		 3093
3094/* Clears each of the exact match registers to zero, so they
3095 * don't interfere with normal reception */
3096static void gfar_clear_exact_match(struct net_device *dev)
3097{
3098 int idx;
3099 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
3100
3101 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3102 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
3103}
3104
1da177e4
LT		 3105/* Set the appropriate hash bit for the given addr */
3106/* The algorithm works like so:
3107 * 1) Take the Destination Address (ie the multicast address), and
3108 * do a CRC on it (little endian), and reverse the bits of the
3109 * result.
3110 * 2) Use the 8 most significant bits as a hash into a 256-entry
3111 * table. The table is controlled through 8 32-bit registers:
3112 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3113 * gaddr7. This means that the 3 most significant bits in the
3114 * hash index which gaddr register to use, and the 5 other bits
3115 * indicate which bit (assuming an IBM numbering scheme, which
3116 * for PowerPC (tm) is usually the case) in the register holds
3117 * the entry. */
3118static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3119{
3120 u32 tempval;
3121 struct gfar_private *priv = netdev_priv(dev);
1da177e4 3122 u32 result = ether_crc(MAC_ADDR_LEN, addr);
0bbaf069
KG		 3123 int width = priv->hash_width;
3124 u8 whichbit = (result >> (32 - width)) & 0x1f;
3125 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3126 u32 value = (1 << (31-whichbit));
3127
0bbaf069 3128 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3129 tempval |= value;
0bbaf069 3130 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3131}
3132
7f7f5316
AF		 3133
3134/* There are multiple MAC Address register pairs on some controllers
3135 * This function sets the numth pair to a given address
3136 */
3137static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
3138{
3139 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3140 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316
AF		 3141 int idx;
3142 char tmpbuf[MAC_ADDR_LEN];
3143 u32 tempval;
f4983704 3144 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3145
3146 macptr += num*2;
3147
3148 /* Now copy it into the mac registers backwards, cuz */
3149 /* little endian is silly */
3150 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3151 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3152
3153 gfar_write(macptr, *((u32 *) (tmpbuf)));
3154
3155 tempval = *((u32 *) (tmpbuf + 4));
3156
3157 gfar_write(macptr+1, tempval);
3158}
3159
1da177e4 3160/* GFAR error interrupt handler */
f4983704 3161static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3162{
f4983704
SG		 3163 struct gfar_priv_grp *gfargrp = grp_id;
3164 struct gfar __iomem *regs = gfargrp->regs;
3165 struct gfar_private *priv= gfargrp->priv;
3166 struct net_device *dev = priv->ndev;
1da177e4
LT		 3167
3168 /* Save ievent for future reference */
f4983704 3169 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3170
3171 /* Clear IEVENT */
f4983704 3172 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3173
3174 /* Magic Packet is not an error. */
b31a1d8b 3175 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3176 (events & IEVENT_MAG))
3177 events &= ~IEVENT_MAG;
1da177e4
LT		 3178
3179 /* Hmm... */
0bbaf069
KG		 3180 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3181 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
f4983704 3182 dev->name, events, gfar_read(&regs->imask));
1da177e4
LT		 3183
3184 /* Update the error counters */
3185 if (events & IEVENT_TXE) {
09f75cd7 3186 dev->stats.tx_errors++;
1da177e4
LT		 3187
3188 if (events & IEVENT_LC)
09f75cd7 3189 dev->stats.tx_window_errors++;
1da177e4 3190 if (events & IEVENT_CRL)
09f75cd7 3191 dev->stats.tx_aborted_errors++;
1da177e4 3192 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3193 unsigned long flags;
3194
0bbaf069 3195 if (netif_msg_tx_err(priv))
538cc7ee
SS		 3196 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3197 "packet dropped.\n", dev->name);
09f75cd7 3198 dev->stats.tx_dropped++;
1da177e4
LT		 3199 priv->extra_stats.tx_underrun++;
3200
836cf7fa
AV		 3201 local_irq_save(flags);
3202 lock_tx_qs(priv);
3203
1da177e4 3204 /* Reactivate the Tx Queues */
fba4ed03 3205 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3206
3207 unlock_tx_qs(priv);
3208 local_irq_restore(flags);
1da177e4 3209 }
0bbaf069
KG		 3210 if (netif_msg_tx_err(priv))
3211 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1da177e4
LT		 3212 }
3213 if (events & IEVENT_BSY) {
09f75cd7 3214 dev->stats.rx_errors++;
1da177e4
LT		 3215 priv->extra_stats.rx_bsy++;
3216
f4983704 3217 gfar_receive(irq, grp_id);
1da177e4 3218
0bbaf069 3219 if (netif_msg_rx_err(priv))
538cc7ee 3220 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
f4983704 3221 dev->name, gfar_read(&regs->rstat));
1da177e4
LT		 3222 }
3223 if (events & IEVENT_BABR) {
09f75cd7 3224 dev->stats.rx_errors++;
1da177e4
LT		 3225 priv->extra_stats.rx_babr++;
3226
0bbaf069 3227 if (netif_msg_rx_err(priv))
538cc7ee 3228 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1da177e4
LT		 3229 }
3230 if (events & IEVENT_EBERR) {
3231 priv->extra_stats.eberr++;
0bbaf069 3232 if (netif_msg_rx_err(priv))
538cc7ee 3233 printk(KERN_DEBUG "%s: bus error\n", dev->name);
1da177e4 3234 }
0bbaf069 3235 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
538cc7ee 3236 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1da177e4
LT		 3237
3238 if (events & IEVENT_BABT) {
3239 priv->extra_stats.tx_babt++;
0bbaf069 3240 if (netif_msg_tx_err(priv))
538cc7ee 3241 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1da177e4
LT		 3242 }
3243 return IRQ_HANDLED;
3244}
3245
b31a1d8b
AF		 3246static struct of_device_id gfar_match[] =
3247{
3248 {
3249 .type = "network",
3250 .compatible = "gianfar",
3251 },
46ceb60c
SG		 3252 {
3253 .compatible = "fsl,etsec2",
3254 },
b31a1d8b
AF		 3255 {},
3256};
e72701ac 3257MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3258
1da177e4 3259/* Structure for a device driver */
b31a1d8b 3260static struct of_platform_driver gfar_driver = {
4018294b
GL		 3261 .driver = {
3262 .name = "fsl-gianfar",
3263 .owner = THIS_MODULE,
3264 .pm = GFAR_PM_OPS,
3265 .of_match_table = gfar_match,
3266 },
1da177e4
LT		 3267 .probe = gfar_probe,
3268 .remove = gfar_remove,
3269};
3270
3271static int __init gfar_init(void)
3272{
1577ecef 3273 return of_register_platform_driver(&gfar_driver);
1da177e4
LT		 3274}
3275
3276static void __exit gfar_exit(void)
3277{
b31a1d8b 3278 of_unregister_platform_driver(&gfar_driver);
1da177e4
LT		 3279}
3280
3281module_init(gfar_init);
3282module_exit(gfar_exit);
3283
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