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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Linux Kernel Additions:
21
22 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
23 0.99H+lk1.0 - Jeff Garzik <jgarzik@pobox.com>
24 Remove compatibility defines for kernel versions < 2.2.x.
25 Update for new 2.3.x module interface
26 LK1.1.2 (March 19, 2000)
27 * New PCI interface (jgarzik)
28
29 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
30 - Merged with 3c575_cb.c
31 - Don't set RxComplete in boomerang interrupt enable reg
32 - spinlock in vortex_timer to protect mdio functions
33 - disable local interrupts around call to vortex_interrupt in
34 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
35 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
36 - In vortex_start_xmit(), move the lock to _after_ we've altered
37 vp->cur_tx and vp->tx_full. This defeats the race between
38 vortex_start_xmit() and vortex_interrupt which was identified
39 by Bogdan Costescu.
40 - Merged back support for six new cards from various sources
41 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
42 insertion oops)
43 - Tell it that 3c905C has NWAY for 100bT autoneg
44 - Fix handling of SetStatusEnd in 'Too much work..' code, as
45 per 2.3.99's 3c575_cb (Dave Hinds).
46 - Split ISR into two for vortex & boomerang
47 - Fix MOD_INC/DEC races
48 - Handle resource allocation failures.
49 - Fix 3CCFE575CT LED polarity
50 - Make tx_interrupt_mitigation the default
51
52 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
53 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
54 - Put vortex_info_tbl into __devinitdata
55 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
56 as in the hardware.
57 - Increased the loop counter in issue_and_wait from 2,000 to 4,000.
58
59 LK1.1.5 28 April 2000, andrewm
60 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
61 - Some extra diagnostics
62 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
63 chips usually get a Tx timeout.
64 - Added extra_reset module parm
65 - Replaced some inline timer manip with mod_timer
66 (Franois romieu <Francois.Romieu@nic.fr>)
67 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
68 (this came across from 3c575_cb).
69
70 LK1.1.6 06 Jun 2000, andrewm
71 - Backed out the PPC defines.
72 - Use del_timer_sync(), mod_timer().
73 - Fix wrapped ulong comparison in boomerang_rx()
74 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
75 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
76 - Replace union wn3_config with BFINS/BFEXT manipulation for
77 sparc64 (Pete Zaitcev, Peter Jones)
78 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
79 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
80 Donald Becker)
81 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
82 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
83
84 LK1.1.7 2 Jul 2000 andrewm
85 - Better handling of shared IRQs
86 - Reset the transmitter on a Tx reclaim error
87 - Fixed crash under OOM during vortex_open() (Mark Hemment)
88 - Fix Rx cessation problem during OOM (help from Mark Hemment)
89 - The spinlocks around the mdio access were blocking interrupts for 300uS.
90 Fix all this to use spin_lock_bh() within mdio_read/write
91 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
92 have one.
93 - Added 802.3x MAC-layer flow control support
94
95 LK1.1.8 13 Aug 2000 andrewm
96 - Ignore request_region() return value - already reserved if Cardbus.
97 - Merged some additional Cardbus flags from Don's 0.99Qk
98 - Some fixes for 3c556 (Fred Maciel)
99 - Fix for EISA initialisation (Jan Rekorajski)
100 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
101 - Fixed MII_XCVR_PWR for 3CCFE575CT
102 - Added INVERT_LED_PWR, used it.
103 - Backed out the extra_reset stuff
104
105 LK1.1.9 12 Sep 2000 andrewm
106 - Backed out the tx_reset_resume flags. It was a no-op.
107 - In vortex_error, don't reset the Tx on txReclaim errors
108 - In vortex_error, don't reset the Tx on maxCollisions errors.
109 Hence backed out all the DownListPtr logic here.
110 - In vortex_error, give Tornado cards a partial TxReset on
111 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
112 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
113 - Fixed a bug where, if vp->tx_full is set when the interface
114 is downed, it remains set when the interface is upped. Bad
115 things happen.
116
117 LK1.1.10 17 Sep 2000 andrewm
118 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
119 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
120 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
121
122 LK1.1.11 13 Nov 2000 andrewm
123 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
124
125 LK1.1.12 1 Jan 2001 andrewm (2.4.0-pre1)
126 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
127 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
128 - Added extended issue_and_wait for the 3c905CX.
129 - Look for an MII on PHY index 24 first (3c905CX oddity).
130 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
131 - Don't free skbs we don't own on oom path in vortex_open().
132
133 LK1.1.13 27 Jan 2001
134 - Added explicit `medialock' flag so we can truly
135 lock the media type down with `options'.
136 - "check ioremap return and some tidbits" (Arnaldo Carvalho de Melo <acme@conectiva.com.br>)
137 - Added and used EEPROM_NORESET for 3c556B PM resumes.
138 - Fixed leakage of vp->rx_ring.
139 - Break out separate HAS_HWCKSM device capability flag.
140 - Kill vp->tx_full (ANK)
141 - Merge zerocopy fragment handling (ANK?)
142
143 LK1.1.14 15 Feb 2001
144 - Enable WOL. Can be turned on with `enable_wol' module option.
145 - EISA and PCI initialisation fixes (jgarzik, Manfred Spraul)
146 - If a device's internalconfig register reports it has NWAY,
147 use it, even if autoselect is enabled.
148
149 LK1.1.15 6 June 2001 akpm
150 - Prevent double counting of received bytes (Lars Christensen)
151 - Add ethtool support (jgarzik)
152 - Add module parm descriptions (Andrzej M. Krzysztofowicz)
153 - Implemented alloc_etherdev() API
154 - Special-case the 'Tx error 82' message.
155
156 LK1.1.16 18 July 2001 akpm
157 - Make NETIF_F_SG dependent upon nr_free_highpages(), not on CONFIG_HIGHMEM
158 - Lessen verbosity of bootup messages
159 - Fix WOL - use new PM API functions.
160 - Use netif_running() instead of vp->open in suspend/resume.
161 - Don't reset the interface logic on open/close/rmmod. It upsets
162 autonegotiation, and hence DHCP (from 0.99T).
163 - Back out EEPROM_NORESET flag because of the above (we do it for all
164 NICs).
165 - Correct 3c982 identification string
166 - Rename wait_for_completion() to issue_and_wait() to avoid completion.h
167 clash.
168
169 LK1.1.17 18Dec01 akpm
170 - PCI ID 9805 is a Python-T, not a dual-port Cyclone. Apparently.
171 And it has NWAY.
172 - Mask our advertised modes (vp->advertising) with our capabilities
173 (MII reg5) when deciding which duplex mode to use.
174 - Add `global_options' as default for options[]. Ditto global_enable_wol,
175 global_full_duplex.
176
177 LK1.1.18 01Jul02 akpm
178 - Fix for undocumented transceiver power-up bit on some 3c566B's
179 (Donald Becker, Rahul Karnik)
180
181 - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
182 - Also see Documentation/networking/vortex.txt
183
184 LK1.1.19 10Nov02 Marc Zyngier <maz@wild-wind.fr.eu.org>
185 - EISA sysfs integration.
186*/
187
188/*
189 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
190 * as well as other drivers
191 *
192 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
193 * due to dead code elimination. There will be some performance benefits from this due to
194 * elimination of all the tests and reduced cache footprint.
195 */
196
197
198#define DRV_NAME "3c59x"
1da177e4
LT		 199
200
201
202/* A few values that may be tweaked. */
203/* Keep the ring sizes a power of two for efficiency. */
204#define TX_RING_SIZE 16
205#define RX_RING_SIZE 32
206#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
207
208/* "Knobs" that adjust features and parameters. */
209/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
210 Setting to > 1512 effectively disables this feature. */
211#ifndef __arm__
212static int rx_copybreak = 200;
213#else
214/* ARM systems perform better by disregarding the bus-master
215 transfer capability of these cards. -- rmk */
216static int rx_copybreak = 1513;
217#endif
218/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
219static const int mtu = 1500;
220/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
221static int max_interrupt_work = 32;
222/* Tx timeout interval (millisecs) */
223static int watchdog = 5000;
224
225/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
226 * of possible Tx stalls if the system is blocking interrupts
227 * somewhere else. Undefine this to disable.
228 */
229#define tx_interrupt_mitigation 1
230
231/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
232#define vortex_debug debug
233#ifdef VORTEX_DEBUG
234static int vortex_debug = VORTEX_DEBUG;
235#else
236static int vortex_debug = 1;
237#endif
238
239#include <linux/config.h>
240#include <linux/module.h>
241#include <linux/kernel.h>
242#include <linux/string.h>
243#include <linux/timer.h>
244#include <linux/errno.h>
245#include <linux/in.h>
246#include <linux/ioport.h>
247#include <linux/slab.h>
248#include <linux/interrupt.h>
249#include <linux/pci.h>
250#include <linux/mii.h>
251#include <linux/init.h>
252#include <linux/netdevice.h>
253#include <linux/etherdevice.h>
254#include <linux/skbuff.h>
255#include <linux/ethtool.h>
256#include <linux/highmem.h>
257#include <linux/eisa.h>
258#include <linux/bitops.h>
ff5688ae 259#include <linux/jiffies.h>
1da177e4
LT		 260#include <asm/irq.h> /* For NR_IRQS only. */
261#include <asm/io.h>
262#include <asm/uaccess.h>
263
264/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
265 This is only in the support-all-kernels source code. */
266
267#define RUN_AT(x) (jiffies + (x))
268
269#include <linux/delay.h>
270
271
272static char version[] __devinitdata =
273DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
274
275MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 276MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 277MODULE_LICENSE("GPL");
1da177e4
LT		 278
279
280/* Operational parameter that usually are not changed. */
281
282/* The Vortex size is twice that of the original EtherLinkIII series: the
283 runtime register window, window 1, is now always mapped in.
284 The Boomerang size is twice as large as the Vortex -- it has additional
285 bus master control registers. */
286#define VORTEX_TOTAL_SIZE 0x20
287#define BOOMERANG_TOTAL_SIZE 0x40
288
289/* Set iff a MII transceiver on any interface requires mdio preamble.
290 This only set with the original DP83840 on older 3c905 boards, so the extra
291 code size of a per-interface flag is not worthwhile. */
292static char mii_preamble_required;
293
294#define PFX DRV_NAME ": "
295
296
297
298/*
299 Theory of Operation
300
301I. Board Compatibility
302
303This device driver is designed for the 3Com FastEtherLink and FastEtherLink
304XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
305versions of the FastEtherLink cards. The supported product IDs are
306 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
307
308The related ISA 3c515 is supported with a separate driver, 3c515.c, included
309with the kernel source or available from
310 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
311
312II. Board-specific settings
313
314PCI bus devices are configured by the system at boot time, so no jumpers
315need to be set on the board. The system BIOS should be set to assign the
316PCI INTA signal to an otherwise unused system IRQ line.
317
318The EEPROM settings for media type and forced-full-duplex are observed.
319The EEPROM media type should be left at the default "autoselect" unless using
32010base2 or AUI connections which cannot be reliably detected.
321
322III. Driver operation
323
324The 3c59x series use an interface that's very similar to the previous 3c5x9
325series. The primary interface is two programmed-I/O FIFOs, with an
326alternate single-contiguous-region bus-master transfer (see next).
327
328The 3c900 "Boomerang" series uses a full-bus-master interface with separate
329lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
330DEC Tulip and Intel Speedo3. The first chip version retains a compatible
331programmed-I/O interface that has been removed in 'B' and subsequent board
332revisions.
333
334One extension that is advertised in a very large font is that the adapters
335are capable of being bus masters. On the Vortex chip this capability was
336only for a single contiguous region making it far less useful than the full
337bus master capability. There is a significant performance impact of taking
338an extra interrupt or polling for the completion of each transfer, as well
339as difficulty sharing the single transfer engine between the transmit and
340receive threads. Using DMA transfers is a win only with large blocks or
341with the flawed versions of the Intel Orion motherboard PCI controller.
342
343The Boomerang chip's full-bus-master interface is useful, and has the
344currently-unused advantages over other similar chips that queued transmit
345packets may be reordered and receive buffer groups are associated with a
346single frame.
347
348With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
349Rather than a fixed intermediate receive buffer, this scheme allocates
350full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
351the copying breakpoint: it is chosen to trade-off the memory wasted by
352passing the full-sized skbuff to the queue layer for all frames vs. the
353copying cost of copying a frame to a correctly-sized skbuff.
354
355IIIC. Synchronization
356The driver runs as two independent, single-threaded flows of control. One
357is the send-packet routine, which enforces single-threaded use by the
358dev->tbusy flag. The other thread is the interrupt handler, which is single
359threaded by the hardware and other software.
360
361IV. Notes
362
363Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
3643c590, 3c595, and 3c900 boards.
365The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
366the EISA version is called "Demon". According to Terry these names come
367from rides at the local amusement park.
368
369The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
370This driver only supports ethernet packets because of the skbuff allocation
371limit of 4K.
372*/
373
374/* This table drives the PCI probe routines. It's mostly boilerplate in all
375 of the drivers, and will likely be provided by some future kernel.
376*/
377enum pci_flags_bit {
378 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
379 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
380};
381
382enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
383 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
384 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
385 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
386 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
387 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
388
389enum vortex_chips {
390 CH_3C590 = 0,
391 CH_3C592,
392 CH_3C597,
393 CH_3C595_1,
394 CH_3C595_2,
395
396 CH_3C595_3,
397 CH_3C900_1,
398 CH_3C900_2,
399 CH_3C900_3,
400 CH_3C900_4,
401
402 CH_3C900_5,
403 CH_3C900B_FL,
404 CH_3C905_1,
405 CH_3C905_2,
406 CH_3C905B_1,
407
408 CH_3C905B_2,
409 CH_3C905B_FX,
410 CH_3C905C,
411 CH_3C9202,
412 CH_3C980,
413 CH_3C9805,
414
415 CH_3CSOHO100_TX,
416 CH_3C555,
417 CH_3C556,
418 CH_3C556B,
419 CH_3C575,
420
421 CH_3C575_1,
422 CH_3CCFE575,
423 CH_3CCFE575CT,
424 CH_3CCFE656,
425 CH_3CCFEM656,
426
427 CH_3CCFEM656_1,
428 CH_3C450,
429 CH_3C920,
430 CH_3C982A,
431 CH_3C982B,
432
433 CH_905BT4,
434 CH_920B_EMB_WNM,
435};
436
437
438/* note: this array directly indexed by above enums, and MUST
439 * be kept in sync with both the enums above, and the PCI device
440 * table below
441 */
442static struct vortex_chip_info {
443 const char *name;
444 int flags;
445 int drv_flags;
446 int io_size;
447} vortex_info_tbl[] __devinitdata = {
448 {"3c590 Vortex 10Mbps",
449 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
450 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
451 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
452 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
453 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
454 {"3c595 Vortex 100baseTx",
455 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
456 {"3c595 Vortex 100baseT4",
457 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
458
459 {"3c595 Vortex 100base-MII",
460 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
461 {"3c900 Boomerang 10baseT",
462 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
463 {"3c900 Boomerang 10Mbps Combo",
464 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
465 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
466 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
467 {"3c900 Cyclone 10Mbps Combo",
468 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
469
470 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
471 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
472 {"3c900B-FL Cyclone 10base-FL",
473 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
474 {"3c905 Boomerang 100baseTx",
475 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
476 {"3c905 Boomerang 100baseT4",
477 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
478 {"3c905B Cyclone 100baseTx",
479 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
480
481 {"3c905B Cyclone 10/100/BNC",
482 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
483 {"3c905B-FX Cyclone 100baseFx",
484 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
485 {"3c905C Tornado",
486 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
487 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
488 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
489 {"3c980 Cyclone",
490 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
491
492 {"3c980C Python-T",
493 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
494 {"3cSOHO100-TX Hurricane",
495 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
496 {"3c555 Laptop Hurricane",
497 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
498 {"3c556 Laptop Tornado",
499 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
500 HAS_HWCKSM, 128, },
501 {"3c556B Laptop Hurricane",
502 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
503 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
504
505 {"3c575 [Megahertz] 10/100 LAN CardBus",
506 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
507 {"3c575 Boomerang CardBus",
508 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
509 {"3CCFE575BT Cyclone CardBus",
510 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
511 INVERT_LED_PWR|HAS_HWCKSM, 128, },
512 {"3CCFE575CT Tornado CardBus",
513 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
514 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
515 {"3CCFE656 Cyclone CardBus",
516 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
517 INVERT_LED_PWR|HAS_HWCKSM, 128, },
518
519 {"3CCFEM656B Cyclone+Winmodem CardBus",
520 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
521 INVERT_LED_PWR|HAS_HWCKSM, 128, },
522 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
523 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
524 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
525 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
526 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
527 {"3c920 Tornado",
528 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
529 {"3c982 Hydra Dual Port A",
530 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
531
532 {"3c982 Hydra Dual Port B",
533 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
534 {"3c905B-T4",
535 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
536 {"3c920B-EMB-WNM Tornado",
537 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
538
539 {NULL,}, /* NULL terminated list. */
540};
541
542
543static struct pci_device_id vortex_pci_tbl[] = {
544 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
545 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
546 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
547 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
548 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
549
550 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
551 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
552 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
553 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
554 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
555
556 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
557 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
558 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
559 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
560 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
561
562 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
563 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
564 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
565 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
566 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
567 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
568
569 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
570 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
571 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
572 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
573 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
574
575 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
576 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
577 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
578 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
579 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
580
581 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
582 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
583 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
584 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
585 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
586
587 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
588 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
589
590 {0,} /* 0 terminated list. */
591};
592MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
593
594
595/* Operational definitions.
596 These are not used by other compilation units and thus are not
597 exported in a ".h" file.
598
599 First the windows. There are eight register windows, with the command
600 and status registers available in each.
601 */
62afe595 602#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 603#define EL3_CMD 0x0e
604#define EL3_STATUS 0x0e
605
606/* The top five bits written to EL3_CMD are a command, the lower
607 11 bits are the parameter, if applicable.
608 Note that 11 parameters bits was fine for ethernet, but the new chip
609 can handle FDDI length frames (~4500 octets) and now parameters count
610 32-bit 'Dwords' rather than octets. */
611
612enum vortex_cmd {
613 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
614 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
615 UpStall = 6<<11, UpUnstall = (6<<11)+1,
616 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
617 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
618 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
619 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
620 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
621 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
622 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
623
624/* The SetRxFilter command accepts the following classes: */
625enum RxFilter {
626 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
627
628/* Bits in the general status register. */
629enum vortex_status {
630 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
631 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
632 IntReq = 0x0040, StatsFull = 0x0080,
633 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
634 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
635 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
636};
637
638/* Register window 1 offsets, the window used in normal operation.
639 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
640enum Window1 {
641 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
642 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
643 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
644};
645enum Window0 {
646 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
647 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
648 IntrStatus=0x0E, /* Valid in all windows. */
649};
650enum Win0_EEPROM_bits {
651 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
652 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
653 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
654};
655/* EEPROM locations. */
656enum eeprom_offset {
657 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
658 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
659 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
660 DriverTune=13, Checksum=15};
661
662enum Window2 { /* Window 2. */
663 Wn2_ResetOptions=12,
664};
665enum Window3 { /* Window 3: MAC/config bits. */
666 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
667};
668
669#define BFEXT(value, offset, bitcount) \
670 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
671
672#define BFINS(lhs, rhs, offset, bitcount) \
673 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
674 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
675
676#define RAM_SIZE(v) BFEXT(v, 0, 3)
677#define RAM_WIDTH(v) BFEXT(v, 3, 1)
678#define RAM_SPEED(v) BFEXT(v, 4, 2)
679#define ROM_SIZE(v) BFEXT(v, 6, 2)
680#define RAM_SPLIT(v) BFEXT(v, 16, 2)
681#define XCVR(v) BFEXT(v, 20, 4)
682#define AUTOSELECT(v) BFEXT(v, 24, 1)
683
684enum Window4 { /* Window 4: Xcvr/media bits. */
685 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
686};
687enum Win4_Media_bits {
688 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
689 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
690 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
691 Media_LnkBeat = 0x0800,
692};
693enum Window7 { /* Window 7: Bus Master control. */
694 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
695 Wn7_MasterStatus = 12,
696};
697/* Boomerang bus master control registers. */
698enum MasterCtrl {
699 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
700 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
701};
702
703/* The Rx and Tx descriptor lists.
704 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
705 alignment contraint on tx_ring[] and rx_ring[]. */
706#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
707#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
708struct boom_rx_desc {
709 u32 next; /* Last entry points to 0. */
710 s32 status;
711 u32 addr; /* Up to 63 addr/len pairs possible. */
712 s32 length; /* Set LAST_FRAG to indicate last pair. */
713};
714/* Values for the Rx status entry. */
715enum rx_desc_status {
716 RxDComplete=0x00008000, RxDError=0x4000,
717 /* See boomerang_rx() for actual error bits */
718 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
719 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
720};
721
722#ifdef MAX_SKB_FRAGS
723#define DO_ZEROCOPY 1
724#else
725#define DO_ZEROCOPY 0
726#endif
727
728struct boom_tx_desc {
729 u32 next; /* Last entry points to 0. */
730 s32 status; /* bits 0:12 length, others see below. */
731#if DO_ZEROCOPY
732 struct {
733 u32 addr;
734 s32 length;
735 } frag[1+MAX_SKB_FRAGS];
736#else
737 u32 addr;
738 s32 length;
739#endif
740};
741
742/* Values for the Tx status entry. */
743enum tx_desc_status {
744 CRCDisable=0x2000, TxDComplete=0x8000,
745 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
746 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
747};
748
749/* Chip features we care about in vp->capabilities, read from the EEPROM. */
750enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
751
752struct vortex_extra_stats {
8d1d0340
SK		 753 unsigned long tx_deferred;
754 unsigned long tx_max_collisions;
755 unsigned long tx_multiple_collisions;
756 unsigned long tx_single_collisions;
757 unsigned long rx_bad_ssd;
1da177e4
LT		 758};
759
760struct vortex_private {
761 /* The Rx and Tx rings should be quad-word-aligned. */
762 struct boom_rx_desc* rx_ring;
763 struct boom_tx_desc* tx_ring;
764 dma_addr_t rx_ring_dma;
765 dma_addr_t tx_ring_dma;
766 /* The addresses of transmit- and receive-in-place skbuffs. */
767 struct sk_buff* rx_skbuff[RX_RING_SIZE];
768 struct sk_buff* tx_skbuff[TX_RING_SIZE];
769 unsigned int cur_rx, cur_tx; /* The next free ring entry */
770 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
771 struct net_device_stats stats; /* Generic stats */
772 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
773 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
774 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
775
776 /* PCI configuration space information. */
777 struct device *gendev;
62afe595
JL		 778 void __iomem *ioaddr; /* IO address space */
779 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 780
781 /* Some values here only for performance evaluation and path-coverage */
782 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
783 int card_idx;
784
785 /* The remainder are related to chip state, mostly media selection. */
786 struct timer_list timer; /* Media selection timer. */
787 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
788 int options; /* User-settable misc. driver options. */
789 unsigned int media_override:4, /* Passed-in media type. */
790 default_media:4, /* Read from the EEPROM/Wn3_Config. */
791 full_duplex:1, force_fd:1, autoselect:1,
792 bus_master:1, /* Vortex can only do a fragment bus-m. */
793 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
794 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
795 partner_flow_ctrl:1, /* Partner supports flow control */
796 has_nway:1,
797 enable_wol:1, /* Wake-on-LAN is enabled */
798 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
799 open:1,
800 medialock:1,
801 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
802 large_frames:1; /* accept large frames */
803 int drv_flags;
804 u16 status_enable;
805 u16 intr_enable;
806 u16 available_media; /* From Wn3_Options. */
807 u16 capabilities, info1, info2; /* Various, from EEPROM. */
808 u16 advertising; /* NWay media advertisement */
809 unsigned char phys[2]; /* MII device addresses. */
810 u16 deferred; /* Resend these interrupts when we
811 * bale from the ISR */
812 u16 io_size; /* Size of PCI region (for release_region) */
813 spinlock_t lock; /* Serialise access to device & its vortex_private */
814 struct mii_if_info mii; /* MII lib hooks/info */
815};
816
817#ifdef CONFIG_PCI
818#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
819#else
820#define DEVICE_PCI(dev) NULL
821#endif
822
823#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
824
825#ifdef CONFIG_EISA
826#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
827#else
828#define DEVICE_EISA(dev) NULL
829#endif
830
831#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
832
833/* The action to take with a media selection timer tick.
834 Note that we deviate from the 3Com order by checking 10base2 before AUI.
835 */
836enum xcvr_types {
837 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
838 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
839};
840
f71e1309 841static const struct media_table {
1da177e4
LT		 842 char *name;
843 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
844 mask:8, /* The transceiver-present bit in Wn3_Config.*/
845 next:8; /* The media type to try next. */
846 int wait; /* Time before we check media status. */
847} media_tbl[] = {
848 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
849 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
850 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
851 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
852 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
853 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
854 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
855 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
856 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
857 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
858 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
859};
860
861static struct {
862 const char str[ETH_GSTRING_LEN];
863} ethtool_stats_keys[] = {
864 { "tx_deferred" },
8d1d0340 865 { "tx_max_collisions" },
1da177e4 866 { "tx_multiple_collisions" },
8d1d0340 867 { "tx_single_collisions" },
1da177e4
LT		 868 { "rx_bad_ssd" },
869};
870
871/* number of ETHTOOL_GSTATS u64's */
8d1d0340 872#define VORTEX_NUM_STATS 5
1da177e4 873
62afe595 874static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4
LT		 875 int chip_idx, int card_idx);
876static void vortex_up(struct net_device *dev);
877static void vortex_down(struct net_device *dev, int final);
878static int vortex_open(struct net_device *dev);
62afe595 879static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 880static int mdio_read(struct net_device *dev, int phy_id, int location);
881static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
882static void vortex_timer(unsigned long arg);
883static void rx_oom_timer(unsigned long arg);
884static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
885static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
886static int vortex_rx(struct net_device *dev);
887static int boomerang_rx(struct net_device *dev);
888static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
889static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
890static int vortex_close(struct net_device *dev);
891static void dump_tx_ring(struct net_device *dev);
62afe595 892static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 893static struct net_device_stats *vortex_get_stats(struct net_device *dev);
894static void set_rx_mode(struct net_device *dev);
895#ifdef CONFIG_PCI
896static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
897#endif
898static void vortex_tx_timeout(struct net_device *dev);
899static void acpi_set_WOL(struct net_device *dev);
900static struct ethtool_ops vortex_ethtool_ops;
901static void set_8021q_mode(struct net_device *dev, int enable);
902
1da177e4
LT		 903/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
904/* Option count limit only -- unlimited interfaces are supported. */
905#define MAX_UNITS 8
9954ab7f
JL		 906static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
907static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
908static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
909static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
910static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 911static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 912static int global_options = -1;
913static int global_full_duplex = -1;
914static int global_enable_wol = -1;
900fd17d 915static int global_use_mmio = -1;
1da177e4 916
1da177e4
LT		 917/* Variables to work-around the Compaq PCI BIOS32 problem. */
918static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
919static struct net_device *compaq_net_device;
920
921static int vortex_cards_found;
922
923module_param(debug, int, 0);
924module_param(global_options, int, 0);
925module_param_array(options, int, NULL, 0);
926module_param(global_full_duplex, int, 0);
927module_param_array(full_duplex, int, NULL, 0);
928module_param_array(hw_checksums, int, NULL, 0);
929module_param_array(flow_ctrl, int, NULL, 0);
930module_param(global_enable_wol, int, 0);
931module_param_array(enable_wol, int, NULL, 0);
932module_param(rx_copybreak, int, 0);
933module_param(max_interrupt_work, int, 0);
934module_param(compaq_ioaddr, int, 0);
935module_param(compaq_irq, int, 0);
936module_param(compaq_device_id, int, 0);
937module_param(watchdog, int, 0);
900fd17d
JL		 938module_param(global_use_mmio, int, 0);
939module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 940MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
941MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
942MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
943MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 944MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 945MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
946MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
947MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 948MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 949MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
950MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
951MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
952MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
953MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
954MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 955MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
956MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 957
958#ifdef CONFIG_NET_POLL_CONTROLLER
959static void poll_vortex(struct net_device *dev)
960{
961 struct vortex_private *vp = netdev_priv(dev);
962 unsigned long flags;
963 local_save_flags(flags);
964 local_irq_disable();
965 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
966 local_irq_restore(flags);
967}
968#endif
969
970#ifdef CONFIG_PM
971
a880c4cd 972static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 973{
974 struct net_device *dev = pci_get_drvdata(pdev);
975
976 if (dev && dev->priv) {
977 if (netif_running(dev)) {
978 netif_device_detach(dev);
979 vortex_down(dev, 1);
980 }
5b039e68
RW		 981 pci_save_state(pdev);
982 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
983 free_irq(dev->irq, dev);
984 pci_disable_device(pdev);
985 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 986 }
987 return 0;
988}
989
a880c4cd 990static int vortex_resume(struct pci_dev *pdev)
1da177e4
LT		 991{
992 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 993 struct vortex_private *vp = netdev_priv(dev);
1da177e4 994
5b039e68
RW		 995 if (dev && vp) {
996 pci_set_power_state(pdev, PCI_D0);
997 pci_restore_state(pdev);
998 pci_enable_device(pdev);
999 pci_set_master(pdev);
1000 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1001 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev)) {
1002 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1003 pci_disable_device(pdev);
1004 return -EBUSY;
1005 }
1da177e4
LT		 1006 if (netif_running(dev)) {
1007 vortex_up(dev);
1008 netif_device_attach(dev);
1009 }
1010 }
1011 return 0;
1012}
1013
1014#endif /* CONFIG_PM */
1015
1016#ifdef CONFIG_EISA
1017static struct eisa_device_id vortex_eisa_ids[] = {
1018 { "TCM5920", CH_3C592 },
1019 { "TCM5970", CH_3C597 },
1020 { "" }
1021};
1022
a880c4cd
SK		 1023static int vortex_eisa_probe(struct device *device);
1024static int vortex_eisa_remove(struct device *device);
1da177e4
LT		 1025
1026static struct eisa_driver vortex_eisa_driver = {
1027 .id_table = vortex_eisa_ids,
1028 .driver = {
1029 .name = "3c59x",
1030 .probe = vortex_eisa_probe,
1031 .remove = vortex_eisa_remove
1032 }
1033};
1034
a880c4cd 1035static int vortex_eisa_probe(struct device *device)
1da177e4 1036{
62afe595 1037 void __iomem *ioaddr;
1da177e4
LT		 1038 struct eisa_device *edev;
1039
a880c4cd 1040 edev = to_eisa_device(device);
1da177e4 1041
62afe595 1042 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 1043 return -EBUSY;
1044
62afe595
JL		 1045 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
1046
1047 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 1048 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 1049 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 1050 return -ENODEV;
1051 }
1052
1053 vortex_cards_found++;
1054
1055 return 0;
1056}
1057
a880c4cd 1058static int vortex_eisa_remove(struct device *device)
1da177e4
LT		 1059{
1060 struct eisa_device *edev;
1061 struct net_device *dev;
1062 struct vortex_private *vp;
62afe595 1063 void __iomem *ioaddr;
1da177e4 1064
a880c4cd
SK		 1065 edev = to_eisa_device(device);
1066 dev = eisa_get_drvdata(edev);
1da177e4
LT		 1067
1068 if (!dev) {
1069 printk("vortex_eisa_remove called for Compaq device!\n");
1070 BUG();
1071 }
1072
1073 vp = netdev_priv(dev);
62afe595 1074 ioaddr = vp->ioaddr;
1da177e4 1075
a880c4cd
SK		 1076 unregister_netdev(dev);
1077 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
1078 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 1079
a880c4cd 1080 free_netdev(dev);
1da177e4
LT		 1081 return 0;
1082}
1083#endif
1084
1085/* returns count found (>= 0), or negative on error */
a880c4cd 1086static int __init vortex_eisa_init(void)
1da177e4
LT		 1087{
1088 int eisa_found = 0;
1089 int orig_cards_found = vortex_cards_found;
1090
1091#ifdef CONFIG_EISA
c2f6fabb
BH		 1092 int err;
1093
1094 err = eisa_driver_register (&vortex_eisa_driver);
1095 if (!err) {
1096 /*
1097 * Because of the way EISA bus is probed, we cannot assume
1098 * any device have been found when we exit from
1099 * eisa_driver_register (the bus root driver may not be
1100 * initialized yet). So we blindly assume something was
1101 * found, and let the sysfs magic happend...
1102 */
1103 eisa_found = 1;
1da177e4
LT		 1104 }
1105#endif
1106
1107 /* Special code to work-around the Compaq PCI BIOS32 problem. */
1108 if (compaq_ioaddr) {
62afe595
JL		 1109 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
1110 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 1111 }
1112
1113 return vortex_cards_found - orig_cards_found + eisa_found;
1114}
1115
1116/* returns count (>= 0), or negative on error */
a880c4cd 1117static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 1118 const struct pci_device_id *ent)
1119{
900fd17d
JL		 1120 int rc, unit, pci_bar;
1121 struct vortex_chip_info *vci;
1122 void __iomem *ioaddr;
1da177e4
LT		 1123
1124 /* wake up and enable device */
a880c4cd 1125 rc = pci_enable_device(pdev);
1da177e4
LT		 1126 if (rc < 0)
1127 goto out;
1128
900fd17d
JL		 1129 unit = vortex_cards_found;
1130
1131 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1132 /* Determine the default if the user didn't override us */
1133 vci = &vortex_info_tbl[ent->driver_data];
1134 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1135 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1136 pci_bar = use_mmio[unit] ? 1 : 0;
1137 else
1138 pci_bar = global_use_mmio ? 1 : 0;
1139
1140 ioaddr = pci_iomap(pdev, pci_bar, 0);
1141 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1142 ioaddr = pci_iomap(pdev, 0, 0);
1143
1144 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1145 ent->driver_data, unit);
1da177e4 1146 if (rc < 0) {
a880c4cd 1147 pci_disable_device(pdev);
1da177e4
LT		 1148 goto out;
1149 }
1150
1151 vortex_cards_found++;
1152
1153out:
1154 return rc;
1155}
1156
1157/*
1158 * Start up the PCI/EISA device which is described by *gendev.
1159 * Return 0 on success.
1160 *
1161 * NOTE: pdev can be NULL, for the case of a Compaq device
1162 */
1163static int __devinit vortex_probe1(struct device *gendev,
62afe595 1164 void __iomem *ioaddr, int irq,
1da177e4
LT		 1165 int chip_idx, int card_idx)
1166{
1167 struct vortex_private *vp;
1168 int option;
1169 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1170 int i, step;
1171 struct net_device *dev;
1172 static int printed_version;
1173 int retval, print_info;
1174 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1175 char *print_name = "3c59x";
1176 struct pci_dev *pdev = NULL;
1177 struct eisa_device *edev = NULL;
1178
1179 if (!printed_version) {
1180 printk (version);
1181 printed_version = 1;
1182 }
1183
1184 if (gendev) {
1185 if ((pdev = DEVICE_PCI(gendev))) {
1186 print_name = pci_name(pdev);
1187 }
1188
1189 if ((edev = DEVICE_EISA(gendev))) {
1190 print_name = edev->dev.bus_id;
1191 }
1192 }
1193
1194 dev = alloc_etherdev(sizeof(*vp));
1195 retval = -ENOMEM;
1196 if (!dev) {
1197 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1198 goto out;
1199 }
1200 SET_MODULE_OWNER(dev);
1201 SET_NETDEV_DEV(dev, gendev);
1202 vp = netdev_priv(dev);
1203
1204 option = global_options;
1205
1206 /* The lower four bits are the media type. */
1207 if (dev->mem_start) {
1208 /*
1209 * The 'options' param is passed in as the third arg to the
1210 * LILO 'ether=' argument for non-modular use
1211 */
1212 option = dev->mem_start;
1213 }
1214 else if (card_idx < MAX_UNITS) {
1215 if (options[card_idx] >= 0)
1216 option = options[card_idx];
1217 }
1218
1219 if (option > 0) {
1220 if (option & 0x8000)
1221 vortex_debug = 7;
1222 if (option & 0x4000)
1223 vortex_debug = 2;
1224 if (option & 0x0400)
1225 vp->enable_wol = 1;
1226 }
1227
1228 print_info = (vortex_debug > 1);
1229 if (print_info)
1230 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1231
61238602 1232 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1233 print_name,
1234 pdev ? "PCI" : "EISA",
1235 vci->name,
1236 ioaddr);
1237
62afe595 1238 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1239 dev->irq = irq;
1240 dev->mtu = mtu;
62afe595 1241 vp->ioaddr = ioaddr;
1da177e4
LT		 1242 vp->large_frames = mtu > 1500;
1243 vp->drv_flags = vci->drv_flags;
1244 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1245 vp->io_size = vci->io_size;
1246 vp->card_idx = card_idx;
1247
1248 /* module list only for Compaq device */
1249 if (gendev == NULL) {
1250 compaq_net_device = dev;
1251 }
1252
1253 /* PCI-only startup logic */
1254 if (pdev) {
1255 /* EISA resources already marked, so only PCI needs to do this here */
1256 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1257 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1258 vp->must_free_region = 1;
1259
1260 /* enable bus-mastering if necessary */
1261 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1262 pci_set_master(pdev);
1da177e4
LT		 1263
1264 if (vci->drv_flags & IS_VORTEX) {
1265 u8 pci_latency;
1266 u8 new_latency = 248;
1267
1268 /* Check the PCI latency value. On the 3c590 series the latency timer
1269 must be set to the maximum value to avoid data corruption that occurs
1270 when the timer expires during a transfer. This bug exists the Vortex
1271 chip only. */
1272 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1273 if (pci_latency < new_latency) {
1274 printk(KERN_INFO "%s: Overriding PCI latency"
1275 " timer (CFLT) setting of %d, new value is %d.\n",
1276 print_name, pci_latency, new_latency);
1277 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1278 }
1279 }
1280 }
1281
1282 spin_lock_init(&vp->lock);
1283 vp->gendev = gendev;
1284 vp->mii.dev = dev;
1285 vp->mii.mdio_read = mdio_read;
1286 vp->mii.mdio_write = mdio_write;
1287 vp->mii.phy_id_mask = 0x1f;
1288 vp->mii.reg_num_mask = 0x1f;
1289
1290 /* Makes sure rings are at least 16 byte aligned. */
1291 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1292 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1293 &vp->rx_ring_dma);
1294 retval = -ENOMEM;
1295 if (vp->rx_ring == 0)
1296 goto free_region;
1297
1298 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1299 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1300
1301 /* if we are a PCI driver, we store info in pdev->driver_data
1302 * instead of a module list */
1303 if (pdev)
1304 pci_set_drvdata(pdev, dev);
1305 if (edev)
a880c4cd 1306 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1307
1308 vp->media_override = 7;
1309 if (option >= 0) {
1310 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1311 if (vp->media_override != 7)
1312 vp->medialock = 1;
1313 vp->full_duplex = (option & 0x200) ? 1 : 0;
1314 vp->bus_master = (option & 16) ? 1 : 0;
1315 }
1316
1317 if (global_full_duplex > 0)
1318 vp->full_duplex = 1;
1319 if (global_enable_wol > 0)
1320 vp->enable_wol = 1;
1321
1322 if (card_idx < MAX_UNITS) {
1323 if (full_duplex[card_idx] > 0)
1324 vp->full_duplex = 1;
1325 if (flow_ctrl[card_idx] > 0)
1326 vp->flow_ctrl = 1;
1327 if (enable_wol[card_idx] > 0)
1328 vp->enable_wol = 1;
1329 }
1330
125d5ce8 1331 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1332 vp->options = option;
1333 /* Read the station address from the EEPROM. */
1334 EL3WINDOW(0);
1335 {
1336 int base;
1337
1338 if (vci->drv_flags & EEPROM_8BIT)
1339 base = 0x230;
1340 else if (vci->drv_flags & EEPROM_OFFSET)
1341 base = EEPROM_Read + 0x30;
1342 else
1343 base = EEPROM_Read;
1344
1345 for (i = 0; i < 0x40; i++) {
1346 int timer;
62afe595 1347 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1348 /* Pause for at least 162 us. for the read to take place. */
1349 for (timer = 10; timer >= 0; timer--) {
1350 udelay(162);
62afe595 1351 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1352 break;
1353 }
62afe595 1354 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1355 }
1356 }
1357 for (i = 0; i < 0x18; i++)
1358 checksum ^= eeprom[i];
1359 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1360 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1361 while (i < 0x21)
1362 checksum ^= eeprom[i++];
1363 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1364 }
1365 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1366 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1367 for (i = 0; i < 3; i++)
1368 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1369 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1370 if (print_info) {
1371 for (i = 0; i < 6; i++)
1372 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1373 }
1374 /* Unfortunately an all zero eeprom passes the checksum and this
1375 gets found in the wild in failure cases. Crypto is hard 8) */
1376 if (!is_valid_ether_addr(dev->dev_addr)) {
1377 retval = -EINVAL;
1378 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1379 goto free_ring; /* With every pack */
1380 }
1381 EL3WINDOW(2);
1382 for (i = 0; i < 6; i++)
62afe595 1383 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4
LT		 1384
1385#ifdef __sparc__
1386 if (print_info)
1387 printk(", IRQ %s\n", __irq_itoa(dev->irq));
1388#else
1389 if (print_info)
1390 printk(", IRQ %d\n", dev->irq);
1391 /* Tell them about an invalid IRQ. */
1392 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1393 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1394 dev->irq);
1395#endif
1396
1397 EL3WINDOW(4);
62afe595 1398 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1399 if (print_info) {
1400 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1401 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1402 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1403 }
1404
1405
1406 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1407 unsigned short n;
1408
62afe595
JL		 1409 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1410 if (!vp->cb_fn_base) {
1da177e4 1411 retval = -ENOMEM;
62afe595 1412 goto free_ring;
1da177e4 1413 }
62afe595 1414
1da177e4
LT		 1415 if (print_info) {
1416 printk(KERN_INFO "%s: CardBus functions mapped %8.8lx->%p\n",
62afe595
JL		 1417 print_name, pci_resource_start(pdev, 2),
1418 vp->cb_fn_base);
1da177e4
LT		 1419 }
1420 EL3WINDOW(2);
1421
62afe595 1422 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1423 if (vp->drv_flags & INVERT_LED_PWR)
1424 n |= 0x10;
1425 if (vp->drv_flags & INVERT_MII_PWR)
1426 n |= 0x4000;
62afe595 1427 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1428 if (vp->drv_flags & WNO_XCVR_PWR) {
1429 EL3WINDOW(0);
62afe595 1430 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1431 }
1432 }
1433
1434 /* Extract our information from the EEPROM data. */
1435 vp->info1 = eeprom[13];
1436 vp->info2 = eeprom[15];
1437 vp->capabilities = eeprom[16];
1438
1439 if (vp->info1 & 0x8000) {
1440 vp->full_duplex = 1;
1441 if (print_info)
1442 printk(KERN_INFO "Full duplex capable\n");
1443 }
1444
1445 {
f71e1309 1446 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1447 unsigned int config;
1448 EL3WINDOW(3);
62afe595 1449 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1450 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1451 vp->available_media = 0x40;
62afe595 1452 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1453 if (print_info) {
1454 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1455 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1456 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1457 8 << RAM_SIZE(config),
1458 RAM_WIDTH(config) ? "word" : "byte",
1459 ram_split[RAM_SPLIT(config)],
1460 AUTOSELECT(config) ? "autoselect/" : "",
1461 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1462 media_tbl[XCVR(config)].name);
1463 }
1464 vp->default_media = XCVR(config);
1465 if (vp->default_media == XCVR_NWAY)
1466 vp->has_nway = 1;
1467 vp->autoselect = AUTOSELECT(config);
1468 }
1469
1470 if (vp->media_override != 7) {
1471 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1472 print_name, vp->media_override,
1473 media_tbl[vp->media_override].name);
1474 dev->if_port = vp->media_override;
1475 } else
1476 dev->if_port = vp->default_media;
1477
1478 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1479 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1480 int phy, phy_idx = 0;
1481 EL3WINDOW(4);
1482 mii_preamble_required++;
1483 if (vp->drv_flags & EXTRA_PREAMBLE)
1484 mii_preamble_required++;
1485 mdio_sync(ioaddr, 32);
106427e6 1486 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1487 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1488 int mii_status, phyx;
1489
1490 /*
1491 * For the 3c905CX we look at index 24 first, because it bogusly
1492 * reports an external PHY at all indices
1493 */
1494 if (phy == 0)
1495 phyx = 24;
1496 else if (phy <= 24)
1497 phyx = phy - 1;
1498 else
1499 phyx = phy;
106427e6 1500 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1501 if (mii_status && mii_status != 0xffff) {
1502 vp->phys[phy_idx++] = phyx;
1503 if (print_info) {
1504 printk(KERN_INFO " MII transceiver found at address %d,"
1505 " status %4x.\n", phyx, mii_status);
1506 }
1507 if ((mii_status & 0x0040) == 0)
1508 mii_preamble_required++;
1509 }
1510 }
1511 mii_preamble_required--;
1512 if (phy_idx == 0) {
1513 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1514 vp->phys[0] = 24;
1515 } else {
106427e6 1516 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1517 if (vp->full_duplex) {
1518 /* Only advertise the FD media types. */
1519 vp->advertising &= ~0x02A0;
1520 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1521 }
1522 }
1523 vp->mii.phy_id = vp->phys[0];
1524 }
1525
1526 if (vp->capabilities & CapBusMaster) {
1527 vp->full_bus_master_tx = 1;
1528 if (print_info) {
1529 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1530 (vp->info2 & 1) ? "early" : "whole-frame" );
1531 }
1532 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1533 vp->bus_master = 0; /* AKPM: vortex only */
1534 }
1535
1536 /* The 3c59x-specific entries in the device structure. */
1537 dev->open = vortex_open;
1538 if (vp->full_bus_master_tx) {
1539 dev->hard_start_xmit = boomerang_start_xmit;
1540 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1541 if (card_idx < MAX_UNITS &&
1542 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1543 hw_checksums[card_idx] == 1)) {
d311b0d3 1544 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4
LT		 1545 }
1546 } else {
1547 dev->hard_start_xmit = vortex_start_xmit;
1548 }
1549
1550 if (print_info) {
1551 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1552 print_name,
1553 (dev->features & NETIF_F_SG) ? "en":"dis",
1554 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1555 }
1556
1557 dev->stop = vortex_close;
1558 dev->get_stats = vortex_get_stats;
1559#ifdef CONFIG_PCI
1560 dev->do_ioctl = vortex_ioctl;
1561#endif
1562 dev->ethtool_ops = &vortex_ethtool_ops;
1563 dev->set_multicast_list = set_rx_mode;
1564 dev->tx_timeout = vortex_tx_timeout;
1565 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1566#ifdef CONFIG_NET_POLL_CONTROLLER
1567 dev->poll_controller = poll_vortex;
1568#endif
1569 if (pdev) {
1570 vp->pm_state_valid = 1;
1571 pci_save_state(VORTEX_PCI(vp));
1572 acpi_set_WOL(dev);
1573 }
1574 retval = register_netdev(dev);
1575 if (retval == 0)
1576 return 0;
1577
1578free_ring:
1579 pci_free_consistent(pdev,
1580 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1581 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1582 vp->rx_ring,
1583 vp->rx_ring_dma);
1584free_region:
1585 if (vp->must_free_region)
62afe595 1586 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1587 free_netdev(dev);
1588 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1589out:
1590 return retval;
1591}
1592
1593static void
1594issue_and_wait(struct net_device *dev, int cmd)
1595{
62afe595
JL		 1596 struct vortex_private *vp = netdev_priv(dev);
1597 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1598 int i;
1599
62afe595 1600 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1601 for (i = 0; i < 2000; i++) {
62afe595 1602 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1603 return;
1604 }
1605
1606 /* OK, that didn't work. Do it the slow way. One second */
1607 for (i = 0; i < 100000; i++) {
62afe595 1608 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1609 if (vortex_debug > 1)
1610 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1611 dev->name, cmd, i * 10);
1612 return;
1613 }
1614 udelay(10);
1615 }
1616 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1617 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1618}
1619
125d5ce8
SK		 1620static void
1621vortex_set_duplex(struct net_device *dev)
1622{
1623 struct vortex_private *vp = netdev_priv(dev);
1624 void __iomem *ioaddr = vp->ioaddr;
1625
1626 printk(KERN_INFO "%s: setting %s-duplex.\n",
1627 dev->name, (vp->full_duplex) ? "full" : "half");
1628
1629 EL3WINDOW(3);
1630 /* Set the full-duplex bit. */
1631 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1632 (vp->large_frames ? 0x40 : 0) |
1633 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1634 0x100 : 0),
1635 ioaddr + Wn3_MAC_Ctrl);
1636
1637 issue_and_wait(dev, TxReset);
1638 /*
1639 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1640 */
1641 issue_and_wait(dev, RxReset|0x04);
1642}
1643
1644static void vortex_check_media(struct net_device *dev, unsigned int init)
1645{
1646 struct vortex_private *vp = netdev_priv(dev);
1647 unsigned int ok_to_print = 0;
1648
1649 if (vortex_debug > 3)
1650 ok_to_print = 1;
1651
1652 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1653 vp->full_duplex = vp->mii.full_duplex;
1654 vortex_set_duplex(dev);
1655 } else if (init) {
1656 vortex_set_duplex(dev);
1657 }
1658}
1659
1da177e4
LT		 1660static void
1661vortex_up(struct net_device *dev)
1662{
1da177e4 1663 struct vortex_private *vp = netdev_priv(dev);
62afe595 1664 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1665 unsigned int config;
1666 int i;
1667
1668 if (VORTEX_PCI(vp)) {
1669 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1670 if (vp->pm_state_valid)
1671 pci_restore_state(VORTEX_PCI(vp));
1da177e4
LT		 1672 pci_enable_device(VORTEX_PCI(vp));
1673 }
1674
1675 /* Before initializing select the active media port. */
1676 EL3WINDOW(3);
62afe595 1677 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1678
1679 if (vp->media_override != 7) {
1680 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1681 dev->name, vp->media_override,
1682 media_tbl[vp->media_override].name);
1683 dev->if_port = vp->media_override;
1684 } else if (vp->autoselect) {
1685 if (vp->has_nway) {
1686 if (vortex_debug > 1)
1687 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1688 dev->name, dev->if_port);
1689 dev->if_port = XCVR_NWAY;
1690 } else {
1691 /* Find first available media type, starting with 100baseTx. */
1692 dev->if_port = XCVR_100baseTx;
1693 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1694 dev->if_port = media_tbl[dev->if_port].next;
1695 if (vortex_debug > 1)
1696 printk(KERN_INFO "%s: first available media type: %s\n",
1697 dev->name, media_tbl[dev->if_port].name);
1698 }
1699 } else {
1700 dev->if_port = vp->default_media;
1701 if (vortex_debug > 1)
1702 printk(KERN_INFO "%s: using default media %s\n",
1703 dev->name, media_tbl[dev->if_port].name);
1704 }
1705
1706 init_timer(&vp->timer);
1707 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1708 vp->timer.data = (unsigned long)dev;
1709 vp->timer.function = vortex_timer; /* timer handler */
1710 add_timer(&vp->timer);
1711
1712 init_timer(&vp->rx_oom_timer);
1713 vp->rx_oom_timer.data = (unsigned long)dev;
1714 vp->rx_oom_timer.function = rx_oom_timer;
1715
1716 if (vortex_debug > 1)
1717 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1718 dev->name, media_tbl[dev->if_port].name);
1719
125d5ce8 1720 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1721 config = BFINS(config, dev->if_port, 20, 4);
1722 if (vortex_debug > 6)
1723 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1724 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1725
125d5ce8 1726 netif_carrier_off(dev);
1da177e4 1727 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1728 EL3WINDOW(4);
125d5ce8 1729 vortex_check_media(dev, 1);
1da177e4 1730 }
125d5ce8
SK		 1731 else
1732 vortex_set_duplex(dev);
1da177e4 1733
1da177e4 1734
62afe595 1735 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1736
1737 if (vortex_debug > 1) {
1738 EL3WINDOW(4);
1739 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1740 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1741 }
1742
1743 /* Set the station address and mask in window 2 each time opened. */
1744 EL3WINDOW(2);
1745 for (i = 0; i < 6; i++)
62afe595 1746 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1747 for (; i < 12; i+=2)
62afe595 1748 iowrite16(0, ioaddr + i);
1da177e4
LT		 1749
1750 if (vp->cb_fn_base) {
62afe595 1751 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1752 if (vp->drv_flags & INVERT_LED_PWR)
1753 n |= 0x10;
1754 if (vp->drv_flags & INVERT_MII_PWR)
1755 n |= 0x4000;
62afe595 1756 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1757 }
1758
1759 if (dev->if_port == XCVR_10base2)
1760 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1761 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1762 if (dev->if_port != XCVR_NWAY) {
1763 EL3WINDOW(4);
62afe595 1764 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1765 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1766 }
1767
1768 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1769 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1770 EL3WINDOW(6);
1771 for (i = 0; i < 10; i++)
62afe595
JL		 1772 ioread8(ioaddr + i);
1773 ioread16(ioaddr + 10);
1774 ioread16(ioaddr + 12);
1da177e4
LT		 1775 /* New: On the Vortex we must also clear the BadSSD counter. */
1776 EL3WINDOW(4);
62afe595 1777 ioread8(ioaddr + 12);
1da177e4 1778 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1779 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1780
1781 /* Switch to register set 7 for normal use. */
1782 EL3WINDOW(7);
1783
1784 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1785 vp->cur_rx = vp->dirty_rx = 0;
1786 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1787 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1788 iowrite32(0x0020, ioaddr + PktStatus);
1789 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1790 }
1791 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1792 vp->cur_tx = vp->dirty_tx = 0;
1793 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1794 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1795 /* Clear the Rx, Tx rings. */
1796 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1797 vp->rx_ring[i].status = 0;
1798 for (i = 0; i < TX_RING_SIZE; i++)
1799 vp->tx_skbuff[i] = NULL;
62afe595 1800 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1801 }
1802 /* Set receiver mode: presumably accept b-case and phys addr only. */
1803 set_rx_mode(dev);
1804 /* enable 802.1q tagged frames */
1805 set_8021q_mode(dev, 1);
62afe595 1806 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1807
62afe595
JL		 1808 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1809 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1810 /* Allow status bits to be seen. */
1811 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1812 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1813 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1814 (vp->bus_master ? DMADone : 0);
1815 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1816 (vp->full_bus_master_rx ? 0 : RxComplete) |
1817 StatsFull | HostError | TxComplete | IntReq
1818 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1819 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1820 /* Ack all pending events, and set active indicator mask. */
62afe595 1821 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1822 ioaddr + EL3_CMD);
62afe595 1823 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1824 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1825 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4
LT		 1826 netif_start_queue (dev);
1827}
1828
1829static int
1830vortex_open(struct net_device *dev)
1831{
1832 struct vortex_private *vp = netdev_priv(dev);
1833 int i;
1834 int retval;
1835
1836 /* Use the now-standard shared IRQ implementation. */
1837 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1838 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev))) {
1839 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1840 goto out;
1841 }
1842
1843 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1844 if (vortex_debug > 2)
1845 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1846 for (i = 0; i < RX_RING_SIZE; i++) {
1847 struct sk_buff *skb;
1848 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1849 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1850 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1851 skb = dev_alloc_skb(PKT_BUF_SZ);
1852 vp->rx_skbuff[i] = skb;
1853 if (skb == NULL)
1854 break; /* Bad news! */
1855 skb->dev = dev; /* Mark as being used by this device. */
1856 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1857 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1858 }
1859 if (i != RX_RING_SIZE) {
1860 int j;
1861 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1862 for (j = 0; j < i; j++) {
1863 if (vp->rx_skbuff[j]) {
1864 dev_kfree_skb(vp->rx_skbuff[j]);
1865 vp->rx_skbuff[j] = NULL;
1866 }
1867 }
1868 retval = -ENOMEM;
1869 goto out_free_irq;
1870 }
1871 /* Wrap the ring. */
1872 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1873 }
1874
1875 vortex_up(dev);
1876 return 0;
1877
1878out_free_irq:
1879 free_irq(dev->irq, dev);
1880out:
1881 if (vortex_debug > 1)
1882 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1883 return retval;
1884}
1885
1886static void
1887vortex_timer(unsigned long data)
1888{
1889 struct net_device *dev = (struct net_device *)data;
1890 struct vortex_private *vp = netdev_priv(dev);
62afe595 1891 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1892 int next_tick = 60*HZ;
1893 int ok = 0;
125d5ce8 1894 int media_status, old_window;
1da177e4
LT		 1895
1896 if (vortex_debug > 2) {
1897 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1898 dev->name, media_tbl[dev->if_port].name);
1899 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1900 }
1901
1da177e4 1902 disable_irq(dev->irq);
62afe595 1903 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1904 EL3WINDOW(4);
62afe595 1905 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1906 switch (dev->if_port) {
1907 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1908 if (media_status & Media_LnkBeat) {
1909 netif_carrier_on(dev);
1910 ok = 1;
1911 if (vortex_debug > 1)
1912 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1913 dev->name, media_tbl[dev->if_port].name, media_status);
1914 } else {
1915 netif_carrier_off(dev);
1916 if (vortex_debug > 1) {
1917 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1918 dev->name, media_tbl[dev->if_port].name, media_status);
1919 }
1920 }
1921 break;
1922 case XCVR_MII: case XCVR_NWAY:
1923 {
1da177e4 1924 ok = 1;
125d5ce8
SK		 1925 spin_lock_bh(&vp->lock);
1926 vortex_check_media(dev, 0);
1da177e4
LT		 1927 spin_unlock_bh(&vp->lock);
1928 }
1929 break;
1930 default: /* Other media types handled by Tx timeouts. */
1931 if (vortex_debug > 1)
1932 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1933 dev->name, media_tbl[dev->if_port].name, media_status);
1934 ok = 1;
1935 }
b4ff6450
SK		 1936
1937 if (!netif_carrier_ok(dev))
1938 next_tick = 5*HZ;
1939
e94d10eb
SK		 1940 if (vp->medialock)
1941 goto leave_media_alone;
1942
a880c4cd 1943 if (!ok) {
1da177e4
LT		 1944 unsigned int config;
1945
1946 do {
1947 dev->if_port = media_tbl[dev->if_port].next;
1948 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1949 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1950 dev->if_port = vp->default_media;
1951 if (vortex_debug > 1)
1952 printk(KERN_DEBUG "%s: Media selection failing, using default "
1953 "%s port.\n",
1954 dev->name, media_tbl[dev->if_port].name);
1955 } else {
1956 if (vortex_debug > 1)
1957 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1958 "%s port.\n",
1959 dev->name, media_tbl[dev->if_port].name);
1960 next_tick = media_tbl[dev->if_port].wait;
1961 }
62afe595 1962 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1963 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1964
1965 EL3WINDOW(3);
62afe595 1966 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1967 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1968 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1969
62afe595 1970 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1971 ioaddr + EL3_CMD);
1972 if (vortex_debug > 1)
1973 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1974 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1975 }
1da177e4
LT		 1976
1977leave_media_alone:
1978 if (vortex_debug > 2)
1979 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1980 dev->name, media_tbl[dev->if_port].name);
1981
e94d10eb
SK		 1982 EL3WINDOW(old_window);
1983 enable_irq(dev->irq);
1da177e4
LT		 1984 mod_timer(&vp->timer, RUN_AT(next_tick));
1985 if (vp->deferred)
62afe595 1986 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1987 return;
1988}
1989
1990static void vortex_tx_timeout(struct net_device *dev)
1991{
1992 struct vortex_private *vp = netdev_priv(dev);
62afe595 1993 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1994
1995 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1996 dev->name, ioread8(ioaddr + TxStatus),
1997 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1998 EL3WINDOW(4);
1999 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 2000 ioread16(ioaddr + Wn4_NetDiag),
2001 ioread16(ioaddr + Wn4_Media),
2002 ioread32(ioaddr + PktStatus),
2003 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 2004 /* Slight code bloat to be user friendly. */
62afe595 2005 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 2006 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
2007 " network cable problem?\n", dev->name);
62afe595 2008 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 2009 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
2010 " IRQ blocked by another device?\n", dev->name);
2011 /* Bad idea here.. but we might as well handle a few events. */
2012 {
2013 /*
2014 * Block interrupts because vortex_interrupt does a bare spin_lock()
2015 */
2016 unsigned long flags;
2017 local_irq_save(flags);
2018 if (vp->full_bus_master_tx)
2019 boomerang_interrupt(dev->irq, dev, NULL);
2020 else
2021 vortex_interrupt(dev->irq, dev, NULL);
2022 local_irq_restore(flags);
2023 }
2024 }
2025
2026 if (vortex_debug > 0)
2027 dump_tx_ring(dev);
2028
2029 issue_and_wait(dev, TxReset);
2030
2031 vp->stats.tx_errors++;
2032 if (vp->full_bus_master_tx) {
2033 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 2034 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
2035 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 2036 ioaddr + DownListPtr);
2037 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
2038 netif_wake_queue (dev);
2039 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 2040 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
2041 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2042 } else {
2043 vp->stats.tx_dropped++;
2044 netif_wake_queue(dev);
2045 }
2046
2047 /* Issue Tx Enable */
62afe595 2048 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2049 dev->trans_start = jiffies;
2050
2051 /* Switch to register set 7 for normal use. */
2052 EL3WINDOW(7);
2053}
2054
2055/*
2056 * Handle uncommon interrupt sources. This is a separate routine to minimize
2057 * the cache impact.
2058 */
2059static void
2060vortex_error(struct net_device *dev, int status)
2061{
2062 struct vortex_private *vp = netdev_priv(dev);
62afe595 2063 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2064 int do_tx_reset = 0, reset_mask = 0;
2065 unsigned char tx_status = 0;
2066
2067 if (vortex_debug > 2) {
2068 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
2069 }
2070
2071 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 2072 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 2073 /* Presumably a tx-timeout. We must merely re-enable. */
2074 if (vortex_debug > 2
2075 || (tx_status != 0x88 && vortex_debug > 0)) {
2076 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
2077 dev->name, tx_status);
2078 if (tx_status == 0x82) {
2079 printk(KERN_ERR "Probably a duplex mismatch. See "
2080 "Documentation/networking/vortex.txt\n");
2081 }
2082 dump_tx_ring(dev);
2083 }
2084 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
2085 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
62afe595 2086 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 2087 if (tx_status & 0x30) { /* txJabber or txUnderrun */
2088 do_tx_reset = 1;
8d1d0340
SK		 2089 } else if (tx_status & 0x08) { /* maxCollisions */
2090 vp->xstats.tx_max_collisions++;
2091 if (vp->drv_flags & MAX_COLLISION_RESET) {
2092 do_tx_reset = 1;
2093 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
2094 }
1da177e4 2095 } else { /* Merely re-enable the transmitter. */
62afe595 2096 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2097 }
2098 }
2099
2100 if (status & RxEarly) { /* Rx early is unused. */
2101 vortex_rx(dev);
62afe595 2102 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 2103 }
2104 if (status & StatsFull) { /* Empty statistics. */
2105 static int DoneDidThat;
2106 if (vortex_debug > 4)
2107 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
2108 update_stats(ioaddr, dev);
2109 /* HACK: Disable statistics as an interrupt source. */
2110 /* This occurs when we have the wrong media type! */
2111 if (DoneDidThat == 0 &&
62afe595 2112 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 2113 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
2114 "stats as an interrupt source.\n", dev->name);
2115 EL3WINDOW(5);
62afe595 2116 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 2117 vp->intr_enable &= ~StatsFull;
2118 EL3WINDOW(7);
2119 DoneDidThat++;
2120 }
2121 }
2122 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 2123 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2124 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 2125 }
2126 if (status & HostError) {
2127 u16 fifo_diag;
2128 EL3WINDOW(4);
62afe595 2129 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 2130 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
2131 dev->name, fifo_diag);
2132 /* Adapter failure requires Tx/Rx reset and reinit. */
2133 if (vp->full_bus_master_tx) {
62afe595 2134 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2135 /* 0x80000000 PCI master abort. */
2136 /* 0x40000000 PCI target abort. */
2137 if (vortex_debug)
2138 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2139
2140 /* In this case, blow the card away */
2141 /* Must not enter D3 or we can't legally issue the reset! */
2142 vortex_down(dev, 0);
2143 issue_and_wait(dev, TotalReset | 0xff);
2144 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2145 } else if (fifo_diag & 0x0400)
2146 do_tx_reset = 1;
2147 if (fifo_diag & 0x3000) {
2148 /* Reset Rx fifo and upload logic */
2149 issue_and_wait(dev, RxReset|0x07);
2150 /* Set the Rx filter to the current state. */
2151 set_rx_mode(dev);
2152 /* enable 802.1q VLAN tagged frames */
2153 set_8021q_mode(dev, 1);
62afe595
JL		 2154 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2155 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2156 }
2157 }
2158
2159 if (do_tx_reset) {
2160 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2161 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2162 if (!vp->full_bus_master_tx)
2163 netif_wake_queue(dev);
2164 }
2165}
2166
2167static int
2168vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2169{
2170 struct vortex_private *vp = netdev_priv(dev);
62afe595 2171 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2172
2173 /* Put out the doubleword header... */
62afe595 2174 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2175 if (vp->bus_master) {
2176 /* Set the bus-master controller to transfer the packet. */
2177 int len = (skb->len + 3) & ~3;
a880c4cd 2178 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2179 ioaddr + Wn7_MasterAddr);
62afe595 2180 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2181 vp->tx_skb = skb;
62afe595 2182 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2183 /* netif_wake_queue() will be called at the DMADone interrupt. */
2184 } else {
2185 /* ... and the packet rounded to a doubleword. */
62afe595 2186 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2187 dev_kfree_skb (skb);
62afe595 2188 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2189 netif_start_queue (dev); /* AKPM: redundant? */
2190 } else {
2191 /* Interrupt us when the FIFO has room for max-sized packet. */
2192 netif_stop_queue(dev);
62afe595 2193 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2194 }
2195 }
2196
2197 dev->trans_start = jiffies;
2198
2199 /* Clear the Tx status stack. */
2200 {
2201 int tx_status;
2202 int i = 32;
2203
62afe595 2204 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2205 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2206 if (vortex_debug > 2)
2207 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2208 dev->name, tx_status);
2209 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2210 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2211 if (tx_status & 0x30) {
2212 issue_and_wait(dev, TxReset);
2213 }
62afe595 2214 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2215 }
62afe595 2216 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2217 }
2218 }
2219 return 0;
2220}
2221
2222static int
2223boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2224{
2225 struct vortex_private *vp = netdev_priv(dev);
62afe595 2226 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2227 /* Calculate the next Tx descriptor entry. */
2228 int entry = vp->cur_tx % TX_RING_SIZE;
2229 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2230 unsigned long flags;
2231
2232 if (vortex_debug > 6) {
2233 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2234 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2235 dev->name, vp->cur_tx);
1da177e4
LT		 2236 }
2237
2238 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2239 if (vortex_debug > 0)
2240 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2241 dev->name);
2242 netif_stop_queue(dev);
2243 return 1;
2244 }
2245
2246 vp->tx_skbuff[entry] = skb;
2247
2248 vp->tx_ring[entry].next = 0;
2249#if DO_ZEROCOPY
2250 if (skb->ip_summed != CHECKSUM_HW)
2251 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2252 else
2253 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2254
2255 if (!skb_shinfo(skb)->nr_frags) {
2256 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2257 skb->len, PCI_DMA_TODEVICE));
2258 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2259 } else {
2260 int i;
2261
2262 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2263 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2264 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2265
2266 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2267 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2268
2269 vp->tx_ring[entry].frag[i+1].addr =
2270 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2271 (void*)page_address(frag->page) + frag->page_offset,
2272 frag->size, PCI_DMA_TODEVICE));
2273
2274 if (i == skb_shinfo(skb)->nr_frags-1)
2275 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2276 else
2277 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2278 }
2279 }
2280#else
2281 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2282 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2283 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2284#endif
2285
2286 spin_lock_irqsave(&vp->lock, flags);
2287 /* Wait for the stall to complete. */
2288 issue_and_wait(dev, DownStall);
2289 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2290 if (ioread32(ioaddr + DownListPtr) == 0) {
2291 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2292 vp->queued_packet++;
2293 }
2294
2295 vp->cur_tx++;
2296 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2297 netif_stop_queue (dev);
2298 } else { /* Clear previous interrupt enable. */
2299#if defined(tx_interrupt_mitigation)
2300 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2301 * were selected, this would corrupt DN_COMPLETE. No?
2302 */
2303 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2304#endif
2305 }
62afe595 2306 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2307 spin_unlock_irqrestore(&vp->lock, flags);
2308 dev->trans_start = jiffies;
2309 return 0;
2310}
2311
2312/* The interrupt handler does all of the Rx thread work and cleans up
2313 after the Tx thread. */
2314
2315/*
2316 * This is the ISR for the vortex series chips.
2317 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2318 */
2319
2320static irqreturn_t
2321vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2322{
2323 struct net_device *dev = dev_id;
2324 struct vortex_private *vp = netdev_priv(dev);
62afe595 2325 void __iomem *ioaddr;
1da177e4
LT		 2326 int status;
2327 int work_done = max_interrupt_work;
2328 int handled = 0;
2329
62afe595 2330 ioaddr = vp->ioaddr;
1da177e4
LT		 2331 spin_lock(&vp->lock);
2332
62afe595 2333 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2334
2335 if (vortex_debug > 6)
2336 printk("vortex_interrupt(). status=0x%4x\n", status);
2337
2338 if ((status & IntLatch) == 0)
2339 goto handler_exit; /* No interrupt: shared IRQs cause this */
2340 handled = 1;
2341
2342 if (status & IntReq) {
2343 status |= vp->deferred;
2344 vp->deferred = 0;
2345 }
2346
2347 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2348 goto handler_exit;
2349
2350 if (vortex_debug > 4)
2351 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2352 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2353
2354 do {
2355 if (vortex_debug > 5)
2356 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2357 dev->name, status);
2358 if (status & RxComplete)
2359 vortex_rx(dev);
2360
2361 if (status & TxAvailable) {
2362 if (vortex_debug > 5)
2363 printk(KERN_DEBUG " TX room bit was handled.\n");
2364 /* There's room in the FIFO for a full-sized packet. */
62afe595 2365 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2366 netif_wake_queue (dev);
2367 }
2368
2369 if (status & DMADone) {
62afe595
JL		 2370 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2371 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2372 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2373 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2374 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2375 /*
2376 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2377 * insufficient FIFO room, the TxAvailable test will succeed and call
2378 * netif_wake_queue()
2379 */
2380 netif_wake_queue(dev);
2381 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2382 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2383 netif_stop_queue(dev);
2384 }
2385 }
2386 }
2387 /* Check for all uncommon interrupts at once. */
2388 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2389 if (status == 0xffff)
2390 break;
2391 vortex_error(dev, status);
2392 }
2393
2394 if (--work_done < 0) {
2395 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2396 "%4.4x.\n", dev->name, status);
2397 /* Disable all pending interrupts. */
2398 do {
2399 vp->deferred |= status;
62afe595 2400 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2401 ioaddr + EL3_CMD);
62afe595
JL		 2402 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2403 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2404 /* The timer will reenable interrupts. */
2405 mod_timer(&vp->timer, jiffies + 1*HZ);
2406 break;
2407 }
2408 /* Acknowledge the IRQ. */
62afe595
JL		 2409 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2410 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2411
2412 if (vortex_debug > 4)
2413 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2414 dev->name, status);
2415handler_exit:
2416 spin_unlock(&vp->lock);
2417 return IRQ_RETVAL(handled);
2418}
2419
2420/*
2421 * This is the ISR for the boomerang series chips.
2422 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2423 */
2424
2425static irqreturn_t
2426boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2427{
2428 struct net_device *dev = dev_id;
2429 struct vortex_private *vp = netdev_priv(dev);
62afe595 2430 void __iomem *ioaddr;
1da177e4
LT		 2431 int status;
2432 int work_done = max_interrupt_work;
2433
62afe595 2434 ioaddr = vp->ioaddr;
1da177e4
LT		 2435
2436 /*
2437 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2438 * and boomerang_start_xmit
2439 */
2440 spin_lock(&vp->lock);
2441
62afe595 2442 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2443
2444 if (vortex_debug > 6)
2445 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2446
2447 if ((status & IntLatch) == 0)
2448 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2449
2450 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2451 if (vortex_debug > 1)
2452 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2453 goto handler_exit;
2454 }
2455
2456 if (status & IntReq) {
2457 status |= vp->deferred;
2458 vp->deferred = 0;
2459 }
2460
2461 if (vortex_debug > 4)
2462 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2463 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2464 do {
2465 if (vortex_debug > 5)
2466 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2467 dev->name, status);
2468 if (status & UpComplete) {
62afe595 2469 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2470 if (vortex_debug > 5)
2471 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2472 boomerang_rx(dev);
2473 }
2474
2475 if (status & DownComplete) {
2476 unsigned int dirty_tx = vp->dirty_tx;
2477
62afe595 2478 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2479 while (vp->cur_tx - dirty_tx > 0) {
2480 int entry = dirty_tx % TX_RING_SIZE;
2481#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2482 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2483 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2484 break; /* It still hasn't been processed. */
2485#else
2486 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2487 break; /* It still hasn't been processed. */
2488#endif
2489
2490 if (vp->tx_skbuff[entry]) {
2491 struct sk_buff *skb = vp->tx_skbuff[entry];
2492#if DO_ZEROCOPY
2493 int i;
2494 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2495 pci_unmap_single(VORTEX_PCI(vp),
2496 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2497 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2498 PCI_DMA_TODEVICE);
2499#else
2500 pci_unmap_single(VORTEX_PCI(vp),
2501 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2502#endif
2503 dev_kfree_skb_irq(skb);
2504 vp->tx_skbuff[entry] = NULL;
2505 } else {
2506 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2507 }
2508 /* vp->stats.tx_packets++; Counted below. */
2509 dirty_tx++;
2510 }
2511 vp->dirty_tx = dirty_tx;
2512 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2513 if (vortex_debug > 6)
2514 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2515 netif_wake_queue (dev);
2516 }
2517 }
2518
2519 /* Check for all uncommon interrupts at once. */
2520 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2521 vortex_error(dev, status);
2522
2523 if (--work_done < 0) {
2524 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2525 "%4.4x.\n", dev->name, status);
2526 /* Disable all pending interrupts. */
2527 do {
2528 vp->deferred |= status;
62afe595 2529 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2530 ioaddr + EL3_CMD);
62afe595
JL		 2531 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2532 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2533 /* The timer will reenable interrupts. */
2534 mod_timer(&vp->timer, jiffies + 1*HZ);
2535 break;
2536 }
2537 /* Acknowledge the IRQ. */
62afe595 2538 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2539 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2540 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2541
62afe595 2542 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2543
2544 if (vortex_debug > 4)
2545 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2546 dev->name, status);
2547handler_exit:
2548 spin_unlock(&vp->lock);
2549 return IRQ_HANDLED;
2550}
2551
2552static int vortex_rx(struct net_device *dev)
2553{
2554 struct vortex_private *vp = netdev_priv(dev);
62afe595 2555 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2556 int i;
2557 short rx_status;
2558
2559 if (vortex_debug > 5)
2560 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2561 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2562 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2563 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2564 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2565 if (vortex_debug > 2)
2566 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2567 vp->stats.rx_errors++;
2568 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2569 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2570 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2571 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2572 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2573 } else {
2574 /* The packet length: up to 4.5K!. */
2575 int pkt_len = rx_status & 0x1fff;
2576 struct sk_buff *skb;
2577
2578 skb = dev_alloc_skb(pkt_len + 5);
2579 if (vortex_debug > 4)
2580 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2581 pkt_len, rx_status);
2582 if (skb != NULL) {
2583 skb->dev = dev;
2584 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2585 /* 'skb_put()' points to the start of sk_buff data area. */
2586 if (vp->bus_master &&
62afe595 2587 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2588 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2589 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2590 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2591 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2592 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2593 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2594 ;
2595 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2596 } else {
62afe595
JL		 2597 ioread32_rep(ioaddr + RX_FIFO,
2598 skb_put(skb, pkt_len),
2599 (pkt_len + 3) >> 2);
1da177e4 2600 }
62afe595 2601 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2602 skb->protocol = eth_type_trans(skb, dev);
2603 netif_rx(skb);
2604 dev->last_rx = jiffies;
2605 vp->stats.rx_packets++;
2606 /* Wait a limited time to go to next packet. */
2607 for (i = 200; i >= 0; i--)
62afe595 2608 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2609 break;
2610 continue;
2611 } else if (vortex_debug > 0)
2612 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2613 "size %d.\n", dev->name, pkt_len);
35b30674 2614 vp->stats.rx_dropped++;
1da177e4 2615 }
1da177e4
LT		 2616 issue_and_wait(dev, RxDiscard);
2617 }
2618
2619 return 0;
2620}
2621
2622static int
2623boomerang_rx(struct net_device *dev)
2624{
2625 struct vortex_private *vp = netdev_priv(dev);
2626 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2627 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2628 int rx_status;
2629 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2630
2631 if (vortex_debug > 5)
62afe595 2632 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2633
2634 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2635 if (--rx_work_limit < 0)
2636 break;
2637 if (rx_status & RxDError) { /* Error, update stats. */
2638 unsigned char rx_error = rx_status >> 16;
2639 if (vortex_debug > 2)
2640 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2641 vp->stats.rx_errors++;
2642 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2643 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2644 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2645 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2646 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2647 } else {
2648 /* The packet length: up to 4.5K!. */
2649 int pkt_len = rx_status & 0x1fff;
2650 struct sk_buff *skb;
2651 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2652
2653 if (vortex_debug > 4)
2654 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2655 pkt_len, rx_status);
2656
2657 /* Check if the packet is long enough to just accept without
2658 copying to a properly sized skbuff. */
2659 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2660 skb->dev = dev;
2661 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2662 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2663 /* 'skb_put()' points to the start of sk_buff data area. */
2664 memcpy(skb_put(skb, pkt_len),
689be439 2665 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2666 pkt_len);
2667 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2668 vp->rx_copy++;
2669 } else {
2670 /* Pass up the skbuff already on the Rx ring. */
2671 skb = vp->rx_skbuff[entry];
2672 vp->rx_skbuff[entry] = NULL;
2673 skb_put(skb, pkt_len);
2674 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2675 vp->rx_nocopy++;
2676 }
2677 skb->protocol = eth_type_trans(skb, dev);
2678 { /* Use hardware checksum info. */
2679 int csum_bits = rx_status & 0xee000000;
2680 if (csum_bits &&
2681 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2682 csum_bits == (IPChksumValid | UDPChksumValid))) {
2683 skb->ip_summed = CHECKSUM_UNNECESSARY;
2684 vp->rx_csumhits++;
2685 }
2686 }
2687 netif_rx(skb);
2688 dev->last_rx = jiffies;
2689 vp->stats.rx_packets++;
2690 }
2691 entry = (++vp->cur_rx) % RX_RING_SIZE;
2692 }
2693 /* Refill the Rx ring buffers. */
2694 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2695 struct sk_buff *skb;
2696 entry = vp->dirty_rx % RX_RING_SIZE;
2697 if (vp->rx_skbuff[entry] == NULL) {
2698 skb = dev_alloc_skb(PKT_BUF_SZ);
2699 if (skb == NULL) {
2700 static unsigned long last_jif;
ff5688ae 2701 if (time_after(jiffies, last_jif + 10 * HZ)) {
1da177e4
LT		 2702 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2703 last_jif = jiffies;
2704 }
2705 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2706 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2707 break; /* Bad news! */
2708 }
2709 skb->dev = dev; /* Mark as being used by this device. */
2710 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2711 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2712 vp->rx_skbuff[entry] = skb;
2713 }
2714 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2715 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2716 }
2717 return 0;
2718}
2719
2720/*
2721 * If we've hit a total OOM refilling the Rx ring we poll once a second
2722 * for some memory. Otherwise there is no way to restart the rx process.
2723 */
2724static void
2725rx_oom_timer(unsigned long arg)
2726{
2727 struct net_device *dev = (struct net_device *)arg;
2728 struct vortex_private *vp = netdev_priv(dev);
2729
2730 spin_lock_irq(&vp->lock);
2731 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2732 boomerang_rx(dev);
2733 if (vortex_debug > 1) {
2734 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2735 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2736 }
2737 spin_unlock_irq(&vp->lock);
2738}
2739
2740static void
2741vortex_down(struct net_device *dev, int final_down)
2742{
2743 struct vortex_private *vp = netdev_priv(dev);
62afe595 2744 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2745
2746 netif_stop_queue (dev);
2747
2748 del_timer_sync(&vp->rx_oom_timer);
2749 del_timer_sync(&vp->timer);
2750
2751 /* Turn off statistics ASAP. We update vp->stats below. */
62afe595 2752 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2753
2754 /* Disable the receiver and transmitter. */
62afe595
JL		 2755 iowrite16(RxDisable, ioaddr + EL3_CMD);
2756 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2757
2758 /* Disable receiving 802.1q tagged frames */
2759 set_8021q_mode(dev, 0);
2760
2761 if (dev->if_port == XCVR_10base2)
2762 /* Turn off thinnet power. Green! */
62afe595 2763 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2764
62afe595 2765 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2766
2767 update_stats(ioaddr, dev);
2768 if (vp->full_bus_master_rx)
62afe595 2769 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2770 if (vp->full_bus_master_tx)
62afe595 2771 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2772
2773 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2774 vp->pm_state_valid = 1;
1da177e4
LT		 2775 pci_save_state(VORTEX_PCI(vp));
2776 acpi_set_WOL(dev);
2777 }
2778}
2779
2780static int
2781vortex_close(struct net_device *dev)
2782{
2783 struct vortex_private *vp = netdev_priv(dev);
62afe595 2784 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2785 int i;
2786
2787 if (netif_device_present(dev))
2788 vortex_down(dev, 1);
2789
2790 if (vortex_debug > 1) {
2791 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2792 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2793 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2794 " tx_queued %d Rx pre-checksummed %d.\n",
2795 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2796 }
2797
2798#if DO_ZEROCOPY
32fb5f06
JL		 2799 if (vp->rx_csumhits &&
2800 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2801 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2802 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2803 "not using them!\n", dev->name);
1da177e4
LT		 2804 }
2805#endif
2806
2807 free_irq(dev->irq, dev);
2808
2809 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2810 for (i = 0; i < RX_RING_SIZE; i++)
2811 if (vp->rx_skbuff[i]) {
2812 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2813 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2814 dev_kfree_skb(vp->rx_skbuff[i]);
2815 vp->rx_skbuff[i] = NULL;
2816 }
2817 }
2818 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2819 for (i = 0; i < TX_RING_SIZE; i++) {
2820 if (vp->tx_skbuff[i]) {
2821 struct sk_buff *skb = vp->tx_skbuff[i];
2822#if DO_ZEROCOPY
2823 int k;
2824
2825 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2826 pci_unmap_single(VORTEX_PCI(vp),
2827 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2828 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2829 PCI_DMA_TODEVICE);
2830#else
2831 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2832#endif
2833 dev_kfree_skb(skb);
2834 vp->tx_skbuff[i] = NULL;
2835 }
2836 }
2837 }
2838
2839 return 0;
2840}
2841
2842static void
2843dump_tx_ring(struct net_device *dev)
2844{
2845 if (vortex_debug > 0) {
2846 struct vortex_private *vp = netdev_priv(dev);
62afe595 2847 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2848
2849 if (vp->full_bus_master_tx) {
2850 int i;
62afe595 2851 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2852
2853 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2854 vp->full_bus_master_tx,
2855 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2856 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2857 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2858 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2859 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2860 issue_and_wait(dev, DownStall);
2861 for (i = 0; i < TX_RING_SIZE; i++) {
2862 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2863 &vp->tx_ring[i],
2864#if DO_ZEROCOPY
2865 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2866#else
2867 le32_to_cpu(vp->tx_ring[i].length),
2868#endif
2869 le32_to_cpu(vp->tx_ring[i].status));
2870 }
2871 if (!stalled)
62afe595 2872 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2873 }
2874 }
2875}
2876
2877static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2878{
2879 struct vortex_private *vp = netdev_priv(dev);
62afe595 2880 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2881 unsigned long flags;
2882
2883 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2884 spin_lock_irqsave (&vp->lock, flags);
62afe595 2885 update_stats(ioaddr, dev);
1da177e4
LT		 2886 spin_unlock_irqrestore (&vp->lock, flags);
2887 }
2888 return &vp->stats;
2889}
2890
2891/* Update statistics.
2892 Unlike with the EL3 we need not worry about interrupts changing
2893 the window setting from underneath us, but we must still guard
2894 against a race condition with a StatsUpdate interrupt updating the
2895 table. This is done by checking that the ASM (!) code generated uses
2896 atomic updates with '+='.
2897 */
62afe595 2898static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2899{
2900 struct vortex_private *vp = netdev_priv(dev);
62afe595 2901 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2902
2903 if (old_window == 0xffff) /* Chip suspended or ejected. */
2904 return;
2905 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2906 /* Switch to the stats window, and read everything. */
2907 EL3WINDOW(6);
62afe595
JL		 2908 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2909 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
62afe595
JL		 2910 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2911 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2912 vp->stats.tx_packets += ioread8(ioaddr + 6);
2913 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2914 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2915 /* Don't bother with register 9, an extension of registers 6&7.
2916 If we do use the 6&7 values the atomic update assumption above
2917 is invalid. */
62afe595
JL		 2918 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2919 vp->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2920 /* Extra stats for get_ethtool_stats() */
62afe595 2921 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2922 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2923 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2924 EL3WINDOW(4);
62afe595 2925 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2926
8d1d0340
SK		 2927 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2928 + vp->xstats.tx_single_collisions
2929 + vp->xstats.tx_max_collisions;
2930
1da177e4 2931 {
62afe595 2932 u8 up = ioread8(ioaddr + 13);
1da177e4
LT		 2933 vp->stats.rx_bytes += (up & 0x0f) << 16;
2934 vp->stats.tx_bytes += (up & 0xf0) << 12;
2935 }
2936
2937 EL3WINDOW(old_window >> 13);
2938 return;
2939}
2940
2941static int vortex_nway_reset(struct net_device *dev)
2942{
2943 struct vortex_private *vp = netdev_priv(dev);
62afe595 2944 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2945 unsigned long flags;
2946 int rc;
2947
2948 spin_lock_irqsave(&vp->lock, flags);
2949 EL3WINDOW(4);
2950 rc = mii_nway_restart(&vp->mii);
2951 spin_unlock_irqrestore(&vp->lock, flags);
2952 return rc;
2953}
2954
1da177e4
LT		 2955static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2956{
2957 struct vortex_private *vp = netdev_priv(dev);
62afe595 2958 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2959 unsigned long flags;
2960 int rc;
2961
2962 spin_lock_irqsave(&vp->lock, flags);
2963 EL3WINDOW(4);
2964 rc = mii_ethtool_gset(&vp->mii, cmd);
2965 spin_unlock_irqrestore(&vp->lock, flags);
2966 return rc;
2967}
2968
2969static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2970{
2971 struct vortex_private *vp = netdev_priv(dev);
62afe595 2972 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2973 unsigned long flags;
2974 int rc;
2975
2976 spin_lock_irqsave(&vp->lock, flags);
2977 EL3WINDOW(4);
2978 rc = mii_ethtool_sset(&vp->mii, cmd);
2979 spin_unlock_irqrestore(&vp->lock, flags);
2980 return rc;
2981}
2982
2983static u32 vortex_get_msglevel(struct net_device *dev)
2984{
2985 return vortex_debug;
2986}
2987
2988static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2989{
2990 vortex_debug = dbg;
2991}
2992
2993static int vortex_get_stats_count(struct net_device *dev)
2994{
2995 return VORTEX_NUM_STATS;
2996}
2997
2998static void vortex_get_ethtool_stats(struct net_device *dev,
2999 struct ethtool_stats *stats, u64 *data)
3000{
3001 struct vortex_private *vp = netdev_priv(dev);
62afe595 3002 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3003 unsigned long flags;
3004
3005 spin_lock_irqsave(&vp->lock, flags);
62afe595 3006 update_stats(ioaddr, dev);
1da177e4
LT		 3007 spin_unlock_irqrestore(&vp->lock, flags);
3008
3009 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 3010 data[1] = vp->xstats.tx_max_collisions;
3011 data[2] = vp->xstats.tx_multiple_collisions;
3012 data[3] = vp->xstats.tx_single_collisions;
3013 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 3014}
3015
3016
3017static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3018{
3019 switch (stringset) {
3020 case ETH_SS_STATS:
3021 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
3022 break;
3023 default:
3024 WARN_ON(1);
3025 break;
3026 }
3027}
3028
3029static void vortex_get_drvinfo(struct net_device *dev,
3030 struct ethtool_drvinfo *info)
3031{
3032 struct vortex_private *vp = netdev_priv(dev);
3033
3034 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 3035 if (VORTEX_PCI(vp)) {
3036 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
3037 } else {
3038 if (VORTEX_EISA(vp))
3039 sprintf(info->bus_info, vp->gendev->bus_id);
3040 else
3041 sprintf(info->bus_info, "EISA 0x%lx %d",
3042 dev->base_addr, dev->irq);
3043 }
3044}
3045
3046static struct ethtool_ops vortex_ethtool_ops = {
3047 .get_drvinfo = vortex_get_drvinfo,
3048 .get_strings = vortex_get_strings,
3049 .get_msglevel = vortex_get_msglevel,
3050 .set_msglevel = vortex_set_msglevel,
3051 .get_ethtool_stats = vortex_get_ethtool_stats,
3052 .get_stats_count = vortex_get_stats_count,
3053 .get_settings = vortex_get_settings,
3054 .set_settings = vortex_set_settings,
373a6887 3055 .get_link = ethtool_op_get_link,
1da177e4 3056 .nway_reset = vortex_nway_reset,
a880c4cd 3057 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 3058};
3059
3060#ifdef CONFIG_PCI
3061/*
3062 * Must power the device up to do MDIO operations
3063 */
3064static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3065{
3066 int err;
3067 struct vortex_private *vp = netdev_priv(dev);
62afe595 3068 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3069 unsigned long flags;
3070 int state = 0;
3071
3072 if(VORTEX_PCI(vp))
3073 state = VORTEX_PCI(vp)->current_state;
3074
3075 /* The kernel core really should have pci_get_power_state() */
3076
3077 if(state != 0)
3078 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3079 spin_lock_irqsave(&vp->lock, flags);
3080 EL3WINDOW(4);
3081 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3082 spin_unlock_irqrestore(&vp->lock, flags);
3083 if(state != 0)
3084 pci_set_power_state(VORTEX_PCI(vp), state);
3085
3086 return err;
3087}
3088#endif
3089
3090
3091/* Pre-Cyclone chips have no documented multicast filter, so the only
3092 multicast setting is to receive all multicast frames. At least
3093 the chip has a very clean way to set the mode, unlike many others. */
3094static void set_rx_mode(struct net_device *dev)
3095{
62afe595
JL		 3096 struct vortex_private *vp = netdev_priv(dev);
3097 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3098 int new_mode;
3099
3100 if (dev->flags & IFF_PROMISC) {
3101 if (vortex_debug > 0)
3102 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
3103 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3104 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
3105 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3106 } else
3107 new_mode = SetRxFilter | RxStation | RxBroadcast;
3108
62afe595 3109 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 3110}
3111
3112#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3113/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3114 Note that this must be done after each RxReset due to some backwards
3115 compatibility logic in the Cyclone and Tornado ASICs */
3116
3117/* The Ethernet Type used for 802.1q tagged frames */
3118#define VLAN_ETHER_TYPE 0x8100
3119
3120static void set_8021q_mode(struct net_device *dev, int enable)
3121{
3122 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 3123 void __iomem *ioaddr = vp->ioaddr;
3124 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 3125 int mac_ctrl;
3126
3127 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3128 /* cyclone and tornado chipsets can recognize 802.1q
3129 * tagged frames and treat them correctly */
3130
3131 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3132 if (enable)
3133 max_pkt_size += 4; /* 802.1Q VLAN tag */
3134
3135 EL3WINDOW(3);
62afe595 3136 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 3137
3138 /* set VlanEtherType to let the hardware checksumming
3139 treat tagged frames correctly */
3140 EL3WINDOW(7);
62afe595 3141 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 3142 } else {
3143 /* on older cards we have to enable large frames */
3144
3145 vp->large_frames = dev->mtu > 1500 || enable;
3146
3147 EL3WINDOW(3);
62afe595 3148 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3149 if (vp->large_frames)
3150 mac_ctrl |= 0x40;
3151 else
3152 mac_ctrl &= ~0x40;
62afe595 3153 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3154 }
3155
3156 EL3WINDOW(old_window);
3157}
3158#else
3159
3160static void set_8021q_mode(struct net_device *dev, int enable)
3161{
3162}
3163
3164
3165#endif
3166
3167/* MII transceiver control section.
3168 Read and write the MII registers using software-generated serial
3169 MDIO protocol. See the MII specifications or DP83840A data sheet
3170 for details. */
3171
3172/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3173 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3174 "overclocking" issues. */
62afe595 3175#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3176
3177#define MDIO_SHIFT_CLK 0x01
3178#define MDIO_DIR_WRITE 0x04
3179#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3180#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3181#define MDIO_DATA_READ 0x02
3182#define MDIO_ENB_IN 0x00
3183
3184/* Generate the preamble required for initial synchronization and
3185 a few older transceivers. */
62afe595 3186static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3187{
62afe595 3188 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3189
3190 /* Establish sync by sending at least 32 logic ones. */
3191 while (-- bits >= 0) {
62afe595 3192 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3193 mdio_delay();
62afe595 3194 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3195 mdio_delay();
3196 }
3197}
3198
3199static int mdio_read(struct net_device *dev, int phy_id, int location)
3200{
3201 int i;
62afe595
JL		 3202 struct vortex_private *vp = netdev_priv(dev);
3203 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3204 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3205 unsigned int retval = 0;
62afe595 3206 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3207
3208 if (mii_preamble_required)
3209 mdio_sync(ioaddr, 32);
3210
3211 /* Shift the read command bits out. */
3212 for (i = 14; i >= 0; i--) {
3213 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3214 iowrite16(dataval, mdio_addr);
1da177e4 3215 mdio_delay();
62afe595 3216 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3217 mdio_delay();
3218 }
3219 /* Read the two transition, 16 data, and wire-idle bits. */
3220 for (i = 19; i > 0; i--) {
62afe595 3221 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3222 mdio_delay();
62afe595
JL		 3223 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3224 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3225 mdio_delay();
3226 }
3227 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3228}
3229
3230static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3231{
62afe595
JL		 3232 struct vortex_private *vp = netdev_priv(dev);
3233 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3234 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3235 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3236 int i;
3237
3238 if (mii_preamble_required)
3239 mdio_sync(ioaddr, 32);
3240
3241 /* Shift the command bits out. */
3242 for (i = 31; i >= 0; i--) {
3243 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3244 iowrite16(dataval, mdio_addr);
1da177e4 3245 mdio_delay();
62afe595 3246 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3247 mdio_delay();
3248 }
3249 /* Leave the interface idle. */
3250 for (i = 1; i >= 0; i--) {
62afe595 3251 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3252 mdio_delay();
62afe595 3253 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3254 mdio_delay();
3255 }
3256 return;
3257}
a880c4cd 3258
1da177e4
LT		 3259/* ACPI: Advanced Configuration and Power Interface. */
3260/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3261static void acpi_set_WOL(struct net_device *dev)
3262{
3263 struct vortex_private *vp = netdev_priv(dev);
62afe595 3264 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3265
3266 if (vp->enable_wol) {
3267 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3268 EL3WINDOW(7);
62afe595 3269 iowrite16(2, ioaddr + 0x0c);
1da177e4 3270 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3271 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3272 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 3273
3274 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3c8fad18
DR		 3275
3276 /* Change the power state to D3; RxEnable doesn't take effect. */
3277 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3278 }
1da177e4
LT		 3279}
3280
3281
a880c4cd 3282static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3283{
3284 struct net_device *dev = pci_get_drvdata(pdev);
3285 struct vortex_private *vp;
3286
3287 if (!dev) {
3288 printk("vortex_remove_one called for Compaq device!\n");
3289 BUG();
3290 }
3291
3292 vp = netdev_priv(dev);
3293
62afe595
JL		 3294 if (vp->cb_fn_base)
3295 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3296
1da177e4
LT		 3297 unregister_netdev(dev);
3298
3299 if (VORTEX_PCI(vp)) {
3300 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3301 if (vp->pm_state_valid)
3302 pci_restore_state(VORTEX_PCI(vp));
3303 pci_disable_device(VORTEX_PCI(vp));
3304 }
3305 /* Should really use issue_and_wait() here */
62afe595
JL		 3306 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3307 vp->ioaddr + EL3_CMD);
3308
3309 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3310
3311 pci_free_consistent(pdev,
3312 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3313 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3314 vp->rx_ring,
3315 vp->rx_ring_dma);
3316 if (vp->must_free_region)
3317 release_region(dev->base_addr, vp->io_size);
3318 free_netdev(dev);
3319}
3320
3321
3322static struct pci_driver vortex_driver = {
3323 .name = "3c59x",
3324 .probe = vortex_init_one,
3325 .remove = __devexit_p(vortex_remove_one),
3326 .id_table = vortex_pci_tbl,
3327#ifdef CONFIG_PM
3328 .suspend = vortex_suspend,
3329 .resume = vortex_resume,
3330#endif
3331};
3332
3333
3334static int vortex_have_pci;
3335static int vortex_have_eisa;
3336
3337
a880c4cd 3338static int __init vortex_init(void)
1da177e4
LT		 3339{
3340 int pci_rc, eisa_rc;
3341
3342 pci_rc = pci_module_init(&vortex_driver);
3343 eisa_rc = vortex_eisa_init();
3344
3345 if (pci_rc == 0)
3346 vortex_have_pci = 1;
3347 if (eisa_rc > 0)
3348 vortex_have_eisa = 1;
3349
3350 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3351}
3352
3353
a880c4cd 3354static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3355{
3356 struct vortex_private *vp;
62afe595 3357 void __iomem *ioaddr;
1da177e4
LT		 3358
3359#ifdef CONFIG_EISA
3360 /* Take care of the EISA devices */
a880c4cd 3361 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4
LT		 3362#endif
3363
3364 if (compaq_net_device) {
3365 vp = compaq_net_device->priv;
62afe595
JL		 3366 ioaddr = ioport_map(compaq_net_device->base_addr,
3367 VORTEX_TOTAL_SIZE);
1da177e4 3368
a880c4cd
SK		 3369 unregister_netdev(compaq_net_device);
3370 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3371 release_region(compaq_net_device->base_addr,
3372 VORTEX_TOTAL_SIZE);
1da177e4 3373
a880c4cd 3374 free_netdev(compaq_net_device);
1da177e4
LT		 3375 }
3376}
3377
3378
a880c4cd 3379static void __exit vortex_cleanup(void)
1da177e4
LT		 3380{
3381 if (vortex_have_pci)
a880c4cd 3382 pci_unregister_driver(&vortex_driver);
1da177e4 3383 if (vortex_have_eisa)
a880c4cd 3384 vortex_eisa_cleanup();
1da177e4
LT		 3385}
3386
3387
3388module_init(vortex_init);
3389module_exit(vortex_cleanup);
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