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1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Linux Kernel Additions:
21
22 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
23 0.99H+lk1.0 - Jeff Garzik <jgarzik@pobox.com>
24 Remove compatibility defines for kernel versions < 2.2.x.
25 Update for new 2.3.x module interface
26 LK1.1.2 (March 19, 2000)
27 * New PCI interface (jgarzik)
28
29 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
30 - Merged with 3c575_cb.c
31 - Don't set RxComplete in boomerang interrupt enable reg
32 - spinlock in vortex_timer to protect mdio functions
33 - disable local interrupts around call to vortex_interrupt in
34 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
35 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
36 - In vortex_start_xmit(), move the lock to _after_ we've altered
37 vp->cur_tx and vp->tx_full. This defeats the race between
38 vortex_start_xmit() and vortex_interrupt which was identified
39 by Bogdan Costescu.
40 - Merged back support for six new cards from various sources
41 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
42 insertion oops)
43 - Tell it that 3c905C has NWAY for 100bT autoneg
44 - Fix handling of SetStatusEnd in 'Too much work..' code, as
45 per 2.3.99's 3c575_cb (Dave Hinds).
46 - Split ISR into two for vortex & boomerang
47 - Fix MOD_INC/DEC races
48 - Handle resource allocation failures.
49 - Fix 3CCFE575CT LED polarity
50 - Make tx_interrupt_mitigation the default
51
52 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
53 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
54 - Put vortex_info_tbl into __devinitdata
55 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
56 as in the hardware.
57 - Increased the loop counter in issue_and_wait from 2,000 to 4,000.
58
59 LK1.1.5 28 April 2000, andrewm
60 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
61 - Some extra diagnostics
62 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
63 chips usually get a Tx timeout.
64 - Added extra_reset module parm
65 - Replaced some inline timer manip with mod_timer
66 (Franois romieu <Francois.Romieu@nic.fr>)
67 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
68 (this came across from 3c575_cb).
69
70 LK1.1.6 06 Jun 2000, andrewm
71 - Backed out the PPC defines.
72 - Use del_timer_sync(), mod_timer().
73 - Fix wrapped ulong comparison in boomerang_rx()
74 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
75 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
76 - Replace union wn3_config with BFINS/BFEXT manipulation for
77 sparc64 (Pete Zaitcev, Peter Jones)
78 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
79 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
80 Donald Becker)
81 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
82 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
83
84 LK1.1.7 2 Jul 2000 andrewm
85 - Better handling of shared IRQs
86 - Reset the transmitter on a Tx reclaim error
87 - Fixed crash under OOM during vortex_open() (Mark Hemment)
88 - Fix Rx cessation problem during OOM (help from Mark Hemment)
89 - The spinlocks around the mdio access were blocking interrupts for 300uS.
90 Fix all this to use spin_lock_bh() within mdio_read/write
91 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
92 have one.
93 - Added 802.3x MAC-layer flow control support
94
95 LK1.1.8 13 Aug 2000 andrewm
96 - Ignore request_region() return value - already reserved if Cardbus.
97 - Merged some additional Cardbus flags from Don's 0.99Qk
98 - Some fixes for 3c556 (Fred Maciel)
99 - Fix for EISA initialisation (Jan Rekorajski)
100 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
101 - Fixed MII_XCVR_PWR for 3CCFE575CT
102 - Added INVERT_LED_PWR, used it.
103 - Backed out the extra_reset stuff
104
105 LK1.1.9 12 Sep 2000 andrewm
106 - Backed out the tx_reset_resume flags. It was a no-op.
107 - In vortex_error, don't reset the Tx on txReclaim errors
108 - In vortex_error, don't reset the Tx on maxCollisions errors.
109 Hence backed out all the DownListPtr logic here.
110 - In vortex_error, give Tornado cards a partial TxReset on
111 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
112 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
113 - Fixed a bug where, if vp->tx_full is set when the interface
114 is downed, it remains set when the interface is upped. Bad
115 things happen.
116
117 LK1.1.10 17 Sep 2000 andrewm
118 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
119 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
120 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
121
122 LK1.1.11 13 Nov 2000 andrewm
123 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
124
125 LK1.1.12 1 Jan 2001 andrewm (2.4.0-pre1)
126 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
127 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
128 - Added extended issue_and_wait for the 3c905CX.
129 - Look for an MII on PHY index 24 first (3c905CX oddity).
130 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
131 - Don't free skbs we don't own on oom path in vortex_open().
132
133 LK1.1.13 27 Jan 2001
134 - Added explicit `medialock' flag so we can truly
135 lock the media type down with `options'.
136 - "check ioremap return and some tidbits" (Arnaldo Carvalho de Melo <acme@conectiva.com.br>)
137 - Added and used EEPROM_NORESET for 3c556B PM resumes.
138 - Fixed leakage of vp->rx_ring.
139 - Break out separate HAS_HWCKSM device capability flag.
140 - Kill vp->tx_full (ANK)
141 - Merge zerocopy fragment handling (ANK?)
142
143 LK1.1.14 15 Feb 2001
144 - Enable WOL. Can be turned on with `enable_wol' module option.
145 - EISA and PCI initialisation fixes (jgarzik, Manfred Spraul)
146 - If a device's internalconfig register reports it has NWAY,
147 use it, even if autoselect is enabled.
148
149 LK1.1.15 6 June 2001 akpm
150 - Prevent double counting of received bytes (Lars Christensen)
151 - Add ethtool support (jgarzik)
152 - Add module parm descriptions (Andrzej M. Krzysztofowicz)
153 - Implemented alloc_etherdev() API
154 - Special-case the 'Tx error 82' message.
155
156 LK1.1.16 18 July 2001 akpm
157 - Make NETIF_F_SG dependent upon nr_free_highpages(), not on CONFIG_HIGHMEM
158 - Lessen verbosity of bootup messages
159 - Fix WOL - use new PM API functions.
160 - Use netif_running() instead of vp->open in suspend/resume.
161 - Don't reset the interface logic on open/close/rmmod. It upsets
162 autonegotiation, and hence DHCP (from 0.99T).
163 - Back out EEPROM_NORESET flag because of the above (we do it for all
164 NICs).
165 - Correct 3c982 identification string
166 - Rename wait_for_completion() to issue_and_wait() to avoid completion.h
167 clash.
168
169 LK1.1.17 18Dec01 akpm
170 - PCI ID 9805 is a Python-T, not a dual-port Cyclone. Apparently.
171 And it has NWAY.
172 - Mask our advertised modes (vp->advertising) with our capabilities
173 (MII reg5) when deciding which duplex mode to use.
174 - Add `global_options' as default for options[]. Ditto global_enable_wol,
175 global_full_duplex.
176
177 LK1.1.18 01Jul02 akpm
178 - Fix for undocumented transceiver power-up bit on some 3c566B's
179 (Donald Becker, Rahul Karnik)
180
181 - See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
182 - Also see Documentation/networking/vortex.txt
183
184 LK1.1.19 10Nov02 Marc Zyngier <maz@wild-wind.fr.eu.org>
185 - EISA sysfs integration.
186*/
187
188/*
189 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
190 * as well as other drivers
191 *
192 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
193 * due to dead code elimination. There will be some performance benefits from this due to
194 * elimination of all the tests and reduced cache footprint.
195 */
196
197
198#define DRV_NAME "3c59x"
1da177e4
LT		 199
200
201
202/* A few values that may be tweaked. */
203/* Keep the ring sizes a power of two for efficiency. */
204#define TX_RING_SIZE 16
205#define RX_RING_SIZE 32
206#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
207
208/* "Knobs" that adjust features and parameters. */
209/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
210 Setting to > 1512 effectively disables this feature. */
211#ifndef __arm__
212static int rx_copybreak = 200;
213#else
214/* ARM systems perform better by disregarding the bus-master
215 transfer capability of these cards. -- rmk */
216static int rx_copybreak = 1513;
217#endif
218/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
219static const int mtu = 1500;
220/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
221static int max_interrupt_work = 32;
222/* Tx timeout interval (millisecs) */
223static int watchdog = 5000;
224
225/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
226 * of possible Tx stalls if the system is blocking interrupts
227 * somewhere else. Undefine this to disable.
228 */
229#define tx_interrupt_mitigation 1
230
231/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
232#define vortex_debug debug
233#ifdef VORTEX_DEBUG
234static int vortex_debug = VORTEX_DEBUG;
235#else
236static int vortex_debug = 1;
237#endif
238
239#include <linux/config.h>
240#include <linux/module.h>
241#include <linux/kernel.h>
242#include <linux/string.h>
243#include <linux/timer.h>
244#include <linux/errno.h>
245#include <linux/in.h>
246#include <linux/ioport.h>
247#include <linux/slab.h>
248#include <linux/interrupt.h>
249#include <linux/pci.h>
250#include <linux/mii.h>
251#include <linux/init.h>
252#include <linux/netdevice.h>
253#include <linux/etherdevice.h>
254#include <linux/skbuff.h>
255#include <linux/ethtool.h>
256#include <linux/highmem.h>
257#include <linux/eisa.h>
258#include <linux/bitops.h>
ff5688ae 259#include <linux/jiffies.h>
1da177e4
LT		 260#include <asm/irq.h> /* For NR_IRQS only. */
261#include <asm/io.h>
262#include <asm/uaccess.h>
263
264/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
265 This is only in the support-all-kernels source code. */
266
267#define RUN_AT(x) (jiffies + (x))
268
269#include <linux/delay.h>
270
271
272static char version[] __devinitdata =
273DRV_NAME ": Donald Becker and others. www.scyld.com/network/vortex.html\n";
274
275MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 276MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 277MODULE_LICENSE("GPL");
1da177e4
LT		 278
279
280/* Operational parameter that usually are not changed. */
281
282/* The Vortex size is twice that of the original EtherLinkIII series: the
283 runtime register window, window 1, is now always mapped in.
284 The Boomerang size is twice as large as the Vortex -- it has additional
285 bus master control registers. */
286#define VORTEX_TOTAL_SIZE 0x20
287#define BOOMERANG_TOTAL_SIZE 0x40
288
289/* Set iff a MII transceiver on any interface requires mdio preamble.
290 This only set with the original DP83840 on older 3c905 boards, so the extra
291 code size of a per-interface flag is not worthwhile. */
292static char mii_preamble_required;
293
294#define PFX DRV_NAME ": "
295
296
297
298/*
299 Theory of Operation
300
301I. Board Compatibility
302
303This device driver is designed for the 3Com FastEtherLink and FastEtherLink
304XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
305versions of the FastEtherLink cards. The supported product IDs are
306 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
307
308The related ISA 3c515 is supported with a separate driver, 3c515.c, included
309with the kernel source or available from
310 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
311
312II. Board-specific settings
313
314PCI bus devices are configured by the system at boot time, so no jumpers
315need to be set on the board. The system BIOS should be set to assign the
316PCI INTA signal to an otherwise unused system IRQ line.
317
318The EEPROM settings for media type and forced-full-duplex are observed.
319The EEPROM media type should be left at the default "autoselect" unless using
32010base2 or AUI connections which cannot be reliably detected.
321
322III. Driver operation
323
324The 3c59x series use an interface that's very similar to the previous 3c5x9
325series. The primary interface is two programmed-I/O FIFOs, with an
326alternate single-contiguous-region bus-master transfer (see next).
327
328The 3c900 "Boomerang" series uses a full-bus-master interface with separate
329lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
330DEC Tulip and Intel Speedo3. The first chip version retains a compatible
331programmed-I/O interface that has been removed in 'B' and subsequent board
332revisions.
333
334One extension that is advertised in a very large font is that the adapters
335are capable of being bus masters. On the Vortex chip this capability was
336only for a single contiguous region making it far less useful than the full
337bus master capability. There is a significant performance impact of taking
338an extra interrupt or polling for the completion of each transfer, as well
339as difficulty sharing the single transfer engine between the transmit and
340receive threads. Using DMA transfers is a win only with large blocks or
341with the flawed versions of the Intel Orion motherboard PCI controller.
342
343The Boomerang chip's full-bus-master interface is useful, and has the
344currently-unused advantages over other similar chips that queued transmit
345packets may be reordered and receive buffer groups are associated with a
346single frame.
347
348With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
349Rather than a fixed intermediate receive buffer, this scheme allocates
350full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
351the copying breakpoint: it is chosen to trade-off the memory wasted by
352passing the full-sized skbuff to the queue layer for all frames vs. the
353copying cost of copying a frame to a correctly-sized skbuff.
354
355IIIC. Synchronization
356The driver runs as two independent, single-threaded flows of control. One
357is the send-packet routine, which enforces single-threaded use by the
358dev->tbusy flag. The other thread is the interrupt handler, which is single
359threaded by the hardware and other software.
360
361IV. Notes
362
363Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
3643c590, 3c595, and 3c900 boards.
365The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
366the EISA version is called "Demon". According to Terry these names come
367from rides at the local amusement park.
368
369The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
370This driver only supports ethernet packets because of the skbuff allocation
371limit of 4K.
372*/
373
374/* This table drives the PCI probe routines. It's mostly boilerplate in all
375 of the drivers, and will likely be provided by some future kernel.
376*/
377enum pci_flags_bit {
378 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
379 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
380};
381
382enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
383 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
384 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
385 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
386 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
387 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
388
389enum vortex_chips {
390 CH_3C590 = 0,
391 CH_3C592,
392 CH_3C597,
393 CH_3C595_1,
394 CH_3C595_2,
395
396 CH_3C595_3,
397 CH_3C900_1,
398 CH_3C900_2,
399 CH_3C900_3,
400 CH_3C900_4,
401
402 CH_3C900_5,
403 CH_3C900B_FL,
404 CH_3C905_1,
405 CH_3C905_2,
406 CH_3C905B_1,
407
408 CH_3C905B_2,
409 CH_3C905B_FX,
410 CH_3C905C,
411 CH_3C9202,
412 CH_3C980,
413 CH_3C9805,
414
415 CH_3CSOHO100_TX,
416 CH_3C555,
417 CH_3C556,
418 CH_3C556B,
419 CH_3C575,
420
421 CH_3C575_1,
422 CH_3CCFE575,
423 CH_3CCFE575CT,
424 CH_3CCFE656,
425 CH_3CCFEM656,
426
427 CH_3CCFEM656_1,
428 CH_3C450,
429 CH_3C920,
430 CH_3C982A,
431 CH_3C982B,
432
433 CH_905BT4,
434 CH_920B_EMB_WNM,
435};
436
437
438/* note: this array directly indexed by above enums, and MUST
439 * be kept in sync with both the enums above, and the PCI device
440 * table below
441 */
442static struct vortex_chip_info {
443 const char *name;
444 int flags;
445 int drv_flags;
446 int io_size;
447} vortex_info_tbl[] __devinitdata = {
448 {"3c590 Vortex 10Mbps",
449 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
450 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
451 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
452 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
453 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
454 {"3c595 Vortex 100baseTx",
455 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
456 {"3c595 Vortex 100baseT4",
457 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
458
459 {"3c595 Vortex 100base-MII",
460 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
461 {"3c900 Boomerang 10baseT",
462 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
463 {"3c900 Boomerang 10Mbps Combo",
464 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
465 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
466 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
467 {"3c900 Cyclone 10Mbps Combo",
468 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
469
470 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
471 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
472 {"3c900B-FL Cyclone 10base-FL",
473 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
474 {"3c905 Boomerang 100baseTx",
475 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
476 {"3c905 Boomerang 100baseT4",
477 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
478 {"3c905B Cyclone 100baseTx",
479 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
480
481 {"3c905B Cyclone 10/100/BNC",
482 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
483 {"3c905B-FX Cyclone 100baseFx",
484 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
485 {"3c905C Tornado",
486 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
487 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
488 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
489 {"3c980 Cyclone",
490 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
491
492 {"3c980C Python-T",
493 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
494 {"3cSOHO100-TX Hurricane",
495 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
496 {"3c555 Laptop Hurricane",
497 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
498 {"3c556 Laptop Tornado",
499 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
500 HAS_HWCKSM, 128, },
501 {"3c556B Laptop Hurricane",
502 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
503 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
504
505 {"3c575 [Megahertz] 10/100 LAN CardBus",
506 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
507 {"3c575 Boomerang CardBus",
508 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
509 {"3CCFE575BT Cyclone CardBus",
510 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
511 INVERT_LED_PWR|HAS_HWCKSM, 128, },
512 {"3CCFE575CT Tornado CardBus",
513 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
514 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
515 {"3CCFE656 Cyclone CardBus",
516 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
517 INVERT_LED_PWR|HAS_HWCKSM, 128, },
518
519 {"3CCFEM656B Cyclone+Winmodem CardBus",
520 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
521 INVERT_LED_PWR|HAS_HWCKSM, 128, },
522 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
523 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
524 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
525 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
526 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
527 {"3c920 Tornado",
528 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
529 {"3c982 Hydra Dual Port A",
530 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
531
532 {"3c982 Hydra Dual Port B",
533 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
534 {"3c905B-T4",
535 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
536 {"3c920B-EMB-WNM Tornado",
537 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
538
539 {NULL,}, /* NULL terminated list. */
540};
541
542
543static struct pci_device_id vortex_pci_tbl[] = {
544 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
545 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
546 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
547 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
548 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
549
550 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
551 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
552 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
553 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
554 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
555
556 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
557 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
558 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
559 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
560 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
561
562 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
563 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
564 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
565 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
566 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
567 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
568
569 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
570 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
571 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
572 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
573 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
574
575 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
576 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
577 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
578 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
579 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
580
581 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
582 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
583 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
584 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
585 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
586
587 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
588 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
589
590 {0,} /* 0 terminated list. */
591};
592MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
593
594
595/* Operational definitions.
596 These are not used by other compilation units and thus are not
597 exported in a ".h" file.
598
599 First the windows. There are eight register windows, with the command
600 and status registers available in each.
601 */
62afe595 602#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 603#define EL3_CMD 0x0e
604#define EL3_STATUS 0x0e
605
606/* The top five bits written to EL3_CMD are a command, the lower
607 11 bits are the parameter, if applicable.
608 Note that 11 parameters bits was fine for ethernet, but the new chip
609 can handle FDDI length frames (~4500 octets) and now parameters count
610 32-bit 'Dwords' rather than octets. */
611
612enum vortex_cmd {
613 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
614 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
615 UpStall = 6<<11, UpUnstall = (6<<11)+1,
616 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
617 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
618 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
619 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
620 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
621 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
622 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
623
624/* The SetRxFilter command accepts the following classes: */
625enum RxFilter {
626 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
627
628/* Bits in the general status register. */
629enum vortex_status {
630 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
631 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
632 IntReq = 0x0040, StatsFull = 0x0080,
633 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
634 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
635 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
636};
637
638/* Register window 1 offsets, the window used in normal operation.
639 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
640enum Window1 {
641 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
642 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
643 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
644};
645enum Window0 {
646 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
647 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
648 IntrStatus=0x0E, /* Valid in all windows. */
649};
650enum Win0_EEPROM_bits {
651 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
652 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
653 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
654};
655/* EEPROM locations. */
656enum eeprom_offset {
657 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
658 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
659 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
660 DriverTune=13, Checksum=15};
661
662enum Window2 { /* Window 2. */
663 Wn2_ResetOptions=12,
664};
665enum Window3 { /* Window 3: MAC/config bits. */
666 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
667};
668
669#define BFEXT(value, offset, bitcount) \
670 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
671
672#define BFINS(lhs, rhs, offset, bitcount) \
673 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
674 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
675
676#define RAM_SIZE(v) BFEXT(v, 0, 3)
677#define RAM_WIDTH(v) BFEXT(v, 3, 1)
678#define RAM_SPEED(v) BFEXT(v, 4, 2)
679#define ROM_SIZE(v) BFEXT(v, 6, 2)
680#define RAM_SPLIT(v) BFEXT(v, 16, 2)
681#define XCVR(v) BFEXT(v, 20, 4)
682#define AUTOSELECT(v) BFEXT(v, 24, 1)
683
684enum Window4 { /* Window 4: Xcvr/media bits. */
685 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
686};
687enum Win4_Media_bits {
688 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
689 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
690 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
691 Media_LnkBeat = 0x0800,
692};
693enum Window7 { /* Window 7: Bus Master control. */
694 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
695 Wn7_MasterStatus = 12,
696};
697/* Boomerang bus master control registers. */
698enum MasterCtrl {
699 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
700 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
701};
702
703/* The Rx and Tx descriptor lists.
704 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
705 alignment contraint on tx_ring[] and rx_ring[]. */
706#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
707#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
708struct boom_rx_desc {
709 u32 next; /* Last entry points to 0. */
710 s32 status;
711 u32 addr; /* Up to 63 addr/len pairs possible. */
712 s32 length; /* Set LAST_FRAG to indicate last pair. */
713};
714/* Values for the Rx status entry. */
715enum rx_desc_status {
716 RxDComplete=0x00008000, RxDError=0x4000,
717 /* See boomerang_rx() for actual error bits */
718 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
719 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
720};
721
722#ifdef MAX_SKB_FRAGS
723#define DO_ZEROCOPY 1
724#else
725#define DO_ZEROCOPY 0
726#endif
727
728struct boom_tx_desc {
729 u32 next; /* Last entry points to 0. */
730 s32 status; /* bits 0:12 length, others see below. */
731#if DO_ZEROCOPY
732 struct {
733 u32 addr;
734 s32 length;
735 } frag[1+MAX_SKB_FRAGS];
736#else
737 u32 addr;
738 s32 length;
739#endif
740};
741
742/* Values for the Tx status entry. */
743enum tx_desc_status {
744 CRCDisable=0x2000, TxDComplete=0x8000,
745 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
746 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
747};
748
749/* Chip features we care about in vp->capabilities, read from the EEPROM. */
750enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
751
752struct vortex_extra_stats {
8d1d0340
SK		 753 unsigned long tx_deferred;
754 unsigned long tx_max_collisions;
755 unsigned long tx_multiple_collisions;
756 unsigned long tx_single_collisions;
757 unsigned long rx_bad_ssd;
1da177e4
LT		 758};
759
760struct vortex_private {
761 /* The Rx and Tx rings should be quad-word-aligned. */
762 struct boom_rx_desc* rx_ring;
763 struct boom_tx_desc* tx_ring;
764 dma_addr_t rx_ring_dma;
765 dma_addr_t tx_ring_dma;
766 /* The addresses of transmit- and receive-in-place skbuffs. */
767 struct sk_buff* rx_skbuff[RX_RING_SIZE];
768 struct sk_buff* tx_skbuff[TX_RING_SIZE];
769 unsigned int cur_rx, cur_tx; /* The next free ring entry */
770 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
771 struct net_device_stats stats; /* Generic stats */
772 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
773 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
774 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
775
776 /* PCI configuration space information. */
777 struct device *gendev;
62afe595
JL		 778 void __iomem *ioaddr; /* IO address space */
779 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 780
781 /* Some values here only for performance evaluation and path-coverage */
782 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
783 int card_idx;
784
785 /* The remainder are related to chip state, mostly media selection. */
786 struct timer_list timer; /* Media selection timer. */
787 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
788 int options; /* User-settable misc. driver options. */
789 unsigned int media_override:4, /* Passed-in media type. */
790 default_media:4, /* Read from the EEPROM/Wn3_Config. */
791 full_duplex:1, force_fd:1, autoselect:1,
792 bus_master:1, /* Vortex can only do a fragment bus-m. */
793 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
794 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
795 partner_flow_ctrl:1, /* Partner supports flow control */
796 has_nway:1,
797 enable_wol:1, /* Wake-on-LAN is enabled */
798 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
799 open:1,
800 medialock:1,
801 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
802 large_frames:1; /* accept large frames */
803 int drv_flags;
804 u16 status_enable;
805 u16 intr_enable;
806 u16 available_media; /* From Wn3_Options. */
807 u16 capabilities, info1, info2; /* Various, from EEPROM. */
808 u16 advertising; /* NWay media advertisement */
809 unsigned char phys[2]; /* MII device addresses. */
810 u16 deferred; /* Resend these interrupts when we
811 * bale from the ISR */
812 u16 io_size; /* Size of PCI region (for release_region) */
813 spinlock_t lock; /* Serialise access to device & its vortex_private */
814 struct mii_if_info mii; /* MII lib hooks/info */
815};
816
817#ifdef CONFIG_PCI
818#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
819#else
820#define DEVICE_PCI(dev) NULL
821#endif
822
823#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
824
825#ifdef CONFIG_EISA
826#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
827#else
828#define DEVICE_EISA(dev) NULL
829#endif
830
831#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
832
833/* The action to take with a media selection timer tick.
834 Note that we deviate from the 3Com order by checking 10base2 before AUI.
835 */
836enum xcvr_types {
837 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
838 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
839};
840
f71e1309 841static const struct media_table {
1da177e4
LT		 842 char *name;
843 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
844 mask:8, /* The transceiver-present bit in Wn3_Config.*/
845 next:8; /* The media type to try next. */
846 int wait; /* Time before we check media status. */
847} media_tbl[] = {
848 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
849 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
850 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
851 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
852 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
853 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
854 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
855 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
856 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
857 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
858 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
859};
860
861static struct {
862 const char str[ETH_GSTRING_LEN];
863} ethtool_stats_keys[] = {
864 { "tx_deferred" },
8d1d0340 865 { "tx_max_collisions" },
1da177e4 866 { "tx_multiple_collisions" },
8d1d0340 867 { "tx_single_collisions" },
1da177e4
LT		 868 { "rx_bad_ssd" },
869};
870
871/* number of ETHTOOL_GSTATS u64's */
8d1d0340 872#define VORTEX_NUM_STATS 5
1da177e4 873
62afe595 874static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4
LT		 875 int chip_idx, int card_idx);
876static void vortex_up(struct net_device *dev);
877static void vortex_down(struct net_device *dev, int final);
878static int vortex_open(struct net_device *dev);
62afe595 879static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 880static int mdio_read(struct net_device *dev, int phy_id, int location);
881static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
882static void vortex_timer(unsigned long arg);
883static void rx_oom_timer(unsigned long arg);
884static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
885static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
886static int vortex_rx(struct net_device *dev);
887static int boomerang_rx(struct net_device *dev);
888static irqreturn_t vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
889static irqreturn_t boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
890static int vortex_close(struct net_device *dev);
891static void dump_tx_ring(struct net_device *dev);
62afe595 892static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 893static struct net_device_stats *vortex_get_stats(struct net_device *dev);
894static void set_rx_mode(struct net_device *dev);
895#ifdef CONFIG_PCI
896static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
897#endif
898static void vortex_tx_timeout(struct net_device *dev);
899static void acpi_set_WOL(struct net_device *dev);
900static struct ethtool_ops vortex_ethtool_ops;
901static void set_8021q_mode(struct net_device *dev, int enable);
902
903\f
904/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
905/* Option count limit only -- unlimited interfaces are supported. */
906#define MAX_UNITS 8
9954ab7f
JL		 907static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
908static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
909static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
910static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
911static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 912static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 913static int global_options = -1;
914static int global_full_duplex = -1;
915static int global_enable_wol = -1;
900fd17d 916static int global_use_mmio = -1;
1da177e4
LT		 917
918/* #define dev_alloc_skb dev_alloc_skb_debug */
919
920/* Variables to work-around the Compaq PCI BIOS32 problem. */
921static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
922static struct net_device *compaq_net_device;
923
924static int vortex_cards_found;
925
926module_param(debug, int, 0);
927module_param(global_options, int, 0);
928module_param_array(options, int, NULL, 0);
929module_param(global_full_duplex, int, 0);
930module_param_array(full_duplex, int, NULL, 0);
931module_param_array(hw_checksums, int, NULL, 0);
932module_param_array(flow_ctrl, int, NULL, 0);
933module_param(global_enable_wol, int, 0);
934module_param_array(enable_wol, int, NULL, 0);
935module_param(rx_copybreak, int, 0);
936module_param(max_interrupt_work, int, 0);
937module_param(compaq_ioaddr, int, 0);
938module_param(compaq_irq, int, 0);
939module_param(compaq_device_id, int, 0);
940module_param(watchdog, int, 0);
900fd17d
JL		 941module_param(global_use_mmio, int, 0);
942module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 943MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
944MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
945MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
946MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 947MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 948MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
949MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
950MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 951MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 952MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
953MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
954MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
955MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
956MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
957MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 958MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
959MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 960
961#ifdef CONFIG_NET_POLL_CONTROLLER
962static void poll_vortex(struct net_device *dev)
963{
964 struct vortex_private *vp = netdev_priv(dev);
965 unsigned long flags;
966 local_save_flags(flags);
967 local_irq_disable();
968 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev,NULL);
969 local_irq_restore(flags);
970}
971#endif
972
973#ifdef CONFIG_PM
974
975static int vortex_suspend (struct pci_dev *pdev, pm_message_t state)
976{
977 struct net_device *dev = pci_get_drvdata(pdev);
978
979 if (dev && dev->priv) {
980 if (netif_running(dev)) {
981 netif_device_detach(dev);
982 vortex_down(dev, 1);
983 }
5b039e68
RW		 984 pci_save_state(pdev);
985 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
986 free_irq(dev->irq, dev);
987 pci_disable_device(pdev);
988 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 989 }
990 return 0;
991}
992
993static int vortex_resume (struct pci_dev *pdev)
994{
995 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 996 struct vortex_private *vp = netdev_priv(dev);
1da177e4 997
5b039e68
RW		 998 if (dev && vp) {
999 pci_set_power_state(pdev, PCI_D0);
1000 pci_restore_state(pdev);
1001 pci_enable_device(pdev);
1002 pci_set_master(pdev);
1003 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1004 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev)) {
1005 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1006 pci_disable_device(pdev);
1007 return -EBUSY;
1008 }
1da177e4
LT		 1009 if (netif_running(dev)) {
1010 vortex_up(dev);
1011 netif_device_attach(dev);
1012 }
1013 }
1014 return 0;
1015}
1016
1017#endif /* CONFIG_PM */
1018
1019#ifdef CONFIG_EISA
1020static struct eisa_device_id vortex_eisa_ids[] = {
1021 { "TCM5920", CH_3C592 },
1022 { "TCM5970", CH_3C597 },
1023 { "" }
1024};
1025
1026static int vortex_eisa_probe (struct device *device);
1027static int vortex_eisa_remove (struct device *device);
1028
1029static struct eisa_driver vortex_eisa_driver = {
1030 .id_table = vortex_eisa_ids,
1031 .driver = {
1032 .name = "3c59x",
1033 .probe = vortex_eisa_probe,
1034 .remove = vortex_eisa_remove
1035 }
1036};
1037
1038static int vortex_eisa_probe (struct device *device)
1039{
62afe595 1040 void __iomem *ioaddr;
1da177e4
LT		 1041 struct eisa_device *edev;
1042
1043 edev = to_eisa_device (device);
1da177e4 1044
62afe595 1045 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 1046 return -EBUSY;
1047
62afe595
JL		 1048 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
1049
1050 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 1051 edev->id.driver_data, vortex_cards_found)) {
62afe595 1052 release_region (edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 1053 return -ENODEV;
1054 }
1055
1056 vortex_cards_found++;
1057
1058 return 0;
1059}
1060
1061static int vortex_eisa_remove (struct device *device)
1062{
1063 struct eisa_device *edev;
1064 struct net_device *dev;
1065 struct vortex_private *vp;
62afe595 1066 void __iomem *ioaddr;
1da177e4
LT		 1067
1068 edev = to_eisa_device (device);
1069 dev = eisa_get_drvdata (edev);
1070
1071 if (!dev) {
1072 printk("vortex_eisa_remove called for Compaq device!\n");
1073 BUG();
1074 }
1075
1076 vp = netdev_priv(dev);
62afe595 1077 ioaddr = vp->ioaddr;
1da177e4
LT		 1078
1079 unregister_netdev (dev);
62afe595
JL		 1080 iowrite16 (TotalReset|0x14, ioaddr + EL3_CMD);
1081 release_region (dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 1082
1083 free_netdev (dev);
1084 return 0;
1085}
1086#endif
1087
1088/* returns count found (>= 0), or negative on error */
1089static int __init vortex_eisa_init (void)
1090{
1091 int eisa_found = 0;
1092 int orig_cards_found = vortex_cards_found;
1093
1094#ifdef CONFIG_EISA
c2f6fabb
BH		 1095 int err;
1096
1097 err = eisa_driver_register (&vortex_eisa_driver);
1098 if (!err) {
1099 /*
1100 * Because of the way EISA bus is probed, we cannot assume
1101 * any device have been found when we exit from
1102 * eisa_driver_register (the bus root driver may not be
1103 * initialized yet). So we blindly assume something was
1104 * found, and let the sysfs magic happend...
1105 */
1106 eisa_found = 1;
1da177e4
LT		 1107 }
1108#endif
1109
1110 /* Special code to work-around the Compaq PCI BIOS32 problem. */
1111 if (compaq_ioaddr) {
62afe595
JL		 1112 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
1113 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 1114 }
1115
1116 return vortex_cards_found - orig_cards_found + eisa_found;
1117}
1118
1119/* returns count (>= 0), or negative on error */
1120static int __devinit vortex_init_one (struct pci_dev *pdev,
1121 const struct pci_device_id *ent)
1122{
900fd17d
JL		 1123 int rc, unit, pci_bar;
1124 struct vortex_chip_info *vci;
1125 void __iomem *ioaddr;
1da177e4
LT		 1126
1127 /* wake up and enable device */
1128 rc = pci_enable_device (pdev);
1129 if (rc < 0)
1130 goto out;
1131
900fd17d
JL		 1132 unit = vortex_cards_found;
1133
1134 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1135 /* Determine the default if the user didn't override us */
1136 vci = &vortex_info_tbl[ent->driver_data];
1137 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1138 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1139 pci_bar = use_mmio[unit] ? 1 : 0;
1140 else
1141 pci_bar = global_use_mmio ? 1 : 0;
1142
1143 ioaddr = pci_iomap(pdev, pci_bar, 0);
1144 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1145 ioaddr = pci_iomap(pdev, 0, 0);
1146
1147 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1148 ent->driver_data, unit);
1da177e4
LT		 1149 if (rc < 0) {
1150 pci_disable_device (pdev);
1151 goto out;
1152 }
1153
1154 vortex_cards_found++;
1155
1156out:
1157 return rc;
1158}
1159
1160/*
1161 * Start up the PCI/EISA device which is described by *gendev.
1162 * Return 0 on success.
1163 *
1164 * NOTE: pdev can be NULL, for the case of a Compaq device
1165 */
1166static int __devinit vortex_probe1(struct device *gendev,
62afe595 1167 void __iomem *ioaddr, int irq,
1da177e4
LT		 1168 int chip_idx, int card_idx)
1169{
1170 struct vortex_private *vp;
1171 int option;
1172 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1173 int i, step;
1174 struct net_device *dev;
1175 static int printed_version;
1176 int retval, print_info;
1177 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1178 char *print_name = "3c59x";
1179 struct pci_dev *pdev = NULL;
1180 struct eisa_device *edev = NULL;
1181
1182 if (!printed_version) {
1183 printk (version);
1184 printed_version = 1;
1185 }
1186
1187 if (gendev) {
1188 if ((pdev = DEVICE_PCI(gendev))) {
1189 print_name = pci_name(pdev);
1190 }
1191
1192 if ((edev = DEVICE_EISA(gendev))) {
1193 print_name = edev->dev.bus_id;
1194 }
1195 }
1196
1197 dev = alloc_etherdev(sizeof(*vp));
1198 retval = -ENOMEM;
1199 if (!dev) {
1200 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1201 goto out;
1202 }
1203 SET_MODULE_OWNER(dev);
1204 SET_NETDEV_DEV(dev, gendev);
1205 vp = netdev_priv(dev);
1206
1207 option = global_options;
1208
1209 /* The lower four bits are the media type. */
1210 if (dev->mem_start) {
1211 /*
1212 * The 'options' param is passed in as the third arg to the
1213 * LILO 'ether=' argument for non-modular use
1214 */
1215 option = dev->mem_start;
1216 }
1217 else if (card_idx < MAX_UNITS) {
1218 if (options[card_idx] >= 0)
1219 option = options[card_idx];
1220 }
1221
1222 if (option > 0) {
1223 if (option & 0x8000)
1224 vortex_debug = 7;
1225 if (option & 0x4000)
1226 vortex_debug = 2;
1227 if (option & 0x0400)
1228 vp->enable_wol = 1;
1229 }
1230
1231 print_info = (vortex_debug > 1);
1232 if (print_info)
1233 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1234
61238602 1235 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1236 print_name,
1237 pdev ? "PCI" : "EISA",
1238 vci->name,
1239 ioaddr);
1240
62afe595 1241 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1242 dev->irq = irq;
1243 dev->mtu = mtu;
62afe595 1244 vp->ioaddr = ioaddr;
1da177e4
LT		 1245 vp->large_frames = mtu > 1500;
1246 vp->drv_flags = vci->drv_flags;
1247 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1248 vp->io_size = vci->io_size;
1249 vp->card_idx = card_idx;
1250
1251 /* module list only for Compaq device */
1252 if (gendev == NULL) {
1253 compaq_net_device = dev;
1254 }
1255
1256 /* PCI-only startup logic */
1257 if (pdev) {
1258 /* EISA resources already marked, so only PCI needs to do this here */
1259 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1260 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1261 vp->must_free_region = 1;
1262
1263 /* enable bus-mastering if necessary */
1264 if (vci->flags & PCI_USES_MASTER)
1265 pci_set_master (pdev);
1266
1267 if (vci->drv_flags & IS_VORTEX) {
1268 u8 pci_latency;
1269 u8 new_latency = 248;
1270
1271 /* Check the PCI latency value. On the 3c590 series the latency timer
1272 must be set to the maximum value to avoid data corruption that occurs
1273 when the timer expires during a transfer. This bug exists the Vortex
1274 chip only. */
1275 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1276 if (pci_latency < new_latency) {
1277 printk(KERN_INFO "%s: Overriding PCI latency"
1278 " timer (CFLT) setting of %d, new value is %d.\n",
1279 print_name, pci_latency, new_latency);
1280 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1281 }
1282 }
1283 }
1284
1285 spin_lock_init(&vp->lock);
1286 vp->gendev = gendev;
1287 vp->mii.dev = dev;
1288 vp->mii.mdio_read = mdio_read;
1289 vp->mii.mdio_write = mdio_write;
1290 vp->mii.phy_id_mask = 0x1f;
1291 vp->mii.reg_num_mask = 0x1f;
1292
1293 /* Makes sure rings are at least 16 byte aligned. */
1294 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1295 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1296 &vp->rx_ring_dma);
1297 retval = -ENOMEM;
1298 if (vp->rx_ring == 0)
1299 goto free_region;
1300
1301 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1302 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1303
1304 /* if we are a PCI driver, we store info in pdev->driver_data
1305 * instead of a module list */
1306 if (pdev)
1307 pci_set_drvdata(pdev, dev);
1308 if (edev)
1309 eisa_set_drvdata (edev, dev);
1310
1311 vp->media_override = 7;
1312 if (option >= 0) {
1313 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1314 if (vp->media_override != 7)
1315 vp->medialock = 1;
1316 vp->full_duplex = (option & 0x200) ? 1 : 0;
1317 vp->bus_master = (option & 16) ? 1 : 0;
1318 }
1319
1320 if (global_full_duplex > 0)
1321 vp->full_duplex = 1;
1322 if (global_enable_wol > 0)
1323 vp->enable_wol = 1;
1324
1325 if (card_idx < MAX_UNITS) {
1326 if (full_duplex[card_idx] > 0)
1327 vp->full_duplex = 1;
1328 if (flow_ctrl[card_idx] > 0)
1329 vp->flow_ctrl = 1;
1330 if (enable_wol[card_idx] > 0)
1331 vp->enable_wol = 1;
1332 }
1333
125d5ce8 1334 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1335 vp->options = option;
1336 /* Read the station address from the EEPROM. */
1337 EL3WINDOW(0);
1338 {
1339 int base;
1340
1341 if (vci->drv_flags & EEPROM_8BIT)
1342 base = 0x230;
1343 else if (vci->drv_flags & EEPROM_OFFSET)
1344 base = EEPROM_Read + 0x30;
1345 else
1346 base = EEPROM_Read;
1347
1348 for (i = 0; i < 0x40; i++) {
1349 int timer;
62afe595 1350 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1351 /* Pause for at least 162 us. for the read to take place. */
1352 for (timer = 10; timer >= 0; timer--) {
1353 udelay(162);
62afe595 1354 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1355 break;
1356 }
62afe595 1357 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1358 }
1359 }
1360 for (i = 0; i < 0x18; i++)
1361 checksum ^= eeprom[i];
1362 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1363 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1364 while (i < 0x21)
1365 checksum ^= eeprom[i++];
1366 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1367 }
1368 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1369 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1370 for (i = 0; i < 3; i++)
1371 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1372 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1373 if (print_info) {
1374 for (i = 0; i < 6; i++)
1375 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1376 }
1377 /* Unfortunately an all zero eeprom passes the checksum and this
1378 gets found in the wild in failure cases. Crypto is hard 8) */
1379 if (!is_valid_ether_addr(dev->dev_addr)) {
1380 retval = -EINVAL;
1381 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1382 goto free_ring; /* With every pack */
1383 }
1384 EL3WINDOW(2);
1385 for (i = 0; i < 6; i++)
62afe595 1386 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4
LT		 1387
1388#ifdef __sparc__
1389 if (print_info)
1390 printk(", IRQ %s\n", __irq_itoa(dev->irq));
1391#else
1392 if (print_info)
1393 printk(", IRQ %d\n", dev->irq);
1394 /* Tell them about an invalid IRQ. */
1395 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1396 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1397 dev->irq);
1398#endif
1399
1400 EL3WINDOW(4);
62afe595 1401 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4
LT		 1402 if (print_info) {
1403 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1404 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1405 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1406 }
1407
1408
1409 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1410 unsigned short n;
1411
62afe595
JL		 1412 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1413 if (!vp->cb_fn_base) {
1da177e4 1414 retval = -ENOMEM;
62afe595 1415 goto free_ring;
1da177e4 1416 }
62afe595 1417
1da177e4
LT		 1418 if (print_info) {
1419 printk(KERN_INFO "%s: CardBus functions mapped %8.8lx->%p\n",
62afe595
JL		 1420 print_name, pci_resource_start(pdev, 2),
1421 vp->cb_fn_base);
1da177e4
LT		 1422 }
1423 EL3WINDOW(2);
1424
62afe595 1425 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1426 if (vp->drv_flags & INVERT_LED_PWR)
1427 n |= 0x10;
1428 if (vp->drv_flags & INVERT_MII_PWR)
1429 n |= 0x4000;
62afe595 1430 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1431 if (vp->drv_flags & WNO_XCVR_PWR) {
1432 EL3WINDOW(0);
62afe595 1433 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1434 }
1435 }
1436
1437 /* Extract our information from the EEPROM data. */
1438 vp->info1 = eeprom[13];
1439 vp->info2 = eeprom[15];
1440 vp->capabilities = eeprom[16];
1441
1442 if (vp->info1 & 0x8000) {
1443 vp->full_duplex = 1;
1444 if (print_info)
1445 printk(KERN_INFO "Full duplex capable\n");
1446 }
1447
1448 {
f71e1309 1449 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1450 unsigned int config;
1451 EL3WINDOW(3);
62afe595 1452 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1453 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1454 vp->available_media = 0x40;
62afe595 1455 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1456 if (print_info) {
1457 printk(KERN_DEBUG " Internal config register is %4.4x, "
62afe595 1458 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1da177e4
LT		 1459 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1460 8 << RAM_SIZE(config),
1461 RAM_WIDTH(config) ? "word" : "byte",
1462 ram_split[RAM_SPLIT(config)],
1463 AUTOSELECT(config) ? "autoselect/" : "",
1464 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1465 media_tbl[XCVR(config)].name);
1466 }
1467 vp->default_media = XCVR(config);
1468 if (vp->default_media == XCVR_NWAY)
1469 vp->has_nway = 1;
1470 vp->autoselect = AUTOSELECT(config);
1471 }
1472
1473 if (vp->media_override != 7) {
1474 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1475 print_name, vp->media_override,
1476 media_tbl[vp->media_override].name);
1477 dev->if_port = vp->media_override;
1478 } else
1479 dev->if_port = vp->default_media;
1480
1481 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1482 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1483 int phy, phy_idx = 0;
1484 EL3WINDOW(4);
1485 mii_preamble_required++;
1486 if (vp->drv_flags & EXTRA_PREAMBLE)
1487 mii_preamble_required++;
1488 mdio_sync(ioaddr, 32);
106427e6 1489 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1490 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1491 int mii_status, phyx;
1492
1493 /*
1494 * For the 3c905CX we look at index 24 first, because it bogusly
1495 * reports an external PHY at all indices
1496 */
1497 if (phy == 0)
1498 phyx = 24;
1499 else if (phy <= 24)
1500 phyx = phy - 1;
1501 else
1502 phyx = phy;
106427e6 1503 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1504 if (mii_status && mii_status != 0xffff) {
1505 vp->phys[phy_idx++] = phyx;
1506 if (print_info) {
1507 printk(KERN_INFO " MII transceiver found at address %d,"
1508 " status %4x.\n", phyx, mii_status);
1509 }
1510 if ((mii_status & 0x0040) == 0)
1511 mii_preamble_required++;
1512 }
1513 }
1514 mii_preamble_required--;
1515 if (phy_idx == 0) {
1516 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1517 vp->phys[0] = 24;
1518 } else {
106427e6 1519 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1520 if (vp->full_duplex) {
1521 /* Only advertise the FD media types. */
1522 vp->advertising &= ~0x02A0;
1523 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1524 }
1525 }
1526 vp->mii.phy_id = vp->phys[0];
1527 }
1528
1529 if (vp->capabilities & CapBusMaster) {
1530 vp->full_bus_master_tx = 1;
1531 if (print_info) {
1532 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1533 (vp->info2 & 1) ? "early" : "whole-frame" );
1534 }
1535 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1536 vp->bus_master = 0; /* AKPM: vortex only */
1537 }
1538
1539 /* The 3c59x-specific entries in the device structure. */
1540 dev->open = vortex_open;
1541 if (vp->full_bus_master_tx) {
1542 dev->hard_start_xmit = boomerang_start_xmit;
1543 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1544 if (card_idx < MAX_UNITS &&
1545 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1546 hw_checksums[card_idx] == 1)) {
d311b0d3 1547 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4
LT		 1548 }
1549 } else {
1550 dev->hard_start_xmit = vortex_start_xmit;
1551 }
1552
1553 if (print_info) {
1554 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1555 print_name,
1556 (dev->features & NETIF_F_SG) ? "en":"dis",
1557 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1558 }
1559
1560 dev->stop = vortex_close;
1561 dev->get_stats = vortex_get_stats;
1562#ifdef CONFIG_PCI
1563 dev->do_ioctl = vortex_ioctl;
1564#endif
1565 dev->ethtool_ops = &vortex_ethtool_ops;
1566 dev->set_multicast_list = set_rx_mode;
1567 dev->tx_timeout = vortex_tx_timeout;
1568 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1569#ifdef CONFIG_NET_POLL_CONTROLLER
1570 dev->poll_controller = poll_vortex;
1571#endif
1572 if (pdev) {
1573 vp->pm_state_valid = 1;
1574 pci_save_state(VORTEX_PCI(vp));
1575 acpi_set_WOL(dev);
1576 }
1577 retval = register_netdev(dev);
1578 if (retval == 0)
1579 return 0;
1580
1581free_ring:
1582 pci_free_consistent(pdev,
1583 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1584 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1585 vp->rx_ring,
1586 vp->rx_ring_dma);
1587free_region:
1588 if (vp->must_free_region)
62afe595 1589 release_region(dev->base_addr, vci->io_size);
1da177e4
LT		 1590 free_netdev(dev);
1591 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1592out:
1593 return retval;
1594}
1595
1596static void
1597issue_and_wait(struct net_device *dev, int cmd)
1598{
62afe595
JL		 1599 struct vortex_private *vp = netdev_priv(dev);
1600 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1601 int i;
1602
62afe595 1603 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1604 for (i = 0; i < 2000; i++) {
62afe595 1605 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1606 return;
1607 }
1608
1609 /* OK, that didn't work. Do it the slow way. One second */
1610 for (i = 0; i < 100000; i++) {
62afe595 1611 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4
LT		 1612 if (vortex_debug > 1)
1613 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1614 dev->name, cmd, i * 10);
1615 return;
1616 }
1617 udelay(10);
1618 }
1619 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1620 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1621}
1622
125d5ce8
SK		 1623static void
1624vortex_set_duplex(struct net_device *dev)
1625{
1626 struct vortex_private *vp = netdev_priv(dev);
1627 void __iomem *ioaddr = vp->ioaddr;
1628
1629 printk(KERN_INFO "%s: setting %s-duplex.\n",
1630 dev->name, (vp->full_duplex) ? "full" : "half");
1631
1632 EL3WINDOW(3);
1633 /* Set the full-duplex bit. */
1634 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1635 (vp->large_frames ? 0x40 : 0) |
1636 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1637 0x100 : 0),
1638 ioaddr + Wn3_MAC_Ctrl);
1639
1640 issue_and_wait(dev, TxReset);
1641 /*
1642 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1643 */
1644 issue_and_wait(dev, RxReset|0x04);
1645}
1646
1647static void vortex_check_media(struct net_device *dev, unsigned int init)
1648{
1649 struct vortex_private *vp = netdev_priv(dev);
1650 unsigned int ok_to_print = 0;
1651
1652 if (vortex_debug > 3)
1653 ok_to_print = 1;
1654
1655 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1656 vp->full_duplex = vp->mii.full_duplex;
1657 vortex_set_duplex(dev);
1658 } else if (init) {
1659 vortex_set_duplex(dev);
1660 }
1661}
1662
1da177e4
LT		 1663static void
1664vortex_up(struct net_device *dev)
1665{
1da177e4 1666 struct vortex_private *vp = netdev_priv(dev);
62afe595 1667 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1668 unsigned int config;
1669 int i;
1670
1671 if (VORTEX_PCI(vp)) {
1672 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1673 if (vp->pm_state_valid)
1674 pci_restore_state(VORTEX_PCI(vp));
1da177e4
LT		 1675 pci_enable_device(VORTEX_PCI(vp));
1676 }
1677
1678 /* Before initializing select the active media port. */
1679 EL3WINDOW(3);
62afe595 1680 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1681
1682 if (vp->media_override != 7) {
1683 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1684 dev->name, vp->media_override,
1685 media_tbl[vp->media_override].name);
1686 dev->if_port = vp->media_override;
1687 } else if (vp->autoselect) {
1688 if (vp->has_nway) {
1689 if (vortex_debug > 1)
1690 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1691 dev->name, dev->if_port);
1692 dev->if_port = XCVR_NWAY;
1693 } else {
1694 /* Find first available media type, starting with 100baseTx. */
1695 dev->if_port = XCVR_100baseTx;
1696 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1697 dev->if_port = media_tbl[dev->if_port].next;
1698 if (vortex_debug > 1)
1699 printk(KERN_INFO "%s: first available media type: %s\n",
1700 dev->name, media_tbl[dev->if_port].name);
1701 }
1702 } else {
1703 dev->if_port = vp->default_media;
1704 if (vortex_debug > 1)
1705 printk(KERN_INFO "%s: using default media %s\n",
1706 dev->name, media_tbl[dev->if_port].name);
1707 }
1708
1709 init_timer(&vp->timer);
1710 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1711 vp->timer.data = (unsigned long)dev;
1712 vp->timer.function = vortex_timer; /* timer handler */
1713 add_timer(&vp->timer);
1714
1715 init_timer(&vp->rx_oom_timer);
1716 vp->rx_oom_timer.data = (unsigned long)dev;
1717 vp->rx_oom_timer.function = rx_oom_timer;
1718
1719 if (vortex_debug > 1)
1720 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1721 dev->name, media_tbl[dev->if_port].name);
1722
125d5ce8 1723 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1724 config = BFINS(config, dev->if_port, 20, 4);
1725 if (vortex_debug > 6)
1726 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1727 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1728
125d5ce8 1729 netif_carrier_off(dev);
1da177e4 1730 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1731 EL3WINDOW(4);
125d5ce8 1732 vortex_check_media(dev, 1);
1da177e4 1733 }
125d5ce8
SK		 1734 else
1735 vortex_set_duplex(dev);
1da177e4 1736
1da177e4 1737
62afe595 1738 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1739
1740 if (vortex_debug > 1) {
1741 EL3WINDOW(4);
1742 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1743 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1744 }
1745
1746 /* Set the station address and mask in window 2 each time opened. */
1747 EL3WINDOW(2);
1748 for (i = 0; i < 6; i++)
62afe595 1749 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1750 for (; i < 12; i+=2)
62afe595 1751 iowrite16(0, ioaddr + i);
1da177e4
LT		 1752
1753 if (vp->cb_fn_base) {
62afe595 1754 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1755 if (vp->drv_flags & INVERT_LED_PWR)
1756 n |= 0x10;
1757 if (vp->drv_flags & INVERT_MII_PWR)
1758 n |= 0x4000;
62afe595 1759 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1760 }
1761
1762 if (dev->if_port == XCVR_10base2)
1763 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1764 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1765 if (dev->if_port != XCVR_NWAY) {
1766 EL3WINDOW(4);
62afe595 1767 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1768 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1769 }
1770
1771 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1772 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1773 EL3WINDOW(6);
1774 for (i = 0; i < 10; i++)
62afe595
JL		 1775 ioread8(ioaddr + i);
1776 ioread16(ioaddr + 10);
1777 ioread16(ioaddr + 12);
1da177e4
LT		 1778 /* New: On the Vortex we must also clear the BadSSD counter. */
1779 EL3WINDOW(4);
62afe595 1780 ioread8(ioaddr + 12);
1da177e4 1781 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1782 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1783
1784 /* Switch to register set 7 for normal use. */
1785 EL3WINDOW(7);
1786
1787 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1788 vp->cur_rx = vp->dirty_rx = 0;
1789 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1790 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1791 iowrite32(0x0020, ioaddr + PktStatus);
1792 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1793 }
1794 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1795 vp->cur_tx = vp->dirty_tx = 0;
1796 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1797 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1798 /* Clear the Rx, Tx rings. */
1799 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1800 vp->rx_ring[i].status = 0;
1801 for (i = 0; i < TX_RING_SIZE; i++)
1802 vp->tx_skbuff[i] = NULL;
62afe595 1803 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1804 }
1805 /* Set receiver mode: presumably accept b-case and phys addr only. */
1806 set_rx_mode(dev);
1807 /* enable 802.1q tagged frames */
1808 set_8021q_mode(dev, 1);
62afe595 1809 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4
LT		 1810
1811// issue_and_wait(dev, SetTxStart|0x07ff);
62afe595
JL		 1812 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1813 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1814 /* Allow status bits to be seen. */
1815 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1816 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1817 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1818 (vp->bus_master ? DMADone : 0);
1819 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1820 (vp->full_bus_master_rx ? 0 : RxComplete) |
1821 StatsFull | HostError | TxComplete | IntReq
1822 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1823 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1824 /* Ack all pending events, and set active indicator mask. */
62afe595 1825 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1826 ioaddr + EL3_CMD);
62afe595 1827 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1828 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1829 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4
LT		 1830 netif_start_queue (dev);
1831}
1832
1833static int
1834vortex_open(struct net_device *dev)
1835{
1836 struct vortex_private *vp = netdev_priv(dev);
1837 int i;
1838 int retval;
1839
1840 /* Use the now-standard shared IRQ implementation. */
1841 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1842 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev))) {
1843 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1844 goto out;
1845 }
1846
1847 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1848 if (vortex_debug > 2)
1849 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1850 for (i = 0; i < RX_RING_SIZE; i++) {
1851 struct sk_buff *skb;
1852 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1853 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1854 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1855 skb = dev_alloc_skb(PKT_BUF_SZ);
1856 vp->rx_skbuff[i] = skb;
1857 if (skb == NULL)
1858 break; /* Bad news! */
1859 skb->dev = dev; /* Mark as being used by this device. */
1860 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 1861 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1862 }
1863 if (i != RX_RING_SIZE) {
1864 int j;
1865 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1866 for (j = 0; j < i; j++) {
1867 if (vp->rx_skbuff[j]) {
1868 dev_kfree_skb(vp->rx_skbuff[j]);
1869 vp->rx_skbuff[j] = NULL;
1870 }
1871 }
1872 retval = -ENOMEM;
1873 goto out_free_irq;
1874 }
1875 /* Wrap the ring. */
1876 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1877 }
1878
1879 vortex_up(dev);
1880 return 0;
1881
1882out_free_irq:
1883 free_irq(dev->irq, dev);
1884out:
1885 if (vortex_debug > 1)
1886 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1887 return retval;
1888}
1889
1890static void
1891vortex_timer(unsigned long data)
1892{
1893 struct net_device *dev = (struct net_device *)data;
1894 struct vortex_private *vp = netdev_priv(dev);
62afe595 1895 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1896 int next_tick = 60*HZ;
1897 int ok = 0;
125d5ce8 1898 int media_status, old_window;
1da177e4
LT		 1899
1900 if (vortex_debug > 2) {
1901 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1902 dev->name, media_tbl[dev->if_port].name);
1903 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1904 }
1905
1da177e4 1906 disable_irq(dev->irq);
62afe595 1907 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1908 EL3WINDOW(4);
62afe595 1909 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1910 switch (dev->if_port) {
1911 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1912 if (media_status & Media_LnkBeat) {
1913 netif_carrier_on(dev);
1914 ok = 1;
1915 if (vortex_debug > 1)
1916 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1917 dev->name, media_tbl[dev->if_port].name, media_status);
1918 } else {
1919 netif_carrier_off(dev);
1920 if (vortex_debug > 1) {
1921 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1922 dev->name, media_tbl[dev->if_port].name, media_status);
1923 }
1924 }
1925 break;
1926 case XCVR_MII: case XCVR_NWAY:
1927 {
1da177e4 1928 ok = 1;
125d5ce8
SK		 1929 spin_lock_bh(&vp->lock);
1930 vortex_check_media(dev, 0);
1da177e4
LT		 1931 spin_unlock_bh(&vp->lock);
1932 }
1933 break;
1934 default: /* Other media types handled by Tx timeouts. */
1935 if (vortex_debug > 1)
1936 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1937 dev->name, media_tbl[dev->if_port].name, media_status);
1938 ok = 1;
1939 }
b4ff6450
SK		 1940
1941 if (!netif_carrier_ok(dev))
1942 next_tick = 5*HZ;
1943
e94d10eb
SK		 1944 if (vp->medialock)
1945 goto leave_media_alone;
1946
1da177e4
LT		 1947 if ( ! ok) {
1948 unsigned int config;
1949
1950 do {
1951 dev->if_port = media_tbl[dev->if_port].next;
1952 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1953 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1954 dev->if_port = vp->default_media;
1955 if (vortex_debug > 1)
1956 printk(KERN_DEBUG "%s: Media selection failing, using default "
1957 "%s port.\n",
1958 dev->name, media_tbl[dev->if_port].name);
1959 } else {
1960 if (vortex_debug > 1)
1961 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1962 "%s port.\n",
1963 dev->name, media_tbl[dev->if_port].name);
1964 next_tick = media_tbl[dev->if_port].wait;
1965 }
62afe595 1966 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1967 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1968
1969 EL3WINDOW(3);
62afe595 1970 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1971 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1972 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1973
62afe595 1974 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1975 ioaddr + EL3_CMD);
1976 if (vortex_debug > 1)
1977 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1978 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1979 }
1da177e4
LT		 1980
1981leave_media_alone:
1982 if (vortex_debug > 2)
1983 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1984 dev->name, media_tbl[dev->if_port].name);
1985
e94d10eb
SK		 1986 EL3WINDOW(old_window);
1987 enable_irq(dev->irq);
1da177e4
LT		 1988 mod_timer(&vp->timer, RUN_AT(next_tick));
1989 if (vp->deferred)
62afe595 1990 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1991 return;
1992}
1993
1994static void vortex_tx_timeout(struct net_device *dev)
1995{
1996 struct vortex_private *vp = netdev_priv(dev);
62afe595 1997 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1998
1999 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 2000 dev->name, ioread8(ioaddr + TxStatus),
2001 ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 2002 EL3WINDOW(4);
2003 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 2004 ioread16(ioaddr + Wn4_NetDiag),
2005 ioread16(ioaddr + Wn4_Media),
2006 ioread32(ioaddr + PktStatus),
2007 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 2008 /* Slight code bloat to be user friendly. */
62afe595 2009 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1da177e4
LT		 2010 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
2011 " network cable problem?\n", dev->name);
62afe595 2012 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1da177e4
LT		 2013 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
2014 " IRQ blocked by another device?\n", dev->name);
2015 /* Bad idea here.. but we might as well handle a few events. */
2016 {
2017 /*
2018 * Block interrupts because vortex_interrupt does a bare spin_lock()
2019 */
2020 unsigned long flags;
2021 local_irq_save(flags);
2022 if (vp->full_bus_master_tx)
2023 boomerang_interrupt(dev->irq, dev, NULL);
2024 else
2025 vortex_interrupt(dev->irq, dev, NULL);
2026 local_irq_restore(flags);
2027 }
2028 }
2029
2030 if (vortex_debug > 0)
2031 dump_tx_ring(dev);
2032
2033 issue_and_wait(dev, TxReset);
2034
2035 vp->stats.tx_errors++;
2036 if (vp->full_bus_master_tx) {
2037 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 2038 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
2039 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 2040 ioaddr + DownListPtr);
2041 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
2042 netif_wake_queue (dev);
2043 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 2044 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
2045 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2046 } else {
2047 vp->stats.tx_dropped++;
2048 netif_wake_queue(dev);
2049 }
2050
2051 /* Issue Tx Enable */
62afe595 2052 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2053 dev->trans_start = jiffies;
2054
2055 /* Switch to register set 7 for normal use. */
2056 EL3WINDOW(7);
2057}
2058
2059/*
2060 * Handle uncommon interrupt sources. This is a separate routine to minimize
2061 * the cache impact.
2062 */
2063static void
2064vortex_error(struct net_device *dev, int status)
2065{
2066 struct vortex_private *vp = netdev_priv(dev);
62afe595 2067 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2068 int do_tx_reset = 0, reset_mask = 0;
2069 unsigned char tx_status = 0;
2070
2071 if (vortex_debug > 2) {
2072 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
2073 }
2074
2075 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 2076 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 2077 /* Presumably a tx-timeout. We must merely re-enable. */
2078 if (vortex_debug > 2
2079 || (tx_status != 0x88 && vortex_debug > 0)) {
2080 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
2081 dev->name, tx_status);
2082 if (tx_status == 0x82) {
2083 printk(KERN_ERR "Probably a duplex mismatch. See "
2084 "Documentation/networking/vortex.txt\n");
2085 }
2086 dump_tx_ring(dev);
2087 }
2088 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
2089 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
62afe595 2090 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 2091 if (tx_status & 0x30) { /* txJabber or txUnderrun */
2092 do_tx_reset = 1;
8d1d0340
SK		 2093 } else if (tx_status & 0x08) { /* maxCollisions */
2094 vp->xstats.tx_max_collisions++;
2095 if (vp->drv_flags & MAX_COLLISION_RESET) {
2096 do_tx_reset = 1;
2097 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
2098 }
1da177e4 2099 } else { /* Merely re-enable the transmitter. */
62afe595 2100 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2101 }
2102 }
2103
2104 if (status & RxEarly) { /* Rx early is unused. */
2105 vortex_rx(dev);
62afe595 2106 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 2107 }
2108 if (status & StatsFull) { /* Empty statistics. */
2109 static int DoneDidThat;
2110 if (vortex_debug > 4)
2111 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
2112 update_stats(ioaddr, dev);
2113 /* HACK: Disable statistics as an interrupt source. */
2114 /* This occurs when we have the wrong media type! */
2115 if (DoneDidThat == 0 &&
62afe595 2116 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1da177e4
LT		 2117 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
2118 "stats as an interrupt source.\n", dev->name);
2119 EL3WINDOW(5);
62afe595 2120 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 2121 vp->intr_enable &= ~StatsFull;
2122 EL3WINDOW(7);
2123 DoneDidThat++;
2124 }
2125 }
2126 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 2127 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2128 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 2129 }
2130 if (status & HostError) {
2131 u16 fifo_diag;
2132 EL3WINDOW(4);
62afe595 2133 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1da177e4
LT		 2134 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
2135 dev->name, fifo_diag);
2136 /* Adapter failure requires Tx/Rx reset and reinit. */
2137 if (vp->full_bus_master_tx) {
62afe595 2138 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2139 /* 0x80000000 PCI master abort. */
2140 /* 0x40000000 PCI target abort. */
2141 if (vortex_debug)
2142 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2143
2144 /* In this case, blow the card away */
2145 /* Must not enter D3 or we can't legally issue the reset! */
2146 vortex_down(dev, 0);
2147 issue_and_wait(dev, TotalReset | 0xff);
2148 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2149 } else if (fifo_diag & 0x0400)
2150 do_tx_reset = 1;
2151 if (fifo_diag & 0x3000) {
2152 /* Reset Rx fifo and upload logic */
2153 issue_and_wait(dev, RxReset|0x07);
2154 /* Set the Rx filter to the current state. */
2155 set_rx_mode(dev);
2156 /* enable 802.1q VLAN tagged frames */
2157 set_8021q_mode(dev, 1);
62afe595
JL		 2158 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2159 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2160 }
2161 }
2162
2163 if (do_tx_reset) {
2164 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2165 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2166 if (!vp->full_bus_master_tx)
2167 netif_wake_queue(dev);
2168 }
2169}
2170
2171static int
2172vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2173{
2174 struct vortex_private *vp = netdev_priv(dev);
62afe595 2175 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2176
2177 /* Put out the doubleword header... */
62afe595 2178 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2179 if (vp->bus_master) {
2180 /* Set the bus-master controller to transfer the packet. */
2181 int len = (skb->len + 3) & ~3;
62afe595 2182 iowrite32( vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2183 ioaddr + Wn7_MasterAddr);
62afe595 2184 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2185 vp->tx_skb = skb;
62afe595 2186 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2187 /* netif_wake_queue() will be called at the DMADone interrupt. */
2188 } else {
2189 /* ... and the packet rounded to a doubleword. */
62afe595 2190 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2191 dev_kfree_skb (skb);
62afe595 2192 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2193 netif_start_queue (dev); /* AKPM: redundant? */
2194 } else {
2195 /* Interrupt us when the FIFO has room for max-sized packet. */
2196 netif_stop_queue(dev);
62afe595 2197 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2198 }
2199 }
2200
2201 dev->trans_start = jiffies;
2202
2203 /* Clear the Tx status stack. */
2204 {
2205 int tx_status;
2206 int i = 32;
2207
62afe595 2208 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2209 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2210 if (vortex_debug > 2)
2211 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2212 dev->name, tx_status);
2213 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
2214 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
2215 if (tx_status & 0x30) {
2216 issue_and_wait(dev, TxReset);
2217 }
62afe595 2218 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2219 }
62afe595 2220 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2221 }
2222 }
2223 return 0;
2224}
2225
2226static int
2227boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2228{
2229 struct vortex_private *vp = netdev_priv(dev);
62afe595 2230 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2231 /* Calculate the next Tx descriptor entry. */
2232 int entry = vp->cur_tx % TX_RING_SIZE;
2233 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2234 unsigned long flags;
2235
2236 if (vortex_debug > 6) {
2237 printk(KERN_DEBUG "boomerang_start_xmit()\n");
0f667ff5
JL		 2238 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2239 dev->name, vp->cur_tx);
1da177e4
LT		 2240 }
2241
2242 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2243 if (vortex_debug > 0)
2244 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2245 dev->name);
2246 netif_stop_queue(dev);
2247 return 1;
2248 }
2249
2250 vp->tx_skbuff[entry] = skb;
2251
2252 vp->tx_ring[entry].next = 0;
2253#if DO_ZEROCOPY
2254 if (skb->ip_summed != CHECKSUM_HW)
2255 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2256 else
2257 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2258
2259 if (!skb_shinfo(skb)->nr_frags) {
2260 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2261 skb->len, PCI_DMA_TODEVICE));
2262 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2263 } else {
2264 int i;
2265
2266 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2267 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2268 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2269
2270 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2271 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2272
2273 vp->tx_ring[entry].frag[i+1].addr =
2274 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2275 (void*)page_address(frag->page) + frag->page_offset,
2276 frag->size, PCI_DMA_TODEVICE));
2277
2278 if (i == skb_shinfo(skb)->nr_frags-1)
2279 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2280 else
2281 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2282 }
2283 }
2284#else
2285 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2286 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2287 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2288#endif
2289
2290 spin_lock_irqsave(&vp->lock, flags);
2291 /* Wait for the stall to complete. */
2292 issue_and_wait(dev, DownStall);
2293 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2294 if (ioread32(ioaddr + DownListPtr) == 0) {
2295 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2296 vp->queued_packet++;
2297 }
2298
2299 vp->cur_tx++;
2300 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2301 netif_stop_queue (dev);
2302 } else { /* Clear previous interrupt enable. */
2303#if defined(tx_interrupt_mitigation)
2304 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2305 * were selected, this would corrupt DN_COMPLETE. No?
2306 */
2307 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2308#endif
2309 }
62afe595 2310 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2311 spin_unlock_irqrestore(&vp->lock, flags);
2312 dev->trans_start = jiffies;
2313 return 0;
2314}
2315
2316/* The interrupt handler does all of the Rx thread work and cleans up
2317 after the Tx thread. */
2318
2319/*
2320 * This is the ISR for the vortex series chips.
2321 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2322 */
2323
2324static irqreturn_t
2325vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2326{
2327 struct net_device *dev = dev_id;
2328 struct vortex_private *vp = netdev_priv(dev);
62afe595 2329 void __iomem *ioaddr;
1da177e4
LT		 2330 int status;
2331 int work_done = max_interrupt_work;
2332 int handled = 0;
2333
62afe595 2334 ioaddr = vp->ioaddr;
1da177e4
LT		 2335 spin_lock(&vp->lock);
2336
62afe595 2337 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2338
2339 if (vortex_debug > 6)
2340 printk("vortex_interrupt(). status=0x%4x\n", status);
2341
2342 if ((status & IntLatch) == 0)
2343 goto handler_exit; /* No interrupt: shared IRQs cause this */
2344 handled = 1;
2345
2346 if (status & IntReq) {
2347 status |= vp->deferred;
2348 vp->deferred = 0;
2349 }
2350
2351 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2352 goto handler_exit;
2353
2354 if (vortex_debug > 4)
2355 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2356 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2357
2358 do {
2359 if (vortex_debug > 5)
2360 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2361 dev->name, status);
2362 if (status & RxComplete)
2363 vortex_rx(dev);
2364
2365 if (status & TxAvailable) {
2366 if (vortex_debug > 5)
2367 printk(KERN_DEBUG " TX room bit was handled.\n");
2368 /* There's room in the FIFO for a full-sized packet. */
62afe595 2369 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2370 netif_wake_queue (dev);
2371 }
2372
2373 if (status & DMADone) {
62afe595
JL		 2374 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2375 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2376 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2377 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2378 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2379 /*
2380 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2381 * insufficient FIFO room, the TxAvailable test will succeed and call
2382 * netif_wake_queue()
2383 */
2384 netif_wake_queue(dev);
2385 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2386 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2387 netif_stop_queue(dev);
2388 }
2389 }
2390 }
2391 /* Check for all uncommon interrupts at once. */
2392 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2393 if (status == 0xffff)
2394 break;
2395 vortex_error(dev, status);
2396 }
2397
2398 if (--work_done < 0) {
2399 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2400 "%4.4x.\n", dev->name, status);
2401 /* Disable all pending interrupts. */
2402 do {
2403 vp->deferred |= status;
62afe595 2404 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2405 ioaddr + EL3_CMD);
62afe595
JL		 2406 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2407 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2408 /* The timer will reenable interrupts. */
2409 mod_timer(&vp->timer, jiffies + 1*HZ);
2410 break;
2411 }
2412 /* Acknowledge the IRQ. */
62afe595
JL		 2413 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2414 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2415
2416 if (vortex_debug > 4)
2417 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2418 dev->name, status);
2419handler_exit:
2420 spin_unlock(&vp->lock);
2421 return IRQ_RETVAL(handled);
2422}
2423
2424/*
2425 * This is the ISR for the boomerang series chips.
2426 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2427 */
2428
2429static irqreturn_t
2430boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2431{
2432 struct net_device *dev = dev_id;
2433 struct vortex_private *vp = netdev_priv(dev);
62afe595 2434 void __iomem *ioaddr;
1da177e4
LT		 2435 int status;
2436 int work_done = max_interrupt_work;
2437
62afe595 2438 ioaddr = vp->ioaddr;
1da177e4
LT		 2439
2440 /*
2441 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2442 * and boomerang_start_xmit
2443 */
2444 spin_lock(&vp->lock);
2445
62afe595 2446 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2447
2448 if (vortex_debug > 6)
2449 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2450
2451 if ((status & IntLatch) == 0)
2452 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2453
2454 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2455 if (vortex_debug > 1)
2456 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2457 goto handler_exit;
2458 }
2459
2460 if (status & IntReq) {
2461 status |= vp->deferred;
2462 vp->deferred = 0;
2463 }
2464
2465 if (vortex_debug > 4)
2466 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2467 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2468 do {
2469 if (vortex_debug > 5)
2470 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2471 dev->name, status);
2472 if (status & UpComplete) {
62afe595 2473 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2474 if (vortex_debug > 5)
2475 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2476 boomerang_rx(dev);
2477 }
2478
2479 if (status & DownComplete) {
2480 unsigned int dirty_tx = vp->dirty_tx;
2481
62afe595 2482 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2483 while (vp->cur_tx - dirty_tx > 0) {
2484 int entry = dirty_tx % TX_RING_SIZE;
2485#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2486 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2487 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2488 break; /* It still hasn't been processed. */
2489#else
2490 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2491 break; /* It still hasn't been processed. */
2492#endif
2493
2494 if (vp->tx_skbuff[entry]) {
2495 struct sk_buff *skb = vp->tx_skbuff[entry];
2496#if DO_ZEROCOPY
2497 int i;
2498 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2499 pci_unmap_single(VORTEX_PCI(vp),
2500 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2501 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2502 PCI_DMA_TODEVICE);
2503#else
2504 pci_unmap_single(VORTEX_PCI(vp),
2505 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2506#endif
2507 dev_kfree_skb_irq(skb);
2508 vp->tx_skbuff[entry] = NULL;
2509 } else {
2510 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2511 }
2512 /* vp->stats.tx_packets++; Counted below. */
2513 dirty_tx++;
2514 }
2515 vp->dirty_tx = dirty_tx;
2516 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2517 if (vortex_debug > 6)
2518 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2519 netif_wake_queue (dev);
2520 }
2521 }
2522
2523 /* Check for all uncommon interrupts at once. */
2524 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2525 vortex_error(dev, status);
2526
2527 if (--work_done < 0) {
2528 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2529 "%4.4x.\n", dev->name, status);
2530 /* Disable all pending interrupts. */
2531 do {
2532 vp->deferred |= status;
62afe595 2533 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2534 ioaddr + EL3_CMD);
62afe595
JL		 2535 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2536 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2537 /* The timer will reenable interrupts. */
2538 mod_timer(&vp->timer, jiffies + 1*HZ);
2539 break;
2540 }
2541 /* Acknowledge the IRQ. */
62afe595 2542 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2543 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2544 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2545
62afe595 2546 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2547
2548 if (vortex_debug > 4)
2549 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2550 dev->name, status);
2551handler_exit:
2552 spin_unlock(&vp->lock);
2553 return IRQ_HANDLED;
2554}
2555
2556static int vortex_rx(struct net_device *dev)
2557{
2558 struct vortex_private *vp = netdev_priv(dev);
62afe595 2559 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2560 int i;
2561 short rx_status;
2562
2563 if (vortex_debug > 5)
2564 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2565 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2566 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2567 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2568 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4
LT		 2569 if (vortex_debug > 2)
2570 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2571 vp->stats.rx_errors++;
2572 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2573 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2574 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2575 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2576 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2577 } else {
2578 /* The packet length: up to 4.5K!. */
2579 int pkt_len = rx_status & 0x1fff;
2580 struct sk_buff *skb;
2581
2582 skb = dev_alloc_skb(pkt_len + 5);
2583 if (vortex_debug > 4)
2584 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2585 pkt_len, rx_status);
2586 if (skb != NULL) {
2587 skb->dev = dev;
2588 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2589 /* 'skb_put()' points to the start of sk_buff data area. */
2590 if (vp->bus_master &&
62afe595 2591 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2592 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2593 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2594 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2595 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2596 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2597 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2598 ;
2599 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2600 } else {
62afe595
JL		 2601 ioread32_rep(ioaddr + RX_FIFO,
2602 skb_put(skb, pkt_len),
2603 (pkt_len + 3) >> 2);
1da177e4 2604 }
62afe595 2605 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2606 skb->protocol = eth_type_trans(skb, dev);
2607 netif_rx(skb);
2608 dev->last_rx = jiffies;
2609 vp->stats.rx_packets++;
2610 /* Wait a limited time to go to next packet. */
2611 for (i = 200; i >= 0; i--)
62afe595 2612 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2613 break;
2614 continue;
2615 } else if (vortex_debug > 0)
2616 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2617 "size %d.\n", dev->name, pkt_len);
35b30674 2618 vp->stats.rx_dropped++;
1da177e4 2619 }
1da177e4
LT		 2620 issue_and_wait(dev, RxDiscard);
2621 }
2622
2623 return 0;
2624}
2625
2626static int
2627boomerang_rx(struct net_device *dev)
2628{
2629 struct vortex_private *vp = netdev_priv(dev);
2630 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2631 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2632 int rx_status;
2633 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2634
2635 if (vortex_debug > 5)
62afe595 2636 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2637
2638 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2639 if (--rx_work_limit < 0)
2640 break;
2641 if (rx_status & RxDError) { /* Error, update stats. */
2642 unsigned char rx_error = rx_status >> 16;
2643 if (vortex_debug > 2)
2644 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2645 vp->stats.rx_errors++;
2646 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2647 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2648 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2649 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2650 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2651 } else {
2652 /* The packet length: up to 4.5K!. */
2653 int pkt_len = rx_status & 0x1fff;
2654 struct sk_buff *skb;
2655 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2656
2657 if (vortex_debug > 4)
2658 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2659 pkt_len, rx_status);
2660
2661 /* Check if the packet is long enough to just accept without
2662 copying to a properly sized skbuff. */
2663 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2664 skb->dev = dev;
2665 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2666 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2667 /* 'skb_put()' points to the start of sk_buff data area. */
2668 memcpy(skb_put(skb, pkt_len),
689be439 2669 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2670 pkt_len);
2671 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2672 vp->rx_copy++;
2673 } else {
2674 /* Pass up the skbuff already on the Rx ring. */
2675 skb = vp->rx_skbuff[entry];
2676 vp->rx_skbuff[entry] = NULL;
2677 skb_put(skb, pkt_len);
2678 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2679 vp->rx_nocopy++;
2680 }
2681 skb->protocol = eth_type_trans(skb, dev);
2682 { /* Use hardware checksum info. */
2683 int csum_bits = rx_status & 0xee000000;
2684 if (csum_bits &&
2685 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2686 csum_bits == (IPChksumValid | UDPChksumValid))) {
2687 skb->ip_summed = CHECKSUM_UNNECESSARY;
2688 vp->rx_csumhits++;
2689 }
2690 }
2691 netif_rx(skb);
2692 dev->last_rx = jiffies;
2693 vp->stats.rx_packets++;
2694 }
2695 entry = (++vp->cur_rx) % RX_RING_SIZE;
2696 }
2697 /* Refill the Rx ring buffers. */
2698 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2699 struct sk_buff *skb;
2700 entry = vp->dirty_rx % RX_RING_SIZE;
2701 if (vp->rx_skbuff[entry] == NULL) {
2702 skb = dev_alloc_skb(PKT_BUF_SZ);
2703 if (skb == NULL) {
2704 static unsigned long last_jif;
ff5688ae 2705 if (time_after(jiffies, last_jif + 10 * HZ)) {
1da177e4
LT		 2706 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2707 last_jif = jiffies;
2708 }
2709 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2710 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2711 break; /* Bad news! */
2712 }
2713 skb->dev = dev; /* Mark as being used by this device. */
2714 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
689be439 2715 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2716 vp->rx_skbuff[entry] = skb;
2717 }
2718 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2719 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2720 }
2721 return 0;
2722}
2723
2724/*
2725 * If we've hit a total OOM refilling the Rx ring we poll once a second
2726 * for some memory. Otherwise there is no way to restart the rx process.
2727 */
2728static void
2729rx_oom_timer(unsigned long arg)
2730{
2731 struct net_device *dev = (struct net_device *)arg;
2732 struct vortex_private *vp = netdev_priv(dev);
2733
2734 spin_lock_irq(&vp->lock);
2735 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2736 boomerang_rx(dev);
2737 if (vortex_debug > 1) {
2738 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2739 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2740 }
2741 spin_unlock_irq(&vp->lock);
2742}
2743
2744static void
2745vortex_down(struct net_device *dev, int final_down)
2746{
2747 struct vortex_private *vp = netdev_priv(dev);
62afe595 2748 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2749
2750 netif_stop_queue (dev);
2751
2752 del_timer_sync(&vp->rx_oom_timer);
2753 del_timer_sync(&vp->timer);
2754
2755 /* Turn off statistics ASAP. We update vp->stats below. */
62afe595 2756 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2757
2758 /* Disable the receiver and transmitter. */
62afe595
JL		 2759 iowrite16(RxDisable, ioaddr + EL3_CMD);
2760 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2761
2762 /* Disable receiving 802.1q tagged frames */
2763 set_8021q_mode(dev, 0);
2764
2765 if (dev->if_port == XCVR_10base2)
2766 /* Turn off thinnet power. Green! */
62afe595 2767 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2768
62afe595 2769 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2770
2771 update_stats(ioaddr, dev);
2772 if (vp->full_bus_master_rx)
62afe595 2773 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2774 if (vp->full_bus_master_tx)
62afe595 2775 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2776
2777 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2778 vp->pm_state_valid = 1;
1da177e4
LT		 2779 pci_save_state(VORTEX_PCI(vp));
2780 acpi_set_WOL(dev);
2781 }
2782}
2783
2784static int
2785vortex_close(struct net_device *dev)
2786{
2787 struct vortex_private *vp = netdev_priv(dev);
62afe595 2788 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2789 int i;
2790
2791 if (netif_device_present(dev))
2792 vortex_down(dev, 1);
2793
2794 if (vortex_debug > 1) {
2795 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2796 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
1da177e4
LT		 2797 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2798 " tx_queued %d Rx pre-checksummed %d.\n",
2799 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2800 }
2801
2802#if DO_ZEROCOPY
32fb5f06
JL		 2803 if (vp->rx_csumhits &&
2804 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2805 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2806 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2807 "not using them!\n", dev->name);
1da177e4
LT		 2808 }
2809#endif
2810
2811 free_irq(dev->irq, dev);
2812
2813 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2814 for (i = 0; i < RX_RING_SIZE; i++)
2815 if (vp->rx_skbuff[i]) {
2816 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2817 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2818 dev_kfree_skb(vp->rx_skbuff[i]);
2819 vp->rx_skbuff[i] = NULL;
2820 }
2821 }
2822 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2823 for (i = 0; i < TX_RING_SIZE; i++) {
2824 if (vp->tx_skbuff[i]) {
2825 struct sk_buff *skb = vp->tx_skbuff[i];
2826#if DO_ZEROCOPY
2827 int k;
2828
2829 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2830 pci_unmap_single(VORTEX_PCI(vp),
2831 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2832 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2833 PCI_DMA_TODEVICE);
2834#else
2835 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2836#endif
2837 dev_kfree_skb(skb);
2838 vp->tx_skbuff[i] = NULL;
2839 }
2840 }
2841 }
2842
2843 return 0;
2844}
2845
2846static void
2847dump_tx_ring(struct net_device *dev)
2848{
2849 if (vortex_debug > 0) {
2850 struct vortex_private *vp = netdev_priv(dev);
62afe595 2851 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2852
2853 if (vp->full_bus_master_tx) {
2854 int i;
62afe595 2855 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4
LT		 2856
2857 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2858 vp->full_bus_master_tx,
2859 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2860 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2861 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
62afe595 2862 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2863 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2864 issue_and_wait(dev, DownStall);
2865 for (i = 0; i < TX_RING_SIZE; i++) {
2866 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2867 &vp->tx_ring[i],
2868#if DO_ZEROCOPY
2869 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2870#else
2871 le32_to_cpu(vp->tx_ring[i].length),
2872#endif
2873 le32_to_cpu(vp->tx_ring[i].status));
2874 }
2875 if (!stalled)
62afe595 2876 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2877 }
2878 }
2879}
2880
2881static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2882{
2883 struct vortex_private *vp = netdev_priv(dev);
62afe595 2884 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2885 unsigned long flags;
2886
2887 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2888 spin_lock_irqsave (&vp->lock, flags);
62afe595 2889 update_stats(ioaddr, dev);
1da177e4
LT		 2890 spin_unlock_irqrestore (&vp->lock, flags);
2891 }
2892 return &vp->stats;
2893}
2894
2895/* Update statistics.
2896 Unlike with the EL3 we need not worry about interrupts changing
2897 the window setting from underneath us, but we must still guard
2898 against a race condition with a StatsUpdate interrupt updating the
2899 table. This is done by checking that the ASM (!) code generated uses
2900 atomic updates with '+='.
2901 */
62afe595 2902static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2903{
2904 struct vortex_private *vp = netdev_priv(dev);
62afe595 2905 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2906
2907 if (old_window == 0xffff) /* Chip suspended or ejected. */
2908 return;
2909 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2910 /* Switch to the stats window, and read everything. */
2911 EL3WINDOW(6);
62afe595
JL		 2912 vp->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2913 vp->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
62afe595
JL		 2914 vp->stats.tx_window_errors += ioread8(ioaddr + 4);
2915 vp->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2916 vp->stats.tx_packets += ioread8(ioaddr + 6);
2917 vp->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2918 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2919 /* Don't bother with register 9, an extension of registers 6&7.
2920 If we do use the 6&7 values the atomic update assumption above
2921 is invalid. */
62afe595
JL		 2922 vp->stats.rx_bytes += ioread16(ioaddr + 10);
2923 vp->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2924 /* Extra stats for get_ethtool_stats() */
62afe595 2925 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2926 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2927 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2928 EL3WINDOW(4);
62afe595 2929 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2930
8d1d0340
SK		 2931 vp->stats.collisions = vp->xstats.tx_multiple_collisions
2932 + vp->xstats.tx_single_collisions
2933 + vp->xstats.tx_max_collisions;
2934
1da177e4 2935 {
62afe595 2936 u8 up = ioread8(ioaddr + 13);
1da177e4
LT		 2937 vp->stats.rx_bytes += (up & 0x0f) << 16;
2938 vp->stats.tx_bytes += (up & 0xf0) << 12;
2939 }
2940
2941 EL3WINDOW(old_window >> 13);
2942 return;
2943}
2944
2945static int vortex_nway_reset(struct net_device *dev)
2946{
2947 struct vortex_private *vp = netdev_priv(dev);
62afe595 2948 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2949 unsigned long flags;
2950 int rc;
2951
2952 spin_lock_irqsave(&vp->lock, flags);
2953 EL3WINDOW(4);
2954 rc = mii_nway_restart(&vp->mii);
2955 spin_unlock_irqrestore(&vp->lock, flags);
2956 return rc;
2957}
2958
1da177e4
LT		 2959static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2960{
2961 struct vortex_private *vp = netdev_priv(dev);
62afe595 2962 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2963 unsigned long flags;
2964 int rc;
2965
2966 spin_lock_irqsave(&vp->lock, flags);
2967 EL3WINDOW(4);
2968 rc = mii_ethtool_gset(&vp->mii, cmd);
2969 spin_unlock_irqrestore(&vp->lock, flags);
2970 return rc;
2971}
2972
2973static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2974{
2975 struct vortex_private *vp = netdev_priv(dev);
62afe595 2976 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2977 unsigned long flags;
2978 int rc;
2979
2980 spin_lock_irqsave(&vp->lock, flags);
2981 EL3WINDOW(4);
2982 rc = mii_ethtool_sset(&vp->mii, cmd);
2983 spin_unlock_irqrestore(&vp->lock, flags);
2984 return rc;
2985}
2986
2987static u32 vortex_get_msglevel(struct net_device *dev)
2988{
2989 return vortex_debug;
2990}
2991
2992static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2993{
2994 vortex_debug = dbg;
2995}
2996
2997static int vortex_get_stats_count(struct net_device *dev)
2998{
2999 return VORTEX_NUM_STATS;
3000}
3001
3002static void vortex_get_ethtool_stats(struct net_device *dev,
3003 struct ethtool_stats *stats, u64 *data)
3004{
3005 struct vortex_private *vp = netdev_priv(dev);
62afe595 3006 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3007 unsigned long flags;
3008
3009 spin_lock_irqsave(&vp->lock, flags);
62afe595 3010 update_stats(ioaddr, dev);
1da177e4
LT		 3011 spin_unlock_irqrestore(&vp->lock, flags);
3012
3013 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 3014 data[1] = vp->xstats.tx_max_collisions;
3015 data[2] = vp->xstats.tx_multiple_collisions;
3016 data[3] = vp->xstats.tx_single_collisions;
3017 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 3018}
3019
3020
3021static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3022{
3023 switch (stringset) {
3024 case ETH_SS_STATS:
3025 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
3026 break;
3027 default:
3028 WARN_ON(1);
3029 break;
3030 }
3031}
3032
3033static void vortex_get_drvinfo(struct net_device *dev,
3034 struct ethtool_drvinfo *info)
3035{
3036 struct vortex_private *vp = netdev_priv(dev);
3037
3038 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 3039 if (VORTEX_PCI(vp)) {
3040 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
3041 } else {
3042 if (VORTEX_EISA(vp))
3043 sprintf(info->bus_info, vp->gendev->bus_id);
3044 else
3045 sprintf(info->bus_info, "EISA 0x%lx %d",
3046 dev->base_addr, dev->irq);
3047 }
3048}
3049
3050static struct ethtool_ops vortex_ethtool_ops = {
3051 .get_drvinfo = vortex_get_drvinfo,
3052 .get_strings = vortex_get_strings,
3053 .get_msglevel = vortex_get_msglevel,
3054 .set_msglevel = vortex_set_msglevel,
3055 .get_ethtool_stats = vortex_get_ethtool_stats,
3056 .get_stats_count = vortex_get_stats_count,
3057 .get_settings = vortex_get_settings,
3058 .set_settings = vortex_set_settings,
373a6887 3059 .get_link = ethtool_op_get_link,
1da177e4 3060 .nway_reset = vortex_nway_reset,
bb531fc0 3061 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 3062};
3063
3064#ifdef CONFIG_PCI
3065/*
3066 * Must power the device up to do MDIO operations
3067 */
3068static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3069{
3070 int err;
3071 struct vortex_private *vp = netdev_priv(dev);
62afe595 3072 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3073 unsigned long flags;
3074 int state = 0;
3075
3076 if(VORTEX_PCI(vp))
3077 state = VORTEX_PCI(vp)->current_state;
3078
3079 /* The kernel core really should have pci_get_power_state() */
3080
3081 if(state != 0)
3082 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3083 spin_lock_irqsave(&vp->lock, flags);
3084 EL3WINDOW(4);
3085 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3086 spin_unlock_irqrestore(&vp->lock, flags);
3087 if(state != 0)
3088 pci_set_power_state(VORTEX_PCI(vp), state);
3089
3090 return err;
3091}
3092#endif
3093
3094
3095/* Pre-Cyclone chips have no documented multicast filter, so the only
3096 multicast setting is to receive all multicast frames. At least
3097 the chip has a very clean way to set the mode, unlike many others. */
3098static void set_rx_mode(struct net_device *dev)
3099{
62afe595
JL		 3100 struct vortex_private *vp = netdev_priv(dev);
3101 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3102 int new_mode;
3103
3104 if (dev->flags & IFF_PROMISC) {
3105 if (vortex_debug > 0)
3106 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
3107 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3108 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
3109 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3110 } else
3111 new_mode = SetRxFilter | RxStation | RxBroadcast;
3112
62afe595 3113 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 3114}
3115
3116#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3117/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3118 Note that this must be done after each RxReset due to some backwards
3119 compatibility logic in the Cyclone and Tornado ASICs */
3120
3121/* The Ethernet Type used for 802.1q tagged frames */
3122#define VLAN_ETHER_TYPE 0x8100
3123
3124static void set_8021q_mode(struct net_device *dev, int enable)
3125{
3126 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 3127 void __iomem *ioaddr = vp->ioaddr;
3128 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 3129 int mac_ctrl;
3130
3131 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3132 /* cyclone and tornado chipsets can recognize 802.1q
3133 * tagged frames and treat them correctly */
3134
3135 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3136 if (enable)
3137 max_pkt_size += 4; /* 802.1Q VLAN tag */
3138
3139 EL3WINDOW(3);
62afe595 3140 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 3141
3142 /* set VlanEtherType to let the hardware checksumming
3143 treat tagged frames correctly */
3144 EL3WINDOW(7);
62afe595 3145 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 3146 } else {
3147 /* on older cards we have to enable large frames */
3148
3149 vp->large_frames = dev->mtu > 1500 || enable;
3150
3151 EL3WINDOW(3);
62afe595 3152 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3153 if (vp->large_frames)
3154 mac_ctrl |= 0x40;
3155 else
3156 mac_ctrl &= ~0x40;
62afe595 3157 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3158 }
3159
3160 EL3WINDOW(old_window);
3161}
3162#else
3163
3164static void set_8021q_mode(struct net_device *dev, int enable)
3165{
3166}
3167
3168
3169#endif
3170
3171/* MII transceiver control section.
3172 Read and write the MII registers using software-generated serial
3173 MDIO protocol. See the MII specifications or DP83840A data sheet
3174 for details. */
3175
3176/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3177 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3178 "overclocking" issues. */
62afe595 3179#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3180
3181#define MDIO_SHIFT_CLK 0x01
3182#define MDIO_DIR_WRITE 0x04
3183#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3184#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3185#define MDIO_DATA_READ 0x02
3186#define MDIO_ENB_IN 0x00
3187
3188/* Generate the preamble required for initial synchronization and
3189 a few older transceivers. */
62afe595 3190static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3191{
62afe595 3192 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3193
3194 /* Establish sync by sending at least 32 logic ones. */
3195 while (-- bits >= 0) {
62afe595 3196 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3197 mdio_delay();
62afe595 3198 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3199 mdio_delay();
3200 }
3201}
3202
3203static int mdio_read(struct net_device *dev, int phy_id, int location)
3204{
3205 int i;
62afe595
JL		 3206 struct vortex_private *vp = netdev_priv(dev);
3207 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3208 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3209 unsigned int retval = 0;
62afe595 3210 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3211
3212 if (mii_preamble_required)
3213 mdio_sync(ioaddr, 32);
3214
3215 /* Shift the read command bits out. */
3216 for (i = 14; i >= 0; i--) {
3217 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3218 iowrite16(dataval, mdio_addr);
1da177e4 3219 mdio_delay();
62afe595 3220 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3221 mdio_delay();
3222 }
3223 /* Read the two transition, 16 data, and wire-idle bits. */
3224 for (i = 19; i > 0; i--) {
62afe595 3225 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3226 mdio_delay();
62afe595
JL		 3227 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3228 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3229 mdio_delay();
3230 }
3231 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3232}
3233
3234static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3235{
62afe595
JL		 3236 struct vortex_private *vp = netdev_priv(dev);
3237 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3238 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3239 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3240 int i;
3241
3242 if (mii_preamble_required)
3243 mdio_sync(ioaddr, 32);
3244
3245 /* Shift the command bits out. */
3246 for (i = 31; i >= 0; i--) {
3247 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3248 iowrite16(dataval, mdio_addr);
1da177e4 3249 mdio_delay();
62afe595 3250 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3251 mdio_delay();
3252 }
3253 /* Leave the interface idle. */
3254 for (i = 1; i >= 0; i--) {
62afe595 3255 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3256 mdio_delay();
62afe595 3257 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3258 mdio_delay();
3259 }
3260 return;
3261}
3262\f
3263/* ACPI: Advanced Configuration and Power Interface. */
3264/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3265static void acpi_set_WOL(struct net_device *dev)
3266{
3267 struct vortex_private *vp = netdev_priv(dev);
62afe595 3268 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3269
3270 if (vp->enable_wol) {
3271 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3272 EL3WINDOW(7);
62afe595 3273 iowrite16(2, ioaddr + 0x0c);
1da177e4 3274 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3275 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3276 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 3277
3278 pci_enable_wake(VORTEX_PCI(vp), 0, 1);
3c8fad18
DR		 3279
3280 /* Change the power state to D3; RxEnable doesn't take effect. */
3281 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3282 }
1da177e4
LT		 3283}
3284
3285
3286static void __devexit vortex_remove_one (struct pci_dev *pdev)
3287{
3288 struct net_device *dev = pci_get_drvdata(pdev);
3289 struct vortex_private *vp;
3290
3291 if (!dev) {
3292 printk("vortex_remove_one called for Compaq device!\n");
3293 BUG();
3294 }
3295
3296 vp = netdev_priv(dev);
3297
62afe595
JL		 3298 if (vp->cb_fn_base)
3299 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3300
1da177e4
LT		 3301 unregister_netdev(dev);
3302
3303 if (VORTEX_PCI(vp)) {
3304 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3305 if (vp->pm_state_valid)
3306 pci_restore_state(VORTEX_PCI(vp));
3307 pci_disable_device(VORTEX_PCI(vp));
3308 }
3309 /* Should really use issue_and_wait() here */
62afe595
JL		 3310 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3311 vp->ioaddr + EL3_CMD);
3312
3313 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3314
3315 pci_free_consistent(pdev,
3316 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3317 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3318 vp->rx_ring,
3319 vp->rx_ring_dma);
3320 if (vp->must_free_region)
3321 release_region(dev->base_addr, vp->io_size);
3322 free_netdev(dev);
3323}
3324
3325
3326static struct pci_driver vortex_driver = {
3327 .name = "3c59x",
3328 .probe = vortex_init_one,
3329 .remove = __devexit_p(vortex_remove_one),
3330 .id_table = vortex_pci_tbl,
3331#ifdef CONFIG_PM
3332 .suspend = vortex_suspend,
3333 .resume = vortex_resume,
3334#endif
3335};
3336
3337
3338static int vortex_have_pci;
3339static int vortex_have_eisa;
3340
3341
3342static int __init vortex_init (void)
3343{
3344 int pci_rc, eisa_rc;
3345
3346 pci_rc = pci_module_init(&vortex_driver);
3347 eisa_rc = vortex_eisa_init();
3348
3349 if (pci_rc == 0)
3350 vortex_have_pci = 1;
3351 if (eisa_rc > 0)
3352 vortex_have_eisa = 1;
3353
3354 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3355}
3356
3357
3358static void __exit vortex_eisa_cleanup (void)
3359{
3360 struct vortex_private *vp;
62afe595 3361 void __iomem *ioaddr;
1da177e4
LT		 3362
3363#ifdef CONFIG_EISA
3364 /* Take care of the EISA devices */
3365 eisa_driver_unregister (&vortex_eisa_driver);
3366#endif
3367
3368 if (compaq_net_device) {
3369 vp = compaq_net_device->priv;
62afe595
JL		 3370 ioaddr = ioport_map(compaq_net_device->base_addr,
3371 VORTEX_TOTAL_SIZE);
1da177e4
LT		 3372
3373 unregister_netdev (compaq_net_device);
62afe595
JL		 3374 iowrite16 (TotalReset, ioaddr + EL3_CMD);
3375 release_region(compaq_net_device->base_addr,
3376 VORTEX_TOTAL_SIZE);
1da177e4
LT		 3377
3378 free_netdev (compaq_net_device);
3379 }
3380}
3381
3382
3383static void __exit vortex_cleanup (void)
3384{
3385 if (vortex_have_pci)
3386 pci_unregister_driver (&vortex_driver);
3387 if (vortex_have_eisa)
3388 vortex_eisa_cleanup ();
3389}
3390
3391
3392module_init(vortex_init);
3393module_exit(vortex_cleanup);
3394
3395\f
3396/*
3397 * Local variables:
3398 * c-indent-level: 4
3399 * c-basic-offset: 4
3400 * tab-width: 4
3401 * End:
3402 */
Clone of davem's net-next-2.6 tree