jme: Don't show UDP Checksum error if HW misjudged
[jme.git] / jme.h
CommitLineData
4330c2f2
GFT
1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
eee57828 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
4330c2f2 7 *
3bf61c55
GFT
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
4330c2f2
GFT
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
cd0ff491 25#ifndef __JME_H_INCLUDED__
94c5ea02 26#define __JME_H_INCLUDED__
d7699f87
GFT
27
28#define DRV_NAME "jme"
eee57828 29#define DRV_VERSION "1.0.7"
cd0ff491 30#define PFX DRV_NAME ": "
d7699f87 31
cd0ff491
GFT
32#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
33#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
8d27293f 34
cd0ff491
GFT
35/*
36 * Message related definitions
37 */
38#define JME_DEF_MSG_ENABLE \
39 (NETIF_MSG_PROBE | \
40 NETIF_MSG_LINK | \
41 NETIF_MSG_RX_ERR | \
42 NETIF_MSG_TX_ERR | \
43 NETIF_MSG_HW)
44
3bf61c55 45#ifdef TX_DEBUG
c97b5740
GFT
46#define tx_dbg(priv, fmt, args...) \
47 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
3bf61c55 48#else
c97b5740
GFT
49#define tx_dbg(priv, fmt, args...) \
50do { \
51 if (0) \
52 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
53} while (0)
3bf61c55
GFT
54#endif
55
cd0ff491
GFT
56/*
57 * Extra PCI Configuration space interface
58 */
59#define PCI_DCSR_MRRS 0x59
60#define PCI_DCSR_MRRS_MASK 0x70
61
62enum pci_dcsr_mrrs_vals {
4330c2f2
GFT
63 MRRS_128B = 0x00,
64 MRRS_256B = 0x10,
65 MRRS_512B = 0x20,
66 MRRS_1024B = 0x30,
67 MRRS_2048B = 0x40,
68 MRRS_4096B = 0x50,
69};
d7699f87 70
cd0ff491
GFT
71#define PCI_SPI 0xB0
72
73enum pci_spi_bits {
74 SPI_EN = 0x10,
75 SPI_MISO = 0x08,
76 SPI_MOSI = 0x04,
77 SPI_SCLK = 0x02,
78 SPI_CS = 0x01,
79};
80
81struct jme_spi_op {
82 void __user *uwbuf;
83 void __user *urbuf;
84 __u8 wn; /* Number of write actions */
85 __u8 rn; /* Number of read actions */
86 __u8 bitn; /* Number of bits per action */
87 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
88 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
89
90 /* Internal use only */
91 u8 *kwbuf;
92 u8 *krbuf;
93 u8 sr;
94 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
95};
79ce639c 96
cd0ff491
GFT
97enum jme_spi_op_bits {
98 SPI_MODE_CPHA = 0x01,
99 SPI_MODE_CPOL = 0x02,
100 SPI_MODE_DUP = 0x80,
101};
102
103#define HALF_US 500 /* 500 ns */
104#define JMESPIIOCTL SIOCDEVPRIVATE
105
e4610a83
GFT
106#define PCI_PRIV_PE1 0xE4
107
108enum pci_priv_pe1_bit_masks {
109 PE1_ASPMSUPRT = 0x00000003, /*
110 * RW:
111 * Aspm_support[1:0]
112 * (R/W Port of 5C[11:10])
113 */
114 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
115 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
116 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
117 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
118 PE1_GPREG0 = 0x0000FF00, /*
119 * SRW:
120 * Cfg_gp_reg0
121 * [7:6] phy_giga BG control
122 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
123 * [4:0] Reserved
124 */
125 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
126 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
127 PE1_REVID = 0xFF000000, /* RO: Rev ID */
128};
129
130enum pci_priv_pe1_values {
131 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
132 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
133 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
134 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
135};
136
cd0ff491
GFT
137/*
138 * Dynamic(adaptive)/Static PCC values
139 */
3bf61c55 140enum dynamic_pcc_values {
192570e0 141 PCC_OFF = 0,
3bf61c55
GFT
142 PCC_P1 = 1,
143 PCC_P2 = 2,
144 PCC_P3 = 3,
145
192570e0 146 PCC_OFF_TO = 0,
3bf61c55 147 PCC_P1_TO = 1,
192570e0
GFT
148 PCC_P2_TO = 64,
149 PCC_P3_TO = 128,
3bf61c55 150
192570e0 151 PCC_OFF_CNT = 0,
3bf61c55 152 PCC_P1_CNT = 1,
192570e0
GFT
153 PCC_P2_CNT = 16,
154 PCC_P3_CNT = 32,
3bf61c55
GFT
155};
156struct dynpcc_info {
3bf61c55
GFT
157 unsigned long last_bytes;
158 unsigned long last_pkts;
79ce639c 159 unsigned long intr_cnt;
3bf61c55
GFT
160 unsigned char cur;
161 unsigned char attempt;
162 unsigned char cnt;
163};
79ce639c 164#define PCC_INTERVAL_US 100000
cd0ff491
GFT
165#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
166#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
79ce639c
GFT
167#define PCC_P2_THRESHOLD 800
168#define PCC_INTR_THRESHOLD 800
47220951 169#define PCC_TX_TO 1000
b3821cc5 170#define PCC_TX_CNT 8
3bf61c55 171
d7699f87
GFT
172/*
173 * TX/RX Descriptors
4330c2f2 174 *
cd0ff491 175 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
d7699f87 176 */
4330c2f2 177#define RING_DESC_ALIGN 16 /* Descriptor alignment */
d7699f87
GFT
178#define TX_DESC_SIZE 16
179#define TX_RING_NR 8
cd0ff491 180#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 181
3bf61c55 182struct txdesc {
d7699f87 183 union {
cd0ff491
GFT
184 __u8 all[16];
185 __le32 dw[4];
d7699f87
GFT
186 struct {
187 /* DW0 */
cd0ff491
GFT
188 __le16 vlan;
189 __u8 rsv1;
190 __u8 flags;
d7699f87
GFT
191
192 /* DW1 */
cd0ff491
GFT
193 __le16 datalen;
194 __le16 mss;
d7699f87
GFT
195
196 /* DW2 */
cd0ff491
GFT
197 __le16 pktsize;
198 __le16 rsv2;
d7699f87
GFT
199
200 /* DW3 */
cd0ff491 201 __le32 bufaddr;
d7699f87 202 } desc1;
3bf61c55
GFT
203 struct {
204 /* DW0 */
cd0ff491
GFT
205 __le16 rsv1;
206 __u8 rsv2;
207 __u8 flags;
3bf61c55
GFT
208
209 /* DW1 */
cd0ff491
GFT
210 __le16 datalen;
211 __le16 rsv3;
3bf61c55
GFT
212
213 /* DW2 */
cd0ff491 214 __le32 bufaddrh;
3bf61c55
GFT
215
216 /* DW3 */
cd0ff491 217 __le32 bufaddrl;
3bf61c55 218 } desc2;
8c198884
GFT
219 struct {
220 /* DW0 */
cd0ff491
GFT
221 __u8 ehdrsz;
222 __u8 rsv1;
223 __u8 rsv2;
224 __u8 flags;
8c198884
GFT
225
226 /* DW1 */
cd0ff491
GFT
227 __le16 trycnt;
228 __le16 segcnt;
8c198884
GFT
229
230 /* DW2 */
cd0ff491
GFT
231 __le16 pktsz;
232 __le16 rsv3;
8c198884
GFT
233
234 /* DW3 */
cd0ff491 235 __le32 bufaddrl;
8c198884 236 } descwb;
d7699f87
GFT
237 };
238};
cd0ff491 239
8c198884 240enum jme_txdesc_flags_bits {
d7699f87
GFT
241 TXFLAG_OWN = 0x80,
242 TXFLAG_INT = 0x40,
3bf61c55 243 TXFLAG_64BIT = 0x20,
d7699f87
GFT
244 TXFLAG_TCPCS = 0x10,
245 TXFLAG_UDPCS = 0x08,
246 TXFLAG_IPCS = 0x04,
247 TXFLAG_LSEN = 0x02,
248 TXFLAG_TAGON = 0x01,
249};
cd0ff491 250
b3821cc5 251#define TXDESC_MSS_SHIFT 2
fa97b924 252enum jme_txwbdesc_flags_bits {
8c198884
GFT
253 TXWBFLAG_OWN = 0x80,
254 TXWBFLAG_INT = 0x40,
255 TXWBFLAG_TMOUT = 0x20,
256 TXWBFLAG_TRYOUT = 0x10,
257 TXWBFLAG_COL = 0x08,
258
259 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
260 TXWBFLAG_TRYOUT |
261 TXWBFLAG_COL,
262};
d7699f87 263
d7699f87
GFT
264#define RX_DESC_SIZE 16
265#define RX_RING_NR 4
cd0ff491 266#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
d7699f87 267#define RX_BUF_DMA_ALIGN 8
3bf61c55 268#define RX_PREPAD_SIZE 10
79ce639c
GFT
269#define ETH_CRC_LEN 2
270#define RX_VLANHDR_LEN 2
271#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
272 ETH_HLEN + \
273 ETH_CRC_LEN + \
274 RX_VLANHDR_LEN + \
275 RX_BUF_DMA_ALIGN)
d7699f87 276
3bf61c55 277struct rxdesc {
d7699f87 278 union {
cd0ff491
GFT
279 __u8 all[16];
280 __le32 dw[4];
d7699f87
GFT
281 struct {
282 /* DW0 */
cd0ff491
GFT
283 __le16 rsv2;
284 __u8 rsv1;
285 __u8 flags;
d7699f87
GFT
286
287 /* DW1 */
cd0ff491
GFT
288 __le16 datalen;
289 __le16 wbcpl;
d7699f87
GFT
290
291 /* DW2 */
cd0ff491 292 __le32 bufaddrh;
d7699f87
GFT
293
294 /* DW3 */
cd0ff491 295 __le32 bufaddrl;
d7699f87
GFT
296 } desc1;
297 struct {
298 /* DW0 */
cd0ff491
GFT
299 __le16 vlan;
300 __le16 flags;
d7699f87
GFT
301
302 /* DW1 */
cd0ff491
GFT
303 __le16 framesize;
304 __u8 errstat;
305 __u8 desccnt;
d7699f87
GFT
306
307 /* DW2 */
cd0ff491 308 __le32 rsshash;
d7699f87
GFT
309
310 /* DW3 */
cd0ff491
GFT
311 __u8 hashfun;
312 __u8 hashtype;
313 __le16 resrv;
d7699f87
GFT
314 } descwb;
315 };
316};
cd0ff491 317
d7699f87
GFT
318enum jme_rxdesc_flags_bits {
319 RXFLAG_OWN = 0x80,
320 RXFLAG_INT = 0x40,
321 RXFLAG_64BIT = 0x20,
322};
cd0ff491 323
d7699f87 324enum jme_rxwbdesc_flags_bits {
4330c2f2
GFT
325 RXWBFLAG_OWN = 0x8000,
326 RXWBFLAG_INT = 0x4000,
327 RXWBFLAG_MF = 0x2000,
328 RXWBFLAG_64BIT = 0x2000,
329 RXWBFLAG_TCPON = 0x1000,
330 RXWBFLAG_UDPON = 0x0800,
331 RXWBFLAG_IPCS = 0x0400,
332 RXWBFLAG_TCPCS = 0x0200,
333 RXWBFLAG_UDPCS = 0x0100,
334 RXWBFLAG_TAGON = 0x0080,
335 RXWBFLAG_IPV4 = 0x0040,
336 RXWBFLAG_IPV6 = 0x0020,
337 RXWBFLAG_PAUSE = 0x0010,
338 RXWBFLAG_MAGIC = 0x0008,
339 RXWBFLAG_WAKEUP = 0x0004,
340 RXWBFLAG_DEST = 0x0003,
341 RXWBFLAG_DEST_UNI = 0x0001,
342 RXWBFLAG_DEST_MUL = 0x0002,
343 RXWBFLAG_DEST_BRO = 0x0003,
d7699f87 344};
cd0ff491 345
d7699f87
GFT
346enum jme_rxwbdesc_desccnt_mask {
347 RXWBDCNT_WBCPL = 0x80,
348 RXWBDCNT_DCNT = 0x7F,
349};
cd0ff491 350
4330c2f2
GFT
351enum jme_rxwbdesc_errstat_bits {
352 RXWBERR_LIMIT = 0x80,
353 RXWBERR_MIIER = 0x40,
354 RXWBERR_NIBON = 0x20,
355 RXWBERR_COLON = 0x10,
356 RXWBERR_ABORT = 0x08,
357 RXWBERR_SHORT = 0x04,
358 RXWBERR_OVERUN = 0x02,
359 RXWBERR_CRCERR = 0x01,
360 RXWBERR_ALLERR = 0xFF,
361};
362
cd0ff491
GFT
363/*
364 * Buffer information corresponding to ring descriptors.
365 */
4330c2f2
GFT
366struct jme_buffer_info {
367 struct sk_buff *skb;
368 dma_addr_t mapping;
369 int len;
3bf61c55 370 int nr_desc;
cdcdc9eb 371 unsigned long start_xmit;
4330c2f2 372};
d7699f87 373
cd0ff491
GFT
374/*
375 * The structure holding buffer information and ring descriptors all together.
376 */
d7699f87 377struct jme_ring {
cd0ff491
GFT
378 void *alloc; /* pointer to allocated memory */
379 void *desc; /* pointer to ring memory */
380 dma_addr_t dmaalloc; /* phys address of ring alloc */
381 dma_addr_t dma; /* phys address for ring dma */
d7699f87 382
4330c2f2 383 /* Buffer information corresponding to each descriptor */
fa97b924 384 struct jme_buffer_info *bufinf;
d7699f87 385
cd0ff491
GFT
386 int next_to_use;
387 atomic_t next_to_clean;
79ce639c 388 atomic_t nr_free;
d7699f87
GFT
389};
390
cd0ff491 391#define NET_STAT(priv) (priv->dev->stats)
3bf61c55
GFT
392#define NETDEV_GET_STATS(netdev, fun_ptr)
393#define DECLARE_NET_DEVICE_STATS
3bf61c55 394
cdcdc9eb
GFT
395#define DECLARE_NAPI_STRUCT struct napi_struct napi;
396#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
397 netif_napi_add(dev, napis, pollfn, q);
398#define JME_NAPI_HOLDER(holder) struct napi_struct *holder
399#define JME_NAPI_WEIGHT(w) int w
400#define JME_NAPI_WEIGHT_VAL(w) w
401#define JME_NAPI_WEIGHT_SET(w, r)
94c5ea02 402#define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
cdcdc9eb
GFT
403#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
404#define JME_NAPI_DISABLE(priv) \
cd0ff491 405 if (!napi_disable_pending(&priv->napi)) \
cdcdc9eb
GFT
406 napi_disable(&priv->napi);
407#define JME_RX_SCHEDULE_PREP(priv) \
94c5ea02 408 napi_schedule_prep(&priv->napi)
cdcdc9eb 409#define JME_RX_SCHEDULE(priv) \
94c5ea02 410 __napi_schedule(&priv->napi);
cdcdc9eb 411
d7699f87
GFT
412/*
413 * Jmac Adapter Private data
414 */
415struct jme_adapter {
cd0ff491
GFT
416 struct pci_dev *pdev;
417 struct net_device *dev;
418 void __iomem *regs;
d7699f87
GFT
419 struct mii_if_info mii_if;
420 struct jme_ring rxring[RX_RING_NR];
421 struct jme_ring txring[TX_RING_NR];
d7699f87 422 spinlock_t phy_lock;
fcf45b4c 423 spinlock_t macaddr_lock;
8c198884 424 spinlock_t rxmcs_lock;
fcf45b4c 425 struct tasklet_struct rxempty_task;
4330c2f2
GFT
426 struct tasklet_struct rxclean_task;
427 struct tasklet_struct txclean_task;
428 struct tasklet_struct linkch_task;
79ce639c 429 struct tasklet_struct pcc_task;
cd0ff491
GFT
430 unsigned long flags;
431 u32 reg_txcs;
432 u32 reg_txpfc;
433 u32 reg_rxcs;
434 u32 reg_rxmcs;
435 u32 reg_ghc;
436 u32 reg_pmcs;
ed830419 437 u32 reg_gpreg1;
cd0ff491
GFT
438 u32 phylink;
439 u32 tx_ring_size;
440 u32 tx_ring_mask;
441 u32 tx_wake_threshold;
442 u32 rx_ring_size;
443 u32 rx_ring_mask;
444 u8 mrrs;
445 unsigned int fpgaver;
4400ae98
GFT
446 u8 chiprev;
447 u8 chip_main_rev;
448 u8 chip_sub_rev;
449 u8 pcirev;
cd0ff491 450 u32 msg_enable;
29bdd921
GFT
451 struct ethtool_cmd old_ecmd;
452 unsigned int old_mtu;
cd0ff491 453 struct vlan_group *vlgrp;
3bf61c55
GFT
454 struct dynpcc_info dpi;
455 atomic_t intr_sem;
fcf45b4c
GFT
456 atomic_t link_changing;
457 atomic_t tx_cleaning;
458 atomic_t rx_cleaning;
192570e0 459 atomic_t rx_empty;
cdcdc9eb
GFT
460 int (*jme_rx)(struct sk_buff *skb);
461 int (*jme_vlan_rx)(struct sk_buff *skb,
462 struct vlan_group *grp,
463 unsigned short vlan_tag);
464 DECLARE_NAPI_STRUCT
3bf61c55 465 DECLARE_NET_DEVICE_STATS
d7699f87 466};
cd0ff491 467
79ce639c 468enum jme_flags_bits {
cd0ff491
GFT
469 JME_FLAG_MSI = 1,
470 JME_FLAG_SSET = 2,
471 JME_FLAG_TXCSUM = 3,
472 JME_FLAG_TSO = 4,
473 JME_FLAG_POLL = 5,
474 JME_FLAG_SHUTDOWN = 6,
8c198884 475};
cd0ff491
GFT
476
477#define TX_TIMEOUT (5 * HZ)
186fc259 478#define JME_REG_LEN 0x500
cd0ff491 479#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
8c198884 480
cd0ff491 481static inline struct jme_adapter*
cdcdc9eb
GFT
482jme_napi_priv(struct napi_struct *napi)
483{
cd0ff491 484 struct jme_adapter *jme;
cdcdc9eb
GFT
485 jme = container_of(napi, struct jme_adapter, napi);
486 return jme;
487}
d7699f87
GFT
488
489/*
490 * MMaped I/O Resters
491 */
492enum jme_iomap_offsets {
4330c2f2
GFT
493 JME_MAC = 0x0000,
494 JME_PHY = 0x0400,
d7699f87 495 JME_MISC = 0x0800,
4330c2f2 496 JME_RSS = 0x0C00,
d7699f87
GFT
497};
498
8c198884
GFT
499enum jme_iomap_lens {
500 JME_MAC_LEN = 0x80,
501 JME_PHY_LEN = 0x58,
502 JME_MISC_LEN = 0x98,
503 JME_RSS_LEN = 0xFF,
504};
505
d7699f87
GFT
506enum jme_iomap_regs {
507 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
3bf61c55
GFT
508 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
509 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
d7699f87
GFT
510 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
511 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
512 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
513 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
514 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
515
516 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
3bf61c55
GFT
517 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
518 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
d7699f87
GFT
519 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
520 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
521 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
4330c2f2
GFT
522 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
523 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
3bf61c55
GFT
524 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
525 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
d7699f87
GFT
526 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
527 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
528
529 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
530 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
531 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
532
533
e4610a83 534 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
3bf61c55 535 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
d7699f87
GFT
536 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
537 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
186fc259 538 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
d7699f87
GFT
539
540
cd0ff491
GFT
541 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
542 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
543 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
544 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
545 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
546 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
547 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
548 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
549 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
550 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
551 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
552 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
553 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
554 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
555 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
556 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
d7699f87
GFT
557};
558
559/*
560 * TX Control/Status Bits
561 */
562enum jme_txcs_bits {
563 TXCS_QUEUE7S = 0x00008000,
564 TXCS_QUEUE6S = 0x00004000,
565 TXCS_QUEUE5S = 0x00002000,
566 TXCS_QUEUE4S = 0x00001000,
567 TXCS_QUEUE3S = 0x00000800,
568 TXCS_QUEUE2S = 0x00000400,
569 TXCS_QUEUE1S = 0x00000200,
570 TXCS_QUEUE0S = 0x00000100,
571 TXCS_FIFOTH = 0x000000C0,
572 TXCS_DMASIZE = 0x00000030,
573 TXCS_BURST = 0x00000004,
574 TXCS_ENABLE = 0x00000001,
575};
cd0ff491 576
d7699f87
GFT
577enum jme_txcs_value {
578 TXCS_FIFOTH_16QW = 0x000000C0,
579 TXCS_FIFOTH_12QW = 0x00000080,
580 TXCS_FIFOTH_8QW = 0x00000040,
581 TXCS_FIFOTH_4QW = 0x00000000,
582
583 TXCS_DMASIZE_64B = 0x00000000,
584 TXCS_DMASIZE_128B = 0x00000010,
585 TXCS_DMASIZE_256B = 0x00000020,
586 TXCS_DMASIZE_512B = 0x00000030,
587
588 TXCS_SELECT_QUEUE0 = 0x00000000,
589 TXCS_SELECT_QUEUE1 = 0x00010000,
590 TXCS_SELECT_QUEUE2 = 0x00020000,
591 TXCS_SELECT_QUEUE3 = 0x00030000,
592 TXCS_SELECT_QUEUE4 = 0x00040000,
593 TXCS_SELECT_QUEUE5 = 0x00050000,
594 TXCS_SELECT_QUEUE6 = 0x00060000,
595 TXCS_SELECT_QUEUE7 = 0x00070000,
596
597 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
d7699f87
GFT
598 TXCS_BURST,
599};
cd0ff491 600
29bdd921 601#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
602
603/*
604 * TX MAC Control/Status Bits
605 */
606enum jme_txmcs_bit_masks {
607 TXMCS_IFG2 = 0xC0000000,
608 TXMCS_IFG1 = 0x30000000,
609 TXMCS_TTHOLD = 0x00000300,
610 TXMCS_FBURST = 0x00000080,
611 TXMCS_CARRIEREXT = 0x00000040,
612 TXMCS_DEFER = 0x00000020,
613 TXMCS_BACKOFF = 0x00000010,
614 TXMCS_CARRIERSENSE = 0x00000008,
615 TXMCS_COLLISION = 0x00000004,
616 TXMCS_CRC = 0x00000002,
617 TXMCS_PADDING = 0x00000001,
618};
cd0ff491 619
d7699f87
GFT
620enum jme_txmcs_values {
621 TXMCS_IFG2_6_4 = 0x00000000,
622 TXMCS_IFG2_8_5 = 0x40000000,
623 TXMCS_IFG2_10_6 = 0x80000000,
624 TXMCS_IFG2_12_7 = 0xC0000000,
625
626 TXMCS_IFG1_8_4 = 0x00000000,
627 TXMCS_IFG1_12_6 = 0x10000000,
628 TXMCS_IFG1_16_8 = 0x20000000,
629 TXMCS_IFG1_20_10 = 0x30000000,
630
631 TXMCS_TTHOLD_1_8 = 0x00000000,
632 TXMCS_TTHOLD_1_4 = 0x00000100,
633 TXMCS_TTHOLD_1_2 = 0x00000200,
634 TXMCS_TTHOLD_FULL = 0x00000300,
635
636 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
637 TXMCS_IFG1_16_8 |
638 TXMCS_TTHOLD_FULL |
639 TXMCS_DEFER |
640 TXMCS_CRC |
641 TXMCS_PADDING,
642};
643
8c198884
GFT
644enum jme_txpfc_bits_masks {
645 TXPFC_VLAN_TAG = 0xFFFF0000,
646 TXPFC_VLAN_EN = 0x00008000,
647 TXPFC_PF_EN = 0x00000001,
648};
649
650enum jme_txtrhd_bits_masks {
651 TXTRHD_TXPEN = 0x80000000,
652 TXTRHD_TXP = 0x7FFFFF00,
653 TXTRHD_TXREN = 0x00000080,
654 TXTRHD_TXRL = 0x0000007F,
655};
cd0ff491 656
8c198884
GFT
657enum jme_txtrhd_shifts {
658 TXTRHD_TXP_SHIFT = 8,
659 TXTRHD_TXRL_SHIFT = 0,
660};
661
19bbc546
GFT
662enum jme_txtrhd_values {
663 TXTRHD_FULLDUPLEX = 0x00000000,
664 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
665 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
666 TXTRHD_TXREN |
667 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
668};
669
d7699f87
GFT
670/*
671 * RX Control/Status Bits
672 */
4330c2f2 673enum jme_rxcs_bit_masks {
3bf61c55
GFT
674 /* FIFO full threshold for transmitting Tx Pause Packet */
675 RXCS_FIFOTHTP = 0x30000000,
676 /* FIFO threshold for processing next packet */
677 RXCS_FIFOTHNP = 0x0C000000,
4330c2f2
GFT
678 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
679 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
680 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
681 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
682 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
683 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
684 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
685 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
686 RXCS_QST = 0x00000004, /* Receive queue start */
687 RXCS_SUSPEND = 0x00000002,
d7699f87
GFT
688 RXCS_ENABLE = 0x00000001,
689};
cd0ff491 690
4330c2f2
GFT
691enum jme_rxcs_values {
692 RXCS_FIFOTHTP_16T = 0x00000000,
693 RXCS_FIFOTHTP_32T = 0x10000000,
694 RXCS_FIFOTHTP_64T = 0x20000000,
695 RXCS_FIFOTHTP_128T = 0x30000000,
696
697 RXCS_FIFOTHNP_16QW = 0x00000000,
698 RXCS_FIFOTHNP_32QW = 0x04000000,
699 RXCS_FIFOTHNP_64QW = 0x08000000,
700 RXCS_FIFOTHNP_128QW = 0x0C000000,
701
702 RXCS_DMAREQSZ_16B = 0x00000000,
703 RXCS_DMAREQSZ_32B = 0x01000000,
704 RXCS_DMAREQSZ_64B = 0x02000000,
705 RXCS_DMAREQSZ_128B = 0x03000000,
706
707 RXCS_QUEUESEL_Q0 = 0x00000000,
708 RXCS_QUEUESEL_Q1 = 0x00010000,
709 RXCS_QUEUESEL_Q2 = 0x00020000,
710 RXCS_QUEUESEL_Q3 = 0x00030000,
711
712 RXCS_RETRYGAP_256ns = 0x00000000,
713 RXCS_RETRYGAP_512ns = 0x00001000,
714 RXCS_RETRYGAP_1024ns = 0x00002000,
715 RXCS_RETRYGAP_2048ns = 0x00003000,
716 RXCS_RETRYGAP_4096ns = 0x00004000,
717 RXCS_RETRYGAP_8192ns = 0x00005000,
718 RXCS_RETRYGAP_16384ns = 0x00006000,
719 RXCS_RETRYGAP_32768ns = 0x00007000,
720
721 RXCS_RETRYCNT_0 = 0x00000000,
722 RXCS_RETRYCNT_4 = 0x00000100,
723 RXCS_RETRYCNT_8 = 0x00000200,
724 RXCS_RETRYCNT_12 = 0x00000300,
725 RXCS_RETRYCNT_16 = 0x00000400,
726 RXCS_RETRYCNT_20 = 0x00000500,
727 RXCS_RETRYCNT_24 = 0x00000600,
728 RXCS_RETRYCNT_28 = 0x00000700,
729 RXCS_RETRYCNT_32 = 0x00000800,
730 RXCS_RETRYCNT_36 = 0x00000900,
731 RXCS_RETRYCNT_40 = 0x00000A00,
732 RXCS_RETRYCNT_44 = 0x00000B00,
733 RXCS_RETRYCNT_48 = 0x00000C00,
734 RXCS_RETRYCNT_52 = 0x00000D00,
735 RXCS_RETRYCNT_56 = 0x00000E00,
736 RXCS_RETRYCNT_60 = 0x00000F00,
737
738 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
79ce639c 739 RXCS_FIFOTHNP_128QW |
4330c2f2
GFT
740 RXCS_DMAREQSZ_128B |
741 RXCS_RETRYGAP_256ns |
742 RXCS_RETRYCNT_32,
743};
cd0ff491 744
29bdd921 745#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
d7699f87
GFT
746
747/*
748 * RX MAC Control/Status Bits
749 */
750enum jme_rxmcs_bits {
751 RXMCS_ALLFRAME = 0x00000800,
752 RXMCS_BRDFRAME = 0x00000400,
753 RXMCS_MULFRAME = 0x00000200,
754 RXMCS_UNIFRAME = 0x00000100,
755 RXMCS_ALLMULFRAME = 0x00000080,
756 RXMCS_MULFILTERED = 0x00000040,
3bf61c55
GFT
757 RXMCS_RXCOLLDEC = 0x00000020,
758 RXMCS_FLOWCTRL = 0x00000008,
759 RXMCS_VTAGRM = 0x00000004,
760 RXMCS_PREPAD = 0x00000002,
761 RXMCS_CHECKSUM = 0x00000001,
b3821cc5 762
8c198884
GFT
763 RXMCS_DEFAULT = RXMCS_VTAGRM |
764 RXMCS_PREPAD |
765 RXMCS_FLOWCTRL |
766 RXMCS_CHECKSUM,
d7699f87
GFT
767};
768
769/*
b3821cc5
GFT
770 * Wakeup Frame setup interface registers
771 */
772#define WAKEUP_FRAME_NR 8
773#define WAKEUP_FRAME_MASK_DWNR 4
cd0ff491 774
b3821cc5
GFT
775enum jme_wfoi_bit_masks {
776 WFOI_MASK_SEL = 0x00000070,
777 WFOI_CRC_SEL = 0x00000008,
778 WFOI_FRAME_SEL = 0x00000007,
779};
cd0ff491 780
b3821cc5
GFT
781enum jme_wfoi_shifts {
782 WFOI_MASK_SHIFT = 4,
783};
784
785/*
d7699f87
GFT
786 * SMI Related definitions
787 */
cd0ff491 788enum jme_smi_bit_mask {
d7699f87
GFT
789 SMI_DATA_MASK = 0xFFFF0000,
790 SMI_REG_ADDR_MASK = 0x0000F800,
791 SMI_PHY_ADDR_MASK = 0x000007C0,
792 SMI_OP_WRITE = 0x00000020,
3bf61c55
GFT
793 /* Set to 1, after req done it'll be cleared to 0 */
794 SMI_OP_REQ = 0x00000010,
d7699f87
GFT
795 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
796 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
797 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
798 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
799};
cd0ff491
GFT
800
801enum jme_smi_bit_shift {
d7699f87
GFT
802 SMI_DATA_SHIFT = 16,
803 SMI_REG_ADDR_SHIFT = 11,
804 SMI_PHY_ADDR_SHIFT = 6,
805};
cd0ff491
GFT
806
807static inline u32 smi_reg_addr(int x)
d7699f87 808{
cd0ff491 809 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
d7699f87 810}
cd0ff491
GFT
811
812static inline u32 smi_phy_addr(int x)
d7699f87 813{
cd0ff491 814 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
d7699f87 815}
cd0ff491 816
8d27293f 817#define JME_PHY_TIMEOUT 100 /* 100 msec */
186fc259 818#define JME_PHY_REG_NR 32
d7699f87
GFT
819
820/*
821 * Global Host Control
822 */
823enum jme_ghc_bit_mask {
94c5ea02 824 GHC_SWRST = 0x40000000,
ed830419
GFT
825 GHC_TO_CLK_SRC = 0x00C00000,
826 GHC_TXMAC_CLK_SRC = 0x00300000,
94c5ea02
GFT
827 GHC_DPX = 0x00000040,
828 GHC_SPEED = 0x00000030,
829 GHC_LINK_POLL = 0x00000001,
d7699f87 830};
cd0ff491 831
d7699f87 832enum jme_ghc_speed_val {
94c5ea02
GFT
833 GHC_SPEED_10M = 0x00000010,
834 GHC_SPEED_100M = 0x00000020,
835 GHC_SPEED_1000M = 0x00000030,
836};
837
838enum jme_ghc_to_clk {
839 GHC_TO_CLK_OFF = 0x00000000,
840 GHC_TO_CLK_GPHY = 0x00400000,
841 GHC_TO_CLK_PCIE = 0x00800000,
842 GHC_TO_CLK_INVALID = 0x00C00000,
843};
844
845enum jme_ghc_txmac_clk {
846 GHC_TXMAC_CLK_OFF = 0x00000000,
847 GHC_TXMAC_CLK_GPHY = 0x00100000,
848 GHC_TXMAC_CLK_PCIE = 0x00200000,
849 GHC_TXMAC_CLK_INVALID = 0x00300000,
d7699f87
GFT
850};
851
852/*
29bdd921
GFT
853 * Power management control and status register
854 */
855enum jme_pmcs_bit_masks {
856 PMCS_WF7DET = 0x80000000,
857 PMCS_WF6DET = 0x40000000,
858 PMCS_WF5DET = 0x20000000,
859 PMCS_WF4DET = 0x10000000,
860 PMCS_WF3DET = 0x08000000,
861 PMCS_WF2DET = 0x04000000,
862 PMCS_WF1DET = 0x02000000,
863 PMCS_WF0DET = 0x01000000,
864 PMCS_LFDET = 0x00040000,
865 PMCS_LRDET = 0x00020000,
866 PMCS_MFDET = 0x00010000,
867 PMCS_WF7EN = 0x00008000,
868 PMCS_WF6EN = 0x00004000,
869 PMCS_WF5EN = 0x00002000,
870 PMCS_WF4EN = 0x00001000,
871 PMCS_WF3EN = 0x00000800,
872 PMCS_WF2EN = 0x00000400,
873 PMCS_WF1EN = 0x00000200,
874 PMCS_WF0EN = 0x00000100,
875 PMCS_LFEN = 0x00000004,
876 PMCS_LREN = 0x00000002,
877 PMCS_MFEN = 0x00000001,
878};
879
880/*
e4610a83
GFT
881 * New PHY Power Control Register
882 */
883enum jme_phy_pwr_bit_masks {
884 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
885 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
886 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
887 PHY_PWR_CLKSEL = 0x08000000, /*
888 * XTL_OUT Clock select
889 * (an internal free-running clock)
890 * 0: xtl_out = phy_giga.A_XTL25_O
891 * 1: xtl_out = phy_giga.PD_OSC
892 */
893};
894
895/*
3bf61c55 896 * Giga PHY Status Registers
d7699f87
GFT
897 */
898enum jme_phy_link_bit_mask {
899 PHY_LINK_SPEED_MASK = 0x0000C000,
900 PHY_LINK_DUPLEX = 0x00002000,
901 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
902 PHY_LINK_UP = 0x00000400,
903 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
fcf45b4c 904 PHY_LINK_MDI_STAT = 0x00000040,
d7699f87 905};
cd0ff491 906
d7699f87
GFT
907enum jme_phy_link_speed_val {
908 PHY_LINK_SPEED_10M = 0x00000000,
909 PHY_LINK_SPEED_100M = 0x00004000,
910 PHY_LINK_SPEED_1000M = 0x00008000,
911};
cd0ff491 912
fcf45b4c 913#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
d7699f87
GFT
914
915/*
916 * SMB Control and Status
917 */
79ce639c 918enum jme_smbcsr_bit_mask {
d7699f87
GFT
919 SMBCSR_CNACK = 0x00020000,
920 SMBCSR_RELOAD = 0x00010000,
921 SMBCSR_EEPROMD = 0x00000020,
186fc259
GFT
922 SMBCSR_INITDONE = 0x00000010,
923 SMBCSR_BUSY = 0x0000000F,
924};
cd0ff491 925
186fc259
GFT
926enum jme_smbintf_bit_mask {
927 SMBINTF_HWDATR = 0xFF000000,
928 SMBINTF_HWDATW = 0x00FF0000,
929 SMBINTF_HWADDR = 0x0000FF00,
930 SMBINTF_HWRWN = 0x00000020,
931 SMBINTF_HWCMD = 0x00000010,
932 SMBINTF_FASTM = 0x00000008,
933 SMBINTF_GPIOSCL = 0x00000004,
934 SMBINTF_GPIOSDA = 0x00000002,
935 SMBINTF_GPIOEN = 0x00000001,
936};
cd0ff491 937
186fc259
GFT
938enum jme_smbintf_vals {
939 SMBINTF_HWRWN_READ = 0x00000020,
940 SMBINTF_HWRWN_WRITE = 0x00000000,
941};
cd0ff491 942
186fc259
GFT
943enum jme_smbintf_shifts {
944 SMBINTF_HWDATR_SHIFT = 24,
945 SMBINTF_HWDATW_SHIFT = 16,
946 SMBINTF_HWADDR_SHIFT = 8,
947};
cd0ff491 948
186fc259
GFT
949#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
950#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
951#define JME_SMB_LEN 256
952#define JME_EEPROM_MAGIC 0x250
d7699f87 953
79ce639c
GFT
954/*
955 * Timer Control/Status Register
956 */
957enum jme_tmcsr_bit_masks {
958 TMCSR_SWIT = 0x80000000,
959 TMCSR_EN = 0x01000000,
960 TMCSR_CNT = 0x00FFFFFF,
961};
962
d7699f87 963/*
cd0ff491 964 * General Purpose REG-0
4330c2f2
GFT
965 */
966enum jme_gpreg0_masks {
3bf61c55
GFT
967 GPREG0_DISSH = 0xFF000000,
968 GPREG0_PCIRLMT = 0x00300000,
969 GPREG0_PCCNOMUTCLR = 0x00040000,
cdcdc9eb 970 GPREG0_LNKINTPOLL = 0x00001000,
3bf61c55
GFT
971 GPREG0_PCCTMR = 0x00000300,
972 GPREG0_PHYADDR = 0x0000001F,
4330c2f2 973};
cd0ff491 974
4330c2f2
GFT
975enum jme_gpreg0_vals {
976 GPREG0_DISSH_DW7 = 0x80000000,
977 GPREG0_DISSH_DW6 = 0x40000000,
978 GPREG0_DISSH_DW5 = 0x20000000,
979 GPREG0_DISSH_DW4 = 0x10000000,
980 GPREG0_DISSH_DW3 = 0x08000000,
981 GPREG0_DISSH_DW2 = 0x04000000,
982 GPREG0_DISSH_DW1 = 0x02000000,
983 GPREG0_DISSH_DW0 = 0x01000000,
984 GPREG0_DISSH_ALL = 0xFF000000,
985
986 GPREG0_PCIRLMT_8 = 0x00000000,
987 GPREG0_PCIRLMT_6 = 0x00100000,
988 GPREG0_PCIRLMT_5 = 0x00200000,
989 GPREG0_PCIRLMT_4 = 0x00300000,
990
991 GPREG0_PCCTMR_16ns = 0x00000000,
3bf61c55
GFT
992 GPREG0_PCCTMR_256ns = 0x00000100,
993 GPREG0_PCCTMR_1us = 0x00000200,
994 GPREG0_PCCTMR_1ms = 0x00000300,
4330c2f2
GFT
995
996 GPREG0_PHYADDR_1 = 0x00000001,
997
998 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
3bf61c55
GFT
999 GPREG0_PCCTMR_1us |
1000 GPREG0_PHYADDR_1,
4330c2f2
GFT
1001};
1002
1003/*
9b9d55de 1004 * General Purpose REG-1
9b9d55de 1005 */
ed830419
GFT
1006enum jme_gpreg1_bit_masks {
1007 GPREG1_RXCLKOFF = 0x04000000,
1008 GPREG1_PCREQN = 0x00020000,
1009 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1010 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
9b9d55de
GFT
1011 GPREG1_INTRDELAYUNIT = 0x00000018,
1012 GPREG1_INTRDELAYENABLE = 0x00000007,
1013};
1014
1015enum jme_gpreg1_vals {
9b9d55de
GFT
1016 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1017 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1018 GPREG1_INTDLYUNIT_1US = 0x00000010,
1019 GPREG1_INTDLYUNIT_16US = 0x00000018,
1020
1021 GPREG1_INTDLYEN_1U = 0x00000001,
1022 GPREG1_INTDLYEN_2U = 0x00000002,
1023 GPREG1_INTDLYEN_3U = 0x00000003,
1024 GPREG1_INTDLYEN_4U = 0x00000004,
1025 GPREG1_INTDLYEN_5U = 0x00000005,
1026 GPREG1_INTDLYEN_6U = 0x00000006,
1027 GPREG1_INTDLYEN_7U = 0x00000007,
1028
ed830419 1029 GPREG1_DEFAULT = GPREG1_PCREQN,
9b9d55de
GFT
1030};
1031
1032/*
d7699f87
GFT
1033 * Interrupt Status Bits
1034 */
cd0ff491 1035enum jme_interrupt_bits {
d7699f87
GFT
1036 INTR_SWINTR = 0x80000000,
1037 INTR_TMINTR = 0x40000000,
1038 INTR_LINKCH = 0x20000000,
1039 INTR_PAUSERCV = 0x10000000,
1040 INTR_MAGICRCV = 0x08000000,
1041 INTR_WAKERCV = 0x04000000,
1042 INTR_PCCRX0TO = 0x02000000,
1043 INTR_PCCRX1TO = 0x01000000,
1044 INTR_PCCRX2TO = 0x00800000,
1045 INTR_PCCRX3TO = 0x00400000,
1046 INTR_PCCTXTO = 0x00200000,
1047 INTR_PCCRX0 = 0x00100000,
1048 INTR_PCCRX1 = 0x00080000,
1049 INTR_PCCRX2 = 0x00040000,
1050 INTR_PCCRX3 = 0x00020000,
1051 INTR_PCCTX = 0x00010000,
1052 INTR_RX3EMP = 0x00008000,
1053 INTR_RX2EMP = 0x00004000,
1054 INTR_RX1EMP = 0x00002000,
1055 INTR_RX0EMP = 0x00001000,
1056 INTR_RX3 = 0x00000800,
1057 INTR_RX2 = 0x00000400,
1058 INTR_RX1 = 0x00000200,
1059 INTR_RX0 = 0x00000100,
1060 INTR_TX7 = 0x00000080,
1061 INTR_TX6 = 0x00000040,
1062 INTR_TX5 = 0x00000020,
1063 INTR_TX4 = 0x00000010,
1064 INTR_TX3 = 0x00000008,
1065 INTR_TX2 = 0x00000004,
1066 INTR_TX1 = 0x00000002,
1067 INTR_TX0 = 0x00000001,
1068};
cd0ff491
GFT
1069
1070static const u32 INTR_ENABLE = INTR_SWINTR |
79ce639c
GFT
1071 INTR_TMINTR |
1072 INTR_LINKCH |
3bf61c55
GFT
1073 INTR_PCCRX0TO |
1074 INTR_PCCRX0 |
1075 INTR_PCCTXTO |
cdcdc9eb
GFT
1076 INTR_PCCTX |
1077 INTR_RX0EMP;
3bf61c55
GFT
1078
1079/*
1080 * PCC Control Registers
1081 */
1082enum jme_pccrx_masks {
1083 PCCRXTO_MASK = 0xFFFF0000,
1084 PCCRX_MASK = 0x0000FF00,
1085};
cd0ff491 1086
3bf61c55
GFT
1087enum jme_pcctx_masks {
1088 PCCTXTO_MASK = 0xFFFF0000,
1089 PCCTX_MASK = 0x0000FF00,
1090 PCCTX_QS_MASK = 0x000000FF,
1091};
cd0ff491 1092
3bf61c55
GFT
1093enum jme_pccrx_shifts {
1094 PCCRXTO_SHIFT = 16,
1095 PCCRX_SHIFT = 8,
1096};
cd0ff491 1097
3bf61c55
GFT
1098enum jme_pcctx_shifts {
1099 PCCTXTO_SHIFT = 16,
1100 PCCTX_SHIFT = 8,
1101};
cd0ff491 1102
3bf61c55
GFT
1103enum jme_pcctx_bits {
1104 PCCTXQ0_EN = 0x00000001,
1105 PCCTXQ1_EN = 0x00000002,
1106 PCCTXQ2_EN = 0x00000004,
1107 PCCTXQ3_EN = 0x00000008,
1108 PCCTXQ4_EN = 0x00000010,
1109 PCCTXQ5_EN = 0x00000020,
1110 PCCTXQ6_EN = 0x00000040,
1111 PCCTXQ7_EN = 0x00000080,
1112};
1113
cdcdc9eb
GFT
1114/*
1115 * Chip Mode Register
1116 */
1117enum jme_chipmode_bit_masks {
1118 CM_FPGAVER_MASK = 0xFFFF0000,
e882564f 1119 CM_CHIPREV_MASK = 0x0000FF00,
cdcdc9eb
GFT
1120 CM_CHIPMODE_MASK = 0x0000000F,
1121};
cd0ff491 1122
cdcdc9eb
GFT
1123enum jme_chipmode_shifts {
1124 CM_FPGAVER_SHIFT = 16,
e882564f 1125 CM_CHIPREV_SHIFT = 8,
cdcdc9eb 1126};
d7699f87
GFT
1127
1128/*
cd0ff491
GFT
1129 * Aggressive Power Mode Control
1130 */
1131enum jme_apmc_bits {
1132 JME_APMC_PCIE_SD_EN = 0x40000000,
1133 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1134 JME_APMC_EPIEN = 0x04000000,
1135 JME_APMC_EPIEN_CTRL = 0x03000000,
1136};
1137
1138enum jme_apmc_values {
1139 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1140 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1141};
1142
1143#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1144
1145#ifdef REG_DEBUG
1146static char *MAC_REG_NAME[] = {
1147 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1148 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1149 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1150 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1151 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1152 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1153 "JME_PMCS"};
9b9d55de 1154
cd0ff491
GFT
1155static char *PE_REG_NAME[] = {
1156 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1157 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1158 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1159 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1160 "JME_SMBCSR", "JME_SMBINTF"};
9b9d55de 1161
cd0ff491
GFT
1162static char *MISC_REG_NAME[] = {
1163 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1164 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1165 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1166 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1167 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1168 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1169 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1170 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1171 "JME_PCCSRX0"};
9b9d55de 1172
cd0ff491
GFT
1173static inline void reg_dbg(const struct jme_adapter *jme,
1174 const char *msg, u32 val, u32 reg)
1175{
1176 const char *regname;
e882564f 1177 switch (reg & 0xF00) {
cd0ff491
GFT
1178 case 0x000:
1179 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1180 break;
1181 case 0x400:
1182 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1183 break;
1184 case 0x800:
e882564f 1185 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
cd0ff491
GFT
1186 break;
1187 default:
1188 regname = PE_REG_NAME[0];
1189 }
1190 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1191 msg, val, regname);
1192}
1193#else
1194static inline void reg_dbg(const struct jme_adapter *jme,
1195 const char *msg, u32 val, u32 reg) {}
1196#endif
1197
1198/*
d7699f87
GFT
1199 * Read/Write MMaped I/O Registers
1200 */
cd0ff491 1201static inline u32 jread32(struct jme_adapter *jme, u32 reg)
d7699f87 1202{
cd0ff491 1203 return readl(jme->regs + reg);
d7699f87 1204}
cd0ff491
GFT
1205
1206static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
d7699f87 1207{
cd0ff491
GFT
1208 reg_dbg(jme, "REG WRITE", val, reg);
1209 writel(val, jme->regs + reg);
1210 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
d7699f87 1211}
cd0ff491
GFT
1212
1213static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
d7699f87
GFT
1214{
1215 /*
1216 * Read after write should cause flush
1217 */
cd0ff491
GFT
1218 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1219 writel(val, jme->regs + reg);
1220 readl(jme->regs + reg);
1221 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
d7699f87
GFT
1222}
1223
1224/*
cdcdc9eb
GFT
1225 * PHY Regs
1226 */
1227enum jme_phy_reg17_bit_masks {
1228 PREG17_SPEED = 0xC000,
1229 PREG17_DUPLEX = 0x2000,
1230 PREG17_SPDRSV = 0x0800,
1231 PREG17_LNKUP = 0x0400,
1232 PREG17_MDI = 0x0040,
1233};
cd0ff491 1234
cdcdc9eb
GFT
1235enum jme_phy_reg17_vals {
1236 PREG17_SPEED_10M = 0x0000,
1237 PREG17_SPEED_100M = 0x4000,
1238 PREG17_SPEED_1000M = 0x8000,
1239};
cd0ff491 1240
8d27293f 1241#define BMSR_ANCOMP 0x0020
cdcdc9eb
GFT
1242
1243/*
e882564f
GFT
1244 * Workaround
1245 */
4400ae98 1246static inline int is_buggy250(unsigned short device, u8 chiprev)
e882564f
GFT
1247{
1248 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1249}
1250
e4610a83
GFT
1251static inline int new_phy_power_ctrl(u8 chip_main_rev)
1252{
1253 return chip_main_rev >= 5;
1254}
1255
e882564f 1256/*
cd0ff491 1257 * Function prototypes
d7699f87 1258 */
d7699f87 1259static int jme_set_settings(struct net_device *netdev,
cd0ff491 1260 struct ethtool_cmd *ecmd);
bb4c5c8c 1261static void jme_set_unicastaddr(struct net_device *netdev);
d7699f87
GFT
1262static void jme_set_multi(struct net_device *netdev);
1263
cd0ff491 1264#endif